S-8261 Series
www.sii-ic.com BATTERY PROTECTION IC FOR 1-CELL PACK
© Seiko Instruments Inc., 2001-2012 Rev.5.2_00
Seiko Instruments Inc. 1
The S-8261 Series is a lithium-ion / lithium polymer rechargeable battery protection IC incorporating high-accuracy voltage
detection circuit and delay circuit.
The S-8261 Series is suitable for protection of single-cell lithium-ion / lithium polymer battery packs from overcharge,
overdischarge and overcurrent.
Features
(1) Internal high accuracy voltage detection circuit
• Overcharge detection voltage 3.9 V to 4.4 V (applicable in 5 mV step) Accuracy: ±25 mV (+25°C) and
±30 mV (−5°C to +55°C)
• Overcharge hysteresis voltage 0.1 V to 0.4 V*1 Accuracy: ±25 mV
The overcharge hysteresis voltage can be selected from the range 0.1 V to 0.4 V in 50 mV step.
• Overdischarge detection voltage 2.0 V to 3.0 V (applicable in 10 mV step) Accuracy: ±50 mV
• Overdischarge hysteresis voltage 0.0 V to 0.7 V*2 Accuracy: ±50 mV
The overdischarge hysteresis voltage can be selected from the range 0.0 V to 0.7 V in 100 mV step.
• Overcurrent 1 detection voltage 0.05 V to 0.3 V (applicable in 10 mV step) Accuracy: ±15 mV
• Overcurrent 2 detection voltage 0.5 V (fixed) Accuracy: ±100 mV
(2) High voltage device is used for charger connection pins (VM and CO pins: absolute maximum rating = 28 V).
(3) Delay times (overcharge: tCU, overdischarge: tDL, overcurrent 1: tlOV1, overcurrent 2: tlOV2) are generated by an
internal circuit. No external capacitor is necessary. Accuracy: ±20%
(4) Three-step overcurrent detection circuit is included (overcurrent 1, overcurrent 2 and load short-circuiting).
(5) 0 V battery charge function “Available” / “Unavailable” is selectable.
(6) Power-down function “Yes” / “No” is selectable.
(7) Charger detection function and abnormal charge current detection function
•
The overdischarge hysteresis is released by detecting negative voltage at the VM pin (−0.7 V typ.) (Charger
detection function).
•
When the output voltage of the DO pin is high and the voltage at the VM pin is equal to or lower than the charger
detection voltage (−0.7 V typ.), the output voltage of the CO pin goes low (Abnormal charge current detection
function).
(8) Low current consumption
• Operation mode 3.5 μA typ., 7.0 μA max.
• Power-down mode 0.1 μA max.
(9) Wide operating temperature range −40°C to +85°C
(10) Lead-free, Sn 100%, halogen-free*3
*1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (where overcharge
release voltage < 3.8 V is prohibited.)
*2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage (where
overdischarge release voltage > 3.4 V is prohibited.)
*3. Refer to “ Product Name Structure” for details.
Applications
• Lithium-ion rechargeable battery packs
• Lithium polymer rechargeable battery packs
Package
• SOT-23-6
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
2
Block Diagram
－
＋
－
＋
VM
VSS
VDD
CO
DO
Overcharge
detection
comparator
Overcurrent 1
detection comparator
－
＋
－
＋
Load short-circuiting detection comparator
Output control circuit
－
＋
Overcurrent 2
detection comparator
R
VMD
R
VMS
Charger detection circuit
0 V battery charge circuit
or 0 V battery charge
inhibition circuit
Divider control
circuit
Oscillator control
circuit
Overdischarge
detection
comparator
DP
Remark All the diodes shown in the figure are parasitic diodes.
Figure 1
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 3
Product Name Structure
1. Product Name
S-8261A xx MD - xxx T2 x
Environmental code
U: Lead-free (Sn 100%), halogen-free
S: Lead-free, halogen-free
G: Lead-free (for details, please contact our sales office)
IC direction in tape specifications*1
Product name (abbreviation)*2
Package name (abbreviation)
MD: SOT-23-6
Serial code
Assigned from AA to ZZ in alphabetical order
*1. Refer to the tape drawing.
*2. Refer to the “3. Product Name List”.
2. Package
Drawing code
Package name Package Tape Reel
SOT-23-6 MP006-A-P-SD MP006-A-C-SD MP006-A-R-SD
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
4
3. Product Name List
Table 1 (1 / 2)
Product name
Overcharge
detection
voltage
[V
CU
]
Overcharge
hysteresis
voltage
[V
HC
]
Overdischarge
detection
voltage
[V
DL
]
Overdischarge
hysteresis
voltage
[V
HD
]
Overcurrent 1
detection
voltage
[V
IOV1
]
0 V battery
charge
function
Delay
time
combi-
nation
*1
Power down
function
S-8261AAGMD-G2GT2x 4.280 V 0.20 V 2.30 V 0 V 0.16 V Available (1) Yes
S-8261AAHMD-G2HT2x 4.280 V 0.20 V 2.30 V 0 V 0.08 V Available (1) Yes
S-8261AAJMD-G2JT2x 4.325 V 0.25 V 2.50 V 0.4 V 0.15 V Unavailable (1) Yes
S-8261AALMD-G2LT2x 4.300 V 0.10 V 2.30 V 0 V 0.08 V Unavailable (1) Yes
S-8261AAMMD-G2MT2x 4.300 V 0.10 V 2.30 V 0 V 0.20 V Unavailable (1) Yes
S-8261AANMD-G2NT2x 4.275 V 0.10 V 2.30 V 0.1 V 0.10 V Available (1) Yes
S-8261AAOMD-G2OT2x 4.280 V 0.20 V 2.30 V 0 V 0.13 V Unavailable (1) Yes
S-8261AAPMD-G2PT2x 4.325 V 0.25 V 2.50 V 0.4 V 0.10 V Unavailable (1) Yes
S-8261AARMD-G2RT2x 4.280 V 0.20 V 2.30 V 0 V 0.10 V Available (1) Yes
S-8261AASMD-G2ST2x 4.280 V 0.20 V 2.30 V 0 V 0.15 V Unavailable (2) Yes
S-8261AATMD-G2TT2x 4.300 V 0.10 V 2.30 V 0 V 0.08 V Available (3) Yes
S-8261AAUMD-G2UT2x 4.275 V 0.10 V 2.30 V 0.1 V 0.10 V Available (4) Yes
S-8261AAXMD-G2XT2x 4.350 V 0.10 V 2.30 V 0.1 V 0.10 V Available (4) Yes
S-8261AAZMD-G2ZT2x 4.280 V 0.25 V 2.50 V 0.4 V 0.10 V Unavailable (1) Yes
S-8261ABAMD-G3AT2x 4.350 V 0.20 V 2.50 V 0 V 0.20 V Available (4) Yes
S-8261ABBMD-G3BT2x 4.275 V 0.20 V 2.30 V 0 V 0.13 V Available (1) Yes
S-8261ABCMD-G3CT2x 4.300 V 0.20 V 2.30 V 0 V 0.13 V Available (1) Yes
S-8261ABIMD-G3IT2x 4.275 V 0.20 V 2.30 V 0 V 0.20 V Unavailable (5) Yes
S-8261ABJMD-G3JT2x 4.280 V 0.20 V 3.00 V 0 V 0.08 V Available (1) Yes
S-8261ABKMD-G3KT2x 4.100 V 0.25 V 2.50 V 0.4 V 0.15 V Unavailable (1) Yes
S-8261ABLMD-G3LT2x 4.275 V 0.20 V 2.30 V 0 V 0.05 V Unavailable (5) Yes
S-8261ABMMD-G3MT2x 4.280 V 0.20 V 2.80 V 0 V 0.10 V Available (1) Yes
S-8261ABNMD-G3NT2x 4.300 V 0.20 V 2.30 V 0 V 0.06 V Available (1) Yes
S-8261ABPMD-G3PT2x 4.200 V 0.10 V 2.80 V 0.1 V 0.15 V Unavailable (1) Yes
S-8261ABRMD-G3RT2x 4.275 V 0.20 V 2.50 V 0.4 V 0.15 V Unavailable (1) Yes
S-8261ABSMD-G3ST2x 4.280 V 0.10 V 2.50 V 0.5 V 0.18 V Unavailable (1) Yes
S-8261ABTMD-G3TT2x 4.280 V 0.20 V 3.00 V 0.4 V 0.08 V Available (5) Yes
S-8261ABYMD-G3YT2x 4.275 V 0.10 V 2.30 V 0.1 V 0.10 V Available (6) Yes
S-8261ABZMD-G3ZT2x 4.325 V 0.25 V 2.50 V 0.4 V 0.15 V Unavailable (6) Yes
S-8261ACAMD-G4AT2x 4.280 V 0.20 V 2.30 V 0 V 0.13 V Unavailable (6) Yes
S-8261ACBMD-G4BT2x 4.250 V 0.20 V 2.60 V 0.3 V 0.12 V Unavailable (1) No
S-8261ACDMD-G4DT2x 4.350 V 0.25 V 2.30 V 0.7 V 0.25 V Available (7) Yes
S-8261ACEMD-G4ET2x 3.900 V 0.10 V 2.00 V 0.3 V 0.10 V Available (1) Yes
S-8261ACFMD-G4FT2x 4.280 V 0.20 V 2.30 V 0 V 0.10 V Available (8) Yes
S-8261ACHMD-G4HT2x 4.465 V 0.30 V 2.10 V 0 V 0.15 V Available (9) Yes
S-8261ACIMD-G4IT2x 4.250 V 0.20 V 2.40 V 0.5 V 0.10 V Available (1) No
S-8261ACJMD-G4JT2x 4.275 V 0.10 V 2.30 V 0.1 V 0.15 V Available (1) Yes
S-8261ACKMD-G4KT2x 4.280 V 0.20 V 2.80 V 0 V 0.13 V Available (1) Yes
*1. Refer to the Table 2 about the details of the delay time combinations (1) to (9).
Remark 1. Please contact our sales office for the products with detection voltage value other than those specified above.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 5
Table 1 (2 / 2)
Product name
Overcharge
detection
voltage
[V
CU
]
Overcharge
hysteresis
voltage
[V
HC
]
Overdischarge
detection
voltage
[V
DL
]
Overdischarge
hysteresis
voltage
[V
HD
]
Overcurrent 1
detection
voltage
[V
IOV1
]
0 V battery
charge
function
Delay
time
combi-
nation
*1
Power down
function
S-8261ACMMD-G4MT2x 4.325 V 0.20 V 3.00 V 0.4 V 0.06 V Unavailable (1) Yes
S-8261ACNMD-G4NT2x 4.215 V 0.10 V 2.30 V 0.1 V 0.13 V Unavailable (1) Yes
S-8261ACSMD-G4ST2y 4.350 V 0.10 V 2.30 V 0.1 V 0.15 V Available (6) Yes
*1. Refer to the Table 2 about the details of the delay time combinations (1) to (9).
Remark 1. Please contact our sales office for the products with detection voltage value other than those specified above.
2. x: G or U
3. y: S or U
4. Please select products of environmental code = U for Sn 100%, halogen-free products.
Table 2
Delay time
combination
Overcharge
detection
delay time
[tCU]
Overdischarge
detection
delay time
[tDL]
Overcurrent 1
detection
delay time
[tlOV1]
Overcurrent 2
detection
delay time
[tlOV2]
Load short-circuiting
detection
delay time
[tSHORT]
(1) 1.2 s 144 ms 9 ms 2.24 ms 320
μ
s
(2) 1.2 s 144 ms 4.5 ms 2.24 ms 320
μ
s
(3) 4.6 s 36 ms 18 ms 9 ms 320
μ
s
(4) 4.6 s 144 ms 9 ms 2.24 ms 320
μ
s
(5) 1.2 s 36 ms 9 ms 2.24 ms 320
μ
s
(6) 1.2 s 144 ms 9 ms 1.12 ms 320
μ
s
(7) 1.2 s 290 ms 18 ms 2.24 ms 320
μ
s
(8) 1.2 s 144 ms 18 ms 2.24 ms 320
μ
s
(9) 0.3 s 36 ms 9 ms 1.12 ms 320
μ
s
Remark The delay times can be changed within the range listed Table 3. For details, please contact our sales office.
Table 3
Delay time Symbol Selection range Remarks
Overcharge detection delay time tCU 0.15 s
1.2 s*1 4.6 s Choose from the left.
Overdischarge detection delay time tDL 36 ms
144 ms*1 290 ms Choose from the left.
Overcurrent 1 detection delay time tlOV1 4.5 ms
9 ms*1 18 ms Choose from the left.
Overcurrent 2 detection delay time tlOV1 1.12 ms
2.24 ms*1 ⎯ Choose from the left.
Load short-circuiting detection delay time tSHORT ⎯ 320 μs*1 600 μs Choose from the left.
*1. The value is the delay time of the standard products.
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
6
Pin Configuration
Table 4
Pin No. Symbol Description
1 DO
FET gate control pin for discharge
(CMOS output)
2 VM
Voltage detection pin between VM and VSS
(Overcurrent detection pin)
3 CO
FET gate control pin for charge
(CMOS output)
4 DP Test pin for delay time measurement
5 VDD Positive power input pin
6 VSS Negative power input pin
SOT-23-6
Top view
6 4 5
1 2 3
Figure 2
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 7
Absolute Maximum Ratings
Table 5
(Ta = 25°C unless otherwise specified)
Item Symbol Applied pin Absolute Maximum Rating Unit
Input voltage between VDD and VSS VDS VDD VSS −0.3 to VSS +12 V
Input pin voltage for VM VVM VM VDD −28 to VDD +0.3 V
Output pin voltage for CO VCO CO VVM −0.3 to VDD+0.3 V
Output pin voltage for DO VDO DO VSS −0.3 to VDD +0.3 V
250 (When not mounted on board) mW
Power dissipation PD ⎯ 650*1 mW
Operating ambient temperature Topr ⎯ −40 to +85 °C
Storage temperature Tstg ⎯ −55 to +125 °C
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
(1) When mounted on board (2) When not mounted on board
600
400
0
200
0 50 100 150
500
300
100
700
Power dissipation (P
D
) [mW]
Ambient temperature (Ta) [°C]
600
400
0
Power dissipation (P
D
) [mW]
200
050 100 150
Ambient temperature (Ta) [°C]
500
300
100
Figure 3 Power Dissipation of Package
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
8
Electrical Characteristics
1. Except Detection Delay Time (25°C)
Table 6
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DETECTION VOLTAGE
⎯ VCU
−0.025 VCU VCU
+0.025 V 1 1
Overcharge detection voltage
V
CU
=
3.9 V to 4.4 V, 5 mV Step
VCU
Ta
=
−
5
°
C to 55
°
C
*1
VCU
−0.030 VCU VCU
+0.030 V 1 1
Overcharge hysteresis voltage
V
HC
=
0.1 V to 0.4 V, 50 mV Step
VHC ⎯ VHC
−0.025 VHC VHC
+0.025 V 1 1
Overdischarge detection voltage
V
DL
=
2.0 V to 3.0 V, 10 mV Step
VDL ⎯ VDL
−0.050 VDL VDL
+0.050 V 2 2
Overdischarge hysteresis voltage
V
HD
=
0.0 V to 0.7 V, 100 mV Step
VHD ⎯ VHD
−0.050 VHD VHD
+0.050 V 2 2
Overcurrent 1 detection voltage
V
IOV1
=
0.05 V to 0.3 V, 10 mV Step
VIOV1 ⎯ VIOV1
−0.015 VIOV1 VIOV1
+0.015 V 3 2
Overcurrent 2 detection voltage
VIOV2 ⎯ 0.4 0.5 0.6 V 3 2
Load short-circuiting detection voltage
VSHORT ⎯ 0.9 1.2 1.5 V 3 2
Charger detection voltage
VCHA ⎯ −1.0 −0.7 −0.4 V 4 2
INPUT VOLTAGE, OPERATION VOLTAGE
Operation voltage between VDD and VSS
VDSOP1
Internal circuit operating voltage
1.5 ⎯ 8 V ⎯ ⎯
Operation voltage between VDD and VM
VDSOP2
Internal circuit operating voltage
1.5 ⎯ 28 V ⎯ ⎯
CURRENT CONSUMPTION (with power-down function)
Current consumption in normal operation
IOPE
V
DD
=
3.5 V, V
VM
=
0 V
1.0 3.5 7.0 μA 5 2
Current consumption at power down
IPDN
V
DD
=
V
VM
=
1.5 V
⎯ ⎯ 0.1 μA 5 2
CURRENT CONSUMPTION (without power-down function)
Current consumption in normal operation
IOPE
V
DD
=
3.5 V, V
VM
=
0 V
1.0 3.5 7.0 μA 5 2
Overdischarge current consumption
IOPED
V
DD
=
V
VM
=
1.5 V
1.0 3.0 5.5 μA 5 2
OUTPUT RESISTANCE
CO pin resistance “H”
RCOH
V
CO
=
3.0 V, V
DD
=
3.5 V, V
VM
=
0 V
2.5 5 10 kΩ 7 4
CO pin resistance “L”
RCOL
V
CO
=
0.5 V, V
DD
=
4.5 V, V
VM
=
0 V
2.5 5 10 kΩ 7 4
DO pin resistance “H”
RDOH
V
DO
=
3.0 V, V
DD
=
3.5 V, V
VM
=
0 V
2.5 5 10 kΩ 8 4
DO pin resistance “L”
RDOL
V
DO
=
0.5 V, V
DD
=
V
VM
=
1.8 V
2.5 5 10 kΩ 8 4
VM INTERNAL RESISTANCE
Internal resistance between VM and VDD
RVMD
V
DD
=
1.8 V, V
VM
=
0 V
100 300 900 kΩ 6 3
Internal resistance between VM and VSS
RVMS
V
DD
=
3.5 V, V
VM
=
1.0 V
10 20 40 kΩ 6 3
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage
V0CHA
0 V battery charge “available”
1.2 ⎯ ⎯ V 11 2
0 V battery charge inhibition battery voltage
V0INH
0 V battery charge “unavailable”
⎯ ⎯ 0.5 V 12 2
*1. Since products are not screened at high and low temperatures, the specification for this temperature range is
guaranteed by design, not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 9
2. Except Detection Delay Time (−40°C to +85°C*1)
Table 7
(Ta = −40°C to +85°C*1 unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DETECTION VOLTAGE
Overcharge detection voltage
V
CU
=
3.9 V to 4.4 V, 5 mV Step
VCU ⎯ VCU
−0.055 VCU VCU
+0.040 V 1 1
Overcharge hysteresis voltage
V
HC
=
0.1 V to 0.4 V, 50 mV Step
VHC ⎯ VHC
−0.025 VHC VHC
+0.025 V 1 1
Overdischarge detection voltage
V
DL
=
2.0 V to 3.0 V, 10 mV Step
VDL ⎯ VDL
−0.080 VDL VDL
+0.080 V 2 2
Overdischarge hysteresis voltage
V
HD
=
0.0 V to 0.7 V, 100 mV Step
VHD ⎯ VHD
−0.050 VHD VHD
+0.050 V 2 2
Overcurrent 1 detection voltage
V
IOV1
=
0.05 V to 0.3 V, 10 mV Step
VIOV1 ⎯ VIOV1
−0.021 VIOV1 VIOV1
+0.021 V 3 2
Overcurrent 2 detection voltage
VIOV2 ⎯ 0.37 0.5 0.63 V 3 2
Load short-circuiting detection voltage
VSHORT ⎯ 0.7 1.2 1.7 V 3 2
Charger detection voltage
VCHA ⎯ −1.2 −0.7 −0.2 V 4 2
INPUT VOLTAGE, OPERATION VOLTAGE
Operation voltage between VDD and VSS
VDSOP1
Internal circuit operating voltage
1.5 ⎯ 8 V ⎯ ⎯
Operation voltage between VDD and VM
VDSOP2
Internal circuit operating voltage
1.5 ⎯ 28 V ⎯ ⎯
CURRENT CONSUMPTION (with power-down function)
Current consumption in normal operation
IOPE
V
DD
=
3.5 V, V
VM
=
0 V
0.7 3.5 8.0 μA 5 2
Current consumption at power down
IPDN
V
DD
=
V
VM
=
1.5 V
⎯ ⎯ 0.1 μA 5 2
CURRENT CONSUMPTION (without power-down function)
Current consumption in normal operation
IOPE
V
DD
=
3.5 V, V
VM
=
0 V
0.7 3.5 8.0 μA 5 2
Overdischarge current consumption
IOPED
V
DD
=
V
VM
=
1.5 V
0.7 3.0 6.0 μA 5 2
OUTPUT RESISTANCE
CO pin resistance “H”
RCOH
V
CO
=
3.0 V, V
DD
=
3.5 V, V
VM
=
0 V
1.2 5 15 kΩ 7 4
CO pin resistance “L”
RCOL
V
CO
=
0.5 V, V
DD
=
4.5 V, V
VM
=
0 V
1.2 5 15 kΩ 7 4
DO pin resistance “H”
RDOH
V
DO
=
3.0 V, V
DD
=
3.5 V, V
VM
=
0 V
1.2 5 15 kΩ 8 4
DO pin resistance “L”
RDOL
V
DO
=
0.5 V, V
DD
=
V
VM
=
1.8 V
1.2 5 15 kΩ 8 4
VM INTERNAL RESISTANCE
Internal resistance between VM and VDD
RVMD
V
DD
=
1.8 V, V
VM
=
0 V
78 300 1310 kΩ 6 3
Internal resistance between VM and VSS
RVMS
V
DD
=
3.5 V, V
VM
=
1.0 V
7.2 20 44 kΩ 6 3
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage
V0CHA
0 V battery charge “available”
1.7 ⎯ ⎯ V 11 2
0 V battery charge inhibition battery voltage
V0INH
0 V battery charge “unavailable”
⎯ ⎯ 0.3 V 12 2
*1. Since products are not screened at high and low temperatures, the specification for this temperature range is
guaranteed by design, not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
10
3. Detection Delay Time
(1) S-8261AAG, S-8261AAH, S-8261AAJ, S-8261AAL, S-8261AAM, S-8261AAN, S-8261AAO, S-8261AAP,
S-8261AAR, S-8261AAZ, S-8261ABB, S-8261ABC, S-8261ABJ, S-8261ABK, S-8261ABM, S-8261ABN,
S-8261ABP, S-8261ABR, S-8261ABS, S-8261ACB, S-8261ACE, S-8261ACI, S-8261ACK, S-8261ACM,
S-8261ACJ, S-8261ACN
Table 8
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.96 1.2 1.4 s 9 5
Overdischarge detection delay time t
DL
⎯
115 144 173 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
7.2 9 11 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.8 2.24 2.7 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.7 1.2 2.0 s 9 5
Overdischarge detection delay time t
DL
⎯
80 144 245 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
5 9 15 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.2 2.24 3.8 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
(2) S-8261AAS
Table 9
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.96 1.2 1.4 s 9 5
Overdischarge detection delay time t
DL
⎯
115 144 173 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
3.6 4.5 5.4 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.8 2.24 2.7 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.7 1.2 2.0 s 9 5
Overdischarge detection delay time t
DL
⎯
80 144 245 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
2.5 4.5 7.7 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.2 2.24 3.8 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 11
(3) S-8261AAT
Table 10
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
3.7 4.6 5.5 s 9 5
Overdischarge detection delay time t
DL
⎯
29 36 43 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
14 18 22 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
7.2 9 11 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
2.5 4.6 7.8 s 9 5
Overdischarge detection delay time t
DL
⎯
20 36 61 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
10 18 31 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
5 9 15 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
(4) S-8261AAU, S-8261AAX, S-8261ABA
Table 11
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
3.7 4.6 5.5 s 9 5
Overdischarge detection delay time t
DL
⎯
115 144 173 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
7.2 9 11 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.8 2.24 2.7 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
2.5 4.6 7.8 s 9 5
Overdischarge detection delay time t
DL
⎯
80 144 245 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
5 9 15 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.2 2.24 3.8 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
12
(5) S-8261ABI, S-8261ABL, S-8261ABT
Table 12
Item Symbol Condition Min. Typ. Max. Unit
Test
condition
Test
circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.96 1.2 1.4 s 9 5
Overdischarge detection delay time t
DL
⎯
29 36 43 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
7.2 9 11 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.8 2.24 2.7 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.7 1.2 2.0 s 9 5
Overdischarge detection delay time t
DL
⎯
20 36 61 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
5 9 15 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.2 2.24 3.8 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
(6) S-8261ABY, S-8261ABZ, S-8261ACA, S-8261ACS
Table 13
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.96 1.2 1.4 s 9 5
Overdischarge detection delay time t
DL
⎯
115 144 173 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
7.2 9 11 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
0.89 1.12 1.35 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.7 1.2 2.0 s 9 5
Overdischarge detection delay time t
DL
⎯
80 144 245 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
5 9 15 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
0.61 1.12 1.91 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 13
(7) S-8261ACD
Table 14
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.96 1.2 1.4 s 9 5
Overdischarge detection delay time t
DL
⎯
232 290 348 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
14 18 22 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.8 2.24 2.7 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.7 1.2 2.0 s 9 5
Overdischarge detection delay time t
DL
⎯
160 290 493 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
10 18 31 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.2 2.24 3.8 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
(8) S-8261ACF
Table 15
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.96 1.2 1.4 s 9 5
Overdischarge detection delay time t
DL
⎯
115 144 173 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
14 18 22 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.8 2.24 2.7 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.7 1.2 2.0 s 9 5
Overdischarge detection delay time t
DL
⎯
80 144 245 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
10 18 31 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
1.2 2.24 3.8 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
14
(9) S-8261ACH
Table 16
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition
Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time t
CU
⎯
0.24 0.3 0.36 s 9 5
Overdischarge detection delay time t
DL
⎯
29 36 43 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
7.2 9 11 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
0.89 1.12 1.35 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
220 320 380
μ
s 10 5
DELAY TIME (Ta =
−
40°C to
+
85°C)
*1
Overcharge detection delay time t
CU
⎯
0.17 0.3 0.51 s 9 5
Overdischarge detection delay time t
DL
⎯
20 36 61 ms 9 5
Overcurrent 1 detection delay time t
lOV1
⎯
5 9 15 ms 10 5
Overcurrent 2 detection delay time t
lOV2
⎯
0.61 1.12 1.91 ms 10 5
Load short-circuiting detection delay time t
SHORT
⎯
150 320 540
μ
s 10 5
*1.
Since products are not screened at high and low temperatures, the specification for this temperature range is guaranteed by design,
not tested in production.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 15
Test Circuits
Caution Unless otherwise specified, the output voltage levels “H” and “L” at CO pin (VCO) and DO pin (VDO) are
judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to
VVM and the DO pin level with respect to VSS.
(1) Test Condition 1, Test Circuit 1
(Overcharge Detection Voltage, Overcharge Hysteresis Voltage)
The overcharge detection voltage (VCU) is defined as the voltage between VDD and VSS at which VCO goes from “H”
to “L” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V. The overcharge
hysteresis voltage (VHC) is then defined as the difference between the overcharge detection voltage (VCU) and the
voltage between VDD and VSS at which VCO goes from “L” to “H” when the voltage V1 is gradually decreased.
(2) Test Condition 2, Test Circuit 2
(Overdischarge Detection Voltage, Overdischarge Hysteresis Voltage)
The overdischarge detection voltage (VDL) is defined as the voltage between VDD and VSS at which VDO goes from
“H” to “L” when the voltage V1 is gradually decreased from the starting condition of V1 = 3.5 V and V2 = 0 V. The
overdischarge hysteresis voltage (VHD) is then defined as the difference between the overdischarge detection
voltage (VDL) and the voltage between VDD and VSS at which VDO goes from “L” to “H” when the voltage V1 is
gradually increased.
(3) Test Condition 3, Test Circuit 2
(Overcurrent 1 Detection Voltage, Overcurrent 2 Detection Voltage, Load Short-Circuiting Detection Voltage)
The overcurrent 1 detection voltage (VIOV1) is defined as the voltage between VM and VSS whose delay time for
changing VDO from “H” to “L” lies between the minimum and the maximum value of the overcurrent 1 detection delay
time when the voltage V2 is increased rapidly (within 10 μs) from the starting condition V1 = 3.5 V and V2 = 0 V.
The overcurrent 2 detection voltage (VIOV2) is defined as the voltage between VM and VSS whose delay time for
changing VDO from “H” to “L” lies between the minimum and the maximum value of the overcurrent 2 detection delay
time when the voltage V2 is increased rapidly (within 10 μs) from the starting condition V1 = 3.5 V and V2 = 0 V.
The load short-circuiting detection voltage (VSHORT) is defined as the voltage between VM and VSS whose delay time
for changing VDO from “H” to “L” lies between the minimum and the maximum value of the load short-circuiting
detection delay time when the voltage V2 is increased rapidly (within 10 μs) from the starting condition V1 = 3.5 V
and V2 = 0 V.
(4) Test Condition 4, Test Circuit 2
(Charger Detection Voltage, Abnormal Charge Current Detection Voltage)
The charger detection voltage (VCHA) is defined as the voltage between VM and VSS at which VDO goes from “L” to
“H” when the voltage V2 is gradually decreased from 0 V after the voltage V1 is gradually increased from the starting
condition of V1 = 1.8 V and V2 = 0 V until the voltage V1 becomes V1 = VDL + (VHD / 2).
The charger detection voltage can be measured only in the product whose overdischarge hysteresis VHD ≠ 0.
Set V1 = 3.5 V and V2 = 0 V. Decrease V2 from 0 V gradually. The voltage between VM and VSS when VCO goes
from “H” to “L” is the abnormal charge current detection voltage. The abnormal charge current detection voltage has
the same value as the charger detection voltage (VCHA).
(5) Test Condition 5, Test Circuit 2
(Normal Operation Current Consumption, Power-Down Current Consumption, Overdischarge Current Consumption)
With power-down function
The operating current consumption (IOPE) is the current that flows through the VDD pin (IDD) under the set conditions
of V1 = 3.5 V and V2 = 0 V (Normal status).
The power-down current consumption (IPDN) is the current that flows through the VDD pin (IDD) under the set
conditions of V1 = V2 = 1.5 V (Overdischarge status).
Without power-down function
The operating current consumption (IOPE) is the current that flows through the VDD pin (IDD) under the set conditions
of V1 = 3.5 V and V2 = 0 V (Normal status).
The Overdischarge
current consumption (IOPED) is the current that flows through the VDD pin (IDD) under the set
conditions of V1 = V2 = 1.5 V (Overdischarge status).
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
16
(6) Test Condition 6, Test Circuit 3
(Internal Resistance between VM and VDD, Internal Resistance between VM and VSS)
The resistance between VM and VDD (RVMD) is the internal resistance between VM and VDD under the set
conditions of V1 = 1.8 V and V2 = 0 V.
The resistance between VM and VSS (RVMS) is the internal resistance between VM and VSS under the set
conditions of V1 = 3.5 V and V2 = 1.0 V.
(7) Test Condition 7, Test Circuit 4
(CO Pin Resistance “H”, CO Pin Resistance “L”)
The CO pin resistance “H” (RCOH) is the resistance the CO pin under the set condition of V1 = 3.5 V, V2 = 0 V and V3
= 3.0 V.
The CO pin resistance “L” (RCOL) is the resistance the CO pin under the set condition of V1 = 4.5 V, V2 = 0 V and V3
= 0.5 V.
(8) Test Condition 8, Test Circuit 4
(DO Pin Resistance “H”, DO Pin Resistance “L”)
The DO pin resistance “H” (RDOH) is the resistance the DO pin under the set condition of V1 = 3.5 V, V2 = 0 V and V4
= 3.0 V.
The DO pin resistance “L” (RDOL) is the resistance the DO pin under the set condition of V1 = 1.8 V, V2 = 0 V and V4
= 0.5 V.
(9) Test Condition 9, Test Circuit 5
(Overcharge Detection Delay Time, Overdischarge Detection Delay Time)
The overcharge detection delay time (tCU) is the time needed for VCO to change from “H” to “L” just after the voltage
V1 momentarily increases (within 10 μs) from the overcharge detection voltage (VCU) − 0.2 V to the overcharge
detection voltage (VCU) + 0.2 V under the set condition of V2 = 0 V.
The overdischarge detection delay time (tDL) is the time needed for VDO to change from “H” to “L” just after the
voltage V1 momentarily decreases (within 10 μs) from the overdischarge detection voltage (VDL) +0.2 V to the
overdischarge detection voltage (VDL) − 0.2 V under the set condition of V2 = 0 V.
(10) Test Condition 10, Test Circuit 5
(Overcurrent 1 Detection Delay Time, Overcurrent 2 Detection Delay Time, Load Short-circuiting Detection
Delay Time, Abnormal Charge Current Detection Delay Time)
The overcurrent 1 detection delay time (tIOV1) is the time needed for VDO to go “L” after the voltage V2 momentarily
increases (within 10 μs) from 0 V to 0.35 V under the set condition of V1 = 3.5 V and V2=0 V.
The overcurrent 2 detection delay time (tIOV2) is the time needed for VDO to go “L” after the voltage V2 momentarily
increases (within 10 μs) from 0 V to 0.7 V under the set condition of V1 = 3.5 V and V2 = 0 V.
The load short-circuiting detection delay time (tSHORT) is the time needed for VDO to go “L” after the voltage V2
momentarily increases (within 10 μs) from 0 V to 1.6 V under the set condition of V1 = 3.5 V and V2 = 0 V.
The abnormal charge current detection delay time is the time needed for VCO to go from “H” to “L” after the voltage
V2 momentarily decreases (within 10 μs) from 0 V to −1.1 V under the set condition of V1 = 3.5 V and V2 = 0 V. The
abnormal charge current detection delay time has the same value as the overcharge detection delay time.
(11) Test Condition 11, Test Circuit 2 (0 V battery charge function)
(0 V Battery Charge Starting Charger Voltage)
The 0 V battery charge starting charger voltage (V0CHA) is defined as the voltage between VDD and VM at which VCO
goes “H” (VVM + 0.1 V or higher) when the voltage V2 is gradually decreased from the starting condition of V1 = V2 =
0 V.
(12) Test Condition 12, Test Circuit 2 (0 V battery charge inhibition function)
(0 V Battery Charge Inhibition Battery Voltage)
The 0 V battery charge inhibition battery voltage (V0INH) is defined as the voltage between VDD and VSS at which
VCO goes “H” (VVM + 0.1 V or higher) when the voltage V1 is gradually increased from the starting condition of V1 = 0
V and V2 = −4 V.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 17
VSS
DO CO
VDD
S-8261 Series
R1 = 470 Ω
V1
VM
V VDO
COM
V VCO
DP
VSS
DO CO
S-8261 Series
V1
IDD
VM
V2
A
V VDO
COM
V VCO
VDD DP
Test Circuit 1 Test Circuit 2
VDD
DO CO
S-8261 Series
V1
IDD
VM
V2
IVM
A
A
COM
VSS
DP
VSS
DO CO
S-8261 Series
V1
VM
V
2
COM
AIDO A ICO
V4 V3
VDD DP
Test Circuit 3 Test Circuit 4
VSS
DO CO
S-8261 Series
V1
VM
V2
Oscilloscope
COM
Oscilloscope
VDD DP
Test Circuit 5
Figure 4
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
18
Operation
Remark Refer to “ Battery Protection IC Connection Example”.
1. Normal Status
The S-8261 Series monitors the voltage of the battery connected between VDD pin and VSS pin and the voltage
difference between VM pin and VSS pin to control charging and discharging. When the battery voltage is in the
range from the overdischarge detection voltage (VDL) to the overcharge detection voltage (VCU), and the VM pin
voltage is in the range from the charger detection voltage (VCHA) to the overcurrent 1 detection voltage (VIOV1), the IC
turns both the charging and discharging control FETs on. This status is called the normal status, and in this status
charging and discharging can be carried out freely.
Caution When a battery is connected to the IC for the first time, discharging may not be enabled. In this
case, short the VM pin and VSS pin or connect the charger to restore the normal condition.
2. Overcurrent Status (Detection of Overcurrent 1, Overcurrent 2 and Load Short-circuiting)
When a battery in the normal status is in the status where the voltage of the VM pin is equal to or higher than the
overcurrent detection voltage because the discharge current is higher than the specified value and the status lasts for
the overcurrent detection delay time, the discharge control FET is turned off and discharging is stopped. This status
is called the overcurrent status.
In the overcurrent status, the VM and VSS pins are shorted by the resistor between VM and VSS (RVMS) in the IC.
However, the voltage of the VM pin is at the VDD potential due to the load as long as the load is connected. When the
load is disconnected completely, the VM pin returns to the VSS potential.
The voltage of the VM pin returns to overcurrent 1 detection voltage (VIOV1) or lower and the overcurrent status is
restored to the normal status.
3. Overcharge Status
When the battery voltage becomes higher than the overcharge detection voltage (VCU) during charging under the
normal status and the detection continues for the overcharge detection delay time (tCU) or longer, the S-8261 Series
turns the charging control FET off to stop charging. This status is called the overcharge status.
The overcharge status is released by the following two cases ((1) and (2)):
(1) When the battery voltage falls below the overcharge release voltage (VCU) − overcharge detection hysteresis
voltage (VHC), the S-8261 Series turns the charging control FET on and turns to the normal status.
(2) When a load is connected and discharging starts, the S-8261 Series turns the charging control FET on and
returns to the normal status. Just after the load is connected and discharging starts, the discharging current flows
through the parasitic diode in the charging control FET. At this moment the VM pin potential becomes Vf, the
voltage for the parasitic diode, higher than VSS level. When the battery voltage goes under the overcharge
detection voltage (VCU) and provided that the VM pin voltage is higher than the overcurrent 1 detection voltage,
the S-8261 Series releases the overcharge status.
Caution 1. If the battery is charged to a voltage higher than the overcharge detection voltage (VCU) and the
battery voltage does not fall below the overcharge detection voltage (VCU) even when a heavy load
is connected, the detection of overcurrent 1, overcurrent 2 and load short-circuiting do not
function until the battery voltage falls below overcharge detection voltage (VCU). Since an actual
battery has an internal impedance of several dozens of mΩ, the battery voltage drops immediately
after a heavy load that causes overcurrent is connected, and the detection of overcurrent 1,
overcurrent 2 and load short-circuiting function.
2. When a charger is connected after the overcharge detection, the overcharge status is not
released even if the battery voltage is below the overcharge release voltage (VCL). The
overcharge status is released when the VM pin voltage goes over the charger detection voltage
(VCHA) by removing the charger.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 19
4. Overdischarge Status
With power-down function
When the battery voltage falls below the overdischarge detection voltage (VDL) during discharging under the normal
status and the detection continues for the overdischarge detection delay time (tDL) or longer, the S-8261 Series turns
the discharging control FET off to stop discharging. This status is called the overdischarge status. When the
discharging control FET is turned off, the VM pin voltage is pulled up by the resistor between VM and VDD in the IC
(RVMD). When the voltage difference between the VM and VDD then is 1.3 V (typ.) or lower, the current consumption
is reduced to the power-down current consumption (IPDN). This status is called the power-down status.
The power-down status is released when a charger is connected and the voltage difference between the VM and
VDD becomes 1.3 V (typ.) or higher. Moreover when the battery voltage becomes the overdischarge detection
voltage (VDL) or higher, the S-8261 Series turns the discharging FET on and returns to the normal status.
Without power-down function
When the battery voltage falls below the overdischarge detection voltage (VDL) during discharging under the normal
status and the detection continues for the overdischarge detection delay time (tDL) or longer, the S-8261 Series turns
the discharging control FET off to stop discharging. This status is called the overdischarge status. When the
discharging control FET is turned off, the VM pin voltage is pulled up by the resistor between VM and VDD in the IC
(RVMD).
When the battery voltage becomes the overdischarge detection voltage (VDL) or higher, the S-8261 Series turns the
discharging FET on and returns to the normal status.
5. Charger Detection
When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is lower
than the charger detection voltage (VCHA), the S-8261 Series releases the overdischarge status and turns the
discharging control FET on when the battery voltage becomes equal to or higher than the overdischarge detection
voltage (VDL) since the charger detection function works. This action is called charger detection.
When a battery in the overdischarge status is connected to a charger and provided that the VM pin voltage is not
lower than the charger detection voltage (VCHA), the S-8261 Series releases the overdischarge status when the
battery voltage reaches the overdischarge detection voltage (VDL) + overdischarge hysteresis (VHD) or higher.
6. Abnormal Charge Current Detection
If the VM pin voltage falls below the charger detection voltage (VCHA) during charging under normal status and it
continues for the overcharge detection delay time (tCU) or longer, the charging control FET turns off and charging
stops. This action is called the abnormal charge current detection.
Abnormal charge current detection works when the DO pin voltage is “H” and the VM pin voltage falls below the
charger detection voltage (VCHA). Consequently, if an abnormal charge current flows to an over-discharged battery,
the S-8261 Series turns the charging control FET off and stops charging after the battery voltage becomes higher
than the overdischarge detection voltage which make the DO pin voltage “H”, and still after the overcharge detection
delay time (tCU) elapses.
Abnormal charge current detection is released when the voltage difference between VM pin and VSS pin becomes
less than charger detection voltage (VCHA).
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
20
7. Delay Circuit
The detection delay times are determined by dividing a clock of the approximately 3.5 kHz with the counter.
Remark 1. The detection delay time for overcurrent 2 (tIOV2) and load short-circuiting (tSHORT) start when the
overcurrent 1 (VIOV1) is detected. When the overcurrent 2 (VIOV2) or load short-circuiting (VSHORT) is
detected over the detection delay time for each of them (= tIOV2 or tSHORT) after the detection of
overcurrent 1 (VIOV1), the S-8261 Series turns the FET off within tIOV2 or tSHORT of each detection.
DO pin
VM pin
V
DD
V
DD
Time
V
IOV1
V
SS
V
SS
V
IOV2
Overcurrent 2 detection delay time (t
IOV2
)
Time
t
D
0 ≤ t
D
≤ t
IOV2
Figure 5
2. With power-down function
When the overcurrent is detected and continues for longer than the overdischarge detection delay time
(tDL) without releasing the load, the status changes to the power-down status when the battery voltage
falls below the overdischarge detection voltage (VDL). When the battery voltage falls below the
overdischarge detection voltage (VDL) due to the overcurrent, the S-8261 Series turns the discharging
control FET off by the overcurrent detection. In this case if the recovery of the battery voltage is so slow
that the battery voltage after the overdischarge detection delay time (tDL) is still lower than the
overdischarge detection voltage (VDL), the S-8261 Series shifts to the power-down status.
Without power-down function
When the overcurrent is detected and continues for longer than the overdischarge detection delay time
(tDL) without released the load, the status changes to the overdischarge status when the battery voltage
falls below overdischarge detection voltage (VDL).When the battery voltage falls below overdischarge
detection voltage (VDL) due to the overcurrent, the S-8261 Series turns the discharging control FET off by
the overcurrent detection. In this case, if the recovery of the battery voltage is so slow that the battery
voltage after the overdischarge detection delay time (tDL) is still lower than the overdischarge detection
voltage (VDL), the S-8261 Series shifts to the overdischarge status.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 21
8. DP Pin
The DP pin is a test pin for delay time measurement and it should be open in the actual application. If a capacitor
whose capacitance is larger than 1000 pF or a resistor whose resistance is less than 1 MΩ is connected to this pin,
error may occur in the delay times or in the detection voltages.
9. 0 V Battery Charge Function “Available”
This function is used to recharge the connected battery whose voltage is 0 V due to the self-discharge. When the 0 V
battery charge starting charger voltage (V0CHA) or higher is applied between EB+ pin and EB− pin by connecting a
charger, the charging control FET gate is fixed to VDD pin voltage. When the voltage between the gate and source
of the charging control FET becomes equal to or higher than the turn-on voltage due to the charger voltage, the
charging control FET is turned on to start charging. At this time, the discharging control FET is off and the charging
current flows through the internal parasitic diode in the discharging control FET. When the battery voltage becomes
equal to or higher than the overdischarge detection voltage (VDL) and the overdischarge hysteresis voltage (VHD), the
S-8261 Series enters the normal status.
Caution Some battery providers do not recommend charging for completely self-discharged battery.
Please ask battery providers before determine whether to enable or inhibit the 0 V battery charge
function.
Remark The 0 V battery charge function has higher priority than the abnormal charge current detection function.
Consequently, a product with the 0 V battery charging function is enabled charges a battery forcibly and
abnormal charge current cannot be detected when the battery voltage is low.
10. 0 V Battery Charge Function “Unavailable”
This function inhibits the recharging when a battery that is short-circuited (0 V battery) internally is connected. When
the battery voltage is the 0 V battery charge inhibition battery voltage (V0INH) or lower, the charging control FET gate
is fixed to EB− pin voltage to inhibit charging. When the battery voltage is the 0 V battery charge inhibition battery
voltage (V0INH) or higher, charging can be performed.
Caution Some battery providers do not recommend charging for completely self-discharged battery.
Please ask battery providers before determining the 0 V battery charge function.
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
22
Timing Chart
(1) Overcharge and Overdischarge Detection
V
DL+
V
HD
VDL
VDD
VSS
(2)(1) (1)
(1) (3)
Battery
voltage
DO pin
CO pin
VM pin
Charger connection
Load connection
Status
Overdischarge detection delay time (tDL)
Remark (1) Normal status, (2) Overcharge status, (3) Overdischarge status, (4) Overcurrent status
The charger is supposed to charge with constant current.
Overcharge detection delay time (tCU)
V
DD
V
DD
V
IOV1
VSS
VCHA
VSS
VCU
VCU–VHC
Figure 6
(2) Overcurrent Detection
VCU
VCU−VHC
VDL+VHD
VDL
VDD
VSS
V
DD
VSS
(1)
(4)
(1)
(4)
(1)
(4)
(1)
V
DD
VSHORT
VIOV2
VIOV1
VSS
Overcurrent 1 detection delay time (tIOV1) Overcurrent 2 detection delay time (tIOV2) Load short-circuiting detection delay time (tSHORT)
Battery
voltage
DO pin
CO pin
VM pin
Charger connection
Load connection
Status
Remark (1) Normal status, (2) Overcharge status, (3) Overdischarge status, (4) Overcurrent status
The charger is supposed to charge with constant current.
Figure 7
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 23
(3) Charger Detection
VCU
VCU−VHC
VDL+VHD
VDL
VDD
VSS
V
DD
VSS
V
DD
VSS
VCHA
Overdischarge detection delay time (tDL )
In case VM pin voltage < VCHA
Overdischarge is released at the overdischarge
detection voltage (VDL )
(1)
(3)
(1)
Battery
voltage
DO pin
CO pin
VM pin
Charger connection
Load connection
Status
Remark (1) Normal status, (2) Overcharge status, (3) Overdischarge status, (4) Overcurrent status
The charger is supposed to charge with constant current.
Figure 8
(4) Abnormal Charge Current Detection
Abnormal charging current detection delay time
( = Overcharge detection delay time (tCU))
Overdischarge detection delay time (tDL
)
(3) (1) (2) (1)
(1)
Battery
voltage
DO pin
CO pin
VM pin
Charger connection
Load connection
Status
Remark (1) Normal status, (2) Overcharge status, (3) Overdischarge status, (4) Overcurrent status
The charger is supposed to charge with constant current.
V
CU
VCU−VHC
VDL+VHD
VDL
VDD
VSS
V
DD
VSS
VDD
VSS
VCHA
Figure 9
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
24
Battery Protection IC Connection Example
R1 : 470
Ω
Battery C1 :
0.1
μ
F
VSS
DO
VDD
CO VM
S-8261 Series
FET1 FET2
EB
−
EB
+
R2 : 2 k
Ω
DP
Figure 10
Table 17 Constant for External Components
Symbol Part Purpose Typ. Min. Max. Remarks
FET1 N-channel
MOS FET Discharge control
⎯
⎯
⎯
Threshold voltage
≤
Overdischarge detection voltage
*1
Gate to source withstanding voltage
≥
Charger voltage
*2
FET2 N-channel
MOS FET Charge control
⎯
⎯
⎯
Threshold voltage
≤
Overdischarge detection voltage
*1
Gate to source withstanding voltage
≥
Charger voltage
*2
R1 Resistor
ESD protection,
For power fluctuation 470
Ω
300
Ω
1 k
Ω
Resistance should be as small as possible to avoid lowering of
the overcharge detection accuracy caused by VDD pin current.
*3
C1 Capacitor For power fluctuation 0.1
μ
F 0.022
μ
F 1.0
μ
F Install a capacitor of 0.022
μ
F or higher between VDD and
VSS.
*4
R2 Resistor
Protection for reverse
connection of a charger 2 k
Ω
300
Ω
4 k
Ω
Select a resistance as large as possible to prevent large current
when a charger is connected in reverse.
*5
*1. If the threshold voltage of an FET is low, the FET may not cut the charging current.
If an FET with a threshold voltage equal to or higher than the overdischarge detection voltage is used, discharging
may be stopped before overdischarge is detected.
*
*2. If the withstanding voltage between the gate and source is lower than the charger voltage, the FET may be destroyed.
*3. If R1 has a high resistance, the voltage between VDD and VSS may exceed the absolute maximum rating when a
charger is connected in reverse since the current flows from the charger to the IC. Insert a resistor of 300 Ω or higher
to R1 for ESD protection.
*4. If a capacitor of less than 0.022 μF is connected to C1, DO may oscillate when load short-circuiting is detected. Be
sure to connect a capacitor of 0.022 μF or higher to C1.
*5. If R2 has a resistance higher than 4 kΩ, the charging current may not be cut when a high-voltage charger is
connected.
Caution 1. The above constants may be changed without notice.
2. The DP pin should be open.
3. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do not
guarantee proper operation. Perform through evaluation using the actual application to set the
constant.
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 25
Precautions
• The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
26
Characteristics (Typical Data)
1. Detection / Release Voltage Temperature Characteristics
Overcharge detection voltage vs. temperature Overcharge release voltage vs. temperature
4.34
4.36
4.38
4.40
4.42
4.44
−25 0 25 50 75
Ta [°C]
V
CU
[V]
−50 100
3.92
3.94
3.96
3.98
4.00
4.02
−
25 0 25 50 75
Ta
[
°C
]
V
CL
[V]
−
50 100
Overdischarge detection voltage vs. temperature Overdischarge release voltage vs. temperature
2.94
2.96
2.98
3.00
3.02
3.04
−25 0 25 50 75
Ta [°C]
VDL [V]
−50 100
3.34
3.36
3.38
3.40
3.42
3.44
−
25 0 25 50 75
Ta [°C]
V
DU
[V]
−
50 100
Overcurrent 1 detection voltage vs. temperature Overcurrent 2 detection voltage vs. temperature
0.15
0.20
0.25
0.30
0.35
0.40
0.45
−25 0 25 50 75
Ta [°C]
V
IOV1
[V]
−50 100
0.40
0.45
0.50
0.55
0.60
0.65
−
25 0 25 50 75
Ta [°C]
V
IOV2
[V]
−
50 100
Load short-circuiting detection voltage vs. temperature
1.0
1.1
1.2
1.3
1.4
1.5
−25 0 25 50 75
Ta [°C]
VSHORT [V]
−50 100
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 27
2. Current Consumption Temperature Characteristics
Current consumption vs. temperature in normal mode Current consumption vs. temperature in power-down mode
0
1
2
3
4
5
−25 0 25 50 75
Ta
[
°C
]
IOPE [
μ
A]
−50 100
0
0.02
0.04
0.06
0.08
0.10
−
25 0 25 50 75
Ta [°C]
IPDN [
μ
A]
−
50 100
3. Current Consumption Power Voltage Characteristics (Ta = 25°C)
Current consumption power supply voltage dependency
0
1
2
3
4
5
6
0 2 4 6 8 10 12
V
DD
[V]
I
OPE
[μA]
4. Detection / Release Delay Time Temperature Characteristics
Overcharge detection delay time vs. temperature Overcharge release delay time vs. temperature
0.50
0.75
1.00
1.25
1.50
−
25 0 25 50 75
Ta [°C]
t
CU
[s]
−
50 100
10
20
30
40
50
60
−
25 0 25 50 75
Ta [°C]
t
CL
[ms]
−
50 100
Overdischarge detection delay time vs. temperature
100
120
140
160
180
200
−25 0 25 50 75
Ta [°C]
t
DL
[ms]
−50 100
LOW DROPOUT CMOS VOLTAGE REGULATOR
S-8261 Series Rev.5.2_00
Seiko Instruments Inc.
28
Overcurrent 1 detection delay time vs. temperature Overcurrent 2 detection delay time vs. temperature
5
7
9
11
13
15
−25 0 25 50 75
Ta [°C]
t
IOV1
[ms]
−50 100
1.4
1.8
2.2
2.6
3.0
3.4
−
25 0 25 50 75
Ta [°C]
t
IOV2
[ms]
−
50 100
Load short-circuiting delay time vs. temperature
0.16
0.20
0.24
0.28
0.32
0.36
0.40
−25 0 25 50 75
Ta [°C]
t
SHORT
[ms]
−50 100
5. Delay Time Power-Voltage Characteristics (Ta = 25°C)
Overcurrent 1 detection delay time vs. power supply voltage dependency Overcurrent 2 detection delay time vs. power supply voltage dependency
5
7
9
11
13
15
2 2.5 3 3.5 4 4.5
V
DD
[V]
t
IOV1
[V]
1.4
1.8
2.2
2.6
3.0
3.4
2 2.5 3 3.5 4 4.5
V
DD
[V]
t
IOV2
[ms]
Load short-circuiting delay time vs. power supply voltage dependency
0.16
0.2
0.24
0.28
0.32
2.5 3 3.5 4 4.5
V
DD
[V]
t
SHORT
[ms]
LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.5.2_00 S-8261 Series
Seiko Instruments Inc. 29
6. CO Pin / DO Pin Output Current Characteristics (Ta = 25°C)
CO pin source current characteristics V
DD
=
3.5 V, V
M
=
V
SS
=
0 V CO pin sink current characteristics V
DD
=
4.5 V, V
M
=
V
SS
=
0 V
−0.5
−0.4
−0.3
−0.2
−0.1
0
0 1 2 3 4
VCO [V]
ICO [mA]
0.5
0.4
0.3
0.2
0.1
0
0123 5
VCO [V]
ICO [mA]
4
DO pin source current characteristics V
DD
=
3.5 V, V
M
=
V
SS
=
0 V DO pin sink current characteristics V
DD
=
1.8 V, V
M
=
V
SS
=
0 V
−0.5
−0.4
−0.3
−0.2
−0.1
0
0 1 2 3 4
VDO [V]
IDO [mA]
0.5
0.4
0.3
0.2
0.1
0
00.51 2
VDO [V]
IDO [mA]
1.5
2.9±0.2
0.15
1.9±0.2
123
4
65
0.35±0.15
0.95
+0.1
-0.05
0.95
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
No. MP006-A-P-SD-2.0
MP006-A-P-SD-2.0
SOT236-A-PKG Dimensions
No.
TITLE
SCALE
UNIT mm
123
45
6
ø1.5 +0.1
-0 2.0±0.05
ø1.0 +0.2
-0 4.0±0.1
1.4±0.2
0.25±0.1
3.2±0.2
Seiko Instruments Inc.
No. MP006-A-C-SD-3.1
MP006-A-C-SD-3.1
SOT236-A-Carrier Tape
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
No.
TITLE
SCALE
UNIT mm
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY 3,000
Seiko Instruments Inc.
Enlarged drawing in the central part
No. MP006-A-R-SD-2.1
MP006-A-R-SD-2.1
SOT236-A-Reel
www.sii-ic.com
• The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
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• The products described herein cannot be used as part of any device or equipment affecting the human
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installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
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• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
