FEBRUARY 2017
DSC-3619/09
1
©2017 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆64K x 32 memory configuration
◆◆
◆◆
◆Supports high system speed:
Commercial:
– A4 4.5ns clock access time (117 MHz)
Commercial and Industrial:
– 5 5ns clock access time (100 MHz)
– 6 6ns clock access time (83 MHz)
– 7 7ns clock access time (66 MHz)
◆◆
◆◆
◆Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32D7LG-XX)
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆Operates with a single 3.3V power supply (+10/-5%)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP)
◆◆
◆◆
◆Green parts available, see ordering information
Pin Description Summary
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
64K x 32
3.3V Synchronous SRAM
Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V632
Description
The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32
with full support of the Pentium™ and PowerPC™ processor interfaces.
The pipelined burst architecture provides cost-effective 3-1-1-1 second-
ary cache performance for processors up to 117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V632 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address counter
accepts the first cycle address from the processor, initiating the access
sequence. The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode operation is
selected (ADV=LOW), the subsequent three cycles of output data will be
available to the user on the next three rising clock edges. The order of these
three addresses will be defined by the internal burst counter and the LBO
input pin.
The IDT71V632 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density
in both desktop and notebook applications.
A
0
A–
51
stupnIsserddAtupnIsuonorhcnyS
EC elbanEpihCtupnIsuonorhcnyS
SC
0
,SC
1
stceleSspihCtupnIsuonorhcnyS
EO elbanEtuptuOtupnIsuonorhcnysA
WG elbanEetirWlabolGtupnIsuonorhcnyS
EWB elbanEetirWetyBtupnIsuonorhcnyS
WB
,1
WB
,2
WB
,3
WB
4
stceleSetirWetyBlaudividnItupnIsuonorhcnyS
KLCkcolCtupnIA/N
VDA ecnavdAsserddAtsruBtupnIsuonorhcnyS
CSDA )rellortnoCehcaC(sutatSsserddAtupnIsuonorhcnyS
PSDA )rossecorP(sutatSsserddAtupnIsuonorhcnyS
OBL redrOtsruBdevaelretnI/raeniLtupnICD
ZZedoMpeelStupnIsuonorhcnysA
O/I
0
O/I–
13
tuptuO/tupnIataDO/IsuonorhcnyS
V
DD
V,
QDD
V3.3rewoPA/N
V
SS
V,
QSS
dnuorGO/I,dnuorGyarrArewoPA/N
10lbt9163
6.42
2
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
lobmySnoitcnuFniPO/IevitcAnoitpircseD
A
0
A–
51
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EC .
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4
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0
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0
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1
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1
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1
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EO elbanEtuptuOIWOLnehW.elbanetuptuosuonorhcnysA EO erasrevirdtuptuoatadehtWOLsi nehW.detcelesoslasipihcehtfisnipO/Iehtnodelbane EO O/IehtHGIHsi
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V
SS
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20lbt9163
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
A
0
–A
15
ADDRESS
REGISTER
CLR
A
1
*
A
0
*
16
2
16
A
2
–A
15
64K x 32
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
, A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
32 32
ADSP
ADV
CLK
ADSC
CS0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
8
8
8
8
GW
CE
BWE
LBO
I/O
0
–I/O
31
OE
DATA INPUT
REGISTER
32
OUTPUT
BUFFER
OUTPUT
REGISTER
Powerdown
ZZ
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CE
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
3619 drw 01
.
6.42
4
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
lobmySretemaraP
)1(
snoitidnoC.xaMtinU
C
NI
ecnaticapaCtupnIV
NI
Vd3=6Fp
C
O/I
ecnaticapaCO/IV
TUO
Vd3=7Fp
60lbt9163
Absolute Maximum Ratings(1)
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD, VDDQ and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
lobmySgnitaReulaVtinU
V
MRET
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htiwegatloVlanimreT DNGottcepseR 6.4+ot5.0–V
V
MRET
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htiwegatloVlanimreT DNGottcepseR Vot5.0–
DD
5.0+V
T
A
erutarepmeTgnitarepO07+ot0
o
C
T
SAIB
saiBrednUerutarepmeT521+ot55–
o
C
T
GTS
erutarepmeTegarotS521+ot55–
o
C
P
T
noitapissiDrewoP0.1W
I
TUO
tnerruCtuptuOCD05Am
50lbt9163
Recommended DC Operating
Conditions
NOTES:
1. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
lobmySretemaraP.niM.xaMtinU
V
DD
egatloVylppuSeroC531.336.3V
V
QDD
egatloVylppuSO/I531.336.3V
V
,SS
V
QSS
dnuorG00V
V
HI
stupnI—egatloVhgiHtupnI0.20.5
)1(
V
V
HI
O/I—egatloVhgiHtupnI0.2V
QDD
3.0+
)2(
V
V
LI
egatloVwoLtupnI3.0–
)3(
8.0V
40lbt9163
Recommended Operating
Temperature and Supply Voltage
edarGerutarepmeTV
SS
V
DD
V
QDD
laicremmoCC°07+otC°0V0%5-/01+V3.3%5-/01+V3.3
lairtsudnIC°58+otC°04–V0%5-/01+V3.3%5-/01+V3.3
30lbt9163
6.42
5
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration
Top View TQFP
NOTES:
1. Pin 14 can either be directly connected to VDD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
NC
L
BO
A14
A13
A12
A11
A10
VDD
VSS
A0
A1
A2
A3
A4
A5
NC
I/O31
I/O30
VDDQ
VSSQ
I/O29
I/O28
I/O27
I/O26
VSSQ
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSSQ
I/O21
I/O20
I/O19
I/O18
VSSQ
VDDQ
I/O17
I/O16
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O14
VDDQ
VSSQ
I/O13
I/O12
I/O11
I/O10
VSSQ
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ
(2)
I/O7
I/O6
VDDQ
VSSQ
I/O5
I/O4
I/O3
I/O2
VSSQ
VDDQ
I/O1
I/O0
NC
PKG100
3619 drw 02
VDD/NC
(1)
I/O15
A15
6.42
6
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,2)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
noitarepO sserddA desU EC SC 0SC 1PSDACSDAVDAWGEWBWB
X
EO
)3(
KLCO/I
nwoDrewoP,elcyCdetceleseDenoN HXXXLXXXXX↑Z-iH
nwoDrewoP,elcyCdetceleseDenoN LXHLXXXXXX↑Z-iH
nwoDrewoP,elcyCdetceleseDenoN LLXLXXXXXX↑Z-iH
nwoDrewoP,elcyCdetceleseDenoN LXHXLXXXXX↑Z-iH
nwoDrewoP,elcyCdetceleseDenoN LLXXLXXXXX↑Z-iH
tsruBnigeB,elcyCdaeRlanretxE LHLLXXXXXL↑D
TUO
tsruBnigeB,elcyCdaeRlanretxE LHLLXXXXXH↑Z-iH
tsruBnigeB,elcyCdaeRlanretxE LHLHLXHHXL↑D
TUO
tsruBnigeB,elcyCdaeRlanretxE LHLHLXHLHL↑D
TUO
tsruBnigeB,elcyCdaeRlanretxE LHLHLXHLHH↑Z-iH
tsruBnigeB,elcyCetirWlanretxE LHLHLXHLLX↑D
NI
tsruBnigeB,elcyCetirWlanretxE LHLHLXLXXX↑D
NI
tsruBeunitnoC,elcyCdaeRtxeN XXXHHLHHXL↑D
TUO
tsruBeunitnoC,elcyCdaeRtxeN XXXHHLHHXH↑Z-iH
tsruBeunitnoC,elcyCdaeRtxeN XXXHHLHXHL↑D
TUO
tsruBeunitnoC,elcyCdaeRtxeN XXXHHLHXHH↑Z-iH
tsruBeunitnoC,elcyCdaeRtxeN HXXXHLHHXL↑D
TUO
tsruBeunitnoC,elcyCdaeRtxeN HXXXHLHHXH↑Z-iH
tsruBeunitnoC,elcyCdaeRtxeN HXXXHLHXHL↑D
TUO
tsruBeunitnoC,elcyCdaeRtxeN HXXXHLHXHH↑Z-iH
tsruBeunitnoC,elcyCetirWtxeN XXXHHLHLLX↑D
NI
tsruBeunitnoC,elcyCetirWtxeN XXXHHLLXXX↑D
NI
tsruBeunitnoC,elcyCetirWtxeN HXXXHLHLLX↑D
NI
tsruBeunitnoC,elcyCetirWtxeN HXXXHLLXXX↑D
NI
tsruBdnepsuS,elcyCdaeRtnerruC XXXHHHHHXL↑D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC XXXHHHHHXH↑Z-iH
tsruBdnepsuS,elcyCdaeRtnerruC XXXHHHHXHL↑D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC XXXHHHHXHH↑Z-iH
tsruBdnepsuS,elcyCdaeRtnerruC HXXXHHHHXL↑D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC HXXXHHHHXH↑Z-iH
tsruBdnepsuS,elcyCdaeRtnerruC HXXXHHHXHL↑D
TUO
tsruBdnepsuS,elcyCdaeRtnerruC HXXXHHHXHH↑Z-iH
tsruBdnepsuS,elcyCetirWtnerruC XXXHHHHLLX↑D
NI
tsruBdnepsuS,elcyCetirWtnerruC XXXHHHLXXX↑D
NI
tsruBdnepsuS,elcyCetirWtnerruC HXXXHHHLLX↑D
NI
tsruBdnepsuS,elcyCetirWtnerruC HXXXHHLXXX↑D
NI
70lbt9163
6.42
7
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
noitarepO
)2(
EO ZZsutatSO/IrewoP
daeRLLO/I(tuOataD
0
O/I-
13
)evitcA
daeRHL Z-hgiHevitcA
etirWXL O/I(nIataD—Z-hgiH
0
O/I-
13
)evitcA
detceleseDXL Z-hgiHybdnatS
peelSXH Z-hgiHpeelS
90lbt9163
noitarepO WGEWBWB
1
WB
2
WB
3
WB
4
daeR HHXXXX
daeR HLHHHH
setyBllaetirW LXXXXX
setyBllaetirW HLLLLL
1etyBetirW
)2(
HLLHHH
2etyBetirW
)2(
HLHLHH
3etyBetirW
)2(
HLHHLH
4etyBetirW
)2(
HLHHHL
80lbt9163
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Asynchronous Truth Table(1)
Synchronous Write Function Truth Table(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS01001110
sserddAdrihT10110001
sserddAhtruoF
)1(
11 10 01 00
01lbt9163
1ecneuqeS2ecneuqeS3ecneuqeS4ecneuqeS
1A0A1A0A1A0A1A0A
sserddAtsriF 00011011
sserddAdnoceS01101100
sserddAdrihT10110001
sserddAhtruoF
)1(
11 00 01 10
11lbt9163
6.42
8
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
4AS
)4,3(
5S6S7S
lobmySretemaraPsnoitidnoCtseT.l'moC.dnI.l'moC.dnI.l'moC.dnI.l'moC.dnI
t
inU
I
DD
rewoPgnitarepO tnerruCylppuS ,nepOstuptuO,detceleSeciveD
V
DD
V,.xaM=
NI
> V
HI
ro<V
LI
,
f=f
XAM
)2(
022— 002002081081061061Am
I
BS
rewoPybdnatS tnerruCylppuS ,nepOstuptuO,detceleseDeciveD
V
DD
V,.xaM=
NI
> V
HI
ro<V
LI
,
f=f
XAM
)2(
07—565606065555Am
I
1BS
rewoPybdnatSlluF tnerruCylppuS ,nepOstuptuO,detceleseDeciveD
V
DD
V,.xaM=
NI
> V
DH
ro<V
DL
,
0=f
)2(
51— 515151515151Am
I
ZZ
edoMpeelSlluF tnerruCylppuSrewoP ZZ>V
DH
V,
DD
.xaM=01— 010101010101Am
31lbt9163
V
DDQ
/2
50Ω
I/O
Z
0
= 50Ω
3619 drw 03
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1) (VHD = VDDQ – 0.2V, VLD = 0.2V)
Figure 3. Lumped Capacitive Load, Typical Derating
* Including scope and jig capacitance.
Figure 2. High-Impedence Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +10/-5%)
AC Test Loads
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
3619 drw 05
351Ω
+3.3V
317Ω
5pF*
I/O
3619 drw 04
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. SA4 speed grade corresponds to a tCD of 4.5 ns.
4. 0°C to +70°C temperature range only.
lobmySretemaraPsnoitidnoCtseT.niM.xaMtinU
I|
LI
|tnerruCegakaeLtupnIV
DD
V,.xaM=
NI=
VotV0
DD
—5Aµ
I|
ZZL
|dnaZZ OBL tnerruCegakaeLtupnI
)1(
V
DD
V,.xaM=
NI=
VotV0
DD
—03Aµ
I|
OL
|
tnerruCegakaeLtuptuO EC > V
HI
ro EO > V
HI
V,
TUO
VotV0=
DD
V,
DD
.xaM= —5Aµ
V
LO
)V3.3(egatloVwoLtuptuOI
LO
V,Am5=
DD
.niM=—4.0V
V
HO
)V3.3(egatloVhgiHtuptuOI
HO
V,Am5–=
DD
.niM=4.2—V
21lbt9163
Figure 1. AC Test Load
AC Test Conditions
sleveLesluPtupnI
semiTllaF/esiRtupnI
sleveLecnerefeRgnimiTtupnI
sleveLecnerefeRgnimiTtuptuO
daoLtseTCA
V0.3ot0
sn2
V5.1
V5.1
2dna1serugiFeeS
41lbt9163
6.42
9
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
lobmySretemaraP
4AS236V17
)6,5(
5S236V176S236V177S236V17
tinU
.niM.xaM.niM.xaM.niM.xaM.niM.xaM
SRETEMARAPKCOLC
t
CYC
emiTelcyCkcolC5.8
____
01
____
21
____
51
____
sn
t
HC
)1(
htdiWesluPhgiHkcolC5.3
____
4
____
5.4
____
5
____
sn
t
LC
)1(
htdiWesluPwoLkcolC5.3
____
4
____
5.4
____
5
____
sn
SRETEMARAPTUPTUO
t
DC
ataDdilaVothgiHkcolC
____
5.4
____
5
____
6
____
7sn
t
CDC
egnahCataDothgiHkcolC5.1
____
5.1
____
2
____
2
____
sn
t
ZLC
)2(
evitcAtuptuOothgiHkcolC0
____
0
____
0
____
0
____
sn
t
ZHC
)2(
Z-hgiHataDothgiHkcolC5.145.1 52526sn
t
EO
emiTsseccAelbanEtuptuO
____
4
____
5
____
5
____
6sn
t
ZLO
)2(
evitcAataDotwoLelbanEtuptuO0
____
0
____
0
____
0
____
sn
t
ZHO
)2(
Z-hgiHataDothgiHelbanEtuptuO
____
4
____
4
____
5
____
6sn
SEMITPUTES
t
AS
emiTputeSsserddA2.2
____
5.2
____
5.2
____
5.2
____
sn
t
SS
emiTputeSsutatSsserddA2.2
____
5.2
____
5.2
____
5.2
____
sn
t
DS
emiTputeSniataD2.2
____
5.2
____
5.2
____
5.2
____
sn
t
WS
emiTputeSetirW2.2
____
5.2
____
5.2
____
5.2
____
sn
t
VAS
emiTputeSecnavdAsserddA2.2
____
5.2
____
5.2
____
5.2
____
sn
t
CS
emiTputeStceleS/elbanEpihC2.2
____
5.2
____
5.2
____
5.2
____
sn
SEMITDLOH
t
AH
emiTdloHsserddA5.0
____
5.0
____
5.0
____
5.0
____
sn
t
SH
emiTdloHsutatSsserddA5.0
____
5.0
____
5.0
____
5.0
____
sn
t
DH
emiTdloHnIataD5.0
____
5.0
____
5.0
____
5.0
____
sn
t
WH
emiTdloHetirW5.0
____
5.0
____
5.0
____
5.0
____
sn
t
VAH
emiTdloHecnavdAsserddA5.0
____
5.0
____
5.0
____
5.0
____
sn
t
CH
emiTdloHtceleS/elbanEpihC5.0
____
5.0
____
5.0
____
5.0
____
sn
SRETEMARAPNOITARUGIFNOCDNAEDOMPEELS
t
WPZZ
htdiWesluPZZ001
____
001 —001
____
001
____
sn
t
RZZ
)3(
emiTyrevoceRZZ001
____
001—001
____
001
____
sn
t
GFC
)4(
emiTpu-teSnoitarugifnoC43
____
04—05
____
05
____
sn
51lbt9163
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. The 71V632SA4 speed grade corresponds to a tCD of 4.5ns.
6. 0°C to +70°C temperature range only.
AC Electrical Characteristics
(VDD, VDDQ = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
6.42
10
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCHZ
tSA
tSC
tHS
GW , BW E, BW x
tSW
tCL
tSAV
tHW
tHAV
CLK
A DSP
A DSC
(1)
ADDRESS
tCYC
tCH
tHA
tHC
tOE
tOHZ
OE tCD
tOLZ
O1(Ax)
DATAOUT
tCDC
O1(Ay) O3(Ay) O2(Ay)O2(Ay)
tCLZ
ADV
ADV inserts a wait-state
CE, CS1
(Note 3)
3619 drw 06
Pipelined
Read Burst Pipelined Read
Output
Disabled
Ax Ay
tSS
O1(Ay)
(Burst wraps around
to its initial state)
O4(Ay)
6.42
11
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresss Az; O2(Az)
represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
O1(Az)
3619drw07
SingleReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
6.42
12
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
ADDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DATA
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
GW
t
SW
(Note3)
I2(Az)
BurstWrite
BurstRead
3104drw08
BurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVsuspendsburst)
I1(Ay)
BWEisignoredwhenADSPinitiatesburs
t
t
SC
.
t
HW
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
13
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ADDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
WriteBurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
BWE
t
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)
3104drw09
I4(Ay)
I3(Ay)
t
SC
BWEisignoredwhenADSPinitiatesburs
t
BWxisignoredwhenADSPinitiatesburs
t
I3(Az)
O3(Aw)
t
HW
t
HW
6.42
14
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
NOTES:
1. Device must power up in deselected Mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCYC
tSS tCLtCH
tHA
tSA
tSC tHC
tOE
tOLZ
tHS
CLK
ADSP
ADS
C
ADDRESS
GW
CE, CS1
ADV
DATAOUT
OE
ZZ
Single Read Snooze Mode
tZZPW
3104 drw 10
O1(Ax)
Ax
(Note 4)
tZZR
Az
6.42
15
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW, BWE, BWx
CE, CS1
CS0
ADDRESS
ADSC
DATAOUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
3619 drw 11
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
6.42
16
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW
CE, CS1
CS0
ADDRESS
ADSC
DATAIN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
3619 drw 12
,
Non-Burst Write Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
17
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
100-Pin TQFP (PKG100)
S
Power
X
Speed
XX
Package
PF
XXXX
A4
5
6
7
Synchronous Access Time of Nanoseconds
3619 drw 13
Device
Type
71V632 64K x 32 Pipelined Burst Synchronous SRAM
,
X
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
X
Green
G
Tray
Tape and Reel
Blank
8
X
(1)
(2)
(3)
NOTES:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
3. Commercial only.
Part Number Speed in Megahertz t
CD
Parameter Clock Cycle Time
71V632SA4PF 117 MHz 4.5 ns 8.5 ns
71V632S5PF 100 MHz 5 ns 10 ns
71V632S6PF 83 MHz 6 ns 12 ns
71V632S7PF 66 MHz 7 ns 15 ns
3619 tbl 16
6.42
18
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Datasheet Document History
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9/9/99 Updated to new format
Pg. 1, 8, 9, 17 Revised speed offerings to 66–117MHz
Pg. 15, 16 Added non-burst read and write cycle timing diagrams
Pg. 18 Added Datasheet Document History
09/30/99 Pg. 1, 4, 8, 9, 17 Added industrial temperature range offerings
04/04/00 Pg. 17 Added 100pinTQFP package Diagram Outline
08/09/00 Not recommended for new designs
08/17/01 Removed “Not recommended for new designs” from the background on the datasheet
02/28/07 Pg. 18 Added Z generation die step to data sheet ordering information.
10/16/08 Pg. 18 Removed “IDT” from orderable part number.
05/27/10 Pg. 17 Added "Restricted hazardous substance device" to the ordering information
02/24/17 Pg. 1 Removed Z from device part number
Added green availability to features
Pg. 5 Update PK100-1 to package code PKG100 and restore overbars
Pg. 14 Restored Sleep (ZZ) Timing Waveform
Pg. 16 Restored Non-Burst Write Cycle Timing Waveform
Removed PSC Package Diagram
Pg. 17 Restored Ordering Information: Added Green,Tape & Reel, Tray and footnote indicators
Removed Z Die Stepping indicator in Ordering Information
CORPORATE HEADQUARTERS for SALES:
6024 Silver Creek Valley Road 800-345-7015 or
San Jose, CA 95138 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
sramhelp@idt.com
408-284-4532
