LT8494
1
8494fa
For more information www.linear.com/LT8494
INPUT VOLTAGE (V)
0
12
24
36
48
60
0
5
10
15
20
SUPPLY CURRENT (µA)
8494 TA01b
TYPICAL APPLICATION
FEATURES DESCRIPTION
SEPIC/Boost DC/DC
Converter with 2A, 70V Switch,
and 7µA Quiescent Current
The LT
®
8494 is an adjustable frequency (250kHz to
1.5MHz) monolithic switching regulator. Quiescent cur-
rent can be less than 7µA when operating and is ~0.3µA
when SWEN is low. The LT8494 can be configured as
either a SEPIC, boost or flyback converter.
The low ripple Burst Mode operation maintains high
efficiency at low output current while keeping output rip-
ple below 10mV. Dual supply pins (VIN and BIAS) allow
the part to automatically operate from the most efficient
supply. Input supply voltage can be up to 60V for SEPIC
topologies and up to 32V (with ride-through up to 60V)
for boost and flyback topologies. After start-up, battery
life is extended since the part can draw current from its
output (BIAS) even when VIN voltage drops below 2.5V.
Using a resistor divider on the SWEN pin provides a pro-
grammable undervoltage lockout (UVLO) for the con-
verter. A power good flag signals when VOUT reaches 92%
of the programmed output voltage.
Additional features such as frequency foldback and soft-
start are integrated. The LT8494 is available in 20-lead
QFN and 20-lead TSSOP packages with exposed pads
for low thermal resistance. Fault tolerance in the TSSOP
allows for adjacent pin shorts or an open without raising
the output voltage above its programmed value.
450kHz, 5V Output SEPIC Converter No-Load Supply Current Efficiency
APPLICATIONS
n Low Ripple Burst Mode
®
Operation:
n 7µA IQ at 12VIN to 5VOUT
n Output Ripple (<10mV Typ.)
n Dual Supply Pins:
n Improves Efficiency
n Reduces Minimum Supply Voltage to ~1V After
n Start-Up to Extend Battery Life
n Wide Input Voltage Range of ~1V to 60V (2.5V to
32V for Start-Up)
n PG Functional for Input Supply Down to 1.3V
n FMEA Fault Tolerant in TSSOP Package
n Fixed Frequency PWM, SEPIC/BOOST/FLYBACK
Topologies
n NPN Power Switch: 2A/70V
n Programmable Switching Frequency: 250kHz to 1.5MHz
n UVLO Programmable on SWEN Pin
n Soft-Start Programmable with One Capacitor
n Small 20-Lead QFN or 20-Lead TSSOP Packages
n Automotive ECU Power
n Power for Portable Products
n Industrial Supplies
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks of
Analog Devices, Inc. All other trademarks are the property of their respective owners.
2.2µF
15µH •
•
15µH
1µF
VIN
3V TO 60V
VOUT
5V
0.35A (VIN
= 3V)
0.6A (VIN = 5V)
1.0A (VIN
> 12V)
SW BIAS
FB
GND
VIN
SWEN
RT
PG
SS
1M
316k
8494 TA01a
169k
LT8494
47µF
×2
4.7pF
4.7µF
V
IN
V
IN
V
IN
= 5V
LOAD CURRENT (A)
0.0
0.2
0.4
0.6
0.8
1.0
60
65
70
75
80
85
90
EFFICIENCY (%)
8494 TA01c
LT8494
2
8494fa
For more information www.linear.com/LT8494
ABSOLUTE MAXIMUM RATINGS
VIN, BIAS Voltage ......................................................60V
SWEN Voltage ........................................................... 60V
FB Voltage .................................................................60V
SW Voltage ...............................................................70V
PG Voltage ..................................................................6V
RT Voltage ..................................................................6V
SS Voltage ..................................................................3V
Operating Junction Temperature Range
LT8494E, LT8494I (Notes 2, 3) .......... –40°C to 125°C
LT8494H (Notes 2, 3) ........................ –40°C to 150°C
Storage Temperature Range .............. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package .......................................................300°C
(Note 1)
ORDER INFORMATION
20 19 18 17 16
678
TOP VIEW
21
GND
UF PACKAGE
20-LEAD (4mm
×
4mm) PLASTIC QFN
9 10
5
4
3
2
1
11
12
13
14
15
SS
RT
GND
GND
NC
GND
GND
GND
SW
GND
PG
NC
NC
FB
BIAS
SWEN
NC
NC
GND
VIN
θJA = 47°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
BIAS
FB
FB
NC
NC
NC
PG
SS
NC
RT
SW
NC
VIN
NC
GND
NC
GND
NC
SWEN
NC
21
GND
θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8494EUF#PBF LT8494EUF#TRPBF 8494 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LT8494IUF#PBF LT8494IUF#TRPBF 8494 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LT8494EFE#PBF LT8494EFE#TRPBF LT8494FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8494IFE#PBF LT8494IFE#TRPBF LT8494FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8494HFE#PBF LT8494HFE#TRPBF LT8494FE 20-Lead Plastic TSSOP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LT8494#orderinfo
LT8494
3
8494fa
For more information www.linear.com/LT8494
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VSWEN = 12V, VBIAS = 5V, unless otherwise noted (Note 2).
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum VIN Operating Voltages VBIAS < 2.5V
VBIAS ≥ 2.5V
l
l
2.4 2.5
0
V
V
Minimum BIAS Operating Voltages VIN < 2.5V
VIN ≥ 2.5V
l
l
2.4 2.5
0
V
V
Power Switch Driver (PSD) Overvoltage Threshold
(Note 4)
VIN or BIAS Rising
VIN or BIAS Falling
l
l
32.1
32
34
33.9
36.5
36.4
V
V
Power Switch Driver (PSD) Overvoltage Threshold
Hysteresis (Note 4)
100 mV
Quiescent Current from VIN VSWEN = 0V
VSWEN = 5V, VFB = 1.25V
VSWEN = 5V, VFB = 1.25V (LT8494E, LT8494I)
VSWEN = 5V, VFB = 1.25V (LT8494H)
l
l
0.3
3.0
3.0
3.0
0.9
4.8
6.2
8.0
µA
µA
µA
µA
Quiescent Current from BIAS VSWEN = 0V
VSWEN = 5V, VFB = 1.25V
VSWEN = 5V, VFB = 1.25V (LT8494E, LT8494I)
VSWEN = 5V, VFB = 1.25V (LT8494H)
l
l
0.07
1.7
1.7
1.7
0.5
2.8
3.5
10
µA
µA
µA
µA
BIAS to VIN Comparator Threshold VBIAS-VIN, VBIAS Rising, VIN = 12V
VBIAS-VIN, VBIAS Falling, VIN = 12V
Hysteresis (Rising-Falling Threshold)
l
l
l
0.55
0.17
0.20
0.9
0.37
0.53
1.2
0.57
0.8
V
V
V
Feedback Voltage l1.178 1.202 1.230 V
FB Pin Bias Current (Note 7) VFB = 1.202V 0.1 20 nA
FB Voltage Line Regulation 5V ≤ VIN ≤ 32V, BIAS = 5V
5V ≤ VIN ≤ 32V, BIAS = 0V
0.2
0.2
10
10
m%/V
m%/V
Minimum Switch Off-Time 70 ns
Minimum Switch On-Time 95 ns
Switching Frequency RT = 68.1k
RT = 324k
l
l
0.92
219
1.0
250
1.06
280
MHz
kHz
Switch Current Limit at Minimum Duty Cycle (Note 5) l2.1 2.55 2.95 A
Switch Current Limit at Maximum Duty Cycle (Note 6) l1.3 1.85 2.4 A
Switch VCESAT ISW = 1.2A 340 mV
Switch Leakage Current (Note 7) VSW = 12V, VSWEN = 0V 0.01 1 μA
Soft-Start Charging Current (Note 7) VSS = 100mV l5.2 8.2 12.2 μA
SWEN Pin Current (Note 7) VSWEN = 1.2V
VSWEN = 5V
VSWEN = 12V
0
35
240
25
200
550
nA
nA
nA
SWEN Rising Voltage Threshold l0.9 1 1.1 V
SWEN Voltage Hysteresis 30 mV
PG Threshold as % of VFB Regulation Voltage VFB Rising
VFB Falling
l
l
86
82
92
88
97
93
%
%
PG Hysteresis 46 mV
PG Output Voltage Low ISINK = 1.25mA
ISINK = 100μA, VBIAS = 0V, VIN = 1.3V
ISINK = 100μA, VBIAS = 1.3V, VIN = 0V
l
l
l
33
15
15
150
150
150
mV
mV
mV
PG Leakage Current VPG = 5V (LT8494E, LT8494I)
VPG = 5V (LT8494H)
l
l
0
0
0.3
1.0
μA
μA
LT8494
4
8494fa
For more information www.linear.com/LT8494
TYPICAL PERFORMANCE CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Voltages are with respect to GND pin unless
otherwise noted.
Note 2: The LT8494E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8494I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT8494H is guaranteed over the full
–40°C to 150°C operating junction temperature range. Operation lifetime is
derated at junction temperatures greater than 125°C.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 4: See Power Supplies and Operating Limits in the Applications
Information section for more details.
Note 5: Current limit guaranteed by design and/or correlation to static test.
Slope Compensation reduces current limit at higher duty cycles.
Note 6: Max duty cycle current limit measured at 1MHz switching
frequency.
Note 7: Polarity specification for all currents into pins is positive. All
voltages are referenced to GND unless otherwise specified.
ELECTRICAL CHARACTERISTICS
No-Load Supply Current Maximum Load Current Load Regulation
TA = 25°C unless otherwise specified.
FRONT PAGE APPLICATION
TYPICAL
MINIMUM
V
IN
(V)
0
12
24
36
48
60
0.0
0.5
1.0
1.5
2.0
2.5
LOAD CURRENT (A)
8494 G05
FRONT PAGE APPLICATION
V
IN
=12V
TEMPERATURE (°C)
–50
–10
30
70
110
150
0
20
40
60
80
100
SUPPLY CURRENT (µA)
8494 G04
Switching Waveforms,
BurstMode Operation
Transient Load Response, Load
Current is Stepped from 20mA
(Burst Mode Operation) to 220mA
Switching Waveforms, Full
Frequency Continuous Operation
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
I
LOAD
= 20mA
10µs/DIV
8494 G16
VSW
10V/DIV
IL
0.5A/DIV
VOUT
5mV/DIV
FRONT PAGE APPLICATION
VIN = 12V
V
OUT
= 5V
500µs/DIV
8494 G17
VOUT
100mV/DIV
IL
0.5A/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
I
LOAD
= 0.5A
1µs/DIV
8494 G18
VSW
10V/DIV
IL
0.5A/DIV
VOUT
5mV/DIV
V
IN
=12V
FRONT PAGE APPLICATION
REFERENCED TO V
OUT
AT 100mA LOAD
LOAD CURRENT (mA)
0
200
400
600
800
1000
–0.15
–0.10
–0.05
0.00
0.05
0.10
0.15
LOAD REGULATION (%)
8495 G18
LT8494
5
8494fa
For more information www.linear.com/LT8494
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Current Limit at 500kHz
Switch Current Limit at Minimum
Duty Cycle
Switch VCESAT
Minimum Switch On-Time
Feedback Voltage Oscillator Frequency
TA = 25°C unless otherwise specified.
TEMPERATURE (°C)
–50
SWITCH ON-TIME (ns)
140
120
80
40
100
60
20
050
8494 G13
1500 100
TEMPERATURE (°C)
–50
SWITCH OFF-TIME (ns)
180
160
140
120
80
40
100
60
20
050
8494 G14
1500 100
TEMPERATURE (°C)
–50
FREQUENCY (MHz)
1.5
0.5
1.0
0.0 50
8494 G11
1500 100
RT = 68.1k
RT = 324k
SWITCHING FREQUENCY (kHz)
1200
1000
600
400
200
800
0
8494 G12
FB VOLTAGE (V)
0 1.00.7 1.20.50.2
RT = 68.1k
RT = 324k
Frequency Foldback Minimum Switch Off-Time
DUTY CYCLE (%)
10
20
30
40
50
60
70
80
90
0.0
0.5
1.0
1.5
2.0
2.5
3.0
SWITCH CURRENT LIMIT (A)
8494 G06
TEMPERATURE (°C)
–50
SWITCH CURRENT LIMIT (A)
3.0
2.0
1.0
2.5
1.5
0.5
050
8494 G07
1500 100
SWITCH CURRENT (A)
0
SWITCH VCESAT (mV)
600
400
200
500
300
100
01.0
8494 G08
2.00.5 1.5
TEMPERATURE (°C)
–50
FB VOLTAGE (V)
1.23
1.21
1.19
1.22
1.20
1.18 50
8494 G09
1500 100
Transient Load Response, Load
Current is Stepped from 300mA
to 500mA
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
500µs/DIV
8494 G19
VOUT
50mV/DIV
IL
0.5A/DIV
LT8494
6
8494fa
For more information www.linear.com/LT8494
TYPICAL PERFORMANCE CHARACTERISTICS
FB Pin Current
Quiescent Current
PG Output Voltage
vs Supply Voltage
SWEN Pin Current
Pin Current
Internal UVLO PG Pin Current vs Supply Voltage
TA = 25°C unless otherwise specified.
TEMPERATURE (°C)
–50
VIN/BIAS VOLTAGE (V)
2.50
2.40
2.45
2.35
2.30 50
8494 G20
1500 100
VIN/BIAS FALLING
VIN/BIAS RISING
FB PIN CURRENT (µA)
8494 G24
FB VOLTAGE (V)
0
0.001
0.01
0.1
1
10
100
1000
5030 60402010
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (µA)
4
2
5
3
0
1
50
8494 G27
150
0 100
CURRENT INTO BIAS
VIN = 12V
VBIAS = VSWEN = 5V
VFB = 1.25V
CURRENT INTO VIN
VIN VOLTAGE (V)
0
PG PIN CURRENT (mA)
20
2
18
14
10
6
16
12
8
4
0
8494 G22
52 41 3
PG = 0.4V
VIN = BIAS, SWEN = 0
VIN = BIAS = SWEN
PG OUTPUT VOLTAGE (V)
3
2
1
0
8494 G25
VIN/BIAS VOLTAGE (V)
0 321
10k PULL-UP FROM VIN TO PG
SWEN PIN CURRENT (nA)
400
350
300
250
200
150
100
50
0
8494 G23
SWEN PIN VOLTAGE (V)
0 5030 60402010
TEMPERATURE (°C)
–50
CURRENT INTO PIN (nA)
60
20
40
050
8494 G26
150
0 100
IFB
VIN = 1.25V
VSWEN = 1.2V
ISWEN
Overvoltage Lockout
TEMPERATURE (°C)
–50
VIN OR BIAS VOLTAGE (V)
35.5
34.5
33.5
35.0
34.0
33.0 50
8494 G15
1500 100
VIN OR BIAS FALLING
VIN OR BIAS RISING
LT8494
7
8494fa
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SS (Pin 1/Pin 8): Soft-Start Pin. Place a soft-start capaci-
tor on this pin. Upon start-up, the SS pin will be charged
by a (nominally) 256k resistor to about 2.1V.
RT (Pin 2/Pin 10): Oscillator Frequency Set Pin. Place a
resistor from this pin to ground to set the internal oscil-
lator frequency. Minimize capacitance on this pin. See the
Applications Information section for more details.
GND (Pins 3, 4, 9, 11, 13, 14, 15, Exposed Pad 21/Pins
14, 16, Exposed Pad 21): Ground. Solder all pins and
the exposed pad directly to the local ground plane. The
exposed pad metal of the package provides both electrical
contact to ground and good thermal contact to the printed
circuit board.
NC (Pins 5, 7, 8, 18, 19/4, 5, 6, 9, 11, 13, 15, 17, 19):
NC pins are not connected to internal circuitry. Some NC
pins in the TSSOP package must be left floating to ensure
FMEA fault tolerance (see Applications Informations sec-
tion for details).
SWEN (Pin 6/Pin 12): Switch Enable Detect Pin. This pin
enables/disables the switching regulator and soft-start. A
resistor divider can be connected to SWEN to perform an
undervoltage lockout function.
V
IN
(Pin 10/Pin 18): Supply Input Pin. This pin is typically
connected to the input of the DC/DC converter. Must be
locally bypassed.
SW (Pin 12/Pin 20): Switch Pin. This is the collector of
the internal NPN power switch. Minimize trace area con-
nected to this pin to minimize EMI.
BIAS (Pin 16/Pin 1): Supply Input Pin. This pin is typi-
cally connected to the output of the DC/DC converter in
cases where VIN can be higher than VOUT. Must be locally
bypassed.
FB (Pin 17/Pin 2, 3): Output Voltage Feedback Pin. The
LT8494 regulates the FB pin to 1.202V. Connect a resis-
tor divider between the output, FB and GND to set the
regulated output voltage.
PG (Pin 20/Pin 7): The PG pin is the open-drain output of
an internal comparator. PG remains low until the FB pin
is above 92% of the regulation voltage, and there are no
fault conditions. See the Applications Information section
for more details.
PIN FUNCTIONS
(QFN/TSSOP)
LT8494
8
8494fa
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BLOCK DIAGRAM
+
–
+
–
VIN
2.4V
+
–
DIE
TEMP
165°C
2.15V
1.10V
1.00V
OTHERS
+
–
+
–
SW
PG
BIAS
GND
SWEN
2.4V
34V
1.00V
Q
256k
S
R
OVP
ILIMIT
VC_LIMITER
CHIP
SHUTDOWN
SR2
R Q
S
SR1
A2
2.1V
SS
DISABLE PSD
+
–
+
–
SUPPLY
SELECT
LOGIC
VOLTAGE
REFS
Burst
Mode
DETECT
QUADRATIC
RAMP
GENERATOR
FREQUENCY
FOLDBACK
CHIP
SHUTDOWN
1.10V
LOW POWER MODE
SOFT-
START
34V
+
–
100mV
1.202V
+
–
RT
FB
PGOOD
A3
VC
+
–
A1
8494 BD
+
–
POWER
SWITCH
DRIVER
Q1
ADJUSTABLE
OSCILLATOR
LT8494
9
8494fa
For more information www.linear.com/LT8494
OPERATION
The LT8494 is a constant-frequency, current mode
SEPIC/boost/flyback regulator. Operation can be best
understood by referring to the Block Diagram. In the Block
Diagram, the adjustable oscillator, with frequency set by
the external RT resistor, enables an RS latch, turning on
the internal power switch. An amplifier and comparator
monitor the switch current flowing through an internal
sense resistor, turning the switch off when this current
reaches a level determined by the voltage at VC. An error
amplifier adjusts the VC voltage by measuring the output
voltage through an external resistor divider tied to the FB
pin. If the error amplifier’s output voltage (VC) increases,
more current is delivered to the output; if the VC voltage
decreases, less current is delivered. An active clamp on
the VC voltage provides current limit. An internal regulator
provides power to the control circuitry.
In order to improve efficiency, the NPN power switch
driver (see Block Diagram) supplies NPN base current
from whichever of VIN and BIAS has the lower supply
voltage. However, if either of them is below 2.4V or above
34V (typical values), the power switch draws current from
the other pin. If both supply pins are below 2.4V or above
34V then switching activity is stopped.
To further optimize efficiency, the LT8494 automatically
enters Burst Mode operation in light load situations.
Between bursts, all circuitry associated with controlling
the output switch is shut down, reducing the VIN/BIAS
pin supply currents to be less than 3µA typically (see
Electrical Characteristics).
The LT8494 contains a power good comparator which
trips when the FB pin is above 92% of its regulated value.
The PG output is an open-drain transistor that is off when
the output is in regulation, allowing an external resistor to
pull the PG pin high (See Applications Information section
for details).
Several functions are provided to enable a very clean
start-up for the LT8494.
• First, the SWEN pin voltage is monitored by an internal
voltage reference to give a precise turn-on threshold.
An external resistor divider can be connected from
the input power supply to the SWEN pin to provide a
user-programmable undervoltage lockout function.
• Second, the soft-start circuitry provides for a grad-
ual ramp-up of the switch current. When the part is
brought out of shutdown, the external SS capacitor is
first discharged, and then an integrated 256k resistor
pulls the SS pin up to ~2.1V. By connecting an exter-
nal capacitor to the SS pin, the voltage ramp rate on
the pin can be set. Typical values for the soft-start
capacitor range from 100nF to 1µF.
• Finally, the frequency foldback circuit reduces the
maximum switching frequency when the FB pin is
below 1V. This feature reduces the minimum duty
cycle that the part can achieve thus allowing better
control of the switch current during start-up.
LT8494
10
8494fa
For more information www.linear.com/LT8494
FRONT PAGE APPLICATION
LOAD CURRENT (mA)
0.1
1
10
100
1000
0
100
200
300
400
500
SWITCHING FREQUENCY (kHz)
8494 F01
APPLICATIONS INFORMATION
Low Ripple Burst Mode Operation
To enhance efficiency at light loads, the LT8494 regulator
enters low ripple Burst Mode operation keeping the output
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode operation,
the LT8494 regulator delivers single-cycle bursts of cur-
rent to the output capacitor with each followed by a sleep
period where the output power is delivered to the load by
the output capacitor. The quiescent currents of VIN/BIAS
are reduced to less than 3µA typically during the sleep
time (see Electrical Characteristics table).
As the load current decreases towards a no-load con-
dition, the frequency of single current pulses decreases
(see Figure 1), therefore the percentage of time that the
LT8494 operates in sleep mode increases, resulting in
reduced average input current and thus high efficiency
even at very low loads.
By maximizing the time between pulses, the LT8494 qui-
escent current is minimized. Therefore, to optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider and the reverse current
in the external diode must be minimized, as these appear
to the output as load currents. More specifically, during
the sleep time, the boost converter has the reverse diode
leakage current conducting from output to input, while
the SEPIC converter has leakage current conducting
from output to ground. Use the largest possible feedback
Figure 1. Switching Frequency in Burst Mode Operation
resistors and a low leakage Schottky diode in applications
with ultralow Q current.
In Burst Mode operation, the burst frequency and the
charge delivered with each pulse will not change with
output capacitance. Therefore, the output voltage ripple
will be inversely proportional to the output capacitance.
In a typical application with a 47μF output capacitor,
the output ripple is about 10mV, and with two 47μF
output capacitors the output ripple is about 5mV (see
Switching Waveforms, Burst Mode Operation in Typical
Performance Characteristics section). The output voltage
ripple can continue to be decreased by increasing the
output capacitance.
At higher output loads the LT8494 regulator runs at the
frequency programmed by the R
T
resistor and operates as
a standard current mode regulator. The transition between
high current mode and low ripple Burst Mode operation is
seamless, and will not disturb the output voltage.
Setting the Output Voltage
The output voltage is programmed with a resistor divider
from output to the FB pin (R2) and from the FB pin to
ground (R1). Choose the 1% resistors according to:
R2=R1 VOUT
1.202 –1
Note that choosing larger resistors decreases the quies-
cent current of the application circuits. In low load appli-
cations, choosing larger resistors is more critical since
the part enters Burst Mode operation with lower quiescent
current.
Power Switch Duty Cycle
In order to maintain loop stability and deliver adequate
current to the load, the power NPN (Q1 in the Block
Diagram) cannot remain on for 100% of each clock cycle.
The maximum allowable duty cycle is given by:
DCMAX =
T
P
–Minimum Switch Off-Time
T
P
•100%
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where TP is the clock period and Minimum Switch Off-
Time (found in the Electrical Characteristics) is typically
70ns.
Conversely, the power NPNs (Q1 in the Block Diagram)
cannot remain off for 100% of each clock cycle, and will
turn on for a minimum time (Minimum Switch On-Time)
when in regulation. This Minimum Switch On-Time gov-
erns the minimum allowable duty cycle given by:
DCMIN =
Minimum Switch On-Time
T
P
•100%
where TP is the clock period and Minimum Switch On-Time
(found in the Electrical Characteristics) is typically 95ns.
The application should be designed such that the oper-
ating duty cycle (DC) is between DCMIN and DCMAX.
Normally, DC rises with higher VOUT and lower VIN.
Duty cycle equations for both boost and SEPIC topologies
are given below, where VD is the diode forward voltage
drop and VCESAT is typically 340mV at 1.2A.
For the boost topology:
DC ≅
V
OUT
– V
IN
+V
D
V
OUT
+VD– V
CESAT
For the SEPIC topology:
DC ≅
V
OUT
+V
D
VIN +VOUT +VD– VCESAT
The LT8494 can be used in configurations where the duty
cycle is higher than DCMAX, but it must be operated in the
discontinuous conduction mode or Burst Mode operation
so that the effective duty cycle is reduced.
Setting the Switching Frequency
The LT8494 uses a constant frequency PWM architec-
ture that can be programmed to switch from 250kHz to
1.5MHz by using a resistor tied from the RT pin to ground.
Table1 shows the necessary RT values for various switch-
ing frequencies.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz) RT VALUE (kΩ)
0.25 324
0.4 196
0.6 124
0.8 88.7
1.0 68.1
1.2 54.9
1.4 45.3
1.5 41.2
Inductor Selection
General Guidelines: The high frequency operation of
the LT8494 allows for the use of small surface mount
inductors. For high efficiency, choose inductors with high
frequency core material, such as ferrite, to reduce core
losses. To improve efficiency, choose inductors with more
volume for a given inductance. The inductor should have
low DCR (copper wire resistance) to reduce I2R losses,
and must be able to handle the peak inductor current with-
out saturating. Note that in some applications, the cur-
rent handling requirements of the inductor can be lower,
such as in the SEPIC topology when using uncoupled
inductors, where each inductor only carries a fraction of
the total switch current. Molded chokes or chip inductors
usually do not have enough core area to support peak
inductor currents in the 2A to 3A range. To minimize radi-
ated noise, use a toroidal or shielded inductor. Note that
the inductance of shielded types will drop more as current
increases, and will saturate more easily.
Minimum Inductance: Although there can be a trade-off
with efficiency, it is often desirable to minimize board
space by choosing smaller inductors. When choosing
an inductor, there are two conditions that limit the mini-
mum inductance; (1) providing adequate load current,
and (2) avoidance of subharmonic oscillation. Choose
an inductance that is high enough to meet both of these
requirements.
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Adequate Load Current: Small value inductors result in
increased ripple currents and thus, due to the limited peak
switch current, decrease the average current that can be
provided to a load (I
OUT
). In order to provide adequate
load current, L should be at least:
L>
DC• V
IN
2 f
( )
ILIM –VOUT •IOUT
VIN •η
For boost topologies, or:
L>
DC• V
IN
2 f
( )
ILIM –VOUT •IOUT
VIN •η–IOUT
for the SEPIC topologies.
where:
L = L1||L2 for the uncoupled SEPIC topology
DC = switch duty cycle (see previous section)
ILIM = switch current limit, typically about 2.35A
at 50% duty cycle (see the Typical Performance
Characteristics section)
η = power conversion efficiency (typically 85% to
90% for boost and 80% to 85% for SEPIC at high
currents)
f = switching frequency
Negative values of L indicate that the output load cur-
rent IOUT exceeds the switch current limit capability of
the LT8494.
Avoiding Subharmonic Oscillations: The internal slope
compensation circuit of LT8494 helps prevent the subhar-
monic oscillations that can occur when the duty cycle is
greater than 50%, provided that the inductance exceeds
a minimum value. In applications that operate with duty
cycles greater than 50%, the inductance must be at least:
L>VIN – VCESAT
( )
• 2DC–1
( )
0.76 • 1.5•DC+1
( )
• f • 1–DC
( )
for boost and coupled inductor SEPIC, or:
L1||L2 >VIN – VCESAT
( )
• 2DC–1
( )
0.76 • 1.5•DC+1
( )
• f • 1–DC
( )
for the uncoupled inductor SEPIC topologies.
Maximum Inductance: Excessive inductance can reduce
current ripple to levels that are difficult for the current
comparator (A2 in the Block Diagram) to cleanly discrimi-
nate, thus causing duty cycle jitter and/or poor regulation.
The maximum inductance can be calculated by:
LMAX =
V
IN
– V
CESAT
IMIN(RIPPLE)
•
DC
f
where L
MAX
is L1||L2 for uncoupled SEPIC topologies and
IMIN(RIPPLE) is typically 150mA.
Current Rating: Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss.
In steady state, the peak and average input inductor cur-
rents (continuous conduction mode only) are given by:
IL1(PEAK) =
V
OUT
•I
OUT
V
IN
•η+
V
IN
•DC
2•L1• f
IL1(AVG) =
V
OUT
•I
OUT
V
IN
•η
for the boost and uncoupled inductor SEPIC topology.
For uncoupled SEPIC topologies, the peak and average
currents of the output inductor L2 are given by:
IL2(PEAK) =IOUT +VOUT • 1–DC
( )
2•L2• f
I
L2(AVG)
=I
OUT
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For the coupled inductor SEPIC:
I
L(PEAK) =IOUT • 1+VOUT
VIN •η
+VIN •DC
2•L • f
I
L(AVG) =IOUT • 1+VOUT
VIN •η
Note: Inductor current can be higher during load tran-
sients. It can also be higher during short-circuit and
start-up if inadequate soft-start capacitance is used. Thus,
I
L(PEAK)
may be higher than the switch current limit of
2.95A, and the RMS inductor current is approximately
equal to IL(AVG). Choose an inductor having sufficient
saturation current and RMS current ratings.
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple volt-
age. Multilayer ceramic capacitors are an excellent choice,
as they have an extremely low ESR and are available in
very small packages. X5R or X7R dielectrics are preferred,
as these materials retain their capacitance over wider volt-
age and temperature ranges. Always use a capacitor with
a sufficient voltage rating. Many capacitors rated at 2.2µF
to 20µF, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired output voltage. Solid
tantalum or OS-CON capacitors can be used, but they will
occupy more board area than a ceramic and will have a
higher ESR with greater output ripple.
Ceramic capacitors also make a good choice for the input
decoupling capacitor, which should be placed as closely as
possible to the VIN and BIAS pins of the LT8494. A 2.2µF
to 4.7µF input capacitor is sufficient for most applications.
Audible Noise
Ceramic capacitors are small, robust and have very low
ESR. However, due to their piezoelectric nature, ceramic
capacitors can sometimes create audible noise when
used with the LT8494. During Burst Mode operation, the
LT8494 regulator’s switching frequency depends on the
load current, and at very light loads the regulator can
excite the ceramic capacitor at audio frequencies, gen-
erating audible noise. Since LT8494 operates at a lower
current limit during Burst Mode operation, the noise is
typically very quiet. If this is unacceptable, use a high per-
formance tantalum or electrolytic capacitor at the output.
Diode Selection
The diode used in boost or SEPIC topologies conducts
current only during the switch off-time. During the switch
on-time, the diode has reverse voltage across it. The peak
reverse voltage is equal to V
OUT
in the boost topology
and equal to (VOUT + VIN) in the SEPIC topology. Use a
diode with a reverse voltage rating greater than the peak
reverse voltage.
An additional consideration is the reverse leakage cur-
rent. The leakage current appears to the output as load
current and affects the efficiency, most noticeably, under
light load conditions. In Burst Mode operation, after the
inductor current vanishes, the reverse voltage across the
boost diode is approximately equal to VOUT – VIN in the
boost topology and VOUT in the SEPIC topology. The per-
centage of time that the diode is reverse biased increases
as load current decreases.
Schottky diodes that have larger forward voltages often
have less leakage, so a trade-off exists between light
load and high load efficiency. Also the Schottky diodes
with larger reverse bias ratings may have less leakage at
a given output voltage, therefore, superior leakage per-
formance can be achieved at the expense of diode size.
Finally, keep in mind that the leakage current of a power
Schottky diode goes up exponentially with junction tem-
perature. Therefore, the Schottky diode must be selected
with care to avoid excessive increase in light load supply
current at high temperatures.
Soft-Start
The LT8494 contains a soft-start circuit to limit peak
switch currents during start-up. High start-up current is
inherent in switching regulators since the feedback loop
is saturated due to V
OUT
being far from its final value. The
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regulator tries to charge the output capacitor as quickly as
possible, which results in large peak currents. The start-up
current can be limited by connecting an external capacitor
(typically 100nF to 1µF) to the SS pin. This capacitor is
slowly charged to ~2.1V by an internal 256k resistor once
the part is activated. SS pin voltages below ~0.8V reduce
the internal current limit. Thus, the gradual ramping of
the SS voltage also gradually increases the current limit
as the capacitor charges. This, in turn, allows the output
capacitor to charge gradually toward its final value while
limiting the start-up current. When the switching regula-
tor shuts down, the soft-start capacitor is automatically
discharged to ~100mV or less before charging resumes,
thus assuring that the soft-start occurs after every reac-
tivation of the switching regulation.
Power Supplies and Operating Limits
The LT8494 draws supply current from the VIN and BIAS
pins. The largest supply current draw occurs when the
switching regulator is enabled (SWEN is high) and the
power switch is toggling on and off. Under light load con-
ditions the switching regulator enters Burst Mode opera-
tion where the power switch toggles infrequently and the
input current is significantly reduced (see the Low Ripple
Burst Mode Operation section).
Power Switch Driver (PSD) Operating Range: The NPN
power switch is driven by a power switch driver (PSD) as
shown in the Block Diagram. The driver must be powered
by a supply (VIN or BIAS) that is above the minimum oper-
ating voltage and below the PSD overvoltage threshold.
These voltages are typically 2.4V and 34V respectively
(see Electrical Characteristics).
If neither VIN nor BIAS is within this operating range, the
PSD and the switching regulator are automatically dis-
abled. Voltages up to 60V are not harmful to the PSD,
however, as discussed, switching regulation is automati-
cally disabled when neither VIN nor BIAS is in the valid
operating range.
When both VIN and BIAS are too low for proper LT8494
operation (typically < 2.4V), the chip will enter shutdown
and draw minimal current from both supplies.
Automatic Power Supply Selection: In order to minimize
power loss, the LT8494 draws as much of its required
current as possible from the lowest suitable voltage sup-
ply (V
IN
or BIAS) in accordance with the requirements
described in the previous two sections. This selection is
automatic and can change as VIN and/or BIAS voltages
change.
The LT8494 compares the VIN and BIAS voltages to
determine which is lower. The comparator has an offset
and hysteresis as shown in the Electrical Characteristics
section. The voltage comparison happens continuously
when the power switch is toggling. The result of the latest
comparison is latched inside the LT8494 when switching
stops. If the power switch is not toggling, the LT8494
uses the last VIN vs BIAS comparison to determine which
supply is lower. After initial power up or any thermal lock-
out the LT8494 always concludes that V
IN
is the lower
supply voltage until subsequent voltage comparisons can
be made while the power switch is toggling.
BIAS Connection for SEPIC Converters: For SEPIC con-
verters, where VIN can be above or below VOUT, BIAS is
typically connected to V
OUT
which improves efficiency
when VIN voltage is higher than VOUT. Connecting BIAS to
VOUT in a SEPIC topology also allows the switching regu-
lator to operate with VIN above 34V (typical switch driver
overvoltage threshold) in cases where VOUT is regulated
below the PSD overvoltage threshold. Finally, connecting
BIAS to VOUT also allows the converter to operate from
VIN voltages less than 2.4V after VOUT rises within the
PSD operating range. This can be very useful in battery
powered applications since the battery voltage drops as
it discharges.
BIAS Connection for Boost Converters: For boost con-
verters, BIAS is typically connected to VOUT or to ground.
Connecting BIAS to VOUT allows the converter to operate
with VIN < 2.5V after VOUT has risen within the PSD oper-
ating range. However, during no load conditions on VOUT,
despite VIN being selected as the primary input supply,
the overall power loss will be slightly elevated due to the
small amount of current still being drawn from the higher
voltage BIAS pin. To minimize boost converter power
loss during no load conditions, connect BIAS instead to
ground.
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For boost applications with VOUT higher than the PSD
operating range, the BIAS pin should not typically be con-
nected to VOUT. The LT8494 will never draw the majority
of its current from BIAS due to the excessive voltage,
therefore this connection does not help to improve effi-
ciency. Alternative choices for the BIAS pin connection are
ground or another supply that is within the PSD operating
range.
Maximum V
IN
for Boost Converters: V
IN
cannot generally
be higher than VOUT in boost topologies because of the DC
path from VIN to VOUT though the inductor and the output
diode. If VIN must be higher than VOUT, then the induc-
tor must be powered by a separate supply that is always
below VOUT. Otherwise a SEPIC topology can be used.
Also, the LT8494 will not operate in a boost topology
with VIN voltages above the PSD operating range unless
BIAS is connected to an alternative supply within the valid
operating range.
VIN/BIAS Ramp Rate: While initially powering a switching
converter application, the VIN/BIAS ramp rate should be
limited. High VIN/BIAS ramp rates can cause excessive
inrush currents in the passive components of the con-
verter. This can lead to current and/or voltage overstress
and may damage the passive components or the chip.
Ramping rates less than 500mV/µs, depending on com-
ponent parameters, will generally prevent these issues.
Also, be careful to avoid hot-plugging. Hot-plugging
occurs when an active voltage supply is instantly con-
nected or switched to the input of the converter. Hot-
plugging results in very fast input ramp rates and is
not recommended. Finally, for more information, refer
to Linear Application Note 88, which discusses voltage
overstress that can occur when inductive source imped-
ance is hot-plugged to an input pin bypassed by ceramic
capacitors.
Output Power Good
The power good circuits operate properly as long as either
VIN or BIAS is above 1.3V. When the LT8494’s output
voltage is above 92% of the regulation voltage, which
refers to the FB pin voltage being above 1.1V (typical),
the output voltage is considered good and the open-drain
PG pin becomes high impedance and is typically pulled
high with an external resistor. Otherwise, the internal pull-
down device will pull the PG pin low. To prevent glitches,
the power good function has around 46mV of hysteresis
on the FB pin.
As shown in Figure 2, the PG pin is also actively pulled low
during several fault conditions: The SWEN pin is below
1V, thermal shutdown, or VIN and BIAS are both under
2.4V.
Figure 2. Power Good Function
+
–
8494 F02
1.10V
FB
+
–
1.00V
OVER TEMPERATURE
VIN AND BIAS UNDERVOLTAGE
SWEN
LT8494
PG
Enabling the Switching Regulator
The SWEN pin is used to enable or disable the switch-
ing regulator. The rising threshold of SWEN is typically
1V, with 30mV of hysteresis. The switching regulator is
disabled by driving the SWEN pin below this threshold
which deactivates the NPN power switch. The switch-
ing regulator is enabled by driving SWEN pin above its
threshold. Before active switching begins, the soft-start
capacitor will be quickly discharged then slowly charged
causing a gradual startup of the regulator. SWEN can
be connected to V
IN
if always on operation is desired,
although some current may flow into the SWEN pin (see
Typical Performance Characteristics) increasing overall
bias current of the system.
By connecting a resistor divider from VIN to SWEN (see
Figure 3), the LT8494 will be programmed to disable
the switching regulator when VIN drops below a desired
threshold. Typically, this threshold is used in situa-
tions where the input supply is current limited, or has
a relatively high source resistance. A switching regula-
tor draws constant power from the source, so source
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current increases as source voltage drops. This looks like
a negative resistance load to the source and can cause
the source to current limit or latch low under low source
voltage conditions. The input UVLO prevents the regulator
from operating at source voltages where the problems
might occur.
As shown in Figure 3, by connecting a resistor divider
from the VIN pin to the SWEN pin, the falling undervoltage
lockout threshold is set to:
VIN(UVLO) =
R3+R4
R3
•0.97V
From the previous equation, the resistor divider shown in
Figure 3 gives the VIN pin a falling undervoltage lockout
threshold of 2.96V. When VIN is below this threshold, the
switching regulation is disabled and the SS pin starts to
discharge. After choosing the value of R3, for example,
R4 can be calculated using:
R4 =R3• VIN(UVLO)
0.97 –1
Ω
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8494. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread heat dissipated by the LT8494.
Placing additional vias can reduce thermal resistance fur-
ther. The maximum load current should be derated as the
ambient temperature approaches the maximum junction
rating. Power dissipation within the LT8494 is estimated
by calculating the total power loss from an efficiency
measurement and subtracting the diode loss, FB resistor
loss and inductor loss. The die temperature is calculated
by multiplying the LT8494 power dissipation by the ther-
mal resistance from junction to ambient.
The power switch and its driver dissipate the most power
in the LT8494 (see Block Diagram). Higher switch cur-
rent, duty cycle and output voltage result in higher die
temperature. Power loss in the power switch driver also
increases with higher input supply voltage. The PSD is
supplied by the lowest suitable voltage on VIN and BIAS.
Connecting BIAS to a low voltage supply, often VOUT, can
reduce the maximum die temperature of the LT8494 (see
Automatic Power Supply Selection section).
Also note that leakage current into the SWEN and FB
pins increases at high junction temperatures (see Typical
Performance Characteristics). The potential leakage
current should be considered when choosing high value
resistors connected to those pins.
Thermal Lockout: If the die temperature reaches approxi-
mately 165°C, the part will go into thermal lockout and the
chip will be reset. The part will be enabled again when the
die temperature has dropped by ~5°C (nominal). During
thermal lockout, the PG pin is actively pulled low, see the
Output Power Good section for more details.
Fault Tolerance
The LT8494 is designed to tolerate single fault condi-
tions in the TSSOP package. Shorting two adjacent pins
together or leaving one single pin floating does not raise
VOUT or cause damage to the LT8494 regulator.
Table 3 and Table 4 show the effects that result from
shorting adjacent pins and from a floating pin, respec-
tively. NC pins 4, 9, 17, and 19 must remain floating on
the PCB to ensure fault tolerance. NC pins 5 and 15 are not
connected to internal circuitry and can either be floated
or grounded on the PCB without effecting the fault toler-
ance. It is recommended that the remaining NC pins (6,
11 and 13) also remain floating on the PCB for best fault
tolerance. Table 3 assumes that all NC pins are floating.
For the best fault tolerance to inadvertent adjacent pin
shorts, the BIAS pin must be tied to something higher
than 1.230V or to the output to avoid overvoltage during
a short from FB to BIAS.
Figure 3. VIN Undervoltage Lockout
+
–
2.1V
LT8494
1.00V SS
8494 F03
SWEN
256k
R3
487k
R4
1M
VC
VIN
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Table 3. Effects of Pin Shorts (TSSOP)
PIN NAMES PIN # EFFECT ON OUTPUT
FB/BIAS 1/2 Output voltage will fall to approximately
1.202V if BIAS is connected to the output.
PG/SS 7/8 No effect or output will fall below regulation.
Table 4. Effects of Floating Pins (TSSOP)
PIN NAME PIN # EFFECT ON OUTPUT
BIAS 1 Depending on the VIN voltage and the circuit
topology, floating this pin will degrade de-vice
performance or the output will fall below
regulation.
FB 2, 3 No effect if the other FB pad is soldered.
PG 7 No effect on output.
SS 8 No effect after part has started. Can
potentially lead to an increase of inrush
current during start-up.
RT 10 Output may fall below regulation.
SWEN 12 Enable state of the pin becomes undefined.
Output will not exceed regulation voltage.
GND 14 No effect if Exposed Pad is soldered.
GND 16 No effect on output.
VIN 18 Depending on the BIAS voltage and the circuit
topology, floating this pin will degrade device
performance or the output will fall below
regulation.
SW 10 Output will fall below regulation voltage.
Exposed Pad 21 Output maintains regulation, but potential
degradation of device performance.
Layout Hints
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. One will not get adver-
tised performance with a careless layout. For maximum
efficiency, switch rise and fall times are typically in the
5ns to 10ns range. To prevent noise, both radiated and
conducted, the high speed switching current path, shown
in Figures 4 and 5, must be kept as short as possible. This
is implemented in the suggested PCB layouts in Figures 6
and 7. Shortening this path will also reduce the parasitic
trace inductance. At switch-off, this parasitic inductance
produces a flyback spike across the LT8494 switch. When
operating at higher currents and output voltages, with
poor layout, this spike can generate voltages across the
LT8494 that may exceed its absolute maximum rating.
A ground plane should also be used under the switcher
circuitry to prevent interplane coupling and overall noise.
The FB components should be kept as far away as practi-
cal from the switch node. The ground for these compo-
nents should be separated from the switch current path.
Failure to do so can result in poor stability or subharmonic
oscillation.
Figure 4. High Speed Chopped Switching Path for Boost Topology
Figure 5. High Speed Chopped Switching Path for
SEPIC Topology
LT8494
8494 F04
VIN
V
OUT
L1 D1
C1
GND
HIGH
FREQUENCY
SWITCHING
PATH
C2 LOAD
SW
LT8494
8494 F05
VIN
V
OUT
L1
D1
C1
GND
SW
HIGH
FREQUENCY
SWITCHING
PATH
C2
C3
L2 LOAD
•
•
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Figure 6. Suggested Component Placement for Boost Topology
Using TSSOP Package. Pin 21 (Exposed Pad) Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
Figure 7. Suggested Component Placement for SEPIC Topology
Using TSSOP Package. Pin 21 (Exposed Pad) Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
8494 F07
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SWEN
VIAS TO GROUND PLANE
GND
GND
VIN
VOUT
SW
21
RT
SS
PG
FB
L1L2
C1
D1
•
•
C2
C3
8494 F06
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SWEN
VIAS TO GROUND PLANE
GND
GND
VIN
VOUT
SW
21
RT
SS
PG
FB
C1
D1
C2
L1
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TYPICAL APPLICATIONS
750kHz, 16V to 32V Input, 48V Output, 0.5A Boost Converter
450kHz, 5V Output SEPIC Converter (Same as Front Page Application)
L1
22µH
C1: 2.2µF, 50V, X5R, 1206
C2: 4.7µF, 100V, X7R, 1210
D1: ONSEMI MBRA2H100
L1: WURTH LHMI 74437349220
D1
0.2µF
10pF
VIN
16V TO 32V
V
OUT
48V
0.5A
SW FB
BIAS
GND
VIN
SWEN
RT
PG
SS
1M
25.5k
8494 TA02a
93.1k
LT8494
C2
4.7µF
×2
C1
2.2µF
LOAD CURRENT (mA)
0
100
200
300
400
500
70
75
80
85
90
95
100
EFFICIENCY (%)
8494 TA02b
V
IN
= 24V
200µs/DIV
8494 TA02d
VOUT
0.5V/DIV
AC-COUPLED
IL
0.5A/DIV
VIN = 24V
96Ω LOAD
5ms/DIV
8494 TA02e
VOUT
20V/DIV
VSS
0.5V/DIV
IL
0.5A/DIV
Efficiency, VIN = 24V
Transient Response with 400mA to
500mA to 400mA Output Load Step Start-Up Waveforms
L1
15µH
C1: 4.7µF, 100V, X5R, 1206
C3: 2.2µF, 100V, X5R, 1206
C2: TAIYO YUDEN, EMK325BJ476MM-T
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-150-R
D1
1µF
4.7pF
VIN
3V TO 60V
(3V TO 32V
FOR START-UP)
VOUT
5V
0.35A (VIN
= 3V)
0.6A (VIN = 5V)
1.0A (VIN
> 12V)
SW BIAS
FB
GND
VIN
SWEN
RT
PG
SS
316k
1M
8494 TA02c
169k
LT8494
C2
47µF
×2
C3
2.2µF
C1
4.7µF
•
•
L2
15µH
LT8494
20
8494fa
For more information www.linear.com/LT8494
TYPICAL APPLICATIONS
Wide Input and Output Range SEPIC Converter with Charge Pump Switches at 400kHz
L1
22µH
L1, L2: COILCRAFT MSD1260T-223ML
C1: 2.2µF, 50V, X5R, 1206
C2, C7-C10: TAIYO YUDEN GMK325C7106KMHT, 10µF 35V, X7S, 1210
C3: 3.3µF, 100V, X7R, 1210
D1-D4: FAIRCHILD 0540
D5-D7: ON-SEMI MBRA2H100
R1: 1.2Ω, 0.5W, SMD, 2010
D5
D7
•
1µF
VIN
6V TO 38V
(6V TO 32V FOR STARTUP)
VOUT
20V to 60V
80mA
SW BIAS
FB
PG
GND
VIN
SWEN
RT SS
8494 TA03a
196k
LT8494
C2
10µF
×2
C7
10µF
×2
C8
10µF
×2
C1
2.2µF
C3
3.3µF
•
L2
22µH
26.7k
1M
78.7k 0.1V TO 3.2V
R1
1.2Ω
D6
D4
D1
C9
10µF
D3
D2
C10
10µF
DAC
(SET DAC TO 3.2V FOR START-UP)
OUTPUT
ADJUST
LT8494
21
8494fa
For more information www.linear.com/LT8494
TYPICAL APPLICATIONS
Li-Ion to 12V, Low Quiescent Current Boost at 650kHz
Low Quiescent Current, 5V to 300V, 250kHz Flyback Converter
DANGER HIGH VOLTAGE!
Operation by High Voltage Trained Personnel Only
L1
6.8µH
C1: 4.7µF, 6.3V, X7R, 1206
C2: 47µF, 16V, X5R, 1210
D1: ONSEMI MBRM120LT1G
L1: WURTH LHMI 74437346068
D1
1µF
VIN
2.8V TO 4.1V
VOUT
12V
0.2A
SW FB
BIAS
GND
VIN
SWEN
RT
PG
SS
1M
110k
8494 TA04a
113k
LT8494
C2
47µF
C1
4.7µF
14.7µH
*KEEP MAXIMUM OUTPUT POWER BELOW 0.6W
C1: 2.2µF, 25V, X5R, 1206
C2: TDK C3225CH2J223K
D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: ON SEMICONDUCTOR MBRA2H100
T1: WURTH-FLEX FLEXIBAL TRANSFORMER 749196121
D1
T1
1:5
D2
1µF
VIN
5V
VOUT
300V
2mA
SW FB
BIAS
GND
VIN
SWEN
RT
PG
SS
1M
1M
1M
12.1k
8494 TA05
324k
LT8494
C2
22nF
C1
2.2µF
•
•
LOAD CURRENT (mA)
0.2
1
10
100
200
55
60
65
70
75
80
85
90
95
EFFICIENCY (%)
8494 TA04b
Efficiency, VIN = 3.3V
2mA LOAD
5ms/DIV
8494 TA05b
VOUT
50V/DIV
I
PRIMARY
0.5A/DIV
2mA LOAD
2µs/DIV
8494 TA05c
VOUT
0.5V/DIV
I
PRIMARY
1A/DIV
Switching WaveformsStart-Up Waveforms
LT8494
22
8494fa
For more information www.linear.com/LT8494
TYPICAL APPLICATIONS
1.5MHz, 12V Output SEPIC Converter
L1
4.7µH
L2
4.7µH
C1, C3: 2.2µF, 50V, X5R, 1206
C2: TAIYO YUDEN TMK325BJ106MM
D1: DENTRAL SEMI CMMSH2-40
L1, L2: COILTRONICS DRQ74-4R7
1µF
4.7pF
VIN
9V TO 16V
V
OUT
12V
0.5A
SW BIAS
FB
GND
VIN
SWEN
RT
PG
SS
1M
110k
8494 TA08a
41.2k
LT8494
C2
10µF
×2
C1
2.2µF
C3
2.2µF D1
•
•
LOAD CURRENT (mA)
0
100
200
300
400
500
8498 TA08b
50
55
60
65
70
75
80
85
90
0
300
600
900
1200
EFFICIENCY (%)
POWER LOSS (mW)
POWER LOSS
EFFICIENCY
Efficiency, VIN = 12V
LT8494
23
8494fa
For more information www.linear.com/LT8494
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8494#packaging for the most recent package drawings.
4.00 ±0.10
4.00 ±0.10
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.00 REF 2.45 ±0.10
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF20) QFN 01-07 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.00 REF 2.45 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 ×
45°
CHAMFER
2.45 ±0.10
2.45 ±0.05
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
LT8494
24
8494fa
For more information www.linear.com/LT8494
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8494#packaging for the most recent package drawings.
FE20 (CB) TSSOP REV L 0117
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
DETAIL A
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation CB
DETAIL A
0.60
(.024)
REF
0.28
(.011)
REF
LT8494
25
8494fa
For more information www.linear.com/LT8494
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 06/17 Clarified input conditions on top application 19, 24
LT8494
26
8494fa
For more information www.linear.com/LT8494
LINEAR TECHNOLOGY CORPORATION 2015
LT 0617 REV A • PRINTED IN USA
www.linear.com/LT8494
RELATED PARTS
TYPICAL APPLICATION
450kHz, Wide Input Range 12V Output SEPIC Converter
PART NUMBER DESCRIPTION COMMENTS
LT8495 70V, 2A Boost/SEPIC 1.5MHz High Efficiency DC/DC Converter with
POR and Watchdog Timer
VIN: 2.5V to 32V, VOUT(MAX) = 70V, IQ = 9µA, ISD < 1µA,
4mm × 4mm QFN20, TSSOP-20E Packages
LT3580 42V, 2A Boost/Inverting 2.5MHz High Efficiency DC/DC Converter VIN: 2.5V to 32V, VOUT(MAX) = ±40V, IQ = 1mA, ISD < 1µA,
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LT8580 65V, 1A Boost/Inverting DC/DC Converter VIN: 2.55V to 40V, VOUT(MAX) = ±60V, IQ = 1.2mA, ISD < 1µA,
3mm × 3mm DFN-8, MSOP-8E Packages
LT8570/
LT8570-1
65V, 500mA/250mA Boost/Inverting DC/DC Converter VIN: 2.55V to 40V, VOUT(MAX) = ±60V, IQ = 1.2mA, ISD < 1µA,
3mm × 3mm DFN-8, MSOP-8E Packages
LT8582 40V, Dual 3A, 2.5MHz High Efficiency Boost Converter VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 2.8mA, ISD < 1µA,
7mm × 4mm DFN-24 Package
LT8471 40V, Dual 3A, Multitopology High Efficiency DC/DC Converter VIN: 2.6V to 50V, VOUT(MAX) = ±45V, IQ = 2.4mA, ISD < 1µA,
TSSOP-20E Package
LT3581 40V, 3.3A, 2.5MHz High Efficiency Boost Converter VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 1mA, ISD < 1µA,
4mm × 3mm DFN-14, MSOP-16E Packages
LT8582 40V, Dual 3A Boost, Inverter
, SEPIC, 2.5MHz High Efficiency Boost
Converter
VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 2.1mA, ISD < 1µA,
7mm × 4mm DFN-24 Package
LT3579/
LT3579-1
40V, 3.3A Boost, Inverter
, SEPIC, 2.5MHz High Efficiency Boost
Converter
VIN: 2.5V to 40V, VOUT(MAX) = ±40V, IQ = 1mA, ISD < 1µA,
4mm × 5mm QFN-20, TSSOP-20E Packages
C3
2.2µF D1
L1
10µH •
•
L2
10µH
1µF
VIN
3V TO 55V
(3V TO 32V
FOR START-UP)
VOUT
12V
0.2A (VIN = 3V)
0.35A (VIN = 5V)
0.65A (VIN
> 12V)
SW BIAS
FB
GND
VIN
SWEN
RT
PG
SS
1M
110k
8494 TA06a
169k
LT8494
C2
10µF
×3
C1
2.2µF
C1, C3: 2.2µF, 100V, X5R, 1210
C2: 10µF, 25V, X5R, 1210
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-100-R
(VOUT RIPPLE
MAY INCREASE
BELOW 6V VIN)
V
IN
= 12V
V
IN
= 24V
V
IN
= 5V
LOAD CURRENT (A)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
60
65
70
75
80
85
90
EFFICIENCY (%)
8494 TA06b
INPUT VOLTAGE (V)
0
10
20
30
40
50
60
0
20
40
60
80
100
SUPPLY CURRENT (µA)
8494 TA06c
Efficiency
No-Load Supply Current