TPA5052
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FEATURES APPLICATIONS
DESCRIPTION
SIMPLIFIED APPLICATION DIAGRAM
BCLK
LRCLK
DATA DATA_OUT
5
3.3V
BCLK
LRCLK
DATA
TPA5052
Digital Amplifier
SCLK
AudioProcessor
SCLK
BCLK
LRCLK
DATA
DELx
(4:0)
Fixed Delay
Control
VDD
GND
TAS3103A
or
ATSC
Processor
TAS5504A
+TAS5122
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
STEREO DIGITAL AUDIO LIP-SYNC DELAY
•High Definition TV Lip-Sync Delay•Digital Audio Format: 16-24-bit I
2
S
•Flat Panel TV Lip-Sync Delay•Single Serial Input Port
•Home Theater Rear-Channel Effects•Delay Time: 170 ms/ch at fs = 48 kHz
•Wireless Speaker Front-Channel•Delay Resolution: 256 samples
Synchronization•Delay Memory Cleared on Power-Up or After
•CamcordersDelay Changes
– Eliminates Erroneous Data From BeingOutput
The TPA5052 accepts a single serial audio input,•3.3 V Operation With 5 V Tolerant I/O
buffers the data for a selectable period of time, and•Supports Audio Bit Clock Rates of 32 to 64 fs
outputs the delayed audio data on a single serialwith fs = 32 kHz–192 kHz
output. In systems with complex video processingalgorithms, one device allows delay of up to•No External Crystal or Oscillator Required
170 ms/ch (fs = 48 kHz) to synchronize the audio– All Internal Clocks Generated From the
stream to the video stream. If more delay is needed,Audio Clock
the devices can be connected in series.•Surface Mount 4mm ×4mm, 16-pin QFNPackage
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PIN DESCRIPTIONS
DEL1
LRCLK
DEL3
GND
DEL0
DEL2
GND
DATA
7
5
6
11
9
10
12
16
15
14
13
3
1
2
4
DEL4
8
GND
GND
GND
BCLK
DATA_OUT
VDD
VDD
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
RSA (QFN) PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
DEL0 10 I Delay select pin – LSB. 5V tolerant input.DEL1 11 I Delay select pin. 5V tolerant input.DEL2 12 I Delay select pin. 5V tolerant input.DEL3 3 I Delay select pin. 5V tolerant input.DEL4 4 I Delay select pin - MSB. 5V tolerant input.BCLK 16 I Audio data bit clock input for serial input. 5V tolerant input.DATA 2 I Audio serial data input for serial input. 5V tolerant input.DATA_OUT 15 O Delayed audio serial data output.GND 5–9 P Ground – All ground terminals must be tied to GND for proper operationLRCLK 1 I Left and Right serial audio sampling rate clock (fs). 5V tolerant input.VDD 13, 14 P Power supply interface. Both pins must be tied to power supply.Connect to ground. Must be soldered down in all applications to properly secure device on theThermal Pad -
PCB.
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FUNCTIONAL BLOCK DIAGRAM
DATA
BCLK
LRCLK
INPUT
BUFFER
OUTPUT
BUFFER DATA_OUT
CONTROL
5
DELx(4:0)
DELAY
MEMORY
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
over operating free-air temperature (unless otherwise noted)
(1)
VALUE UNIT
V
DD
Supply voltage –0.3 to 3.6 VV
I
Input voltage DATA, LRCLK, BCLK, DEL[4:0] –0.3 to 5.5 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range –40 to 85 °CT
J
Operating junction temperature range –40 to 125 °CT
stg
Storage temperature range –65 to 125 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE T
A
≤25 °C DERATING T
A
= 70 °C T
A
= 85 °CPOWER RATING FACTOR POWER RATING POWER RATING
RSA 2.5 W 25 mW/ °C 1.375 W 1 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad mustbe soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017 D and SLUA271 for more information aboutusing the QFN thermal pad.
MIN MAX UNIT
V
DD
Supply voltage VDD 3 3.6 VV
IH
High-level input voltage DATA, LRCLK, BCLK, DEL[4:0] 2 VV
IL
Low-level input voltage DATA, LRCLK, BCLK, DEL[4:0] 0.8 VT
A
Operating free-air temperature –40 85 °C
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DC CHARACTERISTICS
Serial Audio Input Ports
th1
tsu1
tsu2
th2
DATA
BCLK
(Input)
LRCLK
(Input)
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
T
A
= 25 °C, V
DD
= 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
DD
Supply current V
DD
= 3.3 V, fs = 48 kHz, BCLK = 32 ×fs 1.8 3 mAI
OH
High-level output current DATA_OUT = 2.6 V 5 13 mAI
OL
Low-level output current DATA_OUT = 0.4 V 5 13 mADATA, LRCLK, BCLK, V
I
= 5.5V, VDD = 3V 20I
IH
High-level input current µADEL[4:0], V
I
= 3.6V, VDD = 3.6V 5I
IL
Low-level input current DATA, LRCLK, BCLK, DEL[4:0], V
I
= 0V, VDD = 3.6V 1 µA
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
Frequency, BCLK 32 ×fs, 48 ×fs, 64 ×fs 1.024 12.288 MHzt
su1
Setup time, LRCLK to BCLK rising edge 10 nst
h1
Hold time, LRCLK from BCLK rising edge 10 nst
su2
Setup time, DATA to BCLK rising edge 10 nst
h2
Hold time, DATA from BCLK rising edge 10 nsLRCLK frequency 32 48 192 kHzBCLK duty cycle 50%LRCLK duty cycle 50%BCLK rising edges between LRCLK rising edges LRCLK duty cycle = 50% 32 64 BCLK edges
Figure 1. Serial Data Interface Timing
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APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
I
2
S TIMING
1/fS
(=32fS,48fS, or64fS)
L-Channel R-ChannelLRCK
BCK
DATA 1 2 3 1 2
MSB
N–2 N
N–1
LSB
1 2 3
MSB
N–2 N
N–1
LSB
GENERAL DELAY OPERATION
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
The audio serial interface for the TPA5052 consists of a 3-wire synchronous serial port. It includes LRCLK,BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA intothe serial shift register of the audio interface. Serial data is clocked into the TPA5052 on the rising edge ofBCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers ofthe serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64times the sampling frequency for I
2
S formats. A system clock is not necessary for the operation of the TPA5052.
The I
2
S data format diagram is shown in Figure 2 .
Figure 2. I
2
S Data Format; L-Channel = LOW, R-Channel = HIGH
The delay of the TPA5052 is set using the 5 delay pins (DEL4, DEL3, DEL2, DEL1, DEL0). The minimum delayis 255 samples, and occurs when all five pins are at logic 0. The maximum delay is 8191 samples, and occurswhen all five pins are at logic 1. The delay can be increased by changing the values on each pin from a 0 to a 1.See Table 1 . Delay pin DEL4 is the MSB, and DEL0 is the LSB.
The delay is calculated with the following forumula:Audio Delay (in samples) = 4096 x (DEL4) + 2048 x (DEL3) + 1024 x (DEL2) + 512 x (DEL1) + 256 x(DEL0) + 255Audio Delay (ms) = Audio Delay (in samples) x (1/fs)
Both channels have the same amount of delay. They cannot be controlled individually.
Table 1. Delay Settings
DEL4 DEL3 DEL2 DEL1 DEL0 Delay in Samples
0 0 0 0 0 2550 0 0 0 1 5110 0 0 1 0 7670 0 0 1 1 1023↓ ↓ ↓ ↓ ↓ ↓1 1 1 1 1 8191
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TPA5052 Operation
COMPLETE UPDATE
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
Only a single decoupling capacitor (0.1 µF–1 µF) is required across VDD and GND. The DELx terminals can bedirectly connected to VDD or GND. Table 1 describes the delay settings selectable via the DELx terminals. Aschematic implementation of the TPA5052 is shown in Figure 3 .
Figure 3. TPA5052 Schematic
To avoid pops and clicks in the audio stream when the delay is changed, the TPA5052 holds each channel in aninternal mute mode until all the set number of samples have passed. For example, if the delay is set to 511samples, the TPA5052 holds each channel in mute until all 511 samples of audio data have passed.
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APPLICATION EXAMPLES
Connecting Two Devices in Series to Increase the Delay
VDD VDD
BCLK
BCLK
LRCLK
LRCLK
DATA_OUT DATA_OUT
DEL4 DEL4
DEL3 DEL3
DEL0 DEL0
GND GND
Audio
Amplifier
0.1 Fm0.1 Fm
DEL2 DEL2
DEL1 DEL1
SCLK
DATA DATA
BCLK
LRCLK
Audio
Processor
SCLK
DATA
BCLK
LRCLK
DATA
DEVICE CURRENT CONSUMPTION
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
32 52 72 92 112 132 152 172 192
fs-SamplingFrequency-kHz
I -SupplyCurrent-mA
DD
V =3.6V
DD
V =3.3V
DD
V =3V
DD
BCLK=64fs
Data=24bit
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
It is sometimes desirable to increase the delay time beyond the limit which one device provides. In such cases,the TPA5052 device can be placed in a series to increase the delay. See Figure 4 for an example.
Figure 4. Two Devices in Series
The TPA5052 draws different amounts of supply current depending upon the conditions under which it isoperated. As V
DD
increases, so too does I
DD
. Likewise, as V
DD
decreases, I
DD
decreases. The same is true ofthe sampling frequency, fs. An increase in fs causes an increase in I
DD
.Figure 5 illustrates the relationshipbetween operating condition and typical supply current.
SUPPLY CURRENT
vsSAMPLE FREQUENCY
Figure 5. Typical Supply Current
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPA5052RSAR ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5052RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5052RSAT ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA5052RSATG4 ACTIVE QFN RSA 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA5052RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPA5052RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA5052RSAR QFN RSA 16 3000 367.0 367.0 35.0
TPA5052RSAT QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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