EVALUATION KIT AVAILABLE MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC General Description Features The MAX19793 dual general-purpose analog voltage variable attenuator (VVA) is designed to interface with 50I systems operating in the 1500MHz to 6000MHz frequency range. The device includes a patented control circuit that provides 23.3dB of attenuation range (per attenuator) with a typical linear control slope of 8.4dB/V. S Wideband Coverage 1500MHz to 6000MHz RF Frequency Range Both attenuators share a common analog control and can be cascaded together to yield 46.6dB of total attenuation range with a typical combined linear control slope of 16.8dB/ V (5V operation). S Integrates Two Analog Attenuators in One Monolithic Device Alternatively, the on-chip 4-wire SPI-controlled 10-bit DAC can be used to control both attenuators. In addition, a step-up/down feature allows user-programmable attenuator stepping through command pulses without reprogramming the SPI interface. The MAX19793 is a monolithic device designed using one of Maxim's proprietary SiGe BiCMOS processes. The part operates from a single +5V supply or alternatively from a single +3.3V supply. It is available in a compact 36-pin TQFN package (6mm x 6mm x 0.8mm) with an exposed pad. Electrical performance is guaranteed over the -40NC to +100NC extended temperature range. Applications Broadband System Applications, Including Wireless Infrastructure Digital and Spread-Spectrum Communication Systems S High Linearity Greater Than +37dBm IIP3 Over the Full Attenuation Range +23.7dBm Input P1dB S Two Convenient Control Options Single Analog Voltage On-Chip SPI-Controlled 10-Bit DAC S Step-Up /Down Pulse Command Inputs S Flexible Attenuation Control Ranges 23.3dB (Per Attenuator) 46.6dB (Both Attenuators Cascaded) S Linear dB/V Analog Control Response Curve Simplifies Automatic Leveling Control and Gain-Trim Algorithms S Excellent Attenuation Flatness Over Wide Frequency Ranges and Attenuation Settings S On-Chip Comparator (for Successive Approximation Measurement of Attenuator Control Voltage) S Low 13mA Supply Current S Single 5V or 3.3V Supply Voltage WCDMA/LTE, TD-SCDMA/TD-LTE, WiMAX(R), cdma2000M, GSM/EDGE, and MMDS Base Stations S Pin-Compatible with the MAX19791 and MAX19792 VSAT/Satellite Modems S PCB-Compatible with the MAX19790 Microwave Point-to-Point Systems S Lead(Pb)-Free Package Lineup Gain Trim Ordering Information appears at end of data sheet. Temperature-Compensation Circuits Automatic Level Control (ALC) S Pin-Compatible with the MAX19794 with Addition of Two Shunt Capacitors For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX19793.related. Transmitter Gain Control Receiver Gain Control General Test Equipment WiMAX(R) is a registered certification mark and registered service mark of WiMAX Forum. cdma2000 is a registered trademark of Telecommunications Industry Association. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maximintegrated.com. 19-6452; Rev 1; 5/15 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC ABSOLUTE MAXIMUM RATINGS VCC........................................................................-0.3V to +5.5V REF_IN...............................-0.3V to Minimum (VCC + 0.3V, 3.6V) REF_SEL, DAC_LOGIC, MODE, DWN, UP, DIN, CLK, CS................ -0.3V to Minimum (VCC + 0.3V, 3.6V) COMP_OUT, DOUT...............................................-0.3V to +3.6V IN_A, OUT_A, IN_B, OUT_B........................-0.3V to VCC + 0.3V CTRL (except for test mode)........................-0.3V to VCC + 0.3V Maximum CTRL Pin Load Current (CTRL configured as an output).....................................0.3mA RF Input Power at IN_A, IN_B, OUT_A, OUT_B............ +20dBm Continuous Power Dissipation (Note 1)...............................2.8W Operating Case Temperature Range (Note 2)...-40NC to +100NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details. The junction temperature must not exceed +150NC. Note 2: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS TQFN Junction-to-Ambient Thermal Resistance (qJA) (Notes 3, 4)................................................................ +36NC/W Junction-to-Case Thermal Resistance (qJC) (Notes 1, 4)................................................................ +10NC/W Note 3: Junction temperature TJ = TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is known. The junction temperature must not exceed +150NC. Note 4: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. 3.3V DC ELECTRICAL CHARACTERISTICS (VCC = 3.15V to 3.45V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, no RF signals applied, all input and output ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 3.3V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, TC = +25NC, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC Control Voltage Range VCTRL CTRL Input Resistance RCTRL CONDITIONS MIN TYP MAX UNITS 3.15 3.3 3.45 V 9.5 14 mA 1 2.5 1.0 V MI Input Current Logic-High IIH -1 +1 A Input Current Logic-Low IIL -1 +1 A REF_IN Voltage 1.4 V REF_IN Input Resistance 1.0 MI DAC Number of Bits Monotonic Input Voltage Logic-High VIH Input Voltage Logic-Low VIL 10 2 Bits V 0.8 V COMP_OUT Logic-High RDBK_EN (D9, REG3) = logic 1, RLOAD = 47kI 3.3 V COMP_OUT Logic-Low RDBK_EN (D9, REG3) = logic 1, RLOAD = 47kI 0 V Maxim Integrated 2 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 5V DC ELECTRICAL CHARACTERISTICS (VCC = 4.75V to 5.25V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, no RF signals applied, all input and output ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 5V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, TC = +25NC, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC CTRL Voltage Range VCTRL CTRL Input Resistance RCTRL CONDITIONS MIN TYP MAX UNITS 4.75 5.0 5.25 V 13 20 mA 4 V 1 124 kI Input Current Logic-High IIH -1 +1 A Input Current Logic-Low IIL -1 +1 A REF_IN Voltage Range 1.4 V REF_IN Input Resistance 1.0 MI 10 Bits DAC Number of Bits Monotonic Input Voltage Logic-High VIH Input Voltage Logic-Low VIL 2 V 0.8 V COMP_OUT Logic-High RDBK_EN (D9, REG3) = logic 1, RLOAD = 47kI 3.3 V COMP_OUT Logic-Low RDBK_EN (D9, REG3) = logic 1, RLOAD = 47kI 0 V RECOMMENDED AC OPERATING CONDITIONS PARAMETER SYMBOL CONDITIONS RF Frequency Range fRF (Note 6) RF Port Input Power PRF Continuous operation Maxim Integrated MIN 1500 TYP MAX UNITS 6000 MHz 15 dBm 3 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 3.3V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, one attenuator, VCC = 3.15V to 3.45V, RF ports are driven from 50I sources and loaded into 50I, input PRF = 0dBm, fRF = 3500MHz, VCTRL = 1V to 2.5V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, TC = -40NC to +100NC. Typical values are for TC = +25NC, VCC = 3.3V, input PRF = 0dBm, fRF = 3500MHz, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, unless otherwise noted.) (Notes 5, 7) PARAMETER Insertion Loss SYMBOL IL Loss Variation Over Temperature Input P1dB Minimum Input Second-Order Intercept Point Over Full Attenuation Range (Note 8) Minimum Input Third-Order Intercept Point Over Full Attenuation Range (Note 8) CONDITIONS IIP3 TYP MAX UNITS One attenuator 4.0 Two attenuators 7.9 TC = -40NC to +100NC 0.45 dB 18 dBm IP1dB IIP2 MIN One attenuator, fRF1 + fRF2 term, fRF1 - fRF2 = 1MHz, VCTRL = 1V to 2.5V, PRF = 0dBm/tone applied to attenuator input 54 Two attenuators, fRF1 + fRF2 term, fRF1 - fRF2 = 1MHz, VCTRL = 1V to 2.5V, PRF = 0dBm/tone applied to attenuator input 52.3 One attenuator, VCTRL = 1V to 2.5V, fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone applied to attenuator input 33.8 Two attenuators, VCTRL = 1V to 2.0V, fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone applied to attenuator input 33.6 dB dBm dBm Second Harmonic 60.8 dBc Third Harmonic 88.6 dBc One attenuator, VCTRL = 1V to 2.5V 23.1 Two attenuators, VCTRL = 1V to 2.5V 46.2 Average Attenuation-Control Slope VCTRL = 1.4V to 2.3V 23.9 dB/V Maximum Attenuation-Control Slope VCTRL = 1V to 2.5V 39 dB/V S21 Attenuation Deviation from a Straight Line VCTRL = 1.4V to 2.1V 0.4 dB Attenuation Control Range Maxim Integrated dB 4 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 5V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I, input PRF = 0dBm, fRF = 3500MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, TC = -40NC to +100NC. Typical values are for TC = +25NC, VCC = 5V, input PRF = 0dBm, fRF = 3500MHz, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, unless otherwise noted.) (Notes 5, 7) PARAMETER Insertion Loss SYMBOL IL Loss Variation Over Temperature Input P1dB Minimum Input Second-Order Intercept Point Over Full Attenuation Range (Note 8) Minimum Input Third-Order Intercept Point Over Full Attenuation Range (Note 8) CONDITIONS IIP3 TYP MAX UNITS 3.9 Two attenuators 7.6 TC = -40NC to +100NC 0.45 dB 23.7 dBm IP1dB IIP2 MIN One attenuator One attenuator, fRF1 + fRF2 term, fRF1 - fRF2 = 1MHz, VCTRL = 1V to 4V, PRF = 0dBm/tone applied to attenuator input 65 Two attenuators, fRF1 + fRF2 term, fRF1 - fRF2 = 1MHz, VCTRL = 1V to 3.5V, PRF = 0dBm/tone applied to attenuator input 63 One attenuator, VCTRL from 1V to 4V, fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone applied to attenuator input 38 Two attenuators, VCTRL from 1V to 2.8V, fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone applied to attenuator input 37 Second Harmonic Third Harmonic dB dBm dBm 72.2 dBc 104.7 dBc One attenuator, VCTRL = 1V to 4V 23.3 Two attenuators, VCTRL = 1V to 4V 46.6 Average Attenuation-Control Slope VCTRL = 1.4V to 3.1V 8.4 dB/V Maximum Attenuation-Control Slope VCTRL = 1V to 3.5V 30 dB/V Attenuation Flatness Over 125MHz Band VCTRL = 1V to 4V 0.25 dB Attenuation Control Range Maxim Integrated dB 5 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 5V AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I, input PRF = 0dBm, fRF = 3500MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, TC = -40NC to +100NC. Typical values are for TC = +25NC, VCC = 5V, input PRF = 0dBm, fRF = 3500MHz, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = logic 0, unless otherwise noted.) (Notes 5, 7) PARAMETER SYMBOL CTRL Switching Time (Note 9) CS Switching Time (Note 10) MODE Switching Time (Note 11) CONDITIONS MIN TYP 13dB to 0dB range 350 0dB to 13dB range 730 14dB to 0dB range 675 0dB to 14dB range 2300 15dB to 0dB range (MODE 1 to 0) 700 0dB to 15dB range (MODE 0 to 1) 2650 MAX UNITS ns ns ns Input Return Loss 19 dB Output Return Loss 17 dB Group Delay Input/output 50I lines deembedded 200 ps Group Delay Flatness Over 125MHz Band Peak to peak 20 ps Group Delay Change VCTRL = 1V to 4V -120 ps Insertion Phase Change vs. Attenuation Control VCTRL = 1V to 4V 28 S21 Attenuation Deviation from a Straight Line VCTRL = 1.4V to 3.1V Degrees 0.4 dB 20 MHz SERIAL PERIPHERAL INTERFACE (SPI) Maximum Clock Speed Data-to-Clock Setup Time tCS (Note 12) 2 ns Data-to-Clock Hold Time tCH (Note 12) 2.5 ns CS-to-CLK Setup Time tEWS (Note 12) 3 ns CS Positive Pulse Width tEW (Note 12) 7 ns Clock Pulse Width tCW (Note 12) 5 ns Production tested at TC = +100NC. All other temperatures are guaranteed by design and characterization. Recommended functional range. Not production tested. Operation outside this range is possible, but with degraded performance of some parameters. Note 7: All limits include external component losses, connectors and PCB traces. Output measurements taken at the RF port of the Typical Application Circuit. Note 8: fRF1 = 3501MHz, fRF2 = 3500MHz, PRF = 0dBm/tone applied to attenuator input. Note 9: Switching time measured from 50% of the CTRL signal to when the RF output settles to Q1dB (R3 = 0I). Note 10: Switching time measured from when CS is asserted to when the RF output settles to Q1dB. Note 11: Switching time measured from when MODE is asserted to when the RF output settles to Q1dB. Note 12: Typical minimum time for proper SPI operation. Note 5: Note 6: Maxim Integrated 6 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 3500MHz, TC = +25C, unless otherwise noted.). INPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS 13 -10 S22 (dB) -10 S11 (dB) -20 -20 12 -30 TC = -40C -30 -40 10 4.750 4.875 5.000 -40 1500 5.250 5.125 2400 3300 4200 5100 6000 1500 2400 RF FREQUENCY (MHz) VCC (V) S21 vs. RF FREQUENCY OVER CODE SETTINGS INPUT MATCH vs. DAC CODE 4200 5100 6000 OUTPUT MATCH vs. DAC CODE 0 MAX19793 toc04 0 3300 RF FREQUENCY (MHz) 0 6000MHz 3500MHz -10 MAX19793 toc06 11 MAX19793 toc05 SUPPLY CURRENT (mA) TC = +25C 0 MAX19793 toc02 TC = +85C 14 0 MAX19793 toc01 15 OUTPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS MAX19793 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE 6000MHz 3500MHz -10 -20 2000MHz -20 2700MHz -30 1500 2400 3300 4200 5100 2000MHz -30 -40 6000 -20 2700MHz -40 0 RF FREQUENCY (MHz) 256 512 768 1024 256 0 512 DAC CODE S21 vs. DAC CODE -5 1024 S21 vs. DAC CODE 0 MAX19793 toc07 0 768 DAC CODE fRF = 3500MHz -5 MAX19793 toc08 -30 S22 (dB) S11 (dB) S21 (dB) -10 2700MHz -10 2000MHz S21 (dB) S21 (dB) -10 -15 6000MHz -20 -15 -20 TC = -40C, +25C, +85C 3500MHz -25 -25 -30 -30 0 256 512 DAC CODE Maxim Integrated 768 1024 0 256 512 768 1024 DAC CODE 7 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 3500MHz, TC = +25C, unless otherwise noted.). INPUT IP3 vs. CTRL VOLTAGE 0 MAX19793 toc10 45 40 LSB USB 35 2700MHz 512 768 30 1 1024 4 INPUT IP3 vs. CTRL VOLTAGE INPUT IP3 vs. CTRL VOLTAGE TC = -40C, +25C, +85C. LSB, USB 100 MAX19793 toc13 fRF = 2000MHz PIN = 0dBm/ TONE INPUT IP2 (dBm) 40 LSB, USB 35 fRF = 3500MHz PIN = 0dBm/ TONE 3 4 INPUT IP2 vs. CTRL VOLTAGE 45 INPUT IP3 (dBm) 40 80 60 fRF = 5000MHz PIN = 0dBm/ TONE 30 30 2 3 4 40 1 VCTRL (V) 2 3 4 1 2 VCTRL (V) fRF = 3500MHz PIN = 0dBm/ TONE 90 INPUT IP2 (dBm) 90 4 INPUT IP2 vs. CTRL VOLTAGE 100 MAX19793 toc15 fRF = 2500MHz PIN = 0dBm / TONE 3 VCTRL (V) INPUT IP2 vs. CTRL VOLTAGE 100 INPUT IP2 (dBm) 2 VCTRL (V) 50 MAX19793 toc12 45 1 1 VCTRL (V) 50 35 3 2 DAC CODE INPUT IP3 (dBm) fRF = 2500MHz PIN = 0dBm/ TONE 30 -50 256 LSB, USB 35 fRF = 2000MHz PIN = 0dBm/ TONE 2000MHz 0 40 80 70 MAX19793 toc16 -25 45 MAX19793 toc14 3500MHz 25 50 INPUT IP3 (dBm) 50 INPUT IP3 (dBm) S21 PHASE CHANGE (DEG) MAX19793 toc09 REFERENCED TO INSERTION LOSS STATE POSITIVE PHASE = ELECTRICALLY SHORTER 6000MHz 75 INPUT IP3 vs. CTRL VOLTAGE 50 MAX19793 toc11 S21 PHASE CHANGE vs. DAC CODE 100 80 70 TC = -40C, +25C, +85C 60 60 1 2 3 VCTRL (V) Maxim Integrated 4 1 2 3 4 VCTRL (V) 8 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 3500MHz, TC = +25C, unless otherwise noted.). INPUT IP2 vs. CTRL VOLTAGE INPUT P1dB vs. RF FREQUENCY TC = +25C 24 23 TC = +85C TC = -40C 22 60 2 3 21 4 MAX19793 toc19 VCC = 4.75V 2500 3000 3500 2500 2000 RF FREQUENCY (MHz) RESPONSE TIME CTRL VOLTAGE STEP RESPONSE TIME CTRL VOLTAGE STEP -10 S21 (dB) VCTRL STEP FROM 1V TO 3V -15 -20 CS STEP OCCURS AT t = t0 -5 CODE 0 TO 500 CODE 0 TO 640 -10 VCTRL STEP FROM 3V TO 1V -15 VCTRL STEP FROM 4V TO 1V -20 -15 CODE 0 TO 1023 -20 CODE 0 TO 950 VCTRL STEP FROM 1V TO 4V -25 VCTRL STEP OCCURS AT t = t0 -25 -30 -25 -30 500 0 1000 1500 2000 0 TIME (ns) 250 500 750 1000 MODE 1 TO 0 (CODE 700 TO 0) -10 -15 CODE 640 TO 0 -20 CODE 950 TO 0 -20 -25 CODE 1023 TO 0 -25 CS STEP OCCURS AT t = t0 1000 TIME (ns) Maxim Integrated 1500 4000 MAX19793 toc24 -5 CODE 500 TO 0 500 3000 RESPONSE TIME WITH MODE STEP S21 (dB) S21 (dB) -10 2000 0 MAX19793 toc23 -5 0 1000 0 TIME (ns) RESPONSE TIME WITH CS STEP -30 -30 TIME (ns) 0 3500 RESPONSE TIME WITH CS STEP 0 MAX19793 toc21 -5 -10 3000 RF FREQUENCY (MHz) 0 MAX19793 toc20 VCTRL STEP OCCURS AT t = t0 -5 S21 (dB) 23 21 2000 VCTRL (V) 0 VCC = 5.00V 24 22 S21 (dB) 1 VCC = 5.25V MAX19793 toc22 70 25 INPUT P1dB (dBm) 80 26 MAX19793 toc18 25 INPUT P1dB (dBm) INPUT IP2 (dBm) fRF = 5000MHz PIN = 0dBm/ TONE INPUT P1dB vs. RF FREQUENCY 26 MAX19793 toc17 90 MODE 1 TO 0 (CODE 1023 TO 0) MODE 0 TO 1 (CODE 0 TO 700) -15 MODE 0 TO 1 (CODE 0 TO 1023) MODE STEP OCCURS AT t = t0 -30 2000 0 1000 2000 3000 4000 TIME (ns) 9 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 3500MHz, TC = +25C, unless otherwise noted.). INPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS 0 MAX19793 toc26 MAX19793 toc25 TC = +85C 10 0 -10 -10 S22 (dB) TC = +25C S11 (dB) -20 -20 TC = -40C -30 8 3.15 3.20 3.25 3.30 3.35 3.40 -30 -40 3.45 -40 1500 VCC (V) 2400 3300 4200 5100 6000 1500 2400 RF FREQUENCY (MHz) S21 vs. RF FREQUENCY OVER CODE SETTINGS INPUT MATCH vs. DAC CODE 4200 5100 6000 OUTPUT MATCH vs. DAC CODE 0 MAX19793 toc28 0 3300 RF FREQUENCY (MHz) 0 6000MHz 3500MHz -10 MAX19793 toc30 9 MAX19793 toc29 SUPPLY CURRENT (mA) 11 OUTPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS MAX19793 toc27 SUPPLY CURRENT vs. SUPPLY VOLTAGE 6000MHz -10 3500MHz -20 S22 (dB) S11 (dB) S21 (dB) -10 2000MHz -20 2000MHz -20 -30 2700MHz -30 2700MHz -30 2400 3300 4200 5100 6000 -40 0 RF FREQUENCY (MHz) 256 512 768 1024 768 1024 S21 vs. DAC CODE 0 MAX19793 toc31 3500MHz -5 fRF = 3500MHz -5 -10 6000MHz -15 2000MHz -20 S21 (dB) -10 S21 (dB) 512 DAC CODE S21 vs. DAC CODE 0 -15 -20 2700MHz -25 TC = -40C, +25C, +85C -25 -30 -30 0 256 512 DAC CODE Maxim Integrated 256 0 DAC CODE MAX19793 toc32 1500 -40 768 1024 0 256 512 768 1024 DAC CODE 10 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 3500MHz, TC = +25C, unless otherwise noted.). INPUT IP3 vs. CTRL VOLTAGE 40 USB 35 0 2000MHz 512 768 30 1.0 INPUT IP3 vs. CTRL VOLTAGE 45 40 LSB 35 100 fRF = 2000MHz PIN = 0dBm/ TONE 80 60 fRF = 5000MHz PIN = 0dBm/ TONE TC = -40C, +25C, +85C. LSB, USB 2.0 2.5 INPUT IP2 vs. CTRL VOLTAGE USB 35 2.0 VCTRL (V) INPUT IP2 (dBm) 40 40 30 2.5 1.0 VCTRL (V) 2.0 1.5 2.5 1.5 1.0 VCTRL (V) fRF = 3500MHz PIN = 0dBm/ TONE 80 INPUT IP2 (dBm) 80 2.5 INPUT IP2 vs. CTRL VOLTAGE 90 MAX19793 toc39 fRF = 2500MHz PIN = 0dBm/ TONE 2.0 VCTRL (V) INPUT IP2 vs. CTRL VOLTAGE 90 INPUT IP2 (dBm) 1.5 1.0 INPUT IP3 vs. CTRL VOLTAGE INPUT IP3 (dBm) 45 1.5 2.5 50 MAX19793 toc36 fRF = 3500MHz PIN = 0dBm / TONE INPUT IP3 (dBm) 2.0 1.5 VCTRL (V) 50 1.0 fRF = 2500MHz PIN = 0dBm/ TONE 30 1024 DAC CODE 30 LSB 35 70 MAX19793 toc40 256 0 40 fRF = 2000MHz PIN = 0dBm/ TONE 2700MHz -50 45 MAX19793 toc38 3500MHz MAX19793 toc34 45 USB MAX19793 toc37 50 LSB INPUT IP3 (dBm) 6000MHz 50 INPUT IP3 (dBm) 100 MAX19793 toc33 S21 PHASE CHANGE (DEG) REFERENCED TO INSERTION LOSS STATE POSITIVE PHASE = ELECTRICALLY SHORTER INPUT IP3 vs. CTRL VOLTAGE 50 MAX19793 toc35 S21 PHASE CHANGE vs. DAC CODE 150 70 60 60 50 50 TC = -40C, +25C, +85C 1.0 1.5 2.0 VCTRL (V) Maxim Integrated 2.5 1.0 1.5 2.0 2.5 VCTRL (V) 11 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 3500MHz, TC = +25C, unless otherwise noted.). INPUT P1dB vs. RF FREQUENCY 60 18 17 TC = +25C TC = -40C VCC = 3.45V 19 INPUT P1dB (dBm) TC = +85C INPUT P1dB (dBm) INPUT IP2 (dBm) 19 70 20 MAX19793 toc42 MAX19793 toc41 fRF = 5000MHz PIN = 0dBm/ TONE INPUT P1dB vs. RF FREQUENCY 20 MAX19793 toc43 INPUT IP2 vs. CTRL VOLTAGE 80 VCC = 3.3V 18 17 VCC = 3.15V 1.5 1.0 2.0 16 2.5 16 2000 VCTRL (V) RESPONSE TIME CTRL VOLTAGE STEP 3500 2500 2000 RESPONSE TIME CTRL VOLTAGE STEP -20 CS STEP OCCURS AT t = t0 -5 -10 S21 (dB) S21 (dB) -15 RESPONSE TIME WITH CS STEP VCTRL STEP FROM 1.5V TO 1V -10 -15 -20 CODE 0 TO 500 -15 CODE 0 TO 1023 -20 VCTRL STEP FROM 1V TO 2.5V -25 -30 -30 CODE 0 TO 640 CODE 0 TO 950 VCTRL STEP FROM 2.5V TO 1V -25 3500 0 MAX19793 toc45 -5 VCTRL STEP FROM 1V TO 1.5V 3000 RF FREQUENCY (MHz) 0 MAX19793 toc44 VCTRL STEP OCCURS AT t = t0 -5 S21 (dB) 3000 RF FREQUENCY (MHz) 0 -10 2500 MAX19793 toc46 50 -25 VCTRL STEP OCCURS AT t = t0 1000 1500 2000 0 TIME (ns) 250 500 750 1000 S21 (dB) S21 (dB) -5 MODE 1 TO 0 (CODE 1023 TO 0) CODE 950 TO 0 -20 -25 CODE 1023 TO 0 -25 CS STEP OCCURS AT t = t0 1000 TIME (ns) Maxim Integrated 1500 MODE 0 TO 1 (CODE 0 TO 700) -15 -20 500 MODE 1 TO 0 (CODE 700 TO 0) -10 CODE 640 TO 0 0 4000 RESPONSE TIME WITH MODE STEP CODE 500 TO 0 -30 3000 0 MAX19793 toc47 -5 2000 TIME (ns) RESPONSE TIME WITH CS STEP -15 1000 0 TIME (ns) 0 -10 -30 MODE 0 TO 1 (CODE 0 TO 1023) MODE STEP OCCURS AT t = t0 -30 2000 MAX19793 toc48 500 0 0 1000 2000 3000 4000 TIME (ns) 12 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC CS DOUT DIN CLK UP DWN GND TOP VIEW GND VCC Pin Configuration 27 26 25 24 23 22 21 20 19 16 MAX19793 15 11 10 GND 13 12 EP* + GND 1 2 3 4 5 6 7 8 9 MODE COMP_OUT DAC_LOGIC REF_SEL REF_IN VCC GND CTRL 14 GND GND IN_B GND 17 IN_A N.C. VCC GND 18 VCC GND GND GND 28 29 30 31 32 33 34 35 36 OUT_A GND N.C. GND OUT_B TQFN (6mm x 6mm) *INTERNALLY CONNECTED TO GND. Pin Description PIN NAME 1, 3, 6, 7, 9, 10, 12, 26, 27, 28, 30, 33, 34, 36 GND 2 OUT_A Attenuator A RF Output. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. 4, 31 N.C. No Internal Connection. This pin can be left open or ground. Note: If a common layout is desired to support the MAX19794, connect a 0402 capacitor to ground on each of these pins. 5 VCC Attenuator A Power Supply. Bypass to GND with a capacitor and resistor, as shown in the Typical Application Circuit. 8 IN_A Attenuator A RF Input. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. 11 CTRL Attenuator Control Voltage Input. Except in test mode, where no voltage can be applied to this pin. VCC must be present unless using a current-limiting resistor as noted in the Applications Information section. Maxim Integrated DESCRIPTION Ground. Connect to the board's ground plane using low-inductance layout techniques. 13 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Pin Description (continued) PIN NAME DESCRIPTION 13 VCC Analog Supply Voltage. Bypass to GND with a capacitor as close as possible to the device. See the Typical Application Circuit. 14 REF_IN 15 REF_SEL 16 DAC_LOGIC DAC Logic Control Input (Table 1) 17 COMP_OUT Comparator Logic Output. Use a 4.7pF capacitor to reduce any potential rise-time glitching when the comparator changes state. 18 MODE 19 DWN 20 UP 19/20 DWN/UP 21 CLK SPI Clock Input 22 DIN SPI Data Input 23 DOUT 24 CS SPI Chip-Select Input 25 VCC Digital Supply Voltage. Bypass to GND with a capacitor as close as possible to the device. See the Typical Application Circuit. 29 OUT_B 32 VCC Attenuator B Power Supply. Bypass to GND with a capacitor and resistor, as shown in the Typical Application Circuit. 35 IN_B Attenuator B RF Input. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. EP Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple via grounds are also required to achieve the noted RF performance. See the Layout Considerations section. -- Maxim Integrated DAC Reference Voltage Input (Optional) DAC Reference Voltage Selection Logic Input. Logic = 0 to enable on-chip DAC reference. Logic = 1 to use off-chip DAC reference (pin 14). Attenuator Control Mode Logic Input. Logic = 1 to enable attenuator step control. Logic = 0 to enable attenuator SPI control. Down Pulse Input. Logic pulse = 0 for each step-down. Up Pulse Input. Logic pulse = 0 for each step-up. DWN/UP Pulse. Logic = 0 to both pins to reset the attenuator to a minimum attenuation state. SPI Data Output Attenuator B RF Output. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. 14 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Detailed Description The MAX19793 is a dual general-purpose analog VVA designed to interface with 50I systems operating in the 1500MHz to 6000MHz frequency range. Each attenuator provides 23.3dB of attenuation range with a linear control slope of 8.4dB/V. Both attenuators share a common analog control and can be cascaded together to yield 46.6dB of total dynamic range with a combined linear control slope of 16.8dB/V. Alternatively, the on-chip 4-wire SPIcontrolled 10-bit DAC can be used to control both attenuators. In addition, a step-up/down feature allows user-programmable attenuator stepping through command pulses without reprogramming the SPI interface. Applications Information Attenuation Control and Features The device has various states used to control the analog attenuator along with some monitoring conditions. The device can be controlled by an external control voltage, an internal SPI bus, or a combination of the two. The various states are described in Table 1. The SPI bus has multiple registers used to control the device when not configured for the analog-only mode. For cases where CTRL is used, the control range is 1V to 4V for VCC = 5V, and is 1V to 2.5V for VCC = 3.3V. Up to 23.3dB of attenuation control range is provided per attenuator. At the insertion-loss setting, the single attenuator's loss is approximately 4dB. If a larger attenuationcontrol range is desired, the second on-chip attenuator can be connected in series to provide an additional 23.3dB of gain-control range. Note that the on-chip control driver simultaneously adjusts both on-chip attenuators. It is suggested that a current-limiting resistor be included in series with CTRL to limit the input current to less than 40mA, should the control voltage be applied when VCC is not present. A series resistor of greater than 200I provides complete protection for 5V control voltage ranges. Analog-Only Mode Control In the Table 1 state (0, 0), the attenuators are controlled using a voltage applied to the CTRL pin of the device and the on-chip DAC is disabled. In cases where features of the SPI bus are not needed, the part can be operated in a pure analog control mode by grounding pins 14-25. This method allows the MAX19793 to be pin compatible with the MAX19790. Maxim Integrated DAC Mode Control In the Table 1 state (1, 0), the attenuators are controlled by the on-chip 10-bit DAC register. See the Register Mode Up/Down Operation section. In this condition, no signal is applied to the CTRL pin and the load on the CTRL pin should be > 100kI. The DAC is set using the SPI-loaded code in the registers, along with the setting of the MODE pin. Analog Mode Control with Alarm Monitoring In the Table 1 state (0, 1), the attenuators are controlled using a voltage applied to the CTRL pin of the device. See the Register Mode Up/Down Operation section. In this condition, the DAC is enabled and a voltage is also applied to the CTRL pin. The on-chip switches are set to compare the DAC voltage to the CTRL voltage at the comparator input; the output of the comparator (COMP_OUT) trips from high to low when VCTRL exceeds the on-chip DAC voltage. DAC Test Mode In the Table 1 state (1, 1), the attenuators are controlled by the on-chip 10-bit DAC register. See the Register Mode Up/Down Operation section. In this condition, the DAC is enabled and the DAC voltage appears at the CTRL pin. In this condition, no signal can be applied to the CTRL pin and the load on the CTRL pin should be > 100kI. This mode is only used in production testing of the DAC voltage and is not recommended for customer use. Register Mode Up/Down Operation The device has four 13-bit registers that are used for the operation of the device. The first bit is the read/write bit, the following two are address bits, and the remaining 10 are the desired data bits. The read/write bit determines whether the register is being written to or read from. The next two address bits select the desired register to write or read from. These address bits can be seen in Table 2. Table 3 describes the contents of the four registers. Figure 1 shows the configuration of the internal registers of the device and Figure 2 shows the timing of the SPI bus. Register 0 sets the DAC code to the desired value, register 1 selects the step-up code, and register 2 selects the step-down code. The device also contains a mode control pin (Table 4), along with UP and DWN controls (Table 5). When MODE is 0, the contents of register 0 get loaded into the 10-bit DAC register and set the value of the on-chip DAC. In this condition, the UP and DWN control pins have no effect on 15 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC the part. In MODE 1, the effective DAC code fed to the 10-bit DAC register is equal to: m x Register 1 - n x Register 2 where m and n are the number of UP and DWN control steps accumulated, respectively. After powering up the device, UP and DWN should both be set to 0 to reset the m and n counters to 0. This results in a 10-bit all 0 code out of the mathematical block in Figure 1, and applied to the 10-bit DAC register that drives the DAC. To increase (decrease) the code using the UP (DWN) pin, the DWN (UP) pin must be high and the UP (DWN) pin should be pulsed low to high. The device is designed to produce no wraparounds when using UP and DWN stepping so that the DAC code maxes out at 1023 or goes no lower than 0. See Figure 3 for the UP and DWN control operation. Switching back to MODE = 0 produces the same 10-bit DAC code as was previously loaded into register 0. Switching back to MODE = 1 results in the previous 10-bit DAC code from the register 1 and 2 combiner/ multiplier block. Register 3 is used to set the RDBK_EN register in the write mode and is used to read back the RDBK_EN register and COMP_OUT in the read mode. SPI Interface The device can be controlled with a 4-wire, SPI-compatible serial interface. Figure 2 shows a timing diagram for the interface. In the write mode, a 13-bit word is loaded into the device through the DIN pin, with CS set low. The first bit of the word in the write mode is 0, and the next two bits select the register to be written to (Table 2). The next 10 bits contain the data to be written to the selected register. After the 13 bits are shifted in, a low-to-high CS command is applied and this latches the 10 bits into the selected register. The entire write command is ignored if CS is pulsed low to high before the last data bit is successfully captured. For the read cycle, the first bit clocked in is a 1 and this establishes that a register is to be read. The next two clocked bits form the address of the register to be read (Table 2). In this read mode, data starts to get clocked out of the DOUT pin after A0 is captured. The DOUT pin goes to a high-impedance state after the 10 bits are transmitted or if CS goes high at any point during the transmission. Voltage Reference The device has an on-chip voltage reference for the DAC and a provision to operate with an off-chip reference. Table 6 provides details in selecting the desired reference. Table 1. Attenuator Control Logic States DAC_LOGIC RDBK_EN (D9, REG 3) INTERNAL SWITCH STATES 0 0 S1 = closed S2, S3, S4 = open Controlled by an external analog voltage on the CTRL pin. Disabled 1 0 S1, S3, S4 = open S2 = closed Controlled by an on-chip DAC; no voltage is applied to the CTRL pin. Enabled 1 S1, S3, S4 = closed S2 = open 0 1 Maxim Integrated 1 S1, S2 = closed S3, S4 = open ATTENUATOR Controlled by an external analog voltage on the CTRL pin. CTRL is compared with the DAC output. The comparator drives the COMP_OUT pin. Controlled by an on-chip DAC. The DAC output is connected to the CTRL pin. This state can be used to test the DAC output. In this condition, no voltage can be applied to the CTRL pin and the load on this pin must be > 100k. 10-BIT DAC Enabled (update DAC code to estimate voltage on the CTRL pin) Enabled 16 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Table 2. Address Data Bits R/W A1 A0 DESCRIPTION 0 0 0 Write to register 0 using DIN. 0 0 1 Write to register 1 using DIN. 0 1 0 Write to register 2 using DIN. 0 1 1 Write to register 3 using DIN. 1 0 0 Read from register 0 using DOUT. 1 0 1 Read from register 1 using DOUT. 1 1 0 Read from register 2 using DOUT. 1 1 1 Read from register 3 using DOUT. Table 3. Register Definitions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- -- -- -- -- DAC LSB -- -- -- -- -- Step-up LSB REGISTER 0 (Read/Write Bits, 10-Bit DAC Code) DAC MSB -- -- -- REGISTER 1 (Read/Write Bits, 10-Bit Step-Up Code) Step-up MSB -- -- -- REGISTER 2 (Read/Write Bits, 10-Bit Step-Down Code) Step-down MSB -- -- -- -- -- -- -- -- Step-down LSB Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 Not used set = 0 REGISTER 3 (Write Bits)* RDBK_EN Not used set = 0 REGISTER 3 (Read Bits)** RDBK_EN COMP_OUT *RDBK_EN = Enable bit for the voltage comparator that drives the COMP_OUT pin. **RDBK_EN = Enable bit for the voltage comparator that drives the COMP_OUT pin. COMP_OUT = Read logic level of COMP_OUT pin. Maxim Integrated 17 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC DIN DOUT REGISTER 0 MODE OR 10-BIT DAC REGISTER UP m x REGISTER 1 - n x REGISTER 2 m = NUMBER OF UP PULSES n = NUMBER OF DOWN PULSES m REGISTER 1 n REGISTER 2 RESET TO ALL ZEROS WHEN UP/DOWN PULSED TOGETHER DOWN REGISTER 3 Figure 1. Register Configuration Diagram Table 4. Attenuator-Mode Control Logic State MODE PIN ATTENUATOR 0 SPI-mode control (the DAC code is located in register 0). 1 Step-mode control using the UP and DWN pins (the step-up code is located in register 1 and the step-down code is located in register 2). Maxim Integrated 18 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Table 5. Step-Mode Logic State (MODE = 1) UP DWN Logic 0 Logic 0 Reset the DAC for the minimum attenuation state (DAC code = 0000000000). ATTENUATOR Logic 0 pulse Logic 1 Increase the DAC code* by the amount located in register 1. UP is pulsed from high to low to high (see Figure 3). Logic 1 Logic 0 pulse Decrease the DAC code* by the amount located in register 2. DWN is pulsed from high to low to high (see Figure 3). *Continued UP or DWN stepping results in saturation (no code wrapping). Table 6. REF_SEL Logic State REF_SEL DAC REFERENCE 0 Uses an on-chip DAC reference. 1 User provides off-chip DAC reference voltage on REF_IN pin. SPI Interface Programming DIN DOUT R/W A1 A0 HIGHIMPEDANCE D[9:0] TO REGISTER 0, 1, 2, 3 D[9:0] FROM REGISTER 0, 1, 2, 3 1 HIGHIMPEDANCE 0 tCH tCS CLK 1 DWN 0 tEWS CS tCW NO DAC CODE CHANGE tES tEW Figure 2. SPI Timing Diagram Maxim Integrated UP DAC CODE INCREASED BY UP STEP DAC CODE DAC CODE DECREASED RESET TO BY DWN STEP ALL 0's Figure 3. UP/DWN Control Diagram (MODE = 1) 19 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Layout Considerations A properly designed PCB is an essential part of any RF/ microwave circuit. Keep RF signal lines as short as possible to reduce losses, radiation, and inductance. For best performance, route the ground-pin traces directly to the exposed pad underneath the package. This pad MUST be connected to the ground plane of the board by using multiple vias under the device to provide the best RF and thermal conduction path. Solder the exposed pad on the bottom of the device package to a PCB. Pins 4 and 31 for the MAX19793 have no internal connection. These two pins are in place to support the MAX19794 part in the family. The MAX19794 requires an additional bypass capacitor on each of these pins for proper operation. If desired to have a common layout to support the MAX19794, then include these capacitors in the common layout. Refer to the MAX19794 data sheet for details. Table 7. Typical Application Circuit Component Values DESIGNATION QTY DESCRIPTION C1, C2, C4 3 3.9pF Q0.25pF, 50V C0G ceramic capacitors (0402) C3 1 3.9pF Q0.25pF, 50V C0G ceramic capacitor (0402) Not installed for two attenuators in cascade. C5-C9 5 1000pF Q5%, 50V C0G ceramic capacitors (0402) 1 120pF Q5%, 50V C0G ceramic capacitor (0402) Provides some external noise filtering along with R3. C13 0 Not installed, 4.7pF capacitor could be used to reduce any potential rise time glitching when the comparator changes state. R1, R2 2 10I Q5% resistors* (0402) R3 1 200I Q5% resistor (0402) Use this resistor to provide some lowpass noise filtering when used with C12. The value of R3 slows down the response time. R3 also provides protection for the device in case VCTRL is applied without VCC present. U1 1 Maxim MAX19793 C12 Power-Supply Bypassing Proper voltage-supply bypassing is essential for highfrequency circuit stability. Bypass each VCC pin with capacitors placed as close as possible to the device. Place the smallest capacitor closest to the device. See the Typical Application Circuit and Table 7 for details. Exposed Pad RF and Thermal Considerations The exposed pad (EP) of the device's 36-pin TQFN package provides a low thermal-resistance path to the die. It is important that the PCB on which the IC is mounted be designed to conduct heat from this contact. In addition, provide the EP with a low-inductance RF ground path for the device. The EP must be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. Soldering the pad to ground is also critical for efficient heat transfer. Use a solid ground plane wherever possible. Maxim Integrated *Add two additional 10I series resistors between VCC's leading to C5 and C6, unless a VCC power plane is used. 20 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Application Circuit VCC C9 27 C3 RF_AB IN_B GND UP CLK DIN DOUT CS VCC DWN 19 18 EP 17 S3 30 S4 16 S2 ATTEN_B DAC ATTENUATIONCONTROL CIRCUITRY 32 15 14 S1 33 13 34 12 ATTEN_A 35 11 36 10 1 GND C2 20 2 3 4 5 6 R1 VCC 7 8 MODE MODE COMP_OUT COMP_OUT C13 DAC_LOGIC DAC_LOGIC REF_SEL REF_SEL REF_IN VCC GND CTRL GND REF_IN VCC C8 C7 R3 VCTRL C12 9 GND GND 21 DWN MAX19793 29 31 UP IN_A GND CLK GND C6 VCC 22 GND R2 28 23 VCC VCC N.C. 24 N.C. GND 25 GND RFOUT_B OUT_B 26 OUT_A GND C4 GND GND CS DOUT DIN C1 RFIN_A C5 NOTE: FOR ATTENUATOR A ONLY CONFIGURATION, REMOVE C3 AND MOVE C2 DIAGONALLY TO CONNECT PIN 2 TO THE OUTPUT CONNECTION RF_AB. FOR ATTENUATOR B ONLY CONFIGURATION, REMOVE C2. FOR CASCADED CONFIGURATION, REMOVE C3 AND USE C2 TO CONNECT OUT_A TO IN_B. Maxim Integrated 21 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX19793ETX+ -40NC to +100NC 36 TQFN-EP* MAX19793ETX+T -40NC to +100NC 36 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. Chip Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 36 TQFN-EP T3666+2 21-0141 90-0049 PROCESS: SiGe BiCMOS Maxim Integrated 22 MAX19793 1500MHz to 6000MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Revision History REVISION NUMBER REVISION DATE 0 8/12 Initial release -- 1 5/15 Removed military reference from data sheet 1 DESCRIPTION PAGES CHANGED Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2015 Maxim Integrated 23 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX19793ETX+ MAX19793ETX+T MAX19793EVKIT#