M906-01 Datasheet Rev 1.3 Revised 06Jan2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M906-01
VCSO BASED GBE CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
Preliminary Information
GENERAL DESCRIPTION
The M906-01 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. It is ideal for
Gigabit Ethernet. The output clock
(frequency of 156.25 or 187.50MHz
for example) is provided from six
LVPECL clock output pairs. (Specify frequency at time
of order.) The accuracy of the output frequency is
assured by the internal PLL, which phase-locks the
internal VCSO to the reference input frequency (25 or
30MHz for example). The input reference can either
be an external crystal, utilizing the internal crystal
oscillator, or a stable external clock source such as
a packaged crystal oscillator.
FEATURES
◆Output clock frequency from 125MHz to 190MHz
(Consult factory for frequency availability)
◆Six identical LV PE CL output pairs
◆Integrated SAW (surface acoustic wave) delay line
◆Low jitter 0.7ps RMS (over 12kHz-20MHz)
◆Ideal for Gigabit Ethernet clock reference
◆Output-to-output skew < 100ps
◆External XTAL or LVCMOS reference input
◆Selectable external feed-through clock input
◆STOP clock control (Logic 1 stops output clocks)
◆Industrial temperature grade available
◆Single 3.3V power supply
◆Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Output Frequency Configurations
Ref Clock
Frequency
(MHz)
PLL
Ratio
Output
Frequency 1
(MHz)
Note 1:Specify output clock frequency at time of order
Application
20
25/4
156.25 GbE
25 156.25 10GbE
30 187.50 12GbE
Table 1: Example Output Frequency Configurations
M906-01
(Top View)
1
2
3
4
5
6
7
8
9
XTAL_1 / REF_IN
GND
STOP
EXT_CLK
EN_EXT_CLK
NC
nFOUT3
FOUT3
VCC
nFOUT2
FOUT2
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
GND
XTAL_2
FOUT4
nFOUT4
FOUT5
nFOUT5
VCC
DNC
DNC
DNC
nOP_IN
OP_OUT
VC
nVC
nOP_OUT
OP_IN
GND
GND
GND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
M906-01-156.25
XTAL
OSC O
1
External
Crystal
or
Reference
Clock Input
(e.g., 25 or 30MHz)
LVPECL
Output
Clock Pairs
(e.g., 156.25
or 187.50MHz)
Divider
External
Clock
In
p
ut
External
Clock
Select
Output
Clock STOP
Control
VSCO
Frequency
Multiplying
PLL
External
Loop Filter
M906-01 VCSO Based GbE Clock Generator
M906-01 Datasheet Rev 1.3 2 of 6 Revised 06Jan2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M906-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Preliminary Information
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number Name I/O Configuration Description
1, 2, 3, 10, 14, 26 GND Ground Power supply ground connections.
4
9
OP_IN
nOP_IN Input
External loop filter connections. See Figure 4,
External Loop Filter, on pg. 3.
5
8
nOP_OUT
OP_OUT Output
6
7
nVC
VC Input
11, 19, 33 VCC Power Power supply connection, connect to +3.3V.
12
13
FOUT0
nFOUT0
Output No internal terminator Clock output pairs, differential LVPECL output
(156.25 MHz for the M906-01-156.2500)
15
16
FOUT1
nFOUT1
17
18
FOUT2
nFOUT2
20
21
FOUT3
nFOUT3
29
30
FOUT4
nFOUT4
31
32
FOUT5
nFOUT5
23 EN_EXT_CLK Input Internal pull-down resistor1
Note 1: For typical value of internal pull-down resistor, see DC Characteristics, Pull-down on pg. 5 for typical value.
Logic 1 enables the EXT_CLK input.
Use Logic 0 for normal operation.
24 EXT_CLK Input External clock feed-through: 0 to 200 MHz
25 STOP Input Internal pull-down resistor1Logic 1 stops clock outputs.
Use Logic 0 for normal operation.
27 XTAL_1 / REF_IN Input Internal pull-down resistor1External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
28 XTAL_2 Input External crystal connection. Leave unconnected
when driving pin 27 with external clock reference.
34, 35, 36 DNC Do Not Connect.
Table 2: Pin Descriptions
M906-01
XTAL_2
XTAL_1 / REF_IN XTAL
OSC
EXT_CLK
EN_EXT_CLK
STOP
FOUT2
nFOUT2
FOUT4
nFOUT4
FOUT3
nFOUT3
FOUT5
nFOUT5
FOUT0
nFOUT0
FOUT1
nFOUT1
R Divider
R = 4
Phase
Detector
VCSO
SAW Delay Line
Phase
Shifter
VCSO
CPOST
CPOST
VCnVC
RPOST
nOP_OUTOP_OUT
RPOST
RLOOP
RLOOP
CLOOP
CLOOP
RIN
RIN
OP_IN nOP_IN
Loop Filter
Amplifier
External
Loop Filter
Components
M Divider
M = 25
Phase Locked Loop (PLL)
O
1
M906-01 Datasheet Rev 1.3 3 of 6 Revised 06Jan2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M906-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Preliminary Information
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
The M906-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M906-01 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The input reference can either be an external, discrete
crystal device or a stable external clock source such as
a packaged crystal oscillator:
•If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input
pins. External crystal load capacitors are also
required.
•If an external LVCMOS/LVTTL clock source is used,
apply it to the XTAL_1 / REF_IN input pin.
In either case, the reference clock is supplied to the
phase detector of the PLL. The M906-01 includes a
reference divider that divides the input reference
frequency by a fixed value “R” and provides the result to
the phase detector.
The EX_CLK pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
on pg. 4.
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, a feedback divider (labeled
“M Divider”), and a reference divider (“R Divider”).
The feedback divider divides the VCSO output
frequency by a fixed value “M” to match the reference
frequency provided to the phase detector by the
reference divider.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the
reference divider output. This creates an output
frequency that is a multiple of the reference frequency
(which is output from the VCSO).
The relationship between the VCSO output frequency,
the M Divider, the R Divider and the input reference
frequency is defined as follows:
For the M906-01-156.2500
(see “Ordering Information” on pg. 6):
•VCSO output frequency = 156.25MHz
•Input reference frequency = 25MHz
•M=25
•R= 4
Therefore, for the M906-01-156.2500:
25
156.25MHz = 25MHz 4
The product of the input crystal frequency and
falls within the lock range of the VCSO.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M906-01 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
Figure 4: External Loop Filter
Fvcso Fxtal M
R
-----
×=
External Loop Filter Component Values
PLL
Bandwidth
Damping
Factor R loop C loop R post C post
500Hz 2.1 1.5kΩ4.00µF50kΩ3300pF
1.5kHz 3.3 4.7kΩ1.00µF50kΩ1500pF
6.4kHz 4.4 20.0kΩ0.10µF20kΩ470pF
10.6kHz 1
Note 1: Recommended for most applications
4.2 33.0kΩ0.033µF20kΩ470pF
Table 3: External Loop Filter Component Values
----------
×
M
R
-----
CPOST
CPOST
V
C
nVC
RPOST
nOP_OUTOP_OUT
RPOST
RLOOP
RLOOP
CLOOP
CLOOP
OP_IN nOP_IN
6 7549 8
M906-01 Datasheet Rev 1.3 4 of 6 Revised 06Jan2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M906-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Preliminary Information
External Clock Feed-through
The EXT_CLK pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. In application, this may be used for
system debugging and performance evaluation.
1. Set pin EN_EXT_CLK to Logic 1.
2. Apply an external LVCMOS/LVTTL clock source
to the EXT_CLK input pin.
Due to the fact that EXT_CLK bypasses the PLL,
any frequency between DC and 200MHz can be
used.
STOP Clock
The STOP pin puts the output clock into a static condition.
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VIInputs -0.5 to VCC +0.5 V
VOOutputs -0.5 to VCC +0.5 V
VCC Power Supply Voltage 4.6 V
TSStorage Temperature -45 to +100 oC
Table 4: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min Typ Max Unit
VCC Positive Supply Voltage 3.135 3.3 3.465 V
TAAmbient Operating Temperature
Commercial 0+70 oC
Industrial -40 +85 oC
Table 5: Recommended Conditions of Operation
M906-01 Datasheet Rev 1.3 5 of 6 Revised 06Jan2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M906-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Preliminary Information
Integrated
Circuit
Systems, Inc.
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, V
CC
=
3.3
V +
5
%,T
A
=
0
o
C
to +
70
o
C (commercial)
1
, T
A
=
-40
o
C
to +
85
o
C (industrial)
1
,
Output Frequency=156.25MHz
1
,
LVPECL outputs terminated with
50
Ω
to V
CC
- 2V
Symbol Parameter Min Typ Max Unit
Power Supply VCC Positive Supply Voltage 3.135 3.3 3.465 V
ICC Power Supply Current 350 mA
Logic Inputs VIH Input High Voltage
EN_EXT_CLK, EXT_CLK,
STOP
2Vcc +0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH Input High Current 150 µA
IIL Input Low Current -5.0 µA
Reference
Clock
Input
VIH Input High Voltage
XTAL_1 / REF_IN
(XTAL_2 disconnected)
(Vcc / 2 ) +0.5 Vcc +0.3 V
VIL Input Low Voltage -0.3 (Vcc / 2 ) +0.5 V
IIH Input High Current 150 µA
IIL Input Low Current -5.0 µA
All Inputs CIN Input Capacitance, All Inputs EN_EXT_CLK, EXT_CLK,
STOP, XTAL_1 / REF_IN 4pF
Pull-down Rpulldown Internal Pull-down Resistor EN_EXT_CLK, STOP 51 kΩ
Differential
Output
VOH Output High Voltage
FOUT, nFOUT (0-5)
Vcc -1.4 Vcc -1.0 V
VOL Output Low Voltage Vcc -2.0 Vcc -1.7 V
VP-PPeak to Peak Output Voltage 0.6 0.85 V
Table 6: DC Characteristics
Note 1: See Ordering Information on pg. 6
AC Characteristics
Unless stated otherwise, V
CC
=
3.3
V +
5
%,T
A
=
0
o
C
to +
70
o
C (commercial)
1
, T
A
=
-40
o
C
to +
85
o
C (industrial)
1
,
Output Frequency=156.25MHz
1
,
LVPECL outputs terminated with
50
Ω
to V
CC
- 2V
Symbol Parameter Min Typ Max Unit Test Conditions
FOUT Output Frequency Range 125 156.25 190 MHz
FIN Nominal Input Frequency, XTAL_1 / REF_IN 25 MHz
APR VCSO Pull-Range ±100 ±150 ppm
Φn Single Side Band
Phase Noise
@156.25MHz
1kHz Offset -100 dBc/Hz
10kHz Offset -110 dBc/Hz
100kHz Offset -134 dBc/Hz
J(t) Jitter (rms) 0.7 1.0 ps 12kHz to 20MHz
tDC Output Duty Cycle, High Time 45 50 55 %
tROutput Rise Time FOUT, nFOUT (0-1) 350 450 550 ps 20% to 80%
tFOutput Fall Time FOUT, nFOUT (0-1) 350 450 550 ps 20% to 80%
tSOutput Skew Between Any Pair 100 ps
EXT_CLK Frequency EXT_CLK 0 200 MHz
Table 7: AC Characteristics
Note 1: See Ordering Information on pg. 6
M906-01 Datasheet Rev 1.3 6 of 6 Revised 06Jan2004
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M906-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Preliminary Information
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 5: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Part Numbering Scheme
Figure 6: Part Numbering Scheme
Consult factory for frequency availability.
Part Number: M906- 01 - xxx.xxxx
Output Frequency (MHz)
“ -” = 0
to +
70
o
C
(commercial)
See Table 8, right. Consult ICS for other frequencies.
I
= - 40
to +
85
o
C
(industrial)
Temperature
Device Number
Example Part Numbers
Output Freq. (MHz) Temperature Order Part Number
156.25 commercial M906-01 - 156.2500
industrial M906-01
I
156.2500
156.25 commercial M906-01 - 156.2500
industrial M906-01
I
156.2500
187.50 commercial M906-01 - 187.5000
industrial M906-01
I
187.5000
Table 8: Example Part Numbers
