HYM72V8035GS-50 - Siemens Semiconductors

Semiconductor Group 1

8M × 72-Bit EDO- DRAM Module

(ECC - Module)

168 pin buffered DIMM Module

HYM 72V8025GS-50/-60

HYM 72V8035GS-50/-60

•168 pin JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module

for PC main memory applications

•1 bank 8 M x 72 organisation

•Optimized for ECC applications

•Hyper Page Mode - EDO Operation

•Performance:

•Single + 3.3V ± 0.3 V supply

•CAS-before-RAS refresh, RAS-only refresh

•Decoupling capacitors mounted on substrate

•All inputs, outputs and clock fully LVTTL & LVCMOS compatible

•4 Byte interleave enabled, Dual Address inputs (A0/B0)

•Buffered inputs excepts RAS and DQ

•Parallel Presence Detects

•Utilizes nine 8M × 8 -DRAMs and BiCMOS buffers/line drivers VT244A

•Two versions: HYM 72V8035GS with SOJ-components ( 9 mm module thickness)

HYM 72V8025GS with TSOPII-components ( 4 mm module thickness)

•4048 refresh cycles / 64 ms with 12 / 11 addressing

•Gold contact pad

•Double sided module with 25.35 mm (1000 mil) height

-50 -60

tRAC RAS Access Time 50 ns 60 ns

tCAC CAS Access Time 18 ns 20 ns

tAA Access Time from Address 30 ns 35 ns

tRC Cycle Time 84 ns 104 ns

tHPC EDO Mode Cycle Time 20 ns 25 ns

1 3.97

Semiconductor Group 2

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

The HYM 72V8025/35GS-50/-60 is a 64 MByte DRAM module organized as 8 388 608 words by 72-

bit in a 168-pin, dual read-out, single-in-line package comprising nine HYB3165805AJ/AT 8M × 8

DRAMs in 400 mil wide SOJ or TSOPII - packages mounted together with ceramic decoupling

capacitors on a PC board. All inputs except RAS and DQ are buffered by using BiCMOS buffers/

line drivers.

Each HYB3165805AJ/AT is described in the data sheet and is fully electrically tested and

processed according to Siemens standard quality procedure prior to module assembly. After

assembly onto the board, a further set of electrical tests is performed.

The density and speed of the module can be detected by the use of presence detect pins.

Ordering Information

Pin Names

Presence-Detect and ID-pin Truth Table:

Note: 1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high

level all PD terminal are in tri-state.

Type Ordering Code Package Descriptions

HYM 72V8025GS-50 L-DIM-168-3 EDO-DRAM module (access time 50 ns)

HYM 72V8025GS-60 L-DIM-168-3 EDO-DRAM module (access time 60 ns)

HYM 72V8035GS-50 L-DIM-168-3 EDO-DRAM module (access time 50 ns)

HYM 72V8035GS-60 L-DIM-168-3 EDO-DRAM module (access time 60 ns)

A0-A12,B0 Row Address Inputs

A0-A11,B0 Column Address Inputs

DQ0 - DQ71 Data Input/Output

RAS0, RAS2 Row Address Strobe

CAS0 , CAS2 Column Address Strobe

WE0, WE2 Read / Write Input

OE0, OE2 Output Enable

Vcc Power (+3.3 Volt)

Vss Ground

PD1 - PD8 Presence Detect Pins

PDE Presence Detect Enable

ID0 , ID1 ID indentification bit

N.C. No Connection

Module ID0 ID1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8

HYM 728025/35GS-50 Vss Vss 1 0 1 1 1 0 0 0

HYM 728025/35GS-60 Vss Vss 1 0 1 1 1 1 1 0

Semiconductor Group 3

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Pin Configuration

PIN # Symbol PIN # Symbol PIN # Symbol PIN # Symbol

1 VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 OE2 86 DQ36 128 NC

3 DQ1 45 RAS2 87 DQ37 129 NC

4 DQ2 46 CAS4 88 DQ38 130 NC

5 DQ3 47 NC 89 DQ39 131 NC

6 VCC 48 WE2 90 VCC 132 PDE

7 DQ4 49 VCC 91 DQ40 133 VCC

8 DQ5 50 NC 92 DQ41 134 NC

9 DQ6 51 NC 93 DQ42 135 NC

10 DQ7 52 DQ18 94 DQ43 136 DQ54

11 DQ8 53 DQ19 95 DQ44 137 DQ55

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ20 97 DQ45 139 DQ56

14 DQ10 56 DQ21 98 DQ46 140 DQ57

15 DQ11 57 DQ22 99 DQ47 141 DQ58

16 DQ12 58 DQ23 100 DQ48 142 DQ59

17 DQ13 59 VCC 101 DQ49 143 VCC

18 VCC 60 DQ24 102 VCC 144 DQ60

19 DQ14 61 NC 103 DQ50 145 NC

20 DQ15 62 NC 104 DQ51 146 NC

21 DQ16 63 NC 105 DQ52 147 NC

22 DQ17 64 NC 106 DQ53 148 NC

23 VSS 65 DQ25 107 VSS 149 DQ61

24 NC 66 DQ26 108 NC 150 DQ62

25 NC 67 DQ27 109 NC 151 DQ63

26 VCC 68 VSS 110 VCC 152 VSS

27 WE0 69 DQ28 111 NC 153 DQ64

28 CAS0 70 DQ29 112 NC 154 DQ65

29 NC 71 DQ30 113 NC 155 DQ66

30 RAS0 72 DQ31 114 NC 156 DQ67

31 OE0 73 VCC 115 NC 157 VCC

32 VSS 74 DQ32 116 VSS 158 DQ68

33 A0 75 DQ33 117 A1 159 DQ69

34 A2 76 DQ34 118 A3 160 DQ70

35 A4 77 DQ35 119 A5 161 DQ71

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 PD1 121 A9 163 PD2

38 A10 80 PD3 122 A11 164 PD4

39 NC 81 PD5 123 NC 165 PD6

40 VCC 82 PD7 124 VCC 166 PD8

41 NC 83 ID0 (VSS) 125 NC 16 7 ID1 (VSS)

42 NC 84 VCC 126 B0 168 VCC

Semiconductor Group 4

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Block Diagram

I/O1-I/O8

D0 - D4

D5 - D8

D0 - D8

DQ0-DQ7

DQ8-DQ15

RAS0

CAS0

WE0

OE0

DQ16-DQ23

DQ24-DQ31

DQ32-DQ39

DQ40-DQ47

DQ48-DQ55

RAS2

CAS4

WE2

OE2

DQ56-DQ63

DQ64-DQ71

A1-A11

Vcc

Vss D0-D8, buffers

Vcc or Vss PD1-PD8

PDE

Semiconductor Group 5

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Absolute Maximum Ratings

Operating temperature range ......................................................................................... 0 to + 70 °C

Storage temperature range...................................................................................... – 55 to + 125 °C

Input/output voltage ............................................................................... -0.5 to min (Vcc+0.5, 4.6) V

Power supply voltage................................................................................................. – 0.5V to 4.6 V

Power dissipation.................................................................................................................... 5,8 W

Data out current (short circuit) ................................................................................................ 50 mA

Note:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage to the device. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

DC Characteristics

A = 0 to 70 °C;

CC = 3.3 V ± 0.3 V

Parameter Symbol Limit Values Unit Test

Condition

min. max.

Input high voltage

IH 2.0 Vcc + 0.3 V 1)

Input low voltage

IL – 0.3 0.8 V 1)

Output high voltage (LVTTL)

Output „H“ level voltage (

OUT = – 2 mA)

OH 2.4 – V 1)

Output low voltage (LVTTL)

Output „L“ level voltage (

OUT = + 2 mA)

OL – 0.4 V 1)

Output high voltage (LVCMOS)

Output „H“ level voltage (

OUT = – 100 µA)

OH Vcc-0.2 – V 1)

Output low voltage (LVCMOS)

Output „L“ level voltage (

OUT = + 100 µA)

OL – 0.2 V 1)

Input leakage current

(0 V <

IN < Vcc, all other pins = 0 V)

I(L) – 20 20 µA1)

Output leakage current

(DO is disabled, 0 V <

OUT < Vcc)

O(L) – 20 20 µA1)

Average

CC supply current: -50 version

-60 version

(RAS, CAS, address cycling,

RC =

RC min.)

CC1 –

–1260

1080 mA

2) 3) 4)

Standby

CC supply current

(RAS = CAS =2.4V, one address change

within 15,6 µs trc)

CC2 –50mA–

Semiconductor Group 6

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Capacitance

A = 0 to 70 °C;

CC = 3.3 V ± 0.3 V;

= 1 MHz

Average

CC supply current during RAS

only refresh cycles: -50 version

-60 version

(RAS cycling, CAS =

, t

RC =

RC min.)

CC3

–

–1260

1080 mA

2) 4)

Average

CC supply current during hyper

page mode (EDO): -50 version

-60 version

(RAS =

IL, CAS, address cycling

PC =

PC min.)

CC4

–

–945

765 mA

2) 3) 4)

Standby

CC supply current

(RAS = CAS =

CC – 0.2 V,

one address change within 15,6 µs trc)

CC5 –30mA–

Average

CC supply current during

CAS-before-RAS refresh mode: -50 version

-60 version

(RAS, CAS cycling

, t

RC =

RC min.)

CC6

–

–1260

1080 mA

2) 4)

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A11,B0)

I1 –10pF

Input capacitance (RAS0, RAS2)

I2 –50pF

Input capacitance (CAS0, CAS4)

I3 –15pF

Input capacitance (WE0,WE2,OE0,OE2)

I4 –15pF

I/O capacitance (DQ0-DQ71)

IO1 –15pF

Parameter Symbol Limit Values Unit Test

Condition

min. max.

Semiconductor Group 7

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

AC Characteristics (note: 5,6,7,8)

A = 0 to 70 °C,

CC = 3.3 ± 0.3 V

Parameter Symbol -50 -60 Unit Note

min. max. min. max.

common parameters

Random read or write cycle time tRC 84 – 104 – ns

RAS precharge time tRP 30 – 40 – ns

RAS pulse width tRAS 50 100k 60 100k ns

CAS pulse width tCAS 8 10k 10 10k ns

Row address setup time tASR 5–5–ns

Row address hold time tRAH 6–8–ns

Column address setup time tASC 2–2–ns

Column address hold time tCAH 13 – 15 – ns 9

RAS to CAS delay time tRCD 10 32 12 40 12

RAS to column address delay time tRAD 8 201025ns12

RAS hold time tRSH 18 – 20 – ns 9

CAS hold time tCSH 38 – 48 – ns 10

CAS to RAS precharge time

CRP 10 – 10 – ns 9

Transition time (rise and fall) tT130130ns

Refresh period tREF –64–64ms

Read Cycle

Access time from RAS tRAC –50–60ns

13,14

Access time from CAS tCAC –18–20ns

9,13,14

Access time from column address tAA –30–35ns

9,13, 15

OE access time tOEA –18–20ns

9,13

Column address to RAS lead time tRAL 30 – 35 – ns 9

Read command setup time tRCS 2–2–ns

Read command hold time tRCH 2–2–ns

11,16

Read command hold time referenced

to RAS tRRH 0–0–ns

CAS to output in low-Z tCLZ 2–2–ns

11,13

Output buffer turn-off delay tOFF –18–20ns

9,17

Semiconductor Group 8

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Output buffer turn-off delay from OE tOEZ –18–20ns

9,17

CAS delay time from Din tDZC 0–0–ns

Data to OE low delay tDZO 0–0–ns

CAS high to data delay tCDD 15 – 18 – ns 9,19

OE high to data delay tODD 15 – 18 – ns 9,19

Write Cycle

Write command hold time tWCH 13 – 15 – ns 9

Write command pulse width tWP 8–10–ns

Write command setup time tWCS 2–2–ns

11,20

Write command to RAS lead time tRWL 18 – 20 – ns 9

Write command to CAS lead time tCWL 13 – 15 – ns

Data setup time tDS -2 – -2 – ns 10,21

Data hold time tDH 13 – 15 – ns 9,21

Read-Modify-Write Cycle

Read-write cycle time tRWC 118 – 143 – ns 9

RAS to WE delay time tRWD 66 – 77 – ns 11,21

CAS to WE delay time tCWD 29 – 34 – ns 11,21

Column address to WE delay time tAWD 41 – 49 – ns 11,21

OE command hold time tOEH 8–11–ns10

Hyper Page Mode (EDO) Cycle

Fast page mode cycle time tPC 20 – 25 – ns

CAS precharge time tCP 8–10–ns

Access time from CAS precharge tCPA –32–37ns

9,13

Output data hold time tCOH 3–3–ns

RAS pulse width tRAS 50 200k 60 200k ns

CAS precharge to RAS Delay tRHCP 32 – 37 – ns 9

OE setup time prior to CAS tOES 5–5–ns

AC Characteristics (cont’d) (note: 5,6,7,8)

A = 0 to 70 °C,

CC = 3.3 ± 0.3 V

Parameter Symbol -50 -60 Unit Note

min. max. min. max.

Semiconductor Group 9

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Fast Page Mode Read-Modify-Write

Cycle

Fast page mode read-write cycle time tPRWC 60 – 70 – ns 11

CAS precharge to WE tCPWD 43 – 51 – ns 11,21

CAS-before-RAS Refresh Cycle

CAS setup time tCSR 12 – 12 – ns 11

CAS hold time tCHR 8–8–ns10

RAS to CAS precharge time tRPC 5–5–ns

Write to RAS precharge time tWRP 12 – 12 – ns 11

Write hold time referenced to RAS tWRH 8–8–ns10

Presence Detect Read Cycle

PDE to valid presence detect data tPD –10–10ns

PDE inactive to presence detects

inactive tPDOFF 010010ns

AC Characteristics (cont’d) (note: 5,6,7,8)

A = 0 to 70 °C,

CC = 3.3 ± 0.3 V

Parameter Symbol -50 -60 Unit Note

min. max. min. max.

Semiconductor Group 10

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

Notes:

1) All voltages are referenced to VSS.

2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.

3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.

4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less

during a hyper page mode (EDO) cycle ( thpc).

5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper

device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS

initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume tT = 2 ns.

7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are

measured between VIH and VIL.

8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE,

addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are

not buffered, which preserves the DRAMs access specification of 50ns and 60ns.

9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers.

10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers.

11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers.

12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line

drivers.

13) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. Access time is determined

by the latter of tRAC, tCAC, tAA, tCPA, tOEA. tCAC is measured from tristate.

14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tR C D (max.) is specified as a

reference point only: If t RCD is greater than the specified tRCD (max.) limit, then access time is controlled by

tCAC.

15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a

reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by

tAA.

16) Either tRCH or tRRH must be satisfied for a read cycle.

17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are

not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CA S, whichever

occurs last.

18) Either tDZC or tDZO must be satisfied.

19) Either tCDD or tODD must be satisfied.

20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin

will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD

(min.) , tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will

contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition

of the I/O pins (at access time) is indeterminate.

21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-

Modify-Write cycles.

Waveforms:

For waveforms see “168 pin fast-page mode DIMM modules waveforms“

Semiconductor Group 11

HYM72V8025/35GS-50/-60

8M x 72-ECC EDO-Module

L-DIM-168-3

Module package

(dual read-out, single in-line memory module)

133,35

184

17,78

25,40

10 11 40 41

* )

preliminary drawing

168

3,0

127,35

124 125

*) 4.00 max for modules assembled with TSOPII-packages

9.00 max for modules assembled with SOJ-packages

DM168-3.WMF

6,35

2,0

3,125

Detail C

2,54 min.

1,27 1,0 + 0.5

Detail BDetail A

6,35

2,0

3,125

0,2 0,15

94 95