M50FW040K5TG - Micron Technology Inc.

October 2006 Rev 9 1/53

M50FW040

4-Mbit (512 Kb x8, uniform block)

3-V supply firmware hub Flash memory

Feature summary

■Supply voltage

–V

CC = 3 V to 3.6 V for Program, Erase and

Read operations

–V

PP = 12V for fa st Erase (optional)

■Two interfaces

– Firmware hub (FWH) interface for

embedded operation with PC chipsets

– Address/Address Multiplexed (A/A Mux)

interface for programming equipment

compatibility

■Firmware hub (FWH) hardware inter face mode

– 5-signal communication interface

supporting Read and Write operations

– Hardware Write Protect pins for block

protection

– Register based Read and Write protection

– 5 additional general-purpose inputs for

platform design flexibility

– Synchronized with 33-MHz PCI clock

■Programming time: 10 µs typical

■8 uniform 64 Kbyte memory blocks

■Program/Erase Controller

– Embedded Byte Program and Block Erase

algorithms

– Status Register bits

■Program and Erase Suspend

– Read othe r blocks during Program/Erase

Suspend

– Program other blocks during Erase

Suspend

■For use in PC Bios applications

■Electronic signature

– Manufacturer code: 20h

– Device code: 2Ch

■Packages

– ECOPACK® (RoHS compliant)

TSOP40 (N)

10 × 20mm

PLCC32 (K)

TSOP32 (NB)

8 × 14mm

www.st.com

Contents M50FW040

2/53

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Firmware hub (FWH) signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.1 Input/Output communications (FWH0-FWH3) . . . . . . . . . . . . . . . . . . . . 12

2.1.2 Input communication frame (FWH4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.3 Identification inputs (ID0-ID3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.4 General-purpose inputs (FGPI0-FGPI4) . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.5 Interface configuration (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.6 Interface Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.7 CPU Reset (INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.8 Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.9 Top Block Lock (TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.10 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.11 Reserved for future use (RFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Address/Address multiplexed (A/A Mux) signal descriptions . . . . . . . . . . 14

2.2.1 Address inputs (A0-A10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.3 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.4 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.5 Row/Column Address Select (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.6 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.2 VPP optional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Firmware hub (FWH) bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.3 Bus Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

M50FW040 Contents

3/53

3.1.6 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Address/Address multiplexed (A/A Mux) bus operations . . . . . . . . . . . . . 19

3.2.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.0.1 Program/Erase Controller status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.0.2 Erase Suspend status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.0.3 Erase status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.0.4 Program status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.0.5 VPP status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.0.6 Program Suspend status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.0.7 Block Protection status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.0.8 Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Firmware hub (FWH) interface Configuration Registers . . . . . . . . . . . 30

6.1 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1.1 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1.2 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1.3 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2 Firmware Hub (FWH) General-Purpose Input Register . . . . . . . . . . . . . . 31

6.3 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4 Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.5 Firmware Hub (FWH) General-Purpose Input Register . . . . . . . . . . . . . . 31

Contents M50FW040

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6.6 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7 Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Pr ogram and Erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12 Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

M50FW040 List of tables

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List of tables

Table 1. Signal names (FWH interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Signal names (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. FWH bus Read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. FWH bus Write field definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Read electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Firmware hub Configuration Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Lock Register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 11. General-Purpose Input Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12. Program and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 14. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 15. FWH interface AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16. A/A Mux interface AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 17. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 19. FWH interface clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 20. FWH interface AC signal timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 21. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 22. A/A Mux interface read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 23. A/A Mux interface Write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of figures M50FW040

6/53

List of figures

Figure 1. Logic diagram (FWH interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Logic diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. PLCC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. TSOP32 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. TSOP40 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. FWH Bus Read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. FWH Bus Write waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. FWH interface AC testing input output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 9. A/A Mux interface AC testing input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 10. FWH interface clock waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. FWH interface AC signal timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13. A/A Mux interface Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14. A/A Mux interface Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package outline . . . . . . . . . . 44

Figure 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline . . . . . . . . . . . . 45

Figure 17. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, package outline . . . . . . . . . . . 46

Figure 18. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 19. Program Suspend & Resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 20. Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 21. Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

M50FW040 Summary description

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1 Summary description

The M50FW040 is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and

reprogr amm ed. These op er ations can b e performed using a single low voltage (3.0 to 3. 6V)

supply. For fast erasing in production lines an optional 12V power supply can be used to

reduce the erasing time.

The memory is divided into blocks that can be erased independently so it is possible to

preserve valid data while old data is erased. Blocks can be protected individually to preven t

accidental Program or Erase commands from modifying the memory. Progr am and Erase

commands are written to th e Command Interf ace o f the memory. An on-chip Progr am/Erase

Controller simplifies the process of programming or erasing the memory by taking care of all

of the special operations that are required to update the memory contents. The end of a

program or erase operation can be detected and any error conditions identified. The

command set required to control the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by the memory. The primary interface, the

Fir mware Hub (or FWH) Interface, uses Intel’s proprietar y FWH protocol. This ha s be en

designed to remove the need for the ISA bus in current PC Chipsets; the M50FW040 acts

as the PC BIOS on the Low Pin Count bus for these PC Chipsets.

The secondary interface, the Address/Address Mult iplexed (or A/A Mux) Interface, is

designed to be com patib le with cur rent Flash Prog rammer s f or prod uction line prog r amming

prior to fitting to a PC Moth er bo a rd .

The memory is offere d in TSOP32 (8 x 14mm), TSOP40 (10 x 20mm) and PLCC32

packages and it is supplied with all the bits erased (set to ’1’).

In order to meet environmental requirements, ST offers the M50FW040 in ECOPACK®

pac kages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST

tradem ark. ECOPACK specifications are a vailable at: www.st.com.

Summary description M50 FW040

8/53

Figure 1. Logic diagram (FWH interface)

Table 1. Signal names (FWH i n terface)

FWH0-FWH3 Input/Output Communications

FWH4 Input Communication Fr ame

ID0-ID3 Identification Inputs

FGPI0-FGPI4 Gener al Purpose Inputs

IC Interfa c e Configuration

RP Interface Reset

INIT CPU Reset

CLK Clock

TBL Top Block Loc k

WP Write Protect

RFU Reserved for Future Use. Leave disconnected

VCC Supply Voltage

VPP Optional Supply Voltage for Fast Erase Operations

VSS Ground

NC Not Connected Internally

AI03623

FWH4

FWH0-

FWH3

VCC

M50FW040

CLK

VSS

TBL

INIT

ID0-ID3

FGPI0-

FGPI4

VPP

M50FW040 Summary description

9/53

Figure 2. Logic diagram (A/A Mux Interface)

Table 2. Signal names (A/A Mux interface)

IC Interfa c e Configuration

A0-A10 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

GOutput Enable

WWrite Enable

RC Row/Column Address Select

RB Ready/Busy Output

RP Interface Reset

VCC Supply Voltage

VPP Optional Supply Voltage for Fast Program and Erase Operations

VSS Ground

NC Not Connected Internally

AI10719

DQ0-DQ7

VCC

M50FW040

VSS

A0-A10

VPP

Summary description M50 FW040

10/53

Figure 3. PLCC connections

1. Pins 27 and 28 are not internally connected.

Figure 4. TSOP32 connections

1. the RB pin is not available for the A/A Mux interface in the TSOP32 package.

AI03616

FGPI4

FWH4

RFU

ID1

ID0

FWH0

FWH1

FWH2

FWH3

RFU

FGPI1

TBL

ID3

ID2

FGPI0

CLK

VSS

VCC

FGPI2

RFU

VPP

VCC

M50FW040

FGPI3

IC (VIL)

RFU

INIT

RFU

VSS

DQ0

A10

VPP

VCC

VSS

VCC

DQ7

IC (VIH)

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

VSS

A/A Mux A/A Mux

A/A MuxA/A Mux

AI10718

DQ0

A4 A3

DQ7

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A/A Mux

ID1

FWH1/LAD1

FWH2/LAD2

GPI3

TBL ID2

GPI0

RFU

GPI4

NC FWH4/LFRAME

RFU

FWH3/LAD3

VSS

RFU

CLK

VPP

VCC M50FW040

16 17

ID3/RFU

VSS

INIT

GPI2 FWH0/LAD0

GPI1 ID0

IC (VIH)

VPP

VCC

A10

VSS

M50FW040 Summary description

11/53

Figure 5. TSOP40 connections

AI03617

DQ0

A4 A3

VSS

VCC

DQ7

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A/A Mux

ID1

FWH1

FWH2

FGPI3

TBL ID2

FGPI0

VCC

IC (VIL)

RFU

FGPI4

VSS

FWH4

RFU

FWH3

VSS

VCC

RFU

CLK

VPP

VCC

M50FW040

20 21

ID3

NC INIT

NC RFU

FGPI2 FWH0

FGPI1 ID0

VSS

IC (VIH)

VPP

VCC

A10

VSS

VCC

Signal descriptions M50FW040

12/53

2 Signal descriptions

There are two different bus interfaces available on this part. The active interface is selected

before power-up or during Reset using the Interface Configuration Pin, IC.

The signals for each interface are discussed in the Firmware hub (FWH) signal descriptions

section and the Address/Address multiplexed (A/A Mux) signal descriptions section below.

The supply signals are discussed in the Supply signal descriptions section below.

2.1 Firmware hub (FWH) signal descriptions

For the F irmware Hub (FWH) Inte rface see <Blue>Fi g ure 1. , L o gic dia gram (FWH

interface), and <Blue>Table 1., Signal names (FWH interface).

2.1.1 Input/Output comm unications (FWH0-FWH3)

All Input and Output Communication with the memory take place on these pins. Addresses

and Data for Bus Read and Bus Write operations are encoded on these pins.

2.1.2 Input communication frame (FWH4)

The Input Communication Frame (FWH4) signals the start of a bus operat ion. When Input

Communication Frame is Low, VIL, on the rising edge of the Clock a new bus operation is

initiated. If Input Communication Frame is Low, VIL, during a bus operation then the

operation is aborted. When Input Communication Frame is High, VIH, the current bus

operat ion is proceeding or the bus is idle.

2.1.3 Identification inputs (ID0-ID3)

The Identification Inputs select the address that the memory responds to. Up to 16

memories can be addressed on a b us. For an address bit to be ‘0’ the pin can be left floatin g

or driven Low, VIL; an internal pull-down resistor is included with a value of RIL. For an

address bit to be ‘1’ the pin must be driven High, VIH; there will be a leakage current of ILI2

through each pin when pulle d to VIH; see <Blue>Table 18.

By convention the b oot m emo ry must ha ve address ‘000 0’ and all ad diti onal me mories take

sequential addresses starting from ‘0001’.

2.1.4 General-purpose inputs (FGPI0-FGPI4)

The Gener al Purpose Inputs can be used as digital inputs for the CPU to read. Th e Gener al

Purpose Input s Register holds the values on these pins. The pins must have stable data

from before the start of the cycle that reads the General Purpose Input Register until after

the cycle is complete . Thes e pins m ust n ot be left to f loat, the y should be driv en L o w, VIL, or

High, VIH.

M50FW040 Signal descriptions

13/53

2.1.5 Interface configuration (IC)

The Interface Configuration input selects whether the Firmware Hub (FWH) or the

Address/Address Mult iplexed (A/A Mux) Interface is used. The chosen interface must be

selected before power-up or during a Reset and, thereafter, cannot be changed. The state

of the Interface Configuration, IC, should not be changed during operation.

To select the Firmware Hub (FWH) Inter f ace the Int erf ace Co nfigurat ion pin should be left to

float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the

pin should be driv en High , VIH. An internal pull-down resistor is included with a value of RIL;

there will be a leakage current of ILI2 through each pi n when p ulled t o VIH; see <Blue>Tab le

18.

2.1.6 Interface Reset (RP)

The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is

set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the

current consumption is minimized. When RP is set High, VIH, the memory is in normal

operation. After exiting Reset mode, the memory enters Read mode.

2.1.7 CPU Reset (INIT)

The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves

identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

2.1.8 Clock (CLK)

The Clock, CLK, input is used to clock the signals in and out of the Input/Output

Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification.

2.1.9 Top Block Lock (TBL)

The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed.

When Top Block Lock, TBL, is set Low, VIL, Program and Erase operatio ns in the Top Block

have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is

set High, VIH, the protection of the Block is determined by the Lock Register. The state of

Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 6).

Top Block Loc k, TBL, must be set prior to a Program or Erase operation is initiated and must

not be changed until the operation completes or unpr edictable results may occur. Care

should be taken to avoid unpredictable behavior by changing TBL during Program or Erase

Suspend.

Signal descriptions M50FW040

14/53

2.1.10 Write Protect (WP)

The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being

changed. When Write Protect, WP, is set Low, VIL, Program and Erase operations in the

Main Blocks have no effect, regardless of the state of the Lock Register. When Write

Protect, WP, is set High, VIH, the protection of the Block determined by the Lock Register.

The state of Wr ite Prot ec t, WP, does not affect the protection of the Top Block (Block 7).

Write Protect, WP, must be set prior to a Program or Erase operation is initiated and must

not be changed until the operation completes or unpr edictable results may occur. Care

should be taken to avoid unpredictable behavior by changing WP during Program or Erase

Suspend.

2.1.11 Reserved for future use (RFU)

These pins do not have assigned functions in this revision of t he part. They must be left

disconnected.

2.2 Address/Address multiplexed (A/A Mux) signal descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see <Blue>Figure 1., Logic

diagram (FWH interface), and <Blue>Table 1., Signal names (FWH interface).

2.2.1 Address inputs (A0-A10)

The Address Inputs are used to set the Row Address bits (A0-A10) and the Column

Address bits (A11-A18). They are latched during any bus operation by the Row/Column

Address Select input, RC.

2.2.2 Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs hold the data that is written to or read from the memory. They

output the data stored at the selected address during a Bus Read operation. During Bus

Write operations they represent the commands sent to the Command Interface of the

internal state machine. T he Da ta Inp uts/Ou tput s, DQ0-DQ7, are latched during a Bus Write

operation.

2.2.3 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

2.2.4 Write Enable (W)

The Write Enab le , W, controls the Bus Write operation of the memory’s Command Interface.

2.2.5 Row/Column Address Select (RC)

The Row/Column Address Select input selects whether the Addre ss Inputs should be

latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The

Row Address bits are latched on the falling edge of RC whereas the Column Address bits

are latched on the rising edge.

M50FW040 Signal descriptions

15/53

2.2.6 Ready/Busy Output (RB)

The Ready/Busy pin gives the status of the memory’s Program/Erase Controller. When

Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will

not accept any additional Program or Erase command except the Program/Erase Suspend

command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or

Erase operation.

2.3 Supply signal descriptions

The Supply Signals are the same for both interfaces.

2.3.1 VCC supply voltage

The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout

Voltage, VLKO. This prevents Bus Write oper ations from accidentally damaging the data

during pow er up, power down and power surges. If the Program/Erase Controller is

progr amming or erasin g during this time then th e operation abo rts and the memory contents

being altered will be invalid. After VCC becomes valid the Command Interface is reset to

Read mode.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS

Ground pin to deco uple the curr ent su rges fr om th e po w er supply. Both VCC Supply Voltage

pins must be connected to the power supply. The PCB track widths must be sufficient to

carry the curren ts required during program and erase operations.

2.3.2 VPP optional supply voltag e

The VPP Optional Supply Voltage pin is used to select the Fast Erase option of the memory

and to protect the memory. When VPP < VPPLK Program and Erase opera tions cannot be

performed and an error is reported in the Status Register if an attempt to change the

memory contents is made. When VPP = VCC Program and Erase operations take place as

normal. When VPP = VPPH Fast Erase operations are used. Any other voltage input to VPP

will result in undefined behavior and should not be used.

VPP should not be set to VPPH for more than 80 hours during the life of the memory.

2.3.3 VSS ground

VSS is the reference for all the voltage measurements.

Signal descriptions M50FW040

16/53

Table 3. Bloc k addresses

Size

(Kbytes) Address Range Block Number Block Type

64 70000h-7FFFFh 7 Top Block

64 60000h-6FFFFh 6 Main Block

64 50000h-5FFFFh 5 Main Block

64 40000h-4FFFFh 4 Main Block

64 30000h-3FFFFh 3 Main Block

64 20000h-2FFFFh 2 Main Block

64 10000h-1FFFFh 1 Main Block

64 00000h-0FFFFh 0 Main Block

M50FW040 Bus operations

17/53

3 Bus operations

The two inte rfaces have similar bus operations but the signals and timings are completely

different. The Firmware Hub (FWH) Interf ace is the usual interface and all of the functionality

of the part is available through this interface. Only a subset of functions are available

through the Address/Address Multiplexed (A/A Mux) Interface.

Follow the section Firmware h ub (FWH) bus operations below and the section

Address/Address multiplexed (A/A Mux) bus operations below for a description of the bus

operat ions on each interface.

3.1 Firmware hub (FWH) bus operations

The Firmware Hub (FWH) Interf ace consists of f our data si gnals (FWH0-FWH3), one control

line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data

corruption can be achieved using two further signals (TBL and WP). Finally two reset

signals (RP and INIT) are available to put the memory into a known state.

The data signals, control signal and clock are designed to be compatible with PCI electrical

specifications. The interface operates with clock speeds up to 33MHz.

The f ollowing oper ations can be perf ormed using the ap propriate bus cycles: Bus Read, Bus

Write, Standby, Reset and Block Protection.

3.1.1 Bus Read

Bus Read operations read from the memor y cells, specific registers in the Command

Interface or Firmware Hub Registers. A valid Bus Re ad operation starts when Input

Communication Frame, FWH4, is Low, VIL, as Clock rises and the correct Start cycle is on

FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select,

Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync

data until the wait-states h ave elapsed followed by Data0-Data3 and Data4-Data7.

Ref er to Table 4: FWH b us Re ad fiel d d efinit ion s, and Figu re 6: FWH Bus Read wa veforms,

for a description of the Field definitions for each clock cycle of the transfer. See Table 20:

FWH interface AC signal timing characteristics, and Figure 11: FWH interface AC signal

timing waveforms, for details on the timings of the signals.

3.1.2 Bus Write

Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid

Bus Write operation starts when Input Communication Frame, FWH4, is Low, VIL, as Clock

rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host

will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7

on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed.

Refer to Table 5: FWH bus Write field definitions, and Figure 7: FWH Bus Write waveforms,

for a description of the Field definitions for each clock cycle of the transfer. See Table 20:

FWH interface AC signal timing characteristics, and Figure 11: FWH interface AC signal

timing waveforms, for details on the timings of the signals.

Bus operations M50FW040

18/53

3.1.3 Bus Abort

The Bus Abort operatio n can be used to immediatel y abort the current b us oper ation. A Bus

Abort occurs when FWH4 is driven Low, VIL, during the bus operation; the memory will tri-

state the Input/Output Communication pins, FWH0-FWH3.

Note that, during a Bus Write operation, the Command Interface starts executing the

command as soon as the data is fully received; a Bus Abort during the final TAR cycles is

not guaranteed to abort the command; the bus, however, will be released immediately.

3.1.4 Standby

When FWH4 is High, VIH, the memory is put into Standby mode where FWH0-FWH3 are

put into a high-impedance state and the Supply Current is reduced to the Standby l evel,

ICC1.

3.1.5 Reset

During Reset mode all internal circuits are switched of f, the memory is deselected and the

outputs are put in high -impedance. The me mory is in Reset mode when Interf ace Reset, RP,

or CPU Reset, INIT, is Low, VIL. RP or INIT must be held Low, VIL, for tPLPH. The memory

resets to Read mode upon return from Reset mode and the Lock Registers return to their

default states regardless of their state before Reset, see Table 10 If RP or INIT goes Low,

VIL, during a Progr am or Erase operation, the operation is aborted and the memory cells

affected no longer contain valid data; the memory can take up to tPLRH to abort a Program

or Erase operation.

3.1.6 Block Protection

Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect,

WP, regardless of the state of the Lock Registers.

M50FW040 Bus operations

19/53

3.2 Address/Address multiplexed (A/A Mux) bus operations

The Address/Addre ss Multi plex ed (A/A Mux) I nterface has a more tr aditio nal style in terface .

The signals consist of a m ultiplex ed address sig nals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory.

The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash

Programming equipment for faster factory programming. Only a subset of the features

available to the Firmware Hub (FWH) Interface are available; these include all the

Commands but exclude the Security features and other registers.

The f ollowing oper ations can be perf ormed using the ap propriate bus cycles: Bus Read, Bus

Write, Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are

unprotected. It is not possible to protect any blocks through this interface.

3.2.1 Bus Read

Bus Read oper ations are used to output the contents of the Memory Array, the Electronic

Signature and the Status Register. A valid Bus Read operation begins by latching the Row

Address and Column Address signals into the memory using the Address Inputs, A0-A10,

and the Row/Column Address Select RC. Then Write Enable (W) and Interface Reset (RP)

must be High, VIH, and Output Enable, G, Low, VIL, in order to perform a Bus Read

operation. The Data Inputs/Outputs will output the value, see Figure 13, and Table 22: A/A

Mux interface read AC characteristics, for details of when the output becomes valid.

3.2.2 Bus Write

Bus Write operations write to the Command I nterf ace. A v alid Bus Write operat ion begins b y

latching the Row Address and Column Address signals into the memo ry using the Address

Inputs, A0-A10, and the Row/Column Address Select RC. The da ta sh ould be set up on t he

Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and

Write Enable, W, must be Low, VIL. The Data Inputs/Outputs are latched on the rising edge

of Write Enable, W. See Figure 14: A/A Mux interface Write AC waveforms, and Table 23:

A/A Mux interface Wr ite AC characteristics, for details of the timing require ments.

3.2.3 Output Disable

The data outpu ts are high-impedance when the Output Enable, G, is at VIH.

3.2.4 Reset

During Reset mode all internal circuits are switched of f, the memory is deselected and the

outputs are put in high-impedance. The memory is in Reset mode when RP is Low, VIL. RP

must be held Low , VIL for tPLPH. If RP is goes Low, VIL, during a Program o r Erase oper ation,

the operation is aborted and the memory cells affected no longer contain valid data; the

memory can take up to tPLRH to abort a Program or Erase operation.

Bus operations M50FW040

20/53

Figure 6. FWH Bus Read waveforms

Table 4. FWH bus Read field definitions

Clock

Cycle

Number

Clock

Cycle

Count Field FWH0-

FWH3 Memory

I/O Description

1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the

contents of FWH0-FWH3 indicate the start of a FWH

Read cycle.

2 1 IDSEL XXXX I

Indicates which FWH Flash Memory is selected. The

value on FWH0-FWH3 is compared to the IDSEL

strapping on the FWH Flash Memory pins to select

which FWH Flas h Me mo ry is being addressed.

3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with

the most significant nibble first.

10 1 MSIZE 0000b I Always 0000b (only single byte transfers are

supported).

11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a

tur naround cycle.

12 1 TAR 1111b

(float) OThe FWH Flash Memory takes control of FWH0-

FWH3 during this cycle.

13-14 2 WSYN

C0101b O

The FWH Flash Memo ry drives FWH0-FWH3 to

0101b (short wait-sync) for two clock cycles,

indicating that the data is not yet available. Two wait-

states are always included.

15 1 RSYN

C0000b O The FWH Flash Memor y drives FWH0-FWH3 to

0000b, indicating that data will be available during

the next clock cycle.

16-17 2 DATA XXXX O Data transfer is two CLK cycl es, starting with the

least significant nibble.

18 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to

1111b to indicate a turnaround cycle.

19 1 TAR 1111b

(float) N/A The FWH Flash Memory floats its outputs, the host

takes control of FWH0-FWH3.

AI03437

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START IDSEL ADDR MSIZE TAR SYNC DATA TAR

11712322

M50FW040 Bus operations

21/53

Figure 7. FWH Bus Writ e wavef o rms

Tabl e 5. FWH bus Write field definitions

Clock

Cycle

Number

Clock

Cycle

Count Field FWH0-

FWH3 Memory

I/O Description

1 1 START 1110b I On the rising edge of CLK with FWH4 Low, the

contents of FWH0-FWH3 indicate the start of a

FWH Write Cycle.

2 1 IDSEL XXXX I

Indicates which FWH Flash Memory is selected.

The value on FWH0-FWH3 is compared to the

IDSEL strapp ing on the FWH Flash Memory pins to

select which FWH Flash Memory is being

addressed.

3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with

the most significant nibble first.

10 1 MSIZE 0000b I Always 0000b (single byte tr ansfer).

11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least

significant nibble.

13 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate

a tur naround cycle.

14 1 TAR 1111b

(float) OThe FWH Flash Memory takes control of FWH0-

FWH3 during this cycle.

15 1 SYNC 0000b O The FWH Flash Me mory drives FWH0-FWH3 to

0000b, indicating it has received data or a

command.

16 1 TAR 1111b O The FWH Flash Memory driv es FWH0-FWH3 to

1111b, indicating a turnaround cycle.

17 1 TAR 1111b

(float) N/A The FWH Flash Memory floats its outputs and the

host takes control of FWH0-FWH3.

AI03441

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

11712212

Command interface M50FW040

22/53

4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface.

Commands consist of one or more sequential Bus Write operations.

After power-up or a Reset oper ation the memory enters Read mode.

The commands are summariz ed in Table 7: Commands. Ref er to Table 7 in conjunction with

the text descriptions below.

4.1 Read Memory Array command

The Read Memory Array command returns the memory to its Read mode wher e it behaves

like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array

command and retu rn the memory to Read mode . Once the command is issu ed the memo ry

remains in Read mode until another command is issued. From Read mode Bus Read

operations will access the memory array.

While the Prog r a m/ Er ase Co nt rol ler is executing a Prog r am or Er ase o peration the memory

will not accept the Read Memory Array command until the operation completes.

4.2 Read Status Register command

The Read Status Register command is used to read the Status Register. One Bus Write

cycle is required to issue the Re ad Status Register co mmand. Once the command is issued

subsequent Bus Read operations re ad the Status Register until another command is issued .

See the section on the Status Register for details on the definitions of the Status Register

bits.

4.3 Read Electronic Signature command

The Read Electronic Signature command is used to read the Manufacturer Code and the

Device Code. One Bus Write cycle is required to issue the Read Electronic Signature

command. Once the command is issued subsequent Bus Read operations read th e

Manufacturer Code or the Device Code until another command is issued.

After the Read Electronic Sign ature Command is i ssued the Manufacturer Code and Device

Code can be read using Bus Read operations using the addresses in Table 6.

M50FW040 Command interface

23/53

4.4 Program command

The Prog ram command can be used to prog ram a v alue to one address in the memory arra y

at a time. Two Bus Write operations are required to issue the command; the second Bus

Write cycle latches the address and data in the internal state machine an d starts the

Program/Erase Controller. Once the command is issued subsequent Bus Read operations

read the Status Reg ister . Se e the section on the Stat us Register f or details on th e definitions

of the Status Register bits.

If the address fa lls in a protected block then the Prog ram operation will abort, the data in the

memor y array will not be changed and the Status Register will output the error.

During the Program operation the memory will only accept the Read Status Register

command and the Program/Erase Suspend command. All other commands will be ignored.

Typic al Pro gram times are given in Table 12.

Note that the Prog ram command cannot change a bit set a t ‘0 ’ back to ‘1’ and attempting t o

do so will not cause any modification on its value. The Erase command must be used to set

all of the bits in the block to ‘1’.

See Figur e 18: Progra m flowchart and pseud o code, for a suggested flowchart on using t he

Program command.

4.5 Erase command

The Erase command can be used to erase a block. Two Bus Write operations are required

to issue the command; the se co nd Bus Write cycle latches the block ad dre ss in t he internal

state machine and starts the Program/Erase Controller. Once the command is issued

subsequent Bus Read operations read the Status Register. See the section on the Status

If the block is protected then the Erase operation will abort, the data in the block will not be

changed and the Status Register will output the error.

During the Erase operation the memory will only accept the Read Status Register command

and the Program/Erase Suspend command. All other commands will be ignored. Typical

Erase times are given in Table 12.

The Erase command sets all of the bits in the block to ‘1’. All previous data in the block is

lost.

See Figure 20: Erase flowchart and pseudo code, for a suggested flowchart on using the

Erase command.

4.6 Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status

Once the command is issued the memory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new

Progr am or Erase co mmand is issued. If an error occurs then it is essential to clear any error

bits in the Status Register by issuing the Clear Status Register command before attempting

a new Program or Erase command.

Command interface M50FW040

24/53

4.7 Program/Erase Suspend command

T he Pr ogr am/E ra se Suspend command can b e used to pau se a Prog r am or Era se o per ation .

One Bus Write cycle is required to issue the Program/Er ase Suspend command and pause

the Progr am/Erase Controller. Once the command is issued it is necessary to poll the

Program/Erase Controller Status bit to find out when the Pr ogram/Erase Controller has

paused; no other commands will be accepted until the Program/Erase Controller has

paused. After the Program/Eras e Controller has paused, the memory will continue to output

the Status Register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the

Program/Erase Controller pausing it is possible for the operation to complete. Once

Progr am/Erase Co ntroller Status bit indicates that the Program/Er ase Controller is no longer

active, the Program Suspend Status bit or th e Erase Suspend Status bit can be used to

determine if the operation has completed or is suspended. For timing on the delay between

issuing the Program/Erase Suspend command and the Program/Erase Controller pausing

see Table 12.

During Program/Erase Suspe nd the Rea d Me m ory Array, Read Stat us Re gister, Read

Electronic Signature and Program/Erase Resume commands will be accepted by the

Command Interface. Additionally, if the suspended operation was Erase then the Program

command will also be accepted; only the blocks not being erased may be read or

programmed correctly.

See Figure 19: Program Suspend & Resume flowchart and pseudo code, and Figure 21:

Erase Suspend & Resume flowchart and pseudo code, for suggested flowcharts on using

the Program/Erase Suspend command.

4.8 Program/Erase Resume command

Th e P r o gr a m / E ras e R e s u m e command can be used to restart the Program /Era se Contro ller

after a Progr am/Er ase Suspen d oper ation has paused it. One Bus Write cycle is required to

issue the Prog ram/Er ase Resume command. O nce the command is issued sub sequent Bus

Read operations read the Status Register.

Table 6. Read electronic signature

Code Address Data

Manufacturer code 00000h 20h

Device code 00001h 2Ch

M50FW040 Command interface

25/53

Table 7. Commands(1)

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

Command

Cycles

Bus Write operations

1st 2nd

Address Data Address Data

Read Memory Array(2)

2. Read Memory Array. After a Read Memory Array command, read the memory as normal until another

command is issued.

1 X FFh

Read Status Register(3)

3. Read Status Register. After a Read Status Register command, read the Status Register as normal until

another command is issued.

1 X 70h

Read Electronic Signature(4)

4. Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code,

Device Code until another command is issued.

1 X 90h

1 X 98h

Program(5)

5. Erase, Program. After these commands read the Status Register u ntil the command completes and

another command is issued.

2 X 40h PA PD

2 X 10h PA PD

Erase(5) 2 X 20h BA D0h

Clear Status Register(6)

6. Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register

are reset to ‘0’

1 X 50h

Program/Erase Suspend(7)

7. Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read

Memory Array, Read Status Register, Program (during Erase suspend) and Program/Erase resume

commands.

1X B0h

Program/Erase Resume(8)

8. Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase

operation resumes, read the Status Register until the Program/Erase Controller completes and the

memory returns to Read Mode.

1X D0h

Invalid/Reserved(9)

9. Invalid/Reserved. Do not use Invalid or Reserved commands.

1 X 00h

1 X 01h

1 X 60h

1X 2Fh

1X C0h

Status Register M50FW040

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5 Status Register

The Status Register provides information on the current or previous Program or Erase

operat ion. Diff erent b its in the Status Reg ister con v e y diff er ent inf ormation and errors on t he

operation.

To read the Status Register the Read Status Register command can be issued. The Status

commands are issued. The Status Register can be read from any address.

The Status Register bits are summarized in Status Register bits. Refer to Table 8 in

conjunction with the text descriptions below.

5.0.1 Program/Erase Contro ller status (Bit 7)

The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is

active or inactive. When the Program/Erase Controller Status bit is ‘0’, the Program/Erase

Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive.

The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend

command is issued until the Program/Erase Controller pauses. After the Program/Erase

Controller pauses the bit is ‘1’.

During Program an d Erase operation the Pr og ram/Erase Controller St atus bit can be p olled

to find the end o f the operation. The other bits in the Status Register should not be tested

until the Program/Erase Controller completes the operation and the bit is ‘1’.

After the Program/Erase Controller completes its operation the Erase Status, Program

Status, VPP Status and Block Protection Status bits should be tested for errors.

5.0.2 Erase Suspend status (Bit 6)

The Erase Suspend Sta tus bit indicates that an Er ase oper ation has been suspended and is

waiting t o be resumed. The Erase Suspe nd Status should only be considered v alid when the

Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); af ter a

Program/Erase Suspend command is issued the memory may still complete the operation

rather than entering the Suspend mode.

When the Erase Suspend Stat us bit is ‘0’ the Program/Erase Controller is active or has

completed its operation; when the bit is ‘1’ a Program/Erase Suspend comm and has been

issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the Erase Suspend Status bit returns

to ‘0’.

M50FW040 Status Register

27/53

5.0.3 Erase status (Bit 5)

The Erase Status bit can be used to identify if the memory has applied the maximum

number of erase pulses to the block and still failed to verify that the block has erased

correctly. The Erase Status bit should be read once the Progr am/ Er ase Controller St atus bit

is ‘1’ (Program/Erase Controller inactive).

When the Erase Status bit is ‘0’ the memory has successfully verified that the block has

erased correc tly; when the Erase Status bit is ‘1’ the Program/Erase Controller has applied

the maximum number of pulses to the bl ock and still f ailed to v erify that the bl ock has erased

correctly.

Once the Erase Stat us bit is set to ‘1’ the it can only be reset to ‘0’ by a Clear Status

Program or Erase command is issued, otherwise the new command will appear to fa il.

5.0.4 Program status (Bit 4)

The Program Status bit can be used to identify if the memory has applied the maximum

number of program pulses to the b yte and still failed to verify that the byte has programmed

correctly. The Program Status bit should be read once the Pr og ram/Erase Controller Status

bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has successfully verified that the byte has

progr ammed corr ectly; wh en the Prog r am Status bi t is ‘1’ the Prog r am/Er ase Controlle r has

applied the maximum number of pulses to the byte and still failed to verify that the byte has

programmed correctly.

Once the Progr am Stat us bit is set to ‘1’ it ca n only be reset to ‘0’ b y a Clear Status Re gister

command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or

Erase command is issued, otherwise the new command will appear to fail.

5.0.5 VPP status (Bit 3)

The VPP Status bit can be used to ide nti fy an invalid voltage on the VPP pin du ring Program

and Erase operations. The VPP pin is only sa mpled at the beginning of a Program or Erase

operation. Indeterminate results can occur if VPP becomes invalid during a Program or

Erase operation.

When the VPP Status bit is ‘0’ the voltage on the VPP pin was sample d at a valid volta g e;

when the VPP Status bit is ‘1’ the VPP pin has a voltage that is below the VPP Lo ckout

Voltage, VPPLK, the memory is protected; Program and Erase operation cannot be

performed.

Once the VPP Status bit set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or

Erase command is issued, otherwise the new command will appear to fail.

Status Register M50FW040

28/53

5.0.6 Program Suspend status (Bit 2)

The Program Suspend Status bit indicates that a Program operation has been suspended

and is w aiting to be re sumed. The Prog ram Susp end Status should on ly be considered v alid

when the Prog ram/Erase Contro ller Status bit is ‘1’ (Program/Erase Controller inactive);

after a Program/Erase Suspend command is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has

completed its operation; when the bit is ‘1’ a Program/Erase Suspend comm and has been

issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the Program Suspend Status bit

returns to ‘0’.

5.0.7 Block Protection status (Bit 1)

The Bloc k Protection Status bit can be used to ident ify if the Progr am or Erase operat ion has

tried to mod ify th e con te n ts of a pr ot ected block. When th e Block Protecti on Statu s bit is to

‘0’ no Program or Erase operations have been attempted to protected blocks since t he last

Clear Status Register command or ha rdware reset; when the Blo ck Protection Status bit is

‘1’ a Program or Erase operation has been attempted on a protected block.

Once it is set to ‘1’ the Block Protection Status bit can only be reset to ‘0’ by a Clear Status

Program or Erase command is issued, otherwise the new command will appear to fa il.

Using the A/A Mux Interface the Block Protection Status bit is always ‘0’.

5.0.8 Reserved (Bit 0)

Bit 0 of the Status Register is reserved. Its value should be masked.

M50FW040 Status Register

29/53

Table 8. Status Register bits

Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Program active ‘0’ X(1)

1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’

Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘0’ ‘1’ ‘0’ ‘0’

Program failure due to Block Protection (FWH

Interface only) ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘1’

Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase activ e ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase failure due to VPP Error ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’

Erase failure due to Block Protection (FWH

Interface only) ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’

Erase failure due to failed cell(s) in bloc k ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’

Firmware hub (FWH) interface Configuration Registers M50FW040

30/53

6 Firmware hub (FWH) interface Configuration

Registers

When the Firmware Hub Interface is selected several additional registers can be accessed.

These registers control the protection status of the Blocks, read the General Purpose Input

pins and identify th e me m ory using the Elec tr on ic S ign at ur e code s. See Table 9 for the

memory map of the Configuration Registers.

6.1 Lock Registers

The Loc k Registers control the prot ection status of the Blo c ks . Each Blo c k has its o wn Lo c k

Loc k Bit, the Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written, though care should be taken when writing as,

once the Loc k Down Bit is set, ‘1’, further modificat ions to the Lock Regist er cannot be made

until cleared, to ‘0’, by a reset or power-up.

See Table 10 for details on the bit definitions of the Lock Reg isters.

6.1.1 Write Lock

The Write Lock Bit determines whether the co ntents of t he Bloc k can be mo dified (u sing the

Program or Erase Command). When the Write Lock Bit is set, ‘1’, the block is write

protected; any oper ations that attempt to change the data in the bloc k will fail and the Status

protected through the Lock Register and may be modified unless write protected through

some other means.

When VPP is less than VPPLK all bloc ks are pr otected and cann ot be modifi ed, regardle ss of

the state of the Write Loc k Bit. If Top Block Lock, TBL, is Lo w, VIL, then the Top Block (Bloc k

7) is write protected and cann ot be modi fied. Similarly, if Write Protect, WP, is Low, VIL, then

the Main Blocks (Blocks 0 to 6) are write protected and cannot be modified.

After power-up or reset the Write Loc k Bit is always set to ‘1’ (write protected).

6.1.2 Read Lock

The Read Lock bit determines whether the contents of the Block can be read (from Read

mode). When t he Read Lock Bit is set, ‘1’, the bloc k is read protected; any operation that

attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is

reset, ‘0’, read operations in the Block return the data programmed into the block as

expected.

After power-up or reset the Read Lock Bit is always reset to ‘0’ (not read protected).

M50FW040 Firmware hub (FWH) interface Configuration Registers

31/53

6.1.3 Lock Down

The Lock Down Bit provides a mechanism fo r protecting software data from simple hacking

and malicious attack. When the Lock Down Bit is set, ‘1’, further modificati on to the Write

Loc k, Rea d Lo ck and Lock Down Bits cannot be performed. A reset or powe r-up is requ ired

before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write

Lock, Read Lock and Lock Down Bits can be chan ged.

6.2 Firmware Hub (FWH) General-Purpose Input Register

The Firmware Hub (FWH) General Purpose Input Register holds t he state of the Firmw are

Hub Interface General Purpose Input pins, FGPI0-FGPI4. When this register is read, the

state of these pins is returned. This register is read-only and writing to it has no effect.

The signals on the Firmware Hub Interface General Purpose Input pins should remain

constant throughout the whole Bus Read cycle in order to guarantee that the correct data is

read.

6.3 Manufacturer Code Register

Reading the Manufacturer Code Register returns the manufacturer code for the memory.

The manufacturer code for STMicroelectronics is 20h. This reg ister is read-only and writing

to it has no effect.

6.4 Device Code Register

Reading the Device Code Register returns the device code fo r the memory, 2Ch. This

6.5 Firmware Hub (FWH) General-Purpose Input Register

The Firmware Hub (FWH) General Purpose Input Register holds t he state of the Firmw are

Hub Interface General Purpose Input pins, FGPI0-FGPI4. When this register is read, the

state of these pins is returned. This register is read-only and writing to it has no effect.

The signals on the Firmware Hub Interface General Purpose Input pins should remain

constant throughout the whole Bus Read cycle in order to guarantee that the correct data is

read.

6.6 Manufacturer Code Register

Reading the Manufacturer Code Register returns the manufacturer code for the memory.

The manufacturer code for STMicroelectronics is 20h. This reg ister is read-only and writing

to it has no effect.

Firmware hub (FWH) interface Configuration Registers M50FW040

32/53

6.7 Device Code Register

Reading the Device Code Register returns the device code fo r the memory, 2Ch. This

Table 9. Firmware hub Configuration Register map

Mnemonic Register Name Memory

Address Default

Value Access

T_BLOCK_LK Top Block Lock Register (Block 7) FBF0002h 01h R/W

T_MINUS01_LK Top Block [-1] Lock Register (Block 6) FBE0002h 01h R/W

T_MINUS02_LK Top Block [-2] Lock Register (Block 5) FBD0002h 01h R/W

T_MINUS03_LK Top Block [-3] Lock Register (Block 4) FBC0002h 01h R/W

T_MINUS04_LK Top Block [-4] Lock Register (Block 3) FBB0002h 01h R/W

T_MINUS05_LK Top Block [-5] Lock Register (Block 2) FBA0002h 01h R/W

T_MINUS06_LK Top Block [-6] Lock Register (Block 1) FB90002h 01h R/W

T_MINUS07_LK Top Block [-7] Lock Register (Block 0) FB80002h 01h R/W

FGPI_REG Fir m ware Hub (FWH) General Purpose Input

MANUF_REG Manufacturer Code Regi ster FBC0000h 20h R

DEV_REG Device Code Register FBC0001h 2Ch R

Table 10. Loc k Register bit definitions(1)

1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to

Top Block [-7] Lock Register (T_MINUS07_LK).

Bit Bit name Value Function

7-3 Reserved

2Read-

Lock

‘1’ Bus Read operations in this Block always return 00h.

‘0’ Bus read operations in this Block return the Memo ry Array contents.

(Default value).

1Lock-

Down

‘1’

Changes to the Read-Lock bit and the Write-Lock bit cannot be

performed. Once a ‘1’ is written to the Lock-Down bit it cannot be cleared

to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP or INIT) or

after power-up.

‘0’ Read-Lock and Write -L ock can be changed by writing new values to

them. (Default value).

0Write-

Lock

‘1’ Program and Erase operations in this Block will set an error in the Status

‘0’ Program and Erase operations in this Block are executed and will modify

the Bloc k co ntents.

M50FW040 Firmware hub (FWH) interface Configuration Registers

33/53

Table 11. General-Purpose Input Register definition(1)

1. Applies to the General Purpose Inputs Register (FGPI-REG).

Bit Bit Name Value Function

7-5 Reserved

4FGPI4 ‘1’ Input Pin FGPI4 is at VIH

‘0’ Input Pin FGPI4 is at VIL

3FGPI3 ‘1’ Input Pin FGPI3 is at VIH

‘0’ Input Pin FGPI3 is at VIL

2FGPI2 ‘1’ Input Pin FGPI2 is at VIH

‘0’ Input Pin FGPI2 is at VIL

1FGPI1 ‘1’ Input Pin FGPI1 is at VIH

‘0’ Input Pin FGPI1 is at VIL

0FGPI0 ‘1’ Input Pin FGPI0 is at VIH

‘0’ Input Pin FGPI0 is at VIL

Program and Erase times M50FW040

34/53

7 Program and Erase times

The Program and Erase times are shown in Table 12.

Table 12. Program and Erase times

Parameter Test Condition Min Typ(1)

1. TA = 25°C, VCC = 3.3 V.

Max Unit

Byte Program 10 200 µs

Block Program 0.4 5 s

Block Erase VPP = 12V ± 5% 0.75 8 s

VPP = VCC 110s

Program/Erase Suspend to Pro gram

pause(2)

2. Sampled only, not 100% tested.

5µs

Program/Erase Suspend to Block Erase

pause(2) 30 µs

M50FW040 Maximum rating

35/53

8 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 13. Absolute maximum ratings

Symbol Parameter Min Max Unit

TSTG Storage Temperature –65 150 °C

VIO (1)

1. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions. Maximum Voltage may

overshoot to VCC + 2V and for less than 20ns during transitions.

Input or Output Voltage –0.6 VCC + 0.6 V

VCC Supply Voltage –0.6 4 V

VPP Program Voltage –0.6 13 V

DC and AC parameters M50FW040

36/53

9 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 14, Table 15 and Table 16. Designers should check that the operating conditions in

their circuit match the operating conditio ns when relying on the quoted par ameters.

Figure 8. FWH interface AC testin g input output waveforms

Table 14. Operating conditions

Symbol Parameter Min Max Unit

TAAmbient Operating Temperature (Devic e Grade 5) –20 85 °C

VCC Supply Voltage 3 3.6 V

Table 15. FWH interface AC measurement conditions

Parameter Value Unit

Load Capacita nce (C L)10pF

Input Rise and Fall Times ≤ 1.4 ns

Input Pulse Voltages 0.2 VCC and 0.6 VCC V

Input and Output Timing Ref. Voltages 0.4 VCC V

Table 16. A/A Mux inter face AC measurement conditions

Parameter Value Unit

Load Capacita nce (C L)30pF

Input Rise and Fall Times ≤ 10 ns

Input Pulse Voltages 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 V

AI03404

0.6 VCC

0.2 VCC

0.4 VCC

IO > ILO

IO < ILO IO < ILO

Input and Output AC Testing Waveform

Output AC Tri-state Testing Waveform

M50FW040 DC and AC parameters

37/53

Figure 9. A/A Mux interface AC testing input output waveform

Table 17. Impedance(1)

1. TA = 25 °C, f = 1 MHz).

Symbol Parameter Test Condition Min Max Unit

CIN(2)

2. Sampled only, not 100% tested.

Input Capacitance VIN = 0V 13 pF

CCLK(2) Clock Capacitance VIN = 0V 3 12 pF

LPIN(3)

3. See PCI Specification.

Recommended pin inductance 20 nH

AI01417

1.5V

DC and AC parameters M50FW040

38/53

Table 18. DC characteristics

Symbol Parameter Interface Test Condition Min Max Unit

VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V

A/A Mux 0.7 VCC VCC + 0.3 V

VIL Input Low Voltage FWH –0.5 0.3 VCC V

A/A Mux -0.5 0.8 V

VIH(INIT)INIT Input High

Voltage FWH 1.35 VCC + 0.5 V

VIL(INIT)INIT Input Low

Voltage FWH –0.5 0.2 VCC V

ILI(2) Input Leakage

Current 0V ≤ VIN ≤ VCC ±10 µA

ILI2 IC, IDx Input

Leakage Current IC, ID0, ID1, ID2, ID3 = VCC 200 µA

RIL IC, IDx Input Pull

Low Resistor 20 100 kΩ

VOH Output High

Voltage FWH IOH = –500µA 0.9 VCC V

A/A Mux IOH = –100µAV

CC – 0.4 V

VOL Output Low Voltage FWH IOL = 1.5mA 0.1 VCC V

A/A Mux IOL = 1.8mA 0.45 V

ILO Output Leakage

Current 0V ≤ VOUT ≤ VCC ±10 µA

VPP1 VPP Voltage 3 3.6 V

VPPH VPP Voltage

(Fast Erase) 11.4 12.6 V

VPPLK(1) VPP Lockout

Voltage 1.5 V

VLKO(1) VCC Lockout

Voltage 1.8 2.3 V

ICC1 Supply Current

(Standby) FWH

FWH4 = 0.9 VCC, VPP = VCC

All other inputs 0.9 VCC to

0.1 VCC

VCC = 3.6V, f(CLK) = 33MHz

100 µA

ICC2 Supply Current

(Standby) FWH

FWH4 = 0.1 VCC, VPP = VCC

All other inputs 0.9 VCC to

0.1 VCC

VCC = 3.6V, f(CLK) = 33MHz

10 mA

ICC3

Supply Current

(Any internal

operation active) FWH VCC = VCC max, VPP = VCC

f(CLK) = 33MHz

IOUT = 0mA 60 mA

ICC4 Supply Current

(Read) A/A Mux G = VIH, f = 6MHz 20 mA

M50FW040 DC and AC parameters

39/53

1. Sampled only, not 100% tested.

2. Input leakage currents include High-Z output leakage for all bidirectional buffers with tri-state outputs.

Figure 10. FWH interface clock waveform

1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz

devices may be guaranteed by design rather than tested. Refer to PCI Specification.

ICC5(1) Supply Current

(Program/Erase) A/A Mux Program/Erase Controller

Active 20 mA

IPP VPP Supply Current

(Read/Standby) VPP > VCC 400 µA

IPP1(1) VPP Supply Current

(Program/Erase

active)

VPP = VCC 40 mA

VPP = 12V ± 5% 15 mA

Table 19. FWH interface clock characteristics

Symbol Parameter Test Condition Value Unit

tCYC CLK Cycle Time(1) Min 30 ns

tHIGH CLK High Time Min 11 ns

tLOW CLK Low Time Min 11 ns

CLK Slew Rate peak to peak Min 1 V/ns

Max 4 V/ns

Table 18. DC characteristics (continued)

Symbol Parameter Interface Test Condition Min Max Unit

AI03403

tHIGH tLOW

0.6 VCC

tCYC

0.5 VCC

0.4 VCC

0.3 VCC

0.2 VCC

0.4 VCC, p-to-p

(minimum)

DC and AC parameters M50FW040

40/53

Figure 11. FWH interface AC signal timing waveforms

AI03405

tCHQV

tCHQX

tCHQZ

tCHDX

VALID

FWH0-FWH3

tDVCH

CLK

VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

Table 20. FWH interface AC signal timing characteristics

Symbol PCI Symbol P arameter Test Condition Value Unit

tCHQV tval CLK to Data Out Min 2 ns

Max 11 ns

tCHQX(1) ton CLK to Active (Float to Active Delay) Min 2 ns

tCHQZ toff CLK to Inactive (Active to Float Delay) Max 28 ns

tAVCH

tDVCH tsu In put Set-up Time(2) Min 7 ns

tCHAX

tCHDX thInput Hold Time(2) Min 0 ns

1. The timing measurements for Active/Float transitions are def ined when the current through the pin equals the leakage

current specification.

2. Applies to all inputs except CLK.

M50FW040 DC and AC parameters

41/53

Figure 12. Reset AC waveforms

Table 21. Reset AC characteristics

Symbol Parameter Test Condition Value Unit

tPLPH RP or INIT Reset Pulse Width Min 100 ns

tPLRH RP or INIT Low to Reset Program/Erase Inactive Max 100 ns

Program/Erase Active Max 30 µs

RP or INIT Slew Rate(1)

1. See Chapter 4 of the PCI Specification.

Rising edge only Min 50 mV/ns

tPHFL RP or INIT High to FWH4 Low FWH Interface only Min 30 µs

tPHWL

tPHGL

RP High to Write Enable or

Output Enable Low A/A Mux Interface only M in 50 µs

AI03420

RP, INIT

W, G, FWH4

tPLPH

tPLRH

tPHWL, tPHGL, tPHFL

DC and AC parameters M50FW040

42/53

Figure 13. A/A Mux in terface Read AC waveforms

Table 22. A/A Mux interface read AC characteristics

Symbol Parameter Test Condition Value Unit

tAVAV Read Cycle Time Min 250 ns

tAVCL Row Address Valid to RC Low Min 50 ns

tCLAX RC Low to Row Address Transition Min 50 ns

tAVCH Column Address Valid to RC high Min 50 ns

tCHAX RC High to Column Address

Transition Min 50 ns

tCHQV(1)

1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.

RC High to Output Valid Max 150 ns

tGLQV(1) Output Enable Low to Output Valid Max 50 ns

tPHAV RP High to Row Address Valid Min 1 µs

tGLQX Output Enable Low to Output

Transition Min 0 ns

tGHQZ Output Enable High to Output Hi-Z Max 50 ns

tGHQX Output Hold from Output Enable

High Min 0 ns

AI03406

tAVAV

tCLAX tCHAX

tGLQX

tGLQV

tGHQX

VALID

A0-A10

DQ0-

DQ7

tCHQV

tGHQZ

COLUMN ADDR VALID

tPHAV

ROW ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

M50FW040 DC and AC parameters

43/53

Figure 14. A/A Mux interface Write AC waveforms

AI04185

tCLAX

tCHAX

tWHDXtDVWH

VALID SRD

A0-A10

DQ0-DQ7

tCHWH

tWHRL

tAVCL

tAVCH

R2 C2

tWLWH

tWHWL

VPP

tVPHWH tWHGL

tQVVPL

DIN1 DIN2

Write erase or

program setup

Write erase confirm or

valid address and data

Automated erase

or program delay Read Status

another command

Table 23. A/A Mux interface Write AC characteristics

Symbol Parameter Test Condition Value Unit

tWLWH Write Enable Low to Write Enable High Min 100 ns

tDVWH Data Valid to Write Enable High Min 50 ns

tWHDX Write Enable High to Data Transition Min 5 ns

tAVCL Row Address Valid to RC Low Min 50 ns

tCLAX RC Low to Row Address Transition Min 50 ns

tAVCH Column Address Valid to RC High Min 50 ns

tCHAX RC High to Column Address Transition Min 50 ns

tWHWL Write Enable High to Write Enable Low Min 100 ns

tCHWH RC High to Write Enable High Min 50 ns

tVPHWH(1) VPP High to Write Enable High Min 100 ns

tWHGL Write Enable High to Output Enable Low Min 30 ns

tWHRL Write Enable High to RB Low Min 0 ns

tQVVPL(1)(2) Output Valid, RB High to VPP Low Min 0 ns

1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP < 3.6V).

Package mechanical M50FW040

44/53

10 Package mechanical

Figure 15. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package

outline

1. Drawing is not to scale.

Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.17 3.56 0.125 0.140

A1 1.53 2.41 0.060 0.095

A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495

D1 11.35 11.51 0.447 0.453

D2 4.78 5.66 0.188 0.223

D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595

E1 13.89 14.05 0.547 0.553

E2 6.05 6.93 0.238 0.273

E310.16– –0.400– –

e1.27– –0.050– –

F 0.00 0.13 0.000 0.005

R0.89– –0.035– –

N32 32

PLCC-A

E3 E1 E

1 N

0.51 (.020)

1.14 (.045)

D2 D2

M50FW040 Packa ge mechanical

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Figure 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline

1. Drawing is not to scale.

Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

α0° 5° 0° 5°

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 13.800 14.200 0.5433 0.5591

D1 12.300 12.500 0.4843 0.4921

e 0.500 – – 0.0197 – –

E 7.900 8.100 0.3110 0.3189

L 0.500 0.700 0.0197 0.0276

N32 32

TSOP-a

N/2

DIE

LA1 α

Package mechanical M50FW040

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Figure 17. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, package outline

1. Drawing is not to scale.

Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7283

e 0.500 – – 0.0197 – –

E 9.900 10.100 0.3898 0.3976

L 0.500 0.700 0.0197 0.0276

α0° 5° 0° 5°

N40 40

TSOP-a

N/2

DIE

LA1 α

M50FW040 Part numbering

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11 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’.

F or a list of a vailable options ( Speed, Package, etc.) or for further information on an y aspect

of this device, please contact the ST Sales Office nearest to you.

The category of second-Level Interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box lab el.

Table 27. Or dering information scheme

Example: M50FW040 K 5 T G

Device Type

M50

Architecture

F = Fir m ware Hub Interface

Operating Voltage

W = 3V to 3.6V

Device Function

040 = 4 Mbit (x8), Uniform Block

Package

K = PLCC32

NB = TSOP32 (8 x 14mm)(1)

1. Devices delivered in this package are Not Recommended for New Design.

N = TSOP40: 10 x 20 mm(1)

Device Grade

5 = Temperature range –20 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape & Reel Packing

Plating Technology

P or G = ECOPACK® (RoHs compliant)

Flowcharts and pseudo codes M50FW040

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12 Flowcharts and pseudo codes

Figure 18. Program flowchart and pseudo code

1. A Status check of b1 (Protected Block), b3 (VPP invalid) and b4 (Program Error) can be made after each

Program operation by following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller

operations.

Write 40h or 10h

AI03407

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program command:

– write 40h or 10h

– write Address & Data

(memory enters read status state after

the Program command)

do:

–read Status Register if Program/Erase

Suspend command given execute

suspend program loop

while b7 = 1

If b3 = 1, VPP invalid error:

– error handler

If b4 = 1, Program error:

– error handler

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2) If b1 = 1, Program to protected block error:

– error handler

Suspend

Loop

YES

FWH

Interface

Only

M50FW040 Flowcharts and pseudo codes

49/53

Figure 19. Program Suspend & Resume flowchart and pseudo code

Write 70h

AI03408

Read Status

YES

b7 = 1

YES

b2 = 1

Program Continues

Write a read

Command

Program/Erase Suspend command:

– write B0h

– write 70h

do:

– read Status Register

while b7 = 1

If b2 = 0 Program completed

Write D0h Program/Erase Resume command:

– write D0h to resume the program

– if the Program operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Read data from

another address

Start

Write B0h

Program Complete

Write FFh

Read Data

Flowcharts and pseudo codes M50FW040

50/53

Figure 20. Erase flowchart and pseudo code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller

operations.

Write 20h

AI03409

Start

Write Block Address

& D0h

Read Status

YES

b7 = 1

YES

b3 = 0

b4, b5 = 0

VPP Invalid

Error (1)

Command

Sequence Error (1)

Erase command:

– write 20h

– write Block Address & D0h

(memory enters read Status Register after

the Erase command)

do:

– read Status Register

– if Program/Erase Suspend command

given execute suspend erase loop

while b7 = 1

If b3 = 1, VPP invalid error:

– error handler

If b4, b5 = 1, Command sequence error:

– error handler

YES

b5 = 0 Erase Error (1)

YES

Suspend

Loop

If b5 = 1, Erase error:

– error handler

End

YES

b1 = 0 Erase to Protected

Block Error (1) If b1 = 1, Erase to protected block error:

– error handler

YES

FWH

Interface

Only

M50FW040 Flowcharts and pseudo codes

51/53

Figure 21. Erase Suspend & Resume flowchart and pseudo code

Write 70h

AI03410

Read Status

YES

b7 = 1

YES

b6 = 1

Erase Continues

Program/Erase Suspend command:

– write B0h

– write 70h

do:

– read Status Register

while b7 = 1

If b6 = 0, Erase completed

Write D0h

Read data from

another block

Program

Start

Write B0h

Erase Complete

Write FFh

Read Data

Program/Erase Resume command:

– write D0h to resume erase

– if the Erase operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Revision history M50FW040

52/53

13 Revision history

Table 28. Document revision history

Date Version Changes

September 2000 -01 First Issue

04-Oct-2000 -02 DC Characteristics: ICC4 changed

11-Apr-01 -03

Document type: from Preliminary Data to Data Sheet

Program and Erase functions clarification

Read Electronic Signature table change

FWH Register Configuration Map table change

Input Register Definition table, note clarification

DC Characteristics parameters clarification and new VIH and VIL

parameters added

FWH Interface AC Signal Timing Characteristics change

A/A Mux Interface Read AC Characteristics change

A/A Mux Interface Write AC Characteristics change

A/A Mux Interface Write AC Waveforms change

06-Jul-2001 -04 Note 2 changed (Table 13: Absolute maximum ratings)

12-Mar-2002 -05 RFU pins must be left disconnected

Specification of PLCC32 package mechanical data revised

09-Jul-2004 6.0

Revision numbering modified.

Document imported in new template (and so reformatted).

Temperature Range ordering information replaced by Device Grade,

Standard packing option added and Plating Technology added to

Table 27: Ordering information scheme . TLEAD parameter added to

Table 13: Absolute maximum ratings and TBIAS parameter removed.

12-Jul-2004 7.0 Inches values corrected in Table 27: Ordering information scheme.

10-Nov-2004 8.0 TSOP32 package added. Figure 2: Logic diagram (A/A Mux Interface)

and Table 2: Signal names (A/A Mux interface) added.

24-Oct-2006 9

Document converted to new ST template.

Packages are ECOPACK® compliant. TLEAD removed from Table 13:

Absolute maximum ratings.

Device grade 1 removed. Blank Plating Technology option removed

from Table 27: Ordering information scheme.

M50FW040

53/53

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