14-Bit, 2.5 MSPS, PulSAR,
15.5 mW ADC in LFCSP
Data Sheet AD7944
Rev. C Document Feedback
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Technical Support www.analog.com
FEATURES
14-bit resolution with no missing codes
Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low)
Low power dissipation
15.5 mW at 2.5 MSPS, with external reference
28 mW at 2.5 MSPS, with internal reference
INL: ±0.25 LSB typical, ±1.0 LSB maximum
SNR
84 dB, with on-chip reference
84.5 dB, with external reference
4.096 V internal reference: typical drift of ±10 ppm/°C
Pseudo differential analog input voltage range
0 V to VREF with VREF up to 5.0 V
Allows use of any input range
No pipeline delay
Logic interface: 1.8 V/2.5 V/2.7 V
Proprietary serial interface
SPI/QSPI/MICROWIRE/DSP compatible
Ability to daisy-chain multiple ADCs with busy indicator
20-lead, 4 mm × 4 mm LFCSP (QFN)
APPLICATIONS
Battery-powered equipment
Communications
ATE
Data acquisition systems
Medical instruments
GENERAL DESCRIPTION
The AD79441 is a 14-bit, 2.5 MSPS successive approximation
analog-to-digital converter (SAR ADC). It contains a low power,
high speed, 14-bit sampling ADC, an internal conversion clock,
APPLICATION DIAGRAM
Figure 1.
an internal reference (and buffer), error correction circuits, and
a versatile serial interface port. On the rising edge of CNV, the
AD7944 samples an analog input, IN+, between 0 V and VREF
with respect to a ground sense, IN−. The AD7944 features a
very high sampling rate turbo mode (TURBO high) and a
reduced power normal mode (TURBO low) for low power
applications where the power is scaled with the throughput.
In normal mode (TURBO low), the SPI-compatible serial inter-
face also features the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus and provide an optional busy
indicator. The serial interface is compatible with 1.8 V, 2.5 V,
and 2.7 V supplies using the separate VIO supply.
The AD7944 is available in a 20-lead LFCSP with operation
specified from −40°C to +85°C.
1 Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP, 14-/16-/18-Bit PulSAR® ADCs1
Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver
14-Bit AD7940 AD79422 AD79462 AD79443
16-Bit AD7680 AD76852 AD76862 AD79802 ADA4941-1
AD7683 AD76872 AD76882 AD79832 ADA4841-1
AD7684 AD7694 AD76932 AD79853 AD8021
18-Bit AD76912 AD76902 AD79822 ADA4941-1
AD79842 ADA4841-1
AD79863 AD8021
1 See www.analog.com for the latest selection of PulSAR ADCs and ADC drivers.
2 Pin-for-pin compatible with all other parts marked with this endnote.
3 The AD7944, AD7985, and AD7986 are pin-for-pin compatible.
0V
TO
V
REF
NOTES
1. GND REFERS TO REFGND, AGND, AND DGND.
AD7944
GND REF
AVDD,
DVDD
VIO
BVDD
5V 2.5V
1.8
V
TO
2.7V
VIO
SDI
SCK
SDO
CNV
3- OR 4-WIRE
INTERFACE:
SPI, CS,
DAISY CHAIN
(TURBO = LOW)
TURBO
10µF
IN+
IN–
04658-001
AD7944 Data Sheet
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Application Diagram ........................................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information .................................................................... 13
Converter Operation .................................................................. 13
Conversion Modes of Operation .............................................. 13
Typical Application Diagram .................................................... 14
Analog Inputs ............................................................................. 15
Driver Amplifier Choice ........................................................... 15
Voltage Reference Input ............................................................ 16
Power Supply ............................................................................... 16
Digital Interface .............................................................................. 17
Data Reading Options ............................................................... 18
CS Mode, 3-Wire Without Busy Indicator ............................. 19
CS Mode, 3-Wire with Busy Indicator .................................... 20
CS Mode, 4-Wire Without Busy Indicator ............................. 21
CS Mode, 4-Wire with Busy Indicator .................................... 22
Chain Mode Without Busy Indicator ...................................... 23
Chain Mode with Busy Indicator ............................................. 24
Applications Information .............................................................. 25
Layout .......................................................................................... 25
Evaluating AD7944 Performance ............................................. 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
2/16—Rev. B to Rev. C
Changes to Table 1 ............................................................................ 1
Change to Transition Noise Parameter, Table 2 ........................... 3
Deleted Note 4, Table 2 .................................................................... 3
Changes to Figure 4 .......................................................................... 7
Changed Typical Connection Diagram Section to Typical
Application Diagram Section ........................................................ 14
Change to Typical Application Diagram Section ....................... 14
Changes to Figure 23 ...................................................................... 14
Changes to Driver Amplifier Choice Section ............................. 15
Change to Reference Decoupling Section ................................... 16
Changes to Reading During Conversion, Fast Host (Turbo
or Normal Mode) Section and Split Reading, Any Speed Host
(Turbo or Normal Mode) Section ................................................ 18
Changes to Figure 31 ...................................................................... 21
Changes to Evaluating AD7944 Performance Section .............. 25
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
7/14—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Added Patent Note, Note 1 ............................................................... 1
Changes to Figure 21...................................................................... 13
Changes to Data Reading Options Section ................................. 18
8/10—Rev. 0 to Rev. A
Changes to Table 4, Conversion Time: CNV Rising Edge
to Data Available ................................................................................ 5
10/09—Revision 0: Initial Version
Data Sheet AD7944
Rev. C | Page 3 of 28
SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range (IN+) − (IN−) 0 VREF V
Absolute Input Voltage
IN+
−0.1
V
REF
+ 0.1
V
IN− −0.1 +0.1 V
Leakage Current at 25°C Acquisition phase 250 nA
Input Impedance See the Analog Inputs section
ACCURACY
No Missing Codes 14 Bits
Differential Nonlinearity Error, DNL −0.90 ±0.25 +0.90 LSB1
Integral Nonlinearity Error, INL −1.00 ±0.25 +1.00 LSB1
Transition Noise 0.4 LSB1
Gain Error
2
T
MIN
to T
MAX
−15
±2
+15
LSB
1
Gain Error Temperature Drift ±0.8 ppm/°C
Zero Error2 TMIN to TMAX −0.65 ±0.08 +0.65 mV
Zero Error Temperature Drift 0.55 ppm/°C
Power Supply Sensitivity3 AVDD = 2.5 V ± 5% 84.3 dB
THROUGHPUT
Conversion Rate 0 2.5 MSPS
Transient Response Full-scale step 100 ns
AC ACCURACY3
Dynamic Range VREF = 4.096 V, internal reference 83.5 84.5 dB
VREF = 5.0 V, external reference 84 85 dB
Signal-to-Noise Ratio, SNR
f
IN
= 20 kHz
VREF = 4.096 V, internal reference 83.5 84 dB
VREF = 5.0 V, external reference 84 84.5 dB
Spurious-Free Dynamic Range, SFDR fIN = 20 kHz 103 dB
Total Harmonic Distortion, THD fIN = 20 kHz, VREF = 4.096 V, internal
reference
−102 dB
Signal-to-Noise-and-Distortion Ratio,
SINAD
fIN = 20 kHz, VREF = 4.096 V 84 dB
SAMPLING DYNAMICS
−3 dB Input Bandwidth 19 MHz
Aperture Delay 0.7 ns
1 LSB means least significant bit. With the 4.096 V input range, one LSB is 250 µV.
2 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
3 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
AD7944 Data Sheet
Rev. C | Page 4 of 28
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
INTERNAL REFERENCE PDREF is low
Output Voltage TA = 25°C 4.081 4.096 4.111 V
Temperature Drift −40°C to +85°C ±10 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±50 ppm/V
Turn-On Settling Time CREF = 10 μF, CREFIN = 0.1 μF 40 ms
REFIN Output Voltage REFIN at 25°C 1.2 V
REFIN Output Resistance 6 kΩ
EXTERNAL REFERENCE PDREF is high, REFIN is low
Voltage Range 2.4 5.1 V
Current Drain 500 µA
REFERENCE BUFFER
REFIN Input Voltage 1.2 V
REFIN Input Current 160 µA
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.1 × VIO V
VIH 0.9 × VIO VIO + 0.3 V
IIL −1 +1 µA
I
IH
−1
+1
µA
DIGITAL OUTPUTS
Data Format Serial 14 bits, straight binary
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = +500 µA 0.4 V
VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
AVDD, DVDD 2.375 2.5 2.625 V
BVDD 4.75 5.0 5.25 V
VIO Specified performance 1.8 2.5 2.7 V
Standby Current1, 2 AVDD = DVDD = VIO = 2.5 V 1.0 µA
Power Dissipation
With Internal Reference 2.5 MSPS throughput 28 33 mW
2.0 MSPS throughput 25 30 mW
With External Reference 2.5 MSPS throughput 15.5 17 mW
2.0 MSPS throughput 12 13 mW
TEMPERATURE RANGE3
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Data Sheet AD7944
Rev. C | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Conversion Time: CNV Rising Edge
to Data Available
tCONV Turbo mode 320 ns
tCONV Normal mode 420 ns
Acquisition Time tACQ 80 ns
Time Between Conversions tCYC Turbo mode 400 ns
t
CYC
Normal mode
500
ns
CNV Pulse Width tCNVH CS mode 10 ns
Data Read During Conversion tDATA Turbo mode 190 ns
tDATA Normal mode 290 ns
Quiet Time During Acquisition from Last SCK
Falling Edge to CNV Rising Edge
tQUIET 20 ns
SCK Period
t
SCK
CS mode
9
ns
tSCK Chain mode 11 ns
SCK Low Time tSCKL 3.5 ns
SCK High Time tSCKH 3.5 ns
SCK Falling Edge to Data Remains Valid tHSDO 2 ns
SCK Falling Edge to Data Valid Delay
t
DSDO
4
ns
CNV or SDI Low to SDO D13 MSB Valid tEN 5 ns
CNV or SDI High or Last SCK Falling Edge
to SDO High Impedance
tDIS CS mode 8 ns
SDI Valid Setup Time from CNV Rising Edge tSSDICNV 4 ns
SDI Valid Hold Time from CNV Rising Edge tHSDICNV CS mode 0 ns
t
HSDICNV
Chain mode
0
ns
SCK Valid Setup Time from CNV Rising Edge tSSCKCNV Chain mode 5 ns
SCK Valid Hold Time from CNV Rising Edge tHSCKCNV Chain mode 5 ns
SDI Valid Setup Time from SCK Falling Edge tSSDISCK Chain mode 2 ns
SDI Valid Hold Time from SCK Falling Edge tHSDISCK Chain mode 3 ns
SDI High to SDO High tDSDOSDI Chain mode with busy indicator 15 ns
1 See Figure 2 and Figure 3 for load conditions.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
500µA IOL
500µA IOH
1.4V
TO SDO CL
20pF
04658-002
90% VIO 10% VIO
VIH1
VIL1
VIL1
VIH1
tDELAY tDELAY
1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
04658-003
AD7944 Data Sheet
Rev. C | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+, IN− to GND1 −0.3 V to VREF + 0.3 V
or ±130 mA
Supply Voltage
REF, BVDD to GND, REFGND −0.3 V to +6.0 V
AVDD, DVDD, VIO to GND −0.3 V to +2.7 V
AVDD, DVDD to VIO −6 V to +3 V
Digital Inputs to GND
−0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
20-Lead LFCSP (QFN) 30.4°C/W
Lead Temperatures
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Inputs section for an explanation of IN+ and IN−.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet AD7944
Rev. C | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 2 REF AI Reference Output/Input Voltage.
When PDREF is low, the internal reference and buffer are enabled, producing 4.096 V on this pin.
When PDREF is high, the internal reference and buffer are disabled, allowing an externally supplied
voltage reference up to 5.0 V.
Decoupling is required with or without the internal reference and buffer. This pin is referred to the
REFGND pins and should be decoupled closely to the REFGND pins with a 10 μF capacitor.
3, 4 REFGND AI Reference Input Analog Ground.
5 IN− AI Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote ground sense.
6 IN+ AI
Analog Input. This pin is referred to IN−. The voltage range, that is, the difference between IN+ and IN−,
is 0 V to VREF.
7 PDREF DI
Internal Reference Power-Down Input. When this pin is low, the internal reference is enabled. When
this pin is high, the internal reference is powered down and an external reference must be used.
8 VIO P
Input/Output Interface Digital Power. Nominally at the same supply voltage as the host interface
(1.8 V, 2.5 V, or 2.7 V).
9 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
10 DGND P Digital Power Ground.
11 DVDD P Digital Power. Nominally at 2.5 V.
12 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
13 CNV DI
Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
14 SDI DI
Serial Data Input. This input has multiple functions. It selects the interface mode of the ADC as follows.
Chain mode is selected if SDI is low during the CNV rising edge. In chain mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In CS mode, either SDI or CNV can enable
the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
15 TURBO DI
Conversion Mode Selection. When TURBO is high, the maximum throughput (2.5 MSPS) is achieved,
and the ADC does not power down between conversions. When TURBO is low, the maximum throughput
is lower (2.0 MSPS), and the ADC powers down between conversions.
16 AVDD P Input Analog Power. Nominally at 2.5 V.
17, 18 AGND P Analog Power Ground.
PIN 1
INDICATOR
REF
REF
REFGND
REFGND
IN–
CNV
SDI
TURBO
SCK
DVDD
IN+
PDREF
VIO
DGND
SDO
AGND
BVDD
REFIN
AGND
AVDD
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
04658-004
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
AD7944
TOP VIEW
AD7944 Data Sheet
Rev. C | Page 8 of 28
Pin No. Mnemonic Type 1 Description
19 BVDD P Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum
SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the
REFIN pin to ground. The external reference buffer must be connected to the BVDD pin.
20 REFIN AI/O Internal Reference Output/Reference Buffer Input.
When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin,
which needs external decoupling (0.1 µF typical).
When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin.
When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are
powered down. An external reference must be connected to REF and BVDD.
EPAD EP Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints,
it is recommended that the pad be soldered to the system ground plane.
1 AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power.
Data Sheet AD7944
Rev. C | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF is high, REFIN is low), unless otherwise noted.
Figure 5. Integral Nonlinearity vs. Code
Figure 6. Histogram of DC Input at Code Center (External Reference)
Figure 7. Histogram of DC Input at Code Center (Internal Reference)
Figure 8. Differential Nonlinearity vs. Code
Figure 9. Histogram of DC Input at Code Transition (External Reference)
Figure 10. Histogram of DC Input at Code Transition (Internal Reference)
04096 8192 12,288 16,384
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
CODE
INL (LSB)
04658-105
POSITIVE INL = +0.12 LSB
NEGATI V E INL = –0.20 L S B
04658-106
0 0 24899 149 00 0
0
20,000
40,000
60,000
80,000
100,000
120,000
140,000
8188 8189 8190 8191 8192 8193 8194 8195 8196
COUNT
CODE IN HEX
126,022
04658-110
0025236 1438 000
0
20,000
40,000
60,000
80,000
100,000
120,000
140,000
8188 8189 8190 8191 8192 8193 8194 8195 8196
COUNT
CODE IN HEX
124,396
04096 8192 12,288 16,384
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
CODE
DNL (LSB)
04658-108
POSITIVE DNL = +0.11LSB
NEGATIVE DNL = –0.11LSB
04658-109
0 0 324
62,982
000
0
10,000
20,000
30,000
40,000
50,000
60,000
80,000
70,000
8188 8189 8190 8191 8192 8193 8194 8195
COUNT
CODE IN HEX
67,766
04658-107
0 0 7
63,238
20 0
0
10,000
20,000
30,000
40,000
50,000
60,000
70,000
80,000
8189 8190 8191 8192 8193 8194 8195 8196
COUNT
CODE IN HEX
67,825
AD7944 Data Sheet
Rev. C | Page 10 of 28
Figure 11. FFT Plot (External Reference)
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 13. SINAD vs. Frequency
Figure 14. FFT Plot (Internal Reference)
Figure 15. THD vs. Reference Voltage
Figure 16. THD vs. Frequency
0 250 500 750 1000 1250
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (kHz)
AMPLITUDE (dB)
04658-111
fS
= 2.5MSPS
fIN
= 20kHz
SNR = 84.65dB
THD = –100dB
SINAD = 84.5dB
04658-112
12.0
12.5
13.0
13.5
14.0
14.5
15.0
78
79
80
81
82
83
84
2.5 3.0 3.5 4.0 4.5 5.0
ENOB (Bits)
SNR, SINAD (dB)
REFERENCE VOLTAGE (V)
SINAD
ENOB
SNR
04658-113
80.0
80.5
81.0
81.5
82.0
82.5
83.0
83.5
84.0
84.5
85.0
110 100 1000
SINAD (dB)
FREQUENCY (kHz)
0 250 500 750 1000 1250
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (kHz)
AMPLITUDE (dB)
fS
= 2.5MSPS
fIN
= 20kHz
SNR = 84dB
THD = –102dB
SINAD = 84dB
04658-114
04658-115
–105
–104
–103
–102
–101
–
100
2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00
THD (dB)
REFERENCE VOLTAGE (V)
04658-116
–110
–105
–100
–95
–90
–85
–
80
1 10 100 1000
THD (dB)
FREQUENCY (kHz)
Data Sheet AD7944
Rev. C | Page 11 of 28
Figure 17. SNR vs. Input Level
Figure 18. Operating Current vs. Supply Voltage
Figure 19. Operating Current vs. Temperature
Figure 20. Power-Down Current vs. Temperature
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
SNR (dB)
INPUT LEVEL (dBFS)
04658-117
80
81
82
83
84
85
86
87
88
89
90
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.375 2.625
I
AVDD
I
DVDD
I
VIO
I
BVDD
I
REF
2.5752.5252.4752.425
OPERATING CURRENT (mA)
AVDD AND DVDD VOLTAGE (V)
04658-118
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–55 –35 –15 5 25 45 65 85 105 125
I
AVDD
I
BVDD
I
REF
OPERATING CURRENT (mA)
TEMPERATURE (°C)
04658-119
14
12
10
8
6
4
2
0
–55 –35 –15 5 25 45 65 85 105 125
SUPPLY CURRENT (µA)
TEMPERATURE (°C)
I
AVDD
+ I
DVDD
+ I
VIO
04658-120
AD7944 Data Sheet
Rev. C | Page 12 of 28
TERMINOLOGY
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is mea-
sured with a signal at −60 dBFS so that it includes all noise
sources and DNL artifacts.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is expressed in bits and is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
Effective Resolution
Effective resolution is expressed in bits and is calculated as follows:
Effective Resolution = log2(2N/RMS Input Noise)
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 22).
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to resolve individual codes distinctly. It is expressed in
bits and is calculated as follows:
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Zero Error
Zero error is the difference between the ideal midscale voltage
(0 V) and the actual voltage producing the midscale output code,
that is, 0 LSB.
Data Sheet AD7944
Rev. C | Page 13 of 28
THEORY OF OPERATION
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7944 is a fast, low power, single-supply, precise, 14-bit
ADC using a successive approximation architecture. The AD7944
features different modes to optimize performance according to the
application. In turbo mode, the AD7944 is capable of converting
2,500,000 samples per second (2.5 MSPS).
The AD7944 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7944 can be interfaced to any 1.8 V to 2.7 V digital logic
family. It is available in a space-saving 20-lead LFCSP that allows
flexible configurations. It is pin-for-pin compatible with the
16-bit AD7985 and the 18-bit AD7986.
CONVERTER OPERATION
The AD7944 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary-weighted capacitors that are
connected to the two comparator inputs.
During the acquisition phase, the terminals of the array tied to
the input of the comparator are connected to AGND via SW+
and SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is completed and the CNV
input goes high, a conversion phase is initiated.
When the conversion phase begins, SW+ and SW− are opened
first. The two capacitor arrays are then disconnected from the
analog inputs and connected to the REFGND input. Therefore,
the differential voltage between the IN+ and IN− inputs captured at
the end of the acquisition phase is applied to the comparator
inputs, causing the comparator to become unbalanced. By switch-
ing each element of the capacitor array between REFGND and
REF, the comparator input varies by binary-weighted voltage
steps (VREF/2, VREF/4, … VREF/16,384). The control logic toggles
these switches, starting with the MSB, to bring the comparator
back into a balanced condition. After the completion of this
process, the part returns to the acquisition phase, and the control
logic generates the ADC output code and a busy signal indicator.
Because the AD7944 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
CONVERSION MODES OF OPERATION
The AD7944 features two conversion modes of operation:
turbo and normal. Turbo conversion mode (TURBO high)
allows the fastest conversion rate of up to 2.5 MSPS and does
not power down between conversions. The first conversion in
turbo mode should be ignored because it contains meaningless
data. For applications that require lower power and slightly
slower sampling rates, the normal conversion mode (TURBO
low) allows a maximum conversion rate of 2.0 MSPS and
powers down between conversions. The first conversion in
normal mode contains meaningful data.
04658-005
COMP
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
CONTROL
LOGIC
SW+LSB
SW–LSB
IN+
IN–
MSB
MSB
CC4C 2C
CC4C 2C
REF
REFGND
4096C8192C
4096C8192C
AD7944 Data Sheet
Rev. C | Page 14 of 28
Transfer Functions
The ideal transfer characteristic for the AD7944 is shown in
Figure 22 and Table 7.
Figure 22. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input,
VREF = 4.096 V
Digital Output
Code (Hex)
FSR − 1 LSB 4.09575 V 0x3FFF1
Midscale + 1 LSB 2.04825 V 0x2001
Midscale
2.048 V
0x2000
Midscale − 1 LSB 2.04775 V 0x1FFF
−FSR + 1 LSB 250 µV 0x0001
−FSR 0 V 0x00002
1 This is also the code for an overranged analog input (VIN+ − VIN− above
VREF − REFGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below
REFGND).
TYPICAL APPLICATION DIAGRAM
Figure 23 shows an example of the recommended application
diagram for the AD7944 when multiple supplies are available.
Figure 23. Typical Application Diagram with Multiple Supplies
000 ... 000
000 ... 001
000 ... 010
ADC CODE ( S TRAI GHT BINARY)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
111 ... 101
111 ... 110
111 ... 111
04658-006
NOTES
1. G ND RE FERS TO RE FGND, AG ND, AND DGND.
AD7944
GNDREF
AVDD,
DVDD VIO
BVDD
5V 2.5V
1.8V
TO
2.7V
VIO
SDI
SCK
SDO
CNV
3- O R 4- WIRE
INTERFACE:
SPI, CS,
DAISY CHAIN
(TURBO = LOW)
TURBO
10µF
IN+
IN–
1.5nF
10Ω
V–
0V TO V
REF
V+
04658-007
Data Sheet AD7944
Rev. C | Page 15 of 28
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the analog input
structure of the AD7944.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Take care to ensure that the analog
input signal does not exceed the reference input voltage (VREF)
by more than 0.3 V. If the analog input signal exceeds this level,
the diodes become forward-biased and start conducting
current. These diodes can handle a forward-biased current of
130 mA maximum. However, if the supplies of the input buffer
(for example, the V+ and V− supplies of the buffer amplifier in
Figure 23) are different from those of REF, the analog input
signal may eventually exceed the supply rails by more than
0.3 V. In such a case (for example, an input buffer with a short
circuit), the current limitation can be used to protect the part.
Figure 24. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog inputs
(IN+ and IN−) can be modeled as a parallel combination of
Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase, where the switches are closed, the
input impedance is limited to CPIN. RIN and CIN make a one-pole,
low-pass filter that reduces undesirable aliasing effects and
limits noise.
When the source impedance of the driving circuit is low, the
AD7944 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The
dc performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7944 is easy to drive, the driver amplifier must
meet the following requirements:
• The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7944. The noise from the driver is
filtered by the one-pole, low-pass filter of the AD7944 analog
input circuit, made by RIN and CIN, or by the external filter,
if one is used. Because the typical noise of the AD7944 is
100 µV rms, the SNR degradation due to the amplifier is
+
=
−22
)(
2
π
100
100
20log(dB)
NdB3
LOSS
Nef
SNR
where:
f−3 dB is the input bandwidth, in MHz, of the AD7944
(19 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
• For ac applications, the driver should have a THD perfor-
mance commensurate with that of the AD7944.
• For multichannel multiplexed applications, the driver
amplifier and the AD7944 analog input circuit must settle
for a full-scale step onto the capacitor array at a 14-bit level
(0.0061%, 61 ppm). In the data sheet of the driver amplifier,
settling at 0.1% to 0.01% is more commonly specified. This
value can differ significantly from the settling time at a
14-bit level and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
ADA4899-1 Ultralow noise and high frequency
AD8014
Low power and high frequency
CPIN
REF
RIN CIN
D1
D2
IN+ OR I N–
REFGND
04658-008
AD7944 Data Sheet
Rev. C | Page 16 of 28
VOLTAGE REFERENCE INPUT
The AD7944 allows the choice of a very low temperature drift
internal voltage reference, an external reference, or an external
buffered reference.
The internal reference of the AD7944 provides excellent
performance and can be used in almost all applications.
Internal Reference, REF = 4.096 V (PDREF Low)
To use the internal reference, the PDREF input must be low.
This enables the on-chip band gap reference and buffer, result-
ing in a 4.096 V reference on the REF pin (1.2 V on REFIN).
The internal reference is temperature compensated to 4.096 V ±
15 mV. The reference is trimmed to provide a typical drift of
10 ppm/°C.
The output resistance of REFIN is 6 kΩ when the internal
reference is enabled. It is necessary to decouple this pin with a
ceramic capacitor of at least 100 nF. The output resistance of
REFIN and the decoupling capacitor form an RC filter, which
helps to reduce noise.
Because the output impedance of REFIN is typically 6 kΩ,
relative humidity (among other industrial contaminants) can
directly affect the drift characteristics of the reference. A guard
ring is typically used to reduce the effects of drift under such
circumstances. However, the fine pitch of the AD7944 makes
this difficult to implement. One solution, in these industrial
and other types of applications, is to use a conformal coating,
such as Dow Corning® 1-2577 or HumiSeal® 1B73.
External 1.2 V Reference and Internal Buffer (PDREF High)
To use an external reference along with the internal buffer, PDREF
must be high. This powers down the internal reference and allows
the 1.2 V reference to be applied to REFIN, producing 4.096 V
(typically) on the REF pin.
External Reference (PDREF High, REFIN Low)
To apply an external reference voltage directly to the REF pin, tie
PDREF high and tie REFIN low. BVDD should also be driven to
the same potential as REF. For example, if REF = 2.5 V, BVDD
should be tied to 2.5 V.
The advantages of directly using an external voltage reference
are as follows:
SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a larger reference voltage (5 V)
instead of a typical 4.096 V reference when the internal
reference is used. This is calculated by
0.5
096.4
log20 SNR
Power savings when the internal reference is powered
down (PDREF high).
Reference Decoupling
The AD7944 voltage reference input, REF, has a dynamic input
impedance that requires careful decoupling between the REF
and REFGND pins. The Layout section describes how this can
be done.
When using an external reference, a very low impedance source
(for example, a reference buffer using the AD8031 or the AD8605)
and a 10 μF (X5R, 0805 size) ceramic chip capacitor are appro-
priate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For example, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR435 reference.
If desired, a reference decoupling capacitor with a value as small
as 2.2 μF can be used with minimal impact on performance,
especially DNL.
In any case, there is no need for an additional, lower value
ceramic decoupling capacitor (for example, 100 nF) between
the REF and REFGND pins.
POWER SUPPLY
The AD7944 has four power supply pins: an analog supply
(AVDD), a buffer supply (BVDD), a digital supply (DVDD), and a
digital input/output interface supply (VIO). VIO allows a direct
interface to any logic from 1.8 V to 2.7 V. To reduce the number
of supplies needed, the VIO, DVDD, and AVDD pins can be
tied together. The power supplies do not need to be started in a
particular sequence. In addition, the AD7944 is very insensitive
to power supply variations over a wide frequency range.
In normal mode, the AD7944 powers down automatically at the
end of each conversion phase and, therefore, the power scales
linearly with the sampling rate. This makes the part ideal for
low sampling rates (even of a few SPS) and battery-powered
applications.
Figure 25. Operating Current vs. Sampling Rate in Normal Mode
10
1
0.1
0.01
0.1 1
OPERATING CURRENT (mA)
SAMPLING RATE (MSPS)
I
BVDD
I
AVDD
I
DVDD
I
VIO
I
VREF
04658-121
Data Sheet AD7944
Rev. C | Page 17 of 28
DIGITAL INTERFACE
Although the AD7944 has a reduced number of pins, it offers
flexibility in its serial interface modes.
In CS mode, the AD7944 is compatible with SPI, MICROWIRE,
QSPI™, and digital hosts. In CS mode, the AD7944 can use either a
3-wire or a 4-wire interface. A 3-wire interface that uses the
CNV, SCK, and SDO signals minimizes wiring connections,
which is useful, for example, in isolated applications. A 4-wire
interface that uses the SDI, CNV, SCK, and SDO signals allows
CNV, which initiates conversions, to be independent of the
readback timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
In chain mode, the AD7944 provides a daisy-chain feature that
uses the SDI input for cascading multiple ADCs on a single data
line similar to a shift register. Chain mode is available only in
normal conversion mode (TURBO low).
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. CS mode is selected if SDI is
high, and chain mode is selected if SDI is low. The SDI hold
time is such that when SDI and CNV are connected together,
chain mode is always selected.
In normal mode operation, the AD7944 offers the option of
forcing a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled in CS mode if CNV or SDI is
low when the ADC conversion ends (see Figure 29 and Figure 33).
TURBO must be kept low for both digital interfaces.
Table 9 lists the availability of each serial interface mode, with
and without the busy indicator, for the two conversion modes.
Table 9. Serial Interface Modes (CS and Chain Mode) for
Each Conversion Mode (Turbo and Normal)
Serial Interface Mode
Conversion Mode
Turbo Mode Normal Mode
CS Mode, 3-Wire
Without Busy Indicator Yes Yes
With Busy Indicator
No
Yes
CS Mode, 4-Wire
Without Busy Indicator Yes Yes
With Busy Indicator No Yes
Chain Mode
Without Busy Indicator
No
Yes
With Busy Indicator No Yes
When CNV is low, readback can occur during conversion or
acquisition, or it can be split across acquisition and conversion,
as described in the following sections.
A discontinuous SCK is recommended because the part is selected
with CNV low, and SCK activity begins to clock out data.
Note that in the following sections, the timing diagrams indicate
digital activity (SCK, CNV, SDI, and SDO) during the conversion.
However, due to the possibility of performance degradation,
digital activity should occur only prior to the safe data reading
time, tDATA, because the AD7944 provides error correction
circuitry that can correct for an incorrect bit decision during
this time. From tDATA to tCONV, there is no error correction, and
conversion results may be corrupted.
Similarly, tQUIET, the time from the last falling edge of SCK to the
rising edge of CNV, must remain free of digital activity. The user
should configure the AD7944 and initiate the busy indicator (if
desired in normal mode) prior to tDATA.
It is also possible to corrupt the sample by having SCK near the
sampling instant. Therefore, it is recommended that the digital
pins be kept quiet for approximately 20 ns before and 10 ns after
the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
AD7944 Data Sheet
Rev. C | Page 18 of 28
DATA READING OPTIONS
There are three different data reading options for the AD7944.
There is the option to read during conversion, to split the read
across acquisition and conversion (see Figure 26 and Figure 27),
and, in normal mode, to read during acquisition. The desired
SCK frequency largely determines the reading option to use.
Reading During Conversion, Fast Host (Turbo or
Normal Mode)
When reading during conversion (n), conversion results are for
the previous (n − 1) conversion. Reading should occur only up
to tDATA, and because this time is limited, the host must use a
fast SCK.
The required SCK frequency is calculated by
ENCNVHDATA
SCK t
tt EdgesSCKNumber
f−
−
≥__
To determine the minimum SCK frequency, follow these
examples to read data from conversion (n − 1).
For turbo mode (2.5 MSPS)
Number_SCK_Edges = 14; tDATA = 190 ns; tCNVH = 10 ns;
tEN = 5 ns
fSCK = 14/(190 ns − 10 ns − 5 ns) = 80 MHz
For normal mode (2.0 MSPS)
Number_SCK_Edges = 14; tDATA = 290 ns; tCNVH = 10 ns;
tEN = 5 ns
fSCK = 14/(290 ns − 10 ns − 5 ns) = 50.9 MHz
The time between tDATA and tCONV is an input/output quiet time
during which digital activity should not occur, or sensitive bit
decisions may be corrupted.
Split Reading, Any Speed Host (Turbo or Normal Mode)
To allow for a slower SCK, there is the option of a split read,
where data access starts at the current acquisition (n) and spans
into the conversion (n). Conversion results are for the previous
(n − 1) conversion.
Similar to reading during conversion, split reading should occur
only up to tDATA. For the maximum throughput, the only time
restriction is that split reading take place during the tACQ
(minimum) + (tDATA − tQUIET) time. The time between the falling
edge of SCK and CNV rising is an acquisition quiet time, tQUIET.
To determine how to split the read for a particular SCK frequency,
follow these examples to read data from conversion (n − 1).
For turbo mode (2.5 MSPS)
fSCK = 60 MHz; tDATA = 190 ns; tCNVH = 10 ns; tEN = 5 ns
Number_SCK_Edges = 60 MHz × (190 ns − 10 ns −
5 ns) = 10.5
Ten bits are read during conversion (n), and four bits are read
during acquisition (n).
For normal mode (2.0 MSPS)
fSCK = 40 MHz; tDATA = 290 ns; tCNVH = 10 ns; tEN = 5 ns
Number_SCK_Edges = 40 MHz × (290 ns – 10 ns – 5 ns) = 11
Eleven bits are read during conversion (n), and three bits are
read during acquisition (n).
For slow throughputs, the time restriction is dictated by the
throughput required by the user; the host is free to run at any
speed. Similar to reading during acquisition, data access for
slow hosts must take place during the acquisition phase with
additional time into the conversion.
Note that data access spanning conversion requires the CNV
pin to be driven high to initiate a new conversion, and data
access is not allowed when CNV is high. Thus, the host must
perform two bursts of data access when using this method.
Reading During Acquisition, Any Speed Host (Turbo or
Normal Mode)
When reading during acquisition (n), conversion results are
for the previous (n − 1) conversion. Maximum throughput is
achievable in normal mode (2.0 MSPS); however, in turbo
mode, 2.5 MSPS throughput is not achievable.
For the maximum throughput, the only time restriction is that
reading take place during the tACQ (minimum) time. For slow
throughputs, the time restriction is dictated by the throughput
required by the user; the host is free to run at any speed. Thus,
for slow hosts, data access must take place during the acquisi-
tion phase.
Data Sheet AD7944
Rev. C | Page 19 of 28
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7944 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
Figure 27.
With SDI tied to VIO, a rising edge on CNV initiates a con-
version, selects CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues until completion,
irrespective of the state of CNV. This can be useful, for example,
to bring CNV low to select other SPI devices, such as analog
multiplexers; however, CNV must be returned high before the
minimum conversion time elapses and then held high for the
maximum possible conversion time to avoid the generation of
the busy signal indicator.
When the conversion is complete, the AD7944 enters the
acquisition phase and, if the part is in normal mode (TURBO
low), powers down. When CNV goes low, the MSB is output
onto SDO. The remaining data bits are clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
that it has an acceptable hold time. After the 14th SCK falling
edge or when CNV goes high (whichever occurs first), SDO
returns to high impedance.
Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
AD7944
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
04658-009
ACQUISITION (n)
ACQUISITION
(n + 1)
A
CQUISITION
(n – 1)
12
BEGIN DATA (n – 1)
CONVERSION (n)
END DATA (n – 1)
SCK
CNV
SDO
12 13
CONVERSION (n – 1)
END DATA (n – 2)
t
CONV
t
DATA
0
(I/O QUIET
TIME)
(I/O QUIET
TIME)
14 12 13 14
11312112 012
SDI = 1
>
t
CONV
(I/O QUIET
TIME)
t
CYC
t
ACQ
t
CNVH
t
QUIET
t
SCK
t
DIS
t
DIS
t
DIS
t
DIS
t
EN
t
EN
t
DSDO
t
HSDO
t
DATA
t
CONV
0
4658-010
AD7944 Data Sheet
Rev. C | Page 20 of 28
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7944 is connected
to an SPI-compatible digital host that has an interrupt input. It
is available only in normal conversion mode (TURBO low). The
connection diagram is shown in Figure 28, and the corresponding
timing is given in Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. SDO is
maintained in high impedance until the completion of the
conversion, irrespective of the state of CNV. Prior to the minimum
conversion time, CNV can be used to select other SPI devices,
such as analog multiplexers, but CNV must be returned low
before the minimum conversion time elapses and then held low
for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7944 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the optional 15th SCK falling edge, SDO returns
to high impedance.
If multiple AD7944 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended that this
contention be kept as short as possible to limit extra power
dissipation.
Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
AD7944
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
IRQ
VIO
47kΩ
TURBO
04658-011
SDO D13 D12 D1 D0
t
DIS
SCK 123 131415
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
T
URBO = 0
SDI = 1
t
CNVH
t
ACQ
t
QUIET
(I/O QUIET
TIME)
04658-012
Data Sheet AD7944
Rev. C | Page 21 of 28
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7944 devices are
connected to an SPI-compatible digital host. A connection dia-
gram example using two AD7944 devices is shown in Figure 30,
and the corresponding timing is given in Figure 31.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multi-plexers, but
SDI must be returned high before the minimum
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator.
When the conversion is complete, the AD7944 enters the
acquisition phase and, if the part is in normal mode (TURBO
low), powers down. Each ADC result can be read by bringing its
SDI input low, which consequently outputs the MSB onto SDO.
The remaining data bits are then clocked by subsequent SCK
falling edges. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided that it
has an acceptable hold time. After the 14th SCK falling edge, SDO
returns to high impedance and another AD7944 can be read.
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
AD7944
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
CS1
CS2
AD7944
SDI SDO
CNV
SCK
04658-013
SDO D13 D12 D11 D1 D0
t
DIS
SCK 123 262728
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
S
DI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
12 13
t
SCK
t
SCKL
t
SCKH
D0 D13 D12
15 1614
S
DI(CS2)
04658-014
t
QUIET
AD7944 Data Sheet
Rev. C | Page 22 of 28
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7944 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in applica-
tions where low jitter on CNV is desired. This mode is available
only in normal conversion mode (TURBO low). The connection
diagram is shown in Figure 32, and the corresponding timing is
given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers, but
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7944 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an accept-
able hold time. After the optional 15th SCK falling edge or when
SDI goes high (whichever occurs first), SDO returns to high
impedance.
Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram
Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
AD7944
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
IRQ
VIO
47kΩ
CS1
TURBO
04658-015
(I/O QUIET
TIME)
SDO D13 D12 D1 D0
tDIS
tQUIET
SCK 123 13 14 15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
TURBO = 0
04658-016
Data Sheet AD7944
Rev. C | Page 23 of 28
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7944 devices on
a 3-wire serial interface. It is available only in normal conversion
mode (TURBO is low). This feature is useful for reducing com-
ponent count and wiring connections, for example, in isolated
multiconverter applications or for systems with a limited inter-
facing capacity. Data readback is analogous to clocking a shift
register. A connection diagram example using two AD7944
devices is shown in Figure 34, and the corresponding timing is
given in Figure 35.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects chain mode,
and disables the busy indicator. In this mode, CNV is held high
during the conversion phase and the subsequent data readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD7944 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 14 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate and, consequently, more
AD7944 devices in the chain, provided that the digital host has
an acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time.
Figure 34. Chain Mode Without Busy Indicator Connection Diagram
Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing
CONVERT
DATA I N
CLK
DIGITAL HOST
AD7944
SDI SDO
CNV
B
SCK
AD7944
SDI SDO
CNV
A
SCK TURBO TURBO
04658-017
TURBO = 0
SDOA = SDIBDA13 DA12 DA11
SCK 123 26 27 28
tSSDISCK tHSDISCK
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
12 13
tSCK
tSCKL
tSCKH
DA0
15 1614
SDIA = 0
SDOBDB13 DB12 DB11 DA1DB1 DB0 DA13 DA12
tHSDO
tDSDO
tQUIET
tHSCKCNV
DA0
04658-018
AD7944 Data Sheet
Rev. C | Page 24 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7944 devices
on a 3-wire serial interface while providing a busy indicator. It
is available only in normal conversion mode (TURBO low).
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register. A connection diagram
example using three AD7944 devices is shown in Figure 36, and
the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK high, a
rising edge on CNV initiates a conversion, selects chain mode,
and enables the busy indicator. In this mode, CNV is held high
during the conversion phase and the subsequent data readback.
When all ADCs in the chain have completed their conversions, the
SDO pin of the ADC closest to the digital host (see the AD7944
ADC labeled C in Figure 36) is driven high. This transition on
SDO can be used as a busy indicator to trigger the data read-
back controlled by the digital host. The AD7944 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are clocked out, MSB first, by subsequent SCK
falling edges. For each ADC, SDI feeds the input of the internal
shift register and is clocked by the SCK falling edge. Each ADC
in the chain outputs its data MSB first, and 14 × N + 1 clocks
are required to read back the N ADCs. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate and, consequently, more
AD7944 devices in the chain, provided that the digital host has
an acceptable hold time.
Figure 36. Chain Mode with Busy Indicator Connection Diagram
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
CONVERT
DATA I N
CLK
DIGITAL HOST
AD7944
SDI SDO
CNV
C
SCK
AD7944
SDI SDO
CNV
A
SCK IRQ
AD7944
SDI SDO
CNV
B
SCK TURBOTURBO
TURBO
04658-019
SDO
A
= SDI
B
D
A
13 D
A
12 D
A
11
SCK 1 2 3 31 41 42
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDI
A
D
A
1
413
t
SCK
t
SCKH
t
SCKL
D
A
0
15 3014
SDO
B
= SDI
C
D
B
13 D
B
12 D
B
11 D
A
1D
B
1 D
B
0 D
A
13 D
A
12
43
t
SSDISCK
t
HSDISCK
t
HSDO
t
DSDO
SDO
C
D
C
13 D
C
12 D
C
11 D
A
1 D
A
0D
C
1 D
C
0 D
A
12
17 27 2816 29
D
B
1 D
B
0 D
A
13D
B
13 D
B
12
t
DSDOSDI
t
HSCKCNV
D
A
0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
TURBO = 0
t
SSCKCNV
04658-020
Data Sheet AD7944
Rev. C | Page 25 of 28
APPLICATIONS INFORMATION
LAYOUT
The printed circuit board (PCB) that houses the AD7944 should
be designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7944, with its analog signals on the left side and its digital
signals on the right side, eases this task.
Avoid running digital lines under the device because they couple
noise onto the die, unless a ground plane under the AD7944 is
used as a shield. Fast switching signals, such as CNV or clocks,
should not run near analog signal paths. Avoid crossover of
digital and analog signals.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7944 devices.
The AD7944 voltage reference inputs (REF) have a dynamic
input impedance and should be decoupled with minimal
parasitic inductances. This is done by placing the reference
decoupling ceramic capacitor close to, ideally right up against,
the REF and REFGND pins and connecting them with wide,
low impedance traces.
Finally, the power supplies, VDD and VIO of the AD7944,
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7944 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.
EVALUATING AD7944 PERFORMANCE
Other recommended layouts for the AD7944 are outlined in
the documentation for the AD7944 evaluation board (EVAL-
AD7944FMCZ). The evaluation board package includes a fully
assembled and tested evaluation board, documentation, and
software for controlling the board from a PC via the EVAL-
SDP-CH1Z board.
AD7944 Data Sheet
Rev. C | Page 26 of 28
Figure 38. Example Layout of the AD7944 (Top Layer)
Figure 39. Example Layout of the AD7944 (Bottom Layer)
5
4
PADDLE
3
1
2
6
BVDD AVDD
DVDD
VIO
GND
GND
GND
GND
GND
GNDGND
REF REF REF
04658-030
5V
EXTERNAL
REFERENCE
(ADR435 O R ADR445)
GND
CREF
BVDD AVDD
DVDD
VIO
GND
GND
GND
GND
GND
GNDGND
REF REF REF
CBVDD CAVDD
CVIO
CDVDD
04658-031
Data Sheet AD7944
Rev. C | Page 27 of 28
OUTLINE DIMENSIONS
Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body, and 0.75 mm Package Height
(CP-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description
Package
Option
Ordering
Quantity
AD7944BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP], Tray CP-20-10 490
AD7944BCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel CP-20-10 1,500
EVAL-AD7944FMCZ Evaluation Board
EVAL-SDP-CH1Z ControllerBoard
1 Z = RoHS Compliant Part.
2 The EVAL-AD7944FMCZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CH1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CH1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the FMC designator.
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDSMO-220-WGGD.
061609-B
BOTTOMVIEW
TOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00SQ
3.90
SEATING
PLANE
0.80
0.75
0.700.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
FORPROPER CONNECTION OF
THE EXPOSED PAD,REFERTO
THE PINCONFIGURATIONAND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
