CY7C019V20AXI - CYPRESS SEMICONDUCTOR

3.3V 64K/128K x 8/9

Dual-Port Static RAM

CY7C008V/009V

CY7C018V/019V

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-06044 Rev. *C Revised September 6, 2005

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• 64K x 8 organization (CY7C008)

• 128K x 8 organization (CY7C009)

• 64K x 9 organization (CY7C018)

• 128K x 9 organization (CY7C019)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 15/20/25 ns

• Low operating power

— Active: ICC = 115 mA (typical)

— Standby: ISB3 = 10 µA (typical)

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 16/18 bits or more using

Master/Slave chip select when using more than one

device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

•INT

flag for port-to-port communication

• Dual Chip Enables

• Pin select for Master or Slave

• Commercial and Industrial Temperature Ranges

• Available in 100-pin TQFP

•Pb-Free packages available

Notes:

1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.

2. A0–A15 for 64K devices; A0–A16 for 128K.

3. BUSY is an output in master mode and an input in slave mode.

I/O

Control

Address

Decode

A0L–A15/16L

CEL

OEL

R/WL

BUSYL

I/O

Control

Interrupt

Semaphore

Arbitration

SEML

INTL

M/S

Logic Block Diagram

A0L–A15/16L

True Dual-Ported

RAM Array

A0R–A15/16R

CER

OER

R/WR

BUSYR

SEMR

INTR

Address

Decode A0R–A15/16R

[1] [1]

[2] [2]

[3] [3]

[2] [2]

R/WL

CE0L

CE1L

OEL

I/O0L–I/O7/8L

CEL

R/WR

CE0R

CE1R

OER

I/O0R–I/O7/8R

CER

16/17

8/9

16/17

8/9

16/17 16/17

CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9

Dual-Port Static RAM

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 2 of 18

Functional Description

The CY7C008V/009V and CY7018V/019V are low-power

CMOS 64K, 128K x 8/9 dual-port static RAMs. Various

arbitration schemes are included on the devices to handle

situations when multiple processors access the same piece of

data. Two ports are provided permitting independent,

asynchronous access for reads and writes to any location in

memory. The devices can be utilized as standalone 8/9-bit

dual-port static RAMs or multiple devices can be combined in

order to function as a 16/18-bit or wider master/slave dual-port

static RAM. An M/S pin is provided for implementing 16/18-bit

or wider memory applications without the need for separate

master and slave devices or additional discrete logic. Appli-

cation areas include interprocessor/multiprocessor designs,

communications status buffering, and dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). Two flags

are provided on each port (BUSY and INT). BUSY signals that

the port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from

one port to the other to indicate that a shared resource is in

use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared

resource is in use. An automatic power-down feature is

controlled independently on each port by a chip select (CE)

pin.

The CY7C008V/009V and CY7018V/019V are available in

100-pin Thin Quad Plastic Flatpacks (TQFP).

Pin Configurations

Note:

4. This pin is NC for CY7C008V.

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A7R

A8R

A9R

A10R

A15R

A12R

A14R

GND

CE0R

A13R

A11R

CE1R

SEMR

R/WR

OER

GND

A16R

CY7C008V (64K x 8)

A7L

A8L

A9L

A10L

A15L

A12L

A14L

VCC

CE0L

A13L

A11L

CE1L

SEML

R/WL

OEL

GND

A16L

A6L

A5L

A4L

A3L

INTL

A1L

GND

M/S

A0R

A1R

A0L

A2L

BUSYR

INTR

A2R

A3R

A4R

A5R

A6R

BUSYL

34 35 36 424139 403837 43 44 45 5048 494746

I/O7R

I/O6R

I/O5R

I/01R

I/O3R

I/O2R

GND

VCC

GND

I/O2L

VCC

I/O4R

I/O0L

I/O1L

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

GND

I/O0R

3332313029282726

CY7C009V (128K x 8)

100-Pin TQFP

(Top View)

[4][4]

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 3 of 18

Pin Configurations (continued)

Note:

5. This pin is NC for CY7C018V.

Selection Guide

CY7C008V/009V

CY7C018V/019V

-15

CY7C008V/009V

CY7C018V/019V

-20

CY7C008V/009V

CY7C018V/019V

-25 Unit

Maximum Access Time 15 20 25 ns

Typical Operating Current 125 120 115 mA

Typical Standby Current for ISB1

(Both ports TTL level)

35 35 30 mA

Typical Standby Current for ISB3

(Both ports CMOS level)

10 µA 10 µA10 µAµA

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A7R

A8R

A9R

A10R

A15R

A12R

A14R

GND

CE0R

A13R

A11R

CE1R

SEMR

R/WR

OER

GND

A16R

CY7C018V (64K x 9)

A7L

A8L

A9L

A10L

A15L

A12L

A14L

VCC

CE0L

A13L

A11L

CE1L

SEML

R/WL

OEL

GND

A16L

A6L

A5L

A4L

A3L

BUSYL

A1L

INTL

GND

VCC

INTR

A0R

A0L

A2L

M/S

BUSYR

A1R

A2R

A3R

A4R

A5R

A6R

GND

34 35 36 424139 403837 43 44 45 5048 494746

I/O8R

I/O7R

I/O6R

I/O5R

I/01R

I/O3R

I/O2R

GND

VCC

GND

I/O2L

VCC

I/O4R

I/O0L

I/O1L

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

I/O8L

GND

I/O0R

3332313029282726

CY7C019V (128K x 9)

100-Pin TQFP

(Top View)

[5]

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 4 of 18

Maximum Ratings[6]

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential ............... –0.5V to +4.6V

DC Voltage Applied to

Outputs in High Z State............................–0.5V to VCC+0.5V

DC Input Voltage ..................................... –0.5V to VCC+0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... >1100V

Latch-Up Current.................................................... >200 mA

Notes:

6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

7. Industrial parts are available in CY7C009V and CY7C019V only.

Pin Definitions

Left Port Right Port Description

CE0L, CE1L CER, CE1R Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)

R/WLR/WRRead/Write Enable

OELOEROutput Enable

A0L–A16L A0R–A16R Address (A0–A15 for 64K devices and A0–A16 for 128K devices)

I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)

SEML SEMRSemaphore Enable

INTLINTRInterrupt Flag

BUSYLBUSYRBusy Flag

M/S Master or Slave Select

VCC Power

GND Ground

NC No Connect

Operating Range

Range

Ambient

Temperature VCC

Commercial 0°C to +70°C 3.3V ± 300 mV

Industrial[7] –40°C to +85°C 3.3V ± 300 mV

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 5 of 18

Notes:

8. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f=0 means no address or control lines change. This applies only to inputs at CMOS level

standby ISB3.

9. Tested initially and after any design or process changes that may affect these parameters.

Electrical Characteristics Over the Operating Range

Parameter Description

CY7C008V/009V

CY7C018V/019V

Unit

-15 -20 -25

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

VOH Output HIGH Voltage (VCC = Min., IOH = –4.0 mA) 2.4 2.4 2.4 V

VOL Output LOW Voltage (VCC = Min., IOH = +4.0 mA) 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.2 2.2 2.2 V

VIL Input LOW Voltage 0.8 0.8 0.8 V

IIX Input Leakage Current –5 5 –5 5 –5 5 µA

IOZ Output Leakage Current –10 10 –10 10 –10 10 µA

ICC Operating Current (VCC=Max.

IOUT = 0 mA) Outputs Disabled

Com’l. 125 185 120 175 115 165 mA

Ind.[7] 140 195 mA

ISB1 Standby Current (Both Ports TTL Level)

CEL & CER ≥ VIH, f = fMAX

Com’l. 35 50 35 45 30 40 mA

Ind.[7] 45 55 mA

ISB2 Standby Current (One Port TTL Level)

CEL | CER ≥ VIH, f = fMAX

Com’l. 80 120 75 110 65 95 mA

Ind.[7] 85 120 mA

ISB3 Standby Current (Both Ports CMOS

Level) CEL & CER ≥ VCC − 0.2V, f = 0

Com’l. 10 250 10 250 10 250 µA

Ind.[7] 10 250 µA

ISB4 Standby Current (One Port CMOS Level)

CEL | CER ≥ VIH, f = fMAX[8] Com’l. 75 105 70 95 60 80 mA

Ind.[7] 80 105 mA

Capacitance[9]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 3.3V

10 pF

COUT Output Capacitance 10 pF

AC Test Loads and Waveforms

3.0V

GND 90% 90%

10%

3ns 3ns

10%

ALL INPUT PULSES

(a) Normal Load (Load 1)

R1 = 590Ω

3.3V

OUTPUT

R2 = 435Ω

C = 30 pF

VTH = 1.4V

OUTPUT

(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)

3.3V

OUTPUT

RTH = 250Ω

≤≤

including scope and jig)

(Used for tLZ, tHZ, tHZWE, & tLZWE

C = 30 pF

C = 5 pF

R1 = 590Ω

R2 = 435Ω

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 6 of 18

Switching Characteristics Over the Operating Range[10]

Parameter Description

CY7C008V/009V

CY7C018V/019V

Unit

-15 -20 -25

Min. Max. Min. Max. Min. Max.

READ CYCLE

tRC Read Cycle Time 15 20 25 ns

tAA Address to Data Valid 15 20 25 ns

tOHA Output Hold From Address Change 3 3 3 ns

tACE[11] CE LOW to Data Valid 15 20 25 ns

tDOE OE LOW to Data Valid 10 12 13 ns

tLZOE[12, 13, 14] OE LOW to Low Z 3 3 3 ns

tHZOE[12, 13, 14] OE HIGH to High Z 10 12 15 ns

tLZCE[12, 13, 14] CE LOW to Low Z 3 3 3 ns

tHZCE[12, 13, 14] CE HIGH to High Z 10 12 15 ns

tPU[14] CE LOW to Power-Up 0 0 0 ns

tPD[14] CE HIGH to Power-Down 15 20 25 ns

tABE[11] Byte Enable Access Time 15 20 25 ns

WRITE CYCLE

tWC Write Cycle Time 15 20 25 ns

tSCE[11] CE LOW to Write End 12 16 20 ns

tAW Address Valid to Write End 12 16 20 ns

tHA Address Hold From Write End 0 0 0 ns

tSA[11] Address Set-Up to Write Start 0 0 0 ns

tPWE Write Pulse Width 12 17 22 ns

tSD Data Set-Up to Write End 10 12 15 ns

tHD Data Hold From Write End 0 0 0 ns

tHZWE[13, 14] R/W LOW to High Z 10 12 15 ns

tLZWE[13, 14] R/W HIGH to Low Z 3 3 3 ns

tWDD[15] Write Pulse to Data Delay 30 40 50 ns

tDDD[15] Write Data Valid to Read Data Valid 25 30 35 ns

BUSY TIMING[16]

tBLA BUSY LOW from Address Match 15 20 20 ns

tBHA BUSY HIGH from Address Mismatch 15 20 20 ns

tBLC BUSY LOW from CE LOW 152020ns

tBHC BUSY HIGH from CE HIGH 15 16 17 ns

tPS Port Set-Up for Priority 5 5 5 ns

tWB R/W HIGH after BUSY (Slave)000ns

Notes:

10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOI/IOH and 30-pF load capacitance.

11. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.

12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

13. Test conditions used are Load 2.

14. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port,

refer to Read Timing with Busy waveform.

15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.

16. Test conditions used are Load 1.

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 7 of 18

Data Retention Mode

The CY7C008V/009V and CY7018V/019V are designed with

battery backup in mind. Data retention voltage and supply

current are guaranteed over temperature. The following rules

ensure data retention:

1. Chip enable (CE) must be held HIGH during data retention,

within VCC to VCC – 0.2V.

2. CE must be kept between VCC – 0.2V and 70% of VCC

during the power-up and power-down transitions.

3. The RAM can begin operation >tRC after VCC reaches the

minimum operating voltage (3.0 volts).

Notes:

17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).

18. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.

tWH R/W HIGH after BUSY HIGH (Slave) 13 15 17 ns

tBDD[17] BUSY HIGH to Data Valid 15 20 25 ns

INTERRUPT TIMING[16]

tINS INT Set Time 15 20 20 ns

tINR INT Reset Time 15 20 20 ns

SEMAPHORE TIMING

tSOP SEM Flag Update Pulse (OE or SEM)10 10 12 ns

tSWRD SEM Flag Write to Read Time 5 5 5 ns

tSPS SEM Flag Contention Window 5 5 5 ns

tSAA SEM Address Access Time 15 20 25 ns

Switching Characteristics Over the Operating Range[10] (continued)

Parameter Description

CY7C008V/009V

CY7C018V/019V

Unit

-15 -20 -25

Min. Max. Min. Max. Min. Max.

Timing

Parameter Test Conditions[18] Max. Unit

ICCDR1 @ VCCDR = 2V 50 µA

Data Retention Mode

3.0V 3.0V

VCC > 2.0V

VCC to VCC –0.2V

VCC

tRC

VIH

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 8 of 18

Switching Waveforms

Notes:

19. R/W is HIGH for read cycles.

20. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.

21. OE = VIL.

22. Address valid prior to or coincident with CE transition LOW.

23. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

tRC

tAA

tOHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

tOHA

Read Cycle No.1 (Either Port Address Access)[19, 20, 21]

tACE

tLZOE

tDOE

tHZOE

tHZCE

DATA VALID

tLZCE

tPU tPD

ISB

ICC

DATA OUT

CURRENT

Read Cycle No.2 (Either Port CE/OE Access)[19, 22, 23]

DATA OUT

tRC

ADDRESS

tAA tOHA

tLZCE

tABE

tHZCE

tACE

tLZCE

Read Cycle No. 3 (Either Port)[19, 21, 22, 23]

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 9 of 18

Notes:

24. R/W must be HIGH during all address transitions.

25. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.

26. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified tPWE.

28. To access RAM, CE = VIL, SEM = VIH.

29. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

30. During this period, the I/O pins are in the output state, and input signals must not be applied.

31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

Switching Waveforms (continued)

tAW

tWC

tPWE

tHD

tSD

tHA

R/W

DATA OUT

DATA IN

ADDRESS

tHZOE

tSA

tHZWE tLZWE

Write Cycle No. 1: R/W Controlled Timing[24, 25, 26, 27]

[29]

[27]

[28]

NOTE 30 NOTE 30

tAW

tWC

tSCE

tHD

tSD

tHA

R/W

DATA IN

ADDRESS

tSA

Write Cycle No. 2: CE Controlled Timing[24, 25, 26, 31]

[28]

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 10 of 18

Notes:

32. CE = HIGH for the duration of the above timing (both write and read cycle).

33. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

34. Semaphores are reset (available to both ports) at cycle start.

35. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.

Switching Waveforms (continued)

tSOP

tSAA

VALID ADRESS VALID ADRESS

tHD

DATAIN VALID DATAOUT VALID

tOHA

tAW

tHA

tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

R/W

I/O 0

SEM

A0–A2

Semaphore Read After Write Timing, Either Side[32]

MATCH

tSPS

A0L–A2L

MATCH

R/WL

SEML

R/WR

SEMR

Timing Diagram of Semaphore Contention[33, 34, 35]

A0R–A2R

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 11 of 18

Note:

36. CEL = CER = LOW.

Switching Waveforms (continued)

VALID

tDDD

tWDD

MATCH

R/WR

DATA INR

DATAOUTL

tWC

ADDRESSR

tPWE

VALID

tSD tHD

ADDRESSL

tPS

tBLA tBHA

tBDD

BUSYL

Timing Diagram of Read with BUSY (M/S=HIGH)[36]

tPWE

R/W

BUSY

tWB tWH

Write Timing with Busy Input (M/S=LOW)

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 12 of 18

Note:

37. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Switching Waveforms (continued)

ADDRESS MATCH

tPS

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

CER Valid First:

ADDRESSL,R

BUSYR

CEL

CER

BUSYL

CER

CEL

ADDRESSL,R

Busy Timing Diagram No. 1 (CE Arbitration)[37]

CEL Valid First:

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MISMATCH

tRC or tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH ADDRESS MISMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA tBHA

ADDRESSR

Right Address Valid First:

Busy Timing Diagram No. 2 (Address Arbitration)

[37]

Left Address Valid First:

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 13 of 18

Notes:

38. tHA depends on which enable pin (CEL or R/WL) is deasserted first.

39. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

Switching Waveforms (continued)

Interrupt Timing Diagrams

WRITE FFFF (1FFFF for CY7C009V/19V)

tWC

Right Side Clears INTR:

tHA

READ FFFF

tRC

tINR

WRITE FFFE (1FFFF for CY7C009V/19V)

tWC

Left Side Sets INTR:

READ 1FFE

tINR

tRC

ADDRESSR

CEL

R/WL

INTL

OEL

ADDRESSR

R/WR

CER

INTL

ADDRESSR

CER

R/WR

INTR

OER

ADDRESSL

R/WL

CEL

INTR

tINS

tHA

tINS

(1FFFF for CY7C009V/19V)

[38]

[39]

[38]

[39]

Right Side Sets INTL:

Right Side Clears INTL:

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 14 of 18

Architecture

The CY7C008V/009V and CY7018V/019V consist of an array

of 64K and 128K words of 8 and 9 bits each of dual-port RAM

cells, I/O and address lines, and control signals (CE, OE,

R/W). These control pins permit independent access for reads

or writes to any location in memory. To handle simultaneous

writes/reads to the same location, a BUSY pin is provided on

each port. Two interrupt (INT) pins can be utilized for

port-to-port communication. Two semaphore (SEM) control

pins are used for allocating shared resources. With the M/S

pin, the devices can function as a master (BUSY pins are

outputs) or as a slave (BUSY pins are inputs). The devices

also have an automatic power-down feature controlled by CE.

Each port is provided with its own output enable control (OE),

which allows data to be read from the device.

Functional Description

Write Operation

Data must be set up for a duration of tSD before the rising edge

of R/W in order to guarantee a valid write. A write operation is

controlled by either the R/W pin (see Write Cycle No. 1

waveform) or the CE pin (see Write Cycle No. 2 waveform).

Required inputs for non-contention operations are summa-

rized in Ta b l e 1 .

If a location is being written to by one port and the opposite

port attempts to read that location, a port-to-port flowthrough

delay must occur before the data is read on the output;

otherwise the data read is not deterministic. Data will be valid

on the port tDDD after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE

and CE pins. Data will be available tACE after CE or tDOE after

OE is asserted. If the user wishes to access a semaphore flag,

then the SEM pin must be asserted instead of the CE pin, and

OE must also be asserted.

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (FFFF for the

CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for

the right port and the second-highest memory location (FFFE

for the CY7C008/18, 1FFFE for the CY7C009/19) is the

mailbox for the left port. When one port writes to the other

port’s mailbox, an interrupt is generated to the owner. The

interrupt is reset when the owner reads the contents of the

mailbox. The message is user defined.

Each port can read the other port’s mailbox without resetting

the interrupt. The active state of the busy signal (to a port)

prevents the port from setting the interrupt to the winning port.

Also, an active busy to a port prevents that port from reading

its own mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not

connect the interrupt pin to the processor’s interrupt request

input pin.

The operation of the interrupts and their interaction with Busy

are summarized in Table 2.

Busy

The CY7C008V/009V and CY7018V/019V provide on-chip

arbitration to resolve simultaneous memory location access

(contention). If both ports’ CEs are asserted and an address

match occurs within tPS of each other, the busy logic will

determine which port has access. If tPS is violated, one port

will definitely gain permission to the location, but it is not

predictable which port will get that permission. BUSY will be

asserted tBLA after an address match or tBLC after CE is taken

LOW.

Master/Slave

A M/S pin is provided in order to expand the word width by

configuring the device as either a master or a slave. The BUSY

output of the master is connected to the BUSY input of the

slave. This will allow the device to interface to a master device

with no external components. Writing to slave devices must be

delayed until after the BUSY input has settled (tBLC or tBLA),

otherwise, the slave chip may begin a write cycle during a

contention situation. When tied HIGH, the M/S pin allows the

device to be used as a master and, therefore, the BUSY line

is an output. BUSY can then be used to send the arbitration

outcome to a slave.

Semaphore Operation

The CY7C008V/009V and CY7018V/019V provide eight

semaphore latches, which are separate from the dual-port

memory locations. Semaphores are used to reserve resources

that are shared between the two ports.The state of the

semaphore indicates that a resource is in use. For example, if

the left port wants to request a given resource, it sets a latch

by writing a zero to a semaphore location. The left port then

verifies its success in setting the latch by reading it. After

writing to the semaphore, SEM or OE must be deasserted for

tSOP before attempting to read the semaphore. The

semaphore value will be available tSWRD + tDOE after the rising

edge of the semaphore write. If the left port was successful

(reads a zero), it assumes control of the shared resource,

otherwise (reads a one) it assumes the right port has control

and continues to poll the semaphore. When the right side has

relinquished control of the semaphore (by writing a one), the

left side will succeed in gaining control of the semaphore. If the

left side no longer requires the semaphore, a one is written to

cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM

pin functions as a chip select for the semaphore latches (CE

must remain HIGH during SEM LOW). A0–2 represents the

semaphore address. OE and R/W are used in the same

manner as a normal memory access. When writing or reading

a semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O0 is used. If a zero is

written to the left port of an available semaphore, a one will

appear at the same semaphore address on the right port. That

semaphore can now only be modified by the side showing zero

(the left port in this case). If the left port now relinquishes

control by writing a one to the semaphore, the semaphore will

be set to one for both sides. However, if the right port had

requested the semaphore (written a zero) while the left port

had control, the right port would immediately own the

semaphore as soon as the left port released it. Table 3 shows

sample semaphore operations.

When reading a semaphore, all data lines output the

semaphore value. The read value is latched in an output

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 15 of 18

a write from the other port. If both ports attempt to access the

semaphore within tSPS of each other, the semaphore will

definitely be obtained by one side or the other, but there is no

guarantee which side will control the semaphore.

Notes:

40. A0L–16L and A0R–16R, 1FFFF/1FFFE for the CY7C009V/19V.

41. If BUSYR = L, then no change.

42. If BUSYL = L, then no change.

Table 1. Non-Contending Read/Write

Inputs Outputs

CE R/W OE SEM I/O0–I/O8Operation

H X X H High Z Deselected: Power-Down

H H L L Data Out Read Data in Semaphore Flag

X X H X High Z I/O Lines Disabled

H X L Data In Write into Semaphore Flag

L H L H Data Out Read

L L X H Data In Write

L X X L Not Allowed

Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[40]

Left Port Right Port

Function R/WLCELOELA0L–16L INTLR/WRCEROERA0R–16R INTR

Set Right INTR Flag L L X FFFF (or 1FFFF) X X X X X L[42]

Reset Right INTR Flag X X X X X X L L FFFF (or 1FFFF) H[41]

Set Left INTL Flag X X X X L[41] L L X FFFE (or 1FFFE) X

Reset Left INTL Flag X L L FFFE (or 1FFFE) H[42] X X X X X

Table 3. Semaphore Operation Example

Function I/O0–I/O8 Left I/O0–I/O8Right Status

No action 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left Port has semaphore token

Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore

Left port writes 1 to semaphore 1 0 Right port obtains semaphore token

Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obtains semaphore token

Left port writes 1 to semaphore 1 1 Semaphore free

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Left port writes 1 to semaphore 1 1 Semaphore free

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 16 of 18

Ordering Information

64K x8 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

15 CY7C008V-15AC A100 100-Pin Thin Quad Flat Pack Commercial

20 CY7C008V-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C008V-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C008V-25AXC A100 100-Pin Pb-Free Thin Quad Flat Pack

64K x9 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

15 CY7C018V-15AC A100 100-Pin Thin Quad Flat Pack Commercial

20 CY7C018V-20AC A100 100-Pin Thin Quad Flat Pack Commercial

25 CY7C018V-25AC A100 100-Pin Thin Quad Flat Pack Commercial

128K x8 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

15 CY7C009V-15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C009V-15AXC A100 100-Pin Pb-Free Thin Quad Flat Pack

20 CY7C009V-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C009V-20AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C009V-20AXI A100 100-Pin Pb-Free Thin Quad Flat Pack

25 CY7C009V-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C009V-25AXC A100 100-Pin Pb-Free Thin Quad Flat Pack

128K x9 3.3V Asynchronous Dual-Port SRAM

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

15 CY7C019V-15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C019V-15AXC A100 100-Pin Pb-Free Thin Quad Flat Pack

20 CY7C019V-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C019V-20AXC A100 100-Pin Pb-Free Thin Quad Flat Pack

CY7C019V-20AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C019V-20AXI A100 100-Pin Pb-Free Thin Quad Flat Pack

25 CY7C019V-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C019V-25AXC A100 100-Pin Pb-Free Thin Quad Flat Pack

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 17 of 18

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagram

100-Pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-*B

100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100

[+] Feedback

CY7C008V/009V

CY7C018V/019V

Document #: 38-06044 Rev. *C Page 18 of 18

Document History Page

Document Title: CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM

Document Number: 38-06044

REV. ECN NO.

Issue

Date

Orig. of

Change Description of Change

** 110192 09/29/01 SZV Change from Spec number: 38-00669 to 38-06044

*A 113541 04/15/02 OOR Change pin 85 from BUSYL to BUSYR (pg. 3)

*B 122294 12/27/02 RBI Power up requirements added to Maximum Ratings Information

*C 393440 See ECN YIM Added Pb-Free Logo

Added Pb-Free parts to ordering information:

CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI,

CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC,

CY7C019V-20AXI, CY7C019V-25AXC

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