LM49370RL/NOPB - NATIONAL SEMICONDUCTOR

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

LM49370 Boomer® Audio Power Amplifier Series Audio Sub-System with an Ultra Low

EMI, Spread Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode Stereo Headphone

Amplifier, and a Dedicated PCM Interface for Bluetooth Transceivers

Check for Samples: LM49370

1FEATURES • 16 Step Volume Control for Microphone in 2

dB Steps

2• Spread Spectrum Class D Architecture • Programmable Sidetone Attenuation in 3 dB

Reduces EMI Steps

• Mono Class D 8ΩAmplifier, 490 mW at 3.3V • Two Configurable GPIO Ports

• OCL or AC-Coupled Headphone Operation • Multi-Function IRQ Output

• 33mW Stereo Headphone Amplifier at 3.3V • Micro-Power Shutdown Mode

• 115 mW Earpiece Amplifier at 3.3V • Available in the 4 x 4 mm 49 Bump DSBGA

• 18-bit Stereo DAC Package

• 16-bit Mono ADC • Key Specifications

• 8 kHz to 192 kHz Stereo Audio Playback – PHP (AC-COUP) (A_VDD = 3.3V, 32Ω, 1% THD) 33

• 8 kHz to 48 kHz Mono Recording mW

• Bidirectional I2S Compatible Audio Interface – PHP (OCL) (A_VDD = 3.3V, 32Ω, 1% THD) 31

• Bidirectional PCM Compatible Audio Interface mW

for Bluetooth Transceivers – PLS ( LS_VDD = 5V, 8Ω, 1% THD) 1.2 W

• I2S-PCM Bridge with Sample Rate Conversion – PLS (LS_VDD = 4.2V, 8Ω, 1% THD) 900 mW

• Sigma-Delta PLL for Operation from Any Clock – PLS (LS_VDD = 3.3V, 8Ω, 1% THD) 490 mW

at Any Sample Rate – Shutdown Current 0.8 µA

• Digital 3D Stereo Enhancement – PSRRLS (217 Hz, LS_VDD = 3.3V) 70 dB

• FIR Filter Programmability for Simple Tone – SNRLS (AUX IN to Loudspeaker) 90 dB (typ)

Control – SNRDAC (Stereo DAC to AUXOUT) 85 dB

• Low Power Clock Network Operation if a 12 (typ)

MHz or 13 MHz System Clock is Available – SNRADC (Mono ADC from Cell Phone In) 90

• Read/Write I2C or SPI Compatible Control dB (typ)

Interface – SNRHP (Aux In to Headphones) 98 dB (typ)

• Automatic Headphone & Microphone Detection

• Support for Internal and External Microphones APPLICATIONS

• Automatic Gain Control for Microphone Input • Smart Phones

• Differential Audio I/O for External Cellphone • Mobile Phones and Multimedia Terminals

Module • PDAs, Internet Appliances and Portable

• Mono Differential Auxiliary Output Gaming

• Stereo Auxiliary Inputs • Portable DVD/CD/AAC/MP3 Players

• Differential Microphone Input for Internal • Digital Cameras/Camcorders

Microphone

• Flexible Audio Routing from Input to Output

• 32 Step Volume Control for Mixers in 1.5 dB

Steps

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

AUX_OUT

EP_OUT

LS_OUT

BYPASS

HP_VMIDFB

HP_VMID

HPL_OUT

HPR_OUT

VREF_FLT

INT_BIAS

EXT_BIAS

MIC_DET

EXT_MIC

INT_MIC

CP_OUT

CP_IN

PLL_FLT

MCLK

SCL/SCK

SDA/SDI

TEST_MODE/CS

SPI_MODE

I2S_CLK

I2S_WS

I2S_SDI

I2S_SDO

PCM_CLK

PCM_SYNC

PCM_SDI

IRQ

AUX_R

AUX_L

POWER

MANAGEMENT

and CONTROL

CLOCKS and

6'_PLL

REGISTERS

I2C/SPI

SLAVE

AMP

BIAS

and DET

MIC

BIAS

and DET

AUTOMATIC GAIN

CONTROL

MONO

ADC

STEREO

DAC

DIGITAL AUDIO INTERFACE with PCM - I2S BRIDGE

LEVEL SHIFTERS

G7.11

RIGHT

LEFT

CPI

-34.5 dB to 12 dB

MIC

SIDETONE

-46.5 dB to

12 dB 0 dB to

-30 dB

6 dB to

36 dB

PCM_SDO

GPIO2

GPIO1

FIR FILTER

and

DIGITAL 3D

ALGORITHM

A_VDD

D_VDD LS_VDD LS_VSS

A_VSS

D_VSS

BB_VDD

PLL_VDD

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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DESCRIPTION

The LM49370 is an integrated audio subsystem that supports both analog and digital audio functions. The

LM49370 includes a high quality stereo DAC, a mono ADC, a stereo headphone amplifier, which supports output

cap-less (OCL) or AC-coupled (SE) modes of operation, a mono earpiece amplifier, and an ultra-low EMI spread

spectrum Class D loudspeaker amplifier. It is designed for demanding applications in mobile phones and other

portable devices.

The LM49370 features a bi-directional I2S interface and a bi-directional PCM interface for full range audio on

either interface. The LM49370 utilizes an I2C or SPI compatible interface for control. The stereo DAC path

features an SNR of 85 dB with an 18-bit 48 kHz input. In SE mode the headphone amplifier delivers at least 33

mWRMS to a 32Ωsingle-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V. The mono

earpiece amplifier delivers at least 115mWRMS to a 32Ωbridged-tied load with less than 1% distortion (THD+N)

when A_VDD = 3.3V. The mono speaker amplifier delivers up to 490mW into an 8Ωload with less than 1%

distortion when LS_VDD = 3.3V and up to 1.2W when LS_VDD = 5.0V.

The LM49370 employs advanced techniques to reduce power consumption, to reduce controller overhead, to

speed development time, and to eliminate click and pop. Boomer audio power amplifiers were designed

specifically to provide high quality output power with a minimal amount of external components. It is therefore

ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area

and cost are primary requirements.

LM49370 Overview

Figure 1. Conceptual Schematic

Product Folder Links: LM49370

AB C D E FG

Radio Module

LM49370

CP_INCP_OUT

I2C

IRQ

HP_VMIDFB

MIC_DET

EXT_BIAS

EXT_MIC

HP_VMID

HP_R

HP_L

Baseband

Controller

BB_VDD

BYPASS

VREF_FLT

PLL_FILT

MCLK

AUX_OUT

GPIO1

INT_BIAS

INT_MIC

LM4675

LM4675 Can Be Used

for Stereo Loudspeakers

AUX_RAUX_L

Synthesized

FM Radio/

Analog Inputs

0.5-30 MHz

I2S (Stereo)

Bluetooth

Transceiver PCM (Mono)

GPIO2

A2DP

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Application

Figure 2. Example Application in Multimedia Mobile Phone

Connection Diagrams

Figure 3. 49 Bump DSBGA

Top View (Bump Side Down)

See Package Number YPG0049UUA

Product Folder Links: LM49370

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Pin Descriptions

Pin Pin Name Type Direction Description

A1 EP_NEG Analog Output Earpiece negative output

A2 A_VDD Supply Input Headphone and mixer

VDD

A3 INT_MIC_POS Analog Input Internal microphone

positive input

A4 PCM_SDO Digital Output PCM Serial Data Output

A5 PCM_CLK Digital Inout PCM clock signal

A6 PCM_SYNC Digital Inout PCM sync signal

A7 PCM_SDI Digital Input PCM Serial Data Input

B1 A_VSS Supply Input Headphone and mixer

ground

B2 EP_POS Analog Output Earpiece positive output

B3 INT_MIC_NEG Analog Input Internal microphone

negative input

B4 BYPASS Analog Input A_VDD/2 filter point

If SPI_MODE = 1, then

B5 TEST_MODE/CS Digital Input this pin becomes CS.

B6 PLL_FILT Analog Input Filter point for PLL VCO

input

B7 PLL_VDD Supply Input PLL VDD

C1 HP_R Analog Output Headphone Right Output

C2 EXT_BIAS Analog Output External microphone

supply (2.0/2.5/2.8/3.3V)

C3 INT_BIAS Analog Output Internal microphone

supply (2.0/2.5/2.8/3.3V)

C4 AUX_R Analog Input Right Analog Input

C5 GPIO_2 Digital Inout General Purpose I/O 2

C6 SDA Digital Inout Control Data, I2C_SDA or

SPI_SDA

C7 SCL Digital Input Control Clock, I2C_SCL or

SPI_SCL

D1 HP_L Analog Output Headphone Left Output

D2 VREF_FLT Analog Inout Filter point for the

microphone power supply

D3 EXT_MIC Analog Input External microphone input

D4 SPI_MODE Digital Input Control mode select 1 =

SPI, 0 = I2C

D5 GPIO_1 Digital Inout General Purpose I/O 1

D6 BB_VDD Supply Input Baseband VDD for the

digital I/Os

D7 D_VDD Supply Input Digital VDD

E1 HP_VMID Analog Inout Virtual Ground for

Headphones in OCL

mode, otherwise 1st

headset detection input

E2 MIC_DET Analog Input Headset insertion/removal

and microphone presence

detection input.

E3 AUX_L Analog Input Left Analog Input

E4 CPI_NEG Analog Input Cell Phone analog input

negative

E5 IRQ Digital Output Interrupt request signal

(NOT open drain)

E6 I2S_SDO Digital Output I2S Serial Data Out

Product Folder Links: LM49370

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Pin Descriptions (continued)

Pin Pin Name Type Direction Description

E7 I2S_SDI Digital Input I2S Serial Data Input

F1 HP_VMID_FB Analog Input VMID Feedback in OCL

mode, otherwise a 2nd

headset detection input

F2 LS_VDD Supply Input Loudspeaker VDD

F3 CPI_POS Analog Input Cell Phone analog input

positive

F4 CPO_NEG Analog Output Cell Phone analog output

negative

F5 AUX_OUT_NEG Analog Output Auxiliary analog output

negative

F6 I2S_WS Digital Inout I2S Word Select Signal

(can be master or slave)

F7 I2S_CLK Digital Inout I2S Clock Signal (can be

master or slave)

G1 LS_NEG Analog Output Loudspeaker negative

output

G2 LS_VSS Supply Input Loudspeaker ground

G3 LS_POS Analog Output Loudspeaker positive

output

G4 CPO_POS Analog Output Cell Phone analog output

positive

G5 AUX_OUT_POS Analog Output Auxiliary analog output

positive

G6 D_VSS Supply Input Digital ground

G7 MCLK Digital Input Input clock from 0.5 MHz

to 30 MHz

PIN TYPE DEFINITIONS

Analog Input—A pin that is used by the analog and is never driven by the device. Supplies are part of this

classification.

Analog Output—A pin that is driven by the device and should not be driven by external sources.

Analog Inout—A pin that is typically used for filtering a DC signal within the device, Passive components can be

connected to these pins.

Digital Input—A pin that is used by the digital but is never driven.

Digital Output—A pin that is driven by the device and should not be driven by another device to avoid

contention.

Digital Inout—A pin that is either open drain (I2C_SDA) or a bidirectional CMOS in/out. In the later case the

direction is selected by a control register within the LM49370.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM49370

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Absolute Maximum Ratings (1)(2)

Analog Supply Voltage

(A_VDD & LS_VDD) 6.0V

Digital Supply Voltage

(BB_VDD & D_VDD & PLL_VDD) 6.0V

Storage Temperature −65°C to +150°C

Power Dissipation (3) Internally Limited

ESD Susceptibility Human Body Model (4) 2500V

Machine Model (5) 200V

Junction Temperature 150°C

Thermal Resistance

θJA – YPG49 (soldered down to PCB with 2in21oz. copper plane) 60°C/W

Soldering Information

(1) All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as

possible to the device.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional but do not ensure specific performance limits. Characteristics state DC and AC electrical specifications

under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings.

Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device

performance.

(3) The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,

TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings,

whichever is lower.

(4) Human body model: 100pF discharged through a 1.5kΩresistor.

(5) Machine model: 220pF – 240pF discharged through all pins.

Operating Ratings

Temperature Range −40°C to +85°C

Supply Voltage D_VDD/PLL_VDD 2.5V to 4.5V

BB_VDD 1.8V to 4.5V

LS_VDD = A_VDD(1) 2.5V to 5.5V

(1) LS_VDD must be equal to A_VDD due to intend ESD diode structure. For proper operation, LS_VDD and A_VDD need to be the highest

voltage than BB_VDD, D_VDD, and PLL_VDD and must be applied first.

Electrical Characteristics (1)(2)

Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following

specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370

Symbol Parameter Conditions Units

Limit(4)

Typical(3) (5)

POWER

DISD Digital Shutdown Current(6) Chip Mode '00', fMCLK = 13MHz 0.7 2.2 µA (max)

DIST Digital Standby Current Chip Mode '01', fMCLK = 13MHz 0.9 1.8 mA(max)

AISD Analog Shutdown Current Chip Mode '00' 0.1 1.2 µA(max)

AIST Analog Standby Current Chip Mode '01' 0.1 1.2 µA (max)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional but do not ensure specific performance limits. Characteristics state DC and AC electrical specifications

under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings.

Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device

performance.

(2) All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as

possible to the device.

(3) Typical values are measured at 25°C and represent the parametric norm.

(4) Limits are specified to TI's AOQL (Average Outgoing Quality Level).

(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.

(6) Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled.

Product Folder Links: LM49370

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Electrical Characteristics (1)(2) (continued)

Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following

specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370

Symbol Parameter Conditions Units

Limit(4)

Typical(3) (5)

Chip Mode '10', fMCLK = 12MHz,

fS= 48kHz, 7.9 mA

DAC on; PLL off

Digital Playback Mode Digital

Active Current Chip Mode '10', fMCLK = 13MHz,

fPLLOUT = 12MHz, fS= 48kHz; 12.5 14.5 mA(max)

DAC + PLL on

Chip Mode '10', HP On, SE mode, 9.0 13.5 mA(max)

DAC inputs selected

Digital Playback Mode Analog Chip Mode '10', HP On, OCL mode, 9.4 13.5 mA(max)

Active Current DAC inputs selected

Chip Mode '10', LS On, 11.5 15.5 mA(max)

DAC inputs selected

Analog Playback Mode Digital Active Chip Mode '10', fMCLK = 13MHz, 0.9 1.8 mA(max)

Current DAC +ADC + PLL off

Chip Mode '10', HP On, SE mode, 5.9 9.5 mA(max)

AUX inputs selected

Analog Playback Mode Analog Active Chip Mode '10', HP On, OCL mode, 6.3 9.7 mA(max)

Current AUX inputs selected

Chip Mode '10', LS On, 8.4 12 mA(max)

AUX inputs selected

Chip Mode '10', fMCLK = 13MHz, fS=

CODEC Mode Digital Active Current 2.7 3.5 mA(max)

8kHz, DAC +ADC on; PLL Off

CODEC Mode Analog Active Current Chip Mode '10', EP On, 11.2 15.5 mA(max)

DAC inputs selected

Voice Module Mode Digital Active Chip Mode '10', fMCLK = 13MHz, 0.9 1.8 mA(max)

Current DAC +ADC + PLL off

Voice Module Mode Analog Active Chip Mode '10', EP + CPOUT on, 7.4 11 mA(max)

Current CPIN input selected

LOUDSPEAKER AMPLIFIER

8Ωload, LS_VDD = 5V 1.2 W

PLS Max Loudspeaker Power 8Ωload, LS_VDD = 4.2V 0.9 W

8Ωload, LS_VDD = 3.3V 0.5 0.43 W (min)

8Ωload, LS_VDD = 3.3V,

LSTHD+N Loudspeaker Harmonic Distortion 0.04 %

PO= 400mW

0 dB Input

LSEFF Efficiency 84 %

MCLK = 12.000 MHz

AUX inputs terminated

Power Supply Rejection Ration CBYPASS = 1.0 µF

PSRRLS 70 dB

(Loudspeaker) VRIPPLE = 200 mVP-P

fRIPPLE = 217 Hz

SNRLS Signal to Noise Ratio From 0 dB Analog AUX input, A-weighted 90 80 dB(min)

eNOutput Noise(7) A-weighted 62 µV

VOS Loudspeaker Offset Voltage 12 mV

(7) Disabling or bypassing the PLL will usually result in an improvement in noise measurements.

Product Folder Links: LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Electrical Characteristics (1)(2) (continued)

Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following

specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370

Symbol Parameter Conditions Units

Limit(4)

Typical(3) (5)

HEADPHONE AMPLIFIER

32Ωload, 3.3V, SE 33 25 (min)

16Ωload, 3.3V, SE 52 mW

32Ωload, 3.3V, OCL, VCM = 1.5V 31 mW

PHP Headphone Power 32Ωload, 3.3V, OCL, VCM = 1.2V 20 mW

16Ωload, 3.3V, OCL, VCM = 1.5V 50 mW

16Ωload, 3.3V, OCL, VCM = 1.2V 32 mW

AUX inputs terminated

CBYPASS = 1.0 µF

VRIPPLE = 200 mVP-P

fRIPPLE = 217 Hz

Power Supply Rejection Ratio SE Mode 60 dB

PSRRHP (Headphones) OCL Mode 68 55 dB(min)

VCM = 1.2V

OCL Mode 65 dB

VCM = 1.5V

From 0dB Analog AUX input

A-weighted

SE Mode 98 dB

SNRHP Signal to Noise Ratio OCL Mode 97 dB

VCM = 1.2V

OCL Mode 96 dB

VCM = 1.5V

HPTHD+N Headphone Harmonic Distortion 32Ωload, 3.3V, PO= 7.5mW 0.05 %

eNOutput Noise A-weighted 12 µV

Stereo Channel-to-Channel Gain

ΔACH-CH 0.3 dB

Mismatch SE Mode 61 dB

XTALK Stereo Crosstalk OCL Mode 71 dB

VOS Offset Voltage 8 mV

EARPIECE AMPLIFIER

32Ωload, 3.3V 115 100 (min)

PEP Earpiece Power 16Ωload, 3.3V 150 mW

CP_IN terminated

CBYPASS = 1.0 µF

PSRREP Power Supply Rejection Ratio (Earpiece) 76 dB

VRIPPLE = 200 mVP-P

FRIPPLE = 217 Hz

SNREP Signal to Noise Ratio From 0dB Analog AUX input, A-weighted 93 dB

EPTHD+N Earpiece Harmonic Distortion 32Ωload, 3.3V, PO= 50mW 0.04 %

eNOutput Noise A-weighted 41 µV

VOS Offset Voltage 8 mV

AUXOUT AMPLIFIER

THD+N Total Harmonic Distortion + Noise VO= 1VRMS, 5kΩload 0.02 %

CP_IN terminated

CBYPASS = 1.0μF

PSRR Power Supply Rejection Ratio 86 dB

VRIPPLE = 200mVPP

fRIPPLE = 217Hz

Product Folder Links: LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Electrical Characteristics (1)(2) (continued)

Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following

specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370

Symbol Parameter Conditions Units

Limit(4)

Typical(3) (5)

CP_OUT AMPLIFIER

THD+N Total Harmonic Distortion + Noise VO= 1VRMS, 5kΩload 0.02 %

CBYPASS = 1.0μF

PSRR Power Supply Rejection Ratio VRIPPLE = 200mVPP 86 dB

fRIPPLE = 217Hz

MONO ADC

RADC ADC Ripple ±0.25 dB

ADC Passband Lower (HPF Mode 1), fS= 8 kHz 300 Hz

PBADC Upper 3470 Hz

Above Passband 60 dB

SBAADC ADC Stopband Attenuation HPF Notch, 50 Hz/60 Hz (worst case) 58 dB

SNRADC ADC Signal to Noise Ratio From CPI, A-weighted 90 dB

ADCLEVEL ADC Full Scale Input Level 1 VRMS

STEREO DAC

RDAC DAC Ripple 0.1 dB

PBDAC DAC Passband 20 kHz

SBADAC DAC Stopband Attenuation 70 dB

SNRDAC DAC Signal to Noise Ratio A-weighted, AUXOUT 85 dB

DRDAC DAC Dynamic Range 96 dB

DACLEVEL DAC Full Scale Output Level 1 VRMS

PLL(8)

Min 0.5 MHz

FIN Input Frequency Range Max 30 MHz

I2S/PCM

fS= 48kHz; 16 bit mode 1.536 MHz

fS= 48kHz; 25 bit mode 2.4 MHz

fI2SCLK I2S CLK Frequency fS= 8kHz; 16 bit mode 0.256 MHz

fS= 8kHz; 25 bit mode 0.4 MHz

fS= 48kHz; 16 bit mode 0.768 MHz

fS= 48kHz; 25 bit mode 1.2 MHz

fPCMCLK PCM CLK Frequency fS= 8kHz; 16 bit mode 0.128 MHz

fS= 8kHz; 25 bit mode 0.2 MHz

Min 40 % (min)

DCI2S_CLK I2S_CLK Duty Cycle Max 60 % (max)

DCI2S_WS I2S_WS Duty Cycle 50 %

I2C

TI2CSET I2C Data Setup Time Refer to TRANSFERRING DATA for more 100 ns (min)

details

TI2CHOLD I2C Data Hold Time Refer to TRANSFERRING DATA for more 300 ns (min)

details

SPI

TSPISETENB Enable Setup Time 100 ns (min)

TSPIHOLD-ENB Enable Hold Time 100 ns (min)

TSPISETD Data Setup Time 100 ns (min)

(8) Disabling or bypassing the PLL will usually result in an improvement in noise measurements.

Product Folder Links: LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Electrical Characteristics (1)(2) (continued)

Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following

specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370

Symbol Parameter Conditions Units

Limit(4)

Typical(3) (5)

TSPIHOLDD Data Hold Time 100 ns (min)

TSPICL Clock Low Time 500 ns (min)

TSPICH Clock High Time 500 ns (min)

VOLUME CONTROL

Minimum Gain w/ AUX_BOOST OFF –46.5 dB

Maximum Gain w/ AUX_BOOST OFF 0 dB

VCRAUX AUX Volume Control Range Minimum Gain w/ AUX_BOOST ON –34.5 dB

Maximum Gain w/ AUX_BOOST ON 12 dB

Minimum Gain w/ DAC_BOOST OFF –46.5 dB

Maximum Gain w/ DAC_BOOST OFF 0 dB

VCRDAC DAC Volume Control Range Minimum Gain w/ DAC_BOOST ON –34.5 dB

Maximum Gain w/ DAC_BOOST ON 12 dB

Minimum Gain –34.5 dB

VCRCPIN CPIN Volume Control Range Maximum Gain 12 dB

Minimum Gain 6 dB

VCRMIC MIC Volume Control Range Maximum Gain 36 dB

Minimum Gain –30 dB

VCRSIDE SIDETONE Volume Control Range Maximum Gain 0 dB

SSAUX AUX VCR Stepsize 1.5 dB

SSDAC DAC VCR Stepsize 1.5 dB

SSCPIN CPIN VCR Stepsize 1.5 dB

SSMIC MIC VCR Stepsize 2 dB

SSSIDE SIDETONE VCR Stepsize 3 dB

AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer)

Minimum Gain from AUX input, –34.5 dB

BOOST OFF

Maximum Gain from AUX input, 12 dB

Loudspeaker Audio Path Gain BOOST OFF

Minimum Gain from CPI input –22.5 dB

Maximum Gain from CPI input 24 dB

Minimum Gain from AUX input, –52.5 dB

BOOST OFF

Maximum Gain from AUX input, –6 dB

BOOST OFF

Minimum Gain from CPI input –40.5 dB

Headphone Audio Path Gain Maximum Gain from CPI input 6 dB

Minimum Gain from MIC input using –30 dB

SIDETONE path w/ VCRMIC gain = 6dB

Maximum Gain from MIC input using 0 dB

SIDETONE path w/ VCRMIC gain = 6dB

Product Folder Links: LM49370

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Electrical Characteristics (1)(2) (continued)

Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following

specifications apply for the circuit shown in Figure 2 unless otherwise stated. Limits apply for 25°C. LM49370

Symbol Parameter Conditions Units

Limit(4)

Typical(3) (5)

Minimum Gain from AUX input, –40.5 dB

BOOST OFF

Maximum Gain from AUX input, 6 dB

BOOST OFF

Minimum Gain from CPI input –28.5 dB

Earpiece Audio Path Gain Maximum Gain from CPI input 18 dB

Minimum Gain from MIC input using –18 dB

SIDETONE path w/ VCRMIC gain = 6dB

Maximum Gain from MIC input using 12 dB

SIDETONE path w/ VCRMIC gain = 6dB

Minimum Gain from AUX input, –46.5 dB

BOOST OFF

Maximum Gain from AUX input, 0 dB

AUXOUT Audio Path Gain BOOST OFF

Minimum Gain from CPI input –34.5 dB

Maximum Gain from CPI input 12 dB

Minimum Gain from AUX input, –46.5 dB

BOOST OFF

Maximum Gain from AUX input, 0 dB

CPOUT Audio Path Gain BOOST OFF

Minimum Gain from MIC input 6 dB

Maximum Gain from MIC input 36 dB

Total DC Power Dissipation

DAC (fS= 48kHz) and HP ON

fMCLK = 12MHz, PLL OFF 56 mW

Digital Playback Mode Power Dissipation fMCLK = 13MHz, PLL ON 71 mW

fPLLOUT = 12MHz

AUX Inputs selected and HP ON

Analog Playback Mode Power

Dissipation fMCLK = 13MHz, PLL OFF 22 mW

PCM DAC (fS= 8kHz) + ADC (fS= 8kHz)

and EP ON

VOICE CODEC Mode Power Dissipation fMCLK = 13MHz, PLL OFF 46 mW

CP IN selected. EP and CPOUT ON

VOICE Module Mode Power Dissipation fMCLK = 13MHz, PLL OFF 27 mW

Product Folder Links: LM49370

ADR6

Bit7 ADR5

bit6 ADR4

bit5 ADR3

bit4 ADR2

bit3 ADR1

bit2 ADR0

bit1 R/W

bit0

MSB LSB

I2C SLAVE address (chip address)

SDA

SCL SP

START condition STOP condition

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LM49370

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System Control

Method 1. I2C Compatible Interface

I2C SIGNALS

In I2C mode the LM49370 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal

SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for

LM49370 is 00110102.

I2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when SCL is LOW.

Figure 4. I2C Signals: Data Validity

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits.

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eight bit which is a data direction bit (R/W). The LM49370 address is 00110102. For the eighth bit, a “0” indicates

a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

Figure 5. I2C Chip Address

Product Folder Links: LM49370

SDA

SCL

4 9

1 7

ack from slave

w rs r stop

ack from slave ack from masterrepeated start data from slave

start w ack ack rs r ack ack stop

start

SCL

SDA

MSB Chip Address LSB

slave address =

00110102register address = 0x00h

MSB Register 0x00h LSB MSB Data LSB

MSB Chip Address LSB

slave address =

00110102register 0x00h data

ack ack ack ack

start MSB Chip Address LSB w ack MSB Register 0x02h LSB ack MSB Data LSB ack stop

ack from slave ack from slave ack from slave

SCL

SDA

start slave address =

00110102w ack register address = 0x02h ack ack

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w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by slave)

rs = repeated start

Figure 6. Example I2C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Figure 7. Example I2C Read Cycle

Figure 8. I2C Timing Diagram

I2C TIMING PARAMETERS

Symbol Parameter(1) Limit Units

Min Max

1 Hold Time (repeated) 0.6 µs

START Condition

2 Clock Low Time 1.3 µs

3 Clock High Time 600 ns

4 Setup Time for a 600 ns

Repeated START

Condition

(1) Data specified by design

Product Folder Links: LM49370

CLK

SDI

TSPISETENB

TSPIHOLDD

TSPISETD

TSPICH

TSPIT

TSPICL

TSPIHOLDENB

TEST_MODE/CS

SDI 15 14

CLK

Ignored8

GPIO2 4111

TEST_MODE/CS

SDI 15 14 01

CLK

TEST_MODE/CS

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5 Data Hold Time (Output 300 900 ns

direction, delay generated

by LM49370)

5 Data Hold Time (Input 0 900 ns

direction, delay generated

by the Master)

6 Data Setup Time 100 ns

7 Rise Time of SDA and 20+0.1Cb300 ns

SCL

8 Fall Time of SDA and SCL 15+0.1Cb300 ns

9 Set-up Time for STOP 600 ns

condition

10 Bus Free Time between a 1.3 µs

STOP and a START

Condition

CbCapacitive Load for Each 10 200 pF

Bus Line

Method 2. SPI/Microwire Control/3–wire Control

The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low

chip_select. To use this control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the

chip_select as follows:

Figure 9. SPI Write Transaction

If the application requires read access to the register set; for example to determine the cause of an interrupt

request, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the

GPIO configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address

the MSB of the register address field is set to a 1, this effectively mirrors the contents of the register field to read-

only locations above 0x80h:

Figure 10. SPI Read Transaction

Figure 11. Three Wire Mode Write Bus Timing

Figure 12. SPI Timing

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Status & Control Registers

Table 1. Register Map(1)

Address Register 7 6 5 4 3 2 1 0

0x00h Table 2 BASIC DAC_ MODE CAP_SIZE OSC_ENB PLL_ENB CHP_MODE

Table 3

0x01h R_DIV DAC_CLK_SEL

CLOCKS

0x02h FORCERQ PLL_M

0x03h PLL_N PLL_N

0x04h PLL_P VCOFATS Q_DIV PLL_P

0x05h PLL_MOD PLLTEST PLL_CLK_SEL PLL_N_MOD

0x06h ADC_1 HPF_MODE SAMPLE_RATE RIGHT LEFT CPI MIC

ADC ADC

0x07h ADC_2 NGZXDD ADC_CLK_SEL PEAKTIME MUTE _MODE

0x08h AGC_1 NOISE_GATE_THRESHOLD NG_ENB AGC_TARGET AGC_ENB

AGC

0x09h AGC_2 AGC_DECAY AGC_MAX_GAIN

_TIGHT

0x0Ah AGC_3 AGC_ATTACK AGC_HOLD_TIME

0x0Bh MIC_1 INT_EXT SE_DIFF MUTE PREAMP_GAIN

BTN_DEBOUNCE_TIM

0x0Ch MIC_2 BTNTYPE MIC_BIAS_VOLTAGE VCMVOLT

0x0Dh SIDETONE SIDETONE_ATTEN

0x0Eh CP_INPUT MUTE CPI_LEVEL

0x0Fh AUX_LEFT AUX_DAC MUTE BOOST AUX_LEFT_LEVEL

0x10h AUX_RIGHT AUX_DAC MUTE BOOST AUX_RIGHT_LEVEL

0x11h DAC USAXLVL DACMUTE BOOST DAC_LEVEL

0x12h CP_OUTPUT MICGATE MUTE LEFT RIGHT MIC

0x13h AUX OUTPUT MUTE LEFT RIGHT CPI

0x14h LS_OUTPUT MUTE LEFT RIGHT CPI

0x15h HP_OUTPUT OCL STEREO MUTE LEFT RIGHT CPI SIDE

0x16h EP_OUTPUT MUTE LEFT RIGHT CPI SIDE

0x17h DETECT HS_DBNC_TIME TEMP_INT BTN_INT DET_INT

0x18h STATUS GPIN1 GPIN2 TEMP BTN MIC STEREO HEADSET

CUST

0x19h 3D ATTENUATE FREQ LEVEL MODE 3DENB

_COMP

WORD_ STEREO I2S_MOD

0x1Ah I2SMODE I2S_WS_GEN_MODE WS_MS INENB OUTENB

ORDER REVERSE E

0x1Bh I2SCLOCK PCM_SYNC__WIDTH I2S_CLOCK_GEN_MODE CLKSCE CLK_MS

ALAW/μLA SDO_

0x1Ch PCMMODE COMPAND SYNC_MS CLKSRCE CLK_MS INENB OUTENB

W LSB_HZ

0x1Dh PCMCLOCK PCM_SYNC_GEN_MODE PCM_CLOCKGEN MODE

MONO_ PCM_

0x1Eh BRIDGE MONO_SUM_MODE DAC_TX_SEL I2S_TX_SEL

SUM_SEL TX_SEL

DAC_SRC_ ADC_SRC_

0x1Fh GPIO GPIO_2_SEL GPIO_1_SEL

MODE MODE

0x20h CMP_0_LSB CMP_0_LSB

0x21h CMP_0_0SB CMP_0_MSB

0x22h CMP_1_LSB CMP_1_LSB

0x23h CMP_1_MSB CMP_1_MSB

0x24h CMP_2_LSB CMP_2_LSB

0x25h CMP_2_MSB CMP_2_MSB

(1) The default value of all I2C registers is 0x00h.

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BASIC CONFIGURATION REGISTER

This register is used to control the basic function of the chip.

Table 2. BASIC (0x00h)

Bits Field Description

1:0 CHIP_MODE The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode is

selected the LM49370 will change operation silently and will re-configure the power management profile

automatically. The modes are described as follows:

CHIP MODE Audio System Typical Application

002Off Power-down Mode

012Off Stand-by mode with headset event detection

102On Active without headset event detection

112On Active with headset event detection

2 PLL_ENABLE This enables the PLL.

3 USE_OSC If set the power management and control circuits will assume that no external clock is available and will

resort to using an on-chip oscillator for headset detection and analog power management functions such

as click and pop. The PLL, ADC, and DAC are not wired to use this low quality clock. This bit must be

cleared for the part to be fully turned off power-down mode.

5:4 CAP_SIZE This programs the extra delays required to stabilize once charge/discharge is complete, based on the size

of the bypass capacitor. Bypass Capacitor

CAP_SIZE Turn-off/on time

Size

0020.1 µF 45 ms/75 ms

0121 µF 45 ms/140 ms

1022.2 µF 45 ms/260 ms

1124.7 µF 45 ms/500 ms

7:6 DAC_MODE The DAC can operate in one of four modes. If an “fs*2∧N” audio clock is available, then the DAC can be

run in a slightly lower power mode. If such a clock is not available, the PLL can be used to generate a

suitable clock.

DAC MODE DAC OSR Typical Application

48kHz Playback from

002125 12.000MHz

48kHz Playback from

012128 12.288MHz

10264 96kHz Playback from 12.288MHz

11232 192kHz Playback from 24.576MHz

For reliable headset / push button detection the following bits should be defined before enabling the headset

detection system by setting bit 0 of CHIP_MODE:

The OCL-bit (Cap / Capless headphone interface; bit 6 of HP_OUTPUT (0x15h))

The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))

The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))

The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))

All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should

not be altered while the audio sub-system is active.

If the analog or digital levels are below −12dB then it is not necessary to set the stereo bit allowing greater output

levels to be obtained for such signals.

CLOCKS CONFIGURATION REGISTER

This register is used to control the clocks throughout the chip.

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Table 3. CLOCKS (0x01h)

Bits Field Description

1:0 DAC_CLK This selects the clock to be used by the audio DAC system.

DAC_CLK DAC Input Source

002MCLK

012PLL_OUTPUT

102I2S_CLK_IN

112PCM_CLK_IN

7:2 R_DIV This programs the R divider.

R_DIV Divide Value

0 Bypass

1 Bypass

2 1.5

3 2

4 2.5

5 3

6 3.5

7 4

8 4.5

9 5

10 5.5

11 6

12 6.5

13 to 61 7 to 31

62 31.5

63 32

LM49370 CLOCK NETWORK

The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8

kHz (at point Cas marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires

a 12.000MHz (or 12.288MHz) clock (at point B) for 48 kHz data. It is expected that the PLL is used to drive the

audio system operating at 125*fs unless a 12.000 MHz master clock is supplied or the sample rate is always a

multiple of 8 kHz. In this case the PLL can be bypassed to reduce power, with clock division being performed by

the Q and R dividers instead. The PLL can also be bypassed if the system is running at 128*fs and a 12.288MHz

master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I2S clock input as a

source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the

PLL output divided by 2*FS(DAC)/FS(ADC) or a system clock divided by Q, this allows n*8 kHz recording and 44.1

kHz playback.

MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz.

When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A.

When operating at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A.

This is used to drive the power management and control logic. Performance may not meet the electrical

specifications if the frequency at this point deviates significantly beyond this range.

Product Folder Links: LM49370

MCLK

I2S_CLK

PCM_CLK

PCM Interface

I2S Interface Stereo DAC

Mono ADC

PLL % Q

% R

From on chip 12 MHz oscillator

USE_ONCHIP_OSC

(to DET, PMC)

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Figure 13. LM49370 Clock Network

COMMON CLOCK SETTINGS FOR THE DAC & ADC

When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs

clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems

with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point Bfor various

clock sample rates in the different DAC modes:

Table 4. Common DAC Clock Frequencies

DAC Sample Rate (kHz) Clock Required at B (OSR = 125) Clock Required at B (OSR = 128)

8 2 MHz 2.048 MHz

11.025 2.75625 MHz 2.8224 MHz

12 3 MHz 3.072 MHz

16 4 MHz 4.096 MHz

22.05 5.5125 MHz 5.6448 MHz

24 6 MHz 6.144 MHz

32 8 MHz 8.192 MHz

44.1 11.025 MHz 11.2896 MHz

48 12 MHz 12.288 MHz

NOTE

When DAC_MODE = '01' with the I2S or PCM interface operating as master, the stereo

DAC operates at half the frequency of the clock at point B. This divided by two DAC clock

is used as the source clock for the audio port.

The over sampling ratio of the ADC is set by ADC MODE (bit 0 of 0x07h)). The table below shows the required

clock frequency at point Cfor the different ADC modes.

Table 5. Common ADC Clock Frequencies

ADC Sample Rate (kHz) Clock Required at C (OSR = 125) Clock Required at C (OSR = 128)

8 1 MHz 1.024 MHz

11.025 1.378125 MHz 1.4112 MHz

12 1.5 MHz 1.536 MHz

16 2 MHz 2.048 MHz

22.05 2.75625 MHz 2.8224 MHz

24 3 MHz 3.072 MHz

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Methods for producing these clock frequencies are described in the PLL Section.

PLL M DIVIDER CONFIGURATION REGISTER

This register is used to control the input section of the PLL.

Table 6. PLL_M (0x02h)(1)

Bits Field Description

0 RSVD RESERVED

6:0 PLL_M PLL_M Input Divider Value

0 No Divided Clock

1 1

2 1.5

3 2

4 2.5

... 3 to 63

126 63.5

127 64

7 FORCERQ If set, the R and Q divider are enabled and the DAC and ADC clocks are propagated. This allows operation of

the I2S and PCM interfaces without the ADC or DAC being enabled, for example to act as a bridge or a clock

master.

(1) See Further Notes on PLL Programming for more detail.

The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz.

The division of the M divider is derived from PLL_M such that:

M = (PLL_M + 1) / 2

PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control the feedback divider of the PLL.

Table 7. PLL_N (0x03h)(1)

Bits Field Description

7:0 PLL_N This programs the PLL feedback divider as follows:

PLL_N Feedback Divider Value

0 to 10 10

11 11

12 12

13 13

14 14

… …

249 249

250 to 255 250

(1) See Further Notes on PLL Programming for further details.

The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be

the target resting VCO frequency, FVCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz.

Fin/M is often referred to as Fcomp (comparison frequency) or Fref (reference frequency), in this document Fcomp is

used.

The integer division of the N divider is derived from PLL_N such that:

For 9 < PLL_N < 251: N = PLL_N

PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the output divider of the PLL.

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Table 8. PLL_P (0x04h)(1)

Bits Field Description

3:0 PLL_P This programs the PLL output divider as follows:

PLL_P Output Divider Value

0 No Divided Clock

1 1

2 1.5

3 2

4 2.5

... 3 to 7

14 7.5

15 8

6:4 Q_DIV This programs the Q Divider

Q_DIV Divide Value

00022

00123

01024

01126

10028

101210

110212

111213

7 FAST_VCO This programs the PLL VCO range:

FAST_VCO PLL VCO Range

0 40 to 60MHz

1 60 to 80MHz

(1) See Further Notes on PLL Programming for more details.

The division of the P divider is derived from PLL_P such that:

P = (PLL_P + 1) / 2

PLL N MODULUS CONFIGURATION REGISTER

This register is used to control the modulation applied to the feedback divider of the PLL.

Table 9. PLL_N_MOD (0x05h)(1)

Bits Field Description

4:0 PLL_N_MOD This programs the PLL N divider's fractional component:

PLL_N_MOD Fractional Addition

0 0/32

1 1/32

2 to 30 2/32 to 30/32

31 31/32

6:5 PLL_CLK_SEL This selects the clock to be used as input for the audio PLL.

PLL_INPUT_CLK

002MCLK

012I2S_CLK_IN

102PCM_CLK_IN

112—

7 RSVD Reserved.

(1) See Further Notes on PLL Programming for more details.

Product Folder Links: LM49370

PLL_N_MODPLL_N

8 5

6'M

% N

% PVCO

% M

PLL_M

0.5-30 MHz

PLL_P

External Loop

Filter

40 to 60 MHz 250 x FS

0.5 < 5 MHz

Phase Comparator

and Charge Pump

N = 10..250 31/32

P = 1..8

P = 0,1 + 0/2 - >64

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

The complete N divider is a fractional divider as such:

N = PLL_N + PLL_N_MOD/32

If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is

determined by the following formula:

Fout = (Fin*N)/(M*P)

FURTHER NOTES ON PLL PROGRAMMING

The sigma-delta PLL Is designed to drive audio circuits requiring accurate clock frequencies of up to 30MHz with

frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact

synchronization of 48kHz and 44.1kHz sample rates from any common system clock. In systems where an

isochronous I2S data stream is the source of data to the DAC a clock synchronous to the sample rate should be

used as input to the PLL (typically the I2S clock). If no isochronous source is available, then the PLL can be used

to obtain a clock that is accurate to within 1Hz of the correct sample rate although this is highly unlikely to be a

problem.

Figure 14. PLL Overview

Table 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 00

Fin (MHz) Fs(kHz) M N P PLL_M PLL_N PLL_N_MO PLL_P Fout (MHz)

11 48 11 60 5 21 60 0 9 12

12.288 48 4 19.53125 5 7 19 17 9 12

13 48 13 60 5 25 60 0 9 12

14.4 48 9 37.5 5 17 37 16 9 12

16.2 48 27 100 5 53 100 0 9 12

16.8 48 14 50 5 27 50 0 9 12

19.2 48 13 40.625 5 25 40 20 9 12

19.44 48 27 100 6 53 100 0 11 12

19.68 48 20.5 62.5 5 40 62 16 9 12

19.8 48 16.5 50 5 32 50 0 9 12

11 44.1 11 55.125 5 21 55 4 9 11.025

11.2896 44.1 8 39.0625 5 15 39 2 9 11.025

12 44.1 5 22.96875 5 9 22 31 9 11.025

13 44.1 13 55.125 5 25 55 4 9 11.025

14.4 44.1 12 45.9375 5 23 45 30 9 11.025

16.2 44.1 9 30.625 5 17 9 20 9 11.025

16.8 44.1 17 55.78125 5 33 30 25 9 11.025

19.2 44.1 16 45.9375 5 31 45 30 9 11.025

19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025

19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025

19.8 44.1 11 30.625 5 21 30 20 9 11.025

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Table 11. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 01

Fin (MHz) Fs(kHz) M N P PLL_M PLL_N PLL_N_MO PLL_P Fout (MHz)

12 48 12.5 64 5 24 64 0 9 12.288

13 48 26.5 112.71875 4.5 52 112 23 8 12.288

14.4 48 37.5 128 4 74 128 0 7 12.288

16.2 48 37.5 128 4.5 74 128 0 8 12.288

16.8 48 12.53 32 3.5 24 32 0 6 12.288

19.2 48 12.5 32 4 24 32 0 7 12.288

19.44 48 40.5 128 58 80 128 0 9 12.288

19.68 48 20.5 64 5 40 64 0 9 12.288

19.8 48 37.5 128 5.5 74 128 0 10 12.288

12 44.1 35.5 133.59375 4 70 133 19 7 11.2896

13 44.1 37 144.59375 4.5 73 144 19 8 11.2896

14.4 44.1 37.5 147 5 74 147 0 9 11.2896

16.2 44.1 47.5 182.0625 5.5 94 182 2 10 11.2896

16.8 44.1 12.5 42 5 24 42 0 9 11.2896

19.2 44.1 12.5 36.75 5 24 36 24 9 11.2896

19.44 44.1 37.5 98 4.5 74 98 0 9 11.2896

19.68 44.1 44.5 114.875 4.5 88 114 28 8 11.2896

19.8 44.1 48 136.84375 5 95 136 27 9 11.2896

These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05

kHz should be done by increasing the P divider value or using the R/Q dividers.

An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks

from I2S datastreams).

Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz (or 60–80 MHz if

VCOFAST is used). Remembering that the P divider can divide by half integers, for a 12 MHz output, this gives

possible P values of 3, 3.5, 4, 4.5, or 5. The M divider should be set such that the comparison frequency

(Fcomp) is between 0.5 and 5 MHz. This gives possible M values of 1, 1.5, 2, 2.5, or 3. The most accurate N and

N_MOD can be calculated by sweeping the P and M inputs of the following formulas:

N = FLOOR{[(Fout/Fin)*(P*M)],1}

N_MOD = ROUND{32*[((Fout)/Fin)*(P*M)-N],0}

This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4)

gives a comparison frequency of 1.536MHz, a VCO frequency of 60 MHz and an output frequency of 12.000

MHz. The same settings can be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates.

Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used

but an exact frequency match cannot be found. The I2S should be master on the LM49370 so that the data

source can support appropriate SRC as required. This method should only be used with data being read on

demand to eliminate sample rate mismatch problems.

Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use

this rather than the PLL. The LM49370 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock

and 8 kHz modes from a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter

which can affect SNR.

PLL Loop Filter

LM49370 requires a second or third order loop filter on PLL_FILT pin. LM49370 demoboard schematic has the

recommended values to use for the second order filter. Please refer to the LM49370 demoboard schematic.

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ADC_1 CONFIGURATION REGISTER

This register is used to control the LM49370's audio ADC.

Table 12. ADC_1 (0x06h)

Bits Field Description

0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal.

1 CPI_SELECT If set the cell phone input is added to the ADC input signal.

2 LEFT_SELECT If set the left stereo bus is added to the ADC input signal.

3 RIGHT_SELECT If set the right stereo bus is added to the ADC input signal.

5:4 ADC_SAMPLE This programs the closest expected sample rate of the mono ADC, which is a variable required by the AGC

_RATE algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC.

ADC_SAMPLE_RATE Sample Rate

0028 kHz

01212 kHz

10216 kHz

11224 kHz

7:6 HPF_MODE This sets the HPF of the ADC

HPF-MODE HPF Response

002No HPF

FS= 8 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz

012FS= 12 kHz, −0.5 dB @ 450 Hz, Notch @ 82 Hz

FS= 16 kHz, −0.5 dB @ 600 Hz, Notch @ 110 Hz

FS= 8 kHz, −0.5 dB @ 150 Hz, Notch @ 27 Hz

102FS= 12 kHz, −0.5 dB @ 225 Hz, Notch @ 41 Hz

FS= 16 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz

112No HPF

ADC_2 CONFIGURATION REGISTER

This register is used to control the LM49370's audio ADC.

Table 13. ADC_2 (0x07h)

Bit Field Description

0 ADC_MODE This sets the oversampling ratio of the ADC

MODE ADC OSR

0 125fs

1 128fs

1 ADC_MUTE If set, the analog inputs to the ADC are muted.

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Table 13. ADC_2 (0x07h) (continued)

Bit Field Description

4:2 AGC_FRAME_TIME This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC's peak detector

determines the peak value of the incoming microphone audio signal and compares this value to the target

value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in order to adjust the microphone

preamplifier's gain accordingly. AGC_FRAME_TIME basically sets the sample rate of the AGC to adjust for a

wide variety of speech patterns. (1)

AGC_FRAME_TIME Time (ms)

000296

0012128

0102192

0112256

1002384

1012512

1102768

11121000

6:5 ADC_CLK This selects the clock to be used by the audio ADC system.

ADC_CLK Source

002MCLK

012PLL_OUTPUT

102I2S_CLK_IN

112PCM_CLK_IN

7 NGZXDD If set, the noise gate will not wait for a zero crossing before mute/unmuting. This bit should be set if the ADC's

HPF is disabled and if there is a large DC or low frequency component at the ADC input.

NGZXDD Result

0 Noise Gate operates on ZXD events

1 Noise Gate operates on frame boundaries

(1) Refer to the AGC Overview for further detail.

AGC_1 CONFIGURATION REGISTER

This register is used to control the LM49370's Automatic Gain Control. (2)

Table 14. AGC_1 (0x08h)

Bit Field Description

If set, the AGC controls the analog microphone preamplifier gain into the system. This feature is useful for

0 AGC_ENABLE microphone signals that are routed to the ADC.

3:1 AGC_TARGET This programs the target level of the AGC. This will depend on the expected transients and desired headroom.

Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail.

AGC_TARGET Target Level

0002−6 dB

0012−8 dB

0102−10 dB

0112−12 dB

1002−14 dB

1012−16 dB

1102−18 dB

1112−20 dB

If set, signals below the noise gate threshold are muted. The noise gate is only activated after a set period of

4 NOISE_GATE_ON signal absence.

(2) See the AGC Overview.

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Table 14. AGC_1 (0x08h) (continued)

Bit Field Description

7:5 NOISE_ This field sets the expected background noise level relative to the peak signal level. The sole presence of

GATE_ signals below this level will not result in an AGC gain change of the input and will be gated from the ADC

THRES output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is

required by the AGC algorithm.

NOISE_GATE_THRES Level

0002−72 dB

0012−66 dB

0102−60 dB

0112−54 dB

1002−48 dB

1012−42 dB

1102−36 dB

1112−30 dB

AGC_2 CONFIGURATION REGISTER

This register is used to control the LM49370's Automatic Gain Control.

Table 15. AGC_2 (0x09h)

Bits Field Description

3:0 AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier.

AGC_MAX_GAIN Max Preamplifier Gain

000026 dB

000128 dB

0010210 dB

0011212 dB

01002to 1100214 dB to 30 dB

1101232 dB

1110234 dB

1111236 dB

6:4 AGC_DECAY This programs the speed at which the AGC will increase gains if it detects the input level is a quiet signal.

AGC_DECAY Step Time (ms)

000232

001264

0102128

0112256

1002512

10121024

11022048

11124096

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Table 15. AGC_2 (0x09h) (continued)

Bits Field Description

7 AGC_TIGHT If set, the AGC algorithm controls the microphone preamplifier more exactly. (1)

AGC_TIGHT = 0 AGC_TARGET Min Level Max Level

0002−6 dB −3 dB

0012−8 dB −4 dB

0102−10 dB −5 dB

0112−12 dB −6 dB

1002−14 dB −7 dB

1012−16 dB −8 dB

1102−18 dB −9 dB

1112−20 dB −10 dB

AGC_TIGHT = 1 0002−6 dB −3 dB

0012−8 dB −5 dB

0102−10 dB −7 dB

0112−12 dB −9 dB

1002−14 dB −11 dB

1012−16 dB −13 dB

1102−18 dB −15 dB

1112−20 dB −17 dB

(1) The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for

recording on the ADC. When the analog path is used this bit should be set to ensure the target is tightly adhered to. If the ADC is the

only destination of the microphone or the desired analog mixer level is line level then AGC_TIGHT should be cleared, allowing greater

dynamic rage of the recorded signal. For further details see the AGC Overview.

AGC_3 CONFIGURATION REGISTER

This register is used to control the LM49370's Automatic Gain Control. (2)

Table 16. AGC_3 (0x0Ah)

Bits Field Description

4:0 AGC_HOLDTIME This programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone

preamplifier. AGC_HOLDTIME No. of speech segments

0000020

0000121

0001022

0001123

001002to 1110024 to 28

11101229

11110230

11111231

(2) See the AGC Overview.

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(1)

(1) Decay hold time, (2) Slow Decay, (3) Quick Attack

(2) (3)

12 dB 10 dB

14 dB

12 dB

signal below target

attack

decay

microphone gain

target level

signal above target

peak detection

and ADC output

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Table 16. AGC_3 (0x0Ah) (continued)

Bits Field Description

7:5 AGC_ATTACK This programs the speed at which the AGC will reduce gains if it detects the input level is too large.

AGC_ATTACK Step Time (ms)

000232

001264

0102128

0112256

1002512

10121024

11022048

11124096

AGC OVERVIEW

The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data

when the level of the source is unknown. A target level for the output is set so that any transients on the input

won’t clip during normal operation. The AGC circuit then compares the output of the ADC to this level and

increases or decreases the gain of the microphone preamplifier to compensate. If the audio from the microphone

is to be output digitally through the ADC then the full dynamic range of the ADC can be used automatically. If the

output is through the analog mixer then the ADC is used to monitor the microphone level. In this case, the analog

dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients closely to

the target level.

To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone

preamplifier gain, the ADC output is passed through an envelope detector. This frames the output of the ADC

into time segments roughly equal to the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the

circuit must also know the sample rate of the data from the ADC (ADC_SAMPLERATE). If after a programmable

number of these segments (AGC_HOLDTIME), the level is consistently below target, the gain will be increased

at a programmable rate (AGC_DECAY). If the signal ever exceeds the target level (AGC_TARGET) then the gain

of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demonstrated below:

Figure 15. AGC Operation Example

The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers

a rise in the gain [(1) →(2)]. After some time the real analog input increases and it reaches the threshold for a

gain reduction which decreases the gain at a faster rate [(2) →(3)] to allow the elimination of typical popping

noises.

Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier

gain. The signal to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some

situations it is preferable to remove audio considered to be consisting solely of background noise from the audio

output; for example conference calls. This can be done by setting NOISE_GATE_ON. This does not affect the

performance of the AGC algorithm.

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The AGC algorithm should not be used where very large background noise is present. If the type of input data,

application and microphone is known then the AGC will typically not be required for good performance, it is

intended for use with inputs with a large dynamic range or unknown nominal level. When setting

NOISE_GATE_THRESHOLD be aware that in some mobile phone scenarios the ADC SNR will be dictated by

the microphone performance rather than the ADC or the signal. Gain changes to the microphone are performed

on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC, the ADC's

HPF should always be enabled.

MIC_1 CONFIGURATION REGISTER

This register is used to control the microphone configuration.

Table 17. MIC_1 (0x0Bh)

Bits Field Description

3:0 PREAMP_GAIN This programs the gain applied to the microphone preamplifier if the AGC is not in use.

PREAMP_GAIN Gain

000026 dB

000128 dB

0010210 dB

0011212 dB

01002to 1100214 dB to 30 dB

1101232 dB

1110234 dB

1111236 dB

4 MIC_MUTE If set, the microphone preamplifier is muted.

5 INT_SE_DIFF If set, the internal microphone is assumed to be single ended and the negative connection is connected to the

ADC common mode point internally. This allows a single-ended internal microphone to be used.

6 INT_EXT If set, the single ended external microphone is used and the negative microphone input is grounded internally,

otherwise internal microphone operation is assumed. (1)

(1) On changing INT_EXT from internal to external note that the dc blocking cap will not be charged so some time should be taken (300ms

for a 1µF cap) between the detection of an external headset and the switching of the output stages and ADC to that input to allow the

DC points on either side of this cap to stabilize. This can be accomplished by deselecting the microphone input from the audio outputs

and ADC until the DC points stabilize. An active MIC path to CPOUT or the ADC may result in the microphone DC blocking caps

causing audio pops under the following situations:1) Switching between internal and external microphone operation while in chip modes

'10' or '11'.2) Toggling in and out of powerdown/standby modes.3) Toggling between chip modes '10' and '11' whenever external

microphone operation is selected.4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone

operation is selected. To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC

until the DC points stabilize.

MIC_2 CONFIGURATION REGISTER

This register is used to control the microphone configuration.

Table 18. MIC_2 (0x0Ch)

Bits Field Description

0 OCL_ This selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the

VCM_ available supply and the power output requirements of the headphone amplifiers.

VOLTAGE OCL_VCM_VOLTAGE Voltage

0 1.2V

1 1.5V

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Table 18. MIC_2 (0x0Ch) (continued)

Bits Field Description

2:1 MIC_ This selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven

BIAS_ at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE

VOLTAGE should be set to '11' only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = '00' (EXT_BIAS = 2.0V)

should not be used to generate the EXT_BIAS supply for a cellular headset external microphone. Please refer

to Table 19 for more detail.

MIC_BIAS_VOLTAGE EXT_BIAS/INT_BIAS

0022.0V

0122.5V

1022.8V

1123.3V

3 BUTTON_TYPE If set, the LM49370 assumes that the button (if used) in the headset is in series (series push button) with the

microphone, opening the circuit when pressed. The default is for the button to be in parallel (parallel push

button), shorting out the microphone when pressed.

5:4 BUTTON_ This sets the time used for debouncing the pushing of the button on a headset with a parallel push button.

DEBOUNCE_ BUTTON_DEBOUNCE_TIME Time (ms)

TIME 0020

0128

10216

11232

In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS -

OCL_VCM_ VOLTAGE) and the maximum output power possible from the headphones. A lower

OCL_VCM_VOLTAGE gives a higher microphone supply voltage but a lower maximum output power from the

headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_VSS.

Table 19. External MIC Supply Voltages in OCL Mode

Available Recommended Supply to Microphone

A_VDD EXT_MIC_BIAS OCL_VCM_VOLT = 1.5V OCL_VCM_VOLT = 1.2V

> 3.4V 3.3V 1.8V 2.1V

2.9V to 3.4V 2.8V 1.3V 1.6V

2.8V to 2.9V 2.5V 1.0V 1.3V

2.7V to 2.8V 2.5V - 1.3V

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SIDETONE ATTENUATION REGISTER

This register is used to control the analog sidetone attenuation. (1)

Table 20. SIDETONE (0x0Dh)

Bits Field Description

3:0 SIDETONE_ This programs the attenuation applied to the microphone preamp output to produce a sidetone signal.

ATTEN SIDETONE_ATTEN Attenuation

00002-Inf

00012−30 dB

00102−27 dB

00112−24 dB

01002−21 dB

01012to 10102−18 dB to −3 dB

10112to 111120 dB

(1) An active SIDETONE path to an audio output may result in the microphone DC blocking caps causing audio pops under the following

situations:1) Switching between internal and external microphone operation while in chip modes '10' or '11'.2) Toggling in and out of

powerdown/standby modes.3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected.4) The

insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected.To avoid potential

pop noises, it is recommended to set SIDETONE_ATTEN to '0000' until DC points have stabilized whenever the SIDETONE path is

used.

CP_INPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone input.

Table 21. CP_INPUT (0x0Eh)

Bits Field Description

4:0 CPI_LEVEL This programs the gain/attenuation applied to the cell phone input.

CPI_LEVEL Level

000002−34.5 dB

000012−33 dB

000102−31.5 dB

000112−30 dB

00100 to 111002−28.5 dB to +7.5 dB

111012+9 dB

111102+10.5 dB

111112+12 dB

5 CPI_MUTE If set, the CPI input is muted at source.

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AUX_LEFT CONFIGURATION REGISTER

This register is used to control the left aux analog input.

Table 22. AUX_LEFT (0x0Fh)

Bits Field Description

4:0 AUX_ This programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (1)

LEFT_ AUX_LEFT_LEVEL Level (With Boost) Level (Without Boost)

LEVEL 000002−34.5 dB −46.5 dB

000012−33 dB −45 dB

000102−31.5 dB −43.5 dB

000112−30 dB −42 dB

00100 to 111002−28.5 dB to +7.5 dB −40.5 dB to −4.5 dB

111012+9 dB −3 dB

111102+10.5 dB −1.5 dB

111112+12 dB 0 dB

5 AUX_ If set, the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above).

LEFT_

BOOST

6 AUX_L_MUTE If set, the AUX LEFT input is muted.

7 AUX_OR_DAC_L If set, the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be passed to the

mixer.

(1) The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available.

Clipping may occur if the analog power supply is insufficient to cater for the required gain.

AUX_RIGHT CONFIGURATION REGISTER

This register is used to control the right aux analog input.

Table 23. AUX_RIGHT (0x10h)

Bits Field Description

4:0 AUX_ This programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (1)

RIGHT_ AUX_RIGHT_LEVEL Level (With Boost) Level (Without Boost)

LEVEL 000002−34.5 dB −46.5 dB

000012−33 dB −45 dB

000102−31.5 dB −43.5 dB

000112−30 dB −42 dB

00100 to 111002−28.5 dB to +7.5 dB −40.5 dB to −4.5 dB

111012+9 dB −3 dB

111102+10.5 dB −1.5 dB

111112+12 dB 0 dB

5 AUX_ If set, the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above).

RIGHT_BOOST

6 AUX_R_MUTE If set, the AUX RIGHT input is muted.

7 AUX_OR_DAC_R If set, the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be passed to

the mixer.

(1) The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available.

Clipping may occur if the analog power supply is insufficient to cater for the required gain.

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DAC CONFIGURATION REGISTER

This register is used to control the DAC levels to the mixer.

Table 24. DAC (0x11h)

Bits Field Description

4:0 DAC_LEVEL This programs the gain/attenuation applied to the DAC input to the mixer. (1)

DAC_LEVEL Level (With Boost) Level (Without Boost)

000002−34.5 dB −46.5 dB

000012−33 dB −45 dB

000102−31.5 dB −43.5 dB

000112−30 dB −42 dB

00100 to 111002−28.5 dB to +7.5 dB −40.5 dB to −4.5 dB

111012+9 dB −3 dB

111102+10.5 dB −1.5 dB

111112+12 dB 0 dB

5 DAC_BOOST If set, the gain of the DAC inputs to the mixer is increased by 12dB (see above).

6 DAC_MUTE If set, the stereo DAC input is muted on the next zero crossing.

7 USE_AUX_ If set, the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing a stereo

LEVELS balance to be applied.

(1) The output from the DAC is 1V RMS for a full scale digital input. This can be boosted by 12 dB if enough headroom is available.

Clipping may occur if the analog power supply is insufficient to cater for the required gain.

CP_OUTPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone output.(2)

Table 25. CP_OUTPUT (0x12h)

Bit Field Description

0 MIC_SELECT If set, the microphone channel of the mixer is added to the CP_OUT output signal.

1 RIGHT_SELECT If set, the right channel of the mixer is added to the CP_OUT output signal.

2 LEFT_SELECT If set, the left channel of the mixer is added to the CP_OUT output signal.

3 CPO_MUTE If set, the CPOUT output is muted.

4 MIC_NOISE_GAT If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be gated if the signal is

E determined to be noise by the AGC (that is, if the signal is below the set noise threshold).

(2) The gain of cell phone output amplifier is 0 dB.

AUX_OUTPUT CONFIGURATION REGISTER

This register is used to control the differential auxiliary output. (1)

Table 26. AUX_OUTPUT (0x13h)

Bits Field Description

0 CPI_SELECT If set, the cell phone input channel of the mixer is added to the AUX_OUT output signal.

1 RIGHT_SELECT If set, the right channel of the mixer is added to the AUX_OUT output signal.

2 LEFT_SELECT If set, the left channel of the mixer is added to the AUX_OUT output signal.

3 AUX_MUTE If set, the AUX_OUT output is muted.

(1) The gain of the auxiliary output amplifier is 0 dB. If a second (external) loudspeaker amplifier is to be used its gain should be set to 12

dB to match the onboard loudspeaker amplifier gain.

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LS_OUTPUT CONFIGURATION REGISTER

This register is used to control the loudspeaker output.(1)

Table 27. LS_OUTPUT (0x14h)

Bits Field Description

0 CPI_SELECT If set, the cell phone input channel of the mixer is added to the loudspeaker output signal.

1 RIGHT_SELECT If set, the right channel of the mixer is added to the loudspeaker output signal.

2 LEFT_SELECT If set, the left channel of the mixer is added to the loudspeaker output signal.

3 LS_MUTE If set, the loudspeaker output is muted.

4 RSVD Reserved.

(1) The gain of the loudspeaker output amplifier is 12 dB.

HP_OUTPUT CONFIGURATION REGISTER

This register is used to control the stereo headphone output.(1)

Table 28. HP_OUTPUT (0x15h)

Bits Field Description

0 SIDETONE_SELECT If set, the sidetone channel of the mixer is added to both of the headphone output signals.

1 CPI_SELECT If set, the cell phone input channel of the mixer is added to both of the headphone output signals.

2 RIGHT_SELECT If set, the right channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set,

the right channel is added to the right headphone output signal only. If the STEREO bit (0x00h) is

cleared, it is added to both the right and left headphone output signals.

3 LEFT_SELECT If set, the left channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is set,

the left channel is added to the left headphone output signal only. If the STEREO bit (0x00h) is cleared, it

is added to both the right and left headphone output signals.

4 HP_MUTE If set, the headphone output is muted.

5 STEREO If set, the mixers assume that the signals on the left and right internal busses are highly correlated and

when these signals are combined their levels are reduced by 6dB to allow enough headroom for them to

be summed.

6 OCL If set, the part is placed in OCL (Output Capacitor Less) mode.

(1) The gain of the headphone output amplifier is –6 dB for the cell phone input channel and sidetone channel of the mixer. When the

STEREO bit (0x00h) is set, headphone output amplifier gain is –6 dB for the left and right channel. When the STEREO bit (0x00h) is

cleared, the headphone output amplifier gain is –12 dB for the left and right channel (to allow enough headroom for adding them and

routing them to both headphone amplifiers).

EP_OUTPUT CONFIGURATION REGISTER

This register is used to control the mono earpiece output.(1)

Table 29. EP_OUTPUT (0x16h)

Bits Field Description

0 SIDETONE_SELECT If set, the sidetone channel of the mixer is added to the earpiece output signal.

1 CPI_SELECT If set, the cell phone input channel of the mixer is added to the earpiece output signal.

2 RIGHT_SELECT If set, the right channel of the mixer is added to the earpiece output signal.

3 LEFT_SELECT If set, the left channel of the mixer is added to the earpiece output signal.

4 EP_MUTE If set, the earpiece output is muted.

(1) The gain of the earpiece output amplifier is 6 dB.

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DETECT CONFIGURATION REGISTER

This register is used to control the headset detection system.

Table 30. DETECT (0x17h)

Bits Field Description

0 DET_INT If set, an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ

that has been triggered by the headset detect.

1 BTN_INT If set, an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that has been

triggered by a button event.

2 TEMP_INT If set, an IRQ is raised during a temperature event. The LM49370 will still automatically cycle the class AB

power amplifiers off if the internal temperature is too high. This bit should not be set whenever the class D

amplifier is turned on. Clearing this bit will clear an IRQ that has been triggered by a temperature event.

6:3 HS_ This sets the time used for debouncing the analog signals from the detection inputs used to sense the

DBNC_TIME insertion/removal of a headset.

HS_DBNC_TIME Time (ms)

000020

000128

0010216

0011232

0100248

0101264

0110296

01112128

10002192

10012256

10102384

10112512

11002768

110121024

111021536

111122048

HEADSET DETECT OVERVIEW

The LM49370 has built in monitors to automatically detect headset insertion or removal. The detection scheme

can differentiate between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset

insertion or removal, the LM49370 updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo

headset and bit 2 - headset without mic / with mic, of the STATUS register (0x18h). Headset insertion/removal

and headset type can also be detected in standby mode; this consumes no analog supply current when the

headset is absent.

The LM49370 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is

sensed by setting bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is

not detected, the HPL_OUT and HPR_OUT amplifiers will be disabled (switched off for capless mode and muted

for AC-coupled mode) and the EXT_BIAS pin will be disconnected from the MIC_BIAS amplifier, irrespective of

control register settings.

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47:

g m s

Stereo +

Cellular s

47:

g m

Cellular s

g s

Stereo s

g m s

Stereo +

Cellular s

g m

Cellular s

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The LM49370 also has the capability to detect button press, when a button is present on the headset

microphone. Both parallel button-type (in parallel with the headset microphone, default value) and series button-

type (in series with the headset microphone) can be detected; the button type used needs to be defined in bit 3

of MIC_2 (0x0Ch). Button press can also be detected in stand-by mode; this consumes 10 µA of analog supply

current for a series type push button and 100 µA for a parallel type push button. Upon button press, the

LM49370 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected (INT_EXT =

0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before

BTN (bit 3 of STATUS (0x18h)) can be read. The LM49370 can also be programmed to raise an interrupt on the

IRQ pin when button press is sensed by setting bit 1 of DETECT (0x17h).

The LM49370 provides debounce programmability for headset and button detect. Debounce programmability can

be used to reject glitches generated, and hence avoid false detection, while inserting/removing a headset or

pressing a button.

Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel

button press debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch).

Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from

headset removal, the debounce time for series button press in defined by HS_DBNC_TIME.

Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For

reliable headset / push button detection all following bits should be defined before enabling the headset detection

system:

1. the OCL-bit (AC-Coupled / Capless headphone interface (bit 6 of HP_OUTPUT (0x15h))

2. the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h))

3. the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch))

4. the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch))

Figure 16 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid

any DC path from the MIC_DET pin to ground when a headset is not inserted.

Figure 16. Headset Configurations Supported by the LM49370

Product Folder Links: LM49370

g m s

Stereo +

Cellular s

g m

Cellular s

g s

Stereo s

m = mic

s = speaker

g = virtual ground

1 PF

EXT_MIC

HP_L

HP_R

HP_VMID_FB

HP_VMID

LM49370

MIC_DET

EXT_MIC_BIAS

2.2 k:

3.3/2.8/2.5V

1.2/1.5V

Connection for OCL Mode (DC-Coupled) Headset Detection

g m s

Stereo +

Cellular s

g m

Cellular s

g s

Stereo s

m = mic

s = speaker

g = ground (A_VSS)1 k:

47 PF

1 PF

EXT_MIC

HP_L

HP_R

HP_VMID_FB

HP_VMID

1 k:

MIC_DET

EXT_MIC_BIAS

2.2 k:

2.0/2.5V

A_VDD/2

Connection for Non-OCL Mode (AC-Coupled) Headset Detection

47 PF

LM49370

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The wiring of the headset jack to the LM49370 will depend on the intended mode of the headphone amplifier:

Figure 17. Connection of Headset Jack to LM49370 Depends on the Mode of the Headphone Amplifier.

In non-OCL mode, two 1kΩresistors are optional and not needed if chip is active without headset event

detection in Basic Register (0x00h) bits 1:0. If chip is active with headset event detection, these two resistors set

an internal threshold voltage for a comparator that produces the headphone detect pulse. The value of these

should be 1kΩwith tolerance of ±10% or better.

STATUS REGISTER

This register is used to report the status of the device.

Table 31. STATUS (0x18h)(1)(2)

Bits Field Description

0 HEADSET This field is high when headset presence is detected (only valid if the detection system is enabled).(1)

1 STEREO_ This field is high when a headset with stereo speakers is detected (only valid if the detection system is

HEADSET enabled). (1)

2 MIC This field is high when a headset with a microphone is detected (only valid if the detection system is

enabled).(1)

(1) The detection IRQ is cleared when this register has been written to.

(2) This field is cleared whenever the STATUS (0x18h) register has been written to.

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Table 31. STATUS (0x18h)(1)(2) (continued)

Bits Field Description

3 BTN This field is high when the button on the headset is pressed (only valid if the detection system is enabled).

IRQ is cleared when the button has been released and this register has been written to. (2)

4 TEMP If this field is high then a temperature event has occurred (write to this register to clear IRQ). This field will

stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid whenever the

loudspeaker amplifier is turned off. (2)

5 GPIN1 When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back here.

6 GPIN2 When GPIO_SEL is set to a readable configuration, a digital input on the relevant GPIO can be read back

here.

3D CONFIGURATION REGISTER

This register is used to control the configuration of the 3D circuit.

Table 32. 3D (0x19h)

Bits Field Description

0 3D_ENB Setting this bit enables the 3D effect. When cleared to zero, the 3D effect is disabled and the 3D module

then passes the I2S left and right channel inputs to the DAC unchanged. The stereo AUX inputs are

unaffected by the 3D module.

1 3D_TYPE This bit selects between type 1 and type 2 3D sound effect. Clearing this bit to zero selects type 1 effect and

setting it to one selects type 2.

Type1: Rout = Ri-G*Lout3d, Lout = Li-G*Rout3d

Type2: Rout = -Ri-G*Lout3d, Lout = Li+G*Rout3d

where,

Ri = Right I2S channel input

Li = Left I2S channel input

G = 3D gain level (Mix ratio)

Rout3d = Ri filtered through a high-pass filter with a corner frequency controlled by FREQ

Lout3d = Li filtered through a high-pass filter with a corner frequency controlled by FREQ

3:2 LEVEL This programs the level of 3D effect that is applied. LEVEL

00225%

01237.5%

10250%

11275%

5:4 FREQ This programs the HPF rolloff (-3dB) frequency of the 3D effect.FREQ

0020Hz

012300Hz

102600Hz

112900Hz

6 ATTENUATE Clearing this bit to zero maintains the level of the left and right input channels at the output. Setting this bit

to one attenuates the output level by 50%.

This may be appropriate for high level audio inputs when type 2 3D effect is used. Type 2 effect involves

adding the same polarity of left and right inputs to give the final outputs. Type 2 effect has the potential for

creating a clipping condition, however this bit offers an alternative to clipping.

7 CUST_COMP If set, the DAC compensation filter may be programmed by the user through registers (0x20h) to( 0x25h).

Otherwise, the defaults are used.

Product Folder Links: LM49370

I2S

CLKGEN

ADC_CLOCK

DAC_CLOCK

I2S_CLK_IN

I2S

WSGEN

I2S_WS_IN

I2S_WS

I2S_WS_OUT

I2S_CLK

I2S_CLK_OUT

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I2S PORT MODE CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

Table 33. I2S Mode (0x1Ah)

Bit Field Description

0 I2S_OUT_ENB If set, the I2S output bus is enabled. If cleared, the I2S output will be tristate and all RX clocks will be

gated.

1 I2S_IN_ENB If set, the I2S input is enabled. If this bit cleared, the I2S input is ignored and all TX clocks gated.

2 I2S_MODE This programs the format of the I2S interface. Definition

0 Normal

1 Left Justified

3 I2S_STEREO_REVERSE If set, the left and right channels are reversed. Operation

0 Normal

1 Reversed

4 I2S_WS_MS If set, I2S_WS generation is enabled and is Master. If cleared, I2S_WS acts as slave.

6:5 I2S_WS_GEN_MODE This programs the I2S word length.

Bits/Word

00216

01225

10232

112—

7 I2S_WORD_ORDER This bit alters the RX phasing of left and right channels. If this bit is cleared: right then left. If this bit is

set: left then right.

Figure 18. I2S Audio Port CLOCK/SYNC Options

I2S PORT CLOCK CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

Table 34. I2S Clock (0x1Bh)

Bit Field Description

0 I2S_CLOCK_MS If set, then I2S clock generation is enabled and is Master. If this bit is cleared, then the I2S clock is driven

by the device slave.

1 I2S_CLOCK_SOURCE This selects the source of the clock to be used by the I2S clock generator.

I2S_CLOCK_SOURCE Clock is source from

0 DAC (from R divider)

1 ADC (from Q divider)

Product Folder Links: LM49370

0 24 23 22 21 3 2 1 0 24 23 22 21 3 2 1 0 24

I2S_CLK

I2S_SDO/

I2S_SDI

I2S_WS

Left Word Right Word

LM49370

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Table 34. I2S Clock (0x1Bh) (continued)

Bit Field Description

5:2 I2S_CLOCK_GEN_MODE This programs a clock divider that divides the clock defined by I2S_CLOCK_SOURCE. This divided

clock is used to generate I2S_CLK in Master mode.(1)

Value Divide By Ratio

000021

000122

001024

001126

010028

0101210

0110216

0111220 —

100022.5 2/5

100123 1/3

101023.90625 32/125

101125 25/125

110027.8125 16/125

11012— —

11102— —

11112— —

7:6 PCM_SYNC_WIDTH This programs the width of the PCM sync signal. Generated SYNC Looks like:

0021 bit (Used for Short PCM Modes)

0124 bits (Used for Long PCM Modes)

1028 bits (Used for Long PCM Modes)

11215 bits (Used for Long PCM Modes)

Should not be set if the bits/word is less than 16.

(1) For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a

divided by two version of the clock at the output of the R divider.

DIGITAL AUDIO DATA FORMATS

I2S master mode can only be used when the DAC is enabled unless the FORCE_RQ bit is set. PCM Master

mode can only be used when the ADC is enabled, unless the FORCE_RQ bit is set. If the PCM receiver

interface is operated in slave mode the clock and sync should be enabled at the same time because the PCM

receiver uses the first PCM frame to calculate the PCM interface format. This format can not be changed unless

a soft reset is issued. Operating the LM49370 in master mode eliminates the risk of sample rate mismatch

between the data converters and the audio interfaces.

In slave mode, the PCM and I2S receivers only record the 1st 16 and 18 bits of the serial words respectively. The

I2S and PCM formats are as followed:

Figure 19. I2S Serial Data Format (Default Mode)

Product Folder Links: LM49370

0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9

PCM_CLK

PCM_SDO/

PCM_SDI

PCM_SYNC

Short frame sync mode (PCM_SYNC_WIDTH = '00')

Long frame sync mode (PCM_SYNC_WIDTH = '11')

0 24 23 22 21 3 2 1 0 24 23 22 21 3 2 1 0 24

I2S_CLK

I2S_SDO/

I2S_SDI

I2S_WS

Left Word Right Word

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Figure 20. I2S Serial Data Format (Left Justified)

Figure 21. PCM Serial Data Format (16 bit Slave Example)

PCM PORT MODE CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

Table 35. PCM MODE (0x1Ch)

Bits Field Description

0 PCM_OUT_ENB If set, the PCM output bus is enabled. If this bit is cleared, thr PCM output will be tristate and all RX

clocks will be gated.

1 PCM_IN_ENB If set, the PCM input is enabled. If this bit is cleared, the PCM input is ignored and TX clocks are

generated.

3 PCM_CLOCK_SOURCE DAC or ADC Clock 0 = DAC, 1 = ADC (1)

4 PCM_SYNC_MS If set, PCM_SYNC generation is enabled and is driven by the device (Master).

5 PCM_SDO_LSB_HZ If set, when the PCM port has run out of bits to transmit, it will tristate the SDO output.

6 PCM_COMPAND If set, the data sent to the PCM port is companded and the PCM data received by the PCM receiver

is treated as companded data.

7 PCM_ALAW_μLAW If PCM_ COMPAND is set, then the data across the PCM interface to the DAC and from the ADC is

companded as follows:

PCM_ALAW_μLAW Commanding Type

0μ-LAW

1 A-Law

(1) For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a

divided by two version of the clock at the output of the R divider.

Product Folder Links: LM49370

PCM

CLKGEN

ADC_CLOCK

DAC_CLOCK

PCM_CLK_IN

PCM

SYNCGEN

PCM_SYNC_IN

PCM_SYNC

PCM_SYNC_OUT

PCM_CLOCK

PCM_CLK_OUT

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Figure 22. PCM Audio Port CLOCK/SYNC Options

PCM PORT CLOCK CONFIGURATION REGISTER

This register is used to control the configuration of audio data interfaces.

Table 36. PCM Clock (0x1Dh)

Bits Field Description

3:0 PCM_CLOCK_ This programs a clock divider that divides the clock defined by PCM_CLOCK_SOURCE reg(0x1Ch).

GEN_MODE The divided clock is used to generate PCM_CLK in Master mode. (1)

Value Divide By Ratio

000021

000122

001024

001126

010028

0101210

0110216

0111220 —

100022.5 2/5

100123 1/3

101023.90625 32/125

101125 25/125

110027.8125 16/125

11012— —

11102— —

11112— —

6:4 PCM_SYNC_MODE This programs a clock divider that divides PCM_CLK. The divided clock is used to generate

PCM_SYNC.

Valve Divide By

00028

001216

010225

011232

100264

1012128

1102—

1112—

(1) For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a

divided by two version of the clock at the output of the R divider.

Product Folder Links: LM49370

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SRC CONFIGURATION REGISTER

This register is used to control the configuration of the Digital Routing interfaces. (2)

Table 37. Bridges (0x1Eh)

Bits Field Description

0 PCM_TX_SEL This controls the data sent to the PCM transmitter.

PCM_TX_SEL Source

0 ADC

1 MONO SUM Circuit

2:1 I2S_TX_SEL This controls the data sent to the I2S transmitter.

I2S_TX_SEL Source

002ADC

012PCM Receiver

102DAC Interpolator (oversampled)

112Disabled

4:3 DAC_INPUT_SEL This controls the data sent to the DAC.

DAC_INPUT_SEL Source

002I2S Receiver (In stereo)

012PCM Receiver (Dual Mono)

102ADC

112Disabled

5 MONO_SUM_SEL This controls the data sent to the Stereo to Mono Converter

MONO_SUM_SEL Source

0 DAC Interpolated Output

1 I2S Receiver Output

7:6 MONO_SUM_MODE This controls the operation of the Stereo to Mono Converter.

MONO_SUM_ MODE Operation

002(Left + Right)/2

012Left

102Right

112(Left + Right)/2

(2) Please refer to the Application Note AN-1591 (SNAA039) for the detailed discussion on how to use the I2S to PCM Bridge.

Product Folder Links: LM49370

I2S

I2S_TX_SEL

I2S_SDO

I2S_SDI

Automatic Handshaking

Sample & Hold

PCM

PCM_TX_SEL

PCM_SDO

PCM_SDI

STEREO/

MONO MONO_SUM_MODE

MONO_SUM_SEL

DAC_TX_SEL

@FSI FIR

Interp

DSDM

DAC_SRC_MODE

Stereo DAC

IIR

Dec

Mono ADC

CIC

ADC_SRC_MODE

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Figure 23. I2S to PCM Bridge

GPIO CONFIGURATION REGISTER

This register is used to control the GPIOs and to control the digital signal routing when using the ADC and DAC

to perform sample rate conversion.

Table 38. GPIO Control (0x1Fh)

Bits Field Description

2:0 GPIO_1_SEL This configures the GPIO_1 pin.

GPIO_1_SEL Does What? Direction

0002Disable HiZ

0012SPI_SDO Output

0102Output 0 Output

0112Output 1 Output

1002Read Input

1012Class D Enable Output

1102AUX Enable Output

1112Dig_Mic_Data Input

5:3 GPIO_2_SEL This configures the GPIO_2 pin.

GPIO_2_SEL Does What? Direction

0002Disable HiZ

0012SPI_SDO Output

0102Output 0 Output

0112Output 1 Output

1002Read Input

1012Class D Enable Output

1102Dig_Mic L Clock Output

1112Dig_Mic R Clock Output

6 ADC_SRC_MODE If set, the ADC analog is disabled and the digital is enabled, using the resampler input.

7 DAC_SRC_MODE This does not have to be set to use DAC in SRC mode, but should be set if the user wishes to disable the

DAC analog to save power.

Product Folder Links: LM49370

Z-1

Z-1 Z-1 Z-1

C1 C2 C3 C4

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DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS

To allow for compensation of roll off in the DAC and analog filter sections an FIR compensation filter is applied to

the DAC input data at the original sample rate. Since the DAC can operate at different over sampling ratios the

FIR compensation filter is programmable. By default the filter applies approx 2dB of compensation at 20kHz. 5

taps is sufficient to allow passband equalization and ripple cancellation to around +/0.01dB.

The filter can also be used for precise digital gain and simple tone controls although a DSP or CPU should be

used for more powerful tone control if required. As the FIR filter must always be phase linear, the coefficients are

symmetrical. Coefficients C0, C1, and C2 are programmable, C3 is equal to C1 and C4 is equal to C0. The

maximum power of this filter must not exceed that of the examples given below:

Figure 24. FIR Consumption Filter Taps

Sample Rate DAC_MODE C0 C1 C2 C3 C4

48kHz 00 334 –2291 26984 –2291 343

48kHz 01 61 –371 25699 –371 61

For DAC_MODE = '00 and '01', the defaults should be sufficient; but for DAC_MODE = '10' and '11', care should

be taken to ensure the widest bandwidth is available without requiring such a large attenuation at DC that inband

noise becomes audible.

Table 39. Compensation Filter C0 LSBs (0x20h)

Bits Field Description

7:0 C0_LSB Bits 7:0 of C0[15:0]

Table 40. Compensation Filter C0 MSBs (0x21h)

Bits Field Description

7:0 C0_MSB Bits 15:8 of C0[15:0]

Table 41. Compensation Filter C1 LSBs (0x22h)

Bits Field Description

7:0 C1_LSB Bits 7:0 of C1[15:0]

Table 42. Compensation Filter C1 MSBs (0x23h)

Bits Field Description

7:0 C1_MSB Bits 15:8 of C1[15:0]

Table 43. Compensation Filter C2 LSBs (0x24h)

Bits Field Description

7:0 C2_LSB Bits 7:0 of C2[15:0]

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Table 44. Compensation Filter C2 MSBs (0x25h)

Bits Field Description

7:0 C2_MSB Bits 15:8 of C2[15:0]

Product Folder Links: LM49370

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 100 1k 20k

FREQUENCY (Hz)

-3

-1

MAGNITUDE (dB)

-2

10k

50 200 2k500 5k

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 100 1k 20k

FREQUENCY (Hz)

-3

-1

MAGNITUDE (dB)

-2

10k

50 200 2k500 5k

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 100 1k 20k

FREQUENCY (Hz)

-3

-1

MAGNITUDE (dB)

-2

10k

50 200 2k500 5k

LM49370

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Typical Performance Characteristics

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Stereo DAC Frequency Response Stereo DAC Frequency Response Zoom

fS= 8kHz fS= 8kHz

Figure 25. Figure 26.

Stereo DAC Frequency Response Stereo DAC Frequency Response Zoom

fS= 16kHz fS= 16kHz

Figure 27. Figure 28.

Stereo DAC Frequency Response Stereo DAC Frequency Response Zoom

fS= 24kHz fS= 24kHz

Figure 29. Figure 30.

Product Folder Links: LM49370

10m 100m 1

I2S INPUT VOLTAGE (FFS)

0.01

0.1

THD+N (%)

1m 20m 200m2m 50m 500m5m

0.02

0.2

0.05

0.5

20 20k

FREQUENCY (Hz)

-3

-2

-1

MAGNITUDE (dB)

10k1k 2k 5k50 100200 500 30k

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 100 1k 20k

FREQUENCY (Hz)

-3

-1

MAGNITUDE (dB)

-2

10k

50 200 2k500 5k

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Stereo DAC Frequency Response Stereo DAC Frequency Response Zoom

fS= 32kHz fS= 32kHz

Figure 31. Figure 32.

Stereo DAC Frequency Response Stereo DAC Frequency Response Zoom

fS= 48kHz fS= 48kHz

Figure 33. Figure 34.

THD+N

vs Stereo DAC Crosstalk

Stereo DAC Input Voltage (0dB DAC, AUXOUT) (0dB, DAC, HP SE, 32Ω)

Figure 35. Figure 36.

Product Folder Links: LM49370

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

LM49370

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Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 8kHz, 6dB MIC fS= 8kHz, 6dB MIC

Figure 37. Figure 38.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 8kHz, 36dB MIC fS= 8kHz, 36dB MIC

Figure 39. Figure 40.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 16kHz, 6dB MIC fS= 16kHz, 6dB MIC

Figure 41. Figure 42.

Product Folder Links: LM49370

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 16kHz, 36dB MIC fS= 16kHz, 36dB MIC

Figure 43. Figure 44.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 24kHz, 6dB MIC fS= 24kHz, 6dB MIC

Figure 45. Figure 46.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 24kHz, 36dB MIC fS= 24kHz, 36dB MIC

Figure 47. Figure 48.

Product Folder Links: LM49370

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

1k 2k50 100 200 500

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

1k 2k50 100 200 500

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

20 20k

FREQUENCY (Hz)

-0.5

+0.5

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

-0.4

-0.3

-0.2

-0.1

+0.1

+0.2

+0.3

+0.4

20 20k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

10k1k 2k 5k50 100 200 500

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 32kHz, 6dB MIC fS= 32kHz, 6dB MIC

Figure 49. Figure 50.

MONO ADC Frequency Response MONO ADC Frequency Response Zoom

fS= 32kHz, 36dB MIC fS= 32kHz, 36dB MIC

Figure 51. Figure 52.

MONO ADC HPF Frequency Response MONO ADC HPF Frequency Response

fS= 8kHz, 36dB MIC fS= 16kHz, 36dB MIC

(from left to right: HPF_MODE '00', '10', '01') (from left to right: HPF_MODE '00', '10', '01')

Figure 53. Figure 54.

Product Folder Links: LM49370

20 100 1k 10k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 20k200 2k

20 100 1k 10k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 20k200 2k

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

MIC INPUT VOLTAGE (Vrms)

1m 20m 200m2m 50m 500m5m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

100P

MIC INPUT VOLTAGE (Vrms)

40m

200P500P1m 2m 5m 10m 20m

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

1k 2k50 100 200 500

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

+10

MAGNITUDE (dB)

1k 2k50 100 200 500

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

MONO ADC HPF Frequency Response MONO ADC HPF Frequency Response

fS= 24kHz, 36dB MIC fS= 32kHz, 36dB MIC

(from left to right: HPF_MODE '00', '10', '01') (from left to right: HPF_MODE '00', '10', '01')

Figure 55. Figure 56.

MONO ADC THD+N MONO ADC THD+N

vs MIC Input Voltage vs MIC Input Voltage

(fS= 8kHz, 6dB MIC) (fS= 8kHz, 36dB MIC)

Figure 57. Figure 58.

MONO ADC PSRR MONO ADC PSRR

vs vs

Frequency Frequency

AVDD = 3.3V, 6dB MIC AVDD = 5V, 6dB MIC

Figure 59. Figure 60.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 20k200 2k

20 100 1k 10k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 20k200 2k

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

MONO ADC PSRR MONO ADC PSRR

vs vs

Frequency Frequency

AVDD = 3.3V, 36dB MIC AVDD = 5V, 36dB MIC

Figure 61. Figure 62.

AUXOUT PSRR AUXOUT PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX Frequency AVDD = 5V, 0dB AUX

(AUX inputs terminated) (AUX inputs terminated)

Figure 63. Figure 64.

AUXOUT PSRR AUXOUT PSRR

vs vs

Frequency AVDD = 3.3V, 0dB CPI Frequency AVDD = 5V, 0dB CPI

(CPI inputs terminated) (CPI inputs terminated)

Figure 65. Figure 66.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

AUXOUT PSRR AUXOUT PSRR

vs vs

Frequency AVDD = 3.3V, 0dB DAC Frequency AVDD = 5V, 0dB DAC

(DAC inputs selected) (DAC inputs selected)

Figure 67. Figure 68.

CPOUT PSRR CPOUT PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX Frequency AVDD = 5V, 0dB AUX

(AUX inputs terminated) (AUX inputs terminated)

Figure 69. Figure 70.

CPOUT PSRR CPOUT PSRR

vs vs

Frequency AVDD = 3.3V, 0dB DAC Frequency AVDD = 5V, 0dB DAC

(DAC inputs selected) (DAC inputs selected)

Figure 71. Figure 72.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Earpiece PSRR Earpiece PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX Frequency AVDD = 5V, 0dB AUX

(AUX inputs terminated) (AUX inputs terminated)

Figure 73. Figure 74.

Earpiece PSRR Earpiece PSRR

vs vs

Frequency AVDD = 3.3V, 0dB CPI Frequency AVDD = 5V, 0dB CPI

(CPI input terminated) (CPI input terminated)

Figure 75. Figure 76.

Earpiece PSRR Earpiece PSRR

vs vs

Frequency AVDD = 3.3V, 0dB DAC Frequency AVDD = 5V, 0dB DAC

(DAC input selected) (DAC input selected)

Figure 77. Figure 78.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX, OCL 1.2V Frequency AVDD = 5V, 0dB AUX, OCL 1.2V

(AUX inputs terminated) (AUX inputs terminated)

Figure 79. Figure 80.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB CPI, OCL 1.2V Frequency AVDD = 5V, 0dB CPI, OCL 1.2V

(CPI input terminated) (CPI input terminated)

Figure 81. Figure 82.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB ADC, OCL 1.2V Frequency AVDD = 5V, 0dB ADC, OCL 1.2V

(DAC input selected) (DAC input selected)

Figure 83. Figure 84.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX, OCL 1.5V Frequency AVDD = 5V, 0dB AUX, OCL 1.5V

(AUX inputs terminated) (AUX inputs terminated)

Figure 85. Figure 86.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB CPI, OCL 1.5V Frequency AVDD = 5V, 0dB CPI, OCL 1.5V

(CPI input terminated) (CPI input terminated)

Figure 87. Figure 88.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB DAC, OCL 1.5V Frequency AVDD = 5V, 0dB DAC, OCL 1.5V

(DAC input selected) (DAC input selected)

Figure 89. Figure 90.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX, SE Frequency AVDD = 5V, 0dB AUX, SE

(AUX inputs terminated) (AUX inputs terminated)

Figure 91. Figure 92.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB CPI, SE Frequency AVDD = 5V, 0dB CPI, SE

(CPI input terminated) (CPI input terminated)

Figure 93. Figure 94.

Headphone PSRR Headphone PSRR

vs vs

Frequency AVDD = 3.3V, 0dB DAC, SE Frequency AVDD = 5V, 0dB DAC, SE

(DAC input selected) (DAC input selected)

Figure 95. Figure 96.

Product Folder Links: LM49370

20 20k

FREQUENCY (Hz)

-100

PSRR (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

20 20k

FREQUENCY (Hz)

-100

PSRR (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

20 20k

FREQUENCY (Hz)

-100

PSRR (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

20 20k

FREQUENCY (Hz)

-100

PSRR (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

20 20k

FREQUENCY (Hz)

-100

PSRR (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

20 20k

FREQUENCY (Hz)

-100

PSRR (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Loudspeaker PSRR Loudspeaker PSRR

vs vs

Frequency AVDD = 3.3V, 0dB AUX Frequency AVDD = 5V, 0dB AUX

(AUX inputs terminated) (AUX inputs terminated)

Figure 97. Figure 98.

Loudspeaker PSRR Loudspeaker PSRR

vs vs

Frequency AVDD = 3.3V, 0dB CPI Frequency AVDD = 5V, 0dB CPI

(CPI input terminated) (CPI input terminated)

Figure 99. Figure 100.

Loudspeaker PSRR Loudspeaker PSRR

vs vs

Frequency AVDD = 3.3V, 0dB DAC Frequency AVDD = 5V, 0dB DAC

(DAC input selected) (DAC input selected)

Figure 101. Figure 102.

Product Folder Links: LM49370

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

INT/EXT MICBIAS PSRR INT/EXT MICBIAS PSRR

vs vs

Frequency Frequency

AVDD = 3.3V, MICBIAS = 2.0V AVDD = 5V, MICBIAS = 2.0V

Figure 103. Figure 104.

INT/EXT MICBIAS PSRR INT/EXT MICBIAS PSRR

vs vs

Frequency Frequency

AVDD = 3.3V, MICBIAS = 2.5V AVDD = 5V, MICBIAS = 2.5V

Figure 105. Figure 106.

INT/EXT MICBIAS PSRR INT/EXT MICBIAS PSRR

vs vs

Frequency Frequency

AVDD = 3.3V, MICBIAS = 2.8V AVDD = 5V, MICBIAS = 2.8V

Figure 107. Figure 108.

Product Folder Links: LM49370

20 100 1k 10k 20k

0.001

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.002

0.02

0.2

0.005

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.001

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.002

0.02

0.2

0.005

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.001

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.002

0.02

0.2

0.005

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 100k

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR (dB)

50 500 5k 50k20k200 2k

20 100 1k 10k 20k

0.001

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.002

0.02

0.2

0.005

0.05

0.5

50 200 2k500 5k

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

INT/EXT MICBIAS PSRR AUXOUT THD+N

vs vs

Frequency Frequency

AVDD = 5V, MICBIAS = 3.3V AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ

Figure 109. Figure 110.

AUXOUT THD+N CPOUT THD+N

vs vs

Frequency Frequency

AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩAVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ

Figure 111. Figure 112.

CPOUT THD+N Earpiece THD+N

vs vs

Frequency Frequency

AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩAVDD = 3.3V, 0dB, POUT = 500mW, 32Ω

Figure 113. Figure 114.

Product Folder Links: LM49370

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

20 100 1k 10k

FREQUENCY (Hz)

0.01

0.02

0.05

0.1

THD + N (%)

50 500 5k 20k200 2k

0.2

0.5

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Earpiece THD+N Headphone THD+N

vs vs

Frequency Frequency AVDD = 3.3V, OCL 1.5V, 0dB

AVDD = 5V, 0dB, POUT = 50mW, 32ΩPOUT = 7.5mW, 32Ω

Figure 115. Figure 116.

Headphone THD+N Headphone THD+N

vs vs

Frequency AVDD = 5V, OCL 1.5V, 0dB Frequency AVDD = 3.3V, OCL 1.2V, 0dB

POUT = 10mW, 32ΩPOUT = 7.5mW, 32Ω

Figure 117. Figure 118.

Headphone THD+N Headphone THD+N

vs vs

Frequency AVDD = 5V, OCL 1.2V, 0dB Frequency AVDD = 3.3V, SE, 0dB

POUT = 10mW, 32ΩPOUT = 7.5mW, 32Ω

Figure 119. Figure 120.

Product Folder Links: LM49370

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

20 100 1k 10k 20k

0.001

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.002

0.02

0.2

0.005

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.02

0.2

0.05

0.5

50 200 2k500 5k

20 100 1k 10k 20k

0.001

0.01

0.1

THD+N (%)

FREQUENCY (Hz)

0.002

0.02

0.2

0.005

0.05

0.5

50 200 2k500 5k

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Loudspeaker THD+N

vs vs

Frequency AVDD = 5V, SE, 0dB Frequency AVDD = 3.3V, POUT = 400mW

POUT = 10mW, 32Ω15μH+8Ω+15μH

Figure 121. Figure 122.

Loudspeaker THD+N Earpiece THD+N

vs vs

Frequency AVDD = 5V, POUT = 400mW Output Power AVDD = 3.3V, 0dB AUX

15μH+8Ω+15μH fOUT = 1kHz, 16Ω

Figure 123. Figure 124.

Earpiece THD+N Earpiece THD+N

vs vs

Output Power AVDD = 5V, 0dB AUX Output Power AVDD = 3.3V, 0dB AUX

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 125. Figure 126.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT POWER (W)

1m 20m 200m2m 50m 500m5m

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Earpiece THD+N Earpiece THD+N

vs vs

Output Power AVDD = 5V, 0dB AUX Output Power AVDD = 3.3V, 0dB CPI

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 127. Figure 128.

Earpiece THD+N Earpiece THD+N

vs vs

Output Power AVDD = 5V, 0dB CPI Output Power AVDD = 3.3V, 0dB CPI

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 129. Figure 130.

Earpiece THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, 0dB CPI Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 131. Figure 132.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 0dB DAC Output Power AVDD = 3.3V, OCL 1.2V, 0dB DAC

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 133. Figure 134.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 0dB DAC Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 135. Figure 136.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 12dB DAC Output Power AVDD = 3.3V, OCL 1.2V, 12dB DAC

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 137. Figure 138.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 12dB DAC Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 139. Figure 140.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 0dB DAC Output Power AVDD = 3.3V, OCL 1.5V, 0dB DAC

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 141. Figure 142.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 0dB DAC Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 143. Figure 144.

Product Folder Links: LM49370

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 12dB DAC Output Power AVDD = 3.3V, OCL 1.5V, 12dB DAC

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 145. Figure 146.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 12dB DAC Output Power AVDD = 3.3V, SE, 0dB DAC

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 147. Figure 148.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 0dB DAC Output Power AVDD = 3.3V, SE, 0dB DAC

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 149. Figure 150.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 0dB DAC Output Power AVDD = 3.3V, SE, 12dB DAC

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 151. Figure 152.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 12dB DAC Output Power AVDD = 3.3V, SE, 12dB DAC

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 153. Figure 154.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 12dB DAC Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 155. Figure 156.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX Output Power AVDD = 5V, OCL 1.2V, 0dB AUX

fOUT = 1kHz, 16ΩfOUT = 1kHz, 16Ω

Figure 157. Figure 158.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 12dB AUX Output Power AVDD = 3.3V, OCL 1.2V, 0dB AUX

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 159. Figure 160.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 3.3V, OCL 1.2V, 12dB AUX Output Power AVDD = 5V, OCL 1.2V, 0dB AUX

fOUT = 1kHz, 32ΩfOUT = 1kHz, 32Ω

Figure 161. Figure 162.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 12dB AUX Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 163. Figure 164.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 0dB CPI Output Power AVDD = 3.3V, OCL 1.2V, 0dB CPI

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 165. Figure 166.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.2V, 0dB CPI Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 167. Figure 168.

Product Folder Links: LM49370

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX Output Power AVDD = 5V, OCL 1.5V, 0dB AUX

fOUT = 1kHz, 16ΩfOUT = 1kHz, 16Ω

Figure 169. Figure 170.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 12dB AUX Output Power AVDD = 3.3V, OCL 1.5V, 0dB AUX

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 171. Figure 172.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 3.3V, OCL 1.5V, 12dB AUX Output Power AVDD = 5V, OCL 1.5V, 0dB AUX

fOUT = 1kHz, 32ΩfOUT = 1kHz, 32Ω

Figure 173. Figure 174.

Product Folder Links: LM49370

OUTPUT POWER (W)

0.01

0.02

0.05

0.1

THD + N (%)

2m 10m 50m 100m5m 20m

0.2

0.5

0.001

0.002

0.005

OUTPUT POWER (W)

0.01

0.02

0.05

0.1

THD + N (%)

2m 10m 50m 100m5m 20m

0.2

0.5

0.001

0.002

0.005

OUTPUT POWER (W)

0.01

0.02

0.05

0.1

THD + N (%)

2m 10m 50m 100m5m 20m

0.2

0.5

0.001

0.002

0.005

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 12dB AUX Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 175. Figure 176.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 0dB CPI Output Power AVDD = 3.3V, OCL 1.5V, 0dB CPI

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 177. Figure 178.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, OCL 1.5V, 0dB CPI Output Power AVDD = 3.3V, SE, 0dB AUX

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 179. Figure 180.

Product Folder Links: LM49370

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

0.01

0.02

0.05

0.1

THD + N (%)

2m 10m 50m 100m5m 20m

0.2

0.5

0.001

0.002

0.005

10m 100m

OUTPUT POWER (W)

0.001

0.01

0.1

THD+N (%)

1m 20m2m 50m5m

0.002

0.02

0.2

0.005

0.05

0.5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 0dB AUX Output Power AVDD = 3.3V, SE, 0dB AUX

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 181. Figure 182.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 0dB AUX Output Power AVDD = 3.3V, SE, 0dB CPI

fOUT = 1kHz, 32ΩfOUT = 1kHz, 16Ω

Figure 183. Figure 184.

Headphone THD+N Headphone THD+N

vs vs

Output Power AVDD = 5V, SE, 0dB CPI Output Power AVDD = 3.3V, SE, 0dB CPI

fOUT = 1kHz, 16ΩfOUT = 1kHz, 32Ω

Figure 185. Figure 186.

Product Folder Links: LM49370

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

50m1m 2m 5m 10m 20m 100m200m

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone THD+N Loudspeaker THD+N

vs vs

Output Power AVDD = 5V, SE, 0dB CPI Output Power AVDD = 3.3V, 0dB AUX

fOUT = 1kHz, 32ΩfOUT = 1kHz, 15μH+8Ω+15μH

Figure 187. Figure 188.

Loudspeaker THD+N Loudspeaker THD+N

vs vs

Output Power AVDD = 4.2V, 0dB AUX Output Power AVDD = 5V, 0dB AUX

fOUT = 1kHz, 15μH+8Ω+15μH fOUT = 1kHz, 15μH+8Ω+15μH

Figure 189. Figure 190.

Loudspeaker THD+N Loudspeaker THD+N

vs vs

Output Power AVDD = 3.3V, 0dB CPI Output Power AVDD = 4.2V, 0dB CPI

fOUT = 1kHz, 15μH+8Ω+15μH fOUT = 1kHz, 15μH+8Ω+15μH

Figure 191. Figure 192.

Product Folder Links: LM49370

1m 10m 100m 500m 3

OUTPUT VOLTAGE (VRMS)

21200m2m 20m5m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

1m 10m 100m 500m 3

OUTPUT VOLTAGE (VRMS)

21200m2m 20m5m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT POWER (W)

500m10m 20m 50m 100m 200m 1 2

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Loudspeaker THD+N Loudspeaker THD+N

vs vs

Output Power AVDD = 5V, 0dB CPI Output Power AVDD = 3.3V, 0dB DAC

fOUT = 1kHz, 15μH+8Ω+15μH fOUT = 1kHz, 15μH+8Ω+15μH

Figure 193. Figure 194.

Loudspeaker THD+N Loudspeaker THD+N

vs vs

Output Power AVDD = 4.2V, 0dB DAC Output Power AVDD = 5V, 0dB DAC

fOUT = 1kHz, 15μH+8Ω+15μH fOUT = 1kHz, 15μH+8Ω+15μH

Figure 195. Figure 196.

AUXOUT THD+N AUXOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 0dB AUX Output Voltage AVDD = 5V, 0dB AUX

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 197. Figure 198.

Product Folder Links: LM49370

100m 500m 3

OUTPUT VOLTAGE (VRMS)

200m

20m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

100m 500m 4

OUTPUT VOLTAGE (VRMS)

200m

20m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

10m 100m 500m 3

OUTPUT VOLTAGE (VRMS)

200m

6m 20m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

10m 100m 500m 4

OUTPUT VOLTAGE (VRMS)

200m

6m 20m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

1m 10m 100m 500m 3

OUTPUT VOLTAGE (VRMS)

21200m2m 20m5m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

1m 10m 100m 500m 4

OUTPUT VOLTAGE (VRMS)

21200m2m 20m5m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

AUXOUT THD+N AUXOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 0dB CPI Output Voltage AVDD = 5V, 0dB CPI

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 199. Figure 200.

AUXOUT THD+N AUXOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 0dB DAC Output Voltage AVDD = 5V, 0dB DAC

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 201. Figure 202.

AUXOUT THD+N AUXOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 12dB DAC Output Voltage AVDD = 5V, 12dB DAC

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 203. Figure 204.

Product Folder Links: LM49370

1m 10m 100m 1

OUTPUT VOLTAGE (VRMS)

0.001

0.01

0.1

THD+N (%)

2m 5m 20m

50m 24200m

500m

0.002

0.02

0.2

0.005

0.05

0.5

1m 10m 100m 1

OUTPUT VOLTAGE (VRMS)

0.001

0.01

0.1

THD+N (%)

2m 5m 20m

50m 24200m

500m

0.002

0.02

0.2

0.005

0.05

0.5

100m 500m 3

OUTPUT VOLTAGE (VRMS)

200m

20m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m 100m 1

OUTPUT VOLTAGE (VRMS)

6m 20m 200m50m 500m

1m 10m 100m 500m 3

OUTPUT VOLTAGE (VRMS)

21200m2m 20m5m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

1m 10m 100m 500m 3

OUTPUT VOLTAGE (VRMS)

21200m2m 20m5m 50m

0.001

0.01

0.1

THD + N (%)

0.2

0.5

0.002

0.005

0.02

0.05

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

CPOUT THD+N CPOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 0dB AUX Output Voltage AVDD = 5V, 0dB AUX

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 205. Figure 206.

CPOUT THD+N CPOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 0dB DAC Output Voltage AVDD = 5V, 0dB DAC

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 207. Figure 208.

CPOUT THD+N CPOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 6dB MIC Output Voltage AVDD = 5V, 6dB MIC

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 209. Figure 210.

Product Folder Links: LM49370

20 20k

FREQUENCY (Hz)

-100

CROSSTALK (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

20 20k

FREQUENCY (Hz)

-100

CROSSTALK (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m

OUTPUT VOLTAGE (VRMS)

20m 50m100m 200m500m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

10m

OUTPUT VOLTAGE (VRMS)

20m 50m100m 200m500m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT VOLTAGE (VRMS)

320m 50m 100m 200m 500m 1 2

0.001

0.01

0.1

THD+N (%)

0.002

0.02

0.2

0.005

0.05

0.5

OUTPUT VOLTAGE (VRMS)

420m 50m 100m 200m 500m 1 2

LM49370

www.ti.com

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

CPOUT THD+N CPOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 12dB DAC Output Voltage AVDD = 5V, 12dB DAC

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 211. Figure 212.

CPOUT THD+N CPOUT THD+N

vs vs

Output Voltage AVDD = 3.3V, 36dB MIC Output Voltage AVDD = 5V, 36dB MIC

fOUT = 1kHz, 5kΩfOUT = 1kHz, 5kΩ

Figure 213. Figure 214.

Headphone Crosstalk Headphone Crosstalk

vs vs

Frequency Frequency

OCL 1.2V, 0dB AUX, 32ΩOCL 1.5V, 0dB AUX, 32Ω

Figure 215. Figure 216.

Product Folder Links: LM49370

20 20k

FREQUENCY (Hz)

-100

CROSSTALK (dB)

10k1k 2k 5k50 100 200 500

-90

-80

-70

-60

-50

-40

-30

-20

-10

-95

-85

-75

-65

-55

-45

-35

-25

-15

-5

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

www.ti.com

Typical Performance Characteristics (continued)

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage

applied to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Headphone Crosstalk

Frequency

SE, 0dB AUX, 32Ω

Figure 217.

Product Folder Links: LM49370

LS_VDD

EXT_MIC_BIAS

INT_MIC_BIAS

INT_MIC_POS

INT_MIC_NEG

VDD

MIC_DET

EXT_MIC

A_VDD

LS_VDD

EXT_MIC_BIAS

INT_MIC_BIAS

INT_MIC_POS

INT_MIC_NEG

VDD

MIC_DET

EXT_MIC

A_VDD

LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

APPLICATION NOTE

MICROPHONE BIAS CONFIGURATIONS

Schematic Considerations for MEMs Microphones

The internal microphone bias of the LM49370 is provided through a two stage amplifier. Adding a capacitor larger

than 100pF directly to this pin can cause instability. In many cases, when using MEMs microphones, a larger

bypass capacitor is required on the INT_MIC_BIAS pin. To avoid oscillations and to keep the device stable, it is

recommended to add a resistor (RB) greater than 10Ωin series with the capacitor (CB). Another option is to bias

the MEMs microphone from the 1.8V supply used for D_VDD/IO_VDD.

Figure 218. Schematic for MEMs Microphones

Schematic Considerations for ECM Microphones

When using ECM microphones, refer to the configurations shown in Figure 219 to bias the microphones.

Figure 219. Schematic Option for ECM Microphones

PCB LAYOUT CONSIDERATIONS

A_VDD and LS_VDD

Due to internal ESD diodes structure, for best performance, in the PCB board A_VDD and LS_VDD need to be tied

to the same plane, but requires separate bypassing capacitors for each supply rail.

Microphone Inputs

When routing the differential microphone inputs the electrical length of the two traces should be well matched.

The differential input pair can be routed in parallel on the same plane or the traces can overlap on two adjacent

planes. It is important to surround these traces with a ground plane or trace to isolate the microphone inputs from

the noise coupling from the class D amplifier.

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LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Class D Loudspeaker

To minimize trace resistance and therefore maintain the highest possible output power, the power (LS_VDD) and

class D output (LS-, LS+) traces should be as wide as possible. It is also essential to keep these same traces as

short and well shielded as possible to decrease the amount of EMI radiation.

Capacitors

All supply bypass capacitors (for A_VDD, D_VDD. I/O VDD, and LS_VDD), and charge pump capacitors should be

as close to the device as possible. Careful consideration should be taken with the ground connection of the

analog supply (A_VDD) bypass cap, for proper performance it should be referenced to a low noise ground plane.

The charge pump capacitors and traces connecting the capacitor to the device should be kept away from the

input and output traces to avoid noise coupling issues.

LM49370 Demonstration Board Schematic Diagram

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LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Demoboard PCB Layout

Figure 220. Top Silkscreen

Figure 221. Top Layer

Product Folder Links: LM49370

LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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Figure 222. Mid Layer 1

Figure 223. Mid Layer 2

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LM49370

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SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

Figure 224. Bottom Layer

Figure 225. Bottom Silkscreen

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LM49370

SNAS356D –FEBRUARY 2007–REVISED MARCH 2012

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REVISION HISTORY

Rev Date Description

1.0 02/14/07 Initial release.

1.01 01/08/08 Fixed a typo on X3 value (Physical Dimension section) in the last page.

1.02 02/11/08 Text edits.

1.03 03/31/11 Input edits and added the section ”PLL LOOP FILTER”.

1.04 05/26/11 Added the Application Note section.

Edited (tweak) Figures 16 and 17 (schematics for MEM and ECM

microphones) respectively. Also added the paragraph “In non-OCL

1.05 06/02/11 mode, two 1kohm resistors are optional....... (under Figure 9, Connection

of Headset.... )

1.06 03/09/12 Replaced curve 20191721 (stereo DAC crosstalk, 32Ω) with 201917k5

Product Folder Links: LM49370

PACKAGE OPTION ADDENDUM

www.ti.com 26-Jun-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM49370RL/NOPB LIFEBUY DSBGA YPG 49 250 Green (RoHS

& no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GI3

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM49370RL/NOPB DSBGA YPG 49 250 178.0 12.4 4.19 4.19 0.76 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM49370RL/NOPB DSBGA YPG 49 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 2

MECHANICAL DATA

YPG0049xxx

www.ti.com

RLA49XXX (Rev B)

0.650±0.075 D

4214898/A 12/12

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

D: Max =

E: Max =

3.94 mm, Min =

3.88 mm

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