1
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
NOVEMBER 2004
2004 Integrated Device Technology, Inc. DSC 6195/27c
IDT5T940
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• 3-level inputs for feedback divide ratio and output frequency range
selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT
• Regenerated input clock or QOUT/4 on QREG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Three modes of output frequency range
- Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version
of the input clock.
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version
of the input clock frequency.
• Selectable loop bandwidths
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
DESCRIPTION:
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
The three modes of output frequency range are controlled by the SELmode,
which is a 3-level pin. When SELmode is high or low, the QOUT is a multiplied
version of the input clock while QREG is a regenerated version of the input clock.
When SELmode is mid, the QOUT is a multiplied version of the input clock while
QREG is QOUT/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
• Terabit routers
• Gigabit ethernet systems
• SONET / SDH systems
• Digital cross connects
• Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
PLL
CONTROL
LOGIC
LOCK,
FREQ.
DETECTOR
CLKIN
REFIN
LOCK
DIVN
DIVM
QREG
QOUT
CLK/
REF0
SELMODE
PD
PLLBW1PLLBW0
INPUT
MUX
CLKIN
REFIN
CLK/
REF1
QREG
QOUT
2
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max Unit
VDD Power Supply Voltage –0.5 to +4.1 V
VIInput Voltage –0.5 to +4.1 V
VOOutput Voltage –0.5 to VDD+0.5 V
TJJunction Temperature 1 5 0 °C
TSTG Storage Temperature –65 to +165 °C
NOTE:
1. Capacitance applies to all inputs except CLK/REF[1:0] and SELmode.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description Typ. Max. Unit
CIN Input Capacitance 2.5 3 pF
COUT Output Capacitance — — pF
VFQFPN
TOP VIEW
GND
CLKIN
CLKIN
GND
REFIN
REFIN
GND
VDD
GND
QREG
QREG
LOCK
GND
VDD
V
DD
CLK/REF
1
CLK/REF
0
SEL
MODE
V
DD
PLLBW
0
PLLBW
1
PD
V
DD
GND
Q
OUT
Q
OUT
GND
V
DD
1
2
3
4
5
6
7
21
20
19
18
17
16
15
8 9 10 11 12 13 14
28 27 26 25 24 23 22
GND
Symbol Description Min. Typ. Max. Unit
TAAmbient Operating Temperature –40 +25 +85 °C
VDD Power Supply Voltage 2.375 — 3.465 V
VTTermination Voltage (LVPECL) — VDD – 2 — V
Termination Voltage (LVDS) — 1.2 —
RECOMMENDED OPERATING RANGE
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INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INPUT FREQUENCY RANGE
CLK/REF[1:0] Input Frequency Range
HH 19.4MHz - 20.9MHz
HM reserved
HL 38.8MHz - 41.7MHz
MH 77.7MHz - 83.4MHz
MM Automatic Detection
ML 155.5MHz - 167MHz
L H 311MHz - 334MHz
LM reserved
LL 622MHz - 667MHz
PLL BANDWIDTH SELECTION
PLLBW[1:0] Min. Max. Min. CLKIN/REFIN
LL 65KHz 120KHz 19.44MHz
LH 250KHz 500KHz 19.44MHz
HL 1MHz 2MHz 38.88MHz
HH 4MHz 8MHz 155.52MHz
OUTPUT FREQUENCY RANGE
SELmode QOUT/QOUT QREG/QREG Unit
L 155.5 - 166.6 regenerated CLKIN/CLKIN MHz
M 622 - 666.5 155.5 - 166.6 MHz
H 622 - 666.5 regenerated CLKIN/CLKIN MHz
PIN DESCRIPTION
Pin Name I/O Type Description
CLKIN, CLKIN I Adjustable(1) Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float
to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected
on the floating input.
REFIN, REFIN I Adjustable(1) Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential
or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL
threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the
floating input.
CLK/REF[1:0] I 3-level(2) 3 level inputs controlling PLL feedback divider ratio. Automatic detection is used if both inputs are MID.
SELmode I 3-level(2) 3 level input to select output frequency range for QOUT/QOUT and QREG/QREG (see Output Frequency Range table)
PLLBW[1:0] I LVTTL PLL Bandwidth Select Inputs (see PLL Bandwidth Selection table)
PD I LVTTL Power Down Control. Shuts off entire chip when LOW.
QOUT, QOUT 0 Adjustable(3) Differential clock output. LVPECL or LVDS outputs.
QREG, QREG 0 Adjustable(3) Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs.
LOCK 0 LVTTL LOW when PLL is locked to CLKIN, HIGH in all other conditions
VDD PWR Power Supply
GND PWR Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2 . 3-level inputs are static inputs and must be tied to VDD or GND or left floating.
3. Outputs can be LVPECL or LVDS.
LOCK FREQUENCY DETECTOR
The 5T940 will lock to, and track, a valid CLKIN signal; LOCK will be low
when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK. When a valid input is then applied to CLKIN, the 5T940 will smoothly
switch back to locking on CLKIN, and LOCK will go low. LOCK will also switch
to high should the frequency of CLKIN drift close to the limits of the VCO tuning
range.
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INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
CLOCK INPUT/OUTPUT CONFIGURA TION DESCRIPTION
Application REFIN (MHz) CKIN (MHz) SELmode QREG (MHz) QOUT (MHz)
Non-FEC 19.44, 38.88, 77.76, 155.52, 311.04, 19.44 LOW 19.44 155.52
622.08 MID 155.52 622.08
HIGH 19.44 622.08
38.88 LOW 38.88 155.52
MID 155.52 622.08
HIGH 38.88 622.08
77.76 LOW 77.76 155.52
MID 155.52 622.08
HIGH 77.76 622.08
155.52 LOW 155.52 155.52
MID 155.52 622.08
HIGH 155.52 622.08
311.04 LOW 311.04 155.52
MID 155.52 622.08
HIGH 311.04 622.08
622.08 LOW 622.08 155.52
MID 155.52 622.08
HIGH 622.08 622.08
FEC 20.83, 41.66, 83.31, 166.63, 333.26, 20.83 LOW 20.83 166.63
666.52 MID 166.63 666.52
HIGH 20.83 666.52
41.66 LOW 41.66 166.63
MID 166.63 666.52
HIGH 41.66 666.52
83.31 LOW 83.31 166.63
MID 166.63 666.52
HIGH 83.31 666.52
166.63 LOW 166.63 166.63
MID 166.63 666.52
HIGH 166.63 666.52
333.26 LOW 333.26 166.63
MID 166.63 666.52
HIGH 333.26 666.52
666.52 LOW 666.52 166.63
MID 166.63 666.52
HIGH 666.52 666.52
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INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
CLOCK INPUT/OUTPUT CONFIGURA TION DESCRIPTION (CONTINUED)
Application REFIN (MHz) CKIN (MHz) SEL mode QREG (MHz) QOUT (MHz)
10GE copper 19.53, 39.06, 78.12, 156.25, 312.5, 19.53 LOW 19.53 156.25
625 MID 156.25 625
HIGH 19.53 625
39.06 LOW 39.06 156.25
MID 156.25 625
HIGH 39.06 625
78.12 LOW 78.12 156.25
MID 156.25 625
HIGH 78.12 625
156.25 LOW 156.25 156.25
MID 156.25 625
HIGH 156.25 625
312.5 LOW 312.50 156.25
MID 156.25 625
HIGH 312.5 625
625 LOW 625 156.25
MID 156.25 625
HIGH 625 625
10GE optical 20.14, 40.28, 80.56, 161.13, 322.26, 20.14 LOW 20.14 161.13
644.53 MID 161.13 644.53
HIGH 20.14 644.53
40.28 LOW 40.28 161.13
MID 161.13 644.53
HIGH 40.28 644.53
80.56 LOW 80.56 161.13
MID 161.13 644.53
HIGH 80.56 644.53
161.13 LOW 161.13 161.13
MID 161.13 644.53
HIGH 161.13 644.53
322.26 LOW 322.26 161.13
MID 161.13 644.53
HIGH 322.26 644.53
644.53 LOW 644.53 161.13
MID 161.13 644.53
HIGH 644.53 644.53
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INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL
Symbol Parameter Test Conditions Min. Typ. Max Unit
IIH Input HIGH Current VDD = 3.465V — — ±1 µA
IIL Input LOW Current VDD = 3.465V — — ±1
VIK Clamp Diode Voltage VDD = 2.375V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 — +3.465 V
VIH DC Input HIGH 1.7 — — V
VIL DC Input LOW — — 0 .7 V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVPECL(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Input Characteristics
IIN Input Current (CLKIN, REFIN) VDD = 3.465V -20 —+20 µA
VCMR Common Mode Input Voltage 1 —VDD - 0.3 V
VDIF Differential Voltage Required to Toggle Input 100 ——mV
Output Characteristics
VOH Output Voltage HIGH (terminated through 50Ω tied to VDD - 2V)(2) VDD - 1.15 —VDD - 0.9 V
VOL Output Voltage LOW (terminated through 50Ω tied to VDD - 2V)(2) VDD - 1.95 —VDD - 1.61 V
VSWING Peak-to-Peak Output Voltage Swing 0.55 —0.93 V
NOTES:
1. VDD = 2.375 - 3.645V.
2. Not to exceed VDD - 0.05V.
POWER SUPPLY CHARACTERISTICS(1,2)
Symbol Parameter Test Conditions Typ. Max Unit
IDD_PD Power Supply Current VDD = Max., PD = GND, All outputs unloaded —50 µA
∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 2.375V —100 µA
(LVTTL inputs only)
ITOT Total Power Supply Current VDD = Max., QOUT = 622MHz, All outputs unloaded —200 mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. As a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasonable operating temperature. That means that
these parts must not burn up under extended use in a typical application.
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional tAQ time before all datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Test Conditions Min. Max Unit
VIHH Input HIGH Voltage Level(1) 3-Level Inputs Only VDD – 0.4 — V
VIMM Input MID Voltage Level(1) 3-Level Inputs Only VDD/2 – 0.2 VDD/2 + 0.2 V
VILL Input LOW Voltage Level(1) 3-Level Inputs Only — 0. 4 V
VIN = VDD HIGH Level — 200
I33-Level Input DC Current VIN = VDD/2 MID Level –50 +50 µA
VIN = GND LOW Level –200 —
7
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INPUT TIMING REQUIREMENTS
Symbol Parameter Min. Typ. Max. Unit
REFHInput Reference Clock Duty Cycle 4 0 50 60 %
FREF Input Reference Clock Range 19.44 —666.52 MHz
REFTOL Input Reference Clock Frequency Tolerance -100 —100 ppm
FCLKIN Clock in Frequency Range 19.44 —666.52 MHz
CLKINHClock in Duty Cycle 40 50 60 %
tAQ Acquisition Time from Return of Valid CLKIN —60 150 us
LOCKTOL Frequency Tolerance for LOCK -600 ±450 600 ppm
tJIT(TOL) Tolerance to Input Jitter GR-253 Sect. 5.6.2.2
Symbol Parameter Min. Typ. Max. Unit
SELmode = LOW 155.52 —166.63
QOUT Multiplied Clock Output Frequency SELmode = MID 155.52 —666.52 MHz
SELmode = HIGH 622.08 —666.52
QREG Regenerated Clock Output Frequency 19.44 —666.52 MHz
CLKIN Input Clock Frequency 19.44 —667 MHz
tROutput Rise Time LVPECL —150 —ps
LVDS —100 —
tFOutput Fall Time LVPECL —150 —ps
LVDS —100 —
tSK Skew between QOUT and QREG —10 20 ps
PLLBW PLL Bandwidth Setting 65 80 120 KHz
tPJitter Transfer Peaking ——0.1 dB
tJJitter Generation(1) Output Frequency = 622MHz - 666.5MHz — 0. 3 0.65 ps (RMS)
(with 50KHz to 80MHz band pass filter) Output Frequency = 155.5MHz - 166.6MHz — 1 2
tDUTY Output Duty Cycle 45 —55 %
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-192)
NOTE:
1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVDS
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Input Characteristics
IIN Input Current (CLKIN, REFIN) VDD = 3.465V -20 —+20 µA
VCM Common Mode Input Voltage Range(1) 0.9 —VDD - 0.05 V
VDIF Differential Voltage Required to Toggle Input 100 ——mV
Output Characteristics
VOT(+) Differential Output Voltage for the TRUE Binary State 247 —454 mV
VOT(-) Differential Output Voltage for the FALSE Binary State -247 —-454 mV
∆VOT Change in VOT Between Complementary Output States ——50 mV
VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V
∆VOS Change in VOS Between Complementary Output States ——50 mV
IOS Outputs Short Circuit Current VOUT(+) and VOUT(-) = 0V —924mA
IOSD Differential Outputs Short Circuit Current VOUT(+) = VOUT(-) —612mA
NOTE:
1. Not to exceed VDD - 0.05V.
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INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
Symbol Parameter Min. Typ. Max. Unit
SELmode = LOW 155.52 —166.63
QOUT Multiplied Clock Output Frequency SELmode = MID 155.52 —666.52 MHz
SELmode = HIGH 622.08 —666.52
QREG Regenerated Clock Output Frequency 19.44 —666.52 MHz
CLKIN Input Clock Frequency 19.44 —667 MHz
tROutput Rise Time LVPECL —150 —ps
LVDS —100 —
tFOutput Fall Time LVPECL —150 —ps
LVDS —100 —
tSK Skew between QOUT and QREG —10 20 ps
PLLBW PLL Bandwidth Setting 65 80 120 KHz
250 305 500
tPJitter Transfer Peaking —0.05 0.1 dB
Output frequency = 622MHz - 666.5MHz —0.1 0.3
tJJitter Generation Output frequency = 155.5MHz - 166.6MHz —0.4 1.5 ps (RMS)
(with 12KHz to 20MHz filter)(1) Output frequency = 77.7MHz - 83.4MHz —0.5 1.7
tDUTY Output Duty Cycle 45 —55 %
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-48)
Symbol Parameter Min. Typ. Max. Unit
SELmode = LOW 155.52 —166.63
QOUT Multiplied Clock Output Frequency SELmode = MID 155.52 —666.52 MHz
SELmode = HIGH 622.08 —666.52
QREG Regenerated Clock Output Frequency 19.44 —666.52 MHz
CLKIN Input Clock Frequency 19.44 —667 MHz
tROutput Rise Time LVPECL —150 —ps
LVDS —100 —
tFOutput Fall Time LVPECL —150 —ps
LVDS —100 —
tSK Skew between QOUT and QREG —10 20 ps
65 80 120
PLLBW PLL Bandwidth Setting 250 305 500 KHz
1000 1250 2000
tPJitter Transfer Peaking —0.05 0.1 dB
Output frequency = 155.5MHz - 166.6MHz —0.3 1.1
tJJitter Generation Output frequency = 77.7MHz - 83.4MHz —0.4 1.3 ps (RMS)
(with 3KHz to 5MHz filter)(1) Output frequency = 19.4MHz - 20.9MHz —0.5 1.6
tDUTY Output Duty Cycle 45 —55 %
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-12)
NOTE:
1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table.
NOTE:
1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table.
9
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
LVDS
DRIVER
A
B
50ΩVT TEST POI N T
50Ω
VDIFF
LVPECL
DRIVER
A
50ΩVDD - 2V
50Ω
B
VDIFF
50Ω
50Ω
VDIFF VT
A
B
50Ω
50Ω
VDIFF VB
A
B
VB = VDD - 2V
TEST CONDITIONS
Test Circuit for LVDS Output Characteristics
Test Circuit for LVDS Input Characteristics
Test Circuit for LVPECL Output Characteristics
Test Circuit for LVPECL Input Characteristics
10
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
RECOMMENDED LANDING PATTERN
NL 28 pin
NOTE: All dimensions are in millimeters.
11
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
ORDERING INFORMATION
IDT XXXXX XX X
Package Process
Device Type
I
5T940-10
5T940-30
Precision Clock Generator - LVDS Output
Precision Clock Generator - LVPECL Output
Thermally Enhanced Plastic Very Fine
Pitch Quad Flat No Lead Package
VFQFPN - Green
NL
NLG
-40°C to +85°C (Industrial)
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
