Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to
obtain the latest version of relevant information to verify before placing orders.
Three-Terminal Low Current Positive Voltage Regulator
••
••
• 3-Ternimal Regulators
••
••
• Maximum Input Voltage : 30V
••
••
• Output Voltages of 5V,12V
••
••
• Output Current Up to 100mA
••
••
• No External Components
••
••
• Internal Thermal Overload Protection
••
••
• Internal Short-Circuit Limiting
••
••
• Output Voltage Offered in 4% tolerance
••
••
• SOP-8, SOT-89 and TO-92 Packages.
Features General Description
Pin Description
VIN
GND
VOUT
3
2
1
TO-92 (Top View)
This series of fixed-voltage monolithic integrated-cir-
cuit voltage regulators is designed for a wide range
of applications. These applications include on-card
regulation for elimination of noise and distribution
problems associated with single-point regulation. In
addition, they can be used with power-pass elements
to make high-current voltage regulators. Each of
these regulators can deliver up to 100mA of output
current. The internal limiting and ternal shutdown fea-
tures of these regulators make them essentially im-
mune to overload. When used as a replacement for
a Zener diode-resistor combination, an effective im-
provement in output impedance can be obtained to-
gether with lower-bias current.
SOP-8 (Top View)
1
2
3
45
6
7
8
VOUT
GND
GND
NC
GND
GND
NC
VIN
Applications
• Battery-Powered Circuitry
• Post Regulator for Switching Power Supply
Ordering and Marking Information
Package Code
E : T O -9 2 K : S OP -8 D : S O T -8 9
Temp. Range
C : 0 to 70 C
Handling Code
TU : Tube TR : Tape & Reel PB : Plastic Bag
TB : Tape & Box
Lead Free C ode
L : Lead Free D evice B lank : O riginal D evice
°
APL78L05/12 -
Handling Code
Temp. R ange
Package Code
APL78L05/12 D /K : APL78L05/12
XXXXX XXXXX - Date Code
APL
78L05/12
XXXXX XXXXX - Date CodeAPL78L05/12 E :
Lead Free C ode
VIN
GND
213
VOUT
SOT-89 (Front View)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw2
Symbol Parameter Rating Unit
VIN Input Voltage 30 VDC
TJ Operating Junction Temperature Range
Control Section
Pow er Transistor
0 to 125
0 to 150
°C
TSTG Storage Temperature Range -65 to +150 °C
θJA Thermal Resistance from Junction to Ambient in Free Air
SOP-8
SOT-89/TO-92
160
180
°C/W
Absolute Maximum Ratings
Electrical Characteristics
VIN=10V, IOUT=40mA, TJ=25°C, CIN=0.33µF, COUT=0.1µF, unless otherwise specified
APL78L05
Symbol Parameter Test Condition Min. Typ. Max. Unit
VOOutp ut Voltage 4.8 5.0 5.2 Vdc
1.0mA≤IOUT≤40mA
7.0Vdc≤VIN≤20Vdc
VOOutput Voltage (0° to +125°C) VIN=10V, 1.0mA≤IOUT≤40mA 4.75 5 5.25 Vdc
7.0Vdc≤VIN≤20Vdc 29 150
Regline Line Regulation 8.0Vdc≤VIN≤20Vdc 26 100 mV
1.0mA≤IOUT≤100mA 960
Regload Load Regulation 1.0mA≤IOUT≤40mA 530
mV
IBQu ies cen t C urr ent 2.8 6.0 m A
8.0Vdc≤VIN≤20Vdc 0.15 1.5
∆ IBQuiescent Current Change 1.0mA≤IOUT≤40mA 0.08 0.1 mA
VIN-VODropout Voltage IOUT=100mA 1.9 Vdc
APL78L12
Symbol Parameter Test Co ndition Min. Typ. Max. Unit
VOOutp ut Voltage 11 .5 12 12.5 Vdc
1.0mA≤IOUT≤40mA
14Vdc≤VIN≤27Vdc
VOOutput Voltage (0° to +125°C) VIN=1 9V, 1. 0mA≤IOUT≤40mA 11.4 12 12.6 Vdc
Regline Line Regulation 14.5Vdc≤VIN≤27Vdc 250 mV
1.0mA≤IOUT≤100mA 100
Regload Load Regulation 1.0mA≤IOUT≤40mA 50 mV
IBQuie s c e nt C urren t 6.5 mA
16Vdc≤VIN≤27Vdc 1.5
∆ IBQ uie s c e nt C urren t C ha n ge 1.0mA ≤IOUT≤40mA mA
VIN-VODropout Voltage IOUT=100mA 1.9 Vdc
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw3
Application Circuit
VOUT
APL78L05/12
COUT=
0.1µF
VIN
Cin=
0.33µF
Note1 : A common ground is required between the input and the output voltage. The input voltage must
remain typically 2V above the output voltage even during the low point on the input ripple voltage.
Note2 : Cin is required if regulator is located an appreciable distance from power supply filter.
Note3 : COUT is not needed for stability; however, it does improve transient response.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw4
2.2
2.4
2.6
2.8
3.0
0 25 50 75 100 125
0
1
2
3
4
5
6
7
8
0246810
APL78L05
APL78L05
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35
1
1.25
1.5
1.75
2
2.25
0255075100125
Typical Characteristics
Dropout Voltage vs. Junction Temperature
Dropout of Regulation is
defined as when
∆∆
∆∆
∆Vo=1% of Vo
IO=1mA
Quiescent Current vs. Ambient Temperature
Ambient Temperature (°C)
Quiescent Current (mA)
Quiescent Current (mA)
Quiescent Current vs. Input Voltage
Input Voltage (V)
Output Voltage vs. Input Voltage
Output Voltage (V)
Input Voltage (V)
IO=40mA
IO=100mA
Dropout Voltage (V)
Junction Temperature (°C)
IO=1mA
IO=40mA
IO=70mA
VIN=10V
IO=40mA No Load
APL78L05
APL78L05
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw5
1.6
1.65
1.7
1.75
1.8
1.85
1.9
020406080100
-80
+0
-70
-60
-50
-40
-30
-20
-10
10 100k
100 1k 10k
0
0.5
1
1.5
2
2.5
3
0 20406080100
Typical Characteristics (Cont.)
Dropout Voltage vs. Output Current
Load-Transient Response
Time (20µs/div)
Quiescent Current vs. Output Current
Quiescent Current (mA)
Output Current (mA)
Dropout Voltage (V)
Output Current (mA)
IOUT=
10mA~80mA
VOUT(100mv/div)
COUT=0.1µF
PSRR vs. Frequency
PSRR (dB)
Frequency (Hz)
VIN=10V
IOUT=10mA
APL78L05 APL78L05
APL78L05
APL78L05
VIN=10V
Dropout of
Regulation is
defined as when
∆∆
∆∆
∆Vo=1% of Vo
VOUT(100mv/div)
COUT=0.1uF
IOUT=10mA~80mA
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw6
0.01
0.1
1
10
020406080100
4.995
5
5.005
5.01
5.015
5.02
0 25 50 75 100 125
100
300
500
700
900
1100
1300
25 50 75 100 125 150
Typical Characteristics (Cont.)
Maximum Power Dissipation vs.
Ambient Temperature
TO-92 Type Package
No Heat Sink
Line Transient Response
VIN=9.5V~10.5V
COUT=0.1µF
IOUT=10mA
Time (100us/div)
VOUT=10(mV/div)
Maximum Power Dissipation (mW)
Ambient Temperature (°C)
APL78L05 APL78L05
Ambient Temperature (°C)
Output Voltage(V)
VIN=10V
IO=40mA
Output Voltage vs.
Ambient Temperature Region of Stable ESR vs.
Output Current
Output Current(mA)
COUTESR(Ω)
COUT=0.1uF
Stable Region
APL78L05 APL78L05
Untested
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw7
Typical Characteristics
Input
Constant
Current t o
Grounded
Load
R
APL78L05
lO
0.33µF
The APL78L05/12 Series of fixed voltage regulators
are designed with Thermal Overload Protection that
shuts down the circuit when subjected to an exces-
sive power overload condition. Internal Short Circuit
Protection limits the maximum current the circuit will
pass.
In many low current applications, compensation ca-
pacitors are not required. However, it is recom-
mended that the regulator input be bypassed with a
capacitor if the regulator is connected to the power
supply filter with long wire lengths, or if the output
load capacitance is large. The input bypass capaci-
tor should be selected to provide good high-frequency
characteristics to insure stable operation under all
load conditions. A 0.33µF or larger tantalum, mylar,
or other capacitor having low internal impedance at
high frequencies should be chosen. The bypass ca-
pacitor should be mounted with the shortest possible
leads directly across the regulators input terminals.
Good construction techniques should be used to mini-
mize ground loops and lead resistance drops since
the regulator has no external sense lead. Bypassing
the output is also recommended.
Figure 1. Current Regulator
MC1741
0.33µF
+20V
0.33µF
20V MPSU55
6.5 MPSA70
10K
10K
+VO
-VO
3
2
4
67
APL78L15
The APL78L00 regulators can also be used as a cur-
rent source when connected as above. In order to
minimize dissipation the APL78L05 is chosen in this
application. Resistor R determines the current as
follows :
IO = + IB
5.0V
R
IB =3.8mA over line and load changes
For example, a 100mA current source would require
R to be a 50Ω, 1/2W resistor and the output voltage
compliance would be the input voltage less 7V.
Figure 2. ±15V Tracking Voltage Regulator
Figure 3. Positive and Negative Regulator
+VI
0.1µF
APL78LXX
0.33µF
APL79LXX
0.33µF0.1µF
+VO
-VO
-VI
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw8
Packaging Information
Millimeters Inches
Dim Min. Max. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
H 5.80 6.20 0.228 0.244
L 0.40 1.27 0.016 0.050
e1 0.33 0.51 0.013 0.020
e2 1.27BSC 0.50BSC
φ 18
°8°
HE
e1 e2
0.015X45
D
A
A1
0.004max.
1
L
SOP-8 pin ( Reference JEDEC Registration MS-012)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw9
Package Information
b2
L1
QL2
A
b
L
SEATING PLANE
e1
e
J
E
S
D
1
2
3
S
Millimeters Inches
Dim Min. Max. Min. Max.
A 4.58 5.33 0.170 0.210
φ b 0.41 0.53 0.160 0.021
φ b2 0.41 0.48 0.160 0.019
φ D 4.96 5.20 0.175 0.205
E 3.94 4.19 0.125 0.165
e 2.42 2.66 0.095 0.105
e1 1.15 1.39 0.045 0.055
J 3.43 0.135
L 12.70 0.500
L1 1.27 0.050
L2 6.35 0.250
Q 2.93 0.115
S 2.42 2.66 0.080 0.105
TO-92
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw10
Package Information
SOT-89 (Reference EIAJ ED-7500A Reg stration SC-62)
D
D1
e
B1
e1
B
123
L
HE
C
a
a
A
Millimeters Inches
Dim Min. Max. Min. Max.
A 1.40 1.60 0.055 0.063
B 0.40 0.56 0.016 0.022
B1 0.35 0.48 0.014 0.019
C 0.35 0.44 0.014 0.017
D 4.40 4.60 0.173 0.181
D1 1.35 1.83 0.053 0.072
e 1.50 BSC 0.059 BSC
e1 3.00 BSC 0.118 BSC
E 2.29 2.60 0.090 0.102
H 3.75 4.25 0.148 0.167
L 0.80 1.20 0.031 0.047
α10°10°
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw11
t 2 5 C to Pea k
tp
Ramp-up
tL
Ramp-down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Physical Specifications
Terminal Material Solder-P lated C opp er (Solder Mate rial : 90/10 or 63/3 7 SnP b) , 100 %Sn
Lead Solde rability Mee ts EIA S pe c ification RSI86-91, ANSI/J- S T D-00 2 C atego r y 3.
Reflow Condition (IR/Convection or VPR Reflow)
Classificatin Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (T s min)
- Temperature Max (T smax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classificatioon Temperature (Tp) See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw12
T able 2. Pb-free Process – Pack age C lassification Reflow T em peratures
Packag e T hickness Vo lum e m m3
<350 V o lu me mm3
350-2000 V o lu me m m3
>2000
< 1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 m m – 2.5 m m 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 m m 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/s upplier shall a s s u r e p r o c e s s c o mp a t ib ility u p to a n d
including th e stated clas sification tem perature (th is mea ns Peak reflow tem pe rature +0°C.
For example 260°C+0°C) at the rated M SL level.
R e lia b il ity te st pr o g r am
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C , 5 SEC
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 °C
PCT JESD-22-B, A102 168 Hrs, 100 % RH , 121°C
TST MIL-STD-883D-1011.9 -65°C ~ 150°C , 200 Cyc les
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latc h-Up J E S D 78 10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
Ao
E
W
Po P
D1
D
F
P1
t
Ko
Bo
T able 1. SnP b Entectic Proces s – Pack age Pea k R eflow T emperatures
Pack age T h ickn ess Vo lume m m3
<350 Volume mm3
≥
≥≥
≥350
< 2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Classificatin Reflow Profiles(Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw13
Application A B C J T1 T2 W P E
330±162 ± 1.5 12.75 +
0.1 5 2 + 0.5 12.4 +0.2 2± 0.2 12 + 0.3
- 0.1 8± 0.1 1.75± 0.1
F D D1 Po P1 Ao Bo Ko t
SOP-8
5.5 ± 0.1 1.55±0.1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0.1 2.1± 0.1 0.3±0.013
(mm)
H3
H4 H
H1 W1W
H2H2A
H2H2
T2
T1
TF1F2
P1
PP2
D1
D
LL1
A0
D2
W2
M
A3
C0
C1
A2
A1
C2
B2 B1
T4
B0
T3
205
330
40
UNIT : mm
Box
Dimensions
A
J
B
T2
T1
C
Carrier Tape & Reel Dimensions(Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Oct., 2003
APL78L05/12
www.anpec.com.tw14
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Application A A1 A2 A3 B0 B1 B2 C0 C1
3.18~12 90±1 76±1 30±1 90±1 31±1 76±1 5.8 3.8
C2 H3 H4 L L1 P P1 P2 T
7.8 27.0 MAX 20.0 MAX 11.0 MAX 2.5 MIN 12.7±0.2 6.35±0.4 50.8±0.5 0.55 MAX
T1 T2 T3 T4 W W1 W2
TO-92
1.42 MAX 0.36~0.68 15 1.7 17.5~19 5.0~7.0 0.5 MAX
(mm)
Cover Tape Dimensions
Application Carrier Width Cov er Tap e W idth Devices Pe r Reel
SOP- 8 12 9.3 2500
TO-92 17.5~19 5.0~7.0 2000
Carrier Tape & Reel Dimensions(Cont.)
