06/02/08
Benefits
lImproved Gate, Avalanche and Dynamic
dv/dt Ruggedness
lFully Characterized Capacitance and
Avalanche SOA
lEnhanced body diode dV/dt and dI/dt
Capability
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IRFP4368PbF
Applications
l High Efficiency Synchronous Rectification in
SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
HEXFET® Power MOSFET
S
D
G
PD - 97322
GDS
Gate Drain Source
TO-247AC
S
D
G
D
V
DSS
75V
R
DS
(
on
)
typ. 1.46mΩ
max. 1.85mΩ
I
D (Silicon Limited)
350Ac
I
D (Package Limited)
195A
Absolute Maximum Ratings
Symbol Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited) A
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
I
DM
Pulsed Drain Current d
P
D
@T
C
= 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
dv/dt Peak Diode Recovery fV/ns
T
J
Operating Junction and °C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy emJ
I
AR
Avalanche Currentd A
E
AR
Repetitive Avalanche Energy gmJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
R
θJC
Junction-to-Case k––– 0.29
R
θCS
Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
R
θJA
Junction-to-Ambient jk ––– 40
430
See Fig. 14, 15, 22a, 22b
520
13
-55 to + 175
± 20
3.4
10lbxin (1.1Nxm)
300
Max.
350c
250c
1280
195
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. Refer to App Notes (AN-1140).
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.022mH
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value.
S
D
G
ISD ≤ 195A, di/dt ≤ 1740A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
Static @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage 75 ––– ––– V
∆V
(BR)DSS
/
∆T
J
Breakdown Voltage Temp. Coefficient ––– 0.077 ––– V/°C
R
DS(on)
Static Drain-to-Source On-Resistance ––– 1.46 1.85 mΩ
V
GS(th)
Gate Threshold Voltage 2.0 ––– 4.0 V
I
DSS
Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
I
GSS
Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 650 ––– ––– S
Q
g
Total Gate Charge ––– 380 570 nC
Q
gs
Gate-to-Source Charge ––– 79 –––
Q
gd
Gate-to-Drain ("Miller") Charge ––– 105 –––
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
)––– 275 –––
R
G(int)
Internal Gate Resistance
–––
0.80 –––
Ω
t
d(on)
Turn-On Delay Time ––– 43 ––– ns
t
r
Rise Time ––– 220 –––
t
d(off)
Turn-Off Delay Time ––– 170 –––
t
f
Fall Time ––– 260 –––
C
iss
Input Capacitance ––– 19230 ––– pF
C
oss
Output Capacitance ––– 1670 –––
C
rss
Reverse Transfer Capacitance ––– 770 –––
C
oss
eff. (ER) Effective Output Capacitance (Energy Related)
i
––– 1700 –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related)h––– 1410 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
I
S
Continuous Source Current ––– ––– 350cA
(Body Diode)
I
SM
Pulsed Source Current ––– ––– 1280
(Body Diode)di
V
SD
Diode Forward Voltage ––– ––– 1.3 V
t
rr
Reverse Recovery Time ––– 130 200 ns T
J
= 25°C V
R
= 64V,
––– 140 210 T
J
= 125°C I
F
= 195A
Q
rr
Reverse Recovery Charge ––– 450 680 nC T
J
= 25°C di/dt = 100A/µs g
––– 530 800 T
J
= 125°C
I
RRM
Reverse Recovery Current ––– 9.1 ––– A T
J
= 25°C
t
on
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
I
D
= 195A
R
G
= 2.7Ω
V
GS
= 10V g
V
DD
= 49V
I
D
= 195A, V
DS
=0V, V
GS
= 10V
T
J
= 25°C, I
S
= 195A, V
GS
= 0V g
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 5mAd
V
GS
= 10V, I
D
= 195A g
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 75V, V
GS
= 0V
V
DS
= 75V, V
GS
= 0V, T
J
= 125°C
MOSFET symbol
showing the
V
DS
= 38V
Conditions
V
GS
= 10V g
V
GS
= 0V
V
DS
= 50V
ƒ = 100kHz
V
GS
= 0V, V
DS
= 0V to 60V i
V
GS
= 0V, V
DS
= 0V to 60V h
Conditions
V
DS
= 50V, I
D
= 195A
I
D
= 195A
V
GS
= 20V
V
GS
= -20V
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
4.8V
BOTTOM 4.5V
1234567
VGS, Gate-to-Source Voltage (V)
1.0
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
1E+006
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 195A
VGS = 10V
0 50 100 150 200 250 300 350 400
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 60V
VDS= 38V
ID= 195A
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.4 0.8 1.2 1.6 2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
70
75
80
85
90
95
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5.0mA
1 10 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
50
100
150
200
250
300
350
ID, Drain Current (A)
Limited By Package
10 20 30 40 50 60 70 80
VDS, Drain-to-Source Voltage (V)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Energy (µJ)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
500
1000
1500
2000
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 33A
53A
BOTTOM 195A
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci i/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
0.0145 0.000024
0.0661 0.000148
0.1257 0.002766
0.0838 0.017517
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 195A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0200 400 600 800 1000
diF /dt (A/µs)
5
10
15
20
25
30
IRR (A)
IF = 72A
VR = 64V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
5
10
15
20
25
30
IRR (A)
IF = 108A
VR = 64V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
200
280
360
440
520
600
680
760
840
920
1000
QRR (A)
IF = 72A
VR = 64V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
200
280
360
440
520
600
680
760
840
920
1000
QRR (A)
IF = 108A
VR = 64V
TJ = 25°C
TJ = 125°C
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Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
1K
VCC
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/08
TO-247AC Part Marking Information
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-247AC package is not recommended for Surface Mount Application.
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