SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DHighest-Performance Floating-Point Digital
Signal Processor (DSP)
− Eight 32-Bit Instructions/Cycle
− 32/64-Bit Data Word
− 225-, 200-MHz (GDP), and 200-, 167-MHz
(PYP) Clock Rates
− 4.4-, 5-, 6-Instruction Cycle Times
− 1800/1350, 1600/1200, and 1336/1000
MIPS/MFLOPS
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
− Extended Temperature Devices Available
DAdvanced Very Long Instruction Word
(VLIW) TMS320C67x DSP Core
− Eight Independent Functional Units:
− Two ALUs (Fixed-Point)
− Four ALUs (Floating- and Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
DL1/L2 Memory Architecture
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
DDevice Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
Memory Space
DEnhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D16-Bit Host-Port Interface (HPI)
DTwo McASPs
− Two Independent Clock Zones Each
(1 TX and 1 RX)
− Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
− Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
− Data Formatter for Bit Manipulation
− Wide Variety of I2S and Similar Bit
Stream Formats
− Integrated Digital Audio Interface
Transmitter (DIT) Supports:
− S/PDIF, IEC60958-1, AES-3, CP-430
Formats
− Up to 16 transmit pins
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery
DTwo Inter-Integrated Circuit Bus (I2C Bus)
Multi-Master and Slave Interfaces
DTwo Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface
DTwo 32-Bit General-Purpose Timers
DDedicated GPIO Module With 16 pins
(External Interrupt Capable)
DFlexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
DIEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
D208-Pin PowerPAD Plastic (Low-Profile)
Quad Flatpack (PYP)
D272-BGA Packages (GDP)
D0.13-µm/6-Level Copper Metal Process
− CMOS Technology
D3.3-V I/Os, 1.2-V‡ Internal (GDP & PYP)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I2C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡These values are compatible with existing 1.26−V designs.
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