SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 D Highest-Performance Floating-Point Digital D D D D D Signal Processor (DSP) - Eight 32-Bit Instructions/Cycle - 32/64-Bit Data Word - 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates - 4.4-, 5-, 6-Instruction Cycle Times - 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS - Rich Peripheral Set, Optimized for Audio - Highly Optimized C/C++ Compiler - Extended Temperature Devices Available Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core - Eight Independent Functional Units: - Two ALUs (Fixed-Point) - Four ALUs (Floating- and Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Native Instructions for IEEE 754 - Single- and Double-Precision - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture - 4K-Byte L1P Program Cache (Direct-Mapped) - 4K-Byte L1D Data Cache (2-Way) - 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM Device Configuration - Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot - Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) - Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM - 512M-Byte Total Addressable External Memory Space D Enhanced Direct-Memory-Access (EDMA) D D D D D D D D D D D D Controller (16 Independent Channels) 16-Bit Host-Port Interface (HPI) Two McASPs - Two Independent Clock Zones Each (1 TX and 1 RX) - Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones - Each Clock Zone Includes: - Programmable Clock Generator - Programmable Frame Sync Generator - TDM Streams From 2-32 Time Slots - Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits - Data Formatter for Bit Manipulation - Wide Variety of I2S and Similar Bit Stream Formats - Integrated Digital Audio Interface Transmitter (DIT) Supports: - S/PDIF, IEC60958-1, AES-3, CP-430 Formats - Up to 16 transmit pins - Enhanced Channel Status/User Data - Extensive Error Checking and Recovery Two Inter-Integrated Circuit Bus (I2C Bus) Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports: - Serial-Peripheral-Interface (SPI) - High-Speed TDM Interface - AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) 272-BGA Packages (GDP) 0.13-m/6-Level Copper Metal Process - CMOS Technology 3.3-V I/Os, 1.2-V Internal (GDP & PYP) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x and PowerPAD are trademarks of Texas Instruments. I2C Bus is a trademark of Philips Electronics N.V. Corporation All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. These values are compatible with existing 1.26-V designs. Copyright 2005, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table of Contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 GDP 272-Ball BGA package (bottom view) . . . . . . . . . . . . . 5 PYP PowerPAD QFP package (top view) . . . . . . . . . . . . 10 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 functional block and CPU (DSP core) diagram . . . . . . . . . . 13 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 14 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 18 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 CPU CSR register description . . . . . . . . . . . . . . . . . . . . . . . . 68 interrupts and interrupt selector . . . . . . . . . . . . . . . . . . . . . . . 70 external interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 EDMA module and EDMA selector . . . . . . . . . . . . . . . . . . . . 73 PLL and PLL controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 multichannel audio serial port (McASP) peripherals . . . . . 83 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 89 power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 POST OFFICE BOX 1443 90 92 94 93 EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature . 94 96 96 97 97 98 parameter measurement information . . . . . . . . . . . . . . . 99 signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 timing parameters and board routing analysis . . . . . . 101 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 103 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . 106 synchronous-burst memory timing . . . . . . . . . . . . . . . . 109 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 111 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 121 multichannel audio serial port (McASP) timing . . . . . . 122 inter-integrated circuits (I2C) timing . . . . . . . . . . . . . . . 125 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . 127 multichannel buffered serial port timing . . . . . . . . . . . . 130 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 general-purpose input/output (GPIO) port timing . . . . 141 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS186J device-specific data sheet to make it an SPRS186K revision. It also highlights technical changes made to SPRS186K to generate SPRS186L; these changes are marked by "[Revision L]" in the Revision History table below. Removed device-specific information/data for TMS320C6713B from this document. For information/data on the TMS320C6713B device, see the TMS320C6713B Floating-Point Digital Signal Processor Data Manual SPRS294. Scope: Applicable updates to the C67x device family, specifically relating to the C6713 device, have been incorporated. This device is now at the Production Data (PD) stage of development. Updated information on McASP, McBSP and JTAG for clarification. Changed Pin Description for A12 and B11 (Revisions K and L). TI Recommends for new designs that the following pins be configured as such: D Pin A12 connected directly to CVDD (core power) D Pin B11 connected directly to Vss (ground) PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 6 Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) table: Updated Signal Name for Ball No. A12 Updated Signal Name for Ball No. B11 10 PYP PowerPAD QFP package (top view): Updated drawing 33 Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section: Removed "CE1 width 32-bit" from Functional Description for "00" in HD[4:3](BOOTMODE) Configuration Pin 37 Table 22 Peripheral Pin Selection Matrix: Updated/changed MCBSP0DIS (DEVCFG bit) from "ACLKKO" to "ACLKXO" 46 Configuration Example F (1 McBSP + HPI + 1 McASP) Updated from "McBSP1DIS = 1" to "McBSP1DIS = 0" 50 Terminal Functions, Host Port Interface section: Associated footnote with HD15/GP[15] pin 50 Terminal Functions, Host Port Interface section: Removed "CE1 width 32-bit" from Description for "00" in Bootmode HD[4:3] 55 Terminal Functions table, Timer 1 section: Updated Description for TINP1/AHCLKX0 Signal Name 57 Terminal Functions table, Reserved for Test section: Updated Description for RSV, 181 (PYP), A12 (GDP) Updated Description for RSV, 180 (PYP), B11 (GDP) 57 Terminal Functions, Reserved for Test section: Updated/changed Description for RSV Signal Name, A12 GDP (to "recommended") - [Revision L] Updated/changed Description for RSV Signal Name, B11 GDP (to "recommended") - [Revision L] 66 Device support, device and development-support tool nomenclature section: Updated figure for clarity 67 Device Support, document support section: Updated paragraphs for clarity POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PAGE(S) NO. 94 IEEE 1149.1 JTAG Compatibility Statement section: Updated/added paragraphs for clarity 97 Recommended Operating Conditions: Added VOS, Maximum voltage during overshoot row and associated footnote Added VUS, Maximum voltage during undershoot row and associated footnote 100 Parameter Measurement Information, AC transient rise/fall time specifications section: Added AC Transient Specification Rise Time figure Added AC Transient Specification Fall Time figure 122 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING: timing requirements for McASP section: Updated Parameter No. 3, tc(ACKRX), from "33" to "greater of 2P or 33 ns" and added associated footnote 122 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING: switching characteristics over recommended operating conditions for McASP section: Updated Parameter No. 11, tc(ACKRX), from "33" to "greater of 2P or 33 ns" and added associated footnote 123-124 4 ADDITIONS/CHANGES/DELETIONS MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section: Updated McASP Input and Output drawings 132 MULTICHANNEL BUFFERED SERIAL PORT TIMING, switching characteristics over recommended operating conditions for McBSP section: Updated McBSP Timings figure 144 Mechanical Data section: Added statement to the Packaging Information section POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 GDP 272-Ball BGA package (bottom view) > / 3 0 0 0 : 45 / 1 / : : / / ; 2 < / / / / / / / 1 2 / / < > / / < ; ? / / / / 3 / 1 < / / / / 2 / 3 / / : : ?: ?: ? / / / / ; / / / / / / / ; / / / 2 1 / / / 3 / / 3 / / / < 0 : 745 : : 74 5 / / / / / / / 1 2 7 7 : 7425 07 : / / / / / / / 0 / / 0: = 0 / / / / / / / @ : 745 / : / / / / / = ; A =: 4 5 = 7: 7 7: 74 5 0: 0 / / / =>: 0 ==? : : 745 : 745 07: 07 / / = : 7 45 = : 7 4 5 =:?: 7 45 : 7415 : = 07 / / / =: 7 425 / =: 7 45 0 : / 4 5 678 9 / / =: 07 = : 7 45 =: 7 415 / 45 6789 / 425 415: 67829: 67819: / 0 / =/ = / / / 0 / / / / / / / =: 7 / = : 7 4 5 / / / / / 1 / = 1: 4 15 = : 4 5 =3: 435 =: = 0 / =1: 45 =: ; / / / / / / / 2 / = 2: 4 25 / = : 4 5 =<: 4<5 =2: = 07 / / / / 0 / / 0 / / / / / = : 4 5 = : 4 5 / = : 45 / / 1 2 < 3 1 2 < 3 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 GDP 272-Ball BGA package (bottom view) (continued) Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) BALL NO. A1 SIGNAL NAME BALL NO. VSS VSS C1 GP[5](EXT_INT5)/AMUTEIN0 A2 C2 GP[4](EXT_INT4)/AMUTEIN1 A3 CLKIN C3 CVDD A4 CVDD RSV C4 CLKMODE0 A5 C5 PLLHV A6 TCK C6 A7 TDI C7 VSS CVDD A8 TDO C8 A9 CVDD CVDD C9 VSS VSS C10 DVDD A10 A11 C11 EMU4 A12 VSS RSV [connect directly to CVDD] C12 RSV A13 RESET C13 NMI A14 VSS HD13/GP[13] C14 HD14/GP[14] A15 C15 HD12/GP[12] A16 HD11/GP[11] C16 HD9/GP[9] A17 DVDD HD7/GP[3] C17 HD6/AHCLKR1 C18 CVDD VSS VSS C19 HD4/GP[0] C20 HD3/AMUTE1 VSS CVDD D1 DVDD D2 GP[6](EXT_INT6) D3 EMU2 B4 DVDD VSS D4 B5 RSV D5 VSS CVDD B6 TRST D6 CVDD B7 TMS D7 RSV B8 D8 B9 DVDD EMU1 D9 VSS EMU0 B10 EMU3 D10 CLKOUT3 B11 RSV [connect directly to VSS] D11 CVDD B12 EMU5 D12 RSV B13 DVDD HD15/GP[15] D13 D14 VSS CVDD VSS HD10/GP[10] D15 CVDD B16 D16 DVDD B17 HD8/GP[8] D17 B18 HD5/AHCLKX1 D18 VSS HD2/AFSX1 B19 CVDD VSS D19 DVDD D20 HD1/AXR1[7] A18 A19 A20 B1 B2 B3 B14 B15 B20 Shading denotes the GDP package pin functions that drop out on the PYP package. 6 SIGNAL NAME POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME E1 CLKS1/SCL1 J17 HOLD E2 VSS GP[7](EXT_INT7) J18 HOLDA J19 BUSREQ J20 HINT/GP[1] E17 VSS VSS K1 CVDD E18 HAS/ACLKX1 K2 E19 HDS1/AXR1[6] K3 VSS CLKS0/AHCLKR0 E20 E3 E4 HD0/AXR1[4] K4 CVDD F1 TOUT1/AXR0[4] K9 F2 TINP1/AHCLKX0 K10 VSS VSS F3 DVDD CVDD K12 VSS VSS CVDD HDS2/AXR1[5] K17 CVDD K18 ED0 K19 ED1 F20 VSS HCS/AXR1[2] K20 G1 TOUT0/AXR0[2] L1 VSS FSX1 G2 TINP0/AXR0[3] L2 DX1/AXR0[5] G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0 G4 L4 CVDD G17 VSS VSS L9 G18 HCNTL0/AXR1[3] L10 VSS VSS G19 HCNTL1/AXR1[1] L11 G20 F4 F17 F18 F19 K11 HR/W/AXR1[0] L12 VSS VSS H1 FSX0/AFSX0 L17 CVDD H2 DX0/AXR0[1] L18 ED2 H3 CLKR0/ACLKR0 L19 ED3 H4 VSS VSS L20 CVDD M1 CLKR1/AXR0[6] M2 DR1/SDA1 H19 DVDD HRDY/ACLKR1 M3 FSR1/AXR0[7] H20 HHWIL/AFSR1 M4 J1 DR0/AXR0[0] M9 VSS VSS J2 DVDD FSR0/AFSR0 M10 VSS VSS M12 M17 VSS VSS M18 DVDD J11 VSS VSS M19 ED4 J12 VSS M20 ED5 H17 H18 J3 J4 J9 J10 M11 VSS VSS Shading denotes the GDP package pin functions that drop out on the PYP package. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) BALL NO. SIGNAL NAME BALL NO. N1 SCL0 U9 N2 SDA0 U10 VSS CVDD N3 ED31 U11 CVDD N4 U12 DVDD N17 VSS VSS U13 N18 ED6 U14 VSS CVDD N19 ED7 U15 CVDD N20 ED8 U16 DVDD P1 ED28 U17 P2 ED29 U18 VSS EA21 P3 ED30 U19 BE1 P4 U20 P17 VSS VSS V1 VSS ED20 P18 ED9 V2 ED19 P19 VSS ED10 V3 CVDD V4 ED16 V5 BE3 R2 DVDD ED27 V6 CE3 R3 ED26 V7 EA3 R4 CVDD CVDD V8 EA5 V9 EA8 V10 EA10 R19 DVDD ED11 V11 ARE/SDCAS/SSADS R20 ED12 V12 AWE/SDWE/SSWE T1 ED24 V13 DVDD T2 ED25 V14 EA12 T3 DVDD VSS V15 DVDD V16 EA17 VSS ED13 V17 CE0 T18 V18 CVDD T19 ED15 V19 DVDD T20 ED14 V20 BE0 U1 ED22 W1 U2 ED21 W2 VSS CVDD U3 ED23 W3 DVDD U4 VSS DVDD W4 ED17 W5 W6 VSS CE2 U7 CVDD DVDD W7 EA4 U8 VSS W8 EA6 P20 R1 R17 R18 T4 T17 U5 U6 Shading denotes the GDP package pin functions that drop out on the PYP package. 8 SIGNAL NAME POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) BALL NO. W9 SIGNAL NAME BALL NO. SIGNAL NAME DVDD AOE/SDRAS/SSOE Y5 ARDY Y6 EA2 VSS DVDD Y7 DVDD W12 Y8 EA7 W13 EA11 Y9 EA9 W14 EA13 Y10 ECLKOUT W15 EA15 Y11 ECLKIN W16 VSS EA19 Y12 CLKOUT2/GP[2] W17 Y13 W18 CE1 Y14 VSS EA14 W19 CVDD VSS Y15 EA16 Y16 EA18 VSS VSS Y17 DVDD Y2 Y18 EA20 Y3 ED18 Y19 Y4 BE2 Y20 VSS VSS W10 W11 W20 Y1 Shading denotes the GDP package pin functions that drop out on the PYP package. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PYP PowerPAD QFP package (top view) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 HD4/GP[0] HD2/AFSX1 HD3/AMUTE1 HAS /ACLKX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] CV DD VSS HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/ W/AXR1[0] VSS DV DD HRDY/ACLKR1 HHWIL/AFSR1 HOLD HOLDA BUSREQ HINT/GP[1] VSS CV DD ED0 ED1 ED2 ED3 ED5 ED4 DV DD VSS CV DD ED8 ED7 ED6 ED10 ED9 ED12 ED11 CV DD VSS DV DD ED14 ED15 ED13 BE0 EA21 BE1 DV DD VSS CV DD PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) ( TOP VIEW ) CVDD VSS HD5/AHCLKX1 HD8/GP[8] HD6/AHCLKR1 DVDD VSS HD7/GP[3] HD9/GP[9] HD10/GP[10] HD11/GP[11] HD12/GP[12] CVDD VSS CVDD HD13/GP[13] HD14/GP[14] HD15/GP[15] NMI RESET CVDD RSV RSV RSV RSV VSS DVDD Exposed Thermal PAD 8,30 6,79 8,30 6,79 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CVDD CE1 CE0 EA20 EA19 EA17 DVDD VSS CVDD EA18 EA15 EA12 EA16 EA13 EA14 CVDD VSS DVDD EA11 VSS DVDD AWE/SDWE/SSWE CLKOUT2/GP[2] VSS CVDD ARE/SDCAS/SSADS ECLKIN ECLKOUT EA10 AOE/SDRAS/SSOE EA9 VSS DVDD EA8 EA7 EA6 EA5 CVDD VSS DVDD EA4 EA3 EA2 CE2 CVDD VSS DVDD CE3 ARDY DVDD VSS CVDD GP[4](EXT_INT4)/AMUTEIN1 GP[6](EXT_INT6) CV DD VSS DV DD GP[5](EXT_INT5)/AMUTEIN0 GP[7](EXT_INT7) CLKS1/SCL1 DV DD VSS CV DD TINP1/AHCLKX0 TOUT1/AXR0[4] CV DD VSS CLKX0/ACLKX0 TINP0/AXR0[3] TOUT0/AXR0[2] CLKR0/ACLKR0 DX0/AXR0[1] FSX0/AFSX0 CV DD VSS FSR0/AFSR0 DV DD VSS DR0/AXR0[0] CLKS0/AHCLKR0 CV DD VSS FSX1 DX1/AXR0[5] CLKX1/AMUTE0 VSS CV DD CLKR1/AXR0[6] DR1/SDA1 FSR1/AXR0[7] VSS CV DD SCL0 SDA0 CV DD DV DD VSS CV DD DV DD VSS VSS CV DD CV DD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CLKOUT3 EMU1 EMU0 TDO DVDD VSS CVDD TDI TMS TCK VSS CVDD CVDD TRST RSV VSS RSV CVDD PLLHV VSS CLKIN CLKMODE0 DVDD VSS CVDD 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 NOTE: All linear dimensions are in millimeters. This pad is electrically and thermally connected to the backside of the die. For the TMS320C6713 208-Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad is externally flush with the mold compound. 10 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 description The TMS320C67xt DSPs (including the TMS320C6713 device) compose the floating-point DSP generation in the TMS320C6000t DSP platform. The C6713 device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). The C6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM. The C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713 has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713 allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C6713 device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt kernel. TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments. Throughout the remainder of this document, the TMS320C6713 shall be referred to as C6713 or 13. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 device characteristics Table 2 provides an overview of the C6713 DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Figure 12. Table 2. Characteristics of the C6713 Processor Peripherals Not all peripheral pins are available at the same time. (For more details, see the Device Configurations section.) Peripheral performance is dependent on chip-level configuration. C6713 (FLOATING-POINT DSP) INTERNAL CLOCK SOURCE HARDWARE FEATURES GDP PYP 1 (32 bit) 1 (16 bit) EMIF SYSCLK3 or ECLKIN EDMA (16 Channels) CPU clock frequency 1 HPI (16 bit) SYSCLK2 1 McASPs AUXCLK, SYSCLK2 2 I2Cs SYSCLK2 2 McBSPs SYSCLK2 2 32-Bit Timers 1/2 of SYSCLK2 2 GPIO Module SYSCLK2 1 Size (Bytes) On-Chip Memory 264K 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified L2 Cache/Mapped RAM 192KB L2 Mapped RAM Organization CPU ID+CPU Rev ID Control Status Register (CSR.[31:16]) BSDL File For the C6713 BSDL file, contact your Field Sales Representative. Frequency MHz Cycle Time ns Clock Generator Options Process Technology 200, 167 4.4 ns (C6713GDP-225) 5 ns (C6713GDPA-200) 5 ns (C6713PYP-200) 6 ns (C6713PYPA-167) 1.2 V I/O (V) 3.3 V Prescaler Multiplier Postscaler /1, /2, /3, ..., /32 x4, x5, x6, ..., x25 /1, /2, /3, ..., /32 27 x 27 mm Packages 225, 200 1.20 V Core (V) Voltage 0x0203 272-Ball BGA (GDP) - - 208-Pin PowerPAD PQFP (PYP) 28 x 28 mm m 0.13 Product Status Product Preview (PP) PD PD Advance Information (AI) Production Data (PD) AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit. This value is compatible with existing 1.26-V designs. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. C67x is a trademark of Texas Instruments. 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 functional block and CPU (DSP core) diagram C6713 Digital Signal Processor 32 EMIF L1P Cache Direct Mapped 4K Bytes Total L2 Cache/ Memory 4 Banks 64K Bytes Total McASP1 C67x CPU (up to 4-Way) McASP0 Instruction Fetch Control Registers Instruction Dispatch McBSP1 Data Path A Pin Multiplexing McBSP0 I2C1 I2C0 Timer 1 Control Logic Instruction Decode Data Path B A Register File Enhanced DMA Controller (16 channel) .L1 .S1 .M1 .D1 In-Circuit Emulation .D2 .M2 .S2 .L2 Interrupt Control L1D Cache 2-Way Set Associative 4K Bytes L2 Memory 192K Bytes Clock Generator and PLL x4 through x25 Multiplier /1 through /32 Dividers Timer 0 Test B Register File Power-Down Logic GPIO 16 HPI In addition to fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces to: -SDRAM -SBSRAM -SRAM, -ROM/Flash, and -I/O devices McBSPs interface to: -SPI Control Port -High-Speed TDM Codecs -AC97 Codecs -Serial EEPROM POST OFFICE BOX 1443 McASPs interface to: -I2S Multichannel ADC, DAC, Codec, DIR -DIT: Multiple Outputs * HOUSTON, TEXAS 77251-1443 13 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 CPU (DSP core) description The TMS320C6713 floating-point digital signal processor is based on the C67x CPU. The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 CPU (DSP core) description (continued) AAAAA AAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAA AAAA AAAA AAAAA AAAAA AAAAA src1 .L1 src2 dst long dst long src LD1 32 MSB ST1 long src long dst dst .S1 src1 Data Path A 8 8 32 32 8 8 A A A A src2 dst src1 .M1 src2 LD1 32 LSB DA1 DA2 LD2 32 LSB A A A A .D1 .D2 dst src1 src2 src2 src2 .S2 LD2 32 MSB ST2 A A long src long dst dst .L2 src2 src1 Register File A (A0-A15) 1X .M2 src1 dst Data Path B AAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAAA AAAAA AAAAA AAAAA AAAAA AAAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAA A 2X src2 src1 dst src1 dst long dst long src A A A A 8 A A A A Register File B (B0-B15) 8 32 32 8 A A A A 8 In addition to fixed-point instructions, these functional units execute floating-point instructions. Control Register File Figure 1. TMS320C67x CPU (DSP Core) Data Paths POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 memory map summary Table 3 shows the memory map address ranges of the C6713 device. Table 3. TMS320C6713 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 192K 0000 0000 - 0002 FFFF Internal RAM/Cache 64K 0003 0000 - 0003 FFFF Reserved 24M - 256K 0004 0000 - 017F FFFF External Memory Interface (EMIF) Registers 256K 0180 0000 - 0183 FFFF L2 Registers 128K 0184 0000 - 0185 FFFF Reserved 128K 0186 0000 - 0187 FFFF HPI Registers 256K 0188 0000 - 018B FFFF McBSP 0 Registers 256K 018C 0000 - 018F FFFF McBSP 1 Registers 256K 0190 0000 - 0193 FFFF Timer 0 Registers 256K 0194 0000 - 0197 FFFF Timer 1 Registers 256K 0198 0000 - 019B FFFF 019C 0000 - 019C 01FF Interrupt Selector Registers 512 Device Configuration Registers 4 019C 0200 - 019C 0203 Reserved 256K - 516 019C 0204 - 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 - 01A3 FFFF Reserved 768K 01A4 0000 - 01AF FFFF GPIO Registers 16K 01B0 0000 - 01B0 3FFF Reserved 240K 01B0 4000 - 01B3 FFFF I2C0 Registers 16K 01B4 0000 - 01B4 3FFF I2C1 Registers 16K 01B4 4000 - 01B4 7FFF Reserved 16K 01B4 8000 - 01B4 BFFF McASP0 Registers 16K 01B4 C000 - 01B4 FFFF McASP1 Registers 16K 01B5 0000 - 01B5 3FFF Reserved 160K 01B5 4000 - 01B7 BFFF PLL Registers 8K 01B7 C000 - 01B7 DFFF Reserved 264K 01B7 E000 - 01BB FFFF Emulation Registers 256K 01BC 0000 - 01BF FFFF Reserved 4M 01C0 0000 - 01FF FFFF QDMA Registers 52 0200 0000 - 0200 0033 Reserved 16M - 52 0200 0034 - 02FF FFFF Reserved 720M 0300 0000 - 2FFF FFFF McBSP0 Data Port 64M 3000 0000 - 33FF FFFF McBSP1 Data Port 64M 3400 0000 - 37FF FFFF Reserved 64M 3800 0000 - 3BFF FFFF McASP0 Data Port 1M 3C00 0000 - 3C0F FFFF McASP1 Data Port 1M 3C10 0000 - 3C1F FFFF Reserved EMIF CE0 1G + 62M 3C20 0000 - 7FFF FFFF 256M 8000 0000 - 8FFF FFFF EMIF CE1 EMIF CE2 256M 9000 0000 - 9FFF FFFF 256M A000 0000 - AFFF FFFF EMIF CE3 256M B000 0000 - BFFF FFFF Reserved 1G C000 0000 - FFFF FFFF The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 L2 memory structure expanded Figure 2 shows the detail of the L2 memory structure. L2 Mode 000 001 010 L2 Memory 011 Block Base Address 111 192K SRAM 208K SRAM 224K SRAM 240K SRAM 192K-Byte RAM IIIIIIIIII IIIIIIIIII IIIIIIIIII 0x0003 0000 64K 4-Way Cache 48K 3-Way Cache 32K 2-Way Cache 16K-Byte RAM 16K 1-Way Cache 256K SRAM (All) 0x0000 0000 0x0003 4000 16K-Byte RAM 0x0003 8000 16K-Byte RAM 0x0003 C000 16K-Byte RAM 0x0003 FFFF Figure 2. L2 Memory Configuration POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions Table 4 through Table 17 identify the peripheral registers for the C6713 device by its register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190). Table 4. EMIF Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIF global control REGISTER NAME 0180 0004 CECTL1 EMIF CE1 space control 0180 0008 CECTL0 EMIF CE0 space control 0180 000C - 0180 0010 CECTL2 Reserved EMIF CE2 space control 0180 0014 CECTL3 EMIF CE3 space control 0180 0018 SDCTL EMIF SDRAM control 0180 001C SDTIM EMIF SDRAM refresh control 0180 0020 SDEXT EMIF SDRAM extension 0180 0024 - 0183 FFFF - Reserved Table 5. L2 Cache Registers 18 HEX ADDRESS RANGE ACRONYM 0184 0000 CCFG REGISTER NAME 0184 4000 L2WBAR L2 writeback base address register 0184 4004 L2WWC L2 writeback word count register 0184 4010 L2WIBAR L2 writeback-invalidate base address register 0184 4014 L2WIWC L2 writeback-invalidate word count register 0184 4020 L1PIBAR L1P invalidate base address register 0184 4024 L1PIWC L1P invalidate word count register 0184 4030 L1DWIBAR L1D writeback-invalidate base address register 0184 4034 L1DWIWC L1D writeback-invalidate word count register 0184 5000 L2WB 0184 5004 L2WBINV 0184 8200 MAR0 Controls CE0 range 8000 0000 - 80FF FFFF 0184 8204 MAR1 Controls CE0 range 8100 0000 - 81FF FFFF 0184 8208 MAR2 Controls CE0 range 8200 0000 - 82FF FFFF 0184 820C MAR3 Controls CE0 range 8300 0000 - 83FF FFFF 0184 8240 MAR4 Controls CE1 range 9000 0000 - 90FF FFFF 0184 8244 MAR5 Controls CE1 range 9100 0000 - 91FF FFFF 0184 8248 MAR6 Controls CE1 range 9200 0000 - 92FF FFFF 0184 824C MAR7 Controls CE1 range 9300 0000 - 93FF FFFF 0184 8280 MAR8 Controls CE2 range A000 0000 - A0FF FFFF 0184 8284 MAR9 Controls CE2 range A100 0000 - A1FF FFFF 0184 8288 MAR10 Controls CE2 range A200 0000 - A2FF FFFF 0184 828C MAR11 Controls CE2 range A300 0000 - A3FF FFFF 0184 82C0 MAR12 Controls CE3 range B000 0000 - B0FF FFFF 0184 82C4 MAR13 Controls CE3 range B100 0000 - B1FF FFFF 0184 82C8 MAR14 Controls CE3 range B200 0000 - B2FF FFFF 0184 82CC MAR15 Controls CE3 range B300 0000 - B3FF FFFF 0184 82D0 - 0185 FFFF - Cache configuration register L2 writeback all register L2 writeback-invalidate all register Reserved POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 6. Interrupt Selector Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7) 019C 000C - 019F FFFF - Reserved Table 7. Device Registers HEX ADDRESS RANGE ACRONYM 019C 0200 DEVCFG 019C 0204 - 019F FFFF - N/A CSR REGISTER DESCRIPTION Allows the user to control peripheral selection. This register also offers the user control of the EMIF input clock source. For more detailed information on the device configuration register, see the Device Configurations section of this data sheet. Device Configuration Reserved Identifies which CPU and defines the silicon revision of the CPU. This register also offers the user control of device operation. For more detailed information on the CPU Control Status Register, see the CPU CSR Register Description section of this data sheet. CPU Control Status Register Table 8. EDMA Parameter RAM HEX ADDRESS RANGE ACRONYM 01A0 0000 - 01A0 0017 - Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event 01A0 0018 - 01A0 002F - Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event 01A0 0030 - 01A0 0047 - Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event 01A0 0048 - 01A0 005F - Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event 01A0 0060 - 01A0 0077 - Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event 01A0 0078 - 01A0 008F - Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event 01A0 0090 - 01A0 00A7 - Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event 01A0 00A8 - 01A0 00BF - Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event 01A0 00C0 - 01A0 00D7 - Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event 01A0 00D8 - 01A0 00EF - Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event 01A0 00F0 - 01A0 00107 - Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event 01A0 0108 - 01A0 011F - Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event 01A0 0120 - 01A0 0137 - Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event 01A0 0138 - 01A0 014F - Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event 01A0 0150 - 01A0 0167 - Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event 01A0 0168 - 01A0 017F - Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event 01A0 0180 - 01A0 0197 - Reload/link parameters for Event 0-15 01A0 0198 - 01A0 01AF - Reload/link parameters for Event 0-15 ... REGISTER NAME ... 01A0 07E0 - 01A0 07F7 - 01A0 07F8 - 01A0 07FF - Reload/link parameters for Event 0-15 Scratch pad area (2 words) The C6713 device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 3. 31 0 EDMA Parameter Word 0 EDMA Channel Options Parameter (OPT) OPT Word 1 EDMA Channel Source Address (SRC) SRC Word 2 Array/Frame Count (FRMCNT) Word 3 Element Count (ELECNT) EDMA Channel Destination Address (DST) CNT DST Word 4 Array/Frame Index (FRMIDX) Element Index (ELEIDX) IDX Word 5 Element Count Reload (ELERLD) Link Address (LINK) RLD Figure 3. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event Table 9. EDMA Registers HEX ADDRESS RANGE ACRONYM 01A0 0800 - 01A0 FEFC - 01A0 FF00 ESEL0 EDMA event selector 0 01A0 FF04 ESEL1 EDMA event selector 1 01A0 FF08 - 01A0 FF0B - 01A0 FF0C ESEL3 01A0 FF1F - 01A0 FFDC - 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPR Channel interrupt pending register 01A0 FFE8 CIER Channel interrupt enable register 01A0 FFEC CCER Channel chain enable register 01A0 FFF0 ER 01A0 FFF4 EER Event enable register 01A0 FFF8 ECR Event clear register 01A0 FFFC ESR Event set register 01A1 0000 - 01A3 FFFF - 20 REGISTER NAME Reserved Reserved EDMA event selector 3 Reserved Event register Reserved POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 10. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0200 0000 QOPT QDMA options parameter register 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 - 0200 001C - 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA pseudo source address register 0200 0028 QSCNT QDMA pseudo frame count register 0200 002C QSDST QDMA pseudo destination address register 0200 0030 QSIDX Reserved QDMA pseudo index register All the QDMA and Pseudo registers are write-accessible only Table 11. PLL Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B7 C000 PLLPID Peripheral identification register (PID) 01B7 C004 - 01B7 C0FF - [C6713 value: 0x00010801 for PLL Controller] Reserved 01B7 C100 PLLCSR 01B7 C104 - 01B7 C10F - PLL control/status register 01B7 C110 PLLM 01B7 C114 PLLDIV0 PLL controller divider 0 register 01B7 C118 PLLDIV1 PLL controller divider 1 register 01B7 C11C PLLDIV2 PLL controller divider 2 register 01B7 C120 PLLDIV3 PLL controller divider 3 register 01B7 C124 OSCDIV1 Oscillator divider 1 register 01B7 C128 - 01B7 DFFF - Reserved PLL multiplier control register Reserved POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 3C10 0000 - 3C10 FFFF RBUF/XBUFx McASPx receive buffer or McASPx transmit buffer via the Peripheral Data Bus. (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].) 01B4 C000 01B5 0000 MCASPPIDx Peripheral Identification register [6713 value: 0x00100101 for McASP0 and for McASP1] 01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management register 01B4 C008 01B5 0008 - Reserved 01B4 C00C 01B5 000C - Reserved 01B4 C010 01B5 0010 PFUNCx Pin function register 01B4 C014 01B5 0014 PDIRx Pin direction register 01B4 C018 01B5 0018 PDOUTx Pin data out register 01B4 C01C 01B5 001C PDIN/PDSETx McASP0 McASP1 3C00 0000 - 3C00 FFFF Pin data in / data set register Read returns: PDIN Writes affect: PDSET 01B4 C020 01B5 0020 PDCLRx 01B4 C024 - 01B4 C040 01B5 0024 - 01B5 0040 - 01B4 C044 01B5 0044 GBLCTLx Global control register 01B4 C048 01B5 0048 AMUTEx Mute control register 01B4 C04C 01B5 004C DLBCTLx Digital Loop-back control register 01B4 C050 01B5 0050 DITCTLx DIT mode control register 01B4 C054 - 01B4 C05C 01B5 0054 - 01B5 005C - 01B4 C060 01B5 0060 RGBLCTLx 01B4 C064 01B5 0064 RMASKx Reserved Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register 01B4 C068 01B5 0068 RFMTx 01B4 C06C 01B5 006C AFSRCTLx 01B4 C070 01B5 0070 ACLKRCTLx 01B4 C074 01B5 0074 AHCLKRCTLx 01B4 C078 01B5 0078 RTDMx 01B4 C07C 01B5 007C RINTCTLx 01B4 C080 01B5 0080 RSTATx Status register - Receiver 01B4 C084 01B5 0084 RSLOTx Current receive TDM slot register 01B4 C088 01B5 0088 RCLKCHKx 01B4 C08C - 01B4 C09C 01B5 008C - 01B5 009C - 01B4 C0A0 01B5 00A0 XGBLCTLx 01B4 C0A4 01B5 00A4 XMASKx 01B4 C0A8 01B5 00A8 XFMTx 01B4 C0AC 01B5 00AC AFSXCTLx 01B4 C0B0 01B5 00B0 ACLKXCTLx 01B4 C0B4 01B5 00B4 AHCLKXCTLx 22 Pin data clear register POST OFFICE BOX 1443 Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0-31 register Receiver interrupt control register Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers (Continued) HEX ADDRESS RANGE McASP0 McASP1 ACRONYM REGISTER NAME 01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 0-31 register 01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control register 01B4 C0C0 01B5 00C0 XSTATx Status register - Transmitter 01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot 01B4 C0C8 01B5 00C8 XCLKCHKx 01B4 C0D0 - 01B4 C0FC 01B5 00CC - 01B5 00FC - 01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file 01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file Transmit clock check control register Reserved 01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file 01B4 C10C 01B5 010C DITCSRA3x Left (even TDM slot) channel status register file 01B4 C110 01B5 0110 DITCSRA4x Left (even TDM slot) channel status register file 01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file 01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file 01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file 01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file 01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file 01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file 01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file 01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file 01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file 01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file 01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file 01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file 01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file 01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file 01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file 01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file 01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file 01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file 01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file 01B4 C160 - 01B4 C17C 01B5 0160 - 01B5 017C - 01B4 C180 01B5 0180 SRCTL0x Serializer 0 control register 01B4 C184 01B5 0184 SRCTL1x Serializer 1 control register Reserved 01B4 C188 01B5 0188 SRCTL2x Serializer 2 control register 01B4 C18C 01B5 018C SRCTL3x Serializer 3 control register 01B4 C190 01B5 0190 SRCTL4x Serializer 4 control register 01B4 C194 01B5 0194 SRCTL5x Serializer 5 control register 01B4 C198 01B5 0198 SRCTL6x Serializer 6 control register 01B4 C19C 01B5 019C SRCTL7x Serializer 7 control register 01B4 C1A0 - 01B4 C1FC 01B5 01A0 - 01B5 01FC - POST OFFICE BOX 1443 Reserved * HOUSTON, TEXAS 77251-1443 23 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 12. McASP0 and McASP1 Registers (Continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B5 0200 XBUF0x 01B4 C204 01B5 0204 XBUF1x Transmit Buffer for Serializer 0 through configuration bus Transmit Buffer for Serializer 1 through configuration bus 01B4 C208 01B5 0208 XBUF2x 01B4 C20C 01B5 020C XBUF3x 01B4 C210 01B5 0210 XBUF4x 01B4 C214 01B5 0214 XBUF5x 01B4 C218 01B5 0218 XBUF6x 01B4 C21C 01B5 021C XBUF7x 01B4 C220 - 01B4 C27C 01B5 C220 - 01B5 027C - 01B4 C280 01B5 0280 RBUF0x 01B4 C284 01B5 0284 RBUF1x 01B4 C288 01B5 0288 RBUF2x 01B4 C28C 01B5 028C RBUF3x 01B4 C290 01B5 0290 RBUF4x 01B4 C294 01B5 0294 RBUF5x 01B4 C298 01B5 0298 RBUF6x 01B4 C29C 01B5 029C RBUF7x 01B4 C2A0 - 01B4 FFFF 01B5 02A0 - 01B5 3FFF - McASP0 McASP1 01B4 C200 Transmit Buffer for Serializer 2 through configuration bus Transmit Buffer for Serializer 3 through configuration bus Transmit Buffer for Serializer 4 through configuration bus Transmit Buffer for Serializer 5 through configuration bus Transmit Buffer for Serializer 6 through configuration bus Transmit Buffer for Serializer 7 through configuration bus Reserved Receive Buffer for Serializer 0 through configuration bus Receive Buffer for Serializer 1 through configuration bus Receive Buffer for Serializer 2 through configuration bus Receive Buffer for Serializer 3 through configuration bus Receive Buffer for Serializer 4 through configuration bus Receive Buffer for Serializer 5 through configuration bus Receive Buffer for Serializer 6 through configuration bus Receive Buffer for Serializer 7 through configuration bus Reserved The transmit buffers for serializers 0 - 7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register). The receive buffers for serializers 0 - 7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register). Table 13. I2C0 and I2C1 Registers HEX ADDRESS RANGE 24 ACRONYM REGISTER DESCRIPTION I2C0 I2C1 01B4 0000 01B4 4000 I2COARx I2Cx own address register 01B4 0004 01B4 4004 I2CIERx I2Cx interrupt enable register 01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register 01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider register 01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider register 01B4 0014 01B4 4014 I2CCNTx I2Cx data count register 01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register 01B4 001C 01B4 401C I2CSARx I2Cx slave address register 01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register 01B4 0024 01B4 4024 I2CMDRx I2Cx mode register 01B4 0028 01B4 4028 I2CISRCx I2Cx interrupt source register 01B4 002C 01B4 402C - 01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler register 01B4 0034 01B4 4034 I2CPID10 I2CPID11 I2Cx Peripheral Identification register 1 [C6713 value: 0x0000 0103] 01B4 0038 01B4 4038 I2CPID20 I2CPID21 I2Cx Peripheral Identification register 2 [C6713 value: 0x0000 0005] 01B4 003C - 01B4 3FFF 01B4 403C - 01B4 7FFF - POST OFFICE BOX 1443 Reserved Reserved * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 14. HPI Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS - HPID HPI data register Host read/write access only - HPIA HPI address register Host read/write access only 0188 0000 HPIC HPI control register Both Host/CPU read/write access 0188 0004 - 018B FFFF - Reserved Table 15. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE TIMER 0 TIMER 1 ACRONYM REGISTER NAME COMMENTS 0194 0000 0198 0000 CTLx Timer x control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 0198 0004 PRDx Timer x period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 0198 0008 CNTx Timer x counter register Contains the current value of the incrementing counter. 0194 000C - 0197 FFFF 0198 000C - 019B FFFF - Reserved - Table 16. McBSP0 and McBSP1 Registers HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION McBSP0 McBSP1 018C 0000 0190 0000 DRRx 3000 0000 - 33FF FFFF 3400 0000 - 37FF FFFF DRRx McBSPx data receive register via Peripheral Data Bus 018C 0004 0190 0004 DXRx McBSPx data transmit register via Configuration Bus 3000 0000 - 33FF FFFF 3400 0000 - 37FF FFFF DXRx McBSPx data transmit register via Peripheral Data Bus 018C 0008 0190 0008 SPCRx 018C 000C 0190 000C RCRx McBSPx receive control register 018C 0010 0190 0010 XCRx McBSPx transmit control register 018C 0014 0190 0014 SRGRx McBSPx data receive register via Configuration Bus The CPU and EDMA controller can only read this register; they cannot write to it. McBSPx serial port control register McBSPx sample rate generator register 018C 0018 0190 0018 MCRx McBSPx multichannel control register 018C 001C 0190 001C RCERx McBSPx receive channel enable register 018C 0020 0190 0020 XCERx McBSPx transmit channel enable register 018C 0024 0190 0024 PCRx 018C 0028 - 018F FFFF 0190 0028 - 0193 FFFF - POST OFFICE BOX 1443 McBSPx pin control register Reserved * HOUSTON, TEXAS 77251-1443 25 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 17. GPIO Registers HEX ADDRESS RANGE 26 ACRONYM REGISTER NAME 01B0 0000 GPEN GPIO enable register 01B0 0004 GPDIR GPIO direction register 01B0 0008 GPVAL GPIO value register 01B0 000C - 01B0 0010 GPDH GPIO delta high register 01B0 0014 GPHM GPIO high mask register 01B0 0018 GPDL GPIO delta low register 01B0 001C GPLM GPIO low mask register 01B0 0020 GPGC GPIO global control register 01B0 0024 GPPOL GPIO interrupt polarity register 01B0 0028 - 01B0 3FFF - Reserved Reserved POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 signal groups description CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLHV TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 Clock/PLL Oscillator Reset and Interrupts RESET NMI GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD4/GP[0] IEEE Standard 1149.1 (JTAG) Emulation Control/Status HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] HPI (Host-Port Interface) Control Data Register Select Half-Word Select HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1] HCNTL0/AXR1[3] HCNTL1/AXR1[1] HHWIL/AFSR1 These external pins are applicable to the GDP package only. The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the External Interrupt Sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646). All of these pins are external interrupt sources. For more details, see the External Interrupt Sources section of this data sheet. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 4. CPU (DSP Core) and Peripheral Signals POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 signal groups description (continued) HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0] GPIO General-Purpose Input/Output (GPIO) Port TOUT1/AXR0[4] Timer 1 Timer 0 TOUT0/AXR0[2] TINP0/AXR0[3] TINP1/AHCLKX0 Timers CLKS1/SCL1 DR1/SDA1 I2C1 I2C0 SCL0 SDA0 I2Cs The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external EDMA event source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 5. Peripheral Signals 28 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 signal groups description (continued) ED[31:16] 16 16 Data ED[15:0] CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 Memory Control ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY Memory Map Space Select 20 Address Bus Arbitration HOLD HOLDA BUSREQ Byte Enables EMIF (External Memory Interface) McBSP1 McBSP0 CLKX1/AMUTE0 FSX1 DX1/AXR0[5] Transmit Transmit CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1] CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1 Receive Receive CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0] Clock Clock CLKS1/SCL1 CLKS0/AHCLKR0 McBSPs (Multichannel Buffered Serial Ports) These external pins are applicable to the GDP package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 5. Peripheral Signals (Continued) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 signal groups description (continued) (Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) CLKR0/ACLKR0 CLKS0/AHCLKR0 (Transmit Bit Clock) Receive Clock Generator Transmit Clock Generator (Receive Master Clock) FSR0/AFSR0 (Receive Frame Sync or Left/Right Clock) CLKX0/ACLKX0 TINP1/AHCLKX0 (Transmit Master Clock) Receive Clock Check Circuit Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync Error Detect (see Note A) Auto Mute Logic FSX0/AFSX0 (Transmit Frame Sync or Left/Right Clock) CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0 McASP0 (Multichannel Audio Serial Port 0) NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 5. Peripheral Signals (Continued) 30 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 signal groups description (continued) (Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Transmit Bit Clock) Receive Clock Generator Transmit Clock Generator (Receive Master Clock) HHWIL/AFSR1 (Receive Frame Sync or Left/Right Clock) HAS/ACLKX1 HD5/AHCLKX1 (Transmit Master Clock) Receive Clock Check Circuit Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync Error Detect (see Note A) Auto Mute Logic HD2/AFSX1 (Transmit Frame Sync or Left/Right Clock) HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1 McASP1 (Multichannel Audio Serial Port 1) NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 5. Peripheral Signals (Continued) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS On the C6713 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. device configurations at device reset Table 18 describes the C6713 device configuration pins, which are set up via internal or external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8), and CLKMODE0 pin. These configuration pins must be in the desired state until reset is released. For proper device operation of the C6713 device, do not oppose the HD [15, 13:9, 7, 1, 0] pins with the external pullups/pulldowns at reset. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section of this data sheet. 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 18. Device Configurations Pins at Device Reset (HD[4:3], HD8, and CLKMODE0) CONFIGURATION PIN PYP GDP FUNCTIONAL DESCRIPTION HD12 168 C15 For proper C6713 device operation, do not oppose the internal pullup (IPU) resistor on this pin. HD8 160 B17 Device Endian mode (LEND) 0 - System operates in Big Endian mode 1 - System operates in Little Endian mode (default) HD[4:3] (BOOTMODE) CLKMODE0 156, 154 205 C19, C20 C4 Bootmode Configuration Pins (BOOTMODE) 00 - HPI boot/Emulation boot 01 - CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 - CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 - CE1 width 32-bit, Asynchronous external ROM boot with default timings For more detailed information on these bootmode configurations, see the bootmode section of this data sheet. Clock generator input clock source select 0 - Reserved. Do not use. 1 - CLKIN square wave [default] This pin must be pulled to the correct level even after reset. All other HD pins (HD [15, 13:9, 7:5, 2:0]) have pullups/pulldowns (IPUs or IPDs). For proper device operation of the HD [15, 13:9, 7, 1, 0], do not oppose these pins with external pullups/pulldowns at reset; however, the HD[6, 5, 2] pins can be opposed and driven during reset. IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) peripheral pin selection at device reset Some C6713 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:8, 3, 1, 0] and McASP1). D HPI, McASP1, and GPIO peripherals The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 19). Table 19. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) PERIPHERAL PIN SELECTION HPI_EN (HD14 Pin) [173, C14] PERIPHERAL PINS SELECTED HPI 0 1 DESCRIPTION McASP1 and GP[15:8,3,1,0] HPI_EN = 0 HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as McASP1 and GPIO pins, respectively. To use the GPIO pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. HPI_EN = 1 HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins function as HPI pins. The HPI_EN (HD[14]) pin cannot be controlled via software. 34 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations via the DEVCFG control register The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0, McBSP1, McASP0, I2C1, and Timer peripherals. The DEVCFG register also offers the user control of the EMIF input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits, see Table 20 and Table 21. Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 - 0x019C02FF] 31 16 Reserved RW-0 5 4 3 2 1 0 Reserved EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS RW-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 Legend: R/W = Read/Write; -n = value after reset Do not write non-zero values to these bit locations. Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions BIT # NAME 31:5 Reserved 4 3 2 1 0 EKSRC DESCRIPTION Reserved. Do not write non-zero values to these bit locations. EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock. 0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default) 1 = ECLKIN external pin is the EMIF input clock source TOUT1SEL Timer 1 output (TOUT1) pin function select bit. Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 1 output (TOUT1) pin (default) 1 = The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]). The Timer 1 module is still active. TOUT0SEL Timer 0 output (TOUT0) pin function select bit. Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 0 output (TOUT0) pin (default) 1 = The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]). The Timer 0 module is still active. MCBSP0DIS Multichannel Buffered Serial Port 0 (McBSP0) disable bit. Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled. 0 = McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default). [If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT mode only.] 1 = McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled. MCBSP1DIS Multichannel Buffered Serial Port 1 (McBSP1) disable bit. Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled. 0 = McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default) 1 = McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are enabled. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The muxed pins that are configured by software can be programmed to switch functionalities at any time. The muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 22 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 23 identifies the multiplexed pins on the C6713 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions. 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 22. Peripheral Pin Selection Matrix SELECTION BITS B I T N A M E B I T V A L U E PERIPHERAL PINS AVAILABILITY M c A S P 0 TOUT1SEL (DEVCFG bit) I 2 C 1 M c B S P 0 M c B S P 1 0 1 H P I 0 None 1 None All G P I O P I N S E M I F GP[0:1], GP[3], GP[8:15] 0 None All 1 ACLKX0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] None 0 NO AMUTE0 AXR0[5] AXR0[6] AXR0[7] None All 1 AMUTE0 AXR0[5] AXR0[6] AXR0[7] All None 0 NO AXR0[2] TOUT0 1 AXR0[2] NO TOUT0 0 NO AXR0[4] TOUT1 1 AXR0[4] NO TOUT1 MCBSP1DIS (DEVCFG bit) TOUT0SEL (DEVCFG bit) I 2 C 0 T I M E R AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] to AXR1[7] HPI_EN (boot config pin) MCBSP0DIS (DEVCFG bit) M c A S P 1 T I M E R Plus: GP[2] ctrl'd by GP2EN bit NO GP[0:1], GP[3], GP[8:15] Gray blocks indicate that the peripheral is not affected by the selection bit. The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 23 for more detailed information. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713 Device Multiplexed/Shared Pins MULTIPLEXED PINS NAME CLKOUT2/GP[2] PYP 82 GDP Y12 GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 6 1 C1 C2 CLKS0/AHCLKR0 28 K3 DR0/AXR0[0] 27 J1 DX0/AXR0[1] 20 H2 FSR0/AFSR0 24 J3 FSX0/AFSX0 21 H1 CLKR0/ACLKR0 19 H3 CLKX0/ACLKX0 16 G3 CLKS1/SCL1 8 E1 DR1/SDA1 37 M2 DX1/AXR0[5] 32 L2 FSR1/AXR0[7] 38 M3 CLKR1/AXR0[6] 36 M1 CLKX1/AMUTE0 33 L3 38 DEFAULT FUNCTION CLKOUT2 GP[5](EXT_INT5) GP[4](EXT_INT4) McBSP0 pin function McBSP1 pin function POST OFFICE BOX 1443 DEFAULT SETTING DESCRIPTION GP2EN = 0 (GPEN register bit) GP[2] function disabled, CLKOUT2 enabled When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin. CLK2EN = 0: CLKOUT2 held high CLK2EN = 1: CLKOUT2 enabled to clock [default] No Function GPxDIR = 0 (input) GP5EN = 0 (disabled) GP4EN = 0 (disabled) [(GPEN register bits) GP[x] function disabled] MCBSP0DIS = 0 (DEVCFG register bit) McASP0 pins disabled, McBSP0 pins enabled MCBSP1DIS = 0 (DEVCFG register bit) I2C1 and McASP0 pins disabled, McBSP1 pins enabled * HOUSTON, TEXAS 77251-1443 To use these software-configurable GPIO pins, the GPxEN bits in the GP Enable Register and the GPxDIR bits in the GP Direction Register must be properly configured. GPxEN = 1: GP[x] pin enabled GPxDIR = 0: GP[x] pin is an input GPxDIR = 1: GP[x] pin is an output To use AMUTEIN0/1 pin function, the GP[5]/GP[4] pins must be configured as an input, the INEN bit set to 1, and the polarity through the INPOL bit selected in the associated McASP AMUTE register. By default, McBSP0 peripheral pins are enabled upon reset (McASP0 pins are disabled). To enable the McASP0 peripheral pins, the MCBSP0DIS bit in the DEVCFG register must be set to 1 (disabling the McBSP0 peripheral pins). By default, McBSP1 peripheral pins are enabled upon reset (I2C1 and McASP0 pins are disabled). To enable the I2C1 and McASP0 peripheral pins, the MCBSP1DIS bit in the DEVCFG register must be set to 1 (disabling the McBSP1 peripheral pins). SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713 Device Multiplexed/Shared Pins (Continued) MULTIPLEXED PINS NAME PYP GDP HINT/GP[1] 135 J20 HD15/GP[15] 174 B14 HD14/GP[14] 173 C14 HD13/GP[13] 172 A15 HD12/GP[12] 168 C15 HD11/GP[11] 167 A16 HD10/GP[10] 166 B16 HD9/GP[9] 165 C16 HD8/GP[8] 160 B17 HD7/GP[3] 164 A18 HD4/GP[0] 156 C19 HD1/AXR1[7] 152 D20 HD0/AXR1[4] 147 E20 HCNTL1/AXR1[1] 144 G19 HCNTL0/AXR1[3] 146 G18 HR/W/AXR1[0] 143 G20 HDS1/AXR1[6] 151 E19 HDS2/AXR1[5] 150 F18 HCS/AXR1[2] 145 F20 HD6/AHCLKR1 161 C17 HD5/AHCLKX1 159 B18 HD3/AMUTE1 154 C20 HD2/AFSX1 155 D18 HHWIL/AFSR1 139 H20 HRDY/ACLKR1 140 H19 HAS/ACLKX1 153 E18 TINP0/AXR0[3] 17 G2 DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION By default, the HPI peripheral pins are enabled at reset. McASP1 peripheral pins and eleven GPIO pins are disabled. To enable the McASP1 peripheral pins and the eleven GPIO pins, an external pulldown resistor must be provided on the HD14 pin setting HPI_EN = 0 at reset. HPI_EN (HD14 pin) = 1 (HPI enabled) HPI pin function McASP1 pins and eleven GPIO pins are disabled. To use these software-configurable GPIO pins, the GPxEN bits in the GP Enable Register and the GPxDIR bits in the GP Direction Register must be properly configured. GPxEN = 1: GP[x] pin enabled GPxDIR = 0: GP[x] pin is an input GPxDIR = 1: GP[x] pin is an output McASP1 pin direction is controlled by the PDIR[x] bits in the McASP1PDIR register. Timer 0 input function McASP0PDIR = 0 (input) [specifically AXR0[3] bit] By default, the Timer 0 input pin is enabled (and a shared input until the McASP0 peripheral forces an output). McASP0PDIR = 0 input, = 1 output By default, the Timer 0 output pin is enabled. TOUT0/AXR0[2] 18 G1 Timer 0 output function POST OFFICE BOX 1443 TOUT0SEL = 0 (DEVCFG register bit) [TOUT0 pin enabled and McASP0 AXR0[2] pin disabled] * HOUSTON, TEXAS 77251-1443 To enable the McASP0 AXR0[2] pin, the TOUT0SEL bit in the DEVCFG register must be set to 1 (disabling the Timer 0 peripheral output pin function). The AXR2 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[2] pin McASP0PDIR = 0 input, = 1 output 39 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713 Device Multiplexed/Shared Pins (Continued) MULTIPLEXED PINS NAME TINP1/AHCLKX0 PYP 12 GDP F2 DEFAULT FUNCTION Timer 1 input function DEFAULT SETTING DESCRIPTION McASP0PDIR = 0 (input) [specifically AHCLKX bit] By default, the Timer 1 input and McASP0 clock function are enabled as inputs. For the McASP0 clock to function as an output: McASP0PDIR = 1 (specifically the AHCLKX bit] By default, the Timer 1 output pin is enabled. TOUT1/AXR0[4] 13 F1 Timer 1 output function TOUT1SEL = 0 (DEVCFG register bit) [TOUT1 pin enabled and McASP0 AXR0[4] pin disabled] To enable the McASP0 AXR0[4] pin, the TOUT1SEL bit in the DEVCFG register must be set to 1 (disabling the Timer 1 peripheral output pin function). The AXR4 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[4] pin McASP0PDIR = 0 input, = 1 output configuration examples Figure 6 through Figure 11 illustrate examples of peripheral selections that are configurable on this device. 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI SCL1, SDA1 I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 McASP1 8 AXR1[7:0] 8 AXR0[7:0] {TINP0/AXR0[3]} McBSP1 McASP0 TIMER0 McBSP0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS = 1 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 6. Configuration Example A (2 I2C + 2 McASP + GPIO) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 5 AXR0[4:0] {TINP0/AXR0[3]} DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TIMER0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 McBSP0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E MCBSP0DIS = 1 MCBSP1DIS = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 7. Configuration Example B (1 I2C + 1 McBSP + 2 McASP + GPIO) 42 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI SCL1, SDA1 I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 McASP1 8 AXR1[7:0] 6 McBSP1 McASP0 (DIT Mode) AXR0[7:2] {TINP0/AXR0[3]} AMUTE0, TINP1/AHCLKX0 TIMER0 McBSP0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000D MCBSP0DIS = 0 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 8. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO] POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset GP[15:8, 3:1] GPIO and EXT_INT HPI I2C1 GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) I2C0 SCL0, SDA0 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 3 McBSP1 DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McASP0 (DIT Mode) AXR0[4:2] {TINP0/AXR0[3]} TINP1/AHCLKX0 TIMER0 TOUT0/AXR0[2] TIMER1 TOUT1/AXR0[4] McBSP0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000C MCBSP0DIS = 0 MCBSP1DIS = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 9. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers] 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset CLKOUT2 GPIO and EXT_INT GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) 16 HD[15:0] HPI I2C0 I2C1 McASP1 SCL0, SDA0 HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS SCL1, SDA1 8 AXR0[7:0], {TINP0/AXR0[3]} McBSP1 McASP0 TIMER0 McBSP0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS = 1 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (enabling GPEN.[2]) Figure 10. Configuration Example E (1 I2C + HPI + 1 McASP) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued) ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI Clock, System, EMU, and Reset CLKOUT2 GPIO and EXT_INT GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) 16 HD[15:0] HPI I2C0 I2C1 McASP1 SCL0, SDA0 HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS 5 AXR0[4:0] {TINP0/AXR0[3]} DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1 McBSP1 McASP0 TIMER0 TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 McBSP0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E MCBSP0DIS = 1 MCBSP1DIS = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (enabling GPEN.[2]) Figure 11. Configuration Example F (1 McBSP + HPI + 1 McASP) 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) debugging considerations It is recommended that external connections be provided to peripheral selection/device configuration pins, including HD[14, 8, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus (HD[15, 13:9, 7:5, 2:0]. For proper device operation of the HD[15, 13:9, 7, 1, 0], do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these HD[15, 13:9, 7, 1, 0] non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For a list of routed out, 3-stated, or not-driven pins recommended for external pullup/pulldown resistors, and internal pullup/pulldown resistors for all device pins, etc., see the Terminal Functions table. However, the HD[6, 5, 2] non-configuration pins can be opposed and driven during reset. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. Terminal Functions SIGNAL NAME PIN NO. TYPE IPD/ IPU DESCRIPTION PYP GDP CLKIN 204 A3 I IPD Clock Input CLKOUT2/GP[2] 82 Y12 O/Z IPD Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z) CLKOUT3 184 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller. IPU Clock generator input clock source select 0 - Reserved, do not use. 1 - CLKIN square wave [default] For proper device operation, this pin must be either left unconnected or externally pulled up with a 1-k resistor. CLOCK/PLL CONFIGURATION CLKMODE0 205 C4 I PLLHV 202 C5 A TMS 192 B7 I IPU JTAG test-port mode select TDO 187 A8 O/Z IPU JTAG test-port data out TDI 191 A7 I IPU JTAG test-port data in TCK 193 A6 I IPU JTAG test-port clock TRST 197 B6 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU5 -- B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 -- C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 -- B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 -- D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. Analog power (3.3 V) for PLL (PLL Filter) JTAG EMULATION EMU1 EMU0 185 186 B9 D9 I/O/Z IPU Emulation [1:0] pins * Select the device functional mode of operation EMU[1:0] Operation 00 Boundary Scan/Functional Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Functional Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet) The DSP can be placed in Functional mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Functional mode. For the Boundary Scan mode drive EMU[1:0] and RESET pins low. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] To ensure a proper logic level during reset when these pins are both routed out and 3-stated or not driven, it is recommended to include an external 10 k pullup/pulldown resistor to sustain the IPU/IPD, respectively. 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION RESETS AND INTERRUPTS RESET NMI 176 A13 175 C13 GP[7](EXT_INT7) 7 E3 GP[6](EXT_INT6) 2 D2 GP[5](EXT_INT5)/ AMUTEIN0 6 C1 GP[4](EXT_INT4)/ AMUTEIN1 1 C2 I I I/O/Z IPU Device reset. When using Boundary Scan mode, drive the EMU[1:0] and RESET pins low. IPD Nonmaskable interrupt * Edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. IPU General-purpose input/output pins (I/O/Z) which also function as external interrupts * Edge-driven * Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]), in addition to the GPIO registers. GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the associated McASP AMUTE register. HOST-PORT INTERFACE (HPI) HINT/GP[1] 135 J20 O/Z IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HCNTL1/AXR1[1] 144 G19 I IPU Host control - selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). HCNTL0/AXR1[3] 146 G18 I IPU Host control - selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). HHWIL/AFSR1 139 H20 I IPU Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HR/W/AXR1[0] 143 G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HD15/GP[15] 174 B14 IPU HD14/GP[14] 173 C14 IPU HD13/GP[13] HD12/GP[12] 172 168 A15 Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) * Used for transfer of data, address, and control * Also controls initialization of DSP modes at reset via pullup/pulldown resistors - Device Endian Mode (HD8) 0 - Big Endian 1 - Little Endian IPU C15 IPU HD11/GP[11] 167 A16 HD10/GP[10] 166 B16 IPU HD9/GP[9] 165 C16 IPU HD8/GP[8] 160 B17 IPU I/O/Z For proper C6713 device operation, do not oppose the internal pullup (IPU) resistor on HD12. IPU - Boot mode (HD[4:3]) 00 - HPI boot/Emulation boot 01 - CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 - CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 - CE1 width 32-bit, Asynchronous external ROM boot with default timings - HPI_EN (HD14) 0 - HPI disabled, McASP1 enabled 1 - HPI enabled, McASP1 disabled (default) Other HD pins (HD [15, 13:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation of the HD[15, 13:9, 7, 1, 0], do not oppose these pins with external IPUs/IPDs at reset; however, the HD[6, 5, 2] pins can be opposed HD7/GP[3] 164 A18 IPU and driven at reset. For more details, see the Device Configurations section of this data sheet. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] To ensure a proper logic level during reset when these pins are both routed out and 3-stated or not driven, it is recommended to include an external 10 k pullup/pulldown resistor to sustain the IPU/IPD, respectively. 50 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0] pin (I/O/Z). IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z). IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z). IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z). IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z). I IPU Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z). F20 I IPU Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z). E19 I IPU Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z). F18 I IPU Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z) . H19 O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z). HD6/AHCLKR1 161 C17 HD5/AHCLKX1 159 B18 HD4/GP[0] 156 C19 HD3/AMUTE1 154 C20 HD2/AFSX1 155 D18 HD1/AXR1[7] 152 D20 HD0/AXR1[4] 147 E20 I/O/Z HAS/ACLKX1 153 E18 HCS/AXR1[2] 145 HDS1/AXR1[6] 151 HDS2/AXR1[5] 150 HRDY/ACLKR1 140 I/O/Z I/O/Z I/O/Z EMIF - COMMON SIGNALS TO ALL TYPES OF MEMORY CE3 57 V6 O/Z IPU CE2 61 W6 O/Z IPU CE1 103 W18 O/Z IPU CE0 102 V17 O/Z IPU BE3 -- V5 O/Z IPU BE2 -- Y4 O/Z IPU BE1 108 U19 O/Z IPU BE0 110 V20 O/Z IPU HOLDA 137 J18 O/Z IPU Hold-request-acknowledge to the host HOLD 138 J17 I IPU Hold request from the host Memory space enables * Enabled by bits 28 through 31 of the word address * Only one asserted during any external data access Byte-enable control * Decoded from the two lowest bits of the internal address * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF - BUS ARBITRATION BUSREQ 136 J19 O/Z IPU Bus request output I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] To ensure a proper logic level during reset when these pins are both routed out and 3-stated or not driven, it is recommended to include an external 10 k pullup/pulldown resistor to sustain the IPU/IPD, respectively. To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION EMIF - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL ECLKIN ECLKOUT 78 77 Y11 Y10 I O/Z IPD IPD External EMIF input clock source EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]). EKSRC = 0 - ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default). EKSRC = 1 - ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN) EKEN = 0 EKEN = 1 - ECLKOUT held low - ECLKOUT enabled to clock (default) ARE/SDCAS/ SSADS 79 V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe AOE/SDRAS/ SSOE 75 W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE/SDWE/ SSWE 83 V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY 56 Y5 I IPU EA21 109 U18 EA20 101 Y18 EA19 100 W17 EA18 95 Y16 EA17 99 V16 EA16 92 Y15 EA15 94 W15 EA14 90 Y14 EA13 91 W14 EA12 93 V14 EA11 86 W13 EA10 76 V10 EA9 74 Y9 EA8 71 V9 EA7 70 Y8 EA6 69 W8 EA5 68 V8 EA4 64 W7 EA3 63 V7 O/Z IPU Asynchronous memory ready input EMIF - ADDRESS EMIF external address Note: EMIF address numbering for the C6713PYP device starts with EA2 to maintain signal name compatibility with other C671x devices (e.g., C6711 and C6713GDP) [see the 32-bit EMIF addressing scheme in the TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU266)]. EA2 62 Y6 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. 52 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION EMIF - DATA ED31 -- N3 ED30 -- P3 ED29 -- P2 ED28 -- P1 ED27 -- R2 ED26 -- R3 ED25 -- T2 ED24 -- T1 ED23 -- U3 ED22 -- U1 ED21 -- U2 ED20 -- V1 ED19 -- V2 ED18 -- Y3 ED17 -- W4 ED16 -- V4 ED15 112 T19 ED14 113 T20 ED13 111 T18 ED12 118 R20 ED11 117 R19 ED10 120 P20 ED9 119 P18 ED8 123 N20 ED7 122 N19 ED6 121 N18 ED5 128 M20 ED4 127 M19 ED3 129 L19 ED2 130 L18 ED1 131 K19 I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP package only) ED0 132 K18 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL PIN NO. TYPE IPD/ IPU DESCRIPTION MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1) GP[4](EXT_INT4)/ AMUTEIN1 1 C2 I/O/Z IPU General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or McASP1 mute input (I/O/Z). HD3/AMUTE1 154 C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z). HRDY/ACLKR1 140 H19 I/O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z). HD6/AHCLKR1 161 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). HAS/ACLKX1 153 E18 I/O/Z IPU Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z). HD5/AHCLKX1 159 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). HHWIL/AFSR1 139 H20 I/O/Z IPU Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HD2/AFSX1 155 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/ right clock (LRCLK) (I/O/Z). HD1/AXR1[7] 152 D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 TX/RX data pin 7 (I/O/Z). HDS1/AXR1[6] 151 E19 I/O/Z IPU Host data strobe 1 (I) [default] or McASP1 TX/RX data pin 6 (I/O/Z). HDS2/AXR1[5] 150 F18 I/O/Z IPU Host data strobe 2 (I) [default] or McASP1 TX/RX data pin 5 (I/O/Z). HD0/AXR1[4] 147 E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 TX/RX data pin 4 (I/O/Z). HCNTL0/AXR1[3] 146 G18 I/O/Z IPU Host control - selects between control, address, or data registers (I) [default] or McASP1 TX/RX data pin 3 (I/O/Z). HCS/AXR1[2] 145 F20 I/O/Z IPU Host chip select (I) [default] or McASP1 TX/RX data pin 2 (I/O/Z). HCNTL1/AXR1[1] 144 G19 I/O/Z IPU Host control - selects between control, address, or data registers (I) [default] or McASP1 TX/RX data pin 1 (I/O/Z). HR/W/AXR1[0] 143 G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z). MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) GP[5](EXT_INT5)/ AMUTEIN0 6 C1 I/O/Z IPU General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or McASP0 mute input (I/O/Z). CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z). CLKR0/ACLKR0 19 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). TINP1/AHCLKX0 12 F2 I/O/Z IPD Timer 1 input (I) or McASP0 transmit high-frequency master clock (I/O/Z). This pin defaults as Timer 1 input (I) and McASP transmit high-frequency master clock input (I). CLKX0/ACLKX0 16 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). CLKS0/AHCLKR0 28 K3 I/O/Z IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). FSR0/AFSR0 24 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). FSX0/AFSX0 21 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). FSR1/AXR0[7] 38 M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED) CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z). DX1/AXR0[5] TOUT1/AXR0[4] 32 L2 I/O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z). 13 F1 I/O/Z IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z). TINP0/AXR0[3] 17 G2 I/O/Z IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z). TOUT0/AXR0[2] 18 G1 I/O/Z IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z). DX0/AXR0[1] 20 H2 I/O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z). DR0/AXR0[0] 27 J1 I/O/Z IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z). TOUT1/AXR0[4] 13 F1 O IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z). TINP1/AHCLKX0 12 F2 I IPD Timer 1 input (I) or McASP0 transmit high-frequency master clock (I/O/Z). This pin defaults as Timer 1 input (I) and McASP transmit high-frequency master clock input (I). TIMER 1 TIMER0 TOUT0/AXR0[2] 18 G1 O IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z). TINP0/AXR0[3] 17 G2 I IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z). MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1/SCL1 8 E1 I -- McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-k resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-k pullup resistor may be desirable even when an external device is driving the pin. CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z). CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z). McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-k resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-k pullup resistor may be desirable even when an external device is driving the pin. DR1/SDA1 37 M2 I -- DX1/AXR0[5] 32 L2 O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z). FSR1/AXR0[7] 38 M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z). FSX1 31 L1 I/O/Z IPD McBSP1 transmit frame sync I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 55 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0/AHCLKR0 28 K3 I IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). CLKR0/ACLKR0 19 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). CLKX0/ACLKX0 16 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). DR0/AXR0[0] 27 J1 I IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z). DX0/AXR0[1] 20 H2 O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z). FSR0/AFSR0 24 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). FSX0/AFSX0 21 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). INTER-INTEGRATED CIRCUIT 1 (I2C1) CLKS1/SCL1 DR1/SDA1 8 37 E1 M2 I/O/Z I/O/Z -- McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). This pin must be externally pulled up. When this pin is used as an I2C pin, the value of the pullup resistor is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I 2C Specification Revision 2.1 (January 2000). -- McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). This pin must be externally pulled up. When this pin is used as an I2C pin, the value of the pullup resistor is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I 2C Specification Revision 2.1 (January 2000). INTER-INTEGRATED CIRCUIT 0 (I2C0) SCL0 SDA0 41 42 N1 N2 I/O/Z I/O/Z -- I2C0 clock. This pin must be externally pulled up. The value of the pullup resistor on this pin is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I 2C Specification Revision 2.1 (January 2000). -- I2C0 data. This pin must be externally pulled up. The value of the pullup resistor on this pin is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I 2C Specification Revision 2.1 (January 2000). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE IPD/ IPU DESCRIPTION GENERAL-PURPOSE INPUT/OUTPUT (GPIO) Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) and some function as boot configuration pins at reset. * Used for transfer of data, address, and control * Also controls initialization of DSP modes at reset via pullup/pulldown resistors HD15/GP[15] 174 B14 IPU HD14/GP[14] 173 C14 IPU HD13/GP[13] 172 A15 IPU HD12/GP[12] 168 C15 IPU HD11/GP[11] 167 A16 IPU HD10/GP[10] 166 B16 IPU HD9/GP[9] 165 C16 IPU HD8/GP[8] 160 B17 IPU GP[7](EXT_INT7) 7 E3 GP[6](EXT_INT6) 2 D2 GP[5](EXT_INT5)/ AMUTEIN0 6 C1 GP[4](EXT_INT4)/ AMUTEIN1 1 C2 HD7/GP[3] 164 A18 I/O/Z IPU Host-port data pin 7 (I/O/Z) [default] or general-purpose input/output pin 3 (I/O/Z) CLKOUT2/GP[2] 82 Y12 I/O/Z IPD Clock output at half of device speed (O/Z) [default] or this pin can be programmed as GP[2] pin. HINT/GP[1] 135 J20 O IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HD4/GP[0] 156 C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0] pin (I/O/Z). I/O/Z I/O/Z IPU As general-purpose input/output (GP[x]) functions, these pins are software-configurable through registers. The "GPxEN" bits in the GP Enable register and the GPxDIR bits in the GP Direction register must be properly configured: GPxEN = 1; GP[x] pin is enabled. GPxDIR = 0; GP[x] pin is an input. GPxDIR = 1; GP[x] pin is an output. For the functionality description of the Host-port data pins or the boot configuration pins, see the Host-Port Interface (HPI) portion of this table. General-purpose input/output pins (I/O/Z) which also function as external interrupts * Edge-driven * Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the associated McASP AMUTE register. RESERVED FOR TEST RSV 198 A5 200 B5 O/Z A IPU RSV Reserved. (Leave unconnected, do not connect to power or ground) RSV 179 C12 O -- Reserved. (Leave unconnected, do not connect to power or ground) RSV -- D7 O/Z IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV 178 D12 I -- Reserved. This pin does not have an IPU. For proper device operation, the D12 pin must be externally pulled down with a 10-k resistor. RSV 181 A12 -- Reserved. [For new designs, it is recommended that this pin be connected directly to CVDD (core power). For old designs, this pin can be left unconnected. Reserved. (Leave unconnected, do not connect to power or ground) Reserved. [For new designs, it is recommended that this pin be connected directly to Vss (ground). For old designs, this pin can be left unconnected. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 k and 2.0 k, respectively.] RSV 180 B11 -- POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 57 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP -- A17 -- B3 TYPE DESCRIPTION SUPPLY VOLTAGE PINS DVDD -- B8 -- B13 -- C10 -- D1 -- D16 -- D19 -- F3 -- H18 -- J2 -- M18 -- R1 -- R18 -- T3 -- U5 -- U7 -- U12 -- U16 -- V13 -- V15 -- V19 -- W3 -- W9 -- W12 -- Y7 -- Y17 5 -- 9 -- 25 -- 44 -- 47 -- 55 -- 58 -- 65 -- 72 -- 84 -- 87 -- 98 -- S 3.3-V supply voltage (see the power-supply decoupling portion of this data sheet) 107 -- I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal 58 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP 114 -- 126 -- 141 -- 162 -- 183 -- 188 -- 206 -- -- A4 -- A9 -- A10 TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) DVDD CVDD -- B2 -- B19 -- C3 -- C7 -- C18 -- D5 -- D6 -- D11 -- D14 -- D15 -- F4 -- F17 -- K1 -- K4 -- K17 -- L4 -- L17 -- L20 -- R4 -- R17 -- U6 -- U10 -- U11 -- U14 -- U15 -- V3 -- V18 -- W2 S S 3.3-V supply voltage (see the power-supply decoupling portion of this data sheet) 1.2-V supply voltage [PYP package] 1.20-V supply voltage [GDP package] (See Note) (see the power-supply decoupling portion of this data sheet) Note: This value is compatible with existing 1.26-V designs. -- W19 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 59 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) CVDD 3 -- 11 -- 14 -- 22 -- 29 -- 35 -- 40 -- 43 -- 46 -- 50 -- 51 -- 53 -- 60 -- 67 -- 80 -- 89 -- 96 -- 104 -- 105 -- 116 -- 124 -- 133 -- 149 -- 157 -- 169 -- 171 -- 177 -- 190 -- 195 -- 196 -- 201 -- 208 -- S 1.2-V supply voltage [PYP package] 1.20-V supply voltage [GDP package] (See Note) (see the power-supply decoupling portion of this data sheet) Note: This value is compatible with existing 1.26-V designs. GROUND PINS -- VSS A1 -- A2 -- A11 -- A14 -- A19 -- A20 -- B1 GND Ground pins -- B4 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal 60 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP -- B15 -- B20 -- C6 -- C8 -- C9 -- D4 -- D8 -- D13 -- D17 -- E2 TYPE DESCRIPTION GROUND PINS (CONTINUED) VSS -- E4 -- E17 -- F19 -- G4 -- G17 -- H4 -- H17 -- J4 -- J9 -- J10 -- J11 -- J12 -- K2 -- K9 -- K10 -- K11 -- K12 -- K20 -- L9 -- L10 -- L11 -- L12 -- M4 -- M9 -- M10 -- M11 -- M12 GND Ground pins The center thermal balls (J9-J12, K9-K12, L9-L12, M9-M12) [shaded] are all tied to ground and act as both electrical grounds and thermal relief (thermal dissipation). -- M17 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal Shaded pin numbers denote the center thermal balls. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 61 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP -- N4 -- N17 TYPE DESCRIPTION GROUND PINS (CONTINUED) VSS -- P4 -- P17 -- P19 -- T4 -- T17 -- U4 -- U8 -- U9 -- U13 -- U17 -- U20 -- W1 -- W5 -- W11 -- W16 -- W20 -- Y1 -- Y2 -- Y13 -- Y19 -- Y20 4 -- 10 -- 15 -- 23 -- 26 -- 30 -- 34 -- 39 -- 45 -- 48 -- 49 -- 52 -- 54 -- 59 -- 66 -- 73 -- GND Ground pins 81 -- I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal 62 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Terminal Functions (Continued) SIGNAL NAME PIN NO. PYP GDP 85 -- 88 -- 97 -- 106 -- TYPE DESCRIPTION GROUND PINS (CONTINUED) VSS 115 -- 125 -- 134 -- 142 -- 148 -- 158 -- 163 -- 170 -- 182 -- 189 -- 194 -- 199 -- 203 -- GND Ground pins 207 -- I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 63 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. C6000 and XDS are trademarks of Texas Instruments. 64 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 device support device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. (e.g., TMS320C6713GDP225). Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GDP), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -225 is 225 MHz). For device part numbers and further ordering information for TMS320C6713 in the PYP and GDP, package types, see the TI website (http://www.ti.com) or contact your TI sales representative. TMS320 is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 65 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 device and development-support tool nomenclature (continued) TMS 320 C 6713 GDP ( ) 225 DEVICE SPEED RANGE 225 MHz 200 MHz 167 MHz PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535) TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature DEVICE FAMILY 320 = TMS320 DSP family PACKAGE TYPE GDP = 272-pin plastic BGA PYP = 208-pin PowerPADt plastic QFP TECHNOLOGY C = CMOS DEVICE C6000 DSP: C6713 BGA = Ball Grid Array QFP = Quad Flatpack For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this document or the TI website (www.ti.com). Figure 12. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6713 Device) MicroStar BGA and PowerPAD are trademarks of Texas Instruments. 66 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG Overview] (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. These C6713 peripherals are similar to the peripherals on the TMS320C6711 and TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral information, and in some cases, where indicated, see the TMS320C6711 (C6711 or C671x) peripheral information and in some cases, where indicated, see the C64x information in the C6000 PRG Overview (literature number SPRU190). The TMS320DA6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes the functionality of the McASP peripherals available on the C6713 device. TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233) describes the functionality of the PLL peripheral available on the C6713 device. TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175) describes the functionality of the I2C peripherals available on the C6713 device. The PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) focuses on the specifics of integrating a PowerPAD package into the printed circuit board design to make optimum use of the thermal efficiencies designed into the PowerPAD package. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The Migrating from TMS320C6211(B)/C6711(B) to TMS320C6713 application report (literature number SPRA851) indicates the differences and describes the issues of interest related to the migration from the Texas Instruments TMS320C6211(B)/C6711(B), GFN package, to the TMS320C6713, GDP package. The TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191) describes the known exceptions to the functional specifications for particular silicon revisions of the TMS320C6713 device. The TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A2 or later) discusses the power consumption for user applications with the TMS320C6713B, TMS320C6712D, and TMS320C6711D DSP devices. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the application report How To Begin Development Today With the TMS320C6713 Floating-Point DSP (literature number SPRA809), which describes in more detail the similarities/differences between the C6713 and C6711 C6000 DSP devices. C62x is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 67 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 CPU CSR register description The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16-31) as well as the status of the device power-down modes [PWRD field (bits 15-10)], program and data cache control modes, the endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 13 and Table 24 identify the bit fields in the CPU CSR register. For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). 31 24 23 15 16 CPU ID REVISION ID R-0x02 R-0x03 10 9 8 7 6 PWRD SAT EN PCC R/W-0 R/C-0 R-1 R/W-0 5 4 2 1 0 DCC PGIE GIE R/W-0 R/W-0 R/W-0 Legend: R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after reset, C = Clearable by the MVC instruction Figure 13. CPU Control Status Register (CPU CSR) 68 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 CPU CSR register description (continued) Table 24. CPU CSR Register Bit Field Description BIT # NAME 31:24 CPU ID 23:16 REVISION ID DESCRIPTION CPU ID + REV ID. Read only. Identifies which CPU is used and defines the silicon revision of the CPU. CPU ID + REVISION ID (31:16) are combined for a value of 0x0203 Control power-down modes. The values are always read as zero. 15:10 9 8 PWRD 000000 001001 010001 011010 011100 Others = = = = = = no power-down (default) PD1, wake-up by an enabled interrupt PD1, wake-up by an enabled or not enabled interrupt PD2, wake-up by a device reset PD3, wake-up by a device reset Reserved SAT Saturate bit. Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false. EN Endian bit. This bit is read-only. Depicts the device endian mode. 0 = Big Endian mode. 1 = Little Endian mode [default]. 7:5 PCC Program Cache control mode. L1D, Level 1 Program Cache 000/010 = Cache Enabled / Cache accessed and updated on reads. All other PCC values reserved. 4:2 DCC Data Cache control mode. L1D, Level 1 Data Cache 000/010 = Cache Enabled / 2-Way Cache All other DCC values reserved Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is taken. Allows for proper nesting of interrupts. 1 PGIE 0 = Previous GIE value is 0. (default) 1 = Previous GIE value is 1. Global interrupt enable bit. Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt). 0 GIE 0 = Disables all interrupts (except the reset interrupt and NMI) [default] 1 = Enables all interrupts (except the reset interrupt and NMI) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 69 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 interrupts and interrupt selector The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4-15) are maskable and default to the interrupt source listed in Table 25. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 26 (Interrupt Selector). Table 26 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts 4-15 is made by programming the corresponding fields (listed in Table 25) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers. 70 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 25. DSP Interrupts Table 26. Interrupt Selector DSP INTERRUPT NUMBER INTERRUPT SELECTOR CONTROL REGISTER DEFAULT SELECTOR VALUE (BINARY) DEFAULT INTERRUPT EVENT INTERRUPT SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00 - - RESET 00000 DSPINT HPI INT_01 - - NMI 00001 TINT0 Timer 0 INT_02 - - Reserved 00010 TINT1 Timer 1 Reserved GPINT4 00011 00100 SDINT GPINT4 GPINT5 GPIO INT_03 - - INT_04 MUXL[4:0] 00100 INT_05 MUXL[9:5] 00101 INT_06 MUXL[14:10] INT_07 MODULE EMIF 00101 00110 GPINT5 GPINT6 MUXL[20:16] 00111 GPINT7 00111 INT_08 MUXL[25:21] 01000 EDMAINT 01000 EDMAINT EDMA INT_09 MUXL[30:26] 01001 EMUDTDMA 01001 EMUDTDMA Emulation INT_10 MUXH[4:0] 00011 SDINT 01010 EMURTDXRX Emulation INT_11 MUXH[9:5] 01010 EMURTDXRX 01011 EMURTDXTX Emulation INT_12 MUXH[14:10] 01011 EMURTDXTX 01100 XINT0 McBSP0 INT_13 MUXH[20:16] 00000 DSPINT 01101 RINT0 McBSP0 INT_14 MUXH[25:21] 00001 TINT0 01110 XINT1 McBSP1 INT_15 MUXH[30:26] 00010 TINT1 00110 GPINT6 GPINT7 GPIO GPIO GPIO 01111 RINT1 McBSP1 10000 GPINT0 GPIO 10001 Reserved - 10010 Reserved - 10011 Reserved - 10100 Reserved - 10101 Reserved - 10110 I2CINT0 I2C0 10111 I2CINT1 I2C1 11000 Reserved - 11001 Reserved - 11010 Reserved - 11011 Reserved - 11100 AXINT0 McASP0 11101 ARINT0 McASP0 11110 AXINT1 McASP1 11111 ARINT1 McASP1 Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 71 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 external interrupt sources The C6713 device supports many external interrupt sources as indicated in Table 27. Control of the interrupt source is done by the associated module and is made available by enabling the corresponding binary interrupt selector value (see Table 26 Interrupt Selector shaded rows). Due to pin muxing and module usage, not all external interrupt sources are available at the same time. Table 27. External Interrupt Sources and Peripheral Module Control 72 PIN NAME INTERRUPT EVENT MODULE GP[15] GPINT0 GPIO GP[14] GPINT0 GPIO GP[13] GPINT0 GPIO GP[12] GPINT0 GPIO GP[11] GPINT0 GPIO GP[10] GPINT0 GPIO GP[9] GPINT0 GPIO GP[8] GPINT0 GPIO GP[7] GPINT0 or GPINT7 GPIO GP[6] GPINT0 or GPINT6 GPIO GP[5] GPINT0 or GPINT5 GPIO GP[4] GPINT0 or GPINT4 GPIO GP[3] GPINT0 GPIO GP[2] GPINT0 GPIO GP[1] GPINT0 GPIO GP[0] GPINT0 GPIO POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 EDMA module and EDMA selector The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8-11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 29). By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 28 lists the default EDMA selector value for each EDMA channel. See Table 30 and Table 31 for the EDMA Event Selector registers and their associated bit descriptions. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 73 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 EDMA module and EDMA selector (continued) Table 28. EDMA Channels Table 29. EDMA Selector EDMA CHANNEL EDMA SELECTOR CONTROL REGISTER DEFAULT SELECTOR VALUE (BINARY) DEFAULT EDMA EVENT EDMA SELECTOR CODE (BINARY) EDMA EVENT MODULE 0 ESEL0[5:0] 000000 DSPINT 000000 DSPINT HPI 1 ESEL0[13:8] 000001 TINT0 000001 TINT0 TIMER0 2 ESEL0[21:16] 000010 TINT1 000010 TINT1 TIMER1 3 ESEL0[29:24] 000011 SDINT 000011 SDINT EMIF 4 ESEL1[5:0] 000100 GPINT4 000100 GPINT4 GPIO 5 ESEL1[13:8] 000101 GPINT5 000101 GPINT5 GPIO 6 ESEL1[21:16] 000110 GPINT6 000110 GPINT6 GPIO 7 ESEL1[29:24] 000111 GPINT7 000111 GPINT7 GPIO 8 - - TCC8 (Chaining) 001000 GPINT0 GPIO 9 - - TCC9 (Chaining) 001001 GPINT1 GPIO 10 - - TCC10 (Chaining) 001010 GPINT2 GPIO 11 - - TCC11 (Chaining) 001011 GPINT3 GPIO 12 ESEL3[5:0] 001100 XEVT0 001100 XEVT0 McBSP0 13 ESEL3[13:8] 001101 REVT0 001101 REVT0 McBSP0 14 ESEL3[21:16] 001110 XEVT1 001110 XEVT1 McBSP1 15 ESEL3[29:24] 001111 REVT1 001111 REVT1 010000-011111 100000 AXEVTE0 McASP0 100001 AXEVTO0 McASP0 100010 AXEVT0 McASP0 100011 AREVTE0 McASP0 100100 AREVTO0 McASP0 100101 AREVT0 McASP0 100110 AXEVTE1 McASP1 100111 AXEVTO1 McASP1 101000 AXEVT1 McASP1 101001 AREVTE1 McASP1 101010 AREVTO1 McASP1 101011 AREVT1 McASP1 101100 I2CREVT0 I2C0 101101 I2CXEVT0 I2C0 101110 I2CREVT1 I2C1 101111 I2CXEVT1 I2C1 110000 GPINT8 GPIO 110001 GPINT9 GPIO 110010 GPINT10 GPIO 110011 GPINT11 GPIO 110100 GPINT12 GPIO 110101 GPINT13 GPIO 110110 GPINT14 GPIO 110111 GPINT15 GPIO 111000-111111 74 POST OFFICE BOX 1443 McBSP1 Reserved * HOUSTON, TEXAS 77251-1443 Reserved SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 EDMA module and EDMA selector (continued) Table 30. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3) ESEL0 Register (0x01A0 FF00) 30 31 29 28 27 24 23 22 21 20 19 Reserved EVTSEL3 Reserved EVTSEL2 R-0 R/W-00 0011b R-0 R/W-00 0010b 14 15 13 12 11 8 7 6 5 4 16 0 3 Reserved EVTSEL1 Reserved EVTSEL0 R-0 R/W-00 0001b R-0 R/W-00 0000b Legend: R = Read only, R/W = Read/Write; -n = value after reset ESEL1 Register (0x01A0 FF04) 30 31 29 28 27 24 23 22 21 20 19 Reserved EVTSEL7 Reserved EVTSEL6 R-0 R/W-00 0111b R-0 R/W-00 0110b 14 15 13 12 11 8 6 5 7 4 16 0 3 Reserved EVTSEL5 Reserved EVTSEL4 R-0 R/W-00 0101b R-0 R/W-00 0100b Legend: R = Read only, R/W = Read/Write; -n = value after reset ESEL3 Register (0x01A0 FF0C) 30 31 29 28 27 24 23 22 21 20 19 Reserved EVTSEL15 Reserved EVTSEL14 R-0 R/W-00 1111b R-0 R/W-00 1110b 14 15 13 12 11 8 7 6 5 4 16 3 0 Reserved EVTSEL13 Reserved EVTSEL12 R-0 R/W-00 1101b R-0 R/W-00 1100b Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 31. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description BIT # NAME 31:30 23:22 15:14 7:6 Reserved DESCRIPTION Reserved. Read-only, writes have no effect. EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels. 29:24 21:16 13:8 5:0 EVTSELx The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These EVTSELx fields are user-selectable. By configuring the EVTSELx fields to the EDMA selector value of the desired EDMA sync event number (see Table 29), users can map any EDMA event to the EDMA channel. For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then channel 15 is triggered by Timer0 TINT0 events. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 75 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller The TMS320C6713 includes a PLL and a flexible PLL Controller peripheral consisting of a prescaler (D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other peripherals). Figure 14 illustrates the PLL, the PLL controller, and the clock generator logic. PLLHV +3.3 V C1 EMI filter 10 F C2 0.1 F CLKMODE0 PLLOUT CLKIN PLLREF DIVIDER D0 1 0 Reserved /1, /2, ..., /32 ENA PLLEN (PLL_CSR.[0]) PLL x4 to x25 1 0 D1EN (PLLDIV1.[15]) D0EN (PLLDIV0.[15]) OSCDIV1 CLKOUT3 For Use in System D2EN (PLLDIV2.[15]) /1, /2, ..., /32 ENA OD1EN (OSCDIV1.[15]) AUXCLK (Internal Clock Source to McASP0 and McASP1) D3EN (PLLDIV3.[15]) DIVIDER D1 /1, /2, ..., /32 ENA SYSCLK1 (DSP Core) DIVIDER D2 /1, /2, ..., /32 ENA SYSCLK2 (Peripherals) DIVIDER D3 /1, /2, ..., /32 SYSCLK3 ENA ECLKIN (EMIF Clock Input) 1 0 EKSRC Bit (DEVCFG.[4]) EMIF C6713 DSP ECLKOUT Dividers D1 and D2 must never be disabled. Never write a "0" to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers. NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 14. PLL and Clock Generator Logic 76 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller (continued) The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time value, see Table 32. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL out of reset, but still bypassed) to when the PLLEN bit can be safely changed to "1" (switching from bypass to the PLL path), see Table 32 and Figure 14. Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For the PLL Lock Time values, see Table 32. Table 32. PLL Lock and Reset Times MIN PLL Lock Time PLL Reset Time TYP MAX UNIT 75 187.5 s 125 ns Table 33 shows the C6713 device's CLKOUT signals, how they are derived and by what register control bits, and what is the default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram (Figure 14). Table 33. CLKOUT Signals, Default Settings, and Control CLOCK OUTPUT SIGNAL NAME DEFAULT SETTING (ENABLED or DISABLED) CONTROL BIT(s) (Register) CLKOUT2 ON (ENABLED) D2EN = 1 (PLLDIV2.[15]) CK2EN = 1 (EMIF GBLCTL.[3]) CLKOUT3 ON (ENABLED) OD1EN = 1 (OSCDIV1.[15]) DESCRIPTION SYSCLK2 selected [default] Derived from CLKIN SYSCLK3 selected [default]. ECLKOUT ON (ENABLED); derived from SYSCLK3 EKSRC = 0 (DEVCFG.[4]) EKEN = 1 (EMIF GBLCTL.[5]) To select ECLKIN source: EKSRC = 1 (DEVCFG.[4]) and EKEN = 1 (EMIF GBLCTL.[5]) The input clock (CLKIN) is directly available to the McASP modules as AUXCLK for use as an internal high-frequency clock source. The input clock (CLKIN) may also be divided down by a programmable divider OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system. Figure 14 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then multiplied up by a factor of x4, x5, x6, and so on, up to x25. Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may be divided down from this high-frequency clock (each with a unique divider) . For example, with a 30 MHz input if the PLL output is configured for 450 MHz, the DSP core may be operated at 225 MHz (/2) while the EMIF may be configured to operate at a rate of 75 MHz (/6). Note that there is a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 14, as well as for the DSP core, peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 34 for the PLL clocks input and output frequency ranges. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 77 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 34. PLL Clock Frequency Ranges 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 CLOCK SIGNAL UNIT MIN MAX PLLREF (PLLEN = 1) 12 100 MHz PLLOUT 140 600 MHz SYSCLK1 - Device Speed (DSP Core) MHz SYSCLK3 (EKSRC = 0) - MHz AUXCLK - 100 50 MHz SYSCLK2 rate must be exactly half of SYSCLK1. Also see the electrical specification (timing requirements and switching characteristics parameters) in the input and output clocks section of this data sheet. When the McASP module is not used, the AUXCLK maximum frequency can be any frequency up to the CLKIN maximum frequency. The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 14, PLL and Clock Generator Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register. The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233). SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 14). During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output clocks, see Figure 14), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1 and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final SYSCLK2 rate must be exactly half of the SYSCLK1 rate. Note that Divider D1 and Divider D2 must always be enabled (i. e., D1EN and D2EN bits are set to "1" in the PLLDIV1 and PLLDIV2 registers). The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be used to directly access the PLL Controller registers. For detailed information on the clock generator (PLL Controller registers) and their associated software bit descriptions, see Table 36 through Table 42. 78 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 35. PLL Control/Status Register (PLLCSR) [0x01B7 C100] 28 31 24 27 23 20 19 16 Reserved R-0 15 12 11 8 7 6 5 4 3 2 1 0 Reserved STABLE Reserved PLLRST Reserved PLLPWRDN PLLEN R-0 R-x R-0 RW-1 R/W-0 R/W-0b RW-0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 36. PLL Control/Status Register (PLLCSR) Description BIT # NAME 31:7 Reserved Reserved. Read-only, writes have no effect. 6 STABLE Clock Input Stable. This bit indicates if the clock input has stabilized. 0 - Clock input not yet stable. Clock counter is not finished counting (default). 1 - Clock input stable. 5:4 Reserved Reserved. Read-only, writes have no effect. 3 PLLRST Asserts RESET to PLL 0 - PLL Reset Released. 1 - PLL Reset Asserted (default). 2 Reserved Reserved. The user must write a "0" to this bit. 1 PLLPWRDN 0 PLLEN DESCRIPTION Select PLL Power Down 0 - PLL Operational (default). 1 - PLL Placed in Power-Down State. PLL Mode Enable 0 - Bypass Mode (default). PLL disabled. Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock. 1 - PLL Enabled. Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down from PLL output. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 79 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 37. PLL Multiplier Control Register (PLLM) [0x01B7 C110] 24 23 28 27 31 20 19 16 Reserved R-0 15 12 11 8 7 6 5 4 3 2 Reserved PLLM R-0 R/W-0 0111 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 38. PLL Multiplier Control Register (PLLM) Description BIT # NAME 31:5 Reserved 4:0 PLLM DESCRIPTION Reserved. Read-only, writes have no effect. PLL multiply mode [default is x7 (0 0111)]. 00000 = Reserved 10000 = 00001 = Reserved 10001 = 00010 = Reserved 10010 = 00011 = Reserved 10011 = 00100 = x4 10100 = 00101 = x5 10101 = 00110 = x6 10110 = 00111 = x7 10111 = 01000 = x8 11000 = 01001 = x9 11001 = 01010 = x10 11010 = 01011 = x11 11011 = 01100 = x12 11100 = 01101 = x13 11101 = 01110 = x14 11110 = 01111 = x15 11111 = x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 Reserved Reserved Reserved Reserved Reserved Reserved PLLM select values 00000 through 00011 and 11010 through 11111 are not supported. 80 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 0 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 39. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3) [0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively] 28 31 24 27 23 20 19 16 Reserved R-0 14 15 12 11 8 7 5 4 3 2 DxEN Reserved PLLDIVx R/W-1 R-0 R/W-x xxxx 1 0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively. CAUTION: D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used. Table 40. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1, D2, and D3) Description BIT # NAME 31:16 Reserved 15 DxEN 14:5 Reserved DESCRIPTION Reserved. Read-only, writes have no effect. Divider Dx Enable (where x denotes 0 through 3). 0 - Divider x Disabled. No clock output. 1 - Divider x Enabled (default). These divider-enable bits are device-specific and must be set to 1 to enable. Reserved. Read-only, writes have no effect. PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1, /2, and /2, respectively]. 4:0 PLLDIVx 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 = = = = = = = = = = = = = = = = /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 /12 /13 /14 /15 /16 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 = = = = = = = = = = = = = = = = /17 /18 /19 /20 /21 /22 /23 /24 /25 /26 /27 /28 /29 /30 /31 /32 Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example, if D1 is set to /2, then D2 must be set to /4. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 81 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 41. Oscillator Divider 1 Register (OSCDIV1) [0x01B7 C124] 24 23 28 27 31 20 19 16 Reserved R-0 15 14 12 11 8 7 5 4 3 2 OD1EN Reserved OSCDIV1 R/W-1 R-0 R/W-0 0111 1 0 Legend: R = Read only, R/W = Read/Write; -n = value after reset The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through the PLL path. Table 42. Oscillator Divider 1 Register (OSCDIV1) Description BIT # NAME 31:16 Reserved 15 OD1EN 14:5 Reserved DESCRIPTION Reserved. Read-only, writes have no effect. Oscillator Divider 1 Enable. 0 - Oscillator Divider 1 Disabled. 1 - Oscillator Divider 1 Enabled (default). Reserved. Read-only, writes have no effect. Oscillator Divider 1 Ratio [default is /8 (0 0111)]. 4:0 82 OSCDIV1 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 = = = = = = = = = = = = = = = = /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 /12 /13 /14 /15 /16 POST OFFICE BOX 1443 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 = = = = = = = = = = = = = = = = /17 /18 /19 /20 /21 /22 /23 /24 /25 /26 /27 /28 /29 /30 /31 /32 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 multichannel audio serial port (McASP) peripherals The TMS320C6713 device includes two multi-channel audio serial port (McASP) interface peripherals (McASP1 and McASP0). The McASP is a serial port optimized for the needs of multi-channel audio applications. With two McASP peripherals, the TMS320C6713 device is capable of supporting two completely independent audio zones simultaneously. Each McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. Each McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO). The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format. Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data (for example, passing control information between two DSPs). The McASP peripherals have additional capability for flexible clock generation, and error detection/handling, as well as error management. McASP block diagram Figure 15 illustrates the major blocks along with external signals of the TMS320C6713 McASP1 and McASP0 peripherals; and shows the 8 serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 83 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 multichannel audio serial port (McASP) peripherals (continued) McASP0 McASP1 Transmit Clock Check (HighFrequency) Transmit Clock Generator Receive Clock Check (HighFrequency) Receive Clock Generator Transmit Data Formatter Receive Frame Sync Generator Receive Data Formatter Transmit Frame Sync Generator AHCLKX0 ACLKX0 Transmit Clock Check (HighFrequency) Transmit Clock Generator AMUTE0 AMUTEIN0 Error Detect AHCLKR0 ACLKR0 Receive Clock Check (HighFrequency) Receive Clock Generator Transmit Data Formatter Receive Frame Sync Generator AFSR0 Serializer 0 AXR0[0] Serializer 1 AXR0[1] Serializer 2 AXR0[2] Serializer 3 AXR0[3] Serializer 4 AXR0[4] Serializer 5 AXR0[5] Serializer 6 AXR0[6] Serializer 7 AXR0[7] GPIO Control DMA Receive DMA Receive INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO DMA Transmit Error Detect DIT RAM AFSX0 INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO Transmit Frame Sync Generator DMA Transmit DIT RAM POST OFFICE BOX 1443 AHCLKX1 ACLKX1 AMUTE1 AMUTEIN1 AHCLKR1 ACLKR1 AFSR1 Serializer 0 AXR1[0] Serializer 1 AXR1[1] Serializer 2 AXR1[2] Serializer 3 AXR1[3] Serializer 4 AXR1[4] Serializer 5 AXR1[5] Serializer 6 AXR1[6] Serializer 7 AXR1[7] Receive Data Formatter Figure 15. McASP0 and McASP1 Configuration 84 AFSX1 * HOUSTON, TEXAS 77251-1443 GPIO Control SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 multichannel audio serial port (McASP) peripherals (continued) multichannel time division multiplexed (TDM) synchronous transfer mode The McASP supports a multichannel, time-division-multiplexed (TDM) synchronous transfer mode for both transmit and receive. Within this transfer mode, a wide variety of serial data formats are supported, including formats compatible with devices using the Inter-Integrated Sound (IIS) protocol. TDM synchronous transfer mode is typically used when communicating between integrated circuits such as between a DSP and one or more ADC, DAC, CODEC, or S/PDIF receiver devices. In multichannel applications, it is typical to find several devices operating synchronized with each other. For example, to provide six analog outputs, three stereo DAC devices would be driven with the same bit clock and frame sync, but each stereo DAC would use a different McASP serial data pin carrying stereo data (2 TDM time slots, left and right). The TDM synchronous serial transfer mode utilizes several control signals and one or more serial data signals: D A bit clock signal (ACLKX for transmit, ACKLR for receive) D A frame sync signal (AFSX for transmit, AFSR for receive) D An (Optional) high frequency master clock (AHCLKX for transmit, AHCLKR for receive) from which the bit clock is derived D One or more serial data pins (AXR for transmit and for receive). Except for the optional high-frequency master clock, all of the signals in the TDM synchronous serial transfer mode protocol are synchronous to the bit clocks (ACLKX and ACLKR). In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically (since audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames, and the beginning of a frame is marked by a frame sync pulse on the AFSX, AFSR pin. In a typical audio system, one frame is transferred per sample period. To support multiple channels, the choices are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit clock period constant and use additional data pins to transfer the same number of channels. For example, a particular six-channel DAC might require three McASP serial data pins; transferring two channels of data on each serial data pin during each sample period (frame). Another similar DAC may be designed to use only a single McASP serial data pin, but clocked three times faster and transferring six channels of data per sample period. The McASP is flexible enough to support either type of DAC but a transmitter cannot be configured to do both at the same time. For multiprocessor applications, the McASP supports any number of time slots per frame (between 2 and 32), and includes the ability to "disable" transfers during specific time slots. In addition, to support of S/PDIF, AES-3, IEC-60958, CP-430 receivers chips whose natural block (McASP frame) size is 384 samples; the McASP receiver supports a 384 time slot mode. The advantage to using the 384 time slot mode is that interrupts may be generated synchronous to the S/PDIF, AES-3, IEC-60958, CP-430 receivers, for example the "last slot" interrupt. burst transfer mode The McASP also supports a burst transfer mode, which is useful for non-audio data (for example, passing control information between two DSPs). Burst transfer mode uses a synchronous serial format similar to TDM, except the frame sync is generated for each data word transferred. In addition, frame sync generation is not periodic or time-driven as in TDM mode but rather data-driven. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 85 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 multichannel audio serial port (McASP) peripherals (continued) supported bit stream formats for TDM and burst transfer modes The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data may be transmitted / received with the following options: D D D D D D D Time slots per frame: 1 (Burst/Data Driven), or 2,3...32 (TDM/Time-Driven). Time slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot Data size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot) Data alignment within time slot: Left- or Right-Justified Bit order: MSB or LSB first. Unused bits in time slot: Padded with 0, 1 or extended with value of another bit. Time slot delay from frame sync: 0,1, or 2 bit delay The data format can be programmed independently for transmit and receive, and for McASP0 vs. McASP1. In addition, the McASP can automatically re-align the data as processed natively by the DSP (any format on a nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (TDM, Burst, and DIT modes). This reduces the amount of bit manipulation that the DSP must perform and simplifies software architecture. digital audio interface transmitter (DIT) transfer mode (transmitter only) The McASP transmit section may also be configured in digital audio interface transmitter (DIT) mode where it outputs data formatted for transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These standards encode the serial data such that the equivalent of 'clock' and 'frame sync' are embedded within the data stream. DIT transfer mode is used as an interconnect between audio components and can transfer multichannel digital audio data over a single optical or coaxial cable. From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two time slot TDM mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status, user data, validity, and parity automatically stuffed into the bit stream by the McASP module. The McASP includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel status and user data bits. DIT mode requires at minimum: D One serial data pin (if the AUXCLK is used as the reference [see the PLL and Clock Generator Logic Figure 14]) or D One serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed). If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams (one per pin). However, the bit streams will all be synchronized to the same clock and the user data, channel status, and validity information carried by each bit stream will be the same for all bit streams transmitted by the same McASP module. The McASP can also automatically re-align the data as processed by the DSP (any format on a nibble boundary) in DIT mode; reducing the amount of bit manipulation that the DSP must perform and simplifies software architecture. 86 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 multichannel audio serial port (McASP) peripherals (continued) McASP flexible clock generators The McASP transmit and receive clock generators are identical. Each clock generator can accept a high-frequency master clock input (on the AHCLKX and AHCLKR pins). The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or can be sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ... /4096). The polarity of each bit clock is individually programmable. The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry the left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are individually programmable for either internal or external generation, either bit or slot length, and either rising or falling edge polarity. Some examples of the things that a system designer can use the McASP clocking flexibility for are: D Input a high-frequency master clock (for example, 512fs of the receiver), receive with an internally D D generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. [An example application would be to receive data from a DVD at 48 kHz but output up-sampled or decoded audio at 96 kHz or 192 kHz.] Transmit/receive data based one sample rate (for example, 44.1 kHz) using McASP0 while transmitting and receiving at a different sample rate (for example, 48 kHz) on McASP1. Use the DSP's on-board AUXCLK to supply the system clock when the input source is an A/D converter. McASP error handling and management To support the design of a robust audio system, the McASP module includes error-checking capability for the serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually measures the high-frequency master clock every 32-SYSCLK2 clock cycles. The timer value can be read to get a measurement of the high-frequency master clock frequency and has a min-max range setting that can raise an error flag if the high-frequency master clock goes out of a specified range. The user would read the high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by reading the XCNT field of the XCLKCHK register and the user would read the high-frequency receive master clock measurement (AHCLKR0 or AHCLKR1) by reading the RCNT field of the RCLKCHK register. Upon the detection of any one or more of the above errors (software selectable), or the assertion of the AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error sources. McASP interrupts and EDMA events The McASP transmitter and receiver sections each generate an event on every time slot. This event can be serviced by an interrupt or by the EDMA controller. When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP Registers space (see Table 3). When using the EDMA to service the McASP, the McASP DATA Port space in Table 3 is accessed. In this case, the address least-significant bits are ignored. Writes to any address in this range access the transmitting buffers in order from lowest (serializer 0) to highest (serializer 15), skipping over disabled and receiving serializers. Likewise, reads from any address in this space access the receiving buffers in the same order but skip over disabled and transmitting buffers. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 87 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 I2C Having two I2C modules on the TMS320C6713 simplifies system architecture, since one module may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface. The TMS320C6713 also includes two I2C serial ports for control purposes. Each I2C port supports: D D D D D D D Compatible with Philips I 2C Specification Revision 2.1 (January 2000) Fast Mode up to 400 Kbps (no fail-safe I/O buffers) Noise Filter to Remove Noise 50 ns or less Seven- and Ten-Bit Device Addressing Modes Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality Events: DMA, Interrupt, or Polling Slew-Rate Limited Open-Drain Output Buffers Figure 16 is a block diagram of the I2Cx module. I2Cx Module Clock Prescale SYSCLK2 From PLL Clock Generator I2CPSCx SCL Noise Filter I2C Clock Bit Clock Generator Control I2CCLKHx I2COARx Own Address I2CSARx Slave Address I2CMDRx Mode I2CCNTx Data Count I2CCLKLx Transmit I2CXSRx Transmit Shift I2CDXRx Transmit Buffer Interrupt/DMA SDA I2C Data Noise Filter Receive Interrupt Enable I2CDRRx Receive Buffer I2CSTRx Interrupt Status I2CRSRx Receive Shift I2CISRCx Interrupt Source NOTE A: Shading denotes control/status registers. Figure 16. I2Cx Module Block Diagram 88 I2CIERx POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 general-purpose input/output (GPIO) To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured. GPxEN = 1 GP[x] pin is enabled GPxDIR = 0 GP[x] pin is an input GPxDIR = 1 GP[x] pin is an output where "x" represents one of the 15 through 0 GPIO pins Figure 17 shows the GPIO enable bits in the GPEN register for the C6713 device. To use any of the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to "1" (enabled). Default values are device-specific, so refer to Figure 17 for the C6713 default configuration. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 EN GP14 EN GP13 EN GP12 EN GP11 EN GP10 EN GP9 EN GP8 EN GP7 EN GP6 EN GP5 EN GP4 EN GP3 EN GP2 EN GP1 EN GP0 EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset Figure 17. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] Figure 18 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled (set to "1") in the GPEN register. By default, all the GPIO pins are configured as input pins. 31 24 23 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP15 DIR GP14 DIR GP13 DIR GP12 DIR GP11 DIR GP10 DIR GP9 DIR GP8 DIR GP7 DIR GP6 DIR GP5 DIR GP4 DIR GP3 DIR GP2 DIR GP1 DIR GP0 DIR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset Figure 18. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 89 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 power-down mode logic Figure 19 shows the power-down mode logic on the C6713. CLKOUT2 Internal Clock Tree Clock Distribution and Dividers PD1 PD2 PowerDown Logic Clock PLL IFR IER Internal Peripherals PWRD CSR CPU PD3 TMS320C6713 CLKIN RESET External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic. Figure 19. Power-Down Mode Logic triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15-10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 20 and described in Table 43. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when "writing" to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). 90 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 31 16 15 14 13 12 11 10 Reserved Enable or Non-Enabled Interrupt Wake Enabled Interrupt Wake PD3 PD2 PD1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 9 8 0 Legend: R/W-x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 20. PWRD Field of the CSR Register A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 43 summarizes all the power-down modes. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 91 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 43. Characteristics of the Power-Down Modes PRWD FIELD (BITS 15-10) POWER-DOWN MODE WAKE-UP METHOD 000000 No power-down -- -- 001001 PD1 Wake by an enabled interrupt 010001 PD1 Wake by an enabled or non-enabled interrupt 011010 011100 PD2 PD3 EFFECT ON CHIP'S OPERATION CPU halted (except for the interrupt logic) Power-down mode blocks the internal clock inputs at the boundary of the CPU, preventing most of the CPU's logic from switching. During PD1, EDMA transactions can proceed between peripherals and internal memory. Wake by a device reset Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All register and internal RAM contents are preserved. All functional I/O "freeze" in the last state when the PLL clock is turned off. Wake by a device reset Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O "freeze" in the last state when the PLL clock is turned off. Following reset, the PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked, just as it does following power-up. All others Reserved -- -- When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications. On C6713, the device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit in the PLLCSR register. With this enhanced functionality comes some additional considerations when entering power-down modes. The power-down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the device. However, if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input (CLKIN). Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective. Make sure that the PLL is enabled by writing a "1" to PLLEN bit (PLLCSR.0) before writing to either PD3 (CSR.11) or PD2 (CSR.10) to enter a power-down mode. power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. 92 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 power-supply design considerations A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 21). I/O Supply DVDD Schottky Diode C6000 DSP Core Supply CVDD VSS GND Figure 21. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. power-supply decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps -- 30 for the core supply and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product's production lifetime needs to be considered. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 93 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 IEEE 1149.1 JTAG compatibility statement The TMS320C6713 DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP's emulation logic. Both resets are required for proper operation. Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected after TRST is asserted. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP's emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP's boundary scan functionality. The TMS320C6713 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. Note: The DESIGN-WARNING section of the TMS320C6713 BSDL file contains information and constraints regarding proper device operation while in Boundary Scan Mode. For more detailed information on the C6713 JTAG emulation, see the TMS320C6000 DSP Designing for JTAG Emulation Reference Guide (literature number SPRU641). EMIF device speed The maximum EMIF speed on the C6713 device is 100 MHz. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). For ease of design evaluation, Table 44 contains IBIS simulation results showing the maximum EMIF-SDRAM interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be performed to verify that all AC timings are met for the specified board layout. Other configurations are also possible, but again, timing analysis must be done to verify proper AC timings. To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals). 94 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 Table 44. C6713 Example Boards and Maximum EMIF Speed BOARD CONFIGURATION TYPE 1-Load Short Traces 2-Loads Short Traces 3-Loads Short Traces 3-Loads Long Traces EMIF INTERFACE COMPONENTS One bank of one 32-Bit SDRAM One bank of two 16-Bit SDRAMs One bank of two 32-Bit SDRAMs One bank of buffer One bank of one 32-Bit SDRAM One bank of one 32-Bit SBSRAM One bank of buffer SDRAM SPEED GRADE BOARD TRACE 1 to 3-inch traces with proper termination resistors; Trace impedance ~ 50 1.2 to 3 inches from EMIF to each load, with proper termination resistors; Trace impedance ~ 78 1.2 to 3 inches from EMIF to each load, with proper termination resistors; Trace impedance ~ 78 4 to 7 inches from EMIF; Trace impedance ~ 63 MAXIMUM ACHIEVABLE EMIF-SDRAM INTERFACE SPEED 143 MHz 32-bit SDRAM (-7) 100 MHz 166 MHz 32-bit SDRAM (-6) 200 MHz 32-bit SDRAM (-5) For short traces, SDRAM data output hold time on these SDRAM speed grades cannot meet EMIF input hold time requirement (see NOTE 1). 125 MHz 16-bit SDRAM (-8E) 100 MHz 133 MHz 16-bit SDRAM (-75) 100 MHz 143 MHz 16-bit SDRAM (-7E) 100 MHz 167 MHz 16-bit SDRAM (-6A) 100 MHz 167 MHz 16-bit SDRAM (-6) 100 MHz 125 MHz 16-bit SDRAM (-8E) For short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE 1). 133 MHz 16-bit SDRAM (-75) 100 MHz 143 MHz 16-bit SDRAM (-7E) 100 MHz 167 MHz 16-bit SDRAM (-6A) 100 MHz 167 MHz 16-bit SDRAM (-6) For short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE 1). 143 MHz 32-bit SDRAM (-7) 83 MHz 166 MHz 32-bit SDRAM (-6) 83 MHz 183 MHz 32-bit SDRAM (-55) 83 MHz 200 MHz 32-bit SDRAM (-5) SDRAM data output hold time cannot meet EMIF input hold requirement (see NOTE 1). 183 MHz 32-bit SDRAM (-55) NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing requirements can be met for the particular system. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 95 SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 bootmode The C6713 device resets using the active-low signal RESET and the internal reset signal. While RESET is low, the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of the internal reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts the processor running with the prescribed device configuration and boot mode. The C6713 has three types of boot modes: D Host boot If host boot is selected, upon release of internal reset, the CPU is internally "stalled" while the remainder of the device is released. During this period, an external host can initialize the CPU's memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the "stalled" state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received. D Emulation boot Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to set DSPINT to release the CPU from the "stalled" state. Instead, the emulator will set DSPINT if it has not been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution, the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development. D EMIF boot (using default ROM timings) Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally "stalled". The data should be stored in the endian format that the system is using. The boot process also lets you choose the width of the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the "stalled" state and start running from address 0. reset A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency. 96 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 absolute maximum ratings over operating case temperature range (unless otherwise noted) Supply voltage range, CVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 1.8 V Supply voltage range, DVDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Operating case temperature ranges, TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A version) [GDPA-200, and PYPA-167] . . . . . . -40_C to105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: All voltage values are with respect to VSS. recommended operating conditions PYP packages only CVDD Supply voltage, Core referenced to VSS DVDD Supply voltage, I/O referenced to VSS VIH High-level input voltage GDP packages only MIN NOM MAX UNIT 1.14 1.14 1.20 1.20 1.32 V 1.32 V 3.13 3.3 3.47 V All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 V CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 V All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET VIL IOH Low-level input voltage High-level output current CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 0.8 V 0.3*DVDD V -8 mA -16 mA 8 mA ECLKOUT, CLKOUT2, and CLKOUT3 16 mA CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3 mA ECLKOUT, CLKOUT2, and CLKOUT3 All signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 IOL VOS VUS Low-level output current 4 -0.7 Maximum voltage during overshoot (See Figure 25) Maximum voltage during undershoot (See Figure 26) Default TC Operating case temperature A version (GDPA-200 and PYPA-167) 0 90 -40 105 V V _C The core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. These values are compatible with existing 1.26-V designs. Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models. The absolute maximum ratings should not be exceeded for more than 30% of the cycle period. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 97 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage II Input current TEST CONDITIONS MIN TYP IDD2V Off-state output current IOH =MAX All signals except SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V 170 uA 10 uA 170 uA 10 uA All signals except SCL1, SDA1, SCL0, and SDA0 All signals except SCL1, SDA1, SCL0, and SDA0 2.4 V VI = VSS to DVDD I/O supply current Ci Input capacitance VO = DVDD or 0 V SCL1, SDA1, SCL0, and SDA0 Core supply current IDD3V UNIT All signals except SCL1, SDA1, SCL0, and SDA0 SCL1, SDA1, SCL0, and SDA0 IOZ MAX GDP, CVDD = 1.26 V, CPU clock = 225 MHz 625 mA GDPA, CVDD = 1.26 V, CPU clock = 200 MHz 560 mA PYP, CVDD =1.2 , CPU clock = 200 MHz 565 mA PYPA, CVDD = 1.2 V, CPU clock = 167 MHz 480 mA 75 mA DVDD = 3.3 V, EMIF speed = 100 MHz 7 pF Co Output capacitance 7 pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. Measured with average activity (50% high/50% low power) at 25C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows: High-DSP-Activity Model: CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions; L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate Low-DSP-Activity Model: CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A2 or later). 98 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION Tester Pin Electronics 42 W Data Sheet Timing Reference Point Output Under Test 3.5 nH Transmission Line Z0 = 50 W (see note) 4.0 pF Device Pin (see note) 1.85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 22. Test Load Circuit for AC Timing Measurements signal transition levels All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels. Vref = 1.5 V Figure 23. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 24. Rise and Fall Transition Time Voltage Reference Levels POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 99 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) AC transient rise/fall time specifications Figure 25 and Figure 26 show the AC transient specifications for Rise and Fall Time. For device-specific information on these values, refer to the Recommended Operating Conditions section of this Data Sheet. t = 0.3 tc (max) VOS (max) Minimum Risetime VIH (min) Waveform Valid Region Ground Figure 25. AC Transient Specification Rise Time tc = the peripheral cycle time. t = 0.3 tc(max) VIL (max) VUS (max) Ground Figure 26. AC Transient Specification Fall Time tc = the peripheral cycle time. 100 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 45 and Figure 27). Figure 27 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 101 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) Table 45. Board-Level Timings Example (see Figure 27) NO. DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP setup time requirement 11 Data route delay ECLKOUT (Output from DSP) 1 ECLKOUT (Input to External Device) Control Signals (Output from DSP) 2 3 4 5 Control Signals (Input to External Device) 6 7 Data Signals (Output from External Device) 8 10 9 11 Data Signals (Input to DSP) Control signals include data for Writes. Data signals are generated during Reads from an external device. Figure 27. Board-Level Input/Output Timings 102 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN for PYP-200 and GDP-225 (see Figure 28) PYP-200 PLL MODE (PLLEN = 1) NO. 1 2 3 4 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low GDP-225 BYPASS MODE (PLLEN = 0) BYPASS MODE (PLLEN = 0) UNIT MIN MAX MIN MIN MAX MIN 5 83.3 6.7 4.4 83.3 6.7 ns 0.4C 0.4C 0.4C 0.4C ns 0.4C 0.4C 0.4C 0.4C Transition time, CLKIN MAX PLL MODE (PLLEN = 1) 5 5 5 MAX ns 5 ns The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. See the PLL and PLL controller section of this data sheet. timing requirements for CLKIN for PYPA-167 and GDPA-200 (see Figure 28) PYPA-167 PLL MODE (PLLEN = 1) NO. 1 2 3 GDPA-200 BYPASS MODE (PLLEN = 0) MIN MAX 6 83.3 MIN MAX PLL MODE (PLLEN = 1) MIN MAX 83.3 BYPASS MODE (PLLEN = 0) MIN UNIT MAX tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 6.7 5 6.7 ns Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns 4 Transition time, CLKIN 5 5 5 The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. See the PLL and PLL controller section of this data sheet. 1 5 ns 4 2 CLKIN 3 4 Figure 28. CLKIN Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 103 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 29) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 1 2 3 4 UNIT MAX tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 C2 - 0.8 C2 + 0.8 ns Pulse duration, CLKOUT2 high (C2/2) - 0.8 (C2/2) + 0.8 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low (C2/2) - 0.8 (C2/2) + 0.8 ns Transition time, CLKOUT2 2 ns The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period divide-by-2. 1 4 2 CLKOUT2 3 4 Figure 29. CLKOUT2 Timings switching characteristics over recommended operating conditions for CLKOUT3 (see Figure 30) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 1 2 3 4 UNIT MAX tc(CKO3) tw(CKO3H) Cycle time, CLKOUT3 C3 - 0.6 C3 + 0.6 ns Pulse duration, CLKOUT3 high (C3/2) - 0.6 (C3/2) + 0.6 ns tw(CKO3L) tt(CKO3) Pulse duration, CLKOUT3 low (C3/2) - 0.6 (C3/2) + 0.6 ns 2 ns Transition time, CLKOUT3 5 td(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid 1.5 6.5 ns The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register. For more details, see PLL and PLL controller. CLKIN 5 1 5 4 3 CLKOUT3 2 4 NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2. Figure 30. CLKOUT3 Timings 104 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN (see Figure 31) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 2 3 UNIT MAX tc(EKI) tw(EKIH) Cycle time, ECLKIN 10 ns Pulse duration, ECLKIN high 4.5 ns tw(EKIL) tt(EKI) Pulse duration, ECLKIN low 4.5 ns 4 Transition time, ECLKIN The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 3 ns 4 2 ECLKIN 3 4 Figure 31. ECLKIN Timings switching characteristics over recommended operating conditions for ECLKOUT# (see Figure 32) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 1 2 3 4 5 UNIT MAX tc(EKO) tw(EKOH) Cycle time, ECLKOUT E - 0.9 E + 0.9 ns Pulse duration, ECLKOUT high EH - 0.9 EH + 0.9 ns tw(EKOL) tt(EKO) Pulse duration, ECLKOUT low EL - 0.9 EL + 0.9 ns 2 ns td(EKIH-EKOH) td(EKIL-EKOL) Delay time, ECLKIN high to ECLKOUT high 1 6.5 ns 1 6.5 ns Transition time, ECLKOUT 6 Delay time, ECLKIN low to ECLKOUT low The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = ECLKIN period in ns EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns. ECLKIN 6 1 2 5 3 4 4 ECLKOUT Figure 32. ECLKOUT Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 105 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 33-Figure 34) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 3 4 6 UNIT MAX tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high 6.5 ns Hold time, EDx valid after ARE high 1 ns tsu(ARDY-EKOH) th(EKOH-ARDY) Setup time, ARDY valid before ECLKOUT high 3 ns 7 Hold time, ARDY valid after ECLKOUT high 2.3 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns switching characteristics over recommended operating conditions for asynchronous memory cycles (see Figure 33-Figure 34) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 1 2 5 8 9 10 11 UNIT MAX tosu(SELV-AREL) toh(AREH-SELIV) Output setup time, select signals valid to ARE low RS*E - 1.7 ns Output hold time, ARE high to select signals invalid RH*E - 1.7 ns td(EKOH-AREV) tosu(SELV-AWEL) Delay time, ECLKOUT high to ARE valid Output setup time, select signals valid to AWE low WS*E - 1.7 ns toh(AWEH-SELIV) td(EKOH-AWEV) Output hold time, AWE high to select signals and EDx invalid WH*E - 1.7 ns tosu(EDV-AWEL) Delay time, ECLKOUT high to AWE valid Output setup time, ED valid to AWE low 1.5 1.5 (WS-1)*E - 1.7 7 7 ns ns ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns Select signals include: CEx, BE[3:0], EA[21:2], and AOE. 106 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 ECLKOUT 1 2 CEx 1 2 BE[3:0] BE 1 2 EA[21:2] Address 3 4 ED[31:0] 1 2 Read Data AOE/SDRAS/SSOE 5 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 7 6 7 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 33. Asynchronous Memory Read Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 107 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 Not Ready ECLKOUT 8 9 CEx 8 9 BE[3:0] BE 8 9 EA[21:2] Address 11 9 ED[31:0] Write Data AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 10 AWE/SDWE/SSWE 7 6 7 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 34. Asynchronous Memory Write Timing 108 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 35) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 6 7 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high 1.5 Hold time, read EDx valid after ECLKOUT high 2.5 UNIT MAX ns ns The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles (see Figure 35 and Figure 36) NO. 1 2 3 4 5 8 9 10 11 12 PARAMETER 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 UNIT MIN MAX 1.2 7 ns 7 ns td(EKOH-CEV) td(EKOH-BEV) Delay time, ECLKOUT high to CEx valid td(EKOH-BEIV) td(EKOH-EAV) Delay time, ECLKOUT high to BEx invalid td(EKOH-EAIV) td(EKOH-ADSV) Delay time, ECLKOUT high to EAx invalid 1.2 Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.2 7 ns td(EKOH-OEV) td(EKOH-EDV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.2 7 ns 7 ns td(EKOH-EDIV) td(EKOH-WEV) Delay time, ECLKOUT high to EDx invalid 1.2 Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.2 Delay time, ECLKOUT high to BEx valid 1.2 Delay time, ECLKOUT high to EAx valid ns 7 Delay time, ECLKOUT high to EDx valid ns ns ns ns The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 109 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) ECLKOUT 1 1 CEx BE[3:0] 2 BE1 3 BE2 BE3 4 BE4 5 EA[21:2] EA 6 ED[31:0] 7 Q1 Q2 Q3 Q4 8 8 ARE/SDCAS/SSADS 9 9 AOE/SDRAS/SSOE AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 35. SBSRAM Read Timing ECLKOUT 1 1 CEx BE[3:0] 2 BE1 3 BE2 BE3 5 4 EA[21:2] ED[31:0] BE4 EA 10 Q1 8 11 Q2 Q3 Q4 8 ARE/SDCAS/SSADS AOE/SDRAS/SSOE 12 12 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 36. SBSRAM Write Timing 110 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 37) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 6 7 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high 1.5 Hold time, read EDx valid after ECLKOUT high 2.5 UNIT MAX ns ns The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous DRAM cycles (see Figure 37-Figure 43) NO. 1 2 3 4 5 8 9 10 11 PARAMETER 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 UNIT MIN MAX 1.5 7 ns 7 ns td(EKOH-CEV) td(EKOH-BEV) Delay time, ECLKOUT high to CEx valid td(EKOH-BEIV) td(EKOH-EAV) Delay time, ECLKOUT high to BEx invalid td(EKOH-EAIV) td(EKOH-CASV) Delay time, ECLKOUT high to EAx invalid 1.5 Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.5 td(EKOH-EDV) td(EKOH-EDIV) Delay time, ECLKOUT high to EDx valid Delay time, ECLKOUT high to EDx invalid 1.5 td(EKOH-WEV) td(EKOH-RAS) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 Delay time, ECLKOUT high to BEx valid 1.5 Delay time, ECLKOUT high to EAx valid ns 7 ns ns 7 ns 7 ns ns 7 ns 12 Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 7 ns The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 111 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) READ ECLKOUT 1 1 CEx 2 BE1 BE[3:0] EA[21:13] EA[11:2] 4 Bank 5 4 Column 5 4 3 BE2 BE3 BE4 5 EA12 6 D1 ED[31:0] 7 D2 D3 D4 AOE/SDRAS/SSOE 8 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 37. SDRAM Read Command (CAS Latency 3) 112 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) WRITE ECLKOUT 1 1 CEx 2 3 2 BE[3:0] BE1 4 BE2 BE3 BE4 D2 D3 D4 5 Bank EA[21:13] 5 4 Column EA[11:2] 4 5 EA12 9 ED[31:0] 10 9 D1 AOE/SDRAS/SSOE 8 8 11 11 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 38. SDRAM Write Command POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 113 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV ECLKOUT 1 1 CEx BE[3:0] 4 Bank Activate 5 EA[21:13] 4 Row Address 5 EA[11:2] 4 Row Address 5 EA12 ED[31:0] 12 12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 39. SDRAM ACTV Command DCAB ECLKOUT 1 1 4 5 12 12 11 11 CEx BE[3:0] EA[21:13, 11:2] EA12 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 40. SDRAM DCAB Command 114 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) DEAC ECLKOUT 1 1 CEx BE[3:0] 4 5 Bank EA[21:13] EA[11:2] 4 5 12 12 11 11 EA12 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 41. SDRAM DEAC Command REFR ECLKOUT 1 1 12 12 8 8 CEx BE[3:0] EA[21:2] EA12 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 42. SDRAM REFR Command POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 115 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) MRS ECLKOUT 1 1 4 MRS value 5 12 12 8 8 11 11 CEx BE[3:0] EA[21:2] ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 43. SDRAM MRS Command 116 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 44) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E = ECLKOUT period in ns UNIT MAX E ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles (see Figure 44) NO. 1 2 4 5 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER td(HOLDL-EMHZ) td(EMHZ-HOLDAL) Delay time, HOLD low to EMIF Bus high impedance td(HOLDH-EMLZ) td(EMLZ-HOLDAH) Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, EMIF Bus low impedance to HOLDA high UNIT MIN MAX 2E ns -0.1 2E ns 2E 7E ns -1.5 2E ns E = ECLKOUT period in ns EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus 1 4 C6713 C6713 EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. Figure 44. HOLD/HOLDA Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 117 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 45) NO. 1 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER td(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid ECLKOUT 1 1 BUSREQ Figure 45. BUSREQ Timing 118 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 MIN MAX 1.5 7.2 UNIT ns SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 RESET TIMING timing requirements for reset (see Figure 46) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 13 tw(RST) tsu(HD) 14 Pulse duration, RESET Setup time, HD boot configuration bits valid before RESET high Hold time, HD boot configuration bits valid after RESET high UNIT MAX 100 ns 2P ns th(HD) 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For this device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Phase-Lock Loop (PLL) Controller Peripheral Reference Guide (literature number SPRU233). The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits consist of: HD[14, 8, 4:3]. switching characteristics over recommended operating conditions during reset (see Figure 46) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN Delay time, external RESET high to internal reset high and all signal groups valid#|| UNIT MAX 512 x CLKIN period 2 td(RSTH-ZV) 3 td(RSTL-ECKOL) td(RSTH-ECKOV) Delay time, RESET low to ECLKOUT low td(RSTL-CKO2IV) td(RSTH-CKO2V) Delay time, RESET low to CLKOUT2 invalid td(RSTL-CKO3L) td(RSTH-CKO3V) Delay time, RESET low to CLKOUT3 low td(RSTL-EMIFZHZ) td(RSTL-EMIFLIV) Delay time, RESET low to EMIF Z group high impedance|| 0 ns Delay time, RESET low to EMIF low group (BUSREQ) invalid|| Delay time, RESET low to Z group 1 high impedance|| 0 ns 0 ns Delay time, RESET low to Z group 2 high impedance|| 0 4 5 6 7 8 9 10 11 12 td(RSTL-Z1HZ) td(RSTL-Z2HZ) CLKMODE0 = 1 0 Delay time, RESET high to ECLKOUT valid ns 6P 0 Delay time, RESET high to CLKOUT2 valid ns ns 6P 0 Delay time, RESET high to CLKOUT3 valid ns ns ns 6P ns ns P = 1/CPU clock frequency in ns. Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while internal reset is asserted. # The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET is deasserted, the actual delay time may vary. || EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and HOLDA EMIF low group consists of: BUSREQ Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7], FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0. Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 119 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 RESET TIMING (CONTINUED) Phase 1 Phase 2 Phase 3 CLKIN ECLKIN 1 RESET 2 Internal Reset Internal SYSCLK1 Internal SYSCLK2 Internal SYSCLK3 3 4 5 6 7 8 ECLKOUT CLKOUT2 CLKOUT3 9 2 10 2 11 2 EMIF Z Group EMIF Low Group Z Group 1 2 12 Z Group 2 Boot and Device Configuration Pins 13 14 EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and HOLDA EMIF low group consists of: BUSREQ Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7], FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0. Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals. Boot and device configurations consist of: HD[14, 8, 4:3]. Figure 46. Reset Timing Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin (when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8. 120 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 47) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 2 tw(ILOW) UNIT MAX Width of the NMI interrupt pulse low 2P ns Width of the EXT_INT interrupt pulse low 4P ns Width of the NMI interrupt pulse high 2P ns 4P ns tw(IHIGH) Width of the EXT_INT interrupt pulse high P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. 1 2 EXT_INT, NMI Figure 47. External/NMI Interrupt Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 121 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING timing requirements for McASP (see Figure 48 and Figure 49) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 UNIT MAX Cycle time, AHCLKR/X 20 ns 2 tc(AHCKRX) tw(AHCKRX) Pulse duration, AHCLKR/X high or low 7.5 ns 3 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X ext greater of 2P or 33 ns ns 4 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext 14 ns 5 tsu(AFRXC-ACKRX) Setup time, AFSR/X input valid before ACLKR/X latches data 6 th(ACKRX-AFRX) Hold time, AFSR/X input valid after ACLKR/X latches data 7 tsu(AXR-ACKRX) Setup time, AXR input valid before ACLKR/X latches data 8 th(ACKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data ACLKR/X int 6 ns ACLKR/X ext 3 ns ACLKR/X int 0 ns ACLKR/X ext 3 ns ACLKR/X int 10.2 ns ACLKR/X ext 6 ns ACLKR/X int 1 ns ACLKR/X ext 3 ns P = SYSCLK2 period. switching characteristics over recommended operating conditions for McASP (see Figure 48 and Figure 49) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 9 10 tc(AHCKRX) tw(AHCKRX) Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low UNIT MAX 20 ns (AH/2) - 2.5 ns ns ns 11 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X int greater of 2P or 33 ns 12 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X int (A/2) - 2.5 -1 5 ns td(ACKRX-AFRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int 13 ACLKR/X ext 0 10 ns ACLKR/X int -1 5 ns 14 15 td(ACKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid Disable time, AXR high impedance following last data bit tdis(ACKRX-AXRHZ) from ACLKR/X transmit edge ACLKR/X ext 0 10 ns ACLKR/X int -1 10 ns ACLKR/X ext -1 10 ns P = SYSCLK2 period. AH = AHCLKR/X period in ns. A = ACLKR/X period in ns. 122 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED) 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (CLKRP = CLKXP = 0) ACLKR/X (CLKRP = CLKXP = 1) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). Figure 48. McASP Input Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 123 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED) 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (CLKRP = CLKXP = 1) ACLKR/X (CLKRP = CLKXP = 0) 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). Figure 49. McASP Output Timings 124 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 INTER-INTEGRATED CIRCUITS (I2C) TIMING timing requirements for I2C timings (see Figure 50) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. STANDARD MODE MIN 1 tc(SCL) 2 Setup time, SCL high before SDA low (for a repeated START tsu(SCLH-SDAL) condition) 3 Hold time, SCL low after SDA low (for a START and a repeated th(SCLL-SDAL) START condition) 4 5 6 7 8 9 10 11 12 13 14 15 tw(SCLL) tw(SCLH) Cycle time, SCL Pulse duration, SCL low Pulse duration, SCL high MAX MAX 2.5 s 4.7 0.6 s 4 0.6 s 4.7 1.3 s 4 0.6 100 s 250 0 tw(SDAH) tr(SDA) Pulse duration, SDA high between STOP and START conditions 4.7 Rise time, SDA 1000 tr(SCL) tf(SDA) Rise time, SCL 1000 Fall time, SDA 300 tw(SP) Cb# MIN 10 tsu(SDAV-SDLH) Setup time, SDA valid before SCL high th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus devices) tf(SCL) Fall time, SCL tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) UNIT FAST MODE ns 0 300 4 0.9 s 1.3 20 + 0.1Cb# 300 ns 20 + 0.1Cb# 20 + 0.1Cb# 300 ns 300 ns 20 + 0.1Cb# 0.6 300 Pulse duration, spike (must be suppressed) ns s 0 Capacitive load for each bus line s 400 50 ns 400 pF The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. # Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 11 9 SDA 6 8 14 4 13 5 10 SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop Figure 50. I2C Receive Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 125 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 INTER-INTEGRATED CIRCUITS (I2C) TIMING (CONTINUED) switching characteristics for I2C timings (see Figure 51) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER STANDARD MODE MIN 16 17 18 19 20 21 22 23 24 25 26 27 28 MAX UNIT FAST MODE MIN MAX 10 2.5 s 4.7 0.6 s 4 0.6 s 4.7 1.3 s 4 0.6 s td(SDAV-SDLH) Delay time, SDA valid to SCL high tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices) 250 100 0 0 tw(SDAH) tr(SDA) Pulse duration, SDA high between STOP and START conditions 4.7 Rise time, SDA 1000 1.3 20 + 0.1Cb tr(SCL) tf(SDA) Rise time, SCL 1000 Fall time, SDA tc(SCL) Cycle time, SCL td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) Delay time, SDA low to SCL low (for a START and a repeated td(SDAL-SCLL) START condition) tw(SCLL) tw(SCLH) Pulse duration, SCL low Pulse duration, SCL high tf(SCL) Fall time, SCL td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) ns 0.9 s 300 ns 300 ns 300 20 + 0.1Cb 20 + 0.1Cb 300 ns 300 20 + 0.1Cb 300 4 10 26 24 SDA 21 19 28 20 25 SCL 16 27 18 17 22 18 Stop Start Repeated Start Figure 51. I2C Transmit Timings 126 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 ns s 0.6 29 Cp Capacitance for each I2C pin 10 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 23 s Stop pF SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles (see Figure 52, Figure 53, Figure 54, and Figure 55) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 2 tsu(SELV-HSTBL) th(HSTBL-SELV) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low Pulse duration, HSTROBE low (host read access) UNIT MAX 5 ns 4 ns 10P + 5.8 3 tw(HSTBL) Pulse duration, HSTROBE low (host write access) 4P 4 tw(HSTBH) tsu(SELV-HASL) Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low 4P ns 5 ns 3 ns 12 th(HASL-SELV) tsu(HDV-HSTBH) Hold time, select signals valid after HAS low Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 18 tsu(HASL-HSTBL) th(HSTBL-HASL) Setup time, HAS low before HSTROBE low 2 ns Hold time, HAS low after HSTROBE low 2 ns 10 11 19 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. Select signals include: HCNTL[1:0], HR/W, and HHWIL. switching characteristics over recommended operating conditions during host-port interface cycles (see Figure 52, Figure 53, Figure 54, and Figure 55) NO. PARAMETER 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 UNIT MIN MAX Delay time, HCS to HRDY 1 15 ns 6 td(HCS-HRDY) td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 15 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 8 td(HDV-HRDYL) toh(HSTBH-HDV) Delay time, HD valid to HRDY low 9 Output hold time, HD valid after HSTROBE high 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 2 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 5 ns 2P - 4 ns 10P + 5.8 ns Delay time, HSTROBE high to HRDY high|| 17 td(HSTBH-HRDYH) 3 15 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 127 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st halfword 5 2nd halfword 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 52. HPI Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 5 1st half-word 8 2nd half-word 17 5 17 5 HRDY (case 1) 8 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 53. HPI Read Timing (HAS Used) 128 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 14 HSTROBE HCS 12 12 13 13 HD[15:0] (input) 1st halfword 5 17 2nd halfword 5 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 54. HPI Write Timing (HAS Not Used, Tied High) HAS 19 19 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 5 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 55. HPI Write Timing (HAS Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 129 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 56) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. Cycle time, CLKR/X CLKR/X ext MIN 2P 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5 *tc(CKRX) -1 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low 2 CLKR int 9 CLKR ext 1 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0 CLKR int 3 CLKR ext 4 CLKX int 9 CLKX ext 1 CLKX int 6 CLKX ext 3 UNIT MAX ns ns ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle. 130 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 56) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 1.8 10 2P C - 1# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X CLKR/X int 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -2 3 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 td(FXH-DXV) ns ns CLKX int -2 3 CLKX ext 2 9 CLKX int -1 4 CLKX ext CLKX int 1.5 -3.2 + D1|| 10 4 + D2|| CLKX ext 0.5 + D1|| 10+ D2|| Delay time, FSX high to DX valid FSX int -1.5 4.5 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 2 9 ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0 If DXENA = 1, then D1 = 2P, D2 = 4P POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 131 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 13 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) Figure 56. McBSP Timings 132 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 (n-3) SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 57) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) UNIT MAX Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 57. FSR Timing When GSYNC = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 58) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT MIN MAX 2 - 6P ns 5 + 12P ns 133 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 58) NO. PARAMETER 1 th(CKXL-FXL) 2 td(FXL-CKXH) td(CKXH-DXV) 3 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 MASTER SLAVE MIN MAX Hold time, FSX low after CLKX low T-2 T+3 Delay time, FSX low to CLKX high# L-2 L+3 -3 4 L-4 L+3 Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high MIN UNIT MAX ns ns 6P + 2 10P + 17 ns ns 2P + 1.5 6P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 58. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 134 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 59) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MASTER MIN 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high th(CKXH-DRV) Hold time, DR valid after CLKX high MAX 12 5 4 P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT SLAVE MIN MAX 2 - 6P ns 5 + 12P ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 59) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 MASTER SLAVE PARAMETER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 Disable time, DX high impedance following last data bit from tdis(CKXL-DXHZ) CLKX low 1 MIN UNIT MIN MAX L-2 L+3 MAX T-2 T+3 -3 4 6P + 2 10P + 17 ns -4 4 6P + 1.5 10P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+4 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 135 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 59. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 60) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high MAX POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SLAVE MIN MAX 12 2 - 6P ns 4 5 + 12P ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. 136 UNIT SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 60) NO. PARAMETER 1 th(CKXH-FXL) 2 td(FXL-CKXL) td(CKXL-DXV) 3 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 MASTER SLAVE MIN MAX Hold time, FSX low after CLKX high T-2 T+3 ns Delay time, FSX low to CLKX low# H-2 H+3 ns -3 4 H - 3.6 H+3 Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high MIN UNIT 6P + 2 MAX 10P + 17 ns ns 2P + 1.5 6P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 60. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 137 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 61) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MASTER MIN 4 5 tsu(DRV-CKXH) Setup time, DR valid before CLKX high th(CKXH-DRV) Hold time, DR valid after CLKX high MAX UNIT SLAVE MIN MAX 12 2 - 6P ns 4 5 + 12P ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 61) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 MASTER SLAVE PARAMETER 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 1 6 MIN UNIT MIN MAX MAX H-2 H+3 ns T-2 T+3 ns -3 4 6P + 2 10P + 17 ns -3.6 4 6P + 1.5 10P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+4 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 138 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 61. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 139 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 TIMER TIMING timing requirements for timer inputs (see Figure 62) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 2 tw(TINPH) tw(TINPL) UNIT MAX Pulse duration, TINP high 2P ns Pulse duration, TINP low 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. switching characteristics over recommended operating conditions for timer outputs (see Figure 62) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 3 4 tw(TOUTH) tw(TOUTL) MAX Pulse duration, TOUT high 4P - 3 ns Pulse duration, TOUT low 4P - 3 ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. 2 1 TINPx 4 3 TOUTx Figure 62. Timer Timing 140 UNIT POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs (see Figure 63) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 2 tw(GPIH) tw(GPIL) Pulse duration, GPIx high 4P Pulse duration, GPIx low 4P UNIT MAX ns ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access the GPIO register through the CFGBUS. switching characteristics over recommended operating conditions for GPIO outputs (see Figure 63) NO. 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER MIN 3 4 tw(GPOH) tw(GPOL) Pulse duration, GPOx high 12P - 3 Pulse duration, GPOx low 12P - 3 UNIT MAX ns ns P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles; therefore, the minimum GPOx pulse width is 12P. 2 1 GPIx 4 3 GPOx Figure 63. GPIO Port Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 141 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 64) 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 7 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 64) NO. 2 13PYPA-167 13PYP-200 13GDPA-200 13GDP-225 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid MIN MAX 0 15 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 64. JTAG Test-Port Timing 142 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT ns SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 MECHANICAL DATA The following tables show the thermal resistance characteristics for the GDP and PYP mechanical packages. thermal resistance characteristics (S-PBGA package) for GDP NO C/W Air Flow (m/s) Two Signals, Two Planes (4-Layer Board) 1 RJC Junction-to-case 9.7 N/A 2 PsiJT Junction-to-package top 1.5 0.0 3 RJB RJA Junction-to-board 19 N/A Junction-to-free air 22 0.0 RJA RJA Junction-to-free air 21 0.5 Junction-to-free air 20 1.0 Junction-to-free air 19 2.0 8 RJA RJA Junction-to-free air 18 4.0 9 PsiJB Junction-to-board 16 0.0 4 5 6 7 m/s = meters per second thermal resistance characteristics (S-PQFP-G208 package) for PYP C/W NO Junction-to-Pad Two Signals, Two Planes (4-Layer Board) - 208-pin PYP 1 RJP Junction-to-pad, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 0.2 Junction-to-Package Top Two Signals, Two Planes (4-Layer Board) - 208-pin PYP 2 PsiJT Junction-to-package top, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 0.18 3 PsiJT Junction-to-package top, 7.5 x 7.5 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 0.23 4 PsiJT Junction-to-package top, 26 x 26 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 0.18 5 PsiJT Junction-to-package top, 7.5 x 7.5 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 0.23 Two Signals (2-Layer Board) Junction-to-Still Air Two Signals, Two Planes (4-Layer Board) - 208-pin PYP 6 RJA Junction-to-still air, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 13 7 RJA Junction-to-still air, 7.5 x 7.5 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 20 Two Signals (2-Layer Board) 8 RJA Junction-to-still air, 26 x 26 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 14 9 RJA Junction-to-still air, 7.5 x 7.5 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 143 SPRS186K - DECEMBER 2001 - REVISED OCTOBER 2005 packaging information For proper device thermal performance, the thermal pad must be soldered to an external ground thermal plane. This pad is electrically and thermally connected to the backside of the die. For the TMS320C6713 208-Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad is externally flush with the mold compound. The following packaging information and addendum reflect the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. 144 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TMS320C6713GDP225 OBSOLETE BGA GDP 272 TBD Call TI Call TI TMS320C6713GDPA200 OBSOLETE BGA GDP 272 TBD Call TI Call TI TMS320C6713GDPX225 OBSOLETE BGA GDP 272 TBD Call TI Call TI TMS320C6713PYP200 OBSOLETE HLQFP PYP 208 TBD Call TI Call TI TMS320C6713PYP200B OBSOLETE HLQFP PYP 208 TBD Call TI Call TI TMS320C6713PYPX200 OBSOLETE HLQFP PYP 208 TBD Call TI Call TI TMX320C6713GDP OBSOLETE BGA GDP 272 TBD Call TI Call TI TMX320C6713GFN OBSOLETE BGA GFN 272 TBD Call TI Call TI TMX320C6713PYP OBSOLETE HLQFP PYP 208 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPBG274 - MAY 2002 GDP (S-PBGA-N272) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 24,20 SQ 23,80 24,13 TYP 1,27 0,635 Y W V U T R P N M L K J H G F E D C B A A1 Corner 1,27 0,635 3 1 2 1,22 1,12 5 4 7 6 9 8 11 13 15 17 19 10 12 14 16 18 20 Bottom View 2,57 MAX Seating Plane 0,65 0,57 0,90 0,60 0,10 0,70 0,50 0,15 4204396/A 04/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DLP(R) Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee(R) Solutions amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2009, Texas Instruments Incorporated