LTC4304
1
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Hot Swappable 2-Wire
Bus Buffer with Stuck
Bus Recovery
The LTC®4304 hot swappable 2-wire bus buffer allows I/O
card insertion into a live backplane without corruption of
the data and clock busses. When a connection is made,
the LTC4304 provides bidirectional buffering, keeping the
backplane and card capacitances isolated. If SDAOUT or
SCLOUT is low for ≥30ms (typ), the LTC4304 automatically
breaks the data and clock bus connection and FAULT will
pull low. At this time the LTC4304 automatically generates
up to 16 clock pulses on SCLOUT in an attempt to free the
bus. A connection will be enabled automatically when the
bus becomes free. A logic low on the ACC input enables
the LTC4304’s rise-time accelerators. A logic high on ACC
disables the rise-time accelerators, which allows SDA and
SCL bus pull-up voltages below VCC.
During insertion, the SDA and SCL lines are precharged
to 1V to minimize bus disturbances. When driven high,
ENABLE allows the LTC4304 to connect after a stop bit or
bus idle occurs. Driving ENABLE low breaks the connection
between SDAIN and SDAOUT, SCLIN and SCLOUT. READY
is an open drain output that indicates when the backplane
and card sides are connected together.
■ Automatic Disconnect of SDA/SCL Lines when Bus
is Stuck Low for ≥30ms
■ Fault Flag for Stuck Bus
■ Recovers Stuck Busses with Automatic Clocking*
■ Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
■ Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■ Allows Bus Pullup Voltages Above and Below VCC
■ ±15kV Human Body Model ESD Protection
■ Isolates Input SDA and SCL Lines from Output
■ Compatible with I2CTM, I2C Fast-Mode and SMBus
Standards (Up to 400kHz Operation)
■ READY Open Drain Output
■ 1V Precharge on All SDA and SCL Lines
■ High Impedance SDA, SCL Pins for VCC = 0V
■ ENABLE Gates Connection from Input to Output
■ MSOP 10-Pin and DFN (3mm × 3mm) Packages
■ Hot Board Insertion
■ Servers
■ Capacitance Buffer/Bus Extender
■ RAID Systems
CARD
100k
ENABLE
FAULT
CARD_SCL
CARD_SDA
SCLOUTSCLIN
SDAOUT
READY
SDAIN
GND
VCC
LTC4304
ACC
0.01µF
4304 TA01
10k 10k
10k10k
5V
BACK_SCL
BACKPLANE
CONNECTOR
BACK_SDA
3.3V
3.3V
STAGGERED
CONNECTOR
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6356140, 6650174, 7032051.
SDAOUT
5V/DIV
SCLOUT
5V/DIV
FAULT
5V/DIV
200
m
s/DIV
STUCK LOW > 30ms RECOVERS
DISCONNECT AT TIMEOUT
AUTOMATIC CLOCKING
4304 TA01b
SDAIN
5V/DIV
Stuck Bus Resolved with
Automatic Clocking
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
APPLICATIO S
U
LTC4304
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VCC to GND .................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE,
FAULT, ACC .................................................. –0.3V to 7V
Operating Temperature
LTC4304C ................................................ 0°C to 70°C
LTC4304I .............................................–40°C to 85°C
(Notes 1, 2)
The
● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SDAIN, SCLIN, SDAOUT, SCLOUT,
FAULT READY (Note 3) .........................................30mA
Storage Temperature Range
MSOP ................................................–65°C to 150°C
DFN ....................................................–65°C to 125°C
Lead Temperature (Soldering, 10sec)
MSOP ............................................................... 300°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VCC Positive Supply Voltage ● 2.7 5.5 V
ICC Supply Current VCC = 5.5V, VSDAIN = VSDAOUT = 0V (Note 7) ● 6 8 mA
Supply Current, ENABLE = GND VCC = 5.5V 1.5 mA
Startup Circuitry
VPRE Precharge Voltage SDA, SCL Floating, VCC = 5.5V ● 0.8 1 1.2 V
TIDLE Bus Idle Time ● 60 95 175 µs
VOL_READY READY Output Low Voltage IPULLUP = 3mA ● 0.4 V
I
PULLUP = 6mA, VCC = 4.7V ● 0.4 V
VTHR_ENABLE ENABLE Threshold ● 0.8 1.4 2 V
IENABLE ENABLE Input Current ENABLE from 0 to VCC ● 0.1 ±1.5 µA
VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge ● 1.6 1.8 2 V
TOP VIEW
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11)
PCB GND CONNECTION OPTIONAL
10
9
6
7
811
4
5
3
2
1VCC
SDAOUT
SDAIN
FAULT
READY
ENABLE
SCLOUT
SCLIN
ACC
GND
1
2
3
4
5
ENABLE
SCLOUT
SCLIN
ACC
GND
10
9
8
7
6
VCC
SDAOUT
SDAIN
FAULT
READY
TOP VIEW
MS10 PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA =200°C/W
ORDER PART NUMBER DD PART MARKING* ORDER PART NUMBER MS PART MARKING*
LTC4304CDD
LTC4304IDD
LBBD
LBBD
LTC4304CMS
LTC4304IMS
LTBBC
LTBBC
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
TJMAX = 125°C, θJA = 43°C/W
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
W
WW
U
FOR ATIOPACKAGE/ORDER I
UUW
LTC4304
3
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The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and VCC voltage is shown in the Typical Performance
Characteristics section.
Note 5: IPULLUPAC varies with temperature and VCC voltage, as shown in
the Typical Performance Characteristics section.
Note 6: Determined by design, not tested in production.
Note 7: ICC test performed with connection circuitry active.
Note 8: When fl oating, the ACC pin can tolerate ±5µA of leakage.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specifi ed.
Note 3: Pulsed less than 5µs.
Note 4: The connection circuitry always regulates the output to a higher
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VHYS SDA, SCL, Logic Input Threshold Voltage (Note 6) 50 mV
Hysteresis
tPLH ENABLE Delay On-Off VCC = 3.3V 300 ns
READY Delay Off-On (Note 6) 10 ns
tPHL ENABLE Delay Off-On VCC = 3.3V ● 60 95 175 µs
READY Delay On-Off (Note 6) 10 ns
IOFF_READY Ready Off Leakage Current ● ±10 µA
Rise-Time Accelerators
IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 2.7V, 2 3.5 5.5 mA
Slew Rate = 0.8V/µs (Note 5)
tPDOFF ACC Delay, On/Off (Note 6) 5 ns
VIH Input High Voltage Measured on ACC ● 0.9VCC V
VIL Input Low Voltage Measured on ACC ● 0.1VCC V
IIN ACC Input Current ACC Shorted to GND or VCC (Note 8) ● –100 100 µA
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer SDAOUT, SCLOUT = 0V ● 25 30 35 ms
VOLFAULT FAULT Output Low Voltage IPULLUP = 3mA ● 0.4 V
IOFF_FAULT V
CC = 5.5V ● ±10 µA
Input-Output Connection
VOS Input-Output Offset Voltage 10k to VCC on SDA, SCL, ● 40 80 120 mV
2.7k to VCC on SDA, SCL ● 50 100 150 mV
V
CC = 3.3V, VSDA/SCL = 0.2V (Note 4)
CIN Digital Input Capacitance (Note 6) 10 pF
SDAIN, SDAOUT, SCLIN, SCLOUT
VIL, MAX Input Logic Low Voltage ● 0.4 V
ILEAK Input Leakage Current SDA, SCL, VCC = 5.5V ● ±5 µA
VOL Output Low Voltage, Input = 0V SDA, SCL Pins, ISINK = 4mA, VCC = 2.7V ● 0 0.19 0.3 V
Timing Characteristics
fI2C, MAX I
2C Maximum Operating Frequency (Note 6) 400 600 kHz
tBUF Bus Free Time Between Stop and Start (Note 6) 1.3 µs
Condition
tHD, STA Hold Time After (Repeated) (Note 6) 100 ns
Start Condition
tSU, STA Repeated Start Condition Set-Up Time (Note 6) 0 ns
tSU, STO Stop Condition Set-Up Time (Note 6) 0 ns
tHD, DATI Data Hold Time Input (Note 6) 0 ns
tSU, DAT Data Set-Up Time (Note 6) 100 ns
ELECTRICAL CHARACTERISTICS
LTC4304
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TEMPERATURE (°C)
tPHL (ns)
140
120
100
80
60
40
20
0
4303 G02
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
TEMPERATURE (°C)
IPULLUPAC (mA)
14
12
10
8
6
4
2
0
4303 G03
RPULLUP (Ω)
1000
0
VOUT-VIN (mV)
50
150
200
250
3000 5000
4303 G04
100
7000 9000
COUT (pF)
0
tPHL (ns)
1500
4303 G05
500 1000 2000
180
160
140
120
100
80
60
40
20
VCC = 5.5V
VCC = 2.7V
VCC = 5.5V
VCC = 3.3V
VCC = 2.7V
CIN = COUT = 100pF
RPULLUPIN = RPULLUPOUT = 10k
CIN = 50pF
RPULLUPIN = RPULLUPOUT = 10k
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
5.0
ICC (mA)
5.4
5.8
6.2
5.2
5.6
6.0
4303 G01
VCC = 5.5V
VCC = 2.7V
TA = 25°C unless otherwise indicated.
TYPICAL PERFOR
UW
CE CHARACTERISTICSA
ICC vs Temperature Input-Output tPHL vs Temperature IPULLUPAC vs Temperature
Connection Circuitry VOUT - VIN Input-Output tPHL vs COUT
LTC4304
5
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ENABLE (Pin 1): Connection Enable. This is a digital
threshold input pin. For normal operation ENABLE is high.
Driving ENABLE below 0.8V isolates SDAIN from SDAOUT,
SCLIN from SCLOUT, asserts READY low and disables
automatic clocking. A rising edge on ENABLE after a fault
has occurred unconditionally forces a connection between
SDAIN, SDAOUT and SCLIN, SCLOUT.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
ACC (Pin 4): Rise-Time Accelerator Control. Connect ACC
to VCC to disable all four accelerators. Connect ACC to
GND to enable all four accelerators. Float ACC to enable
the SDAOUT and SCLOUT accelerators only. For applica-
tions when VCC is greater than the bus pull-up voltage,
connect ACC to VCC.
GND (Pin 5): Device Ground. Connect this pin to a ground
plane for best results.
READY (Pin 6): Connection Status Flag. READY provides
a digital fl ag which indicates the status of the connection
circuitry described in the “Connection Circuitry” section.
Connect a resistor of 10k to VCC to provide the pull-up.
FAULT (Pin 7): Bus Stuck Low Fault. FAULT is an open
drain N-channel MOSFET which pulls low to signal a bus
stuck low condition. In normal operation, FAULT is high.
Connect a 10k resistor from this pin to VCC to provide
the pull-up.
SDAIN (Pin 8): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 9): Serial Data Output. Connect this pin to
the SDA bus on the card.
VCC (Pin 10): Supply Voltage Input. Place a bypass capaci-
tor of at least 0.01µF close to VCC for best results.
Exposed Pad (Pin 11, DFN Only): Exposed pad may be
left open or connected to the ground plane.
PI FU CTIO S
UUU
LTC4304
6
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BLOCK DIAGRA
W
SLEW RATE
DETECTOR
3.5mA
CONNECT
PC_CONNECT PC_CONNECT
PC_CONNECT
CONNECT
1
200k
200k
200k
200k
PRECHARGE
LOGIC
30ms
TIMER
95µs
DELAY
ACC
CTRL
UVLO
1.4V
ENABLE
1.8V
3
4
SCLIN
ACC
8
SDAIN
1.8V
CONNECT
CONNECT
9
SDAOUT
10 VCC
2
SCLOUT
READY 6
FAULT 7
GND
4304 BD
5
SLEW RATE
DETECTOR
ACC_IN
ACC_IN
3.5mA
SLEW RATE
DETECTOR
ACC_IN
3.5mA
SLEW RATE
DETECTOR ACC_OUT
3.5mA
UVLO
ACC_OUT
AUTOMATIC
CLOCKING
–
+
–
+
–
+
–
+
–
+
LTC4304 2-Wire Bus Buffer with Stuck Bus Protection
LTC4304
7
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Start-Up
When the LTC4304 fi rst receives power on its VCC pin,
either during power up or live insertion, it starts in an under
voltage lockout (UVLO) state, ignoring any activity on the
SDA or SCL pins until VCC rises above 2.5V (typical).
During this time, the precharge circuitry is active and
forces 1V through 200K nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and VCC.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Once the LTC4304 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the input side to indicate the
completion of a data transaction. When either one occurs,
the part also verifi es that both the SDAOUT and SCLOUT
voltages are high. When all of these conditions are met,
the input-to-output connection circuitry is activated, join-
ing the SDA and SCL busses on the I/O card with those
on the backplane and READY goes high.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages be-
ing low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4304. SDAIN and SDAOUT enter
a logic high state only when all devices on both SDAIN
and SDAOUT release high. The same is true for SCLIN
and SCLOUT. This important feature ensures that clock
stretching, clock synchronization, arbitration and the ac-
knowledge protocol always work, regardless of how the
devices in the system are tied to the LTC4304.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4304’s data or clock pins, the LTC4304 regulates the
voltage on the opposite side of the part (call it VLOW2)
to a slightly higher voltage, as directed by the following
equation:
V
LOW2 = VLOW1 + 75mV + (VCC/R) • 20Ω (typical)
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where VCC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then
the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 20
= 91.6mV(typical). See the Typical Performance Charac-
teristics section for curves showing the offset voltage as
a function of VCC and R.
Bus Stuck Low Timeout
When SDAOUT or SCLOUT is low, an internal timer starts.
The timer is only reset when SDAOUT and SCLOUT are
both high. If they do not go high within 30ms (typical),
FAULT pulls low indicating a bus stuck condition and the
connection between SDAIN and SDAOUT, and SCLIN
and SCLOUT is broken. After a delay of at least 40µs, the
LTC4304 automatically generates up to 16 clock pulses at
8.5kHz (typical) on SCLOUT in an attempt to unstick the
bus. When SDAOUT and SCLOUT go high, FAULT is cleared
and reconnection occurs when the conditions described
in the “Start-Up” section above are satisfi ed.
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated.
30ms after UVLO, FAULT pulls low indicating a bus stuck
low condition, and automatic clocking takes place as
described above.
Propagation Delays
During a rising edge, the rise-time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
OPERATION
LTC4304
8
4304fa
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 1 for a VCC
= 3.3V and a 10k pull-up resistor on each side (50pF on
one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective tPLH is negative.
There is a propagation delay, tPHL, through the connec-
tion circuitry for falling waveforms. Figure 2 shows the
falling edge waveforms. An external driver pulls down
the voltage on the side with 50pF capacitance; LTC4304
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows tPHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. Larger output capacitances translate to longer
delays. Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their systems
and adjust setup and hold times accordingly.
READY Digital Output
The READY pin provides a digital fl ag which indicates the
status of the connection circuitry described previously in
the “Connection Circuitry” section. READY is high when
the connection circuitry is active, and pulls low when
there is not a valid connection. The pin is driven by an
open drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor of 10k to VCC to
provide the pull-up.
FAULT Digital Output
The FAULT pin provides a digital fl ag which is low when
SDAOUT and SCLOUT have not both been high within 30ms
(typical). The pin is driven by an open drain pull-down
capable of sinking 3mA while holding 0.4V on the pin.
Connect a resistor of 10k to VCC to provide the pull-up.
ENABLE
When the ENABLE pin is driven below 0.8V with respect
to the LTC4304’s ground, the backplane side is discon-
nected from the card side, and the READY pin is internally
pulled low. When the pin is driven above 2V, the part
waits for data transactions on both the backplane and
card sides to be complete (as described in the Start-Up
section) before connecting the two sides. At this time the
internal pulldown on READY releases. When ENABLE is
low, automatic clocking is disabled.
Figure 1. Input-Output Connection tPLH Figure 2. Input-Output Connection tPHL
OUTPUT SIDE
50pF
0.5V/DIV
INPUT SIDE
150pF
0.5V/DIV
200ns/DIV 4303 F01
INPUT SIDE
50pF
0.5V/DIV
OUTPUT SIDE
150pF
0.5V/DIV
20ns/DIV 4303 F02
OPERATION
LTC4304
9
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A rising edge on ENABLE after a stuck bus condition has
occurred forces a connection between SDAIN, SDAOUT
and SCLIN, SCLOUT even if bus idle conditions are not
met. At this time the internal 30ms timer is reset but not
disabled.
Rise Time Accelerators
Once connection has been established, rise time accel-
erator circuits on all four SDA and SCL pins are activated
(assuming accelerators are enabled, see ACC pin descrip-
tion). These allow the use of a large pull-up resistor to
reduce power consumption, or bus capacitance beyond
that specifi ed in I2C, while still meeting system rise time
requirements. During positive bus transitions, the LTC4304
switches in 3.5mA (typical) of current to quickly slew the
SDA and SCL lines once their DC voltages exceed 0.8V.
Choose a pull-up resistor so that the bus will rise on its
own at a rate of at least 0.8V/µs to guarantee activation
of the accelerators. Rise time accelerators turn off when
SDA and SCL lines are approximately 1V below VCC.
Rise time accelerators are automatically disabled during
automatic clocking.
Resistor Pull-Up Selection
The system pull-up resistors must be strong enough
to provide a positive slew rate of 0.8V/µs on the SDA
and SCL pins, in order to activate the rise time accelera-
tors during rising edges. Choose maximum resistor value
RPULL-UP(MAX) using the formula:
Rk
V V ns V
CpF
PULLUP MAX
BUS MIN
BUS
()
()
[] –. • [ /]
[]
Ω=
()
0 8 1250
where VBUSMIN is the minimum operating pull-up sup-
ply voltage, and CBUS the total capacitance on respec-
tive bus line.
For example, assume VBUS = VCC = 3.3V, and assuming
±10% supply tolerance, VBUSMIN = 2.97V. With CBUS =
100pF, RPULL-UP, MAX = 27.1k. Therefore a smaller pull-up
resistor than 27.1k must be used, so 10k works fi ne.
Live Insertion and Capacitance Buffering Application
Figures 3 through 6 illustrate applications of the LTC4304
that take advantage of both its Hot SwapTM controlling and
capacitance buffering features. In all of these applications,
note that if the I/O cards were plugged directly into the
backplane without the LTC4304 buffer, all of the backplane
and card capacitances would add directly together, making
rise- and fall-time requirements diffi cult to meet. Placing a
LTC4304 on the edge of each card, however, isolates the
card capacitance from the backplane. For a given I/O card,
the LTC4304 drives the capacitance on the card side and
the backplane must drive only the digital input capacitance
of the LTC4304, which is less than 10pF.
In most applications the LTC4304 will be used with a
staggered connector where VCC and GND will be long
pins. SDA and SCL are medium length pins to ensure that
the VCC and GND pins make contact fi rst. This will allow
the precharge circuitry to be activated on SDA and SCL
before they make contact. ENABLE is a short pin that is
pulled down when not connected. This is to ensure that the
connection between the backplane and the cards data and
clock busses is not enabled until the transients associated
with live insertion have settled.
Figure 3 shows the LTC4304 in a CompactPCITM confi gura-
tion. Connect VCC and ENABLE to the output of one of the
CompactPCI power supply Hot Swap circuits. Use a pull-up
resistor to ENABLE for a card side enable/disable. VCC is
monitored by a fi ltered UVLO circuit. With the VCC voltage
powering up after all the other pins have established con-
nection, the UVLO circuit ensures that the backplane and
the card data and clock busses are not connected until
the transients associated with live insertion have settled.
Owing to their small capacitance, the SDAIN and SCLIN
pins cause minimal disturbance on the backplane busses
when they make contact with the connector.
Hot Swap is a trademark of Linear Technology Corporation.
OPERATION
APPLICATIONS INFORMATION
LTC4304
10
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Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4304 in a CompactPCI System
R13
10k
R12
10k
R14
10k
I/O PERIPHERAL CARD N
CARDN_SCL
CARDN_SDA
4304 F03
• • •
R9
10k
R8
10k
R10
10k
I/O PERIPHERAL CARD 2
CARD2_SCL
CARD2_SDA
R5
10k
R4
10k
R6
10k
I/O PERIPHERAL CARD 1
CARD1_SCL
CARD1_SDA
R1
10k
VCC
R2
10k
BACKPLANE
BACKPLANE
CONNECTOR
CARD
ENABLE/DISABLE
SDA
BD_SEL
SCL
C1
0.01µF
R3
10k
R7
10k
R11
10k
C3
0.01µF
C5
0.01µF
POWER SUPPLY
HOT SWAP
POWER SUPPLY
HOT SWAP
POWER SUPPLY
HOT SWAP
CARD
ENABLE/DISABLE
CARD
ENABLE/DISABLE
ENABLE
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
LTC4304
ENABLE
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
LTC4304
ENABLE
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
LTC4304
STAGGERED
CONNECTOR
APPLICATIONS INFORMATION
LTC4304
11
4304fa
Figure 4 shows the LTC4304 in a PCI application where all
of the pins have the same length. In this case, a RC fi lter
circuit on the I/O card with a product of 10ms provides a
R3
100k
4304 F04
R9
10k
R8
10k
R10
10k
R12
10k
I/O PERIPHERAL CARD 2
CARD2_SCL
CARD2_SDA
R5
10k
R4
10k
I/O PERIPHERAL CARD 1
CARD1_SCL
CARD1_SDA
R1
10k
VCC
R2
10k
BACKPLANE
BACKPLANE
CONNECTOR
SDA
SCL
C1
0.01µF
C2
0.1µF
C3
0.01µF
R6
10k
•
•
•
R7
100k
C4
0.1µF
R11
10k
ENABLE
SDAIN
SCLIN
ACC
VCC
GND
SDAOUT
SCLOUT
READY
FAULT
LTC4304
ENABLE
SDAIN
SCLIN
ACC
VCC
GND
SDAOUT
SCLOUT
READY
FAULT
LTC4304
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4304 in a PCI System
fi lter to prevent the LTC4304 from becoming activated until
the transients associated with live insertion have settled.
Connect the capacitor between ENABLE and GND, and the
resistor from VCC to ENABLE.
APPLICATIONS INFORMATION
LTC4304
12
4304fa
Figure 5. Typical Supply Independent Applications
CARD_SCL
CARD_SDA
3.3V
5V
5V
4304 F05
BACKPLANE
CONNECTOR
SDA
SCL
C1
0.01µF
R1
10k
R6
10k
R11
10k
R12
10k
R7
10k
R10
10k
R15
10k
R2
10k
R3
10k
R8
10k
2.5V
R13
10k
R14
10k
R9
10k
R4
10k
R5
10k
ACC
SDAIN
SCLIN
ENABLE
VCC
GND
SDAOUT
SCLOUT
READY
FAULT
LTC4304
CARD_SCL
CARD_SDA
3.3V
3.3V
3.3V
3.3V
5V
5V
BACKPLANE
CONNECTOR
SDA
SCL
C2
0.01µF
ACC
SDAIN
SCLIN
ENABLE
VCC
GND
SDAOUT
SCLOUT
READY
FAULT
LTC4304
CARD_SCL
CARD_SDA
BACKPLANE
CONNECTOR
SDA
SCL
C3
0.01µF
ACC
SDAIN
SCLIN
ENABLE
VCC
GND
SDAOUT
SCLOUT
READY
FAULT
LTC4304
STAGGERED
CONNECTOR
STAGGERED
CONNECTOR
STAGGERED
CONNECTOR
Supply Independent Operation
Figure 5 illustrates applications of the LTC4304 with differ-
ent bus pull up and VCC voltages, demonstrating its ability
to recognize and buffer bus data levels that are above or
below its VCC supply voltage. In applications where VCC
voltage is greater than bus pull-up voltages, rise-time ac-
celerators cannot be used. Float ACC in applications where
the pull-up voltage on SDAIN and SCLIN is < VCC and the
pull-up voltage on SDAOUT and SCLOUT is ≥ VCC. Connect
ACC to ground in applications where VCC is ≤ SDA and
SCL pull-up voltages. Connect ACC to VCC for applications
where SDA and SCL pull-up voltages are ≤ VCC.
APPLICATIONS INFORMATION
LTC4304
13
4304fa
Figure 6. Simplifi ed ATCA IPMB Application
SDAOUT
SCLOUT
SDAIN
SCLIN
ENABLE VCC
R4
2.7k
R3
2.7k
R1
10k
R2
10k
C1
0.01µFR5
10k
R6
10k
LTC4304
SDAOUT
SCLOUT
SDAIN
SCLIN
ENABLE
VCC
LTC4304
4304 F06
VCC
VCC
ShMC
VCC
IPMC
IPM
BUS
(1 OF 2)
SHELF MANAGER ATCA BOARD
C2
0.01µF
APPLICATIONS INFORMATION
LTC4304
14
4304fa
3.00 0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 0.10
(2 SIDES)
0.75 0.05
R = 0.115
TYP
2.38 0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 0.05
2.38 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 0.05
(2 SIDES)2.15 0.05
0.50
BSC
0.675 0.05
3.50 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
PACKAGE DESCRIPTIO
U
LTC4304
15
4304fa
PACKAGE DESCRIPTIO
U
MSOP (MS) 0603
0.53 0.152
(.021 .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.127 0.076
(.005 .003)
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 0.152
(.193 .006)
0.497 0.076
(.0196 .003)
REF
8910 76
3.00 0.102
(.118 .004)
(NOTE 3)
3.00 0.102
(.118 .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0 – 6 TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 0.127
(.035 .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 0.038
(.0120 .0015)
TYP
0.50
(.0197)
BSC
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4304
16
4304fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT 0806 REV A • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog Low RON: 35Ω Single-Ended/70Ω Differential,
Mux with SMBus Interface Expandable to 32 Single or 16 Differential Channels
LTC1427-50 Micropower, 10-Bit Current Output DAC Precision 50µA ± 2.5% Tolerance Over Temperature,
with SMBus Interface 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623 Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability
LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I2C Rise-Time,
Ensures Data Integrity with Multiple SMBus/I2C Devices
LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz, Floating or Grounded Lamp Confi gurations
LTC1695 SMBus/I2C Fan Speed Controller in ThinSOTTM 0.75Ω PMOS 180mA Regulator, 6-Bit DAC
LTC1840 Dual I2C Fan Speed Controller Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer Isolates Backplane and Card Capacitances
LTC4300A-3 Hot Swappable 2-Wire Bus Buffer Provides Level Shifting and Enable Functions
LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent
LTC4301L Hot Swappable 2-Wire Bus Buffer Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
with Low Voltage Level Translation
LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
LTC4303 Hot Swappable 2-Wire Bus Buffer with Stuck Provides Automatic Clocking to Free Stuck I2C Busses
Bus Recovery
ThinSOT is a trademark of Linear Technology Corporation.
Figure 7. System with Active Connection Control
R1
10k
R2
10k
5V
BACK_SCL
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
CARD
BACK_SDA
3.3V
FROM
MICROPROCESSOR ENABLE
FAULT
CARD_SCL
CARD_SDA
SCLOUTSCLIN
SDAOUT
READY
SDAIN
GND
VCC
LTC4304
ACC
C1
0.01µF
4304 F07
R4
10k
R5
10k
R3
10k
TYPICAL APPLICATIO
U
RELATED PARTS
