SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation ('HC4511) D 4.5-V to 5.5-V VCC Operation CD54HC4511 . . . F PACKAGE CD74HC4511 . . . E, M, OR PW PACKAGE CD74HCT4511 . . . E PACKAGE (TOP VIEW) (CD74HCT4511) D High-Output Sourcing Capability D D D D D D - 7.5 mA at 4.5 V (CD74HCT4511) - 10 mA at 6 V ('HC4511) Input Latches for BCD Code Storage Lamp Test and Blanking Capability Balanced Propagation Delays and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs 'HC4511 - High Noise Immunity, NIL or NIH = 30% of VCC at VCC = 5 V CD74HCT4511 - Direct LSTTL Input Logic Compatibility, VIL = 0.8 V Maximum, VIH = 2 V Minimum - CMOS Input Compatibility, II 1 A at VOL, VOH D1 D2 LT BL LE D3 D0 GND BCD Inputs BCD Inputs 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC f g a 7-Segment b Outputs c d e DISPLAY 0 1 2 3 4 5 6 7 8 9 a f g b c e d description/ordering information The CD54HC4511, CD74HC4511, and CD74HCT4511 are BCD-to-7 segment latch/decoder/drivers with four address inputs (D0-D3), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable (LE) input that, when high, enables the latches to store the BCD inputs. When LE is low, the latches are disabled, making the outputs transparent to the BCD inputs. These devices have standard-size output transistors, but are capable of sourcing (at standard VOH levels) up to 7.5 mA at 4.5 V. The HC types can supply up to 10 mA at 6 V. ORDERING INFORMATION PDIP - E -55C to 125C ORDERABLE PART NUMBER PACKAGE TA SOIC - M TSSOP - PW CDIP - F Tube of 25 TOP-SIDE MARKING CD74HC4511E CD74HC4511E CD74HCT4511E CD74HCT4511E Tube of 40 CD74HC4511M Reel of 2500 CD74HC4511M96 Reel of 250 CD74HC4511MT Reel of 2000 CD74HC4511PWR Reel of 250 CD74HC4511PWT Tube of 25 CD54HC4511F3A HC4511M HJ4511 CD54HC4511F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 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'!!&"&#+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 FUNCTION TABLE OUTPUTS INPUTS LE BL X X X L L H L H L LT D3 D2 D1 D0 a b c d e f g DISPLAY L X X X X H H H H H H H 8 H X X X X L L L L L L L Blank H L L L L H H H H H H L 0 H L L L H L H H L L L L 1 H H L L H L H H L H H L H 2 L H H L L H H H H H H L L H 3 L H H L H L L L H H L L H H 4 L H H L H L H H L H H L H H 5 L H H L H H L L L H H H H H 6 L H H L H H H H H H L L L L 7 L H H H L L L H H H H H H H 8 L H H H L L H H H H L L H H 9 L H H H L H L L L L L L L L Blank L H H H L H H L L L L L L L Blank L H H H H L L L L L L L L L Blank L H H H H L H L L L L L L L Blank L H H H H H L L L L L L L L Blank L H H H H H H H H H X X X X L L L L L L L Blank X = Don't care Depends on BCD code previously applied when LE = L NOTE: Display is blank for all illegal input codes (BCD > HLLH). function diagram D1 1 BCD Inputs D2 2 D3 LE BL 6 Driver 7 Decoder D0 3 Latch LT 13 12 11 10 9 15 14 5 4 VSS = 8 VDD = 16 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 a b c d e f g 7-Segment Outputs SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 logic diagram BL D3 4 13 a 6 D Q 12 b Latch LE LE LE LE Q 11 c D2 2 D Q Latch D1 LE LE LE LE 1 D 10 d Q Q Latch D0 LE LE LE LE 7 D Q 9 e Q Latch LE LE LE LE 15 f Q 14 g LE 5 LE LT 3 LE POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input diode current, IIK (VI < -0.5 V or VI > VCC + 0.5 V) ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output diode current, IOK (VO < -0.5 V or VO > VCC + 0.5V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Lead temperature (during soldering): At distance 1/16 1/32 in (1.59 0.79 mm) from case for 10 s maximum . . . . . . . . . . . . . . . . . . . . . 265C Unit inserted into a PC board (minimum thickness 1/16 in, 1.59 mm), with solder contacting lead tips only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions for 'HC4511 (see Note 3) VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage TA = -55C TO 125C TA = -40C TO 85C MIN MAX MIN MAX MIN MAX 2 6 2 6 2 6 1.5 1.5 1.5 3.15 3.15 3.15 4.2 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage Input transition (rise and fall) time TA = 25C 0 VCC = 2 V VCC = 4.5 V UNIT V 0.5 0.5 0.5 1.35 1.35 1.35 1.8 1.8 1.8 VCC VCC 0 0 VCC VCC 0 0 V VCC VCC 1000 1000 1000 500 500 500 V V V ns VCC = 6 V 400 400 400 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 recommended operating conditions for CD74HCT4511 (see Note 4) VCC VIH Supply voltage VIL VI Low-level input voltage VO tt Output voltage High-level input voltage TA = 25C TA = -55C TO 125C TA = -40C TO 85C MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 2 2 Input voltage Input transition (rise and fall) time 2 UNIT V V 0.8 0.8 0.8 V VCC VCC VCC VCC VCC VCC V 500 500 500 ns V NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 'HC4511 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -20 A VOH VI = VIH or VIL IOH = -7.5 mA IOH = -10 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 VCC TA = 25C TA = -55C TO 125C TA = -40C TO 85C MIN MIN MIN MAX 2V 1.9 1.9 1.9 4.5 V 4.4 4.4 4.4 6V 5.9 5.9 5.9 4.5 V 3.98 3.7 3.84 6V 5.48 5.2 UNIT MAX V 5.34 2V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 6V 0.1 0.1 0.1 4.5 V 0.26 0.4 0.33 6V 0.26 0.4 0.33 6V 0.1 1 1 A 6V 8 160 80 A 10 10 10 pF Ci POST OFFICE BOX 655303 MAX * DALLAS, TEXAS 75265 V 5 SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 CD74HCT4511 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25C VCC MIN VOH VI = VIH or VIL IOH = -20 A IOH = -4 mA 4.5 V VOL VI = VIH or VIL IOL = 20 A IOL = 4 mA 4.5 V II ICC VI = VCC to GND VI = VCC or 0, ICC IO = 0 One input at VCC - 2.1 V, Other inputs at 0 or VCC TYP MAX TA = -55C TO 125C TA = -40C TO 85C MIN MIN MAX 4.4 4.4 4.4 3.98 3.7 3.84 UNIT MAX V 0.1 0.1 0.1 0.26 0.4 0.33 5.5 V 0.1 1 1 A 5.5 V 8 160 80 A 360 490 450 A 4.5 V to 5.5 V 100 V Ci 10 10 10 pF Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. HCT INPUT LOADING TABLE INPUT UNIT LOADS LT, LE 1.5 BL, Dn 0.3 Unit load is ICC limit specified in electrical characteristics table, e.g., 360 A maximum at 25C. 'HC4511 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC tw tsu th 6 Pulse duration, LE low Setup time, BCD inputs before LE Hold time, BCD inputs before LE POST OFFICE BOX 655303 TA = 25C TA = -55C TO 125C TA = -40C TO 85C MIN MIN MIN MAX MAX 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 60 90 75 4.5 V 12 18 15 6V 10 15 13 2V 3 3 3 4.5 V 3 3 3 6V 3 3 3 * DALLAS, TEXAS 75265 UNIT MAX ns ns ns SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 'HC4511 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) Dn TO (OUTPUT) Output Output BL Output tt Output Any MIN MIN 2V 300 450 375 CL = 50 pF 60 90 75 51 77 64 2V 270 405 340 4.5 V 54 81 68 6V 46 69 58 2V 220 330 275 4.5 V 44 66 55 37 56 47 2V 160 240 200 4.5 V 32 48 40 6V 27 41 34 MIN TYP MAX 6V CL = 50 pF CL = 50 pF 5V 5V CL = 50 pF 5V MAX 23 ns 18 CL = 15 pF 5V 2V 75 110 95 CL = 50 pF 4.5 V 15 22 19 6V 13 19 16 POST OFFICE BOX 655303 UNIT MAX 25 6V CL = 15 pF LT TA = -40C TO 85C 4.5 V CL = 15 pF tpd TA = -55C TO 125C VCC CL = 15 pF LE TA = 25C LOAD CAPACITANCE 13 * DALLAS, TEXAS 75265 ns 7 SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 CD74HCT4511 timing requirements over recommended operating free-air temperature range VCC = 4.5 V (unless otherwise noted) (see Figure 2) TA = 25C TA = -55C TO 125C TA = -40C TO 85C MIN MIN MIN MAX MAX UNIT MAX tw tsu Pulse duration, LE low 16 24 20 ns Setup time, BCD inputs before LE 16 24 20 ns th Hold time, BCD inputs before LE 5 5 5 ns CD74HCT4511 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) Dn Output LE Output tpd BL LT tt Output Output Any LOAD CAPACITANCE VCC CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V TA = 25C MIN TYP MAX TA = -55C TO 125C TA = -40C TO 85C MIN MIN MAX UNIT MAX 60 90 75 54 81 68 44 66 55 33 50 41 15 22 19 25 CL = 15 pF 5V CL = 50 pF 4.5 V 23 CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V ns 18 13 ns operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd TYP Power dissipation capacitance Cpd is used to determine the dynamic power consumption, per package. PD = Cpd VCC2 fi + CL VCC2 fo where: fi = input frequency fo = output frequency CL = output load capacitance VCC = supply voltage 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 'HC4511 114 CD74HCT4511 110 UNIT pF SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION - 'HC4511 VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 k tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output 90% tf tf VCC VOH 50% VCC 10% VOL tf 50% 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% VCC 0V tPLZ tPZL VCC Output Waveform 1 (see Note B) 50% VCC Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL VCC Output Control tPLH 50% VCC 10% VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 50% VCC 90% VOH 0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SCHS279D - DECEMBER 1998 - REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION - CD74HCT4511 VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 k tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output 90% tf tf VCC VOH 50% VCC 10% VOL tf 50% 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% VCC 0V tPLZ tPZL VCC Output Waveform 1 (see Note B) 50% VCC Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL VCC Output Control tPLH 50% VCC 10% VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 50% VCC 90% VOH 0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish 5962-8773301EA ACTIVE CDIP J 16 1 TBD Call TI CD54HC4511F3A ACTIVE CDIP J 16 1 TBD A42 MSL Peak Temp Samples (Requires Login) Call TI N / A for Pkg Type CD74HC4511E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4511EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC4511M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC4511PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 5-Sep-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp CD74HC4511PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CD74HCT4511E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT4511EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (3) Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC4511, CD74HC4511 : * Catalog: CD74HC4511 * Military: CD54HC4511 Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4511M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4511PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4511PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4511M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4511PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4511PWT TSSOP PW 16 250 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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