M45PE10-VMP6T - STMicroelectronics

1/34October 2005

M45PE10

1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory

With Byte-Alterability and a 33 MHz SPI Bus Interface

FEATURES SUMMARY

■1Mbit of Page-Erasable Flash Memory

■Page Write (up to 256 Byt es) in 11ms (typica l)

■Page Program (up to 256 Bytes) in 1.2ms

(typical)

■Page Erase (256 By tes) in 10 m s (typical)

■Sector Erase (512 Kbit)

■2.7 to 3.6V Single Supply Voltage

■SPI Bus Compatible Serial Interface

■33MHz Clock Rate (maximum)

■Deep Power-down Mode 1µA (typical)

■Electronic Signature

– JEDEC Standard Two-Byte Signature

(4011h)

■More than 100,000 Write Cycles

■More than 20 Year Data Retention

■Packages

– ECOPACK® (RoHS compliant)

Figure 1. Packag e s

SO8 (MN)

150 mil width

VDFPN8 (MP)

(MLP8)

M45PE10

2/34

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Reset (Reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Page Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3/34

M45PE10

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

M45PE10

4/34

SUMMARY DESCRIPTION

The M45PE10 is a 1Mbit (128K x 8 bit) Serial

Paged Flash Memory accessed by a high speed

SPI-compatible bus.

The memory can be written or programmed 1 to

256 bytes at a time, u sing t he Page Writ e o r Page

Program instruction. The Page Write instruction

consists of an integrated Page Erase cycle fol-

lowed by a Page Program cycle.

The memory is organized as 2 sectors, each con-

taining 256 pages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 512 pages, or 131,072 bytes.

The memory can be erased a page at a time, using

the Page Erase instruction, or a sector at a time,

using the Sector Erase instruction.

In order to meet environmental requirements, ST

offers these devices in ECOPACK® packages.

ECOPACK® packages are Lead-free and RoHS

compliant.

ECOPACK is an ST trademark. ECOPACK speci-

fications are available at: www.st.com.

Figure 2. Logic Diagram

Figure 3. SO and VDFPN Connections

Note: 1. There is an exposed die pad dle on the undersi de of the

MLP8 package. This is pulled, internally, to VSS, and

must not be al lowed to be connecte d to any oth er voltage

or signal li ne on the PCB.

2. See PACKAGE MECHANICAL section for package di-

mensions, and how to identify pin-1.

Table 1. Signal Names

Reset

AI07403

VCC

M45PE10

VSS

DC Serial Clock

D Serial Data Input

Q Serial Data Output

SChip Select

W Write Protect

Reset Reset

VCC Supply Voltage

VSS Ground

AI07404

5WS VCC

VSS

Reset

M45PE10

5/34

M45PE10

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input signal is used to

transfer data ser ially into the device. It rece ives in-

structions, addresses, and the data to be pro-

grammed. Values a re latched on the rising e dge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the serial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high imped ance. Unless an internal Read ,

Program, Erase or Write cycle is in progress, the

device will be in the Standby Power mode (this is

not the Deep Power-down mode). Driving Chip

Select (S) Low selects the device, placing it in the

Active Power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Reset (Reset). The Reset (Reset) input provides

a hardware reset for the memory. In this mode, the

outputs are high impedance.

When Reset ( Reset) is driven High, the memory is

in the normal operating mode. When Reset (Re-

set) is driven Low, the memory will enter the Reset

mode, provided that no internal operation is cur-

rently in progress. Driving Reset (Reset) Low while

an internal operation is in progress has no effect

on that internal operation (a write cycle, program

cycle, or erase cycle).

Write Protect (W). This input signal puts the de-

vice in the Hardware Protected mode, when Write

Protect (W ) is connected to VSS, causing the first

256 pages of memory to become read-only by pro-

tecting them from write, program and erase oper-

ations. When Write Protect (W) is connected to

VCC, the first 256 pages of memory behave like

the other pages of memory.

M45PE10

6/34

SPI MODES

These de vices can be driv en by a micro controller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference bet ween th e two mod es, as shown

in Figure 5., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus Master and Memory Device s on the SPI Bus

Note: The Write Protect (W) signal should be driven, High or Low as appropriate.

Figure 5. SPI Modes Supported

AI04043B

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WRP WRP WRP

AI01438B

MSB

CPHA

CPOL

MSB

7/34

M45PE10

OPERATING FEATURES

Sharing the Overhead of Modifying Data

To write or prog ram on e ( or more) da ta bytes, two

instructions are required: Write Enable (WREN),

which is one byte, and a Page Write (PW) or Page

Program (PP) sequence, which consists of four

bytes plus data. This is followed by the int ernal cy-

cle (of duration tPW or tPP).

To share this overhead, the Page Write (PW) or

Page Program (PP) instruction allows up to 256

bytes to be programmed (changing bits from 1 to

0) or written (changing bits to 0 or 1) at a time, pro-

vided that they lie in consecutive addresses on the

same page of memory.

An Easy Way to Modify Data

The Page Write (PW) instruction provides a con-

venient way of modifying data (up to 256 contigu-

ous bytes at a time), and simply requires the start

address, and the new data in the instruction se-

quence.

The Page Write (PW) instruction is entered by

driving Chip Select (S) Low, and then transmitting

the instruction byte, thr ee ad dres s byte s ( A23-A0 )

and at least one data byte, and then driving Chip

Select (S) High. While Chip Select (S) is being

held Low, the data bytes are written to the data

buffer, star ting at the ad dress given in the th ird ad-

dress byte (A7-A0). When Chip Select (S) is driven

High, the Write cycle starts. The remaining, un-

changed, bytes of the data buffer are automatically

loaded with the values of the corresponding bytes

of the addressed memory page. The addressed

memory page then aut omatically put into an Erase

cycle. Finally, the addressed memory page is pro-

grammed with the contents of the data buffer.

All of this buffer management is handled internally,

and is transparent to the user. The user is given

the facility of being able to alter the contents of the

memory on a byte-by-byte ba sis.

For optimized timings, it is recommended to use

the Page Write (PW) instruction to write all con-

secutive targeted Bytes in a single sequence ver-

sus using several Page Write (PW) sequences

with each containing only a few Bytes (see Page

Write (PW) and AC Characteristics (33MHz oper-

ation)).

A Fast Way to Modify Data

The Page Program (PP) instruction provides a fast

way of modifying d ata (up to 256 contig uous bytes

at a time), provided that it only involves resetting

bits to 0 that had previously been set to 1.

This might be:

– when the designer is programming the device

for the first time

– when the designer knows that the page has

already been erased by an earlier Page Erase

(PE) or Sector Erase (SE) instruction. This is

useful, for example, when storing a fast

stream of data, having first performed the

erase cycle when time was availabl e

– when the designer knows that the only

changes involve resetting bits to 0 that are still

set to 1. When this method is possible , it has

the additional advantage of minimising the

number of unnecessary erase operations, and

the extra stress incurred by each page.

For optimized timings, it is recommended to use

the Page Program (PP) instruction to program all

consecutive targeted Bytes in a single sequence

versus using several Page Program (PP) se-

quences with each containing only a few Bytes

(see Page Program (PP) and AC Characteristics

(33MHz operation)).

Polling Durin g a Write, Program or Erase Cyc le

A further improvement in the write, program or

erase time can be achieved by not waiting for the

worst case delay (tPW, tPP, tPE, or tSE). The Write

In Progress (WIP) bit is provided in the Status

itor its value, polling it to establish when the previ-

ous cycle is complete.

Reset

An internal Power On Reset circuit helps protect

against inadvertent data writes. Addition protec-

tion is provided by driving Reset (Reset) Low dur-

ing the Power-on process, and only driving it High

when VCC has reached the correct voltage level,

VCC(min).

Active Power, Standby Power and Deep

Power-Down Modes

When Chip Select (S) is Low, the device is select-

ed, and in the Active Power mode.

When Chip Select (S) is High, the device is dese-

lected, but coul d remain in the Active Power mode

until all internal cycles have completed (Program,

Erase, Write). The device then goes in to the

Standby Power mode. The device consumption

drops to ICC1.

The Deep Power-down mode is entered whe n the

specific instruction (the Deep Power-down (DP) in-

struction) is executed. The device consumption

drops further to ICC2. The device remains in this

mode until another specific instruction (the Re-

lease from De ep Powe r-down and Read Elect ron-

ic Signature (RES) instruction ) is executed.

All other instructions are ignored while the device

is in the Deep Power-down mode. This can be

used as an extra software protection mechanism,

when the device is not in a ctive use , to pro tect the

device from inadvertent Write, Program or Erase

instructions.

M45PE10

8/34

Status Register

The Status Register contains two status bits that

can be read by the Read Status Register (RDSR)

instruction.

WIP bit. The Write In Progress (WIP) bit indicates

whether the me mory is busy with a Write, Program

or Erase cycle.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the st atus of the internal Writ e Enable Latch.

Table 2. Status Register Format

Note: WEL and WIP are volatile read-only bits (WEL is se t an d re -

set by specific instructions; WIP is automatically set and re-

set by the internal logic of the device).

Protection Modes

The environments where non-vola tile memory de-

vices are used can be very noisy. No SPI device

can operate correc tly in the presence of excessive

noise. To help combat this, the M45PE10 features

the following data protection mechanisms:

■Power On Reset and an internal timer (tPUW)

can provide protection ag ainst inadvertant

changes while the power supply is outside the

operating specification.

■Program, Erase and Write instructions are

checked that they consist of a number of clock

pulses that is a multiple of eight, before they

are accepted for execution.

■All instructions that modify data must be

preceded by a Write Enable (WREN)

instruction to set th e Writ e En ab le La tc h

(WEL) bit. This bit is returned to its reset state

by the following events:

– Power-up

– Reset (RESET) driven Low

– Write Disable (WRDI) instruction

completion

– Page Write (PW) instruction completion

– Page Program (PP) instruction completion

– Page Erase (PE) instruction completion

– Sector Erase (SE) instruction completion

■The Hardware Prot ected mode is entere d

when Write Protect (W) is driven Low, causing

the first 256 pages of memory to become

read-only. When Write Protect (W) is driven

High, the first 256 pages of memory behave

like the other pa ge s of mem o ry

■The Reset (Reset) signal can be driven Low to

protect the contents of the memory during any

critical time , not just during Power-up and

Power-down.

■In addition to the low power consumption

feature, the Deep Power-down mode offers

extra software prot ection from inadvertant

Write, Program and Erase instructions while

the device is not in active use.

b7 b0

0 0 0 0 0 0 WEL WIP

9/34

M45PE10

MEMORY ORGANIZATION

The memory is organized as:

■512 pages (256 bytes each).

■131,072 bytes (8 bits each)

■2 sectors (512 Kbits, 65536 bytes each)

Each page can be individually:

– programmed (bits are programmed from 1 to

– erased (bits are erased from 0 to 1)

– written (bits are changed to either 0 or 1)

The device is Page or Sector Erasable (bits are

erased from 0 to 1).

Table 3. Memory Organizatio n

Figure 6. Block Diagram

Sector Address Range

1 10000h 1FFFFh

0 00000h 0FFFFh

AI07405

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Status

00000h

1FFFFh

000FFh

Reset

10000h

First 256 Pages can

be made read-only

M45PE10

10/34

INSTRUCTIONS

All instructions, addresses and data are shifted in

and out of the device, most significa n t bit firs t.

Serial Data Input (D) is sampled on the first rising

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in to the device, most significant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Serial Clock (C).

The instruction set is listed in Table 4.

Every instruc tion sequence star ts with a one-byte

instruction code. Depending on the instruction,

this might be followed by address bytes, or by data

bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read

Data Bytes at Higher Speed (Fast _Read) or Re ad

Status Register (RDSR) in struction, the shifted-in

instruction sequence is followed by a da ta-ou t se-

quence. Chip Select (S) can be driven High after

any bit of the data-out sequence is being shifted

out.

In the case of a Page Write (PW), Page Program

(PP), Page Erase (PE), Sector Erase (SE), Write

Enable (WREN), Write Disable (WRDI), Deep

Power-down (DP) or Release from Deep Power-

down (RDP) instruction, Chip Select (S) must be

driven High exactly at a byte boundary, otherwise

the instruction is rejected, and is not executed.

That is, Chip Select (S) must driven High when the

number of clock pulses afte r Chip Select (S) b eing

driven Low is an exact multiple of eight.

All attempts to ac cess the memory arr ay during a

Write cycle, Program cycle or Erase cycle are ig-

nored, and th e internal Wr ite cycle, Progr am cycle

or Erase cycle continues unaffected.

Table 4. Instruction Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PW Page Write 0000 1010 0Ah 3 0 1 to 256

PP Page Program 0000 0010 02h 3 0 1 to 256

PE Page Erase 1101 1011 DBh 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RDP Release from Deep Power-down 1010 1011 ABh 0 0 0

11/34

M45PE10

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7.)

sets the Write Enable La tch (WEL) bit.

The Write Enable La tch ( WEL) bit must be set pri-

or to every Page Wr ite ( PW) , Page Pr ogr am (PP),

Page Erase (PE), and Sector Erase (SE) instruc-

tion.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 7. Write Enable (WREN) Instruction Sequence

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8.)

resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and th en driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

–Power-up

– Write Disable (WRDI) instruction completion

– Page Writ e (PW) instruction comple tio n

– Page Program (PP) instr uction completion

– Page Erase (PE) instruction completion

– Sector Erase (SE) instruction completion

Figure 8. Write Disable (WRDI) Instruction Sequence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

M45PE10

12/34

Read Identification (RDID)

The Read Identification (RDID) instruction allows

the 8-bit manufacturer identification to be read, fol-

lowed by two bytes of device identification. The

manufacturer identifica tion is assigned by JEDEC,

and has the va lue 20h for STMicroelectronics. The

device identification is assigned by the device

manufacturer, and indicates the memory type in

the first byte (40h), and the memory capacity of the

device in the second byte (11h).

Any Read Identification (RDID) instruction while

an Erase or Program cycle is in progress, is not

decoded, and has no effect on the cycle that is in

progress.

The device is first selec ted by driving Chip Select

(S) Low. Then , the 8-bi t instruction co de for th e in-

struction is shifted in. This is followed by the 24-bit

device identification, stored in the memory, being

shifted out on Serial Data Output (Q), each bit be-

ing shifted out during the falling edge of Serial

Clock (C).

The instruction sequence is shown in Figure 9.

The Read Identification (RDID) instruction is termi-

nated by driving Chip Select (S) High at any time

during data output.

When Chip Select (S) is driven High, the device is

put in the Standby Power mode. Once in the

Standby Power mode, the device waits to be se-

lected, so that it can receive, decode and execute

instructions.

Table 5. Read Identification (RDID) Data-Out Sequence

Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

Manufacturer Identification Device Identification

Memory Type Memory Capacity

20h 40h 11h

21 3456789101112131415

Instruction

AI06809

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 16 18 28 29 30 31

13/34

M45PE10

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Erase or Write cycle is in progress.

When one of these cycles is in progress, it is rec-

ommended to check the Write In Progress (WIP)

bit before sending a new instruction to the device.

It is also possible to read the Status Register con-

tinuously, as shown in Figure 10.

The status bits of the Status Register are as fol-

lows:

WIP bit. The Write In Progress (WIP) bit indicat es

whether the m emory is busy with a Write, Prog ram

or Erase cycle. When set to 1, such a cycle is in

progress, when reset to 0 no such cycle is in

progress.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status o f the internal Write Enable Lat ch.

When set to 1 the internal Write Enable Latch is

set, when set to 0 the internal Write Enable Latch

is reset and no Write, Program or Erase instruction

is accepted.

Figure 10. Read Status Register (RDSR) Instruction Se quence and Data-Out Sequence

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

M45PE10

14/34

Read Data Bytes (READ)

The device is first selec ted by driving Chip Select

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0) , each bit being latched-in d uring

the rising edge o f Serial Clock (C). Then t he mem-

ory contents, at that addr ess, is sh ift ed out on Se -

rial Data Output (Q), each bit being shifted out, at

a maximum frequency fR, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 11.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The wh ole memory can, therefore, be r ead

with a single Read Data Bytes (READ) instruction.

When the highe st address is reached, the addr ess

counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is termi-

nated by driving Chip Select (S) High. Chip Select

(S) can be driven High at any time dur ing data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rejected without having any e ffects on

the cycle that is in prog re ss .

Figure 11. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

Note: Address bits A23 to A17 are Don’t Care.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

15/34

M45PE10

Read Data Bytes at Higher Speed

(FAST_READ)

The device is first selec ted by driving Chip Select

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of Serial Clock (C). Then the memory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The wh ole memory can, therefore, be r ead

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is termin at ed b y driving

Chip Select (S) High. Chip Select (S) can be driv-

en High at any time during data output. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 12. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out

Sequence

Note: Address bits A23 to A17 are Don’t Care.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

M45PE10

16/34

Page Write (PW)

The Page Write (PW) instruction allows bytes to

be written in th e memo ry. Bef ore it can be accept -

ed, a Write Enable (WREN) instructio n must previ-

ously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device

sets the Write Enable La tch (WEL).

The Page Write (PW) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Ser ial Data Input (D). The rest o f

the page remains unchanged if no power failure

occurs during this write cycle.

The Page Write (PW) instruction performs a page

erase cycle even if only one byte is updated.

If the 8 least significant address bits (A7-A0) are

not all zero, all transmitt ed data exceeding the ad-

dressed page boundary wrap round, and are writ-

ten from the start address of the same page (the

one whose 8 least significan t address b its (A7-A0 )

are all zero). Chip Select (S) must be driven Low

for the entire du ration of the sequence.

The instruction sequence is shown in Figure 13..

If more than 2 56 byte s are sent t o the d evice, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be written correctly

within the same page. If less than 256 Data bytes

are sent to device, they are corre ctly writt en at the

requested addresses without having any effects

on the other b ytes of the sa me page.

For optimized timings, it is recommended to use

the Page Write (PW) instruction to write all con-

secutive targeted Bytes in a single sequence ver-

sus using several Page Write (PW) sequences

with each containing only a few Bytes (see AC

Characteristics (33MHz operation) ).

Chip Select (S) must be driven High after the

eighth bit of the last dat a byte has been latched in,

otherwise the Page Write (PW) instruction is not

executed.

As soon as Chip Select (S) is driven High, the self-

timed Page Write cycle (whose duration is tPW) is

initiated. While the Page Write cycle is in progress,

the Status Register may be read to check the val-

ue of the Write In Prog re ss ( WIP) bit . The Wr ite In

Progress (WIP) bit is 1 during the self-timed Page

Write cycle, and is 0 when it is completed. At some

unspecifie d time before the cycle is com plete, the

Write Enable Latch (WEL) bit is reset.

A Page Write (PW) instruction applied to a page

that is Hardware Protected is not executed.

Any Page Write (PW) instruction, while an Erase,

Program or Write cycle is in progress, is rejected

without having any effects on the cycle that is in

progress.

Figure 13. Page Write (PW) Instruction Sequence

Note: 1. Addre ss bits A23 to A17 are Do n’t Car e

2. 1 ≤ n ≤ 256

AI04045

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte n

765432 0

MSB MSB

MSB MSB MSB

17/34

M45PE10

Page Program (PP)

The Page Program (PP) instruction allows bytes to

be programmed in the memory (changing bits from

1 to 0, only). Before it can be accepted, a Write En-

able (WREN) instruction must previously have

been executed. After the Write Enable (WREN) in-

struction has been decoded, the device sets the

Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted data exceeding the ad-

dressed page boundary wrap round, and are pro-

grammed from th e start address of the sam e page

(the one whose 8 least significant address bits

(A7-A0) are all zero). Chip Select (S) must be driv-

en Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14..

If more than 2 56 byte s are sent t o the d evice, pre-

viously latched data are discarded and the last 256

data bytes a re guara nteed to be programm ed cor-

rectly within the same page. If less than 256 Data

bytes are sent to device, they are correctly pro-

grammed at the r equested addresses without hav-

ing any effects on the other bytes of the same

page.

For optimized timings, it is recommended to use

the Page Program (PP) instruction to program all

consecutive targeted Bytes in a single sequence

versus using several Page Program (PP) se-

quences with each containing only a few Bytes

(see AC Characteristics (33MHz operation)).

Chip Select (S) must be driven High after the

eighth bit of the last dat a byte has been latched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chip Select (S) is driven High, the self-

timed Page Program cycle (whose duration is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of t he Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Page Program (PP) instruction applied to a page

that is Hardware Protected is not executed.

Any Page Program (PP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without having any effe cts on the cycle th at

is in progress.

Figure 14. Page Program (PP) Instruction Sequence

Note: 1. Addre ss bits A23 to A17 are Do n’t Car e

2. 1 ≤ n ≤ 256

AI04044

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte n

765432 0

MSB MSB

MSB MSB MSB

M45PE10

18/34

Page Erase (PE)

The Page Erase (PE) instr uction sets to 1 (FFh) all

bits inside the chosen page. Before it can be ac-

cepted, a Write Enable (WREN) instruction must

previously have been executed. After the Write

Enable (WREN) instruction has been decoded,

the device sets the Write Enable Latch (WEL).

The Page Erase (PE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address bytes on Serial

Data Input (D). Any address inside the Page is a

valid addres s for the Pa ge Er ase (PE) in structio n.

Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 15..

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Page Erase (PE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Page Erase cycle (whose du-

ration is tPE) is initiated. While the Page Erase cy-

cle is in progress, t he Status Register may be r ead

to check the value of the Write In Progress (WIP)

bit. The Write I n Progr ess (WIP) bit is 1 d uri ng the

self-timed Page Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Page Erase (PE) instruction applied to a page

that is Hardware Protected is not executed.

Any Page Erase (PE) instruction, while an Erase,

Program or Write cycle is in progress, is rejected

without having any effects on the cycle that is in

progress.

Figure 15. Page Erase (PE) Instruction Sequence

Note: Address bits A23 to A17 are Don’t Care.

24 Bit Address

AI04046

21 3456789 293031

Instruction

23 22 2 0

MSB

19/34

M45PE10

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instr uction has been decod-

ed, the device sets the Write Enab le Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address bytes on Serial

Data Input (D). Any address inside the Sector ( see

Table 3.) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 16..

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, t he Status Register may be r ead

to check the value of the Write In Progress (WIP)

bit. The Write I n Progr ess (WIP) bit is 1 d uri ng the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Sector Erase (SE) instru ction applied to a sector

that contains a pa ge that is Hardware Protected is

not executed.

Any Sector Erase (SE) instruction, while an Erase,

Program or Write cycle is in progress, is rejected

without having any effects on the cycle that is in

progress.

Figure 16. Sector Erase (SE) Instruction Sequence

Note: Address bits A23 to A17 are Don’t Care.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M45PE10

20/34

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction

is the only wa y to put the device in the lowe st con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, w hile the device is not in active us e,

since in this mode, the device ignores all Write,

Program and Erase instructions.

Driving Chip Select (S) High deselects the device,

and puts the device in the Standby Power m ode (if

there is no internal cycle currently in progress). But

this mode is n ot the Deep Po wer-down mode. The

Deep Power-down mode can only be entered by

executing the Deep Power-down (DP) instruction,

to reduce the standby current (from ICC1 to ICC2,

as specified in Table 11.).

Once the device has entered the Deep Power-

down mode, all instruction s are ignored except the

Release from Deep Power-down (RDP) instruc-

tion. This relea se s th e de vice fro m this mo d e.

The Deep Power-down mode automatically stops

at Power-do wn, and the device always Power s-up

in the Standby Power mode.

The Deep Power-do wn (DP) in structio n is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Input (D). Chip Se-

lect (S) must be driven Low for the entire duration

of the sequence.

The instruction sequence is shown in Figure 17..

Chip Select (S) must be driven High after the

eighth bit of the instruction code has been latched

in, otherwise th e Deep Power-down (DP) instruc-

tion is not executed. As so on as Ch ip Select ( S ) is

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without having any effe cts on the cycle th at

is in progress.

Figure 17. Deep Power-down (DP) Instruction Sequence

AI03753D

21 345670t

Deep Power-down Mode

Stand-by Mode

Instruction

21/34

M45PE10

Release from Deep Power-down (RDP)

Once the device has entered the Deep Power-

down mode, all instruction s are ignored except the

Release from Deep Power-down (RDP) instruc-

tion. Executing this instruction takes the device out

of the Deep Power-down mode.

The Release from Deep Power-down (RDP) in-

struction is entered by driving Chip Select (S) Low,

followed by the instruct ion code on Serial Data In-

put (D). Chip Select (S ) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 18..

The Release from Deep Power-down (RDP) in-

struction is terminated by driving Chip Select (S)

High. Sending additional clock cycles on Serial

Clock (C), while Chip Select (S) is driven Low,

cause the instruction to be rejected, and not exe-

cuted.

After Chip Select (S) has been driven High, fol-

lowed by a delay, tRDP, the device is put in the

Standby Power mode. Chip Select (S) must re-

main High at least until this period is over. The de-

vice waits to be selected, so that it can receive,

decode and execute inst ructions.

Any Release from Deep Power-down (RDP) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 18. Release from Deep Power-down (RDP) Instruction Sequence

AI06807

21 345670tRDP

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

M45PE10

22/34

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selecte d (that is Chip Select (S) must follow

the voltage applied on VCC) until VCC reaches the

correct value:

–V

CC(min) at Power-up, and t hen for a further

delay of tVSL

–V

SS at Power-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to ensure safe and proper Power-up

and Power-down.

To avoid data corruption an d inadve rtent writ e op-

erations during power up, a Power On Reset

(POR) circuit is included. The logic inside the de-

vice is held reset while VCC is less than the Power

On Reset (POR) threshold value, VWI – all opera-

tions are disabled, and the device does not re-

spond to any instruction.

Moreover, the device ignores all Write Enable

(WREN), Page Write (PW), Page Program (PP),

Page Erase (PE) and Sector Erase (SE) instruc-

tions until a time delay of tPUW has elapsed after

the moment that VCC rises above the VWI thresh-

old. However, the correct operation of the device

is not guaranteed if, by this time, VCC is still below

VCC(min). No Write, Program or Erase instructions

should be sent until the later of:

–t

PUW after VCC passed the VWI threshold

–t

VSL after wrap roundVCC passed the

VCC(min) level

These values are specified in Table 6..

If the delay, tVSL, has elapsed, aft er VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not yet

fully elapsed.

As an extra protection, the Reset (Reset) signal

can be driven Low for the whole duration of the

Power-up and Power-down phases.

At Power-up, the device is in the following state:

– The device is in the Standby Power mode (not

the Deep Power-down mode).

– The Write Enab le La tc h (WE L) bit is rese t.

Normal precautions must be taken for supply rail

decoupling, to stabilize the VCC supply. Eac h de-

vice in a system should have the VCC rail decou-

pled by a suitable capacitor close to the package

pins. (Generally, this capacitor is of the order of

0.1µF).

At Power-down, when VCC drops f rom the opera t-

ing voltage, to below the Power On Reset (POR)

threshold value, VWI, all operations are disabled

and the device does not respond to any instruc-

tion. (The designer needs to be aware that if a

Power-down occurs while a Write, Program or

Erase cycle is in progress, some data corruption

can result.)

Figure 19. Power-up Timing

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

23/34

M45PE10

Table 6. Power-Up Timing and VWI Threshold

Note: 1. These parameters are characterized only, over the temperature range –40°C to +85°C.

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh). All usable Status Register bits are 0.

MAXIMUM RATING

Stressing the device outside the ratings listed in

Table 7. may cause pe rmanent damage t o the de-

vice. These are stress ratings only, and operation

of the device at these, or any other conditions out-

side those indicated in the Operating sections of

this specification, is not implied. Exposure to Ab-

solute Maximum Rating conditions for extended

periods may affect device reliability. Refer also to

the STMicroelectronics SURE Program and other

relevant quality documents.

Table 7. Absolut e Maximum Ratings

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 spec ificat ion, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

tVSL1VCC(min) to S low 30 µs

tPUW1Time delay before the first Write, Program or Erase instruction 1 10 ms

VWI1Write Inhibit Voltage 1.5 2.5 V

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1°C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V

M45PE10

24/34

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 8. Operating Conditions

Table 9. AC Measurement Conditions

Note: Output Hi-Z is defined as th e point where data out is no longer driven.

Figure 20. AC Measurement I/O Waveform

Table 10. Capacitance

Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmbient Operating Temperature –40 85 °C

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V

Symbol Parameter Test Condition Min. Max. Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

25/34

M45PE10

Table 11. DC Characteristics

Symbol Parameter Test Condition

(in addition to those in Table 8.)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current

(Standby and Reset modes) S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Po wer-down Current S = VCC, VIN = VSS or VCC 10 µA

ICC3 Operating Current

(FAST_READ) C = 0.1VCC / 0.9.VCC at 25MHz, Q = open 6mA

C = 0.1VCC / 0.9.VCC at 33MHz, Q = open 8

ICC4 Operating Current (PW) S = VCC 15 mA

ICC5 Operating Current (SE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Voltage 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6 mA 0.4 V

VOH Output High Voltage IOH = –100 µAV

CC–0.2 V

M45PE10

26/34

Table 12. AC Characteristics (25MHz operation)

Note: 1. tCH + tCL must be greater than or equal to 1/ fC(max)

2. Value guaranteed by characterization, not 100% tested in production.

3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all

the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256)

Test conditions specified in Table 8. and Table 9.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following

instructions: FAST_READ, PW, PP, PE,

SE, DP, RDP, WREN, WRDI, RDSR D.C. 25 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH 1tCLH Clock High Time 18 ns

tCL 1tCLL Clock Low Time 18 ns

Clock Slew Rate 2 (peak to peak) 0.03 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Setup Time (relative to C) 10 ns

tSHSL tCSH S Deselect Time 200 ns

tSHQZ 2tDIS Output Disable Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO Output Hold Time 0 ns

tRLRH 2tRST Reset Pulse Width 10 µs

tRHSL tREC Reset Recovery Time 3 µs

tSHRH Chip should have been deselected

before Reset is de-asserted 10 ns

tWHSL Write Protect Setup Time 50 ns

tSHWL Write Protect Hold Time 100 ns

tDP 2S to Deep Power-down 3 µs

tRDP 2S High to Standby Power mode 30 µs

tPW (3) Page Write Cycle Time (256 Bytes) 11 25 ms

Page Write Cycle Time (n Bytes) 10.2+

n*0.8/256

tPP (3) Page Program Cycle Time (256 Bytes) 1.2 5ms

Page Program Cycle Time (n Bytes) 0.4+

n*0.8/256

tPE Page Erase Cycle Time 10 20 ms

tSE Sector Erase Cycle Time 1 5 s

27/34

M45PE10

Table 13. AC Characteristics (33MHz operation)

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all

the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256)

4. Details of how to find the date of marking are given in Application Note, AN1995.

33MHz only available for products marked since week 40 of 2005(4)

Test conditions specified in Table 8. and Table 9.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock Frequency for the following

instructions: FAST_READ, PW, PP,

PE, SE, DP, RDP, WREN, WRDI,

RDSR

D.C. 33 MHz

fRClock Frequency for READ

instructions D.C. 20 MHz

tCH (1) tCLH Clock High Time 13 ns

tCL (1) tCLL Clock Low Time 13 ns

Clock Slew Rate 2 (peak to peak) 0.03 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 3 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Activ e Setup Time (relativ e to C) 5 ns

tSHSL tCSH S Deselect Time 200 ns

tSHQZ (2) tDIS Output Disable Time 12 ns

tCLQV tVClock Low to Output Valid 12 ns

tCLQX tHO Output Hold Time 0 ns

tTHSL Top Sector Lock Setup Time 50 ns

tSHTL Top Sector Lock Hold Time 100 ns

tDP (2) S to Deep Power-down 3 µs

tRDP (2) S High to Standby Power mode 30 µs

tPW (3) Page Write Cycle Time (256 Bytes) 11 25 ms

Page Write Cycle Time (n Bytes) 10.2+

n*0.8/256

tPP (3) Page Progr am Cycle Time (256 Bytes) 1.2 5ms

Page Program Cycle Time (n Bytes) 0.4+

n*0.8/256

tPE Page Erase Cycle Time 10 20 ms

tSE Sector Erase Cycle Time 1 5 s

M45PE10

28/34

Figure 21. Serial Input Timing

Figure 22. Write Protect Setup and Hold Timing

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

29/34

M45PE10

Figure 23. Output Timing

Figure 24. Reset AC Waveforms

AI01449D

LSB OUT

DADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

AI06808

Reset tRLRH

tRHSLtSHRH

M45PE10

30/34

PACKAGE MECHANICAL

Figure 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

Note: Drawing is not to scale.

Table 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27––0.050––

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO-a

LA1 α

h x 45˚

31/34

M45PE10

Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline

Note: Drawing is not to scale.

Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.20 0.1575 0.1496 0.1654

e 1.27 0.0500

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

θ12° 12°

VDFPN-01

eE2

M45PE10

32/34

PART NUMBERING

Table 16. Ordering Information Scheme

For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-

fice.

The category of second Level Interconnect is

marked on the package and on the inner box label,

in compliance with JEDEC Standar d JESD97. The

maximum ratings related to soldering conditions

are also marked on the inner box label.

Example: M45PE10 – V MP 6 T G

Device Type

M45PE = Serial Flash Memory for Data Storage

Device Function

10 = 1Mbit (128K x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MN = SO8 (150 mil width)

MP = VDFPN8 6x5mm (MLP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

P or G = ECOPACK® (RoHS compliant)

33/34

M45PE10

REVISION HISTORY

Table 17. Document Revision History

Date Version Description of Revision

29-Apr-2003 1.0 Document written

04-Jun-2003 1.1 Description corrected of entering Hardware Protected mode (W must be driven, and

cannot be left unconnected).

04-Dec-2003 1.2 VIO(min) e xtended to –0.6V, tPW(typ) and tPP(typ) improv ed. Table of c ontents, warning

about exposed paddle on MLP8, and Pb-free options added. Change of naming for

VDFPN8 package.

25-Jun-2004 1.3 Soldering temperature information clarified for RoHS compliant de vices. De vice Grade

clarified.

22-Sep-2004 2.0 Document promoted to Preliminar y Data. Minor wording changes

08-Oct-2004 3.0 Document promoted to Mature Datasheet. No other changes

4-Oct-2005 4.0

Added AC Characteristics (33MHz operation). An Easy Way to Modify Data, A Fast

Way to Modify Data, Page Write (PW) and Page Program (PP) sections updated to

explain optimal use of Page Write and Page Program instructions. Updated ICC3

values in Table 11., DC Characteristics. Updated Table 16., Ordering Information

Scheme. Added Ecopack® information.

M45PE10

34/34

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