©1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-2691/8
1
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
Features
◆◆
◆◆
◆High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 55ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT71321/IDT71421SA
—Active: 325mW (typ.)
—Standby: 5mW (typ.)
– IDT71321/421LA
—Active: 325mW (typ.)
—Standby: 1mW (typ.)
◆◆
◆◆
◆Two INT flags for port-to-port communications
Functional Block Diagram
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
1
◆◆
◆◆
◆MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
◆◆
◆◆
◆On-chip port arbitration logic (IDT71321 only)
◆◆
◆◆
◆BUSY output flag on IDT71321; BUSY input on IDT71421
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆Battery backup operation – 2V data retention (LA only)
◆◆
◆◆
◆TTL-compatible, single 5V ±10% power supply
◆◆
◆◆
◆Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/WL
CEL
OEL
BUSYL
A10L
A0L
2691 drw 01
I/O0L-I/O
7L
CEL
OEL
R/WL
INTL
BUSYR
I/O0R-I/O7R
A10R
A0R
INTR
CER
OER
(2)
(1,2) (1,2)
(2)
R/WR
CER
OER
R/WR
11
11
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
IDT71321/421J
J52-1(4)
PLCC
Top View(5)
INDEX
I/O
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
3L
2L
OE
A
A
A
A
A
A
A
A
A
A
NC
I/O
R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
4L
5L
6L
7L
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0R
1R
2R
3R
4R
6R
5R
A
0L
OE
A
INT
BUSY
R/W
CE
V
CE
R/W
BUSY
INT
A
L
10L
L
L
CC
R
R
R
10R
R
L
L
1
234567474849505152
9
8
10
11
12
13
14
15
16
17
18
19
20 27262524232221 333231302928
35
34
36
37
38
39
40
41
42
43
44
45
46
2691 drw 02
,
INDEX
IDT71321/421PF or TF
PN64-1 / PP64-1(4)
64-Pin TQFP
64-Pin STQFP
Top View(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33 I/O6R
N/C
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
OER
N/C
N/C
I/O2L
A0L
OEL
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
N/C
N/C
2691 drw 03
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
N/C
A
10R
N/C
N/C
A
10L
N/C
GND
N/C
N/C
GND
N/C
R/W
R
CE
R
V
CC
V
CC
BUSY
L
INT
L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
R/W
L
CE
L
BUSY
R
INT
R
,
Pin Configurations(1,2,3)
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs,
64-pin TQFPs, and 64-pin STQFPs.
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Recommended DC Operating
Conditions
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2) Te rmi nal Voltage
with Re spe ct
to GND
-0.5 to +7.0 V
TBIAS Temperature
Und e r B ias -55 to +125 oC
TSTG Storage
Temperature -55 to +125 oC
IOUT DC Output
Current 50 mA
2691 tbl 01
Grade
Ambient
Temperature
GND
Vcc
Commercial 0OC to + 70OC0V5.0V
+ 10%
Industrial -40OC to +85OC0V 5.0V
+ 10%
2691 tbl 02
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Sup p ly Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
In p u t H i g h Vol tage 2 . 2 ____ 6.0(2) V
V
IL
Inp ut Lo w Vo l tag e -0 .5(1) ____ 0.8 V
2691 tbl 03
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Inp ut Cap ac i tance V
IN
= 3dV 9 pF
C
OUT
Output Cap acitance V
OUT
= 3dV 10 pF
2691 tbl 00
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4,6) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Op erating
Current
(Bo th Ports Active )
CE
L
and
CE
R
= V
IL
,
Outputs Open
f = f
MAX(2)
COM'L
SA
LA
110
110
250
200
110
110
220
170
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB1
Standby Current
(Bo th Ports - TTL
Le vel Inp uts )
CE
L
and
CE
R
= V
IH
f = f
MAX(2)
COM'L
SA
LA
30
30
65
45
30
30
65
45
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB2
Standby Current
(One Po rt - TTL
Le vel Inp uts )
CE
"A"
= V
IL
and
CE
"B"
= V
IH(5)
A ctive P o rt Outp uts Op en,
f=f
MAX(2)
COM'L
SA
LA
65
65
165
125
65
65
150
115
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB3
Full Standb y Current
(Bo th Ports -
CM OS Le ve l Inp uts )
CE
L
and
CE
R
>
V
CC
- 0.2V,
V
IN
>
V
CC
- 0.2V o r
V
IN
<
0.2V, f = 0
(3)
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB4
Full Standb y Current
(One Po rt -
CM OS Le ve l Inp uts )
CE
"A"
<
0.2V and
CE
"B"
>
V
CC
- 0.2V
(5)
V
IN
>
V
CC
- 0. 2V or V
IN
<
0.2V
A ctive P o rt Outp uts Op en,
f = f
MAX(2)
COM'L
SA
LA
60
60
155
115
60
60
145
105
mA
IND
SA
LA
____
____
____
____
____
____
____
____
2691 tbl 04a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Ope rating
Current
(Both Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Open
f = f
MAX(2)
COM'L
SA
LA
80
80
165
120
65
65
155
110
mA
IND
SA
LA
____
____
____
____
65
65
190
140
I
SB1
Standby Current
(Bo th Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX(2)
COM'L
SA
LA
25
25
65
45
20
20
65
35
mA
IND
SA
LA
____
____
____
____
20
20
65
45
I
SB2
Standby Current
(One Po rt - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH(5)
Active Port Outputs Open,
f=f
MAX(2)
COM'L
SA
LA
50
50
125
90
40
40
110
75
mA
IND
SA
LA
____
____
____
____
40
40
125
90
I
SB3
Full Stand by Curre nt
(Bo th Ports -
CM OS Level Inp uts)
CE
L
and
CE
R
>
V
CC
- 0.2V,
V
IN
>
V
CC
- 0.2V or
V
IN
<
0.2V, f = 0
(3)
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
mA
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
I
SB4
Full Stand by Curre nt
(One Po rt -
CM OS Level Inp uts)
CE
"A"
<
0.2V and
CE
"B"
>
V
CC
- 0.2V
(5)
V
IN
>
V
CC
- 0.2V or V
IN
<
0.2V
Active Port Outputs Open,
f = f
MAX(2)
COM'L
SA
LA
45
45
110
85
40
40
100
70
mA
IND
SA
LA
____
____
____
____
40
40
110
85
2691 tbl 04b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
VCC
CE
4.5V 4.5V
DATA RETENTION MODE
tCDR tR
VIH VIH
VDR
VDR 2.0V
2691 drw 04
≥
,
Symbol
Parameter
Test Conditions
71321SA
71421SA
71321LA
71421LA
Unit
Min.
Max.
Min.
Max.
|ILI| Inp ut Leakage Current(1) VCC = 5. 5V, VIN = 0V to VCC ___ 10 ___ 5µA
|ILO|Output Leakage Current(1) CE = VIH, VOUT = 0V to V CC,
VCC - 5. 5V ___ 10 ___ 5µA
VOL Output Low Vo ltage (I/O0-I/O7)I
OL = 4mA ___ 0.4 ___ 0.4 V
VOL Op e n Drain Outp ut
Lo w Vo ltag e (BUSY/INT)IOL = 16mA ___ 0.5 ___ 0.5 V
VOH Output High Vo ltage IOH = -4mA 2.4 ___ 2.4 ___ V
2691 t bl 0 5
Symbol
Parameter
Test Condi tion
Min.
Typ.
(1)
Max.
Unit
VDR VCC
fo r Data Re tenti o n 2. 0 ____ 0V
ICCDR Data Retention Current VCC = 2.0V, CE > VCC - 0. 2V COM'L ____ 100 1500 µA
VIN > VCC - 0. 2V or V IN < 0. 2V IND ____ 100 4000 µA
tCDR(3) Chip Des e le ct to Data Rete ntion Time 0 ____ ____ ns
tR(3) Op e ratio n Re c ov e ry Time tRC(2) ____ ____ ns
2691 t bl 0 6
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
6
5V
1250Ω
30pF*
775Ω
DATA OUT
5V
1250Ω
775Ω5pF*
DATA OUT
2691 drw 05
5V
270Ω
30pF*
BUSY or INT
*100pF for 55ns versions
*100pF for 55ns versions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
Figure 3. BUSY and INT
AC Output Test Load
AC Test Conditions
Input Pulse Levels
Inp ut Ris e/Fall Time s
In p ut Timi ng Refe r e nc e L e v e l s
Outp ut Refe re nce Lev els
Outp ut Lo ad
GND to 3.0V
5ns
1.5V
1.5V
Fig u res 1,2 and 3
2691 tbl 07
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
7
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2,4)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cyc le Time 20
____
25
____
ns
t
AA
Add ress Access Time
____
20
____
25 ns
t
ACE
Chip Enable Access Time
____
20
____
25 ns
t
AOE
Output Enable Acc ess Time
____
11
____
12 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time(1,3) 0
____
0
____
ns
t
HZ
Output High-Z Time (1,3) ____ 10 ____ 10 ns
t
PU
Chip Enable to Po wer Up Time (3) 0
____
0
____
ns
t
PD
Chi p Dis ab le to Powe r Do wn Time (3) ____ 20 ____ 25 ns
2 691 tb l 08 a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
tRC Re ad Cyc le Time 35
____
55
____
ns
tAA Address Acce ss Time
____
35
____
55 ns
tACE Chip Enable Access Time
____
35
____
55 ns
tAOE Output Enable Access Time
____
20
____
25 ns
tOH Output Hold from Address Change 3
____
3
____
ns
tLZ Output Low-Z Time(1,3) 0
____
5
____
ns
tHZ Output High-Z Time(1,3)
____
15
____
25 ns
tPU Chip Enab le to Power Up Time (3) 0
____
0
____
ns
tPD Chi p Dis ab le to P owe r Do wn Time (3)
____
35
____
50 ns
2691 t bl 0 8b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
8
Timing Waveform of Read Cycle No. 2, Either Side (3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4 . Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 1, Either Side(1)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATA VALID
tAA
tOH
DATA VALID
2691 drw 06
tBDDH (2,3)
BUSYOUT
CE
tACE
tAOE
tHZ
tLZ
tPD
VALID DATA
tPU
50%
OE
DATAOUT
CURRENT
ICC
ISS 50%
2691 drw 07
(4)
(1)
(1) (2)
(2)
(4)
tLZ
tHZ
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temeprature and Supply Voltage Range(4,5)
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
5. Industrial temperature: for other speeds, packages and powers contact your sales office.
Symbol
Parameter
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Unit
Min.
Max.
Min.
Max.
WRI TE CYCLE
tWC Write Cy cl e Time (2) 20
____
25
____
ns
tEW Chip Enable to End -of-Write 15
____
20
____
ns
tAW Address Valid to End-of-Write 15
____
20
____
ns
tAS Add ress Set-up Time 0
____
0
____
ns
tWP Write Pulse Width(3) 15
____
15
____
ns
tWR Write Re covery Time 0
____
0
____
ns
tDW Data Valid to End-of-Write 10
____
12
____
ns
tHZ Output High-Z Time(1)
____
10
____
10 ns
tDH Data Hold Time 0
____
0
____
ns
tWZ Write Enab le to Output in High-Z(1)
____
10
____
10 ns
tOW Output Active fro m End -o f-Write (1) 0
____
0
____
ns
2691 tbl 09 a
Symbol
Parameter
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com 'l & Ind
Unit
Min.
Max.
Min.
Max.
WRI TE CYCLE
tWC Write Cy cl e Time (2) 35
____
55 ____ ns
tEW Chip Enable to End -of-Write 30
____
40 ____ ns
tAW Address Valid to End-of-Write 30
____
40 ____ ns
tAS Add ress Set-up Time 0
____
0____ ns
tWP Write Pulse Width(3) 25
____
30 ____ ns
tWR Write Re covery Time 0
____
0____ ns
tDW Data Valid to End-of-Write 15
____
20 ____ ns
tHZ Output High-Z Time(1)
____
15 ____ 25 ns
tDH Data Hold Time 0
____
0____ ns
tWZ Write Enab le to Output in High-Z(1)
____
15 ____ 30 ns
tOW Output Active fro m End -o f-Write (1) 0
____
0____ ns
2691 t bl 0 9b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured ±500mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers toturn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
ADDRESS
OE
CE
R/W
DATA OUT
DATA IN
(4) (4)
2691drw 08
tWC
tAS(6) tWR(3)
tOW
tDW tDH
tAW
tWP(2)
tHZ(7)
tWZ(7)
tHZ(7)
tWC
ADDRESS
CE
R/W
DATAIN
tAS(6) tEW(2) tWR
tDW tDH
tAW
2691 drw 09
(3)
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, t WDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY
TIMING (For MASTER 71321)
t
BAA
BUSY
Access Time from Address
____
20
____
20
ns
t
BDA
BUSY
Disable Time from Address
____
20
____
20
ns
t
BAC
BUSY
Access Time from Chip Enable
____
20
____
20
ns
t
BDC
BUSY
Disable Time from Chip Enable
____
20
____
20
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
50
ns
t
DDD
Write Data Val id to Re ad Data De lay
(1)
____
35
____
35
ns
t
APS
Arb itration Priority Se t-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
25
____
35
ns
BUSY
INPUT TIMING (For SLAVE 71421)
t
WB
Write to
BUSY
Inp ut
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
40
____
50
ns
t
DDD
Write Data Val id to Re ad Data De lay
(1)
____
30
____
35
ns
2 691 tbl 10 a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& In d
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY
TIMING (For MASTER 71321)
t
BAA
BUSY
Access Time from Address
____
20
____
30
ns
t
BDA
BUSY
Disable Time from Address
____
20
____
30
ns
t
BAC
BUSY
Access Time from Chip Enable
____
20
____
30
ns
t
BDC
BUSY
Disable Time from Chip Enable
____
20
____
30
ns
t
WH
Write Hold After
BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
ns
t
DDD
Write Data Val id to Re ad Data De lay
(1)
____
35
____
55
ns
t
APS
Arb itration Priority Se t-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
50
ns
BUSY
INPUT TIMING (For SLAVE 71421)
t
WB
Write to
BUSY
Inp ut
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
ns
t
DDD
Write Data Val id to Re ad Data De lay
(1)
____
35
____
55
ns
2691 t bl 10b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
12
tWC
tWP
tDW tDH
tBDD
tDDD
tBDA
tWDD
ADDR"B"
DATAOUT"B"
DATAIN"A"
ADDR"A" MATCH
VALID
MATCH
VALID
R/W"A"
BUSY"B"
tAPS(1)
2691 drw 10
tBAA
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (71421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B " is opposite from port "A".
NOTES:
1. tWH must be met for both BUSY input (71421, slave) or output (71321, Master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version (71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(4)
BUSY"B"
2691 drw 11
R/W"A"
tWP
tWH
tWB
R/W"B" (2)
(1)
(3)
,
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71321 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
tAPS(2)
ADDR "A"
AND "B" ADDRESSES MATCH
tBAC tBDC
CE"B"
CE"A"
BUSY"A"
2691 drw 12
BUSY"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
tAPS(2)
ADDR"A"
ADDR"B"
2691 drw 13
tBAA tBDA
tRC or tWC
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS Add ress Set-up Time 0
____
0
____
ns
tWR Write Re covery Time 0
____
0
____
ns
tINS Interrupt Se t Time
____
20
____
25 ns
tINR Inte rrup t Re se t Time
____
20
____
25 ns
2691 tbl 11 a
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
14
Timing Waveform of Interrupt Mode(1)
SET INT
CLEAR INT
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(1,2)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
tINS
ADDR"A"
INT"B"
INTERRUPT ADDRESS
tWC
tAS
R/W"A"
tWR
2691 drw 14
(3)
(3)
(2)
(4)
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
OE"B" tINR
INT"A" 2691 drw 15
tAS(3)
(3)
(2)
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS Add ress Set-up Time 0
____
0
____
ns
tWR Write Re covery Time 0
____
0
____
ns
tINS Interrupt Se t Time
____
25
____
45 ns
tINR Inte rrup t Re se t Time
____
25
____
45 ns
2691 tbl 11b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
15
Truth Table III Address BUSY Arbitration
Truth Table I. Non-Contention Read/Write Control(4)
NOTES:
1. Pins BUSYL and BUSYR are both outputs for 71321 (Master). Both are inputs for 71421 (Slave). BUSYX outputs on the 71321 are open drain, not push-pull outputs.
On slaves the BUSYX input internally inhibits writes.
2 . 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3 . Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Tables
Truth Table II. Interrupt Flag(1,4)
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Left or Right Port
(1)
Function
R/
WCE OE
D
0-7
X H X Z Port Disab l ed and in P ower-Down Mo d e, ISB2 or ISB4
XHX Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
LLXDATA
IN D ata o n Po rt Writte n Into Me mo ry (2)
HLLDATA
OUT Data in Memory Output on Port(3)
H L H Z Hig h Im pe d anc e Outp uts
2691 tbl 12
Left Port Right Port
FunctionR/WLCE
LOELA10L-A0L INTLR/WRCE
ROERA10R-A0R INTR
LLX7FFXXXX X L
(2)
S et Rig ht INTR Flag
XXXXXXLL7FF H
(3)
Re se t Rig ht INTR Flag
XXX X L
(3)
LLX7FE XSet Left INTL Flag
XLL7FE H
(2)
X X X X X Re s et L e ft INTL Flag
2 691 tbl 13
Inputs
Outputs
Function
CE
L
CE
R
A
0L
-A
10L
A
0R
-A
10R
BUSY
L
(1)
BUSY
R
(1)
XXNO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L M ATCH (2) (2) Write Inhi b it(3)
26 91 tb l 14
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
16
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic, one
master part is used to decide which side of the SRAM array will receive
a BUSY indication, and to output that indication. Any number of slaves to
be addressed in the same address range as the master, use the BUSY
signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs
the BUSY pin is an output if the part is Master (IDT7132), and the BUSY
pin is an input if the part is a Slave (IDT7142) as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Functional Description
The IDT71321/IDT71421 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71321/IDT71421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL, per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. In slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT71321 (Master) are open drain type
outputs and require open drain resistors to operate. If these SRAMs are
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
2691 drw 16
MASTER
Dual Port
SRAM
BUSYLBUSYR
CE
MASTER
Dual Port
SRAM
BUSYLBUSYR
CE
SLAVE
Dual Port
SRAM
BUSYLBUSYR
CE
SLAVE
Dual Port
SRAM
BUSYLBUSYR
CE
BUSYLBUSYR
DECODER
5V 5V
270Ω
270Ω
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
17
Ordering Information
NOTE:
1. Industrial temperature range is available in selected PLCC packages in standard power.
For other speeds, packages and powers contact your sales office.
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
XXXXIDT Device Type A999 A A
Power Speed Package Process/
Temperature
Range
71321
71421
16K (2K x 8-Bit) MASTER Dual-Port SRAM
w/ Interrupt
16K (2K x 8-Bit) SLAVE Dual-Port SRAM
w/ Interrupt
Speed in nanoseconds
2691 drw 17
BLANK
I(1)
J
PF
TF
20
25
35
55
LA
SA
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
Standard Power
Commercial Only
Commercial Only
Commercial Only
Commercial & Industrial
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/24/99: Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
6/7/99: Changed drawing format
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com
