@IDT CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 1DT7280 IDT7281 IDT7282 IDT7283 IDT7284 IDT7285 FEATURES: * The 7280 is equivalent to two 7200 256 x 9 FIFOs * The 7281 is equivalent to two 7201 512 x 9 FIFOs * The 7282 is equivalent to two 7202 1,024 x 9 FIFOs * The 7283 is equivatent to two 7203 2,048 x 9 FIFOs * The 7284 is equivalent to two 7204 4,096 x 9 FIFOs * The 7285 is equivalent to two 7205 8,192 x 9 FIFOs + Low power consumption -- Active: 685 mW (max.) Power-down: 2.75 mW (max.) * Ultra high speed12 ns access time * Asynchronous and simultaneous read and write * Offers optimal combination of data capacity, small foot print and functional flexibility * Ideal for bi-directional, width expansion, depth expansion, bus- matching, and data sorting applications - Status Flags: Empty, Half-Full, Full * Auto-retransmit capability + High-performance CMOS technology * Space-saving TSSOP * Industrial temperature range (-40C to +85C) is available DESCRIPTION: The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that load and empty data on afirst-inffirst-out basis. These devices are functional and compatible to two 7200/7201/7202/7203/7204/7205 FIFOs in a single package with all associated control, data, and flaglines assigned to separate pins. The devices use Full and Empty flags to prevent data overflow and underflowandexpansionlogic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user's option. This feature is especially useful in data commu- nications applications where itis necessary to use a parity bit for transmis- sion/reception error checking. Italso features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allowfor retransmission from the beginning of data. A Half-Full Flags available in the single device mode and width expansion modes. These FIFOs are fabricated using IDT's high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. FUNCTIONAL BLOCK DIAGRAM DATA INPUTS (DAG -DAs} a DATA OUTPUTS. (QA0-QA8) DBo- DBs DATA INFUTS 9 1,024 x9 WRITE 2/048 x 9 POINTER 4,096 x9 8,192 x9 THREE- STATE o BUFFERS RESET } Locic ~ DATA OUTPUTS (QBo-OBs) FB FFB E NOVEMBER 1998 1998 Integrated Device Technology, Inc. OSC-3208/3IDT7280/81/82 eas PIN CONFIGURATION Com'l & Unit FFAC)10 56/2 XiA VreRM | Terminal Voltagewith 0.50 +7.0 V Qo Cj 2 55] DAo toGND QAi CJ 3 541 DA QA2 Cy 4 53 DAo = Os 8 6 = bis tour | DCOutputCurrent -50to+50 mA GND C7 50/9 WA NOTE: 3208 thi 01 RAC] 8 49(2 Vcc 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause QM 9 483 DAs permanent damage to the device. This is a stress rating only and functional operation QAs [J 10 47 DAs of the device at these or any other conditions above those indicated in the operational QAs J 11 46 (2 DAs sections of this specification is not implied. Exposure to absolute maximum rating QA7 CJ 12 45 Daz conditions for extended periods may affect reliability. XOAHEFA 3 44 = FLAYRTA era ie a3] BSA RECOMMENDED DC OPERATING QBo F 16 41 FFI DBo CONDITIONS OB: q 18 39 =n Symbol Parameter Min. | Typ. | Max. | Unit QBs oS 18 38 = Des Vec Supply Voltage 45 5.0 55 | V GND Gi 21 ae We GND | Supply Volage 0 0 . Vv RB CJ 22 35,2] Vcc VinTinput High Volta 2.0 = QBs EF] 23 341 Bs High Voltage V QBs CJ 24 332) DBs Vi! Input Low Voltage _ _ 08 | Vv QBe J 25 32/0) DBe i _ ___QB7 Cy 26 30 DB7 Ta Operating Temperature 0 n C XOB/HEB CJ 27 30/0 FLB/ATB Commercial EFB CY 28 29/9) ASB Ta Operating Temperature 40 85 | C 3208 rw 02 Industrial TSSOP (SO56-2, order code: PA) NOTES: 3208 tbl 03 TOP VIEW 1. For RE/RSXI input, Vin = 2.6V (commercial). 2. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5V + 10%, TA = 0C to +70C; Industrial: Vcc = 5V + 10%, Ta = -40C to +85C) IDT7280L 1DT7263L IDT7281L iDT7284L IDT7282L IDT7285IL Com'l & ind'Il Com & indi ta= 12, 15, 20ns ta= 12, 15, 20ns Parameter Min. Max. Current -1 1 -10 10 1" loH = -2mA 24 _ lo. = 8mA _ 0.4 Active Power Current _ Current =VIH) - 15 NOTES: 1. Industrial temperature range product for the 20ns speed grade is available asa standard AC TEST CON DITIONS device. All other speed grades are available by special order. 2. Measurements with 0.4 < Vin < Vec. Input Pulse Levels GND to 3.0V 3. Re Vin, 0.4 < Vout < Vec. Input Rise/F ail Times 5ns . ree wn oh flour = 0). Input Timing Reference Levels 1.5V 6. Typical lect = 2[15 + 2'fs + 0.02C. fs] (in mA) with Vcc = 5V, Ta = 25C, fs=WCLK | OutputReferenceLevels 1.5V frequency = RCLK frequency (in MHz, using TTL levels), data switching at fs/2, Output Load See Figure 1 Ci = capacitive load (in pF). 7. All Inputs = Vcc - 0.2V of GND + 0.2V. S208 wh 08 5V TO 1.1K CAPACITANCE (1: = +25C, f= 1.0MHz) OUT EN Symbol - Parameter Condition Max. | Unit 6802 30pF* CIN Input Capactance VIN = OV 8 pF . 9208 aw 03 Cout Output Capacitance Vout = OV 8 pF of equivalent circuit > NOTE: 2679 thi 02 Figure 1. Output Load 1. Characterized values, not currently tested. * Includes scope and jig capacitances.1 as -10 R ee Y4 Tey AC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5V + 10%, TA = 0C to +70C; Industrial: Voc = 5V + 10%, TA = -40C to +85C) Commercial Com't & ind? T20L12 T200L15 7280120 728112 T2B1L15 7281L20 T2B2L12 7282L.15 7282.20 T283L12 7263L15 7283.20 T2BAL12 T2BAL15 T2BAL20 7285L.12 7285L.15 7285120 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit ts Shift Frequency 50 _ _ 33 MHz Rc Read Cycle Time a - 2 - XD _ ns ta Access Time - 12 5 - 2 ns tRR Read Recovery Time 8 _ 10 10 ns trew | ReadPulsewidth 2 - 6 2 ~ ns RZ Read Pulse Lowto Data Bus at Low Z? 3 _ 3 - 3 _ ns twiz | Write Pulse Highto Data Bus at Low 2" 5 5 = 5 = ns tov Data Valid from Read Pulse High 5 - 5 ~ 5 ns IRHZ Read Pulse High to Data Bus at High 2) - 12 _ 15 - 15 ns two Write Cycle Time 2 = 25 _ XD ns twew _| WritePulse Width) 12 = 5 ~ 20 ns twR Write Recovery Time 8 10 = 10 ns tos Data Set-up Time 9 = " = 12 ns {DH Data Hold Time 0 _ 0 _ 0 _ ns tRSC Reset Cycle Time 2 = 4 _ x0 = ns tRS Reset Puse Width? 2 = 15 2 ns RSS Reset Set-up Time 12 - 15 2 _ ns IRSR Reset Recovery Time 8 - 10 _ 10 ns (RIC Retransmit Cycle Time _ 2 = 2 _ D ns RT Retransmit Pulse Width) 12 = 5 _ ~ - ns tRTS Retransmit Set-up Time 12 - 5 ~ 20 - ns IRTR Retransmit Recovery Time 8 - 10 - 10 - ns tEFL Resetto Empty Flag Low - 12 - 2 - D ns tHFH.FFH | ResettoHalf-Fulland Full Flag High TT - a - x ns (RIF Retransmit Lowto Flags Valid - a - a _ K ns (REF Read Low to Empty Flag Low _ 12 _ 5 - 20 ns (RFF Read High to Full Flag High - 4 - a) - 2 ns (RPE Read Putse Width after EF High 2 - 5 _ 2 - ns (Wer Write High to Empty Flag High _ 12 - aK) ~ 2 ns twrF Write Low to Full Flag Low - 14 - 5 _ 2 ns (WHF Write Low to Half-Full Flag Low _ 7 - 2 _ x rs (RHF Read Highto Half-Full Flag High - 7 - 2 - 0 ns (WPF Write Pulse Width after FF High 12 - 15 20 ns bxoL Read/Writeto XOLow = 12 5 - 2 ns 1XOH ReadMWriteto XOHigh _ 12 - 15 _ 2 ns bi Xi Pulse Width) 12 _ 15 = 2 ~ ns BR Xi Recovery Time 8 = 10 - 10 ns bis X Set-up Time 8 _ 10 10 _ ns bores: 3208 thi 06 1. Timings referenced as in AC Test Cohditions. 2. Industrial temperature range is available by special order for speed grades faster than 20ns. 3. Putse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode.ON aan se SIGNAL DESCRIPTIONS INPUTS: DATA IN (Do - Ds) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Resetis accomplished whenever the Reset (RS) inputistakentoa LOW state. During reset, both internal read and write pointers are set to the first location. Aresetis required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, (7.e., tRss before the rising edge of RS) and should not change until trsr after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset (R WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) willbe setto LOW and will remain set until the difference between the write pointer andread pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FP) will go HIGH after treF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when itis full. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF)isnotset. The datais accessed on a First-In/First- Outbasis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Qo- Qs) willreturnto a high impedance condition until the next Read operation. When all datahas been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the final read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) wil go HIGH after twer and a valid Read can then begin. When the FIFO is empty, the internal read pointeris blocked from Riso external changes in Rwill not affect the FIFO when itis empty. FIRST LOAD/RETRANSMIT (FLAT) This is a dual-purpose input. tn the Depth Expansion Mode, this pin is grounded toindicate thatitis the firstloaded (see Operating Modes). In the Single IDT Device Mode, this pin acts as the retransmitinput. The Single Device Modeis initiated by grounding the Expansion In (XI). These devices can be made to retransmit data when the Retransmit Enable control (RT) inputis pulsed LOW. Aretransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during setransmit. This featureis useful when less than 256/512/1,024/2,048/4,096/ 8,192 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the devices full. if the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 256 writes for IDT 7280, 512 writes for the IDT7281, 1,024 writes for the IDT7282, 2,048 writes for the IDT7283, 4,096 writes for the IDT7284 and 8,192 writes for the IDT7285. EMPTY FLAG (EF) __ The Empty Flag (EF) willgo LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expan- sion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain setuntil the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (Xi) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. DATA OUTPUTS (Qo - Qa) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a HIGH state.Res Ua P4 IDT a 2) N 2 1. EF, FF, HF may change status during Reset. but flags will be valid at trsc. 2. Wand R = Vin around the rising edge of RS. Figure 2. Reset < tre * tRePwW > ta-~| tRR-->_ ta- a \ y Kd KY h- tRLZ tov }t tRHZ > SZ Qo-Qa DATA out VALID. X X DATA obtt VALID twe + twew mle twR4 cK CU XK Do-Ds DATAIN VALID DATA IN VALID D 3208 drw 05 Figure 3. Asynchronous Write and Read Operation LAST WRITE IGNORED FIRST READ ADDITIONAL FIRST WRITE READS WRITE Bb F a Ww \_/ \_/ co tWFF 7 tRFF FF 3208 drw 06 Figure 4. Full Flag From Last Write to First Read 5Oe esse BEEP IDT LAST READ | IGNORED| = FIRSTWRITE | ADDITIONAL| FIRST READ WRITES READ _ y W \ 7 R \ \_/ a; tREF i WEF => ta vy Vv Vv 7 DATA OUT XA vacip XX XX VALID XX) senww Figure 5. Empty Flag From Last Read to First Write tRTC > <2 iRT _- ae TN fl RT x 7 tRTS mt tATR > XXXKXY YK ~? tRTF >| RE SOOOOOOOOOOOI OOK RASTA Dl W, Ww \ tWeEF n WALLIN veotawco Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse A w YALL ee Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse 7 tRFFIDT7280/81/82 ae Ww x / tRHF | mt {WHF HE HALF-FULL OR LESS MORE THAN HALF-FULL 7 HALF-FULL OR LESS 3206 drw 11 Figure 9. Half-Full Flag Timing WRITE TO LAST PHYSICAL LOCATION W READ FROM LAST PHYSICAL LOCATION R XO 3208 drw 12 Figure 10. Expansion Out xi WRITE TO FIRST PHYSICAL WwW LOCATION iis READ FROM FIRST PHYSICAL R LOCATION 3208 drw 13 Figure 11. Expansion In OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). Single Device Mode A single IDT7280/7281/7282/7283/7284/7285 may be used when the application requirements are for 256/512/1,024/2,048/4,096/8, 192 words or less. These FIFOs arein a Single Device Configuration when the Expansion In XI) control input is grounded (see Figure 12). Depth Expansion These devices can easily be adapted to applications when the require- ments are for greater than 256/512/1,024/2,048/4,096/8, 192 words. Figure 14 demonstrates a four-FIFO Depth Expansion using two IDT7280/7281/ 7282/7283/7284/7285s. Any depth can be attained by adding additional IDT7280/7281/7282/7283/7284/7285s. These FIFOs operate in the Depth Expansion mode when the following conditions are met: 1. The first FIFO must be designated by grounding the First Load (FL) control input. 2. Allother FIFOs must have FLin the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4, External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EP). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode.Oh Wes: a ah USAGE MODES: Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple FIFOs. Status flags (EF, FF and HF} can be detected from any one FIFO. Figure 13 demonstrates an 18-bit word width byusing the two FIFOs containedin the IDT7280/7281/7282/7283/7284/ 7285s. Any word width can be attained by adding FIFOs (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7280/7281/7282/7283/7384/7285s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), IDT the FIFO permits a reading of a single word after writing one word of datainto an empty FIFO. The datais enabled on the bus in (tweF + ta)nsafterthe rising edge of W, called the first write edge, anditremainsonthe busuntil the R lineis raised fromLOW-to-HIGH, after which the bus would gointo a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. Inthe write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The Rline causes the FF to be deasserted but the Wine being LOW causes itto be asserted againin anticipation of anew data word. On therising edge of W, the new word is loaded in the FIFO. The Wine must be toggled when FFis notasserted to write new datain the FIFO and toincrementthe write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). (HALF-FULL FLAG) (AF) WRITE (W) FIFO or DATA IN (D) 7280 FULL FLAG (FF) 2281 RESET (RS)*|_ 7283 7284 7285 /+ REAp (A) DATA OUT (Q) + _ EMPTY FLAG (EF) -+ RETRANSMIT (RT) EXPANSION IN (XI) 1 Figure 12. Block Diagram of One 256 x 9, 512 x 9, 1,024 x 9, DATA nN (D) WRITE (W) FULL FLAG (FFA) RESET (RS) ~TeQO/T28 1/7282! 3208 drw 14 2,048 x 9, 4,096 x 9, 8,192 x 9 FIFO Used in Single Device Mode READ (R) EMPTY FLAG (EFB) RETRANSMIT (RT) ----4 DATA ouT(Q) 3208 drw 15 Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 FIFO Memory Used in Width Expansion ModeOe es: 1 UE RELY IDT TABLE IRESET AND RETRANSMIT Device Mode NOTE: 2679 thi 09 1. Pointer will increment if flaq is High. TABLE lIRESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Internal Status Mode RS FL Read Pointer Write Pointer Other 0 1 Zero Location Read/Write 1 X X X NOTE: 2679 tbl 10 1. XTis connected to XO of previous device. See Figure 14. RS = Reset Input, FLAT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Haif-Full Flag Output 7280/7281/ 7282/7283/ 7284/7285 S| FULL 7280/7281/ 7282/7283/ 7284/7285 XIB 3208 drw 16 Figure 14. Block Diagram of 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 FIFO Memory (Depth Expansion)IDT7280/81/82 eae Qo-Qa Q9-Q17 QiN-8)-QN eee | Qo-Qs | | Q9-Q17 QiN-8)-QN IDT7280/7281/ IDT7280/7281/ 1DT7280/7281/ 7282/7283/ 7282/7283/ 7282/7283/ 7284/7285 7284/7285 7284/7285 R, W,RS * DEPTH > DEPTH +- eo > DEPTH EXPANSION EXPANSION EXPANSION BLOCK BLOCK BLOCK 4 S Do-Ds 4 * Do-D17 D(n-8)-DN Do-DN eee De-DN Dis-DN Din-8)-DN 3208 dew 17 NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. SIDE1 < Figure 15. Compound FIFO Expansion IDT 7280 7281 7282 7284 7285 1 ' i ' 1 ! | 7283 CO! \ ! I 1 ' 1 j Re*] Firoe Figure 16. Bidirectional FIFO Mode [+ tRPE 4 t~ tA DATAOouT Figure 17. Read Data Flow-Through Mode Z| + tWweF __* eer twiz ey DATA OUTVALID 3208 drw 19=< -< twep > WANA 7 h {RFF ] FF Z __ tWFF TDH DATAIN DATA IN VALID i tA tps oxraou <K one xX Figure 18. Write Data Flow-Through Mode ORDERING INFORMATION (DT XXXX X XXX X Xx Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0C to +70C) ) Industrial (-40C to +85C) PA Thin Shrink SOIC (TSSOP, SO56-2) 12 Commercial ; | 15 Commercial Access Time (ta) Speed 20 Commercial and !ndustrial in Nanoseconds qt Low Power 7280 256 x 9 Dual FIFO 7281 512 x 9 Dual FIFO 7282 1,024 x 9 Dua! FIFO | 7283 2,048 x 9 Dual FIFO 7284 4,096 x 9 Dual FIFO 7285 8,192 x 9 Dual FIFO 3208 drw 21 NOTE: 1. Industrial temperature grade is available by special order for speed grades faster than 20ns. 2975 Stender Way 800-345-7015 i DT Santa Clara, CA 95054 fax: 408-492-8674 www.idicom - The IDT logo is a registered trademark of Integrated Device Technology, Inc.