TMXF281553BAL-2-DB - Agere Systems, Inc.

Prelimina ry Data Sheet

Ma y 2001

TM XF28155 Super Mapp er

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

1 Features

■Versatile IC supports 155/51 Mbits/s SONET/SDH

interface solutions for T3/E3, DS2, T1/E 1/J1, a nd

DS0/E0/J0 applications.

■Implem entation sup ports both linear (1 + 1, unpro-

tected) and ring (UPSR) network topologies.

■Provides f ull termination of up to 21 E1, 28 T1, or

28 J1.

■Low power 3.3 V supply.

■–40 °C to +85 °C industrial tem perature range.

■456-pin ball grid array (PBGA) package.

■Complies with

Bellcore*

, ITU,

ANSI

†, ET SI and Jap-

anese TTC standards: GR-253-CORE, GR-499,

(ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,

G.96 2, G.964, G.9 65, Q.542, T1.105, JT-G704 ,

JT-G706, JT-G707, JT-I431-a, ET S 300 417-1-1,

ETS 300 011, T1.107, T1.404.

1.1 SO N E T/S D H Inte rf a ce

■Termination of a single 155 Mbits/s STS-3/STM-1 or

single 51 Mbits/s STS-1 /S TM-0.

■Built-in clock and data recove ry circui t at

155 Mbits/s STS-3/STM-1 interface (can be des e-

lected if ex ternal clock rec over y i s provided).

■Supports ove rh ead processing for all transport and

path overhead bytes.

■Optional insertion and extraction of overhead bytes

via a serial transport overhead access channel. Con-

figurable as dedicated DCC channels.

■Softwar e controlled line ar 1 + 1 protec tion via dedi-

cated interface to protect ion card .

■Full path termination an d SPE extraction/inse rtion.

■SONET/SDH compliant condition and al arm repo r t-

ing.

■Built-in diagnostic loopback modes.

■8 kHz line frame sync output.

Bellcore

is now

Tel co rdi a Techno l og ie s

Telcordia Technologies

is a

trademark of Telcordia Technologies, Inc.

†

ANSI

is a registered trademark of American National Standards

Institute, Inc.

1.2 STS/ST M Poin ter In terpreter

■Interprets STS/AU/TU-3 pointers.

■S ynch roniz es 8 kH z f ram e and 2 kHz superframe to

system/shelf timing reference by setting the transmit

STS-3/STM-1 pointers to a fixed value of 522.

■Monitors/terminates SPE path overhead.

1. 3 Tele c o m Bu s Int e rfa ce

■Telecom bus interface to mate devices including

cloc k, data[8], parity, SPE-, J0 - , J1-, and V1 timing

indicator.

■Line and p ath RDI and REI signals passed to mate

devices.

■Three Su per Mapper devices, two configured as

mate devices, provide full ter min ation of an

STS-3/STM-1. A three-chip soluti on to terminate

84 DS 1s /J1s or 63 E1s .

1. 4 VT Te rm in a tio n /G e nera t ion (x28/x 21 )

■Monitors/terminates VT path overhead for

28 VT1.5/TU-11 or 21 VT2/TU-12.

■Synchronizes VT/TU SPE to system/shelf timing ref-

erence b y setting the transmit VT/TU pointers to fix ed

values for asynchronous mapping or by dyna mically

chan ging the transmit VT/TU pointers for byte syn-

chron ous mapping.

■Fixed pointer generation in transmit s ide for asyn-

chron ous mapping.

■Dynamic pointer generation in transmi t side for byte -

synchronous mapping.

1.5 M a pping /M ul t iplex in g Mo de s ( x 28 /x 21 )

■Maps DS3 clear channel or framed signal into STS-1

or TUG-3.

■Maps T1/E1/J1 into VT/TU (including DS1 into

TU-12).

■Supp orts asy nchronous, byt e-s ynchronous, an d bit-

synchronous mapping.

2Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

1 Features (continued)

■Suppo rts UP S R applications via the de dicat ed ring

int erfac e and an external tributary selector.

■Supports all valid T1/E1/J1 multiplexing structures

into STS-1 and STS-3/STM-1:

— STS-3/STS-1/SPE/VTG/VTx

— STM-1/AU-3/TUG-2/TU-1x/VC-1x

— STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x

■Allows grooming of VTs/TUs in granularity of TUG-2s

within the STS-3/STM-1 signal.

■Suppo rts J2 trace identifier mo n ito ring/inse rtion.

■Configurable VT/TU slot selection f or DS1, E1, and

J1 insertion and drop.

■Automatic receive m onitor functions include VT/TU

RDI-V, REI-V, BIP-2 errors, AIS-V, L OP-V.

■Complies with GR-253-CORE, GR-499, ITU-T

G.707, G.704, G.783, T1.105, JT-G707, ETS 300

417-1-1.

1. 6 M13 F ea t ur es

■Configurable mult iplexer/demultiplexer for 28 DS1

signals, 21 E1 signals, or 7 DS2 signals to/from a

DS3 signal.

■Operates in ei the r M23 o r C-bit parity mode.

■Provisionable time slot select ion for DS 1, E1, and

DS2 insertion or drop.

■Full alarm monitoring and generation (LOS, BPV,

EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit pa r-

ity errors, FEBE).

■HDLC transmitter with 128-byte data buffer and

HDLC rec eiver with 128-byte data FIFO for the C-bit

parit y path maintenance data lin k.

■DS3, DS 2, DS1, and E1 loopback and loopback

request generation.

■Complies wi th T1.102, T1. 107, T1.231, T 1.4 03,

T1.404, GR 499, G.747, and G.775.

1.7 DS3/DS2/DS1/E1 Cross Connect

■Highly configurable interconnect for up to 28 DS1 or

21 E1 s ignal s to/from the framer, external pins, M13,

or VT mappers.

■Suppor t s up to seven DS2 signals to/from the ex te r-

nal pins or M13.

■Sources may be broadcast, looped back, or routed

to/from a test-pattern generator or monitor.

■Any DS1 or E1 channel may be routed through the

jit ter at tenuator.

■DS3 may be configured for the M13 to interconnect

with the SPE, or external I/O to int erc onnec t with the

M13 or SPE.

1.8 Jitter Attenuation

■PLL-free receive operat ion using built-in digital jitter

attenuator (in VT/VC mode or M13 mode).

■Configurable to meet jitter and MTIE requirements.

1.9 PDH Interfaces

■One DS3, 7x DS2.

■x28/x21 framed or unframed DS1 or E1 interfaces.

■One additional dedicated protection channel for

DS2/DS1/E1.

1.10 T1/E1/J1 Framing Features (x28/x21)

■x28/x21 T1/E1/J1 channels .

■Line coding: B8ZS, HDB3, ZCS, AM I, a nd

CM I (JJ20- 11).

■T1 framing m odes : ESF, D4,

SLC

®-96, T1 DM DDS,

and SF (Ft only).

■E1 framing: G.704 basic and CRC-4 multiframe con-

sistent with G.706.

■J1 framing modes: J ESF (Japan).

■Supports T1 and E1 unframed and transparent trans-

mission format.

■T1 signaling modes: transparent;

and 16-state; D4 2-s ta te , 4-state, and 16-state;

SLC

-96 2-state, 4-state, and 16-state; J-ESF han-

dling groups maintenance and signaling ; VT 1.5

SPE 2, 4, 16 state.

■E1 signaling modes: t ransparent;

frame structure as per ITU G.732.

■Signaling debounce and change of state in terrupt.

■V5.2 Sa7 processing.

3Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

1 Features (continued)

■Alarm reporting and performance monitoring per

AT&T,

ANSI

, ITU-T, and ETSI st andards.

■Facility d ata link fea tur e s :

— HDLC or transparent acc es s for either ESF o r

DDS + FDL fra me formats .

— Register/stack access for

SLC

-96 transmit and re-

ceive data.

— Extended superframe (ESF): automatic transmis-

sion of the ES F performance report messages

(PRM). Automatic transmission of the

ANSI

T1.403 ESF performance report messages. Auto-

matic de tection and tr ansmission of the

ANSI

T1.403 ESF FDL bit-oriented codes.

— Regi ster/stack access for all CEPT Sa-bits trans-

mit and receive data.

■HDLC features :

— HDLC or transparent mode.

— Programmable logical channel assignment: any

time slot, any bit for ISDN D-channel, al so inser t s/

extracts C-channels for V5.1, V5.2 interfaces.

— 64 logical channels in both transmit and receive di-

rection (any f r aming format).

— Maximum channel data rate: 64 kbits/s.

— Minimum channel data rate: 4 kbits/s (DS1-FDL or

E1 Sa bit).

— 128-byte FIFO per channel in both transmit and re-

ceive direction.

— Tx to Rx loopback supported.

■System interfaces:

— Concentration highway interface: Single clock and

fr ame syn c signals; programmable clock rates at

2.048 MH z, 4.096 MHz , 8.192 MHz, and

16.384 MHz; programmable data rates at 2.048

Mbits/s,

4.096 Mbit s /s, and 8.192 Mbits/s; program mable

clock edges and bit/by te offsets.

— Parallel system bus interface at 19.4 4 MHz for

data and signaling: single clock and frame sync

signals.

— Time-division multiplex data rate serial interface at

1.544 MH z or 2.048 MHz. Twenty-eight receive

data, cloc k, and frame sync sig nals. T went y-eight

transmit data signals with a global clock and frame

sync.

— Network serial multiplexed interface mini mal pin

count seri al inter face at 51 .84 MHz op timized for

data and IMA applications.

1.11 System Test and Maintenance

■A variety of loopback mod es im ple men ted on

SONET/SDH s id e as well as on framer level.

■Built-in test pa ttern generator and monitor config-

urabl e for simultaneously testing E1, DS1, DS2, and

DS3 (one chan nel each).

Microprocessor Inter face

■20-bit address and 16-bit data interface w ith 16 MHz

to 66 MHz read and write access.

■Compatible wit h most industry-standard processors.

Chip Testing an d Maintena nce

■

IEEE

* 1149.1 JTAG boundary scan.

Interface to Other Agere ME Devices

Seamless interface to t he following Agere Systems ’

devices:

■TADM042G5.

IEEE

is a registered trademark of the Institute of Electrical and

Electr onics En gineer s, I n c .

4Agere Sy stem s Inc.
TMXF 28155 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
 
Ta ble of Conte nts
By Major Sections
Contents Page
Features ...................................................................................................................................................................1
Pr oduc t Descri p ti o n   ............ ....................................................................... ...............................................................5
Preface ...................................................................................................................................................................5
In te r face Speci fi c a tions  ........... .................................................... .............................................................................8
Pin Information  .......................................................................................................................................................8
Ele c trical Characteristics ......................................................................................................................................33
Timing Characteristics  .........................................................................................................................................37
Order ing Information ............................................................................................................................................61
Register Description ...............................................................................................................................................62
Microprocessor Interface and Global Control and Status  Reg i st ers ... ... ..................... ... .... ... ...... ... .... ... ..... .... ... ...62
TMUX Registers ............... ....................................................................................................................................75
SPE Mapper Re gisters  ............................... ................................. ............... ........... ............... .............................133
VT/TU Mapper Registers ...................................................................................................................................153
M13/M23 MUX/DeMUX Registers  .....................................................................................................................196
28-Channel Framer Registers .............................................. .......................... ....................................................239
Cross Connect (XC) Registers ...........................................................................................................................321
Digital Jitter Attenuation Controller Registers  .... ................... .......................... .......................... .........................331
Test-Pattern Generation/Detecti on Registers .....................................................................................................336
Fu nctional  Descriptions ........... .............. .............. .............. .............. ............... .............. ........................................354
Microprocessor Interface Functional Description .................. ..................... ..... .......................... .........................354
TMUX Functional Description ...................... ....... ..... ....... ....... ..... ....... ..... ....... ....... .. .......... .. ...............................359
SPE Mapper F unct ional Descri ption .. .................. ........................ .......................... ..................... .......................396
VT/TU Mapper F unc t ional  Descri ption . ..................... ..................... . ................ ..................... . .............................425
M13/M23 MUX/DeMUX Block Functional Description .......................................................................................455
28-Channel Framer Block Functional Description ............................................................................. .................475
Cross Connect (X C) Block Functional Description  .............. .. ....... ..... ..... ....... .. ..... ....... ..... .. ....... ..... .. .................542
Digital J itter Attenuation Controller Functional D escription ............ . ....................... ..................... . ......................570
Test-Patter n Generation/Detection Functional Description ......................................................... ....... . ...............574
Philosophies .......................................................................................................................................................582
Applications ..........................................................................................................................................................588
Change History .. .... ..... .......... ......... ..... ......... .......... .... .......... ......... ..... .......... ......... ..... ...... ..................................604

5Agere Systems Inc.
Prelim inary Data Sheet TMXF28155 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Product Description
2 Preface 
Ta ble of Conte nts
Contents Page
1 Features  ............................................................................................................................................................... 1
1. 1  SONET /SDH Interface .............................................................................................. ..................................... 1
1. 2  STS/STM Poin te r  Inter p re ter  ....................................... .......................................... ........................................ 1
1. 3  Tele co m Bus Inter face ................................................. .................................................................................. 1
1.4  VT Termination/Generation (x28/x21) .... ..... ....... ..... .. .......... .. ....... ..... ....... ..... .. ....... ..... ....... ..... ....................... 1
1. 5  Mapping/Mul tiplex ing  M o des (x28 /x21)  ................................................. ........................................................ 1
1. 6  M13 Featur e s .... ......... .................................................... ................................................................................ 2
1.7  DS3/ DS2/DS1/E1 Cross Connect .......... ..... ..... .. ..... .. .......... .. ..... .. ..... .. .......... .. ..... .. ..... ....... ..... .. ..................... 2
1.8  Jit ter Attenuation .................................... ................... ............ .............. ................. .......................................... 2
1. 9  PDH Interf a ce s .... ........................................... ................................................................................................ 2
1.10  T1/E1/J1 Framing Features (x28/x21) ......................................................................................................... 2
1.11  System Test and Maintenance  ............ ...................................... .......................... ........................................ 3
2 Preface ................................................................................................................................................................. 5
2. 1  Majo r  Categories ......................... ........................................................ ........................................................... 6
2.2  Naming Convention for Registers and Parameters  ........ ..... ... ....................... ... ....................... ...................... 6
2. 3  Over view ........ .................................................... ..................................................... ....................................... 7
Figures Page
Figure 1. Functional Diagram of Super Mapper ....................... ....... ..... ....... .. .......... ....... ....... .. .......... ....................... 7

6Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

2 Preface (continued)

The objective of this data sheet is t o define the func-

tionality of the Super Mapper for hardware and soft-

ware dev elopers. The inf ormation contained in this data

sheet is prelimin ary, and may change without notice;

the reader mu st therefore asce rtain that the latest ver-

sion is u sed whe n a product is under development.

The latest version of this data s heet c an b e accessed

at: http://www.lucent.com/m icro/n etcom/produc ts/

pdh.html#super_mapper.

2.1 M aj or Ca t e go ries

This data sheet is divided into six major categories with

sub-sections as follows:

■Features

■Product Desc r ipt ion

— Features

— Preface

— Overview

■Interface Specifications

— Pin Information

— Electrical Characteristics

— Timing Characteristics

— Ordering Information

■Register Descriptions

— Microprocessor Interface Registers

— TMUX Registers

— SPE Mapper Registers

— VT/UT Mapper Registers

— M13/M23 MUX/deMUX Registers

— 28-Channel Framer Registers

— Cross Connect (XC) Registers

— Digital Jitter Attenuation Registers

— Test Pattern Generation/Detection Registers

■Functional Descriptions

— Microprocessor Interface Description

— TMUX Registers Description

— SPE Mapper Registers Description

— VT/UT Mapper Registers Description

— M13/M23 MUX/deMUX Registers Description

— 28-Channel Framer Registers Description

— Cross Connec t (XC) Registers Description

— Digital Jitter Attenuation Registers Description

— Test Pattern Generation/Det ection Registers De-

scription

■Applications

— Applicatio n Block Diagrams and Descriptions

2.2 N aming Conventio n fo r Registers and

Parameters

Ther e are many pro visioning register s for controlling

the Super Mapper . A naming convention for all regis-

ters and parameters (bit name s) is followed throughout

this dat a s heet. A prefix is attached to the base name

of each register or parameter, depending on which

functional section the register or parameter is associ-

ated with:

■SMPR_, for the Microproc essor Interface

■TMUX_, for the TMUX

■SPE_, for the SPE Mapper

■VT_, for the VT/VC Mapper

■M13_, for the M13/M23 MUX/deMUX

■FRM_, for the 28-Channel Framer

■XC_, for the Cross Connect

■DJA_, for the Digital Jitter Attenuator

■TPG_ a nd TPM_, for the Test-Pat tern Generator/

Detection

A su ffix is appended to the base name of three com-

mon param eters :

■_IS, for i nterr upt s i gnal.

■_IM, for interrupt m as k.

■_SWRS, fo r software reset.

7Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

2 Preface (continued)

2. 3 Overview

The SONET/SDH Super Mapper device integrates the S ONE T/ S DH line, path, and tributary termination functions

with M13 multip lex functions and the primary rate framing fun ction. It is d esigned to drive an OC-3/ST M-1 optical

signal directly or to a llow for modular growth in termina l o r add /drop applications.

It provides a versatile interface for all STS-3/STM- 1 and ST S-1 termination applications in point-to-point sc ena rios

and for ring applic ations. This chip can be used in tributary shelf applications for up to 28 T1 or J1 or 21 E1 line

cards prov iding all possible mappings into SON ET /SDH. Because of the flexib ility of the mappings, s oftware

upgrades f rom M13 mapped connections t o VT/TU mapped connec tions a re possible. This device ca n also be

use d for DS3/DS2 applications.

A single Super Mapper is capable of pr oc es sing the aggregate bandwidth of one ST S-1 or DS3. By communicating

to two other mate devic es via the telecom bus inter face, the Super Mapper is capable of term inat ing a full

STS-3/STM-1 signal.

5-8923(F)

Figure 1 . Functional D i agr am of Sup er Mapper

TMUX

SPE/

AU-3

MAPPER

M13

MUX

VT/VC

MAPPER

TEST

PATTERN

GEN/MON

FRAMER

BANK

DIGITAL

JITTER

ATTENUATOR

T1/E1

DS2

DS3

CROSS

CONNECT

OVERHEAD

STS-1/

STS-3

MSP

MPU INTERFACE

AND CONTROL

MPU INTERFACE

TE LECO M BUS

MAPPI N G &

DS3

T1/E1/J1

SYS TEM INTERFACE

DS0/E0

DS1 (X29)

DS2 (X7)

DS1XCLK

DS1/E1

DS3/STS1

TPOAC

RPOAC

TTOAC

RTOAC

LOPOHOUT

LOPOHIN

TCB AND TDL

LINERX

LINETX

MISC

DS2AISCLK

SYS TERMINATION MULTIPLEXING FRAMING

STM-1

AU-3

1 + 1

CLK

SYNC

RCB AND RDL

E1XCLK

(NSMI MODE)

/ E1 ( X22 )

(XN)

BUS

8Agere Sy stem s Inc.
TMXF 28155 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
Interface  Specifications
3 Pin Informa ti on
Ta ble of Conte nts
Contents Page
3 Pin Information  ..................................................................................................................................................... 8
3.1  456-Pin PBGA Pin Diagram ......................... ....... ............ ....... .......... ....... ......... .......... ....... ............................. 9
3. 2  Pin  Assignment s ..... ............................ ....................................................................... .................................... 9
3. 3  Pin  Descriptio n s . ............................................... ........................................................................................... 15
3.3 .1 High -speed I/O Pin Description s ........................................................................................................ 15
3.3 .2 Protection Switch I/O Pin Description  ................................................................................................ 16
3.3.3 Telecom Bus (Low-speed I/O) Pin Description  ...... . ....................... ..................... . .................. . ........... 16
3.3 .4 TOAC and POAC ............................................................................................................................... 19
3.3 .5 Miscellane ous Signals ........................................................................................................................ 20
3.3 .6 DS3 Port ............................................................................................................................................. 20
3.3 .7 M13 Multip lexer/Demultiplexer Receive Section ................................................................................ 22
3.3.8 Low-Order Path Overhead Access Channel ...................................................................................... 23
3.3 .9 Framer PLL ........................................................................................................................................ 27
3. 3. 1 0 Test Pins ..... ................................. .................................................... ................................................ 30
3. 4  Outline Diagram ......................................... .................................................................................................. 32
3.4 .1 456-Pin PBGA .................................................................................................................................... 32
List o f Fig ures
Figure 2 . Pin Diagram  of 456-Pin PBGA (Bott om View).................... ..... ..... ... .................. ..... ... ................................ 9
Fig ure 3. Protection Switch..................................................................................................................................... 16
Fig ure 4. DS1/E1 to DXC Bl ock Diag ram............................................................................................................... 23
List of Ta bles
Table 1 . Pin Assignments for 456-Pin PBGA  by Pin Number Orde r  ........................ ... .................. ..... ..................... 9
Table 2. Pin Assign ments for 456-Pin PBGA by Signal Name ....... ............................ .......... ................................. 12
Tabl e  3. Hi g h -sp e ed I/ O Pin Descriptio n s  ............................................................................................................. 15
Tabl e  4. Protecti o n  Switch I/O Pin  Descri p tion ...................................................................................................... 16
Table 5 . Telecom Bus (Low-spe ed I/O) Pin Description  ........................................................................................ 17
Tabl e  6. T OA C and POAC  ........................................... ......................................................................................... 19
Table 7. Mi s ce llaneous Signals ................................................. ............................................................................ 20
Table 8. DS3 Port .................................................................................................................................................. 21
Table 9 . DS3 Port, C-Bit, and Datalink Access  ....... ................ ................... ..................... ...................................... 22
Table 1 0. M 13 Multiplexer/Demultiplexer Receive Section  ................................................................................... 22
Tab le 11. Low-Ord er  Path Overhead Access C hannel  ......................................................................................... 23
Table 1 2. M ultifunction System Interface Transmit Path Direction ........................................................................ 24
Table 13. Framer PLL ............................................................................................................................................ 27
Table 1 4. Microprocessor Interfaces ..................................................................................................................... 28
Table 15. General Pu rpose Interface  .................................................................................................................... 29
Table 16. Test  Pins ................................................................................................................................................ 30
Table 17. CDR Power ............................................................................................................................................ 30
Tabl e  18. L VDS Control Pin s .......................... ....................................................................... .. .............................. 30

9Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

3.1 456-Pin PBGA Pin Diagram

5-8931(F)

Figure 2. Pin Di a gr a m of 456-Pin PBGA (Bott om View)

3.2 P in Assignm ents

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Or der

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Na me

A1 VDD A21 VSS B15 LINETXDATA2 C9 LINERXSYNC24

A2 VSS A22 VDD B16 LINETXSYNC4 C10 LINERXCLK25

A3 LINERXDATA17 A23 LINETXSYNC12 B17 LINETXSYNC5 C11 LINERXCLK26

A4 LINERXDATA18 A24 LINETXSYNC13 B18 LINETXSYNC6 C12 LINERXCLK27

A5 VDD A25 VSS B19 LINETXCLK7 C13 LINERXDATA28

A6 VSS A26 VDD B20 LINETXDATA8 C14 LINETXSYNC2

A7 LINERXDATA21 B1 VSS B21 LINETXSYNC10 C15 LINETXCLK3

A8 LINERXSYNC23 B2 LINERXCLK15 B22 LINETXDATA10 C16 LINETXCLK4

A9 LINERXCLK24 B3 LINERXSYNC18 B23 LINETXDATA11 C17 LINETXCLK5

A10 VDD B4 LINERXSYNC19 B24 LINETXDATA12 C18 LINETXDATA6

A11 VSS B5 LINERXSYNC20 B25 LINETXCLK13 C19 LINETXSYNC8

A12 LINERXDATA27 B6 LINERXDATA20 B26 VSS C20 LINETXCLK9

A13 LINERXSYNC29 B7 LINERXSYNC22 C1 LINERXSYNC15 C21 LINETXCLK10

A14 LINETXDATA1 B8 LINERXCLK23 C2 LINERXDATA14 C22 LINETXCLK11

A15 LINETXSYNC3 B9 LINERXDATA24 C3 LINERXCLK17 C23 LINETXCLK12

A16 VSS B10 LINERXDATA25 C4 LINERXCLK18 C24 LINETXCLK14

A17 VDD B11 LINERXDATA26 C5 LINERXCLK19 C25 LINETXSYNC15

A18 LINETXCLK6 B12 LINERXSYNC28 C6 LINERXCLK20 C26 LINETXDATA14

A19 LINETXDATA7 B13 LINERXCLK29 C7 LINERXCLK21 D1 LINERXSYNC14

A20 LINETXSYNC9 B14 LINETXCLK1 C8 LINERXDATA22 D2 LINERXDATA13

BALL

CORNER

10 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Na me

D3 LINERXCLK14 E21 LINETXDATA13 J25 LINETXDATA21 N1 LINERXDATA3

D4 VSS E22 VDD J26 LINETXCLK21 N2 LINERXCLK3

D5 LINERXDATA19 E23 LINETXDATA16 K1 VDD N3 LINERXSYNC4

D6 LINERXSYNC21 E24 LINETXCLK16 K2 LINERXSYNC7 N4 LINERXSYNC3

D7 LINERXCLK22 E25 LINETXSYNC17 K3 LINERXCLK7 N5 SCAN_EN

D8 LINERXDATA23 E26 VDD K4 LINERXDATA6 N11 VSS

D9 LINERXSYNC25 F1 VSS K5 LINERXSYNC16 N12 VSS

D10 LINERXSYNC26 F2 LINERXSYNC12 K22 DS3NEGDATAIN N13 VSS

D11 LINERXSYNC27 F3 LINERXCLK12 K23 LINETXSYNC23 N14 VSS

D12 LINERXCLK28 F4 LINERXDATA11 K24 LINETXCLK22 N15 VSS

D13 LINERXDATA29 F5 LINERXDATA15 K25 LINETXDATA22 N16 VSS

D14 LINETXSYNC1 F22 LINETXSYNC14 K26 VDD N22 DS3DATAOUTCLK

D15 LINETXCLK2 F23 LINETXSYNC18 L1 VSS N23 LINETXDATA26

D16 LINETXDATA3 F24 LINETXCLK17 L2 LINERXSYNC6 N24 LINETXDATA25

D17 LINETXDATA4 F25 LINETXDATA17 L3 LINERXCLK6 N25 LINETXCLK26

D18 LINETXDATA5 F26 VSS L4 LINERXDATA5 N26 LINETXSYNC26

D19 LINETXSYNC7 G1 LINERXSYNC11 L5 VDD P1 LINERXSYNC2

D20 LINETXCLK8 G2 LINERXDATA10 L11 VSS P2 LINERXCLK2

D21 LINETXDATA9 G3 LINERXCLK11 L12 VSS P3 LINERXDATA1

D22 LINETXSYNC11 G4 LINERXCLK10 L13 VSS P4 LINERXDATA2

D23 VSS G5 VSS L14 VSS P5 IDDQ

D24 LINETXCLK15 G22 VSS L15 VSS P11 VSS

D25 LINETXSYNC16 G23 LINETXCLK19 L16 VSS P12 VSS

D26 LINETXDATA15 G24 LINETXCLK18 L22 VDD P13 VSS

E1 VDD G25 LINETXSYNC19 L23 LINETXSYNC24 P14 VSS

E2 LINERXDATA12 G26 LINETXDATA18 L24 LINETXCLK23 P15 VSS

E3 LINERXCLK13 H1 LINERXDATA9 L25 LINETXDATA23 P16 VSS

E4 LINERXSYNC13 H2 LINERXCLK9 L26 VSS P22 DS3NEGDATAOUT

E5 VDD H3 LINERXSYNC10 M1 LINERXSYNC5 P23 LINETXSYNC27

E6 LINERXSYNC17 H4 LINERXSYNC9 M2 LINERXDATA4 P24 LINETXSYNC28

E7 VSS H5 LINERXDATA16 M3 LINERXCLK5 P25 LINETXCLK27

E8 TDLDATA H22 RDLDATA M4 LINERXCLK4 P26 LINETXDATA27

E9 TDLCLK H23 LINETXDATA20 M5 SCAN_MODE R1 RLSDATA7

E10 DS2AISCLK H24 LINETXDATA19 M11 VSS R2 LINERXSYNC1

E11 VDD H25 LINETXCLK20 M12 VSS R3 RLSDATA6

E12 TCBDATA H26 LINETXSYNC20 M13 VSS R4 LINERXCLK1

E13 TCBCLK J1 LINERXCLK8 M14 VSS R5 TCK

E14 TCBSYNC J2 LINERXSYNC8 M15 VSS R11 VSS

E15 RCBDATA J3 LINERXDATA8 M16 VSS R12 VSS

E16 VDD J4 LINERXDATA7 M22 DS3POSDATAIN R13 VSS

E17 RCBCLK J5 LINERXCLK16 M23 LINETXCLK25 R14 VSS

E18 RCBSYNC J22 DS3DATAINCLK M24 LINETXCLK24 R15 VSS

E19 RDLCLK J23 LINETXSYNC22 M25 LINETXSYNC25 R16 VSS

E20 VSS J24 LINETXSYNC21 M26 LINETXDATA24 R22 DS3POSDATAOUT

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

11Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Na me

R23 LINETXCLK28 W5 TMSN AB19 RXDATAEN AD11 RPSC155N

R24 LINETXCLK29 W22 TXDATAEN AB20 VDD AD12 REF14

R25 LINETXDATA28 W23 DATA4 AB21 MODE2_PLL AD13 TPSC155N

R26 LINETXSYNC29 W24 DATA7 AB22 VDD AD14 ECSEL

T1 VSS W25 DATA5 AB23 ADDR19 AD15 TSTSFTLD

T2 RLSDATA4 W26 DATA6 AB24 INTN AD16 DS1XCLK

T3 RLSDATA3 Y1 TLSDATA2 AB25 DATA15 AD17 MPMODE

T4 RLSDATA5 Y2 TLSDATA3 AB26 VDD AD18 DSN

T5 VDD Y3 TLSDATA1 AC1 RLSSYNC52 AD19 ADDR3

T11 VSS Y4 TLSDATA4 AC2 RLSC52 AD20 ADDR7

T12 VSS Y5 VSS AC3 TLSC52 AD21 ADDR10

T13 VSS Y22 VSS AC4 VSS AD22 VDDD_PLL

T14 VSS Y23 DATA8 AC5 TPOACSYNC AD23 VSSS_PLL

T15 VSS Y24 DATA11 AC6 AUTO_AIS1 AD24 CLKIN_PLL

T16 VSS Y25 DATA9 AC7 RHSCP AD25 ADDR16

T22 VDD Y26 DATA10 AC8 THSSYNCP AD26 ADDR15

T23 LINETXDATA29 AA1 VSS AC9 VDDA_CDR AE1 VSS

T24 RSTN AA2 TLSCLK AC10 RPSC155P AE2 TTOACDATA

T25 PMRST AA3 TLSPAR AC11 REF10 AE3 RPOACCLK

T26 VSS AA4 TLSDATA0 AC12 TPSC155P AE4 TPOACCLK

U1 VDD AA5 RTOACSYNC AC13 LOPOHCLKIN AE5 LOSEXT

U2 RLSDATA1 AA22 ADDR13 AC14 LOPOHDATAIN AE6 AUTO_AIS2

U3 RLSDATA0 AA23 DATA12 AC15 ETOGGLE AE7 RHSDN

U4 RLSDATA2 AA24 DATA14 AC16 TSTMUX0 AE8 THSCN

U5 TDI AA25 DATA13 AC17 E1XCLK AE9 THSDN

U22 PHASEDETDOWN AA26 VSS AC18 CSN AE10 RPSD155N

U23 DTN AB1 VDD AC19 ADDR0 AE11 CTAPTH

U24 PAR1 AB2 TLSSPE AC20 ADDR4 AE12 RESLO

U25 PAR0 AB3 TLSV1 AC21 ADDR8 AE13 TPSD155N

U26 VDD AB4 TLSJ0J1V1 AC22 ADDR12 AE14 BYPASS

V1 RLSSPE AB5 VDD AC23 VSS AE15 EXDNUP

V2 RLSPAR AB6 TTOACCLK AC24 ADDR17 AE16 TSTMUX1

V3 RLSJ0J1V1 AB7 VSS AC25 APS_INTN AE17 MPCLK

V4 RLSCLK AB8 TRSTN AC26 ADDR18 AE18 ADSN

V5 TDO AB9 IC3STATEN AD1 RTOACCLK AE19 ADDR1

V22 PHASEDETUP AB10 CTAPRH AD2 TLSSYNC52 AE20 ADDR5

V23 DATA0 AB11 VDD AD3 RTOACDATA AE21 ADDR9

V24 DATA3 AB12 VSSA_CDR AD4 RPOACDATA AE22 ADDR11

V25 DATA1 AB13 CTAPRP AD5 TPOACDATA AE23 VDDS_PLL

V26 DATA2 AB14 LOPOHVALIDIN AD6 AUTO_AIS3 AE24 MODE1_PLL

W1 TLSDATA6 AB15 LOPOHCLKOUT AD7 RHSFSYNCN AE25 ADDR14

W2 TLSDATA7 AB16 VDD AD8 RHSCN AE26 VSS

W3 TLSDATA5 AB17 LOPOHDATAOUT AD9 THSSYNCN AF1 VDD

W4 RLSV1 AB18 LOPOHVALIDOUT AD10 RPSD155P AF2 VSS

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

12 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Na me

AF3 TTOACSYNC AF9 THSDP A15 TSTMODE AF21 VSS

AF4 RPOACSYNC AF10 VDD A16 VSS AF22 VDD

AF5 VDD AF11 VSS A17 VDD AF23 VSSA_PLL

AF6 VSS A12 REWSHI A18 RWMN AF24 MODE0_PLL

AF7 RHSDP AF13 TPSD155P A19 ADDR2

AF8 THSCP AF14 TSTPHASE AF20 ADDR6

Table 2. P in Assignments for 456-Pin PBGA by Signal Name

Signal Name Pin Signal Name Pin Signal Name Pin Sig nal Name Pin

ADDR0 AC19 CTAPRP AB13 ECSEL AD14 LINERXCLK24 A9

ADDR1 AE19 CTAPTH AE11 ETOGGLE AC15 LINERXCLK25 C10

ADDR2 AF19 DATA0 V23 EXDNUP AE15 LINERXCLK26 C11

ADDR3 AD19 DATA1 V25 IC3STATEN AB9 LINERXCLK27 C12

ADDR4 AC20 DATA2 V26 IDDQ P5 LINERXCLK28 D12

ADDR5 AE20 DATA3 V24 INTN AB24 LINERXCLK29 B13

ADDR6 AF20 DATA4 W23 LINERXCLK1 R4 LINERXDATA1 P3

ADDR7 AD20 DATA5 W25 LINERXCLK2 P2 LINERXDATA2 P4

ADDR8 AC21 DATA6 W26 LINERXCLK3 N2 LINERXDATA3 N1

ADDR9 AE21 DATA7 W24 LINERXCLK4 M4 LINERXDATA4 M2

ADDR10 AD21 DATA8 Y23 LINERXCLK5 M3 LINERXDATA5 L4

ADDR11 AE22 DATA9 Y25 LINERXCLK6 L3 LINERXDATA6 K4

ADDR12 AC22 DATA10 Y26 LINERXCLK7 K3 LINERXDATA7 J4

ADDR13 AA22 DATA11 Y24 LINERXCLK8 J1 LINERXDATA8 J3

ADDR14 AE25 DATA12 AA23 LINERXCLK9 H2 LINERXDATA9 H1

ADDR15 AD26 DATA13 AA25 LINERXCLK10 G4 LINERXDATA10 G2

ADDR16 AD25 DATA14 AA24 LINERXCLK11 G3 LINERXDATA11 F4

ADDR17 AC24 DATA15 AB25 LINERXCLK12 F3 LINERXDATA12 E2

ADDR18 AC26 DS1XCLK AD16 LINERXCLK13 E3 LINERXDATA13 D2

ADDR19 AB23 DS2AISCLK E10 LINERXCLK14 D3 LINERXDATA14 C2

ADSN AE18 DS3DATAINCLK J22 LINERXCLK15 B2 LINERXDATA15 F5

APS_INTN AC25 DS3DATAOUTCLK N22 LINERXCLK16 J5 LINERXDATA16 H5

AUTO_AIS1 AC6 DS3NEGDATAIN K22 LINERXCLK17 C3 LINERXDATA17 A3

AUTO_AIS2 AE6 DS3NEGDATAOUT P22 LINERXCLK18 C4 LINERXDATA18 A4

AUTO_AIS3 AD6 DS3POSDATAIN M22 LINERXCLK19 C5 LINERXDATA19 D5

BYPASS AE14 DS3POSDATAOUT R22 LINERXCLK20 C6 LINERXDATA20 B6

CLKIN_PLL AD24 DSN AD18 LINERXCLK21 C7 LINERXDATA21 A7

CSN AC18 DTN U23 LINERXCLK22 D7 LINERXDATA22 C8

CTAPRH AB10 E1XCLK AC17 LINERXCLK23 B8 LINERXDATA23 D8

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

13Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Signal Name Pin Signal Name Pin Signal Name Pin Sig nal Name Pin

LINERXDATA24 B9 LINETXCLK7 B19 LINETXDATA19 H24 LOPOHCLKOUT AB15

LINERXDATA25 B10 LINETXCLK8 D20 LINETXDATA20 H23 LOPOHDATAIN AC14

LINERXDATA26 B11 LINETXCLK9 C20 LINETXDATA21 J25 LOPOHDATAOUT AB17

LINERXDATA27 A12 LINETXCLK10 C21 LINETXDATA22 K25 LOPOHVALIDIN AB14

LINERXDATA28 C13 LINETXCLK11 C22 LINETXDATA23 L25 LOPOHVALIDOUT AB18

LINERXDATA29 D13 LINETXCLK12 C23 LINETXDATA24 M26 LOSEXT AE5

LINERXSYNC1 R2 LINETXCLK13 B25 LINETXDATA25 N24 MODE0_PLL AF24

LINERXSYNC2 P1 LINETXCLK14 C24 LINETXDATA26 N23 MODE1_PLL AE24

LINERXSYNC3 N4 LINETXCLK15 D24 LINETXDATA27 P26 MODE2_PLL AB21

LINERXSYNC4 N3 LINETXCLK16 E24 LINETXDATA28 R25 MPCLK AE17

LINERXSYNC5 M1 LINETXCLK17 F24 LINETXDATA29 T23 MPMODE AD17

LINERXSYNC6 L2 LINETXCLK18 G24 LINETXSYNC1 D14 PAR0 U25

LINERXSYNC7 K2 LINETXCLK19 G23 LINETXSYNC2 C14 PAR1 U24

LINERXSYNC8 J2 LINETXCLK20 H25 LINETXSYNC3 A15 PHASEDETDOWN U22

LINERXSYNC9 H4 LINETXCLK21 J26 LINETXSYNC4 B16 PHASEDETUP V22

LINERXSYNC10 H3 LINETXCLK22 K24 LINETXSYNC5 B17 PMRST T25

LINERXSYNC11 G1 LINETXCLK23 L24 LINETXSYNC6 B18 RCBCLK E17

LINERXSYNC12 F2 LINETXCLK24 M24 LINETXSYNC7 D19 RCBDATA E15

LINERXSYNC13 E4 LINETXCLK25 M23 LINETXSYNC8 C19 RCBSYNC E18

LINERXSYNC14 D1 LINETXCLK26 N25 LINETXSYNC9 A20 RDLCLK E19

LINERXSYNC15 C1 LINETXCLK27 P25 LINETXSYNC10 B21 RDLDATA H22

LINERXSYNC16 K5 LINETXCLK28 R23 LINETXSYNC11 D22 REF10 AC11

LINERXSYNC17 E6 LINETXCLK29 R24 LINETXSYNC12 A23 REF14 AD12

LINERXSYNC18 B3 LINETXDATA1 A14 LINETXSYNC13 A24 RESHI AF12

LINERXSYNC19 B4 LINETXDATA2 B15 LINETXSYNC14 F22 RESLO AE12

LINERXSYNC20 B5 LINETXDATA3 D16 LINETXSYNC15 C25 RHSCN AD8

LINERXSYNC21 D6 LINETXDATA4 D17 LINETXSYNC16 D25 RHSCP AC7

LINERXSYNC22 B7 LINETXDATA5 D18 LINETXSYNC17 E25 RHSDN AE7

LINERXSYNC23 A8 LINETXDATA6 C18 LINETXSYNC18 F23 RHSDP AF7

LINERXSYNC24 C9 LINETXDATA7 A19 LINETXSYNC19 G25 RHSFSYNCN AD7

LINERXSYNC25 D9 LINETXDATA8 B20 LINETXSYNC20 H26 RLSC52 AC2

LINERXSYNC26 D10 LINETXDATA9 D21 LINETXSYNC21 J24 RLSCLK V4

LINERXSYNC27 D11 LINETXDATA10 B22 LINETXSYNC22 J23 RLSDATA0 U3

LINERXSYNC28 B12 LINETXDATA11 B23 LINETXSYNC23 K23 RLSDATA1 U2

LINERXSYNC29 A13 LINETXDATA12 B24 LINETXSYNC24 L23 RLSDATA2 U4

LINETXCLK1 B14 LINETXDATA13 E21 LINETXSYNC25 M25 RLSDATA3 T3

LINETXCLK2 D15 LINETXDATA14 C26 LINETXSYNC26 N26 RLSDATA4 T2

LINETXCLK3 C15 LINETXDATA15 D26 LINETXSYNC27 P23 RLSDATA5 T4

LINETXCLK4 C16 LINETXDATA16 E23 LINETXSYNC28 P24 RLSDATA6 R3

LINETXCLK5 C17 LINETXDATA17 F25 LINETXSYNC29 R26 RLSDATA7 R1

LINETXCLK6 A18 LINETXDATA18 G26 LOPOHCLKIN AC13 RLSJ0J1V1 V3

Table 2. P in Assignments for 456-Pin PBGA by Signal Name (continued)

14 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Signal Name Pin Signal Name Pin Signal Name Pin Sig nal Name Pin

RLSPAR V2 TLSPAR AA3 VDD AB11 VSS N12

RLSSPE V1 TLSSPE AB2 VDD AB16 VSS N13

RLSSYNC52 AC1 TLSSYNC52 AD2 VDD AB22 VSS N14

RLSV1 W4 TLSV1 AB3 VDD AB26 VSS N15

RPOACCLK AE3 TMSN W5 VDD AF1 VSS N16

RPOACDATA AD4 TPOACCLK AE4 VDD AF5 VSS P11

RPOACSYNC AF4 TPOACDATA AD5 VDD AF10 VSS P12

RPSC155N AD11 TPOACSYNC AC5 VDD AF17 VSS P13

RPSC155P AC10 TPSC155N AD13 VDD AF22 VSS P14

RPSD155N AE10 TPSC155P AC12 VDD AF26 VSS P15

RPSD155P AD10 TPSD155N AE13 VDDA_CDR AC9 VSS P16

RSTN T24 TPSD155P AF13 VDDD_PLL AD22 VSS R11

RTOACCLK AD1 TRSTN AB8 VDDS_PLL AE23 VSS R12

RTOACDATA AD3 TSTMODE AF15 VSS A2 VSS R13

RTOACSYNC AA5 TSTMUX0 AC16 VSS A6 VSS R14

RWN AF18 TSTMUX1 AE16 VSS A11 VSS R15

RXDATAEN AB19 TSTPHASE AF14 VSS A16 VSS R16

SCAN_EN N5 TSTSFTLD AD15 VSS A21 VSS T1

SCAN_MODE M5 TTOACCLK AB6 VSS A25 VSS T11

TCBCLK E13 TTOACDATA AE2 VSS B1 VSS T12

TCBDATA E12 TTOACSYNC AF3 VSS B26 VSS T13

TCBSYNC E14 TXDATAEN W22 VSS D4 VSS T14

TCK R5 VDD A1 VSS D23 VSS T15

TDI U5 VDD A5 VSS E7 VSS T16

TDLCLK E9 VDD A10 VSS E20 VSS T26

TDLDATA E8 VDD A17 VSS F1 VSS Y5

TDO V5 VDD A22 VSS F26 VSS Y22

THSCN AE8 VDD A26 VSS G5 VSS AA1

THSCP AF8 VDD E1 VSS G22 VSS AA26

THSDN AE9 VDD E5 VSS L1 VSS AB7

THSDP AF9 VDD E11 VSS L11 VSS AB20

THSSYNCN AD9 VDD E16 VSS L12 VSS AC4

THSSYNCP AC8 VDD E22 VSS L13 VSS AC23

TLSC52 AC3 VDD E26 VSS L14 VSS AE1

TLSCLK AA2 VDD K1 VSS L15 VSS AE26

TLSDATA0 AA4 VDD K26 VSS L16 VSS AF2

TLSDATA1 Y3 VDD L5 VSS L26 VSS AF6

TLSDATA2 Y1 VDD L22 VSS M11 VSS AF11

TLSDATA3 Y2 VDD T5 VSS M12 VSS AF16

TLSDATA4 Y4 VDD T22 VSS M13 VSS AF21

TLSDATA5 W3 VDD U1 VSS M14 VSS AF25

TLSDATA6 W1 VDD U26 VSS M15 VSSA_CDR AB12

TLSDATA7 W2 VDD AB1 VSS M16 VSSA_PLL AF23

TLSJ0J1V1 AB4 VDD AB5 VSS N11 VSSS_PLL AD23

Table 2. P in Assignments for 456-Pin PBGA by Signal Name (continued)

15Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

3.3 P in Descriptions

3.3.1 High-speed I/O Pin Descriptions

The high spe ed I/O co nsists of five LVDS signals (10 pins) that connect the Su per Mapper to an external OC-3

optics device. I t e xchanges an STS-3 or STM-1 signal between the TMUX and an OC-3 transceiver. The Super

Mapper is capable of recovering a clock f rom the receive data, or can accept a clock recovered externally by the

optics device. I f internal c lock recove r y i s used, the Super Mapper uses TH SCP/N as a reference.

The high-speed I/O may also r un at 52.8 4 Mbits /s in applicati ons that terminate an STS-1 or EC-1 s ignal. In this

case, the (electri cal) line signals are typically terminat ed by a line int erfa c e unit (LIU) chip. The operating speed of

the high-speed I/O is determined by T MUX_RCV_TX _MODE.

Table 3. Hi gh-speed I/O Pin Descriptions

Pin Symbol Type I/O Description

AF7,

AE7 RHSDP

RHSDN LVDS I Receive High-speed Data. 155.52 M bits/s serial data input in STS-1 or

STM-1 format, or 51.84 Mbits/s data in STS-1 format. If RHSD is not used

(in a slave Super Mapper, for example) the P input should be pulled high

through a 1 kΩ resistor and the N input pulled low through a 1 kΩ resistor.

RHSD is ty picall y provided by and OC-3 receiver, an STS-1 line interfac e

unit or an h igher order (e.g. ST S-12) demultiplexing ch ip.

AC7,

AD8 RHSCP

RHSCN LVDS I Receive High-speed Clock. 155.52 or 51.84 MHz clock for STS-3 or

STS-1 input data. Typically supplied by an external OC-3 opto-electonic

device, or an STS-1/EC1 line interface unit, synchronous with R H SD. I f

the internal clock recovery (CDR) feat ure is enabled, R HC is not required

and should be c onnected to t hrough 1 kΩ resistors to VDD (RHCP input)

and VSS (RHCN input).

AF8,

AE8 THSCP

THSCN LVDS I Transmit High-speed Clo ck. Transmit 155.52 MHz or 51.84 MHz clock.

Maste r clock for the transmit sections of the TMUX, telecom bus, SPE ,

and VT mappers. THSC is also used as a reference clock for the receive

CDR, if it is being used.

AC8,

AD9 THSSYNCP

THSSYNCN LVDS I Transmit High-speed Frame Synchroniz ation. An optional input that

may be used to specify the position of the transmit STS-3, STM-1, or

STS-1 frame. THSSYNC m ark s the position of bit 1 of the A1 byte, i.e.,

the first bit of the overhead in the THSD output. If THSSYNC is not used,

the P input should be pulled high through a 1 kΩ res istor, and the N input

pulled low through a 1 kΩ resistor. A typical application f or this pin may be

to synchronize a group of Super Mappers, so that their ST S-3 outputs

may be multiplexed into an STS-12 signal.

AF9,

AE9 THSDP

THSDN LVDS O Transmit High-speed Data. Transmit output for STS-3, STM-1, or STS-1

serial data. Ty pically connected to an OC-3 module or an LIU, if operating

in STS-1 mode. May also be connected to a higher order multiplexing

devi ce, STS-12 for example.

16 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

3.3.2 Protection Switch I/O Pin Description

The prote ction switch I/O provides additional copies of the high-speed interf ace signals so that various protection

schemes may be implemented. The protecti on interf ace ma y be used when the high-speed interface is operating in

both STS-3 and STS-1 modes. If the protection port is not used, the input clo ck and dat a may be left unconnected,

tied to power ( P inputs), or ground (N i nput s ) through 1 kΩ resistors. Unused protection outputs should be l ef t

unconnected.

Table 4. Pr otection Switch I/ O Pin Descri ption

Figure 3 . Protection Sw itch

3.3.3 Telecom Bus (Low-speed I/O) Pin Description

The telecom bus on the Super Mapper is us ed for interconnecting STS-1 signals. It has two eight-bit data buses,

one for upstream data and one for downstream data, plus clock and frame indication signals for each bus. T he tele-

com bus can operate at 19.44 MHz (space for three S TS-1 signals ) or 6.48 MHz (space for 1 STS-1 signal) .

Super Mappers in OC - 3 applicati ons are typi cally connected together using the telecom bus, and the bus is config-

ured to operate at 19.44 MHz.

Pin Symbol Type I/O Description

AD10,

AE10 RPSD155P

RPSD155N LVDS I Receive Protection Data. Receive side high-speed serial data input

from protection board.

AC10,

AD11 RPSC155P

RPSC155N LVDS I Receive Protection Clock. Receive side high-speed cl ock input from

pro tection board .

AF13,

AE13 TPSD155P

TPSD155N LVDS O Transmit Protection Data. Transmit side high-speed serial data output

to protection board.

AC12,

AD13 TPSC155P

TPSC155N LVDS O Transmit Protection Clock. Transmit side high-speed clock output t o

pro tection board .

STS-3 TRANSMIT

FRAMER

STS-3 RECEIVE

FRAMER

RPSMUXSEL1

HIGH-SPEED

PROTECTION

INPUTS

TPSMUXSEL2

HIGH-SPEED

PROTECTION

OUTPUTS

TPSMUXSEL3

HI GH-SPEE D I/O

17Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Table 5. Telecom Bus (Low-speed I/O) P in Description

Pin Symbol Type I/O Description

R1, R3, T4, T2 ,

T3, U4, U2, U3 RLSDATA[7:0] —I/O Receive Low-speed Data (7:0), Pa rallel Data Bus. Used

to connect the downstream ST S-1 signa ls from the master

to the slave devices. In master mode, RLSDATA is an out-

put bus, eight bits wide. It contains all the received data for

distribution to the two slave devices. Connect to

RLS DATA(7:0) on the slave devi ces. In slave mode, thes e

pins are inputs and should be connect ed to the

RLSD ATA(7:0) outputs on the master. RLSD ATA contains

three byte-interleaved STS-1 time slots. The slot use d b y

each SPE mapper in the slaves and the master device, is

determ ined by programing the SPE_RS TS3_TMSLOT reg-

ister bits.

V4 RLSCLK —I/O Receive Low-speed Clock. Th is is a 19.44 M Hz or

6.48 MHz clock for the recei ve low speed data b i ts. In

19.44 MHz m ast er m ode, this is a 19.44 MHz clock output

for distribution to the two slave devices. Connect to

RLSCLK on the slav es. RLSCLK is an input signal on sla ve

devices.

Note: As outputs, these pins have 6 mA drive c apability.

V2 RLSPAR —I/O Receive Lo w-speed Parity . Receive data parity bit, ma y be

configured for odd or even parity generat ed on

RLSDATA(7:0). The defaul t is odd parity; it may be set to

even by setting bit 2 of the register at 0x4001B an output in

master mode and an input in slave mode. Connect the

RSLPA R (out put) on the master to T he RLS PAR (input)

pins on the slaves.

V1 RLSSPE —I/O Receive Low-speed SPE Marker. Receive synchronous

payl oad envelop e timing indicator. It is high, while there is

SPE data on the RLSDATA(7:0) output bus. Connect to

RLSSPE on the slaves. RLSSPE is an input on slave

devices.

V3 RLSJ0J1V1 —I/O Receive Low-speed J0/J1/ V1 Marker. On the master

device, this is an output that is high while J0-1, J1

(1, 2 and 3) and V1 (1, 2 and 3) bytes are pre sent on the

RLSD ATA b us. Connect to RLSJ0J1V1 on the slav es, which

is an inp u t.

W4 RLSV1 —I/O Receive Low-speed V1 Marker. Receive V1 timing indica-

tor. On the master this is an output that is high while the V1

byt es (1, 2 and 3) are present on RLSD ATA(7:0) output bus .

Connect to RLSV1 on the slaves.

18 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued)

Pin Symbol Type I/O Description

W2, W1, W3, Y4,

Y2, Y1, Y3, AA4 TLSDATAI[7:0] —I/O Transmit Low-speed Data (7:0). This i s a parallel data

bus. It is used to connect the upstream STS-1 signals from

the slave devices to the master device. In master mo d e,

TLSDATA is an input bus, eight bits wide. It contains all the

transmit STS-1 data from the slave devices. In slave mode,

these pins are outputs and should be conne ct e d t o t he

TLSDATA(7:0) inputs on the master. TLSDATA contains

three byte-interleaved STS-1 time slots. The slot used by

each SPE mapper in the slaves and the master device, is

determ ined by programing the SPE_TSTS3_TMSLOT reg-

ister bits.

AA2 TLSCLK —I/O Transm it Low-speed Clock. This is a 19 .44 M H z or

6.48 MHz clock for the TLSDATA(7:0) bits. TLSCLK is an

output on a master Super Mapper and an input on a slave.

Note: As outputs, these pins have 6 mA drive c apability.

AA3 TLSPAR —I/O Transmit Low-speed Parity. This parity bit is generated on

the TLSDATA(7:0) bits output f rom slav e devices and input

to the master Super Mapper. May be configured for odd or

even parity generation or for checking.

AB2 TLSSPE —I/O Transm it Low-speed SPE Marker. High while the STS-1

payloads are present on th e TLSDAT A(7:0) bus. Low while

the STS-1 overhead is present on the TLSDATA(7:0) bus.

An output from the master and input on the slaves.

AB4 TLSJ0J1V1 —I/O Transm it Low-speed J 0/J1/V1 Marker. Transmit J0, J1, or

V1, timing i ndicat or. High while the J0, J1 or V1 bits are

present on the TLSDATA(7:0) bus. An output on the master

and input on slaves.

AB3 TLSV1 —I/O Transmit Low-speed V1 Marker 3. Tr ansmit V1 timing indi-

cator. High while the V1 bits are present on the

TLSDATA(7:0) bus. An output on the master and input on

slaves.

AC2 RLSC52 —I/O Receive Low-speed Clock. When in output (master)

mode, it is the receive side of the 51.84 MHz clock output,

synchronous to the receive high-speed input clock (data).

When in input (slave) mode, it receive s a 51.84 MHz clock

input, s y nc hronous to the receive high-speed input clock

(data).

Note: As outputs, these pins have 6 mA drive c apability.

AC1 RLSSYNC52 —I/O Receive Low-speed Sync. When in output (master) mode,

it is the receive side frame sync output sy nchronous to a

51.84 MH z o utp ut. When in input mode, it is the receive

side frame sync i nput sy nchronous to a 51.84 MHz inp ut.

19Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued)

3.3.4 TOAC and POAC

The transport and path overhead acces s channels (TOAC an d POAC) allow parts of the S ONE T/SDH overhead to

be examined externally (receive direction) or overwritten (transmit direction) through serial data ports. Each port

has clock and data lines and synchronization signal that marks the last bit of the frame so that the rest of the over-

head bytes can be ident ified.

The receive TOAC and POAC channels contain all of the respective overheads bytes. The transmit channels con-

tain spa ce for all the overhea d bytes, but whether they ar e actually transmitted depend on how the d evice is pro-

grammed. Some overhead bytes can not be modified; others may be m odified on ly through t he CPU port; some

may be modified only through the overhead access channels; and some may be modified either through the CPU

port, or through the overhead access channels.

Pin Symbol Type I/O Description

AC3 TLSC52 —I/O Transm it Low-speed Clock. When in output (master) mode,

it is the transmit side 51.84 MHz clock output synchronous to

transmit high-speed input clock. When in input mode, it

receives a 51.84 M Hz clock input synchronous to transmit

high-speed input c lock

Note: TLSCLK is used as the master clock for the T1/E1

framer and should therefore be provided even if the

TMUX SPE a n d VT mappers are not used.

AD2 TLSSYNC52 —I/O Transm it Low-speed Syn c. When in out put (mast er) mode,

it is the transmit side fra me sync output synchronous to

51.84 MHz output. When in input (slave) mode, it receiv es the

transmit s ide frame sync input synchronous to 51.84 MHz

input.

Table 6. TOAC and POAC

Pin Symbol Type I/O Description

AD1 RTOACCLK —OReceive TOAC Clock. Receive side serial access channel

clock output for the transport overhead bytes.

AD3 RTOACDATA —ORecei ve T OAC Data. Rec eive side seria l access cha nnel

data output for the transport overhead byt es .

AA5 RTOACSYNC —ORe cei ve TO AC Synchr oni z at ion . Receive side sync output

for TOAC channel. Act ive-high during the LSB of the last

byte.

AB6 TTOACCLK —OTran s mit TOAC C l o ck. Transmit side ser ial access channel

clock output for the transport overhead bytes.

AE2 TTOACDATA —I

Pull down Transmit TOAC Data. Transm it side se rial a c cess channel

data input for the transport overhead bytes.

AF3 TTOACSYNC —OTransmit TOAC Synchronization. Transmit side sync out-

put for T OA C channel. Activ e-high during the LSB of the last

byte.

Path Overhead Access Channel (POAC)

AE3 RPOACCLK —OReceive POAC Clock. Receive side serial access channel

clock output for the path overhead bytes.

AD4 RPOACDATA —OReceive POAC Data. Receive side serial acc ess channel

data output for the path overhead bytes.

20 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

3.3.5 Miscellaneous Signa ls

Table 7 . Miscellaneous S ig nal s

3.3.6 DS3 Port

If a DS3 output is required in a Super Mapper application and the DS3 signal has been reco vered (demapped) from

an STS-1, the n it is necessary to s mooth the DS3 r ecovered clock. The DS3 clock extracted from the STS-1 clock

will have considerable jitter introduced when th e SON ET overhead is re moved and pointer adj ustments are made.

A phase locked loop is recommended for this purpose. The Super Mapper con tains a phase comparator, that can

be used in conjunction with an external low-pass filter and voltage controlled crystal oscillator to implement the

PLL.

Pin Symbol Type I/O Description

AF4 RPOACSYNC —OReceive PO AC Synchr onization. Receive side sync output

for POAC channel. Act ive-high during the last bit of the last

byte of the PO AC fr ame.

AE4 TPOACCLK —OTransmit PO A C Clock. Transmit side serial access channel

clock output for the path overhead bytes.

AD5 TPOACDATA —I

Pull down Transmit POAC Data. Transmit side serial access channel

data input for the path overhead byte s.

AC5 TPOACSYNC —OTransmit POAC Synchronization. Transmit side sync out-

put for POAC channe l. Active-high during the last bit of the

la st b y te.

Pin Symbol Type I/O Description

AE5 LOSEXT —I

Pull up Loss o f S ignal External. Exte rnal loss of signal input. If

external clock and data recovery is used on the high-speed

I/O port, it may be connected t o thi s input which can be con-

figured to assert the LOS regi ster bit normally ass ociated

with t he internal LOS detecti on in the internal CDR bloc k. The

polarity of LOS may be programmed active-high or low.

AD6, AE6,

AC6 AUTO_AIS —I/O AIS En able (3:1). Control signal for automatic AIS insertion

on each STS1. The STS-1 AIS is applied down stream on the

telecom bus, i.e., it is an output from masters and an input to

slaves. Active-high.

Input when slave mode.

Output when master m ode

If not used, leave open.

AD7 RHSFSYNCN —OReceive High-speed Frame Synchronization. Receive side

frame sync output indicating the fram e location of the high-

speed data input. May be used as a 8 kHz tim ing reference

for networ k synchronization to the receive high-s peed data

input (STS-3 or STS-1).

Table 6. TOAC and POAC (continued)

21Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Table 8. DS3 Port

Pin Symbol Type I/O Description

V22 PHASEDETUP —OPhase Detector Up. Phase error signal out to external filter

a nd VCXO. This ou tput will generate an error signal when

the VCXO output is slower than the reference signal.

U22 PHASEDETDOWN —OPhase Detector Down . Phase error signal out to externa l fil-

ter and VCXO . This output will generate an error si gnal when

the VCXO output is faster that the reference s ignal.

R22 DS3POSDATAOUT —OPositi ve Data Output. Se ria l DS 3 positive data out to LIU

w hen the DS3 output port is operating in dual rail-mode.

N onretu rn to zero DS3 data output whe n the DS3 output is

opera ting in single ended mode.

P22 DS3NEGDATAOUT —ON egative Data Output. Ser ial DS3 negative data output to

LIU when the DS3 port is operating in dual r ai l mode. In sin-

g le rail mode, this outpu t is not used and may be left uncon-

nected.

N22 DS3DATAOUTCLK —I

Pull

down

D S3 Data Out Clock. 44.736 MHz DS3 cl ock in put. If the

Super Mapper is being used to map DS3 data to and from

ST S-1, the n this clock will be suppli ed b y t he externa l VCXO

that is as sociated with the DS3 c lock recovery PLL. In other

D S3 modes (e.g., M13) this i nput will be supplied by an

external crystal oscillator , usually as sociated with a DS3 LIU .

If the DS3 port is n ot us ed, this input may be tied to ground

or left op en, since it is equi pped with an i nternal pull-down

resistor.

M22 DS3POSDATAIN —I

Pull

down

Positi ve Data Input. If the DS3 port is configured in dual-rail

mode, then this input is serial positive data from an external

DS3 LIU. If the DS3 port is configured in single-rail mode,

then this input is serial nonreturn-to zero data from th e exter-

nal LIU.

K22 DS3NEGDATAIN —I

Pull

down

N egative Data I n. In dual rail mode, this is negative data

from an e xternal DS3 LIU. In single rail mode, it may be con-

nected to the bipolar violation output of the external DS3 LIU ,

left unconnected, or ti ed to ground.

J22 DS3DATAINCLK —I

Pull

down

D S3 Data In Clo ck. This is a 44.736 MH z clock input from

the clock recovery in the external DS3 LIU.

22 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Table 9. DS3 Port, C-Bit, and Datalink Access

3.3.7 M13 Multiplexer/Demultiplexer Receive Section

Two grou ps of signals are defined in this s ection. The first group are reference clocks, used internally in the jitter

attenuation and AI S generation processes. Note that these a r e typically supplied by free-running crystal oscillators.

The outputs below provide access to the received C-bits and data link bits extracted from the received DS3 frame.

These operate in the same way if the sourc e of the DS3 s ignal is from an SPE or from the external DS3 port.

Pin Symbol Type I/O Description

E14 TCBSYNC —OTransmit C-Bit Sync. In the C-bit parity mode, 10 C-bits may

opti onally be input for multiplexing into the transmit DS3 frame

throug h the TCBDATA input. The TCBSYNC ou tput is low, except

duri ng the rising edge of TCBCLK th at is us ed to i nput C2.

E13 TCBCLK —OTransmit C-Bit Clock. A gapped clock (nom inally 93.983 kH z) for

accepting selected C-bits on input M13_CBDATA.

E12 TCBDATA —I

Pull down Transmit C-Bit Data. In the C-bit parity mode, the network require-

m ents bi t (C2), a nd th e unused C- bits (C4, C5, C6, C16, C 17, C 18,

C 19, C20, and C21) may optionally b e input for multiplexing in to the

transmit DS3 frame through this input.

E9 TDLCLK —OTransmit Da ta Link Cl ock. A gapped clock (nominally 28.195 kHz)

for accepting path maintenance data link C-bits on input TDLDATA.

E8 TDLDATA —I

Pull down Transmit Data Link Data. The path maintenance data link C-bits

(C13, C14, and C15) ma y opt ionally be input f or multiple xing into the

transmit DS3 frame through this input.

Table 1 0. M13 Multiplexer/Demultiplexer Receive Section

Pin Symbol Type I/O Description

AC17 E1XCLK —I

Pulldown E 1 Reference Clock. This clock is used as a reference for the jitter

attenuator when it is operating in the E1 mode. It must have a fre-

quency of 2.048 MHz, 32.768 MHz, or 65.536 MHz and a stability of

50 ppm. It is also used to generate an E1 AIS (all ones). May be left

unconnected, or tied to ground, if no E1 options are being used.

AD16 DS1XCLK —I

Pulldown DS 1 Reference Clock. This clock is used as a reference for the jit ter

attenuato r when it is op erating in the DS1 or the J1 mode. It must

have a frequency of 1.544 MHz, 24.704 MHz, or 49.408 MHz and a

st ability o f ±32 ppm. T his clo ck sign a l is also used to g enerate DS1

AIS signals. Ma y be left unconnected or tied to ground, if not, no DS1

options are being used.

E10 DS2AISCLK —I

Pulldown DS 2 Reference Clock. A 6.312 MHz ±30 ppm inpu t. In the M23

mode, this clock is used to gener ate DS2 AIS . M ay b e left uncon-

n ected or tied to ground if no DS2 options are being used. Not e that

C-bit parity mode does no require a DS2 reference c l ock.

E18 RCBSYNC —OReceive C-Bit Sync. Ten C-bits are o utput on RCD after they are

demultiplexed from the received DS3 signal. The RCS outp ut is low,

except d uring the ri sing edge of RCD that is used to output C2.

23Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

3.3.8 Low-Order Path Overhead Access Chann el

Each V T has a low-order path overhead, and thi s interface allows access to all LOPOH bits for all VTs. Note that

the purpose of doing this is s lightly different form the t ransport and path overhead a ccess. These are use d to c ross

couple the bits between links in a prot ection scheme, rather than provide access for examination or modific ation of

the overhead, although that is possibl e too.

Table 11. Low-Or der P ath Overhead Access Channel

Figure 4. DS1/E1 to DXC Block Diagram

Pin Symbol Type I/O Description

E17 RCBCLK —OReceive C-Bit Clock. A gapped clock (nominally 93.983 kHz) f or out-

putting selected C-bits on RCD.

E15 RCBDATA —OReceive C-Bit Data. The receiv ed network requirements bit (C2) and

the received unused C-bits (C4, C5, C6, C16, C 17, C18, C19, C20,

and C 21) are output afte r they are demultiplexed from the received

DS3 signal.

E19 RDLCLK —OReceiv e Data Link Clock. A gapped clock (nominally 28.195 kHz )

for outputting path maintenance data li nk C-bits on RDLD.

H22 RDLDATA —OReceive Data Link Data. The received path maintenance data link

C-bits (C13, C14, and C15) that are demultiplexed from the received

DS3 signal.

Pin Symbol Type I/O Description

Transmit Direction

AC13 LOPOHCLKIN —I Pull down 6.48 MHz Low Order Path Overhead Clock.

AC14 LOPOHDATAIN —I Pull down Low-Order Path Overhead Data. (O-bits, V5, J2,

Z6/N2, Z7, and K4 byte. )

AB14 LOPOHVALIDIN —I Pull down Valid LOPOH_DATA.

Receive Direction

AB15 LOPOHCLKOUT —O6.48 MHz Low Orde r Path Overhead Clock.

AB17 LOPOHDATAOUT —OLow-Order Path Overhead Data. (O-bits,V5, J2,

Z6/N2, Z7/K4 byte.)

AB18 LOPOHVALIDOUT —OValid VTMPR_LOPOH_DATA Output.

Table 1 0. M13 Multiplexer/Demultiplexer Receive Section (continued)

VT MAPPER VT MAPPER

LOPOH

OUTPUTS

LOPOH

INPUTS

LOPOH

OUTPUTS

LOPOH

INPUTS

TELE CO M B US

DS1/E1 TO DXC

24 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Table 12. Multifunction System Interface Transmit Path Direction

Pin Symbol Type I/O Description

C13, A12,

B11, B10, B9,

D8, C8, A7,

B6, D5, A4,

A3, H5, F5,

C2, D2, E2,

F4, G2, H1,

J3, J4, K4, L4,

M2, N 1 , P4 ,

LINERXDATA[28:1] —I

Pull down Line Receive Data (2 8:1). Configurabl e inputs to the

internal cross connect. The use depends on the appli-

cation. Generally, these inputs are used for the recei ved

pos itive-rail or single-rail DS1/ E1 line data input. If oper-

a ting in dual rail mode, the negative rail will be ex pected

on LINERXSYNC(28:1). Us ing d ual rail mode implies

that the internal B8ZS or HDB 3 decoders are enabled,

a nd line c ode violation s can be detected and counted

inside th e Super Mapper.

These data inputs may be assigned, using the cross

con nec t block, to the DS1 or E1 inputs on the VT map-

per, M13 or DS1/E1 framers. It is also possible to u se

the inputs for DS2 data, i n which case they may be

assigned to the M23 multiplexer inputs.

D13 LINERXDATA29 —I

Pull down Receive Data 29. Configurable input to the internal

cross connect. May be used as an additional line

receive data input, for a protect ion channel. Other pos-

sibl e uses are as fo llows:

Globa l transmit line clock input. Externally supplied

1.54 4 MHz or 2.048 MHz low jitter clock phase-locked

to the TDM s ystem cloc k. Used for t ransmit line c lock on

the DS1/E1 fr amers. This is not normally used, because

the DS1/ E1 framer has a PLL which can generate a

1.544 MHz clock from the TDM system clock ( CHI

clock). This applies i n PSB and CHI modes.

Receive data input. If NSMI mode is used, this will be a

51.84 Mbits/s serial data input.

D12, C12 ,

C11, C10, A9,

B8, D7, C7,

C6, C5, C4,

C3, J5, B2,

D3, E3, F3,

G3, G4, H2,

J1, K3, L3,

M3, M4, N2,

P2, R4

LINERXCLK[28:1] —I/O

Pull down Receive Clock (28:1). Conf igurable inputs/outputs t o

the internal cross connect. Typically a line clock associ-

ated with the corresponding LINERXDATA input. It can

therefore be running at DS1, E1 or DS2 rate. The c ross

connect is us ed to assign these inputs to the VT map-

per, M13 or DS1 /E1 framers.

B13 LINERXCLK29 —I/O

Pull down Receive Clock 29. May be used as add itional receive

clock input for a DS1/E1 protection chann el. Also has

special u se as a m aste r clock. In C HI mode, it is the

receive clock input (2.048 MHz, 4.096 MHz, 8.192 MHz,

or 16.384 MHz). In PSB m ode, it is the rec eive clock

input (19.44 MHz). In NSMI mode, it is the receiv e clock

outp ut. (51 .84 MHz).

25Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Pin Symbol Type I/O Description

B12, D11,

D10, D9, C9,

A8, B7, D6,

B5, B4, B3,

E6, K5, C1,

D1, E4, F2,

G1, H3, H4,

J2, K2, L2,

M1, N3, N4,

P1, R2

LINERXSYNC[28:1] —ILine Recei ve Synchrono us 28:1. Multifunction inpu t.

C hannel assignment may be co nfig ured through the

internal cross connect. Can be used as the negative rail

of a DS1/E1 signal in conjunction with LINERX-

DATA(28:1), when operating in dual-rail mode. In CHI

mode these inputs are used for receive TDM highways

that may run at 2.048, 4.096, or 8.192 Mbits/s. In p a ral -

lel system b us mode the receive syst em data b us inputs

are assigned to LINERXSYNC 16:1. The PSB is a 16-

bit wide bus that operates at 19.44 MHz.

A13 LINERXSYNC29 —I/O Line Receive Synchronous 29. Multifunction input.

C hannel assignment may be co nfig ured through the

internal cross connect. Can be used as the negative rail

of a DS1/E1 signal in conjunction with LINERXDATA 29,

w hen operatin g i n d ual-ra il mode.

In CHI and PSB modes this input is used as the rece ive

system frame synchronizat ion input . In NSMI mode, it is

the receive frame sync output

R25, P26,

N23, N2 4,

M26, L25,

K25, J25,

H23, H2 4,

G 26, F25,

E23, D26,

C26, E21,

B24, B 23,

B22, D21,

B20, A 19,

C18, D1 8,

D17, D1 6,

B15, A14

LINETXDATA[28:1] —I/O Line Transmit Data (28:1) Co nfigurable out puts f rom

the internal cross connect. Used for transmit positive-

rai l or sin gle-rail DS1/E 1 line d ata outputs. May be co n-

nected to the DS1/E1 outputs from the VT mapper , M13

MUX or DS1/E1 frame line outputs. May also be used

as a DS2 output.

T23 LINETXDATA29 —OLin e Tr ansmit Dat a 29. Configur able output from the

internal cross connect. A n extr a DS1 or E1 transmit port

that may b e used for protectio n o r as a timing reference

output.

Table 12. Multifunction System Interface Transmit Path Direction (continued)

26 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Pin Symbol Type I/O Description

R23, P25,

N25, M23,

M24, L24,

K24, J26,

H25, G 23,

G 24, F24,

E24, D24,

C24, B25,

C23, C22 ,

C21, C20 ,

D20, B19,

A18, C17,

C16, C15 ,

D15, B14

LINETXCLK[28:1] —I/O Line Transmit Clock (28:1). Configurable outputs from

the internal cross connect. Can be used as the clock

signals for LINET XDATA(28:1) in DS1, E1, and DS2

modes.

R24 LINETXCLK29 —I/O L ine Tran smit Clo ck 29. Configurable output to the

internal cross connect for the protection or timing refer-

ence channel. Also used as the transmit glo bal system

clock input f or CHI (2.048 MHz, 4.096 MHz, 8.192 MHz,

or 16.384 MHz ), PSB (19.44 MHz), and NS MI (5 1.84

MHz) modes.

P24, P 23,

N26, M25,

L23, K23, J23,

J24, H26,

G 25, F23,

E25, D25,

C25, F22,

A24, A 23,

D22, B21,

A20, C19,

D19, B18,

B17, B 16,

A15, C14,

D14

LINETXSYNC[28:1] —I/O Line Transmit Synchronous (28:1). C onfigura ble

inputs/outputs to the internal cross connect. An output

w hen used as the negative rail of a DS1 or E1 output

port operating in dual-rail mode. In CHI m ode, these

pins may be used as output TDM highwa ys. I n PSB

mode, bits 16:1 are used for the transmit data bus, and

bits 28: 17 are not used. These pins m ay also be used

as DS 2 I/O to the M12 block as follows: 7:1—Tx data

out. 14:8 —Tx clock in. 21 :16—Rx data in. 28:22—Rx

clock in.

R26 LINETXSYNC29 —I/O Line Tran s mit Sync hronous 29. Configurable input/

output to the internal cross connect. An output when

used as the negative rail of a DS1 or E1 output port

operat ing in dual-r ail mode . In CHI and PSB modes, it is

use d as the transmit s ys tem frame synchronization

input. In NSMI mode, it is the transmit system frame

sync out put.

AB19 RXDATAEN —ONSMI Receive Enable. Receive data enable for NSMI

mode.

W22 TXDATAEN —ONMSI T ran smit Enable. Tr ansmit data enabl e fo r NSMI

mode.

Table 12. Multifunction System Interface Transmit Path Direction (continued)

27Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

3.3.9 Framer PLL

The DS1/E1 framer has a phase-locked loop that may be used to generate a transmit line clock at 1.544 MHz or

2.048 MHz. The reference signal for this PLL may be chosen from a number of possible sources, all ty pically syn-

chronized to the system clock (CHI transmit/receive clock for example.) In order to ensure reliable performance

,this PL L has its own is olated po wer pins. The PLL also has a number o f tes t control pins that are used for factory

testing on ly .

The PLL is active when framer bit PLL_BYPAS = 0. When PLL_BYPAS = 1, the PLL is b ypassed and an external

clock at the s y stem interface is us ed as the line clock. An exampl e would be when the framers are programmed for

a CHI interface at 2.048 MHz and the fram es are programmed for E1, the PLL may be by passed and the CHI sys-

tem clock may be used as the line clock.

Table 13 . Framer PLL

Pin Symbol Type I/O Description

AD22 VDDD_PLL VDD —Digital VDD for PLL.

AE23 VDDS_PLL VDD —Analog VDD for PLL.

AF23 VSSA_PLL VSS —Analog VSS for PLL.

AD23 VSSS_PLL VSS —Digital VSS for PLL.

AD24 CLKIN_PLL —I

Pull down Clock In PLL. Phase l ocked-loop reference clock input. Fre-

quency should be consistent with the MODE_PLL pins in the

PLL M ode1 table below. A 1.544 MHz clo ck for DS1 transmit

outputs i s generated synch ronous to this clock.

AB21 MODE2_PLL —I/O PLL Mode 2. Control bit that should be tied to the appropriate

state depending on the frequency of CLKIN_PLL consistent

with th e PLL Mode1 ta ble below. This pin is al so us ed during

factory te sting as an output.

AF24 MODE0_PLL —I

Pull down PLL Mode 0. PLL control input 0.

AE24 MODE1_PLL —I

Pull down PLL Mod e 1 . PLL control input 1. The PLL mode inputs should

be hardwired to the logic levels shown in the table below,

depending o n the freque n cy of the refer ence s upplied to

CLKIN_PLL.

Mode2

Mode1

Mode0

CLKIN_PLL

Reserved

51.84 MHz

26.624 MHz

19.44 MHz

16.348 MHz

8.194 MHz

4.096 MHz

2.048 MHz

28 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

Table 14. Micropro cessor Interfaces

Pin Symbol Type I/O Description

AE17 MPCLK —IProcessor Clock. This is the syn chronous m icroproc ess or

clock (when MP M ODE=1). The maximum clock frequenc y is

6 6 M Hz. T his clock is requ ired to p roper ly sample address,

data, and control signals from the microprocessor in both

asynchronous and synchronous modes of operatio n. This

clock must be within the range of 16 MH z—66 MHz.

AD17 MPMODE —IContr ol Port Mode. If the microprocessor interface is syn -

chronous, CPM should be set to 1. If the microprocessor

interface is asynchronous, CPM should be set to 0.

AC18 CSN —I

Pul l up Chip Select. Active-low chip select. For synchronous mode,

it should b e stable beyond a certain setup time before the ris-

ing clock edge when AS is active. For asynchronous mo de, it

should be st able before DS is asserted.

AE18 ADSN —IAdd ress St robe. Active-low address strobe that is a 1 PCK

cycle wide pulse for synchronous mode and active for the

entire read/write cycle for asynchronous mode. Addres s bus

signals, A(19:0), are transparentl y latched into Super Mapper

when AS is low. The address bus should remain valid for the

duration of AS.

AF18 RWN —IRead/Write Cycle Selectio n. RW is set high for a read oper-

ation, or set l ow for write operat ion .

AD18 DSN —IData Strobe. DS is not used for synchrono us mode. For

asynchronous mode, write operat ion, DS become s a ctive

after data is st able. F o r read operation, it is si mi l ar t o AS.

AB23, AC26,

AC24, AD25,

AD26, AE25,

AA22, AC22,

AE22, AD21,

AE21, AC21,

AD20, AF20,

AE20, AC20,

AD19, AF19,

AE19, AC19

ADDR[19:0] —IAddress (19:0). A19 is the mos t significant and A0 the least

sig nificant bi t for ad dress ing a ll the in terna l SM reg i ste rs dur-

ing CPU access cycles.

Note: The Super Mapper is little endian, the lea s t significant

byte is stored in the lowest address and the most s ig-

nificant byte is stored i n the highest address. Care

must be exercised in connection to microprocess ors

that use bi g- endian byte or der ing.

AB25, AA24,

AA25, AA23,

Y24, Y 26,

Y25, Y 23,

W24, W 26,

W25, W 23,

V24, V 26,

V25, V 23

DATA[15:0] —I/O Data (15:0). Data bus for all transfers between the CPU and

the internal SM registers. The pins are inputs dur ing write

cycles and outputs during read cycles. DATA15 is the MSB

and DATA0 is the LSB.

U2 4 , U 2 5 PA R [1:0 ] —I/O CPU Port Parity (1:0). Byte-wide parity bits for data. C PP[1]

is the parity for D[15:8] an d CPP[0] is the parity for D[7:0].

29Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Table 1 5 . General Pu rpose Interface

Pin Symbol Type I/O Description

U23 DTN —O

Open Drain Data Transfer Acknowledge. In synchronous CPU mode,

DTA goes low at 4t h cycle for write or 5th cycle for read,

resulting in a fixed 2 wait-states for writes and 3 wait-states

for reads. In asynchronous µP mode, after qualification of AS

and DS by TLSC52 c lock, DTA goes low for two TLSC52

clock cycles for writes and three TLSC52 clock cycles for

reads. DTA goes high, along with the rising edge of AS.

AB24 INTN —O

Open Drain Interrupt. S uper Mapper interrupt request, active-low. An

open drain output should be connec ted to an external pull-up

resistor.

AC25 APS_INTN —O

Open Drain APS I nterr upt. A utomatic protection s witch i nterrupt request,

active-low. An open drain ou t put should be connected to an

external pull-up resistor.

Pin Symbol Type I/O Description

T24 RSTN —I

Pull up Reset. Global reset, act ive-l ow. Initializes all internal registers

to their default s tate.

T25 PMRST —I/O

Pull down Performance Monitor Reset. May be configured as an input

and then used to directly reset all the co unters associ ated with

DS1/E1 performance monitor ing. If an internal PM reset is

used, PMRST is configured as an output that indicates when a

PM reset occurred.

R5 TCK —ITest Clock. This signal provides timing for the boundary s can

and TA P controller. This signal s hould be stati c, except during

boundary scan testing.

U5 TDI —I

Pull up Test Data In. Data input for the boundary scan; sampled on

th e risin g edge of TCK .

W5 TMSN —I

Pull up Test Mode S elect (Activ e-Low). Controls boundary scan test

operations. TMS is sampled on the rising edge of TCK.

AB8 TRSTN —I

Pull down Test Re set (Active-Low). This signal i s an asynchronous

reset for the TAP controller.

V5 TDO —OTest Da ta Out. Updated on the falling edge of TCK. The TDO

output is high impedance, except when sc anning out test data.

AB9 IC3STATEN —I

Pull up Global Output Enable. All output and bidirectional buffers will

be high impedance when this input is low. Normally pulled high

internally.

Table 14. Micropro cessor Interfaces (continued)

30 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

3.3.10 Test Pins

These pins are for fa ctory test purposes o nly and must be connected as stated below for normal operation. They

are used to establish special conf igurati ons f or testing, inserting test data, etc. For normal oper ati on they should be

left unconne cted; each is equipped with a pull-up or pull-down to the inactive (normal operation) state.

Table 16. Test Pins

Table 17. CDR Power

Pin Symbol Type I/O Description

N5 SCAN_EN —I

Pull down Test Only. Scan enable (active-high).

M5 SCAN_MODE —I

Pull down Test Only. Serial scan input for testing (active-high).

P5 IDDQ —I

Pull up Test Only. IDDQ input (active-high).

AE14 BYPASS —I

Pull down T est Only. Enables functional bypassing of the clock synthesis

with a test clock (active-high).

AF14 TSTPHASE —I

Pull down Test Only. Controls bypass of 32 PLL-generated phases with

32 low-speed phases, generated b y test logic (ac tive-high).

AD14 ECSEL —I

Pull down Test Only. Enables ext ernal test control of 155 M Hz clock

phase selection through ETOGGLE and EXDNUP inputs

(active-high).

AC15 ETOGGLE —I

Pulldown Test Only. Moves 155 MHz clock sel ecti on one ph ase per pos-

itive pulse > 20ns. Active + pulse.

AE15 EXDNUP —I

Pulldown Test Only. Direction of phase changes.

0 = down

1 = up.

AF15 TSTMODE —I

Pulldown Test Only. E nables CDR test mode.

AD15 TSTSFTLD —I

Pulldown Test Only. E nables CDR test mode shift register.

AE16 ,

AC16 TSTMUX[1:0] —OTest Only. CDR test mode output

Pin Symbol Type I/O Description

AC9 VDDA_CDR —IAna log Power. Is olated analog power suppl y VDD for CDR.

AB12 VSSA_CDR —IAnalog Ground. Isolated analog power supply VSS for CDR.

Table 18. LVDS Control Pins

Pin Symbol Type I/O Description

AF12

AE12 RESHI

RESLO —IResistor 1, 2. A 100 Ω 1% resistor is sh ould be connected be tween

these two pins as a refer ence for the LVDS input buffer te rmination.

AC11 REF10 —IVoltag e Reference 1. 1.0 V reference voltage input .

AD12 REF14 —IVo ltag e Reference 2. 1.4 V reference voltage input .

31Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

3 Pin Information (continued)

Pin Symbol Type I/O Description

AB10 CTAPRH ——

Center Tap 1. For RHSD P /N and RHSC P/ N. Optional, 0.1 µF

capacitor connected betwe en CTAP pin and ground, to improve the

common mode rej ec tion of the LVDS in put buffers.

AE11 CTAPTH ——

Center Tap 2. For THSD P/N and THSC P/N. Optional, 0.1 µF

capacitor connected betwe en CTAP pin and ground, to improve the

common mode rej ec tion of the LVDS in put buffers.

AB13 CTAPRP ——

Center Tap 3. For RPSD155 P/N and RPSC155 P/N. Optional,

0.1 µF capacit or connected between CTAP pin and groun d, to

improve the common m ode rejection of the LVDS input buffers.

Table 18. LVDS Control Pins (continued)

32 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

3 Pin Information (continued)

3.4 Ou tl in e D iagr a m

3.4.1 456-Pin PBGA

Dimensions are in millimeters.

5-6216(F)r.1

0.56 ± 0.06 1.17 ± 0.05 2.33 ± 0.21

SE ATING PLANE

SOLDER BALL

0.60 ± 0.10

0.20

PWB

MOLD

COMPOUND

35.00 ± 0.20

35.00

± 0.20

+0.70

–0.00

30.00

+0.70

–0.00

30.00

A1 BALL

IDENTIFIER ZON E

25 SPACES @ 1.2 7 = 3 1. 75

1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 2620

11 13 15 17 2119 23 25

CENTER ARRAY

FOR THERMAL

ENHANCEMENT

(OPTIONAL)

25 SPACES

@ 1.27 = 31.75

A1 BAL L

CORNER

0.75 ± 0.15

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
33Agere Systems Inc.  
4 Elect r ic al Char acter isti cs
Ta ble of Conte nts
Contents Page
4 Electrical Characteristics .................................................................................................................................... 33
4. 1  Absolute Maximum Ratings  ................................................................................................. ........................ 34
4.2  Handling Precauti ons ............................................................ .............. ................... ....... ............................... 34
4. 3  Operat ing Condi tions ... ......................................................... ....................................................................... 34
4.4  Logic Interface Characteristics ........ ....... .......... ....... ....... ....... ....... ..... ....... ....... ....... ....... ............................... 35
4. 5  LVDS Interface  Char a cte r isti cs ..... ...................................................................................... ......................... 36
List o f Fig ur es
Figure 5. Single-Ended Input  Spe cification ....... ............ ................... .............. ................... ....... .............................. 35
List of Ta bles
Table 1 9. Absolute Maximum Ratings ................................................................................................................... 34
Table 20. Handling Precaution  ......................... ............ ....... ................... ....... ................... ....... .............................. 34
Table 21. Recommended Operating Co nditions  ...................... ....... .............. .......... ... ........................................... 34
Table 22. Logi c Interf ace Characteristics............... ..... ... .......................................... ... .......................................... 35
Tabl e  23. L VDS In te r face Chara c te ristic s  ............................................................ ................................................. 36

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

34 Agere Sy stem s Inc.

4 Elect r ic al Char acter isti cs (continued)

4.1 Absolute Maximum Ratings

Stresses in excess of th e absolute maximum ratings ca n caus e permanent da mage to the device. These are abso-

lute str es s r atings only. Func tional op eration of the device is not impli ed at thes e or any other condit ions in excess

of t hose given in the operational sections of the data sheet. Exposure to absolute maximum ratings f o r extended

period s can ad versely affect devic e reliab ilit y.

4.2 Han d lin g Pr ec au t ions

Although protectio n circuitry has been designed into th i s device, proper precautio ns should be taken to avoid expo-

sure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM)

and charged-device model (CDM) for ESD-susceptibility testing and prot e ction design evaluation . ESD voltage

thresholds are dependent on the circuit parameters used in the defined model. No industry -wide standard has

been adopted fo r the C D M. However, a standard HBM (resistance = 1500 Ω, capacitanc e = 100 pF) is widely used

and, therefore, can be used for compari son purposes. The HBM ES D threshold presented here was obtained by

using these circuit para meters :

4.3 Ope r at i ng Co nditio n s

The fo llowing tables list the voltages req uired for proper operation of the TMXF28155 device, along with their toler-

ances.

Table 21. Recommended Operating Condi tions

* Internal reference voltage is used if SMPR_LVDS_REF_SEL = 1 (Table 70); or else exte rna l voltag e is us ed .

Table 19. Absolute Maximum Rati ngs

Parameter Symbol Min Max Unit

dc Supply Voltage Range VDD –0.5 4.6 V

Power Dissipation PD——mW

Storage Temperature Range Tstg –65 125 °C

Ambient Operating Temperature Range TA–40 85 °C

Maxim um Voltage (digital input pins) ——5.25 V

Minimum Voltage (digital input pins) —–0.3 —V

Table 20. Handling Precaution

Device Voltage

TMXF28155 2000 V

Parameter Symbol Min Typ Max Unit

Power VDD 3.14 3.3 3.47 V

Ground VSS —0.0 —V

Input Voltage, Hig h VIH VDD – 1.0 —5.25 V

Input Voltage, Low VIL VSS —1.0 V

1.0 V, LV DS Reference* LVDS _REF10 —1.0 —V

1.4 V:,LV D S Reference* LVDS_REF14 —1.4 —V

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

35Agere Systems Inc.

4 Elect r ic al Char acter isti cs (continued)

4. 4 Log ic Int e r fac e Char ac t e ri stic s

Table 22. Logic Interface Char acteristics

The input specification for the remaining (nonbalanced) inputs are specified in Figure 5.

5-6032(F)r.2

Figure 5. Single-Ended Input Specification

Parameter Symbol Test Cond i tions Min Max Unit

Input Leak age IL——1.0 µA

Output Current:

Low

High IOL

IOH —

——

—2

2mA

Output Volt age:

Low

High VOL

VOH —

—VSS

VDD – 0.5 0.5

5.25 V

Input Capacit ance C I— —1.5 pF

VIL

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

36 Agere Sy stem s Inc.

4 Elect r ic al Char acter isti cs (continued)

4.5 LVDS Interface Characteristics

3.3 V ± 5% VDD, 0—125 °C, sl o w—fast process.

Table 23. LVDS Interface Characteristics

* Buffer will not produce output transition when input is open-circuited.

Parameter Symbol Test Co nd itions Min Typ Max Un it

Input Buffer Parameters

Input Voltage Range, VIA or VIB VI|VGPD| < 925 m V, d c—1 MHz 0.0 1.2 2.4 V

Input Differential Threshold VIDTH |VGPD| < 925 mV, 311 M H z –100 —100 mV

Input Differential Hysteresis V HYST (+VIDTH) – (–VIDTH)———*mV

Receiver Differential Input

Impedance RIN With built-in termination,

center-tapped 80 100 120 Ω

Output Buffer Parameters

Output Volt age:

Low (VOA or VOB)

High (VOA or VOB)VOL

VOH RLOAD = 100 Ω ±1%

RLOAD = 100 Ω ±1% —

0.925 —

—1.475

—V

Output Di fferential Voltage |V OD|R

LOAD = 100 Ω ±1% 0.25 —0.40 V

Output Offset Voltage VOS RLOAD = 100 Ω ±1% 1.125 —1.275 V

Output Impedance, Single Ended ROVCM = 1.0 V and 1.4 V 40 50 60 Ω

RO Mismat ch Between A and B ∆ROVCM = 1.0 V and 1.4 V —— 10 %

Change in Different ial Voltage

Between Complementary

States

|∆VOD|R

LOAD = 100 Ω ±1% —— 25 mV

Change in Output O ffset Voltage

Between Complementary

States

∆VOS RLOAD = 100 Ω ±1% —— 25 mV

Output Current ISA, ISB Driver shorted to VSS —— 24 mA

Output Current ISAB Drivers sh orted together —— 12 mA

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
37Agere Systems Inc.  
5 Timing Character is ti cs
Ta ble of Conte nts
Contents Page
5 Timing Characteristics ........................................................................................................................................ 37
5. 1  TMUX Bl oc k Ti mi ng  ........................ ....................................................................... ...................................... 39
5. 2  DS3 Timing  .................................................................... .............................................................................. 43
5. 3  M13 Timin g  .... .............. ......................................................... .................................... ................................... 44
5. 4  VT M a pper  Timin g   ............................... .................................................... .................................................... 45
5.4.1 V T Mappe r Lower-Order Path Overhead I nterface Timing ............................ . ......................... .......... . 45
5. 5  Conce n tra tion High w a y (CHI ) Tim ing   .... ...................................................................................................... 46
5. 6  Para l lel Syste m Bus Timing  ................. .................................................... .................................................... 47
5.7  NSMI Timing Mode 1  .......................................... ................................. ............ ............................................ 49
5.8  SMI Timing M ode 2 (8 pin) .. .......................... ............................................................................................... 49
5. 9  Fra me r On l y  Mode Timin g   .......................................................................... ................................................. 51
5.10  Fram er—LIU Mode Timing  ........................................................................................................................ 53
5.1 1  Microprocessor Interface Timin g ................................................................................................................ 54
5.11.1 Synchronous Mode  .... .. ............ .............. ....... ............ ....... ................. ......... ....... ............ ................... 54
5.12  Asynchronous Mode .................................................................................................................................. 56
5.1 3  General Purpose Interface Timing ............................................................................................................. 60
6 Ordering Information............................................................................................................................................ 61
Figures Page
Fig ure 6. Generic Clock Timing.............................................................................................................................. 39
Fig ure 7. Generic Interface Data Timing ................................................................................................................ 41
Fig ure 8. VT Mapper Transmit Path Overhe ad Detailed Timing ............................................................................ 45
Figure 9 . VT Mapper Rec eive Path O v erhead Det aile d Timing ............................... .......................... ... ................. 45
Figure 10. CHI Transmit I/O Timing........................................................................................................................ 46
Fi gure  11.  CHI Receiv e I/ O Timi n g......................................................................................................................... 47
Fi gure  12. Pa r a l lel Syste m Bus Inte r fa ce  Tra n smi t I/O Timing....................................... ............................ ............ 48
Figure 13. Parallel System Bus  Interface Receive I/O Timing................................................................................ 48
Figure 14. Microprocessor Interface Synchronous Wri te Cycle (MPMODE (Pin AD17) = 1) .................................54
Figure 15. Microprocesso r Interface Synchronous  Read Cycle (MPMODE (Pin AD17) = 1).................................55
Figure 1 6. Microprocessor Interface Asynchrono us Write Cycle Description (M PMODE (Pin AC18) = 0) .. ..........57
Figure 17. Micro processo r Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0) ...............................59
Tables Page
Table 2 4. High-speed Input Clock Specifications .................................................................................................. 39
Table 2 5. Output Clock Specifications ................................................................................................................... 40
Table 26. I nput Timing Specifications  . ....... ....... ....................................................................... ..............................41
Table 27. Output Timing Specifications ................................................................................................................. 42
Table 2 8. DS3 Input Clock Specifications  .............................................................................................................43
Table 29. I nput Timing Specifications  . ....... ....... ....................................................................... ..............................43
Table 30. Output Timing Specifications ................................................................................................................. 43
Table 3 1. M 13 Clock Specifications  ...................................................................................................................... 44
Table 32. I nput Timing Specifications  . ....... ....... ....................................................................... ..............................44
Table 33. Output Timing Specifications ................................................................................................................. 44
Table 34. VT Mapper Receive Path Overhead Detailed Timing ...... ....... ..... ... .............................. ....... . ................. 45
Tabl e  35. CHI Transm it Timi ng Characteristics .. ................................................................................................... 46
Table 3 6. CHI Receive T iming Characteristics ......................................................................................................47
Table 3 7. PSB Interface Transmit Ti ming Characteristics ..................................................................................... 47

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
38 Agere Sy stem s Inc.
 
5 Timing Char act er istics (continued)
Table of Conten ts (continued)
Tables Page
Table 3 8. PSB Interface R eceive Timing Characteristics ...................................................................................... 48
Table 3 9. NSMI (Mode 1) Input Clock  Specif ications ............................................................................................ 49
Table 40. Input Tim ing Sp ec ifications  ... ................................... ... ................................ . .......................................... 49
Table 41. Output Timing Specifications ................................................................................................................. 49
Tabl e  42. SMI ( Mo d e 2) Inpu t Clock Specific at ions .... ................... ........................................................................ 49
Table 43. Input Tim ing Sp ec ifications  ... ................................... ... ................................ . .......................................... 50
Table 44. Output Timing Specifications ................................................................................................................. 50
Table 45. Framer Only Mode Clock S pec if icat ions  . ......................... .......... ... ......................... . .............................. 51
Table 46. Framer Mode Only Input Timing Specifications ..................................................................................... 52
Table 47. Framer Mode Only Output Timing Specifications .................................................................................. 52
Table 48. Framer—LIU M ode Clock Sp ecifications  . ................ ...................... .................. . ............. . ................... .... 53
Table 49. Framer—LIU M ode Input Timing Specifications .. .............................. ... ......................... ....... . ................ 54
Table 50. Framer—LIU M ode Output Timing Specifications ............ . ..................................... ....... . ....................... 54
Table 51. M icroproc es sor Interface Synchro nous   Write Cycle Specifications   ..................... ... ......................... . ....55
Table 52. M icroproc es s or Interface Synchronous   Read Cycle Specifications ............................ ... ....................... 56
Table 5 3. M icroprocessor Interface Asynchronous Write Cycle Sp ecifi cations .....................................................58
Table 5 4. M icroprocessor Interface Asynchronous Read Cycle Specifications .................................................... 60
Table 55. Input Tim ing Sp ec ifications  ... ................................... ... ................................ . .......................................... 60
Table 56. Output Timing Specifications ................................................................................................................. 61

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

39Agere Systems Inc.

5 Timing Character is ti cs (continued)

5.1 TM U X Bl ock Timin g

The TMUX (STS-N/STM-1) timing parameters can be grouped separately for clocks, inputs, and outputs. Table 24

sho ws the input clock specifications for this d evice. The rise and fall times refer to the transition times fr om 1 0 % to

90% of f ull sw i ng.

For defi n itions of the signal nam es, see the pin descriptions secti on at the beginni ng o f this data sheet.

Table 24. High-speed Input Clock Specifications

Not e: When the true an d comp le m ent inp ut s a re f lo at ing, the input buffer wil l not oscillate.

5-9077(F)

Figure 6. Gen e ric Clock Timing

Symbol Parameter Signal Nam e 155 Clock 51 Clock Unit

Min Nom Max Min Nom Max

fCK Operating

Frequency THSCP/N —155.52 ±30 ppm —— 51.84 ±50 ppm —MHz

RHSCP/N —155.52 ±30 ppm —— 51.84 ±50 ppm —MHz

RPSC155P/N —155.52 ±30 ppm —MHz

tCK Clock

Period THSCP/N —6.43 ±0.4% —— 19.29 ±0.4% —ns

RHSCP/N —6.43 ±0.5% —— 19.29 ±0.5% —ns

RPSC155P/N —6.43 ±0.5% —— ns

tCLKHI Clock

Pulse High

Time

THSCP/N 2.5 —3.9 7.8 —11.6 ns

RHSCP/N 2.5 —3.9 7.8 —11.6 ns

RPSC155P/N 2.5 —3.9 —ns

tR Ris e Tim e THSCP/N ——1.5 ——5.0 ns

RHSCP/N ——1.5 ——5.0 ns

RPSC155P/N ——1.5 —ns

tF Fall Time THSCP/N ——1.5 ——5.0 ns

RHSCP/N ——1.5 ——5.0 ns

RPSC155P/N ——1.5 —ns

tCLKHI

tCK

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

40 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

The output cl ock specifications are shown in Table 25, where the symbols match the waveform diagram above.

Table 25. Output Clock Specifications

* The specificatio ns for the table are with al l l oopbacks disabled.

Note: Any of the telecom signals being us ed as inputs (slave Super Ma pper) need to meet these same output

clock specificatio ns.

Signal Name Refer ence CLK*Frequency Clock Pulse High

Time (tCLKHI) Test

Condition Max Rise

Time (tR) Max Fall

Time (tF)

TLSCLK TH SCP/N 19.44 MHz 24.43—27.00 n s C L = 50 pF 3.5 ns 3.5 ns

TTOACCLK T HSCP/N 5.184 M H z 91.62—101. 3 n s C L = 15 pF 3.5 ns 3.5 ns

RLSCLK RHS CP/N or

Internal CDR Clock 19.44 MH z 24.43—27.00 ns CL = 50 pF 3.5 ns 3. 5 ns

RTOACCLK RHSCP/N or

Internal CDR Clock 5.184 MH z 91.62—101.3 ns CL = 15 pF 3.5 ns 3. 5 ns

TPSC155P /N THSCP/N 15 5.5 MH z 3.119—3.31 1 n s C L = 15 pF 1.5 ns 1.5 ns

TP OACCLK THSCP/N 5.184 MHz 91.62—101. 3 n s C L = 15 pF 3.5 ns 3.5 ns

RPOACCLK RHSCP /N 5.184 MHz 91.62—101. 3 ns CL = 15 pF 3.5 n s 3.5 ns

TLS C 52 T H SCP/N 51.84 MHz 9.162—10.13 n s C L = 30 pF 3.0 ns 3.0 ns

RLSC52 RHSCP/N 51.84 MHz 9.162—10.13 n s C L = 30 pF 3.0 ns 3.0 ns

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

41Agere Systems Inc.

5 Timing Character is ti cs (continued)

Tabl e 26 . In put Timing Specificat ions

Figure 7. Generic Interface Data Timi ng

Input Name Reference CLK Min S etup Time (tS) Min Hold Time (tH)

Transmit S igna ls

THSSYNC THSC ↑2. 0 ns 0.0 ns

TLSDATA[7:0] TLSCLK ↑5.0 ns 0.0 ns

TLSPAR TLSCLK ↑5.0 ns 0.0 ns

TLSSPE TLSCL K ↑5.0 ns 0.0 n s

TLSJ0J1V1 TLSCLK ↑5.0 ns 0.0 ns

TLSV1 TLSCLK ↑5.0 ns 0.0 ns

TLSSYNC52 TLS C52 ↑4.0 ns 0.0 ns

TTOACDATA TTOACCLK ↑1 0.0 ns 0.0 ns

TPOACDATA TPOACCLK ↑10.0 ns 0.0 ns

Receive Signals

RHSDP/N RHSCP/N ↑↓ 2.0 ns 0.0 n s

RPSD155P/N RPSC155P/N 2.0 ns 0.0 ns

RLSDATA[7:0] RLSCLK ↑5.0 ns 0.0 ns

RLSPAR RLSCLK ↑5.0 ns 0.0 n s

RLSSPE RLSCLK ↑5.0 ns 0.0 ns

RLSJ0J1V1 RLSCLK ↑5.0 ns 0.0 ns

RLSV1 RLSCLK ↑5.0 ns 0.0 n s

R LSSYNC52 RLSC52 ↑4.0 ns 0.0 ns

Miscellaneous Signals

LOSEXT NA ASYNC ASYNC

AUTO_AIS[3:1] NA ASYNC ASYNC

CLOCK

DATA

CLOCK

DATA

tSU tH

tPD

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

42 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

Tabl e 27. Output Timi ng Specifications

* Propagation delay skew, tPLH – tPHL, is ±200 ps.

Output Name Reference CL K Te st

Conditions Pr opagation Delay* Unit

tPD

Min Max

Transmi t Signals

THSDP/N T HSCP/N ↑CL = 15 pF 0.6 2.9 ns

TPSD155P/N TPSC155P/N CL = 15 pF 0.6 2.9 ns

TLSDATA[7:0] TLSCLK ↑CL = 50 pF 4.0 12.0 ns

TLSPAR TLSCLK ↑CL = 50 pF 4.0 12.0 ns

TLSSPE TLSCLK ↑CL = 50 pF 4.0 12.0 ns

TLSJ0J1V1 TLSCLK ↑CL = 50 pF 4.0 12.0 ns

TLSV1 TLSCLK ↑CL = 50 pF 4.0 12.0 ns

TLSSYNC52 T LSC52 ↑CL = 30 pF 0.0 6.0 ns

TTOACSYNC TTOACCLK ↑↓ CL = 15 pF 10.0 30.0 ns

TPOACS YNC TPOACCLK ↑↓ CL = 15 pF 10.0 30.0 ns

Receive Signals

RLSDATA[7:0] RLSCLK ↑CL = 50 pF 4.0 12.0 ns

RLSPAR RLSCLK ↑CL = 50 pF 4.0 12.0 ns

RLSSPE RLSCLK ↑CL = 50 pF 4.0 12.0 ns

RLSJO J1V1 RLSCLK ↑CL = 50 pF 4.0 12.0 ns

RLSVI RLSCLK ↑CL = 50 pF 4.0 12.0 ns

RLSSYNC52 RLSC52 ↑CL = 30 pF 0.0 6.0 ns

RTOACSYNC RTOACCLK ↑↓ CL = 15 pF 10.0 30.0 ns

RTOACDATA RTOACCLK ↑↓ CL = 15 pF 10.0 30.0 ns

RPOACSYNC RPOAC CLK ↑↓ CL = 15 pF 1 0.0 30.0 ns

RPOACDATA RPOACCLK ↑↓ CL = 15 pF 10.0 30.0 ns

RH SFSYNCN RLSCLK ↓CL = 30 pF 0.0 8.0 ns

Miscellaneous Signals

AUTO_AIS[3:1] NA —ASYNC ASYNC —

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

43Agere Systems Inc.

5 Timing Character is ti cs (continued)

5.2 DS3 Timi n g

Table 28. DS3 Input Clock Specifications

Tabl e 29 . In put Timing Specificat ions

Tabl e 30. Output Timi ng Specifications

Symbol Pa r ameter Signal Na me Mi n Max Unit

fCK Clock Frequ enc y DS3DATAINCLK

DS3DATAOUTCLK —

—44.736 MHz ±50 pp m —

tCK Clock Period DS3DATAINCLK

DS3DATAOUTCLK —

—22.353

22.353 ns

tCLKHI Clock Pul se High Time DS 3DATAINCLK

DS3DATAOUTCLK 6

616

16 ns

tRRise Time DS3DATAINCLK

DS3DATAOUTCLK 02ns

tFFall T ime DS3DATAINCLK

DS3DATAOUTCLK 02ns

Input Name Reference CLK Min Setup Time (tS) Min Hold Time (tH)

D S3POSDATA IN DS3DATAINCLK ↑↓ 40

DS3NEG DATA IN DS3DATAINCLK ↑↓ 40

Outp ut Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

DS3POSDATAOUT DS3DA TAOUTCLK ↑↓ CL = 15 pF 2 6 ns

DS3NEGD ATAOUT DS3DATAOUTCLK ↑↓ CL = 15 pF 2 6 ns

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

44 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

5. 3 M13 T im i ng

Table 31. M13 Cl ock Speci fication s

Tabl e 32 . In put Timing Specificat ions

Tabl e 33. Output Timi ng Specifications

Symbol Parameter Signal Name Min Nom Max Unit

fCK Clock

Frequency TCBCLK

TDLCLK

E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

—

2.048

1.544

—

93.983 gapped

28.195 gapped

32.768

24.704

6.312

93.983

28.195

—

65.536

49.408

—

kHz

MHz

kHz

tCLKHI Clock Pulse

High Time TCBCLK

TDLCLK

RCBCLK

RDLCLK

212.19

223.53

250.77

tRRise Tim e TCBC LK

TDLCLK

E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

—

tFFall Time TCBCLK

TDLCLK

E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

—

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

Min Max Min Max

TCBDATA T CB CLK ↑50 —0—ns

TDLDATA TDLCLK ↑50 —0—ns

O ut put N a me Refere nc e C LK Test C onditions Prop ag a t ion Del ay tPD Unit

Min Max

TCBSYNC TCBCLK ↑CL = 15 pF 2 10 ns

RCBSYNC RCBCLK ↑CL = 15 pF 2 10 ns

RCBDATA RCBCLK ↑CL = 15 pF 2 10 ns

RDLDATA RDLCLK ↑CL = 15 pF 2 10 ns

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

45Agere Systems Inc.

5 Timing Character is ti cs (continued)

5.4 VT M a pper Ti min g

5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing

Table 34. VT Mapper Receive Path Overhead Detailed Timing

5-9078(F)

Figure 8. VT Mapper Transmit Path Overhead Detailed Timing

5-9079(F)

Figure 9. VT Mapper Receive Path Overhead Detailed Timing

Symbol Parameter Min Max Unit

fCK Clock Frequ enc y 6.48 6.48 M Hz

tCK Clock Per iod 154 154 ns

tCLKHI Clock Pulse High Time 50 75 ns

tRClock Rise Time 0 3 ns

tFClock Fall Time 0 3 ns

tSD LOPOH Data Se tup Time 5 —ns

tHD LOPOH Data Hold Time 0 —ns

tSV LOPOH Valid Signal Setup Time 5 —ns

tHV LOPOH Valid Signal Hold Time 0 —ns

tPDV Clock to LO POH Valid Signal Out 0 5 ns

tPDD Clock to LOPOH Da ta Out 0 5 ns

LOPOHCLKIN

LOPOHVALIDIN

LOPOHDATAIN

tPDV

tPDD

LOPOHCLKOUT

LOPOHVALIDOUT

LOPOHDATAOUT

tCK

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

46 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

5.5 Co nc entra tion Highway (CH I) Timing

Table 35 and Table 36 with Figure 10 and Figure 11, respectively, illustrate the detailed CHI timing for clock, da ta,

and frame synchronization.

Table 35. CHI Transmit Timing Characteristics

CK can be either 2.048 M H z , 4.096 MHz, 8.192 MHz, or 16.384 MHz.

5-9080(F)

Figure 10. CHI Transmit I/O Timing

Symbol Parameter Min Max Unit

fCK C lock Frequency* 2.048 16.3 84 MHz

tCK C lock Per iod 488.2 61.04 n s

tRClock Rise Time 0 3 ns

tFC lo ck Fall Time 0 3 n s

tSFrame Sy nc Setup Tim e 35 —ns

tHFrame Sy nc Hold Tim e 0 —ns

tPD C lock to CHI Data Delay —25 ns

LINETXCLK29

LINETXSYNC29

LINETXSYNC[28:1]

CLOCK

FRAME SYNC

DATA

tCK

tPD

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

47Agere Systems Inc.

5 Timing Character is ti cs (continued)

Table 36. CHI Receive Ti ming Characteristics

*fCK can be either 2.048 M H z , 4.096 MHz, 8.192 MHz, or 16.384 MHz.

5-9081(F)

Figure 11. CHI Receive I/O Timin g

5.6 Pa r al le l Sy ste m Bus T im in g

Table 37 and Table 38 with Figure 12 and Figure 13, respec tively, show the transmit an d recei ve tim ing. In the

transmit direct ion (to the system interf ace) the frame sync is sampled and the data is clo cked out on the rising edge

of the clock. In the receive direction (from the switch) the data and frame sync are sampled on the rising edge of

th e clock.

Table 37. PSB Interface Transmit Timing Characterist ics

Symbol Parameter Min Max Unit

fCK Clock Frequ ency * 2.048 16.384 MHz

tCK Clock Period 488.2 61.04 ns

tRClock Rise Time 0 3 ns

tFClock Fall Time 0 3 ns

tSSYNC Frame S y nc Setup Time 30 —ns

tHSYNC Frame Sync Hold Time 0 —ns

tSDATA CHI Dat a Se tup Time 25 —ns

tHDATA CHI Data Hold Time 0 —ns

Symbol Parameter Min Max Unit

fCK Clock Frequency 19.44 19.44 MHz

tCK Clock Period 51.44 51.44 ns

tRClock Ri se T ime 0 3 ns

tFClock Fall Time 0 3 ns

tSFrame Sync Setup Time 8 —ns

tHFrame Sync Hold Ti me 0 —ns

tPD Clock to PSB Out De lay 3 10 ns

tHDATA

LINERXCLK29

LINERXSYNC29

LINERXSYNC[28:1]

CLOCK

F RAME SYNC

DATA

tSSYNC tHSYNC

tSDATA

tCK

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

48 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

5-9082(F)

Figure 1 2. Para llel System Bus I nterface Transmit I/O Timin g

Table 38. PSB Interface Receive Timing Characteristics

5-9083(F)

Figure 13. Parallel System Bus Interface Recei ve I/O Timing

Symbol Parameter Min Max Unit

fCK C lock Frequency 19.44 19.44 MH z

tCK C lock Per iod 51.44 51.44 ns

tRC lock Rise Time 0 3 ns

tFC lock Fall Time 0 3 ns

tSSYNC Frame Sync Setup Time 8 —ns

tHSYNC Frame Sync Hold Time 0 —ns

tSDATA PSB to Clock Setup Time 8 —ns

tHDATA PSB Hold Time from Clock 0 —ns

DEV #0, TS #1, DEV #0, TS #1,

tPD

STUFFED TS STUFFED TS

6 (3) STUFFED TS IN DS1 (E1)

tHtS

LINETXCLK29

LINETXSYNC29

LINETXSYNC[16:1]

CLOCK

FRAM E SYNC

DATA LINK #0 LINK #1

tCK

DATA SAM P LED

tSDATA tHDATA

DEV #0, TS #1, DEV #0, TS #1,

STUFFED TS STUFFED TS

tHSYNCtSSYNC

LINERXCLK29

LINERXSYNC29

LINERXSYNC[16:1]

CLOCK

FRAME SYNC

DATA LINK #0 LINK #1

tCK

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

49Agere Systems Inc.

5 Timing Character is ti cs (continued)

5.7 NSM I T im ing M ode 1 (6 P i n)

Tabl e 39. NSMI (Mode 1) Input Clock Spec ific ations

Tabl e 40 . In put Timing Specificat ions

Tabl e 41. Output Timi ng Specifications

5. 8 SMI T imi n g Mo d e 2 (8 Pi n)

Tabl e 42. SMI ( Mode 2) Input Clock Sp eci fications

Symbol Parameter Signal Nam e Min Nom Max Un it

tCK Clock

Frequency LINE_TXCLK29

LINE_RXCLK29 —

—51.84/44.73 6 ±50 ppm

51.84/44.73 6 ±50 ppm —

—MHz

MHz

tCKHI Clock Pu lse

High Time LINE_TXCLK29

LINE_RXCLK29 6

6—

—12

12 ns

tRRise Time LINE_TXCLK29

LINE_RXCLK29 —

——

—3

3ns

tFFall Time LINE_TXCLK29

LINE_RXCLK29 —

——

—3

3ns

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

Min Max Min Max

LINE_ R XDATA29 LINE_R XCL K2 9 ↓5—0—ns

LINE_RXSYNC29 LINE_RXCLK29 ↓5—0—ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINE_TXDATA29 L INE_TXCLK29 ↑CL = 15 pF 0 3 .5 ns

LINE_T XSYNC29 LINE_TXCLK29 ↑CL = 15 pF 0 3.5 ns

RXDATAEN LINE_TXCLK29 ↑CL = 15 pF 0 3.5 ns

TXDATAEN LINE_TXCLK29 ↑CL = 15 pF 0 3.5 ns

Symbol Parameter Signal Name Min Nom Max Unit

tCK Clock

Period LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

44.736 MHz ±50 ppm

TBD

19.29

TBD

tCKHI Cl ock Pu lse

High Time LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

TBD

1/3 tck

1/3 or 1/2 tck

TBD

tRRise Time LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

—

tFFall Time LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

—

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

50 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

Tabl e 43 . In put Timing Specificat ions

Tabl e 44. Output Timi ng Specifications

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

Min Max Min Max

LINE_ R XDATA29 LINE_R XCL K2 9 ↓5—0—ns

LINE_RXSYNC29 LINE_RXCLK29 ↓5—0—ns

Output Name Reference CLK Test Conditions Propagation De lay tPD Unit

Min Max

LINE_TXDATA29 LINE_TXCLK29 ↑CL = TBD pF 0 3.5 ns

LINE_TXSYNC29 LINE _TXCLK 29 ↑CL = TBD pF 0 3.5 ns

TXDATAEN RXDATAEN ↑CL = TBD pF 0 3.5 ns

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

51Agere Systems Inc.

5 Timing Character is ti cs (continued)

5. 9 Fram e r O nly Mod e Timing

Table 4 5. Framer Only Mode Clock Specifications

Symbol Pa r a met er Signal Na me Min Nom Max Unit

tCK Clock

Frequency TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

–50 ppm

–130 ppm

–50 ppm

–130 ppm

–50 ppm

–130 ppm

–50 ppm

51.84

1.544

or 2.048

1.544

2.048

or 4.096

or 8.192

or 16.384

1.544

or 2.048

or 4.096

or 8.192

or 16.384

50 ppm

130 ppm

50 ppm

130 ppm

50 ppm

130 ppm

50 ppm

MHz

tCKHI Clock Pulse

H igh Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

TBD

tRRise Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

—

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

52 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

Table 45. Framer Only Mode Clock Specifications (continued)

Tabl e 46. Frame r Mode Only Input Ti ming S pe c ificatio ns

Table 47. Framer Mode Only Output Tim in g Specification s

Symbol P a ramete r Sign al Na me Min Nom Max Uni t

tFFall Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

—

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA[28:1] LINERXCLK[28: 1] ↑25 —0—ns

LINERXSYNC[28:1 ] LINERXCLK[ 28: 1] ↑30 —0—ns

LINERXSY NC29 LINERXCLK29 ↑30 —0—ns

LINETXS YNC 29 LINETXCLK 29 ↑35 —0—ns

Outp ut Name Reference CLK Test Con ditions Propagation Delay tPD Unit

Min Max

LINET XDATA[28:1] LINETXCLK[28:1] ↑CL = TBD pF 2 5 TBD ns

LINETXDATA29 LINE TXCLK29 ↑CL = TBD pF 25 TBD ns

LINETXS Y NC[2 8:1] LINETXCLK[28:1] ↑CL = TBD pF TBD TBD ns

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

53Agere Systems Inc.

5 Timing Character is ti cs (continued)

5.10 Framer — L IU Mo d e T im in g

Table 48. Framer—LIU Mode Clock S pecifica tions

Symbol Parameter Signal Name Min Nom Max Unit

tCK Clock

Frequency TLSC52

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

TBD

51.84

TBD

2.048

or 4.096

or 8.192

or 16.384

TBD

or 2.048

or 4.096

or 8.192

or 16.384

TBD

MHz

TBD

MHz

TBD

MHz

tCKHI Clock Pulse

H igh Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

TBD

tRRise Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

—

tFFall Time TLSC52

LINERXDATA29

LINERXCLK[28:1]

LINERXCLK29

LINETXCLK[28:1]

LINETXCLK29

—

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

54 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

Tabl e 49. Frame r —LI U Mode In put Timing Specific a tions

Table 50. Framer—LIU M od e Output Timing Specifications

5.11 Microprocessor Interface Timing

5.11.1 Synchronous Mode

The synchronous microprocessor interface m ode is selected whe n MPMODE (pin AD17) = 1. Interface timing for

the synchronous mode write cycle is given in Figure 14 and in Table 51 and for the read cycle in Figure 15 and in

Table 52.

Note: In addition to the MP U_CLK, the VT mapper block also requires TLSC 52,TLSSYNC52, RLSC52,

RLSSYNC52 signals to access specific portions of the register map. T he user needs to make sure that the

VT_RDY bit is set be fore VT_MAPPER reads/writes can o ccur.

5-7659(F)a

Figure 14. Microprocessor Inte rface Synchronous W rite Cycle (MPMODE (Pin AD17) = 1)

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA[28:1] LINERXCLK[28:1] ↑↓TBD 35 35 —ns

LINERXDATA29 LINERX CLK 29 ↑↓TBD 35 35 —ns

LINERXSYNC[28:1] LINERXCLK[28:1] ↑↓TBD 35 35 —ns

LIN ERXSYNC29 LINERXCLK29 ↑↓TBD 35 35 —ns

Output Name Reference CLK Test Con ditions Propagation Delay tPD Unit

Min Max

LINETXDATA[28:1] LINETXCLK[28:1] ↑↓CL = TBD pF –35 35 ns

LINETXDATA29 LINETXCLK29 ↑↓CL = TBD pF –35 35 ns

LINETXS Y NC[2 8:1] LINETXCLK[28:1] ↑↓CL = TB D pF –35 35 ns

LINETXSYNC29 LINETXCLK29 ↑↓CL = TBD pF –35 35 ns

MPCLK

ADDR[9:0]

CSN

ADSN

RWN

DATA[15:0]

DTN

(66 M Hz MA X )

(INPUT)

tADSNVS

tWS

tDTNVPD

tWS

tCSNVS

tWS

tCLK T1 T2 T3 Tn – 2 Tn – 1Tn

tAIPD

tAPD

tDTNIPD

HIGH ZHIGH Z tADSNVDTF

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

55Agere Systems Inc.

5 Timing Character is ti cs (continued)

MPCLK 16 MHz minimum to 66 MHz maximum frequency.

ADDR [19:0] The address wil l be available throughout the entire cycle.

DATA [15:0] Data will be avail a ble during cycle T1.

RWN (Input) The rea d ( H ) w r ite (L) sig nal is always high except during a write cycle.

CSN (Input) Chip select i s an active-l ow signal.

DTN (Output) Data transfer acknowledge is active-low for o ne clock and then driven high before entering a high-

imped ance st ate. (This i s done wit h an I /O pad usi ng the input as feedback to qualify the 3-state

term.) D TN will become 3-stated when CSN is high. Typically DT N is active 4 or 5 MPCLK cycles

after ADSN is low.

AD SN (Inpu t ) A d d r ess s t r obe is active -low . ADSN must be 1 MPCLK clock period wide.

Table 5 1. Microprocessor Interface Syn chronous Write Cycle Sp ecificati ons

(See Figure 14 on page 54 for the tim ing diagram.)

5-7660(F).a

Figure 15. Mi croprocessor Interface Synchronous Read Cycl e (MP MODE (Pin AD17) = 1 )

Sym bol Parame te r Set up ( ns)

(Min) Hold (n s)

(Min) Delay (ns)

(Max) Delay (ns)

(Min)

TCLK MPCLK 1 6 MHz Min—66 M H z M ax Frequency ————

tWS ADDR, RWN, DATA (write) Valid to M P CLK 3.5 0 ——

tAPD MPCLK to ADDR, RWN, DATA, CSN (write) Invalid —5——

tCSNVS CSN Valid to MPCLK 3.5 0 ——

tADSNVS ADSN Valid to MPCLK 5.5 0 ——

tAIPD MPCLK to ADSN Invali d —5——

tDTNVPD MPCLK to DTN Valid ——16 4

tDTNIPD MPCLK to DTN Invalid ——16 4

TADSNVDTF AD SN Valid to D T Fallin g ——1000 —

MPCLK

ADDR[9:0]

CSN

ADSN

RWN

(66 MHz MAX)

tADSNSU tSNIPD

tCSNSU

tAVS

T0 T1 T2 Tn – 4Tn – 3Tn – 2Tn – 1 Tn

DTN

DATA[15:0]

(OUTPUT)

tDAIPD

tDVPD tDIPD

tADSNVDTF HIGH Z

HIGH Z

tAPD

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

56 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

MPCLK 16 MHz minimum to 66 MHz maximum frequency.

ADDR [19:0] The address will be available throughout the entire cycle , and must be stable before ADSN turns

high.

DATA [15:0] Read da ta is stable in Tn –1.

RWN (Input) The rea d (H) write (L) signal is always high during the read cycle.

CSN (Input) Chip select i s an active-l ow signal.

DTN (Output) Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one

clock and then driven hig h b efore entering a high-impedance st ate. (This is done w ith an I/O pad

using the input as feedback to qualify the 3-state term.) DT will bec ome 3-s tated when CS is high.

Typically DTN is active 4 or 5 MPCLK cycles after ADSN is low.

AD SN ( Input ) Ad dr e s s st r obe is ac tive -low . ADSN must b e on e MP C LK clock period wide.

Table 52. Microprocessor Interface Syn chronous Read Cycle Specifications

(See Figure 15 on page 55 for the tim ing diagram.)

5.12 Asyn chronous Mode

The asynchronous microprocessor interface mode is selected when MPMODE (pin AC18) = 0. I n terface timing for

the asynchronous mode write cycle is given in Figure 16 and in Table 53, and for the read cycle in Figure 17 and in

Table 54 (see pages 59—60).

Symbol Parameter Setup (ns)

(Min) Hold (ns)

(Min) Delay (ns)

(Max)

tCLK MP C LK 16 MH z Min—66 MH z Max Frequency ———

tAVS ADDR Valid to MPCLK 3.5 0 —

tAPD MPCLK to ADDR Inva lid —5—

tCSNSU CSN Active to MPCLK 3.5 0 —

tADSNSU ADSN Valid to MPCLK 5.5 0 —

tSNIPD MPCLK to ADSN Inactive —5—

tDVPD MPCLK to DTN Valid —— 8

tDIPD MPCLK to DT N Invalid —— 8

tDAIPD MPCLK to DATA 3-state —— 8

tADSNVDTF AD SN Valid to DT Falling ——1000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

57Agere Systems Inc.

5 Timing Character is ti cs (continued)

5-7661(F).ar.1

Figure 16. Micr o processor Interface Asynchronous Write Cycle Description (MPMODE (Pi n AC18) = 0)

ADDR [19:0] Address is asynchronou sly passed from the host bus to the internal bus. The address will be avail-

able throug hout the entire cycle.

DATA [15:0] Write data is async hronous ly pas s ed from the hos t bus to the internal bus. Data will be available

throughout the entire cycle.

RWN (Input) The rea d ( H ) w r ite (L) sig nal is always high except during a write cycle.

CSN (Input) Chip select i s an active-l ow signal.

DTN (Output)Data transfer acknowl edge (ac tive-low). DTN is driven asynchronously based on the arrival of CSN.

DTN is driven high until the internal transaction is d one. DTN is driven high again when eithe r ADSN

or DSN is deasserted. DTN will become 3-stated when CSN is high.

AD SN ( Input ) Ad dr e s s st r obe is ac tive -low . ADSN must be a minimum of one MPCLK clock period wide.

DSN (Input ) Data strobe is active-low.

ADDR[19:0]

CSN

ADSN

DSN

RWN

DATA[15:0]

DTN

(INPUT)

tAVADSF

tDVDSF

tCSFDTR tDSFDTF

tADSRDTR tCSRDT3

tDSRDI

tDSRRWR

tDSNRAI

tADSRAI

tAICSR

tRWFDSF

tAVDSF

HIGH Z HIGH Z

tCSFDSF

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

58 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

Table 5 3. Microprocessor Interface Asynchronous Write Cycle Specifications

(See Figure 16 on page 57 for the timing di agram.)

* Simulation results.

† Falling edge s of ADSN a nd DSN dete r mine falling edge of DTN.

‡ DTN fall is variable, depending on the block selected for access, and may be longer than the typical maxi mum sp ecifi ed .

§ Rising edge of ADSN deter mines r ising edge of DTN.

Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select

(CSN) may be connect ed and driv en from the same sourc e. In thi s configuration, the setup and hold times

for ADSN must be satisfied.

Symbol Parameter Min Interval (ns) Max Interval (ns)

tCSFDSF CSN Fall to DSN Fall 0 —

tAICSR ADDR Invalid to CS N Rise 0 —

tAVADSF ADDR Valid to AD SN Fall 0 —

tADSRAI ADSN Rise to ADDR Invalid 0 —

tAVDSF ADDR Valid to DSN Fall 0 —

tDSNRAI DSN Rise to ADDR Invalid 0 —

tRWFDSF RWN Fall to DSN Fall 0* —

tDSRRWR DSN Rise to RWN Rise 0* —

tDVDSF DATA Valid to DSN Fall 0* —

tDSRDI DSN Rise to DATA Invalid 0* —

tCSFDTR CSN Fall to DTN Rise 20 —

tDSFDTF DSN Fall to DTN Fall 120 280†‡

tADSRDTR ADSN Rise to DTN Rise 20§—

tCSRDT3 CSN Rise to DTN 3-state 10 —

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

59Agere Systems Inc.

5 Timing Character is ti cs (continued)

5-7662(F).ar.1

Figure 17. Microprocessor Interface Asynchr onous Read Cycle (MPMODE (Pi n A C18) = 0)

ADDR [19:0] Address is asynchronou sly passed from the host bus to the internal bus. The address will be avail-

able throug hout the entire cycle.

D ATA [15:0] Read data on the internal b us is only vali d f or one clock cycle; therefore, a latch is necessary to meet

the correct timing on t he host bus.

RWN (Input) The rea d (H) write (L) signal is always high during a read cycle.

CSN (Input) Chip select i s an active-l ow signal.

DTN (Output)Data transfer acknowl edge (ac tive-low). DTN is driven asynchronously based on the arrival of CSN,

DSN, and ADSN. DTN is driven high while the internal bus transaction is in progress. There is no

need to pro vide synchronization to outgoing signals in this mode. DTN is driv en high and then placed

in a high-impedance state when either ADSN or DSN is deasserted. DTN will become 3-stated when

CSN is high.

AD SN ( Input ) Ad dr e s s st r obe is ac tive -low .

DSN (Input ) Data strobe is active-low.

ADDR[19:0]

CSN

ADSN

DSN

DTN

DATA[15:0]

tADSRD3

tCSRDT3

tADSRDTR

tCSFDSF

RWN

tAVADSF

tAVDSF

tAICSR

tADSRAI

tDSNRAI

tDTVDV

tDSFDTF

tCSFDTR

HIGH Z

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

60 Agere Sy stem s Inc.

5 Timing Char act er istics (continued)

Table 54. Microprocessor Interface Asynchronous Read Cycl e Speci fications

(See Figure 17 on page 59 for the tim ing diagram.)

Notes:

1 DSN can be asserted up to 20 ns (1 clk at 50 MHz) previous to CSN.

2 ADDR can b e a sse r ted up t o 60 n s (3 c lk at 5 0 MHz) into c ycle fr om A S DN.

3 DTN fall is variable depending on the block selected for access and may be longer than typical maximum specified.

4 Le ad ing edg es o f A D SN a nd DS N det erm ine the fallin g ed ge of D TN .

5 Rising edge of ADSN determines t he rising edge of DTN.

6 Data toggle 20 ns (1 clk at 50 MHz) previous to CS N.

Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select

(CSN) may be connect ed and driv en from the same sourc e. In thi s configuration, the setup and hold times

for ADSN must be satisfied.

5.13 General Purpose Interface Timing

Tabl e 55 . In put Timing Specificat ions

Symbol Para meter Min Interval (ns) Max Interval (ns)

tCSFDSF CSN Fall to DSN Fall 01—

tAICSR ADDR Invalid to CS N Rise 0 —

tAVADSF ADDR Valid to ADSN Fall 0 602

tADSRAI ADSN Rise to ADDR Invalid 0 —

tAVDSF ADDR Valid to DSN Fall 0 —

tDSNRAI DSN Rise to ADDR Invalid 0 —

tCSFDTR CSN Fall to DTN Rise 20 —

tDSFDTF DSN Fall to DTN Fall 100 2803, 4

tADSRDTR ADSN Rise to DTN R ise 20 —5

tCSRDT3 CSN Rise to DTN 3-state 10 —

tDTVDV DTN Valid to DATA Valid 06—

tADSRD3 AD SN Rise to DATA 3-state 20 —

Input Name Ref e renc e CLK Min Setup Time (tS) Min Hold Time (tH)

JTAG Signals

TDI TCLK ↑15.0 ns 2.0 ns

TMSN TCLK ↑15.0 ns 2.0 ns

TRSTN NA ASYNC ASYNC

SCAN_EN NA ASYNC ASYNC

SCAN_MODE NA ASYNC ASYNC

Miscellaneous Signals

RSTN NA ASYNC ASYNC

PMRST NA ASYNC ASYNC

IC3STATEN NA ASYNC ASYNC

IDDQ NA ASYNC ASYNC

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

61Agere Systems Inc.

5 Timing Character is ti cs (continued)

Tabl e 56. Output Timi ng Specifications

* Propagation delay skew, tPLH – tPHL, is ±200 ps.

6 Ordering Information

Outp ut Name Reference CLK Test Conditions Propagation Delay* (tPD) Unit

Min Max

Transmi t Signals

TDO TLCK ↓CL = 25 pF 3.0 20.0 ns

Miscellaneous Signals

PMRST NA —ASYNC ASYNC —

Device Code Package Temperature Comcode

TMXF281553BAL-2-DB 456-pin PB GA –40 °C to 85 °C 108700055

62 Agere Sy stem s Inc.
TMXF 28155 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
Register Description
7 Micro processor Interface and Global Control and Status Registers
Ta ble of Conte nts
Contents Page
7 Microprocessor Interface and Global Co ntrol and Status  Regis ters  .... ................ .... ... ... ........... ... .... ... ..... .... ... .... 6 2
7.1  Super Mapper Global Control and S tatus Registers .. ....................... ............ ............ ......... ............ .............. 63
7. 2  Microprocessor Inter fa ce  Reg i ste r  Map........................................................................................................ 73
Tables Page
Table 5 7. SMPR_VCR, S uper Mapper V ers ion Control R egister (RO) . . ............. . ................ ................ . ................63
Table 5 8. SMPR_SYM R[4],  Super Mapper Symbol Register4 SMPR (RO)  .................... .................. ................... 63
Table 5 9. SMPR_SYMR[3], Super M apper Sym bol Regis ter3 (RO) ............ ..... ..................... . .................. . ...........63
Table 6 0. SMPR_SYMR[2], Super M apper Sym bol Regis ter2 (RO) ...................................... . .................. . ...........63
Table 6 1. SMPR_SYMR[1], Super M apper Sym bol Regis ter1 (RO) ...................................... . .................. . ...........64
Table 6 2. SMPR_SYMR[0], Super M apper Sym bol Regis ter0 (RO) ...................................... . .................. . ...........64
Table 6 3. SMPR_ISR, Super Mapper Interrupt S ta tus Register (RO) .... ............. . ................................ ................. 64
Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW) ................ ..... .. ..... ..... .. ..... .. ....... ..... ..... .. ...... 65
Table 6 5. SMPR_GTR,   Global Trigger Regi ster (RW) ................... .......................... .......................... ................... 66
Table 6 6. SMPR_MSRR, Block So ftware Reset Register (RW)  ........................................................................... 66
Table 67. SMPR_GCR, Global Control Register (RW)  ... ............................ .......................................................... 68
Tabl e  68. SMPR_TSCR, T MUX, and SPEMPR Cont rol Regis ter (RW) .... ............................................................ 69
Table 6 9. SMPR_FCR, Framer Control Register (RW) ......................................................................................... 69
Table 70. SMPR_CLCR, CDR and LVDS Control Register (RW) ... ..... ... .. .. ................. .. ..... ..... .. .. ..... ..... .. ..... ..... ... 70
Table 7 1. SMPR_CPCR, Clock an d Power Control Register (RW)  ...................................................................... 71
Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW) .......... .. ... .. .. ..... .. ... .. ..... .. ..... .. ... .. .. ..... ... .. .. ..... .71
Table 73. SMPR_PMRCLR, PM Res et Count Low Register (RW) ............. ..... .. ..... .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... . 72
Tabl e  74. SMPR_SR, Scra tch Regi ster (RW) ..... .............................................................. .................................... 72
Table 7 5. SMPR_TX_LINE_EN1 ........................................................................................................................... 72
Table 7 6. Microprocessor Interface Register Map ................................................................................................. 73

63Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

7.1 Super Mapper Global Control and Status Registers

This section gives a brief de scription of each register bit and i ts functi onality. The abbrev i ations after each register

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/writ e (R/W) .

Table 57. SMPR_VCR, Super Mapper Version Control Register (RO)

Table 58. SMPR_SYMR[4], Super Ma pp e r Symbol Regist e r4 SMPR (RO)

Table 59. SMPR_SYMR[3], S uper Mapper Symbol Register3 (RO)

Table 60. SMPR_SYMR[2], S uper Mapper Symbol Register2 (RO)

Address Bit Name Function Reset Default

0x00000 15:11 —Reserved . 0x0000

10:8 SMPR_VERSION[2:0] Super Mapper Version Number. SMPR version

7:0 SMPR_ID[7:0] SMPR ID Nu m b er.

Address Bit Name Function Res et Defau lt

0x00001 15:8 T Super Mapper Symbol Bit. 0x544D

7:0 M Super Mapper Symbol Bit.

Address Bit Name Function Res et Defau lt

0x00002 15:8 X Super Mapper Symbol Bit. 0x5846

7:0 F Super Mapper Symbol Bit.

Address Bit Name Function Res et Defau lt

0x00003 15:8 2 Super Mapper Symbol Bit. 0x3238

7:0 8 Super Mapper Symbol Bit.

64 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 61. SMPR_SYMR[1], S uper Mapper Symbol Register1 (RO)

Table 62. SMPR_SYMR[0], S uper Mapper Symbol Register0 (RO)

Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO)

Address Bit Name Function Reset Default

0x00004 15:8 1 S uper Mapper Symbol Bit. 0x3135

7:0 5 Super Mapper Symbol Bit.

Address Bit Name Function Reset Default

0x00005 15:8 5 S uper Mapper Symbol Bit. 0x350D

7:0 CR Super Mapper Symbol Bit.

Address Bit Name F un ction Re set

Default

0x00008 15 SMPR_APS_IS APS Interrupt. Active-high signal indicating an interrupt event

has occurred in the automatic protection switch (APS) block,

w hich is within the TMUX block.

0x0000

14:10 —Reserved.

9SMPR_PARITY_IS

Microprocessor Interface Data Bus Parity Error Interrupt.

Act ive-high signal indicating a µP data b us parity error has

occurred. Summary of errors detected in PAR[1] and PAR[0]

parity detectors.

8 SMPR_PMRESET_IS Perform ance Monitor Reset Interru pt. Active-high signal

indicat ing a 1 second event has occurred.

7SMPR_TPG_IS

TPG Interrupt. Active-high signal indicating an interrupt event

has occurred in the test pattern generation block.

6 SMPR_DJA_IS DJA Interrupt. Active-high signal indicating an interrupt event

has occurred in the digital jitter attenuation block.

5SMPR_FRM_IS

FRM Interrupt. Active-high signal indicat ing an interrupt

event has oc c urred in the f ra mer block. However, on device

powerup, this bit is erroneously set. A device initialization rou-

tine containing the f ollowing sequence should clear t he inter-

rupt:

■Power up the framer block by selecting one of the clock

options in addres s 0x00012.

■Set and clear the framer software reset bit, bit of address

0x0000E.

■Power down the framer block in address 0x00012.

4SMPR_XC_IS

XC Interrupt. Active-high signal indicating an interrupt event

has occurred in the cross connect block.

3 SMPR_M13_IS M13 Interrupt. Active-high signal indicating an interrupt event

has occurred in the M13 multiplexer/demultiplexer block.

2 SMPR_VTMPR_IS VT MPR In te rrupt. A ctive-high signal indicating an i n terrupt

event has oc curred in the VT mapper block.

1 SMPR_SPEMPR_IS SPEMPR Interrupt. Active-high signal indicating an interrupt

event has occurred in the SPE mapper block.

0 SMPR_TMUX_IS TMUX Interrupt. Active-high signal indicating an interrupt

event has occurred in the TMUX blo ck.

65Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 64. SMPR_IMR , Super Mapper Interrupt Mask Register (RW)

Address Bit Name F un ction Re set

Default

0x00009 15 SMPR_APS_IM APS Interrupt Mask. When this bit is set to 1, the composite

interrupt bit will be inhibited from contrib uting to the interrupt

pin APS_INTN.

0x83FF

14:10 —Reserved.

9 SMPR_PARITY_IM Microprocessor Interface Data Bus Parity Error Interrupt

Mask. When this bit is set to 1, the composite interrupt bit will

be inhibited from contributing to the interrupt pin INTN.

8 SMPR_PMRESET_IM Perf ormance Monitor Reset Interrupt Mask. When t his bit

is set to 1, the composit e i nterrupt bit will be inhibited from

con tributing to the interru pt pin INTN.

7SMPR_TPG_IM

TPG Interrupt Mask. When this bit is set to 1, the composite

interrupt bit will be inhibited from contrib uting to the interrupt

pin INTN.

6 SMPR_DJA_IM DJ A Interrupt Mask. When this bit is set to 1, the composite

interrupt bit will be inhibited from contrib uting to the interrupt

pin INTN.

5 SMPR_FRM_IM FRM Interrupt Mask. When this bit is set to 1, the composite

interrupt bit will be inhibited from contrib uting to the interrupt

pin INTN.

4SMPR_XC_IM

XC Interrupt Mas k. When this bit is set to 1, the composite

interrupt bit will be inhibited from contrib uting to the interrupt

pin INTN.

3 SMPR_M13_IM M13 Interrupt Mask. When this bit is set to 1, the composite

interrupt bit will be inhibited from contrib uting to the interrupt

pin INTN.

2 SMPR_VTMPR_IM VTMPR Interrupt Mask. When this bit is set to 1, the co m-

posite interrupt bit will be inhibited from contrib uting to the

inte rrupt p in INTN.

1 SMPR_SPEMPR_IM SPEMPR Int err upt Mask. When this bit is set t o 1, the com-

posite interrupt bit will be inhibited from contrib uting to the

inte rrupt p in INTN.

0 SMPR_TMUX_IM TMUX I nterrupt Mask. When this bit is set to 1, the compos-

ite interrupt bit wil l be inhibited from contributing to the inter-

r upt pin INTN.

66 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 65. SMPR_GTR, G lobal Trigger Register (RW)

Table 66. SMPR_MSRR, Bloc k Software Reset Register (RW)

Address Bit Name Function Reset Default

0x0000D 15:10 —Reserved. 0x0000

9 SMPR_BER_INSRT Bit Error Rate Inserti on. When this bit is set to 1,

this bit indicates to th e S uper Mapper that a bit error

has to b e inserted in the appropriate frame.

8 SMPR_PMRESET Perform a nce Monitor Reset. When this bit is set to

1, the PM RESET signal will transition from a logic 0

to a l o g ic 1 s t a te. It will stay at a logi c 1 state for a

minim um of 100 ns. (Self-clearing.)

7:1 —Reserved.

0 SMPR_SWRS Super Mapper Software Reset. When this bit is set

to 1, i t will create a software reset of the device. This

reset has t he same effect as the hardware reset. All

microproces s or registers are reset to their default

stat es and all inte rnal data path state machine are

reset. (S elf-c lear ing.)

Address Bit Name F un ction Re set

Default

0x0000E 15:8 —Reserved. 0x0000

7 SMPR_TPG_SWRS T PG Block So ftware Reset. When this bit is set to 1, it will

create a software reset for the test-pattern generation macro.

This res et has the same effects as the h ardware reset and

chip-lev el software reset. All microprocessor registers within

the macro are reset to th eir default states. All internal data

path state machine within the block are also reset.

6 SMPR_DJA_SWRS D JA B lock Software Rese t. When this bit is set to 1, it will

create a software reset for the digital jitter attenuation bloc k.

This res et has the same effects as the h ardware reset and

chip-lev el software reset. All microprocessor registers within

the macro are reset to th eir default states. All internal data

path state machine within the block are also reset.

5 SMPR_FRM_SWRS FRM Blo ck Software Reset. When this b it is set to 1, it w ill

create a software reset for the framer block. This reset has the

same effects as the hardware reset and chip-level software

reset. All microprocessor registers within the bloc k are reset

to their default states. All inter nal data path s tate machine

w ith in the block are also reset.

67Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 66. SMPR_MSRR, Block Software Reset Register (RW) (continued)

Address Bit Nam e Function Res et

Default

0x0000E 4 SMPR_XC_SWRS XC Block S oftware Reset. When this bit is set to 1, it will

create a software reset f or the cross connect block. This

reset has the same effects as the hardware reset and chip-

level software reset. All microprocessor registers within the

block are reset to their def ault states. All internal data path

state machine within t he block are also reset .

0x0000

3 SMPR_M13_SWRS M13 Block Software Reset. When this bit is set to 1, it will

create a software reset for the M13 multiplexer/demulti-

plexer block. This reset has the same effects as the hard-

ware reset and chip-level software reset.

All microprocessor registers w ithin the block are reset to

their default states. All internal data path state machine

within the block are also reset.

2 SMPR_VTMPR_SWRS VTMPR B lock Software Reset. When this bit is se t to 1 ,

it will create a software reset for the VTMPR block. This

reset has the same effects as the hardware reset and

chip-level software reset. All microprocessor registers

within the block are reset to their default states. All inter-

nal data path state machine within the block are also

reset.

1 SMPR_SPEMPR_SWRS SPE MPR Block Software Reset . Wh en this bit is se t

to 1, i t will create a software reset for the SPEMP R block.

This reset has the same eff ects as the hardware reset and

chip-level software reset. All microprocessor registers

within the block are reset to their default states. All internal

data path state machine within the block are also reset.

0SMPR_TMUX_SWRS

TMUX Bloc k Software Reset. When this bit is set to 1, it

will create a software reset for the TMUX block. This reset

has the same effects as the hardware reset and chip-lev el

software reset. All microproces s or registers within the

block are reset to their def ault states. All internal data path

state machine within t he block are also reset .

68 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 67. SMPR_GCR, Global Control Register (RW)

Address Bi t Name Function Reset

Default

0x0000F 15:10 —Reserved. 0x0000

9:8 SMPR_PMMODE[1:0] Perform a nce Monitor Mode:

00 = PMRST comes from external pin.

10 = PMRST comes from external pin.

01 = PMRS T comes from internal 1 second counter.

Note: P lease see Table 72 and Table 73.

11 = PMRST is software controlled using the

SMPR_PMREST regi ster bit 8 (Table 65 on

page 66).

7:5 —Reserved.

4 SMPR_PARITY_EVEN_ODD Even or Odd Parity Indication on the Microproces-

sor Data Bus. This bit cont rols the parity se tting and

checking on the microprocessor data bus:

0 = Even parity on microprocessor byte data/parity bus.

1 = Odd pa ri ty on microprocessor byte data/parity bus.

3SMPR_OH_DEFLT

Overhead Default. T h is b it c on t r o ls the f illing of the

unused overhead bytes:

0 = Fi lling the unused overhead bits with 0.

1 = Fi lling the unused overhead bits with 1.

2 SMPR_FXD_STFF_DEFLT Fixed Stuff Default. This bi t co ntro l the filling of the

fixed stuff bytes:

0 = Fi lling t he fi xed stuff bytes with 0.

1 = Fi lling t he fi xed stuff bytes with 1.

1 SMPR_COR_COW Clear On Read or Clear On Write. This bit controls the

way clearin g i s perfor med on all delta and event bits in

all registers:

0 = The delta and event bit is cleared by writing a 1 to it.

Note: The clear-on-w rite (COW) feature does not apply

to all registers in the 28-channel framer block.

The only framer block register that has CO W is

transmit FDL link register 8 (address 0x8LTD7).

All other registers in the framer bl ock are only

clear-on-read.

1 = The d e lta and event bit is cleared when a microp ro-

cessor read is performed on this delta and ev ent bit.

0 SMPR_SAT_ROLLOVER S aturate or Rol lover. This bit cont rols i f error counters

hold their values or rollover when they reach the ir ma xi-

mum values .

0 = Error counters rollov er when reaching maximum v al-

ues.

1 = Error counters hold their values when reaching max-

imum values.

69Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register ( RW)

Table 69. SMPR_FCR, Framer Contro l Register (RW)

Address Bit Name Function Reset

Default

0x00010 15:4 —Reserved. 0x0000

3 MPU_RHDZTHD_LB Forces Received High-speed to Transmit High-

speed Data Loo pback Prior to the CDR.

2 SMPR_RETIME_CLK_EDGE Ret ime Clock Edge f or the Received High-speed

Data. This bit controls on whic h clock edge, positive

or negative, the rece ived high-speed data is to

retimed.

1 = The received data will be clock ed into the device

on the negativ e clock edge.

0 = The received data will be clock ed into the device

on the positive clock edge.

1 SMPR_TELECOMBUS_EDGE Teleco m Bu s Edg e. When the SPE mapper is

enabled t o use a time slot on the telecom bus. This

bit selects the clock edge for the data signals trans-

mitted to the telecom bus during the s elected time

slot.

0 = Clock telecom bus signals out on the falling edge.

1 = Cloc k telecom bus signals out on the rising edge.

0 SMPR_TMUX_MASTER_SLAVE SMP R/T MUX M aster Slave . Thi s bit controls if the

TM UX blo ck in this Super M apper is the master

de vice in the system module that this Super Mapper

is on, o r if i t is a slave dev ice.

0 = This Super Mapper/TMUX is a slave d evice in

the module.

1 = This Super Mapper/TMUX is a mas t er device in

the module.

Address Bit Name Function Reset

Default

0x00012 15:3 —Reserv ed. 0x0000

2:0 SMPR_FRM_CLK_SEL[2:0] Fram er Clock Selection. Selects the source of the

framer high-speed clock the sel ec ted clo ck needs to be

faster than the aggregate throughput of the framer block

for proper operation.

000 = Framer is powered down. No clock required.

001 = Framer receives TLSC 52 (pin AC3) clock input

010 = Framer receives DS1XCLK (pin AD16) clock input.

011 = Fr amer receives E1XCLK (pin AC17) clock input.

70 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 70. SMPR_CLCR, CDR, and LVDS Control Register (RW)

Address Bit N am e Function R eset

Default

0x00013 15:11 —Reserved. 0x000C

10 SMPR_MPU_CDR_MODE CDR Mode Selection. This bit controls the operating

mode of the internal CDR; whether it operates a t

155 MHz or 5 1 MHz.

0 = 155 MHz mode.

1 = 51 MH z mode.

9 SMPR_MPU_CG_PWRDN PLL Powerdown Selection. This bit con trols whether

the internal framer PLL is powered on or off.

0 = Internal PLL powered on.

1 = Internal PLL pow ered off.

8 SMPR_LVDS_REF_SEL LV DS Reference Vo ltage Selecti on. This bit controls

which re ference voltage, internal or ext ernal, is used to

power t he LVDS buffers.

0 = External reference voltage is used.

1 = Internal reference voltage is u se d.

7:4 —Reser ved.

3 SMPR_RXPWRDN CDR C hannel Po werdo wn. This bit cont rols the power

to the CDR data channel.

0 = Cha nnel is active, power is on.

1 = Channel is inactive, power to the channel is turned off.

2 SMPR_PLLPWRDN CDR Phase-Lock Lo op Pow erdown. This bit controls

the power to t he CDR PLL c ircui t.

0 = PLL is active, power to the PLL is turned on.

1 = PLL is inactive, power to the PLL is turned off.

1 SMPR_MRESET CDR Master Reset. This bit is us ed for the CDR initial-

ization. I t can also be used in test mode to reset t est cir-

cuitry.

0 = No reset.

1 = Reset mode.

0 SMPR_CDR_SEL CDR Selection. This bit c ontrols if the T MU X receives

its high-spee d recei ve clock and data from the on-chip

CDR block o r from the p ins (bypass th e CDR).

0 = Bypass CDR. Receive s clock and data directly from

pins.

1 = Use CDR. Receives clock and dat a through CDR.

71Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 71. SMPR_CPCR, Clock an d Power Control Reg ister (RW)

Table 72. SMPR_PMRCHR, PM Reset Count High Regist er (RW)

Address Bit Name Function Reset

Default

0x00014 15:9 —Reserved. 0x0000

8 SMPR_M13_TCLK M13 M U X/Tx Clock Enable.

0 = M13 MUX/Tx clock is powered down and inactive.

1 = M13 MUX/Tx clock is powered up and active.

7 SMPR_M13_RCLK M13 DeMUX Rx Clock Enable.

0 = M13 d eMUX/Rx clock is powered down and inactive.

1 = M 13 deM UX/Rx clock is powered up and active.

6 SMPR_DJA_CLK Digital Jitter Attenua tion Clock Enable.

0 = DJA DPLL is powered down and in a ctive.

1 = DJA DPLL is powered up and active.

5 SMPR_VTMPR_TCLK VT Mapper T x Cl ock Enable.

0 = VT mapper Tx clock is powered down and inactive.

1 = VT mapper Tx clock is powered up and active.

4 SMPR_VTMPR_RCLK VT Mapper Rx Clock Enable.

0 = VT mapper Rx clock is powered and inactive.

1 = VT mapper Rx clo c k is p owered up and active.

3 SMPR_SPEMPR_TCLK SPE Mapper Tx C lock Enable .

0 = SPE mappe r Tx clock is powered down and ina ctive.

1 = SPE mappe r Tx clock is pow ered up and active.

2 SMPR_SPEMPR_RCLK SPE Mapper Rx Clock Ena ble .

0 = SPE mapper Rx clock i s powered dow n and inactive.

1 = SPE mappe r Rx clock is powered up and active.

1 SMPR_TMUX_TCLK TMUX Tx Clock Enable.

0 = TMUX Tx clock is powered down and inactive.

1 = TMUX Tx clock is powered up and activ e.

0 SMPR_TMUX_RCLK TMUX Rx Clock Enable.

0 = TMUX Rx clock is powered down and i nactive.

1 = TMUX Rx clock is powered up and active.

Address Bit Name Fun ction Reset

Default

0x00016 15:11 —Reserved. 0x01F8

10:0 SMPR_PMRESET_HIGH_COUNT[10:0] Performance Monitor Counter Preset. The

pre se t value of this register dete rmines the

frequen cy of the internal PM counter. User

should preload an appropriate value based

on the microprocessor interface clock rate in

order to reach the de sir ed PMR ST rate.

72 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 73. SMPR_PM RCLR, PM Reset Cou nt Low Register (RW)

Table 74. SMPR_SR, Scrat c h Re gister (RW)

Table 75. SMPR_TX_LINE_EN1

Address Bit Name Function Reset

Default

0x00017 15:0 SMPR_PMRESET_LOW_COUNT[15:0] Performance Monit or Counter Preset .

The preset value of this register determines

the frequency of the internal PM count er.

User should preload an appropriate value

based on the microprocessor int erface

clock rate in order to reach the desired

PMR ST ra te.

0x0000

Address Bit Name Function Reset

Default

0x0001F 15:0 SMPR_SCRATCH_REGISTER[15:0] Scratch Register. This regi ster is for test

and diagnostics purpose.

Read/write operations can be performed on

all bits. No SMPR control and status will be

aff ected b y any read/write operations to this

0x0000

Address Bit Nam e Fun ction Reset

Default

0x00018 15:0 SMPR_TX_LINE_EN[16:1] 3-State Control for LINETXDATA, LINETXCLK,

and LINETXSYNC Output Pins. 0x0000

0x00019 12:0 SMPR_TX_LINE_EN[29:17] 3-State Control for LINETXDATA, LINETXCLK,

and LINETXSYNC Output Pins. 0x0000

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

73Agere Sy stem s Inc.

7 Microprocessor Interface and Global Control and Status Registers (continued)

7.2 M icroprocessor Inte rface Register Map

Table 76. Micro processor Interface Register Map

Address Symbol Bit

15 Bit

14 Bit

13 Bit

12 Bit

11 Bit

10 Bit

9Bit

8Bit

7Bit

6Bit

5Bit

4Bit

3Bit

2Bit

1Bit

Super Mappe r Ve rsi on Control Register—RO

0x00000 SMPR_VCR 0 0 0 0 0 SMPR_VERSION[2:0] SMPR_ID[7:0]

Super Mappe r Symbol Re gi ster—RO

0x00001 SMPR_SYMR4 0x54 = T 0x4D = M

0x00002 SM PR_SY MR3 0x58 = X 0x46 = F

0x00003 SMPR_SYMR2 0x32 = 2 0x38 = 8

0x00004 SMPR_SYMR1 0x31 = 1 0x35 = 5

0x00005 SMPR_SYMR0 0x35 = 5 0x0D = CR

0x00006

—

0x00007

—

Super Mapper Inte rrupt Status Re gi ster—RO

0x00008 SMPR_ISR SMPR_APS_IS SMPR_

PARITY_IS SMPR_

PMRESET_IS SMPR_TPG_IS SMPR_DJA_IS SMPR_FRM_

IS SMPR_XC_IS SMPR_M13_

IS SMPR_VTMPR_

IS SMPR_

SPEMPR_IS SMPR_TMUX_

Super Mapper Interrupt Mask Register —R/W

0x00009 SMPR_IMR SMPR_APS_IM SMPR_

PARITY_IM SMPR_

PMRESET_IM SMPR_TPG_IM SMPR_DJA_

IM SMPR_FRM_

IM SMPR_XC_IM SMPR_M13_

IM SMPR_VTMPR_

IM SMPR_

SPEMPR_IM SMPR_TMUX_

0x0000A

—

0x0000C

—

Global Trigger Registe r—R/W

0x0000D SMPR_GTR SMPR_BER_

INSRT SMPR_

PMRESET SMPR_SWRS

Block Software Reset Register—R/W

0x0000E SMPR_MSRR SMPR_TPG_SWRS SMPR_DJA_

SWRS SMPR_FRM_

SWRS SMPR_XC_

SWRS SMPR_M13_

SWRS SMPR_VTMPR_

SWRS SMPR_SPEMPR_

SWRS SMPR_TMUX_

SWRS

Global Control Register (SMPR_GCR)—R/W

0x0000F SMPR_GCR SMPR_PMMODE[1:0] SMPR_PARITY_

EVEN_ODD SMPR_OH_

DEFLT SMPR_FXD_

STFF_DEFLT SMPR_COR_

COW SMPR_SAT_

ROLLOVER

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

74 Agere Systems Inc.

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 76. Micr oprocessor Interface Register Map (continued)

Address Symbol Bit

15:11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMUX and SPEMOR CONTROL Register—R/W

0x00010 SMPR_TSCR MP0RH02THD_LB SMPR_RETIME_

CLK_EDGE SMPR_TELECOMBUS_

EDGE SMPR_SMPR_TMUX_

MASTER_SLAVE

0x00011 —

FRAMER Control Register—R/W

0x00012 SMPR_FCR SMPR_FRM_CLK_SEL[2:0]

CDR and LVDS Control Register—R/W

0x00013 SMPR_CLCR —SMPR_MPU_C

DR_MODE SMPR_MPU_

CG_PWRDN SMPR_LVDS_

REF_SEL SMPR_RXPWRDN SMPR_

PLLPWRDN SMPR_MRESET SMPR_CDR_SEL

Clock and Power Control Register—R/W

0x00014 SMPR_CPCR SMPR_M13_

TXCLK SMPR_M13_

RXCLK SMPR_DJA_

CLK SMPR_VTMPR_

TXCLK SMPR_VTMPR_

RXCLK SMPR_SPEMPR_

TXCLK SMPR_SPEMPR_

RXCLK SMPR_TMUX_

TXCLK SMPR_TMUX_RXCLK

0x00015 —

PM Reset Co unt R eg ister Hi g h—R/W

0x00016 SMPR_PMRCHR SMPR_PMRESET_HIGH_COUNT[10:0]

PM Reset Co unt R eg ist er Low—R/W

0x00017 SMPR_PMRCLR SMPR_PMRESET_LOW_COUNT[15:0]

0x00018 TX_LINE_EN1 TX_LINE_EN[16-1]

0x00019 TX_LINE_EN2 TX_LINE_EN[29-17]

Scratch Register—R/W

0x0001F SMPR_SR SMPR_SCRATCH_REGISTER[15:0]

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
75Agere Systems Inc.  
8 TMUX Regi sters
Ta ble of Conte nts
Contents Page
8 TMUX Registers  ................................................................................................................................................. 75
8. 1  TMUX Register Descrip tions .... ........................................................................................... ......................... 77
8. 2  TMUX Register Map ..... .............................................................................................................................. 124
Tables Page
Table 7 7. TMUX_ID_R, TMUX Identification Register (RO) .................................................................................. 77
Table 7 8. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W) ................................................................. 77
Tabl e 79.  T MUX_ RCV_ TX _MODE , TMUX Receive/Transmit Mode  (R/W) ........................... ...............................77
Table 80. TMUX_TX_D LT, Delta/Event (COR /COW) ........................................................................................... 78
Tabl e  81. TMUX_RPS_DLT,  De lta/Eve n t ( COR/CO W)   ...................... .................................................................. 78
Tabl e  82. TMUX_RHS_DLT,  De lta/Event (COR/CO W)  ........................................................................................ 79
Table 83. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)  ............................................................................ 81
Table 84. TMUX_TX_MSK, M ask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)  ..........................87
Table 85. TMUX_RPS_MSK, Mask Bits for INT Int errupt Signal (R/W) (Mask = 1, No Mask = 0) ................ ..... .. 88
Table 8 6. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)  .......................88
Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) .... ....... ....... 89
Ta ble  88.  T MUX_ APSINT_M SK, Mask Bits for APSINT Inter ru p t Signal (R/W) ( Mask = 1, No Mask = 0) .... ....... 91
Ta ble  89. TMUX_TX_STA TE, Sta te  Parameters (RO)  .. ........................................................ ............................... 91
Table 9 0. TMUX_RPS _S TA TE, State a nd Value Parameters  (RO)  ............. ..... . .................. .......................... ..... . 91
Table 9 1. TMUX_RHS_STATE, State and Value Parameters (RO) .....................................................................92
Table 92. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO) .. ......................... .......... ... .................92
Table 9 3. TMUX_RHS_CTL, Receive High-speed Control Param eters (R/W) ..................................................... 94
Table 9 4. TMUX_RLS_B I TB LK _CTL, Receive Low- speed Co ntrol Parameters (R/W)  ............... ..... .................... 94
Tabl e  95. TMUX_RLS_MODE_ CTL, Receiv e Lo w- sp eed Cont r o l Par a mete rs (R/W) .... ...................................... 95
Table 9 6. TMUX_RAISINH_CT L, Receive Low-speed Control Parameters (R/W) ................. . ................ ............. 96
Table 9 7. TMUX_LOSDETCNT, Receive Low-speed Cont rol Parameters (R/ W)  ................................................ 97
Table 98. TM UX_CNTD_TOH_[A—B], Continuous N-Times Detect  Control Par amet ers (R/W) ..........................98
Table 99. TM UX_CNTD_POH_[A—B] , Continuous N-Ti me s Detect Cont rol Parameters (R/W)  ......................... 99
Table 100.  TMUX_C2EXP[1 —2_3], Continuous N-Times Det ect Control Pa r ameters (R/W) ................... ......... 100
Table 101. TMUX_RF1MON, Receive Monitor Values (RO) .............................................................................. 100
Table 102. TMUX_RAPSMON, Receive Monitor Values (RO)  ...........................................................................100
Table 103. TMUX_RS1MON, Receive Mon itor Values (RO) .............................................................................. 100
Table 1 04.  TMUX_RPOHMON[1—3][A—D], Receive Monito r Values (RO)  .......................................................1 01
Table 105. TMUX_TLS_CTL, Transmit Low -spe ed Control Parameters (R/W) ..................................................1 02
Table 106. TMUX_THS_PORT_CTL, Transmit High-spe ed Port Co ntrol Parameters (R/W)  .............................103
Table 107. TMUX_THS _TO H_CTL, Transmit Hig h-speed Control Parameters  (R/W)  ................. ........... ........... 1 03
Table 1 08. TMUX_THS_POH[ 1—3]_CTL, Transmit High-speed Control Parameters (R/W) ..... ..... .. ..... .. ..... .....105
Table 109. TMUX_TLRDI_CTL, Transm it High-sp eed Line RDI Co ntrol Parameters (R/ W) .............. ................109
Table 110. TMUX_TPRDI_CTL, Transmit High-speed Path RDI Control Parameters (R/W) ..... ..... .. ..... .. ..... .....109
Table 111.  T MUX_T Z0_INS _V AL, Transmit TOH and POH Insert Values (R/W)  .. .............. .............. ................ 110
Table 112.  T MUX_T S1 _F1_ INS_V AL, Transmit TOH and POH Insert Values (R/W) ................. .............. . ........ 1 10
Table 113.  T MUX_T APS_I NS _VAL, Transm it T OH and POH Insert Valu es (R/ W) .................. ................. ........110
Table 1 14.  TMUX_T PO H[1—3]_INS_[A—C], Transmit T OH and POH Insert V alu es (R/ W) .. ............ ............ ...110
Table 115. TMUX_TBERINS _CTL , Transm it Hi gh-s peed Error Insertion Control Param eters (R/W) . ............ ... 112
Table 116. TMUX_THS _ER R_CTL, Transmit Hig h-speed Error Insertion Control Parameters (R/W) ............ ... 1 13
Table 117.  T MUX_T OA C_CT L, Receive/Transmit TOA C/ POA C Control Parameters (R/W) . .................... ........113
Table 118.  T MUX_RP OAC_CTL, Re ce ive/Transmit TOAC/POAC Con trol Parameters (R/W) ................. ......... 1 15
Table 119.  T MUX_T FRA M EOFF SET , Tran smit High-speed Offset Control Parameters  (R/W) .......... ............... 116
Table 1 20.  TMUX_SD_CTL[1—6],  B1/ B2 Signal Degrade Set/Clear Control Registers (R/ W) ................. ......... 116

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
76 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Table of Conten ts (continued)
Tables Page
Table 1 21. TMUX_SF_CTL[1—6], B1/B2 Signal Fa il Set/Clear Control Registers (R/W) ............ ....... ................ 117
Table 1 22. TMUX_B3SD_CTL[1 —6], B3 Signal Degrade Set/Clear Control Registers (R/W) ................ ..... .. .... 117
Table 1 23. TMUX_B3SF_CTL[1—6], B3 Signal Fail  Set/Clear Control Registers (R/W) ................ .................... 118
Table 1 24. TMUX_B1ECNT, Receive B1 Error Counts (RO) .............................................................................. 118
Table 1 25. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error  Cou nt s (R O)  ... ... . .. .. . .. ... .. .. 1 1 9
Table 1 26.  TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO) .................................................................... 1 19
Tab le 127. TMUX_M1ECNT_17_16 and TM UX_M1ECNT_15_0, Receive M1 Error Counts (RO)  ................... 1 20
Table 1 28.  TMUX_G1ECNT[1—3], Re ce ive G1 Error Counts (RO) ................. ................... ................ . .............. 120
Table 129. TMUX_RPTR_INCCNT[1—3], Re ceive Poin ter Increment Count (RO ) ................ .............. ..............121
Table 130. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO) ......................................... 1 21
Table 131. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W )  ........................... ...................... 121
Table 132. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO) .................................................... 121
Table 1 33. TMUX_TJ0VALUE[1—8], J0 B y te Transmit Insert (R /W) .. ................. ................ ................. .............. 121
Table 134. TMUX_RJ1EXPECTED1_[1—32] , Expected  J1 Byt e Val u e for Port 1 (R/W) ................................... 122
Table 135. TMUX_RJ1EXPECTED2_[1—32] , Expected  J1 Byt e Val u e for Port 2 (R/W) ................................... 122
Table 136. TMUX_RJ1EXPECTED3_[1—32] , Expected  J1 Byt e Val u e for Port 3 (R/W) ................................... 122
Table 137.  TMUX_RJ1CAPTURED1_ [1—32], Captured J1 Value for STS #1 (RO) ..........................................122
Table 138.  TMUX_RJ1CAPTURED2_ [1—32], Captured J1 Value for STS #2 (RO) ..........................................122
Table 139.  TMUX_RJ1CAPTURED3_ [1—32], Captured J1 Value for STS #3 (RO) ..........................................123
Table 1 40. TMUX_TJ1VALUE_1[1—3 2 ], J1 Byte Tran smi t Insert for STS #1 (R/W)  .. ....................................... 123
Table 1 41. TMUX_TJ1VALUE_2[1—3 2 ], J1 Byte Tran smi t Insert for STS #2 (R/W)  .. ....................................... 123
Table 1 42. TMUX_TJ1VALUE_3[1—3 2 ], J1 Byte Tran smi t Insert for STS #3 (R/W)  .. ....................................... 123
Table 1 43. TMUX Register Map .......................................................................................................................... 124

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

77Agere Systems Inc.

8 TMUX Registers (continued)

8.1 TMUX Re giste r Des criptions

This section provides a brief description of each register bit and its functionality. The abbreviations after each regis-

ter indicate if the regi ster is read only (R O), c l e ar-on- read/ clear- on-wri te (COR /C OW ), o r read/ wri t e ( R / W) .

Table 77. T MUX_ID_R, TMUX Identification Register (RO)

Table 78. TMUX_ONESHOT, TMUX One- Shot Register 0 to 1 (R/W)

Table 79. TMUX_RCV_TX_M ODE, TMUX Receive/Transmit Mod e (R/ W)

Address Bit Name Function Reset Default

0x40000 15:11 —Reserved. 0x0

10:8 TMUX_VERSION[2:0] Block V ersion Number. B lo ck version register w ill

change each time t he device is changed. 0x0

7:0 TMUX_ID[7:0] Block ID Number. 0x04

Address Bit Nam e Fun ction Reset Default

0x40002 15:8 —Reserved. 0x00

7 TMUX_B3SFCLEAR B3 Signal Fail Clear. Allo ws the signal f ail algorithm

to be force d into the normal state. 0

6 TMUX_B3SFSET B3 Signal Fail Set. Allows the signal fail algorithm

to be fo rced into the failed state. 0

5 TMUX_B3SDCLEAR B3 Signal Degrade Clear. Allows the signal

degrade algorit hm to be f orced into the normal state. 0

4 TMUX_B3SDSET B3 Signal Deg rade Set. Allows the signal degrade

algorithm to be forced into the degraded state. 0

3 TMUX_SFCLEAR Signal Fail Cl ear. Allows the signal fail algorithm to

be forced into the n or mal state. 0

2 TMUX_SFSET Signa l Fail Set. Allows the signal f ai l algorithm to be

forced into the failed state. 0

1 TMUX_SDCLEAR Signal Degrade Clear. Allo ws the signal degrade

algo rithm to be forced into the normal state. 0

0 TMUX_SDSET Signal De grade Set. Allows the signal degrade

algorithm to be forced into the degraded state. 0

Address Bit Nam e Function Reset Default

0x40003 15:1 —Reserved. 0x000

0 TMUX_STS1MODE STS-1 Mode Control Bit. A 1 indicates that the

received and transmitted high-speed data is STS-1

data operating at 52 MHz. A 0 indicates that the

received and transmitted high-speed data operates

at 155 MHz.

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
78 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Table 80. TMUX _TX_DLT, Delta/Event (COR/COW)
Table 81. TMUX_RPS_DLT, Delt a/Event (COR/COW)
Address Bit Name Fun ction Reset 
Default
0x40004 15:7 —Reserved. 0x000
6:4 TMUX_TLSPARE[3:1] Transm it Low-speed Parity Error Even t (Input Port  Num-
ber). This event bit ind icates a byt e t rans fer parity error was 
detected on the respective STS-1/A U-3 input. The mask bits 
are TM UX_TLSPARM[3:1] ( Table 84).
0
3TMUX_TPOAC_PETransmit Path Overhead Access Channel (TPOAC) Par-
ity Error Event. This event b it indicates a parity error was 
detected on the incoming tra nsmit path overhead access 
channel. The mask bit is TMUX_TPOAC_PM (Table 84).
0
2TMUX_TTOAC_PETran sm it Tr ansp ort Overhead Access Channel (TTOAC) 
Parity Error Event. This  event  bi t indicates a pari ty error 
was detected on the incom ing transmit transport overhead 
access channel. The mask bit is TMUX_TTOAC_PM 
(Table 84).
0
1TMUX_THSILOFDTransmit High-speed  Input Loss of Frame Delta. This 
delta bit i n dicates a change of sta te  for  the transmit loss of 
frame bit TMU X_THSILO F  (Table 89). The m as k bit is 
TMUX_THSILOFM (Table 84).
0
0 TMUX_THSILOCD Transmit High-speed Input Loss of Clock Delta. This 
delta bit i n dicates a change of sta te  for  the transmit loss of 
high-speed cloc k bit TMUX_THSILOC (Table 89). The mask 
bit i s TM UX_THSILOC M (Table 84).
0
Address Bit Name F un ction Reset 
Default
0x40005 15:6 —Reserved. 0x000
5TMUX_RPSLOFDReceive Protection High-speed Loss of Frame Delta. This 
de lta bit indicates a change in  state of TMUX_RPSLOF 
(Table 90). T he mask bit is TMUX_RP S LOF M (Table 85).
0
4 TMUX_RPSOOFD Receive Protection High-speed Out of Frame Delta. This 
de lta bit indicates a change in  state of TMUX_RPSOOF 
(Table 90). T he mask bit is TMUX_RP S OOF M  (Table 85).
0
3TMUX_RPSILOCDReceive Protection High-speed Loss of Input Clock 
Delta. This delta bit indic ates a change in state of the 
TMUX_RPS ILOC (Table 90) state bit. The mask bit is 
TMUX_RPS ILOCM  (Table 85).
0
2TMUX_RPSB2EReceive Protection High-speed B2 Error Event. This e vent 
bit indicates a B2 error w as detected in the receive protection 
input. The mask bit is TMUX_RPSB2M (Table 85).
0
1 TMUX_RPSLREIE Recei ve Protection High-speed Line REI Event. This 
event bit indi c ates a line REI error was detected in the 
receive protection input. The mask bit is T MUX _RPSLREIM 
(Table 85).
0
0—Reserved. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
79Agere Systems Inc.  
8 TMUX Registers (continued)
Table 82.  T MUX_RHS_DLT, Delta/Event (COR/COW)
Address Bit Nam e Function Reset Default
0x40006 15 —Reserved. 0
14 TMUX_RS1BABE Receive S1 Babble Event. This event bit indicates an 
inconsistent S1 value is being received. The ev ent is 
triggered if TMUX_CNTDS 1FRAME[3:0] (Table 98) co n-
secutive frames pass without a validated me ssage 
occurring.  T he m ask bit is TMUX_RS 1BABM  (Table 86).
0
13 TMUX_RS1MOND Receive S1 Monitor Delta. Thi s delta bit indicates a 
chang e of state for TMUX_RS1MON[7:0] (Table 103). A 
new S1 value is detected after TMUX_CNTDS1[3:0] 
(Table 98) consecutive occurrences of a co nsistent new 
val ue in the S1 b yte. The mask bit is TMUX_RS1MONM.
0
12 TMUX_RLRDIMOND Receive Line RDI  Monitor Delta. Thi s delta bit indi-
cates a c hange in state for TM UX _RLRDI MON 
(Table 91) when the pattern 110 is detected/not detected 
TMUX_CNTDK2[3:0] (Table 98)  cons ec uti v e ti mes in t he 
incoming STS-3/STM-1 fra me. The mask b it is 
TMUX_RLRD IMONM (Table 86).
0
11 TMUX_RLAISMOND Receive Line AIS  Monitor Delta. This  de lt a  bit i ndi -
cates a c hange in state for TM UX_RLAISMON 
(Table 91) when the pattern 111 is detected/not detected 
TMUX_CNTDK2[3:0] consecutive times in th e incoming 
STS-3/STM-1 fr ame. T he mask bit i s 
TMUX_RLAISMONM (Table 86).
0
10 TMUX_RK2MOND Receive K2 Monitor Delta.  This delta bit indicates a 
change in state f or TMUX_K2MON[2:0] (Table 102 on 
page 100). A new K 2 value is detected after 
TMUX_CNTDK2[3:0] consecutive occurrences of a con-
sistent new value in the t hree least signif icant  bits of  the 
incoming K2 byte.  Note that this d elta b it may  be coinci-
dent with TMUX_RLRDIMOND and 
TMUX_RLAISMOND. The mask bit is 
TMUX_RK2MONM  (Table 86).
0
9 TMUX_RAPSBABE Receive APS Babble Event. This event bit indi ca tes 
when an inconsistent APS value has been detected 
TMUX_CNTDK1K2[3:0] (Table 98) times in the incoming 
TMUX_CNTDK 1K2FRAM E[3:0] (Table 98) co ns ec utive 
frames. T he ma sk bit is TMUX_RAPSBABM (Table 86 
on page88 ).
0
8 TMUX_RAPSMOND Receive APS Monitor Delta. This delt a bit indicates a 
change in state in the received APS v a lu e  
TMUX_RAPSMON[12:0] (Table 102) when a new con-
sistent value is detected TMUX_CNTDK1K2[3:0] times 
in the K1 and K2[7:3] bits. The mask bit is 
TMUX_RAPSMONM (Table 86).
0

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
80 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW) (continued)
Address Bit Name Function Reset Default
0x40006 7 TMUX_RF1MOND Rece ive F 1 Monitor Delta. T his delt a  bit i ndicat es a 
change in state of TMUX_RF1MON0[7:0] and 
TM U X _ RF1MO N 1[7:0] (Table 101) w hen a cons istent 
new value is detec ted  in the incom ing F1 byte for 
TMUX_CNTDF1[3:0] (Table 98) continuous frames. The 
current value is stored in TMUX_RF1M ON0[ 7: 0] and the 
previous  value is  stored in TMU X_RF 1M ON0[7:0]. The 
mask bit is TMUX_RF1MONM (Table 86). 
0
6TMUX_RTIMSDReceive Section Trace Identifier Mismatch Delta. This 
delta bit indicates a change in state in the  received 16-
byte J0 sequence of bytes if the J0 mode is programmed 
to receive a 16-byte sequence. The mask  bit is 
TM UX_RTI MSM (Table 86). 
0
5 TMUX_RHSSFD Receive High-speed Signal F ail  BER Algori thm Delta. 
This delta bit indicates a change of state for the signal fail 
BER algorithm  s tate bit  TMUX_RHSSF (Table 91). The 
mask   bit for this delta bit is TMUX_RHSS FM  (Table 86). 
0
4 TMUX_RHSSDD Receive High-speed Signal Degrade BER Algorithm 
Delta. This delta bit i ndicates a change of s tate for the 
signal d egrade BER algorithm  state bit TMUX _RHSSD 
(Table 91). T he mas k bit is TMUX_RHS S DM (Table 86). 
0
3 TMUX_RHSLOSD Receive High-speed Loss of Signal Delta. This delta 
bit indicates  a c hange i n s tate of either  TMUX_RHSLO S 
(Table 91) or TMUX_RHS LOSEXTI (Table 91). 
TMUX_RHSLOS EXTI is an external  input from a devic e  
pin. TM UX _RHSLOS  is an internally generated state bit  
based on monitoring for a consecutive 0/1s p attern  i n the 
data input. The mask bit is TMUX_RHSLOSM ( Table 86).  
0
2 TMUX_RHSLOFD Receive High-speed Loss of Frame Delta. This delta 
bit indicates  a c hange i n state of T M UX_RHSLOF 
(Table 91). The mask bit is TMUX_RHSLOFM (Table 86). 
0
1 TMUX_RHSOOFD Receive High-speed Out of Frame  Delta. This  de lta bit 
indicates a change in state of TMUX_R HSOOF 
(Table 91). The mask bit is TMUX_RHSOOFM (Table 86). 
0
0 TMUX_RHSILOCD Receive High- speed Loss of  Input Clock Delta. This 
delta bit indicates a change in s tate of the 
TMUX_RHSILOC (Table 91) state b it.  The mask bit is 
TMUX_RHSILOCM (Table 86). 
0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
81Agere Systems Inc.  
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW)
Address Bit N am e Function Rese t 
Default
0x40007 15 TMUX_RSFB3D1 Receive P ath Signal Fail BER Algorithm Delta. T his d e lt a  
bit i ndicat es  a c hange of state for the signal fail BER algo-
rithm state bit TMUX_RSFB31 (Table 92) at the path level for 
port 1. O nly  port 1 infor mation is valid in AU-4 mode and in 
STS-1 m ode. The mask bit is TMUX_RSFB3M1 (Table 87). 
0
14 TMUX_RSDB3D1 Receive Path Signal Degrade BER Algorithm Delta. This 
delta bit indicates a change of state for the signal fail BER 
algorithm state bit T MUX_RSDB31 (Table 92) at   the path 
leve l for p ort 1 . Only port  1 informa tion is valid in AU-4 mode 
and in STS-1 mode. The mask bit is TMUX_RS D B3M1 
(Table 87). 
0
13 TMUX_RUNEQPE1 Receive Path Unequipped Event. T his event bit indicates 
that the curren t value of the received C 2 (signal label) byte, 
TMUX_C2M ON1[7: 0]  (Table 104), has a value 0x00,  indicat-
ing unequipped payload on port 1. Only port  1 information is 
valid in AU-4 mode and in  STS-1 mode. The mask bit is 
TMUX_RUNEQPM1 (Table 87). 
0
12 TMUX_RPLMPE1 Receive P ath Payload Label  Mismatch Event. This event 
bit indicates th at the current value of the r e ceived C2 (signal 
label) byte,  TMUX _C2M ON1[ 7:0], differs from the expected 
C2 value, TMUX_C2EX P1[7:0] (Table 100) for port 1. Only 
port 1 inform ation is valid in AU-4 mode and in STS- 1 mode. 
The mask bit  i s TMUX_RPLMPM1 (Table 87).
0
11 TMUX_RN1MOND1 Receive N1 Monitor Delta. Thi s delta bit indicates a change 
in state in TMUX_N1MON1[7:0] (Table 104). The N 1 c urrent 
value is updated when a consecutive and consistent value is 
detected in the incoming N1 byte for TMUX_CNTDN1[ 3:0] 
(Table 99) frames  on port 1. Only port 1 inform ation is valid 
in AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RN1MONM1 (Table 87).
0
10 TMUX_RK3MOND1 Receive K3 Monitor Delta. This delt a bit indicates a change 
in state in TMUX_K3MON 1[7:0] (Table 104), which is 
updated when a consecutive and consistent value is 
detected in the incoming K3 byte for TMUX_CNTDK3[3:0] 
(Table 99) frames  on port 1. Only port 1 inform ation is valid 
in AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RK3M ONM1 (Table 87).
0
9 TMUX_RF3MOND1 Receive F3 (Path U ser Byte) Monitor Delta. This delta bit 
indicates a change in state in TMUX_F3M ON01[7:0] 
(Table 104), which is updated when a consecutive a nd con-
sistent value is detected in the in co ming F3 byte for 
TMUX_CNTDF3[3:0] (Table 99) frames on port 1. Only port 
1 information is valid in AU-4 mode and in STS-1 mode. The 
mask bit is T MUX_RF 3M ONM1 (Table 87).
0

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
82 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW) (continued)
Address Bit Name Function Reset 
Default
0x40007 8 TMUX_RF2MOND1 Receive F2 (Path User Byte) Monitor Delta. This delta b it 
indicates a change in state in TMUX_F2MON01[7:0] 
(Table 104), which is updated when a consecutive and con-
sistent value is detected in the inc oming F2 byte for 
TMUX_CNTDF2[3:0] (Table 99) frames on port 1. Only port 1 
information is valid in AU-4 mode and in STS -1 mode. The 
mask bit is TM UX_RF2MONM1 (Table 87).
0
7 TMUX_RRDIPD1 Recei ve Path RDI (Remote Defect Indication) Monitor 
Delta. This delta bit indicates a change in state in 
TMUX_RDIPMON1[2:0] (Table 104) that o ccurs when a con-
secutive and consistent new value is detected in  the incom-
ing G1[3:1] bits f or TMUX_CNTDRDIP[3:0] (Table 99) frames 
on port 1. The device monitors either G1 bit 3 or G1[3:1] 
depending on TMUX_REPRD I_MODE ( Table 95). Only port 
1 information is valid in AU-4 mode and in STS-1 mode. The 
mask bit is TMUX_RRDIPM1 (Table 87).
0
6 TMUX_RC2MOND1 Receive C2 (Signal Label ) Monitor Delta. This de lt a  bit 
indicates a change in state in TMUX_C2MON1[7:0] 
(Table 104), which is updated when a consecutive and con-
sistent value is detected in the incoming C2 byte for 
TMUX_CNTDC2[3:0] (Table 99) frames  on port 1. Only port 
1 information is valid in AU-4 mode and in STS-1 mode. The 
mask bit is TMUX_RC2M ONM1 (Table 87). 
0
5 TMUX_RTIMPD1 Receive Path Trace I dentifier Mismatch Delta. This  de lt a  
bit in dicates a change in state in the received 16-byt e J 1 
sequence on port 1 if the J1 mode is programm ed to re ceive 
a 16-byte sequence. Only port 1 inform ation  is valid in AU-4 
mode and in STS-1 mode. The mask bit is TMUX_RTIMPM1 
(Table 87).
0
4 TMUX_RNDFE1 Receive New Data Flag Event. T his even t bit  in dicat es  that  
the incoming pointer has t he new data flag enabled, causing 
a jump in the current poi nter location for port 1. Only port 1 
information is valid in AU-4 mode and in STS -1 mode. The 
mask bit is TMUX_RNDF M1 (Table 87).
0
3 TMUX_RDECE1 Receive Pointer Decrement Event. This event bit in dicates 
that a valid incoming pointer decrem ent ind i cation was 
received on por t 1 . Only port 1 inform ation is va lid in AU-4 
mod e and in STS-1 mode. The mask  bit is  TM UX_RDECM1 
(Table 87).
0
2 TMUX_RINCE1 Receive Pointer Increm ent Event.  This  event  bit indic a tes 
that a valid incoming pointer increment indication was 
received on por t 1 . Only port 1 inform ation is va lid in AU-4 
mod e and in STS-1 mode. The mask  bit is  TM UX_RINC M1 
(Table 87).
0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
83Agere Systems Inc.  
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW) (continued)
Address Bit N am e Function Reset 
Default
0x4007 1 TMUX_RPAISD1 Receive Path AIS Delta. This delta bit indicates a change in 
state of  the TMUX_RPAIS1 (Table 92) state bit, which desig-
nates that the port 1 pointer interpret er is in the alarm indica-
tion signal state. Only port 1 information is va lid in AU-4 
mode and in STS-1 mode. The mask bit is T M UX_RPAISM1 
(Table 87).
0
0 TMUX_RLOPD1 Receive Lo ss of Pointer Delta.  This delta bit indi cate s  a 
change in state of the TMUX_RLOP1 (Table 92) state bit, 
which designates that the port 1 po inter interpreter is in the 
loss of pointer state. Only port 1 informat ion is valid in AU-4 
mode. The mask bit is TMUX_RLOPM1 (Table 87).
0
0x40008 15 TMUX_RSFB3D2 Receive P ath Signal Fail BER Algorithm Delta. T his d e lt a  
bit i ndicat es  a c hange of state for the signal fail BER algo-
rithm state bit T MUX_RSFB32  (Table 92) at the path le vel  f or 
port 2. O nly  port 1 infor mation is valid in AU-4 mode and in 
STS-1 m ode. The mask bit is TMUX_RSFB3M2 (Table 87). 
0
14 TMUX_RSDB3D2 Receive Path Signal Degrade BER Algorithm Delta. This 
delta bit indicates a change of state for the signal fail BER 
algorithm state bit T MUX_RSDB32 (Table 92) at   the path 
level for port 2. Only  port 1 information is valid in  AU-4 mode 
and in STS-1 mode.  The m ask bit is TMUX_RHSSD B3M2. 
0
13 TMUX_RUNEQPD2 Receive Pa th Unequipped Delta.  This  delt a  bit indi cate s  
that the curren t value of the received C 2 (signal label) byte, 
TMUX_C2M ON2[7: 0]  (Table 104), has a value 0x00,  indicat-
ing unequipped payload for port 2. Onl y  port 1 information is 
valid in AU-4 mode and in  STS-1 mode.The mask bit is 
TMUX_RUNEQPM2 (Table 87). 
0
12 TMUX_RPLMPD2 Receive Pat h Payload Label  Mismatch Delta. T his event 
bit indicate s   that the current value of the received C2 (signal 
label) byte,  TMUX _C2M ON2[ 7:0], differs from the expected 
C2 value, TMUX_C2EX P2[7:0] (Table 100) for port 2. Only 
port 1 information is valid in AU -4 mode and in STS-1 
mode.The mask  bi t is  TMUX _RP LMPM 2 (Table 87). 
0
11 TMUX_RN1MOND2 Receive N1 Monitor Delta. This delta bit  indicates a change 
in state in TMUX_N1MON2[7:0] (Table 104). The N1 current 
value is  update d when a consecutive and consistent value is 
detected in the incoming N1 byte for TMUX_CNTDN1[ 3:0] 
(Table 99) frames on port 2. Only port 1 inf ormation is vali d in 
AU-4 mode and in STS-1 mo de. The mask bit is 
TMUX_RN1MONM2 (Table 87). 
0
10 TMUX_RK3MOND2 Receive K3 Monitor Delta. This delta bit indicates a change 
in state in TMUX_K3MON 2[7:0] (Table 104), which is 
updated when a consecutive and consistent value is 
detected in the incoming K3 byte for TMUX_CNTDK3[3:0] 
(Table 99) frames on port 2. Only port 1 inf ormation is vali d in 
AU-4 mode and in STS-1 mo de. The mask bit is 
TMUX_RK3M ONM2 (Table 87). 
0

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
84 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW) (continued)
Address Bit Name Functi on Reset 
Default
0x40008 9 TMUX_RF3MOND2 Receive F 3 (Path User Byte) Monitor Delta. T his delta b it indi-
cates a change in st ate in T MUX_F3MON02[7:0] (Table 104), 
which is up dated when a consecutive and consistent value is 
detected in the incoming F3 byte for TMUX_CNTDF3 [3:0] 
(Table 99) f rames  on port 2. Only  port 1 informat ion is valid in 
AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RF3MON M2 (Table 87). 
0
8 TMUX_RF2MOND2 Receive F2 (Path User Byte) Monitor Delta. T his delta b it indi-
cates a change in st ate in T MUX_F2MON02[7:0] (Table 104), 
which is up dated when a consecutive and consistent value is 
detected in the incoming F2 byte for TMUX_CNTDF2 [3:0] 
(Table 99) f rames  on port 2. Only  port 1 informat ion is valid in 
AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RF2MON M2 (Table 87). 
0
7 TMUX_RRDIPD2 Receive Path RD I (Remote Defect Ind ica tion) M onitor  Delta. 
This delta bit indicates a change in state in 
TMUX_RDIPMON2[2:0] (Table 104) which occurs when a con-
secutive and consistent new value is detected in the incoming 
G1[3: 1] bi ts for TMUX_CNTDRDIP [3:0]  (Table 99) frames on 
po rt  2. The device mon it or s either  G1 bit 3 o r G1 [3:1] depending 
on TMUX_REPRDI_MODE  (Table 95). Only port 1 information 
is valid in AU-4 mode and in STS-1 mode. The mask  bit is 
TMUX_RRDIPM2 (Table 87). 
0
6 TMUX_RC2MOND2 Receive C2 (Signal Label) Monitor Delta. This delta b it indi-
cates a change in st ate in TMUX_C2MON2[7:0] (Table 104), 
which is up dated when a consecutive and consistent value is 
de te cted in th e incomin g C2 byte f or TMUX_CNTDC2[3:0]  
(Table 99) f rames  on port 2. Only  port 1 informat ion is valid in 
AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RC2MONM2 (Table 87). 
0
5 TMUX_RTIMPD2 Receive Path Trace Identifier Mismatch Delta. T h is  delta b it 
indicates a change in state in t he rec eived 16-b yte J1 sequence 
for port 2 if the  J1 mode is programmed to receive a   16-byte 
sequence. Only port 1 information is valid in AU-4 mode and in 
STS-1 mode. T he mask bit is TMUX_RTIMPM2 (Table 87).  
0
4 TMUX_RNDFE2 Receive New Data Flag Event. T his event bit indicates that the 
incoming pointer has the new data flag enabled for por t 2,  caus-
ing a jump in the current pointer location. Only port 1 inf ormation 
is valid in AU-4 mode and in STS-1 mode. The mask  bit is 
TMUX_RNDFM2 (Table 87). 
0
3 TMUX_RDECE2 Receive Pointer Decrement Event. This event bit indicates 
that a val id incom ing pointer de c rement indication was rece ived 
on p ort 2. Only port 1 informatio n i s valid in AU-4 mode and in 
STS-1 mode. The mask bit is TMUX_RDECM2 (Table 87). How-
ever,  incre ment and decrement event indica tion should be 
ignored during loss-of-pointer (LOP) condition.
0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
85Agere Systems Inc.  
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW) (continued)
Address Bit Name Fun ction Reset 
Default
0x40008 2 TMUX_RINCE2 Receive Poi nter Increment Event. This even t bit  i ndicat es 
that a valid incoming pointer increment indication was  
received on  port 2. Only port 1 information is valid in  AU-4 
mode and in STS-1 mode. The mask bit is TMUX _RINCM2 
(Table 87). Ho wever, increment and decrement e vent indica-
tion should be ignored during loss-of-pointer (L OP ) condi-
tion.
0
1 TMUX_RPAISD2 Recei ve Path AIS Delta. This delta bit indicates a change in 
state of  the TMUX_RPAIS2 (Table 92) state bit, which desig-
nates that the port 2 po inter  interpreter is  in the alarm indica-
tion signal state. Only port 1 informat ion is valid in AU-4 
mode a nd in STS-1 m ode. The mask bit is TMUX_ RPAISM2 
(Table 87). 
0
0 TMUX_RLOPD2 Receive Loss of Pointer Delta. Thi s delta bit indicates a 
change in state of the TMUX_RLOP2 (Table 92) state bit, 
which designates that the port 2 pointer interpreter is in the 
loss of pointer state. Only por t 1 inform at ion is valid in AU-4 
mode. The mask bit is  T MUX_RLOPM2 (Table 87). 
0
0x40009 15 TMUX_RSFB3D3 Receive Path Signal Fail BER Algorithm Delta.  This  delta 
bit i ndicat es  a c hange of st ate for the signal fail BER algo-
rithm state bit TMUX_RSFB32 (Table 92) at the path le vel  for 
port 3. O nly  port 1 infor mation is valid in AU-4 mode and in 
STS-1 m ode. The mask bit is TM UX_RSFB3M3 (Table 87).
0
14 TMUX_RSDB3D3 Receive Path Signal Degrade BER Algorithm Delta. This 
delta bit indicates a change of state for the signal fail  BER 
algorithm state bit T MUX_RSDB32 (Table 92) at   the path 
level for port 3. Only port 1 information is valid in AU-4 mode  
and in STS-1 mode. The mask bit is  TMUX_RSD B3M3 
(Table 87).
0
13 TMUX_RUNEQPE3 Receive Path  Un equ ipped Event. This event bit indicates 
that the curren t value of the received C2 (signal label) byte, 
TMUX_C2M ON3[7: 0]  (Table 104), h as a value 0x00,   indicat-
ing unequipped payload for port 3. Only port 1  information is 
valid in AU-4 mode and in STS-1 mode. The mask bit  is 
TMUX_RUNEQPM3 (Table 87). 
0
12 TMUX_RPLMPE3 Receive P ath Payload Label  Mismatch Event.  This event 
bit indicate s   that the current value of the received C2 (signal 
label) byte,  TMUX _C2M ON3[ 7:0], differs f rom the expected 
C2 value, TMUX_C2EX P3[7:0] (Table 100) for port 3. Only 
port 1 informa tion is valid in AU- 4 mode and in STS-1 mode. 
The mask bit  i s TMUX_RPLMPM3 (Table 87).
0

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
86 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW) (continued)
Address Bit N am e Function Re set 
Default
0x40009 11 TMUX_RN1MOND3 Receive N1 Monitor Delta. This delta bit indicates a change in 
state in TMUX_N1MON3[7:0] (Table 104). The N1 current 
value is updated when a consecutive an d consistent value  is 
detected in the incoming N1 byte for TMUX_CNTDN1[3:0] 
(Table 99) frames on po rt 3. Only port 1 information is valid in 
AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RN1MONM3 (Table 87).
0
10 TMUX_RK3MOND3 Receive K3 Monitor Delta. This delta bit  indicates a change in 
state in TMUX_K3MON3[7:0] (Table 104), whi ch is updated 
when a consecutive and consistent value is detected in the 
incoming K3 byte for TMUX_CNTDK3[3 :0] (Table 99) frames 
on port 2. Only  port 1 i nformat ion is val id in AU-4 mode and in 
STS-1 mode. The mask bit is TMUX_RK 3M ONM3 (Table 87).
0
9TMUX_RF3MOND3Receive F3 (Path User Byte) Monitor Delta. This delta bit 
indicates a change in state in TMUX _F3M ON03[7:0] 
(Table 104), which is updated when  a consec utive and consis-
tent  value is detec ted in the incoming F3 byte for 
TMUX_CNTDF3[3:0] (Table 99) frames on port 3. Only port 1 
information is valid in AU-4 mode and in S TS-1 mode. The 
mask bit is T MU X_R F3M ONM 3 (Table 87). 
0
8TMUX_RF2MOND3Receive F2 (Path User Byte) Monitor Delta. This delta bit 
indicates a change in state in TMUX _F2M ON03[7:0] 
(Table 104), which is updated when  a consec utive and consis-
tent  value is detec ted in the incoming F2 byte for 
TMUX_CNTDF2[3:0] (Table 99) frames on port 3. Only port 1 
information is valid in AU-4 mode and in S TS-1 mode. The 
mask bit is T MU X_R F2M ONM 3 (Table 87). 
0
7 TMUX_RDIPD3 Receive Path RDI  (Remote Defect Indication) Monitor 
Delta. This delta bit indicates a change in state in 
TMUX_RDIP MO N3[2:0] (Table 104) which occurs when a con-
secutive and c onsistent new value is de tected in the incomin g 
G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 99) frames o n 
port 3. The de vice monitors eith e r G1 bit 3 or G1[3:1] depend-
ing on TMUX_REPRDI_MODE (Table 95).  O nly port 1 informa-
tion is valid in AU-4 m ode and in STS-1 mode. The mask bit is 
TMUX_RRDIPM3 (Table 87).  
0
6 TMUX_RC2MOND3 Receive C2 (Signal Label) Monitor Delta. Thi s delta bit indi-
cates  a c hange in state in TMUX_C2MON3[7:0] (Table 104), 
which is updated when a consecutive  and consistent value is 
detected in the incoming C2 byte for TMUX_CNTDC2[3:0] 
(Table 99) frames on po rt 3. Only port 1 information is valid in 
AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RC2MONM3 (Table 87). 
0
5 TMUX_RTIMPD3 Receive Path Trace Identifier Mismatch Delta. This delta bit 
indicates a c hange in state in  the received 16-b yte J1 sequence 
for port 3 if the J1 m ode is programmed to rece i v e  a 16-byte 
sequence. Only port 1 information is  val id in AU-4  mode and in 
STS-1 mode. The ma sk bit is TMUX_RTIMPM3 (Table 87). 
0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
87Agere Systems Inc.  
8 TMUX Registers (continued)
Tabl e 8 3. TMUX_RPOH[1 —3]_DLT,  Delta/ Event (COR/COW) (continued)
Note: In Table 84, the mask bits  are set to suppress an interrupt when the corresponding event has occurred or 
change in state has  taken place.
Table 84. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address Bit Name Fun ction Reset 
Default
0x40009 4 TMUX_RNDFE3 Recei ve New Data Flag Event. This event bit indicates that the 
incoming pointer has the n ew data flag  enabled, causing a  jump 
in the current pointer location for port 3. Only port 1 informat ion 
is valid in AU-4 mode and in STS-1 mode. The mask bit is 
TMUX_RNDFM3 (Table 87).  
0
3 TMUX_RDECE3 Receive Pointer  Dec rem ent Event. This event bit indicates 
that a valid incoming pointer decrement  indication was received 
on port 3. Only port 1 information is valid in AU-4 mode and in 
STS-1 m ode.  The mask bit  is  TM UX_RDECM3 (Table 87). 
0
2 TMUX_RINCE3 Receive Po in ter Increment Event.  This event bit indicates that 
a valid inc oming pointer increment indication was received on 
port 3. O nly  port 1 inform ation is valid i n AU-4 mode a nd in 
STS-1 m ode.  The mask bit  is  TM UX_RINCM3 (Table 87). 
0
1 TMUX_RPAISD3 Receive P ath AIS Delta. T h is  delta bit i n dicates a change in 
state of the TMUX_RPAIS3 (Table 92) state bit, which desig-
nates that the port 3 pointer interpreter is in the alarm indication 
signal state. Only port 1 inf ormation is valid in AU-4 mode and in 
STS-1 m ode. The mask   bit is TMUX_RPA ISM3 (Table 87). 
0
0 TMUX_RLOPD3 Receive Loss of Pointer Delta.  This  del ta bit indicates  a 
change in state of the TMUX_RLOP3 (Table 92) state bit, which 
designates that the port  3 point er interpreter is in the loss of 
pointer state. Only  port 1 information is valid in AU-4 mode. The 
mask bit is TMUX_RLOP M3 (Table 87). 
0
Address Bit N ame Function R eset 
Default
0x4000A 15:7 —Reserved. 0x000
6:4 TMUX_TLSPARM[3:1] Tran sm it Low-speed  Parity Error Mask (Input Port Nu m -
ber). See Table 80 for description. 1
3TMUX_TPOAC_PMTransmit Path  O verhead Access Channel (TPOAC) Par-
ity Error Mask. See  Table 80 for description. 1
2TMUX_TTOAC_PMT ransmit Transport Overhead Access Channel (TT O AC) 
Parity Error Mask. See Table 80 for description. 1
1 TMUX_THSILOFM Transmit High-speed Input Loss of Fram e Ma sk. See 
Table 80 for description. 1
0TMUX_THSILOCMTran sm it High-speed Input Loss of Cl ock Mask. See 
Table 80 for description. 1

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
88 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Note: In Table 85, the mask bits  are set to suppress an interrupt w hen the corresponding event  has occurred or 
change in state has  taken place.
Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No  Mask = 0)
Note: In Table 86, the mask bits  are set to suppress an interrupt w hen the corresponding event  has occurred or 
change in state has  taken place.
Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address Bit Name Function Reset 
Default
0x4000B 15:6 —Reserved. 0x000
5 TMUX_RPSLOFM Receive Protection High-speed Loss o f Frame Mask. See 
Table 81 for description. 1
4 TMUX_RPSOOFM Recei ve Protection High -speed Out of Frame Mask. See 
Table 81 for description. 1
3 TMUX_RPSILOCM Receive Protection High-speed Loss of I nput Clock M ask.  
See Table 81 for description. 1
2 TMUX_RPSB2M Receive Protection High -speed B2 Error Mask. See 
Table 81 for description. 1
1 TMUX_RPSLREIM Receive Protection High-speed Line REI Mask. See 
Table 81 for description. 1
Address Bit Name Function Reset 
Default
0x4000C 15 —Reserved. 0
14 TMUX_RS1BABM Receive S1 Babble Mask. See Table 82 for description. 1
13 TMUX_RS1MONM Receive S1 Monitor Mask. See Table 82 for description. 1
12 TMUX_RLRDIMONM Recei v e Line RDI Monitor Mask.  See  Table 82 for descrip-
tion. 1
11 TMUX_RLAISMONM Receive Line AIS Monitor Mask. See Table 82 for descrip-
tion. 1
10 TMUX_RK2MONM Receive K2 Monitor Mask. See Table 82 for description. 1
9 TMUX_RAPSBABM Receive APS Babble Mask. See Table 82 for description. 1
8 TMUX_RAPSMONM R eceive APS Monitor Mask.  S ee Table 82 for description. 1
7TMUX_RF1MONMReceive F1 Mo nitor Mask.  See Table 82 for description. 1
6 TMUX_RTIMSM Receive Section Trace Identifier Mismatch Mask. See 
Table 82 for description. 1
5 TMUX_RHSSFM Receive High-spee d Signal Fail  BER  Algorithm M ask. 
See Table 82 for description. 1
4 TMUX_RHSSDM Receive High-speed Signal Degrade BER Algorithm 
Mask. See Table 82 for description. 1
3 TMUX_RHSLOSM Receive High-speed Loss of Signal  Mask. See Table 82 
for description. 1
2 TMUX_RHSLOFM Receive High-speed Loss of Frame Mask. S ee Table 82 
for description. 1
1 TMUX_RHSOOFM Receive High-speed Out of Frame Mask. See Table 82 for 
description. 1
0 TMUX_RHSILOCM Receive High-speed Loss of Input Clock Mask. See 
Table 82 for description. 1

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
89Agere Systems Inc.  
8 TMUX Registers (continued)
Note: In Table 87, the mask bits  are set to suppress an interrupt when the corresponding event has occurred or 
change in state has  taken place.
Tabl e  87. TMUX_RPOH [1—3]_MSK, Mask Bits fo r Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Address Bit Name Function Reset 
Default
0x4000D 15 TMUX_RSFB3M1 Receive Path  Signal Fail BER Algorithm Mask. See Table 83 
fo r descri ption. 1
14 TMUX_RSDB3M1 Receive Path Signal Degrade BER Algorithm Mask. S ee 
Table 83 for description. 1
13 TMUX_RUNEQPM1 Receive Pa th Unequipped Mask. See Table 83 for description.  1
12 TMUX_RPLMPM1 Receive Path Payload Label Mismatch Mask. See Table 83 
fo r descri ption. 1
11 TMUX_RN1MONM1 Receive N1 Monitor Mask. See Table 83 for description. 1
10 TMUX_RK3MONM1 Receive K3 Monitor Mask. See Table 83 for description. 1
9 TMUX_RF3MONM1 Receive F3  (Path User Byte) Monitor Mask. See Table 83 for 
description. 1
8 TMUX_RF2MONM1 Receive F2  (Path User Byte) Monitor Mask. See Table 83 for 
description. 1
7 TMUX_RRDIPM1 Receive P ath RDI (Remote Defect Indication) Monitor Mask. 
See Table 83 for description. 1
6 TMUX_RC2MONM1 Receive C2 (Signal Label) Monitor Mask. See Table 83 for 
description. 1
5 TMUX_RTIMPM1 Receive Path Trace Identifier M ismatch Mask. See  Table 83 
fo r descri ption. 1
4 TMUX_RNDFM1 Receive New Data Flag Mask.  See Table 83 for description. 1
3 TMUX_RDECM1 Rece ive Pointer De crem ent Mask. See Table 83 for descrip-
tion. 1
2 TMUX_RINCM1 Receive Pointer Increment Mask. S ee Table 83 for descrip-
tion. 1
1 TMUX_RPAISM1 Receive Path AIS Mas k. See Table 83 for description. 1
0 TMUX_RLOPM1 Receive Loss of Pointer Mask. See Table 83 for description. 1
0x4000E 15 TMUX_RSFB3M2 Receive Path  Signal Fail BER Algorithm Mask. See  Table 83 
fo r descri ption. 1
14 TMUX_RSDB3M2 Receive Path Signal Degrade BER Algorithm Mask. S ee 
Table 83 for description. 1
13 TMUX_RUNEQPM2 Receive P ath Unequipped Mask. See Table 83 for description. 1
12 TMUX_RPLMPM2 Receive Path Payload Label Mismatch Mask. See Table 83 
fo r descri ption. 1
11 TMUX_RN1MONM2 Receive N1 Monitor Mask. See Table 83 for description. 1
10 TMUX_RK3MONM2 Receive K3 Monitor Mask. See Table 83 for description. 1
9 TMUX_RF3MONM2 Receive F3  (Path User Byte) Monitor Mask. See Table 83 for 
description. 1
8 TMUX_RF2MONM2 Receive F2  (Path User Byte) Monitor Mask. See Table 83 for 
description. 1
7 TMUX_RRDIPM2 Receive P ath RDI (Remote Defect Indication) Monitor Mask. 
See Table 83 for description. 1

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
90 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Note: In Table 87, the mask bits  are set to suppress an interrupt w hen the corresponding event  has occurred or 
change in state has  taken place.
Table 87. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) (continued)
Address Bit Name Function Rese t 
Default
0x4000E 6 TMUX_RC2MONM2 Receive C2 (Signal Label) Monitor Mask.  See Table 83 for 
description. 1
5 TMUX_RTIMPM2 Receive Path Trace Identifier Mismatch Mask. See 
Table 83 for description. 1
4 TMUX_RNDFM2 Receive New Data Flag Mask. See Table 83 for description. 1
3 TMUX_RDECM2 Rec eive Pointer Decrement M ask. See Table 83 for 
description. 1
2 TMUX_RINCM2 Receive Poin ter Increment M ask. See Table 83 for descrip-
tion. 1
1 TMUX_RPAISM2 Receive Path AIS Mask. See Table 83 for description. 1
0 TMUX_RLOPM2 Receive Loss of P ointer Mask. S ee Table 83 for description. 1
0x4000F 15 TMUX_RSFB3M3 Receive Path Signal Fail BER Algorithm Mask. S ee 
Table 83 for description. 1
14 TMUX_RSDB3M3 Receive Path Signal De grad e BER Algorithm Mask. See 
Table 83 for description. 1
13 TMUX_RUNEQPM3 Receive Path Unequipped Mask. See Table 83 for descrip-
tion.  1
12 TMUX_RPLMPM3 Receive P ath Pa yload Label Mismatch Mask. See Table 83 
for description. 1
11 TMUX_RN1MONM3 Rec eive N1 Monitor Mask. See Table 83 for description. 1
10 TMUX_RK3MONM3 Receive K3 Mon itor Mask. See Table 83 for description. 1
9 TMUX_RF3MONM3 Receive F3 (Path User Byte) Monitor Mask. See Table 83 
for description. 1
8 TMUX_RF2MONM3 Receive F2 (Path User Byte) Monitor Mask. See Table 83 
for description. 1
7 TMUX_RRDIPM3 Rec eive Path RDI (Remo te Defect In dicati on) Monitor 
Mask. See Table 83 for description. 1
6 TMUX_RC2MONM3 Receive C2 (Signal Label) Monitor Mask. S ee Ta ble 83 for 
description. 1
5 TMUX_RTIMPM3 Receive Path Trace Identifier Mismatch Mask. See 
Table 83 for description. 1
4 TMUX_RNDFM3 Receive New Data Flag Mask. See Table 83 for descript ion. 1
3 TMUX_RDECM3 Rec eive Pointer Decrement M ask. See Table 83 for 
description. 1
2 TMUX_RINCM3 Receive Poin ter Increment M ask. Se e Table 83 for descrip-
tion. 1
1 TMUX_RPAISM3 Receive Path AIS Mask. See Table 83 for description . 1
0 TMUX_RLOPM3 Receive Loss of P ointer Mask. S ee Table 83 for desc ription. 1

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
91Agere Systems Inc.  
8 TMUX Registers (continued)
Note: In Table 88, the mask bits  are set to suppress an interrupt when the corresponding event has occurred or 
change in state has  taken place.
Table 88. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
Note: When state bits are set in Table 89,  the corresponding function has occurred.
Table 89. TMUX_TX_S TATE,  State Parameters (RO)
Note: When state bits are set in Table 90,  the corresponding function has occurred.
Table 90. T MUX_RPS_STATE, State and  Value Parameters (RO)
Address Bit Name Function Reset 
Default
0x40011 15:8 —Reserved. 0x000
7 TMUX_RHSSF_APSM Rec e ive  Hi gh - spe ed Signa l  Fail  BER Algo rithm  
APSINT Mask. See Table 82 for description. 1
6 TMUX_RHSSD_APSM Receive High-speed Signal Degrade BER Algo-
rithm APS INT Mask. See Table 82 for description.  1
5 TMUX_RAPSMON_APSM Receive APS Monitor APSINT Mask. See Table 83 
for description. 1
4 TMUX_RLAISMON_APSM Recei ve Line AIS Monitor APSINT Mask. See 
Table 82 for description. 1
3 TMUX_RHSLOS_APSM Receive High-sp e ed Loss of Signa l APSINT Mask. 
See Table 82 for description. 1
2 TMUX_RHSLOF_APSM Receiv e High-speed Loss of Frame APSINT Mask. 
See Table 82 for description.  1
1 TMUX_RHSOOF_APSM Receive High-spe ed Out of Frame AP SIN T Mask. 
See Table 82 for description. 1
0 TMUX_RHSILOC_APSM R eceive High-spe ed L oss o f  Inpu t  Clock APSI NT 
Mask. See Table 82 for description.  1
Address Bit Name Function Reset 
Default
0x40012 15:2 —Reserved. 0x000
1TMUX_THSILOFTr ansmi t  High-speed Input Loss of Frame S tate. See 
Table 80 for description. 0
0TMUX_THSILOCTr ansmi t High-speed Input Loss of Clo ck State. See 
Table 80 for description. 0
Address Bit Name Function Reset 
Default
0x40013 15:6 —Reserved. 0x000
5 TMUX_RPSLOF Receive Protection High-speed Loss of Frame State. See 
Table 81 for description. 0
4TMUX_RPSOOFReceive Protection High-speed Out of Frame State . See 
Table 81 for description. 0
3 TMUX_RPSILOC Receive Pr otection High-speed Loss of Input Clock State. 
See Table 81 for description. 0
2:0 —Reserved. 000

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
92 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Note: When state bits are set in Table 91,  the corresponding f unct ion has occurred.
Table 91. TMUX_RHS_STATE, State and Value Parameters (RO)
Note: When state bits are set in Table 92,  the corresponding f unct ion has occurred.
Address Bit Nam e Function Reset 
Default
0x40014 15:13 —Reserved. 000
12 TMUX_RLRDIMON Receive Line RDI M o nit or St ate. See  Table 82 for 
description. 0
11 TMUX_RLAISMON Receive Line AI S  M o nitor State.  See Table 82 for 
description. 0
10:8 —Reserved. 000
7 TMUX_RHSLOSEXTI Reflects LOSEXT Pin (AE5) Input. —
6TMUX_RTIMSReflects Section-Level Trace Identifier Mismatch State. —
5 TMUX_RHSSF Re ceive High - speed Sign a l  Fail  BER Algo rithm  S ta t e. 
See Table 82 for description.  0
4 TMUX_RHSSD Receive High-speed Signal Degrade BER Algor it hm 
State . See Table 82 for description.  0
3 TMUX_RHSLOS Receive High-speed Loss of Signal State. See Table 82 
for description.  0
2 TMUX_RHSLOF Receive High-speed Loss of Frame State. See Table 82 
for description.  0
1 TMUX_RHSOOF Receive High-speed Out of Frame State. See Table 82 
for description. 0
0 TMUX_RHSILOC Receive High-speed Loss of Input Clock State. See 
Table 82 for description. 0
Tabl e  92. TMUX_RPOH [1—3]_STATE, S t ate an d Value Para meters (RO )
Address Bit Nam e Function R eset 
Default
0x40015 15 TMUX_RSFB31 Receive Path Sig nal  Fail BER Algorithm State. 
See Table 83 for description. 0
14 TMUX_RSDB31 Receive Path Signal Degrade BER Algorithm 
State . See Table 83 for description. 0
13 TMUX_RUNEQP1 Receive Path Unequipped State. See Table 83 
for description. 0
12 TMUX_RPLMP1 Receive Path Payload Label Mismatch State. 
See Table 83 for description.  0
11:6 —Reserved. 0x00
5 TMUX_RTIMP1 Receive Path Trace Identifier Mismatch State. 
See Table 83 for description. 0
4:2 —Reserved. 000
1 TMUX_RPAIS1 Receive Path AI S State . See Table 83 for descrip-
tion. 0
0TMUX_RLOP1Receive Loss of Pointer State. S ee Table 83 for 
description. 0

Prelim inary Data Sheet TMXF28155 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
93Agere Systems Inc.  
Address Bit Name Function Reset 
Default
0x40016 15 TMUX_RSFB32 R ecei ve Path S ignal Fail BER Algorithm State. 
See Table 83 for description. 0
14 TMUX_RSDB32 Recei ve Path Signal Degrade BER A lg or ithm  
State . S ee Table 83 for description. 0
13 TMUX_RUNEQP2 Receive Path Unequipped State. S ee Table 83 
for description. 0
12 TMUX_RPLMP2 Receive Path Payload Label Mismatch State. 
See Table 83 for description. 0
11:6 —Reserved. 0x000
5 TMUX_RTIMP2 Receive Path Trace Identifier Mismatch State . 
See Table 83 for description. 0
4—Reserved. 0
3:2 TMUX_CONCAT_S TATE2[1:0]  C oncatenation Po in ter State M achi ne S ta t e. 
State bits indicate th e state of the c oncatenation 
stat e machine (LOPC = 10,  AISC = 01, 
C ONC = 00) for port 2.   These values only have 
meaning in the AU-4 mode with the 
TMUX_RCONCATMODE bit (Table 95) set to the 
con ca tenation mode (1).
00
1 TMUX_RPAIS2 Recei ve Path AIS S t ate. See Table 83 for descrip-
tion .  0
0TMUX_RLOP2R eceive Loss of Pointer State. See Table 83 for 
description.  0
0x40017 15 TMUX_RSFB33 R ecei ve Path S ignal Fail BER Algorithm State. 
See Table 83 for description. 0
14 TMUX_RSDB33 Recei ve Path Signal Degrade BER A lg or ithm  
State . S ee Table 83 for description. 0
13 TMUX_RUNEQP3 Receive Path Unequipped State. S ee Table 83 
for description.  0
12 TMUX_RPLMP3 Receive Path Payload Label Mismatch State. 
See Table 83 for description. 0
11:6 —Reserved. 0x000
5 TMUX_RTIMP3 Receive Path Trace Identifier Mismatch State . 
See Table 83 for description. 0
4—Reserved. 0
3:2 TMUX_CONCAT_S TATE3[1:0]  C oncatenation Po in ter State M achi ne S ta t e. 
State bits indicate th e state of the c oncatenation 
stat e machine (LOPC = 10,  AISC = 01, 
C ONC = 00) for port 3.   These values only have 
meaning in the AU-4 mode and the 
TMUX_RCONCATMODE bit (Table 95) set to the 
con ca tenation mode (1).
00
1 TMUX_RPAIS3 Recei ve Path AIS S t ate. See Table 83 for descrip-
tion. 0
0TMUX_RLOP3R eceive Loss of Pointer State. See Table 83 for 
description. 0
Ta ble 92. TMUX_R POH[1 —3]_ STATE, State and Value P ar ameters (RO) (continued)

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

94 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RHS_CTL, Receive High-speed Control Parameter s (R/W)

Address Bit N ame Function Rese t Default

0x40019 15:4 —Reserved. 0x000

3 TMUX_LOSEXT_LEVEL Controls External LOSEXT Polarity.

0 = active-low. 1 = active-high. 0

2 TMUX_RPSMUXSEL1 Receive Protection Switch Control. Control bit,

when set to a logic 1 , causes the receive prote c -

tion switch data and clock input s t o be sele c ted;

otherwise, the normal receive high-speed data

input is selec ted.

1 TMUX_THS2RHSLB Transmit High-speed to Receive High-speed

Loopback Control. Control bit, when set to a

logic 1, causes the transmit out put S TS-3/STM- 1

(AU-4) signal to be looped bac k to the receive

input; ot herwise, the loopback is d i sabled.

0 TMUX_RHSDSCR Receive High-speed Descram ble Enable . Con-

trol bit, when set to a logic 1, c auses the input

STS-3/STM-1 (AU-4) signal to be descrambled;

otherwise, the signal is not descr ambled.

Table 94. TMUX_RLS_BITBLK_CT L, Receive Low-speed Control Parameters (R/W)

Address Bit Name Function Reset Default

0x4001A 15:9 —Reserved. 0x00

8:7 TMUX_RCV_SS_EXP[1:0] Expected Receive P ointer Size Bits V alue.

Expected value of incoming pointer SS bits. 00

6 TMUX_RCV_SS_ENB Receive Size Bits Enable. Control bit, when set to

a logic 0, causes the received size bits to be

ignored by the pointer interpreter; otherwise, the

received size bits must equal the expected size bits

or the received pointer value will be invalid.

5—Reserved. 0

4 TMUX_BITBLKG1 Receive Bit/Bl ock Err or Count Control. Control

bit, when set to a logic 0, causes the receive error

counter to count bit errors; otherwise, count bloc k

errors (a block equals one frame).

3 TMUX_BITBLKM1 Receive Bi t/Block E rror Co unt Control. Control

bit, when set to a logic 0, causes the receive error

counter to count bit errors; otherwise, count bloc k

errors (a block equals one frame).

2 TMUX_BITBLKB3 Receive Bit/Bl ock Err or Count Contro l. Control

bit, when set to a logic 0, causes the receive error

counter to count bit errors; otherwise, count bloc k

errors (a block equals one frame).

1 TMUX_BITBLKB2 Receive Bit/Bl ock Err or Count Contro l. Control

bit, when set to a logic 0, causes the receive error

counter to count bit errors; otherwise, count bloc k

errors (a block equals one frame).

0 TMUX_BITBLKB1 Receive Bit/ Block Error Count Control. Control

bit, when s et to a logi c 0, causes the receive error

counter to count bit errors; ot herwise , count b l ock

errors (a bl ock equ als one frame).

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

95Agere Systems Inc.

8 TMUX Registers (continued)

Table 95. TMUX_RLS_MODE_CTL, Receive Low-speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001B 15:14 —Reserved. 00

13 TMUX_RPAIS_INS Receive F orce Path AIS Inserti on. Control bit, when

set to a logic 1, causes the recei ve low-speed signal to

carry PAIS as well as asserting all AUTO_AIS[1—3]

(pins AC6, AE6, and AD6) (Table 3) outputs.

12 TMUX_8ORMAJORITY Receive Control Bit for Poi nter Justifications. Con-

trol bit, when set to a logi c 1, causes the pointer inter-

p re ter t o accept an increme nt or decrement only if 8 out

of 10 bits are correct; otherwise, i t will accept an incre-

ment or decrement bas ed on majorit y vote only.

11 TMUX_SDB1B2SEL Receive Signal Degrade Algorithm Input Selection.

Contro l bi t, when set to a logic 1 , causes the B2 errors

to contr ibute to the s ignal degrade calculation; other-

wise, the B1 error count is used.

10 TMUX_SFB1B2SEL Receive Si gn al Fail Algorithm Input S el ection. Con-

trol bit, when set to a logic, causes the B2 errors to con-

tribute to the signal degrade calculation; otherwise, the

B1 error count is used.

9:7 TMUX_J1MONMODE[2:0] Receive J 1 Monitor Mo de. There are si x modes, as

defined in J1 monitor on page 377. 000

6:4 TMUX_J0MONMODE[2:0] Receive J 0 Monitor Mo de. There are si x modes, as

defi ned in Section 17.5.5 J0 Monitor on page 370. 000

3 TMUX_S1MODE4 R eceive S1 Mon itor Mode. Control bit, when set to a

logic 1, causes the most significant nibble of the S1 byte

to be monitored; otherwise, the entire S1 byte is moni-

tored.

2 TMUX_RLSPAROEG Receive Low-speed Parity Odd or Even Gen eration.

Control bit , when set to a logic 1, forces the output parity

bit to be even; otherwise, the parity is odd.

1 TMUX_RCONCATMODE Receive Concatenation Mode. Control bit, when set to

a logic 1, c auses the input pointer interpreter to operate

in concatenati on mode. This mode is most likely used in

AU-4 m ode; otherwise, th ree independent pointers are

expected.

0 TMUX_REPRDI_MODE Receive Enhanced Path RDI Mode. Control bit, when

set to a logic 1, causes the receive path RDI monitor to

monitor the enhanced (3-bit found in G1[3:1]) valu e of

path RDI; otherwise, a 1-bit v al ue (G1[3]) is monitored.

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

96 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001C 15 TMUX_R_M1_BIT7 Re ceive M1 MSB Mode. Control bit, when set to a logic

1, causes the most sign ificant bit in the M1 byte t o be

ignored for line REI accumulation; otherwise, the MSB is

included.

14 TMUX_RSDB3_AISINH Rece ive B3 Signal Degrade AIS Inhibit. Control bit,

when set to a logic 1, inhibit the associ ated alar m from

causing the assertion of t he AUTO_AIS o utput; other-

wise, the a ssociated failure causes assertio n of the cor-

responding AUTO_AIS output signal.

13 TMUX_RSFB3_AISINH Receive B3 Signal Fail AIS Inhibit. Control bit, when

set to a logic 1, inhibit the associated alarm from causing

the assertion of the AUTO_ AIS output; other wise, t he

associated failure causes assertion of the corresponding

AUTO_AIS output signal.

12:10 TMUX_RTIMP_AISINH[3:1] Receive Path Trace Identifier Mismatch AIS Inhibit

Bits. Control bits, when set to a logic 1, inhibit the asso-

ciated alarm from causing the assertion of the

AUTO_AIS output ; otherwise, the associated failure

causes assertion of the corresponding A UTO_AIS output

signal.

9 TMUX_RUNEQP_AISINH Receive Path Unequip AIS In hi bi t. Control bit, when

set to a logic 1, inhibit the associated alarm from causing

the assertion of the AUTO_ AIS output; other wise, t he

associated failure causes assertion of the corresponding

AUTO_AIS output signal.

8 TMUX_RPLMP_AISINH Receive Path Payload Label Mismatch AIS Inhibit.

Control bit, when set to a logic 1, inhibit the associated

alarm from c aus ing the assertion of the AUTO_ AIS out-

put; otherwise, the associated failure causes assertion of

the corresponding AUTO_A IS output signal.

7 TMUX_RHSSD_AISINH Receive High-speed Signal Degrade AIS Inhibit. Con-

trol bits, w hen s et to a l ogic 1, inhibit th e associate d

alarm from causing AIS generation; otherwise, the asso-

ciated failure causes AIS generation on a ll STS-1/AU-3

outputs as we ll as the asser tion of AUTO_AIS out puts.

6 TMUX_RHSSF_AISINH Receive High-speed Signal Fail AIS Inhibit. Control

bits, w hen set to a logic 1, inhibit the associated alarm

from causing AIS generation; otherwise, t he associated

failure causes AIS gen eration o n all STS-1/AU- 3 outputs

as well as the asse r tion of AUTO_AIS out puts.

5 TMUX_RPAISLOP_AISINH Rec ei v e P a t h AIS or LOP AIS Inhibit . Control bits,

when set to a logic 1, inhibit the associ ated alar m from

causing AIS generation; otherwise, the associated failure

causes AIS generation on all STS-1/AU-3 outputs as well

as the assertion of AUTO_AIS outp uts.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

97Agere Systems Inc.

8 TMUX Registers (continued)

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Contro l Param eters (R/ W) (continued)

Table 97. TMUX _LOSDETCNT, Re ceive Low-speed Control Parameters (R/W)

Address Bit Name Function Res et

Default

0x4001C 4 TMUX_RLAISMON_AISINH Receive Line AIS Monitor AIS Inhibit. Control bit,

when set to a logic 1, inhibits the associated alarm

from causing AIS generation; otherwise, the associ-

ated failure causes AIS generation on all STS-1/AU-3

outputs as well as the assertion of AUTO_AIS out-

puts.

3TMUX_RLOF_AISINHReceive Loss-of-Frame AIS Inhibit. Control bit,

when set to a logic 1, inhibits the associated alarm

from causing AIS generation; otherwise, the associ-

ated failure causes AIS generation on all STS-1/AU-3

outputs as well as the assertion of AUTO_AIS out-

puts.

2 TMUX_ROOF_AISINH Receive High-speed Out-of-Frame A IS In hibit.

Control bit, when set to a logic 1, inhibits the associ-

ated alarm from causing AIS generation; otherwis e,

the associated failure causes AIS generation on all

STS-1/AU-3 outputs as well as the assertion of

AUTO _AIS out puts.

1 TMUX_RHSLOS_AISINH Receive High-speed Loss-of-Signal AIS Inh ibit.

Control bit, when set to a logic 1, inhibits the associ-

ated alarm from causing AIS generation; otherwis e,

the associated failure causes AIS generation on all

STS-1/AU-3 outputs as well as the assertion of

AUTO _AIS out puts.

0 TMUX_RILOC_AISINH Receive Input Loss-of-Clock AIS Inhibit. Control

bit, when set to a logic 1, inhi bit s the associated alarm

from c aus ing th e assertion of the AUTO_AIS outp uts;

otherwise, the associated failure causes assertion of

all AUTO_AIS output signals.

Address Bit Nam e Function Res et

Default

0x4001D 15:14 —Reserved. 00

13:11 TMUX_FORCEC2DEF[2:0] Force TMUX_RPLMP Defects. These bits (one for

each STS-1 in an STS-3) will force TMUX_RPLMP

defects on cer tain conditions as shown in Table 524

(STS Signal Label Defect Conditio n s).

000

10:0 TMUX_LOSDETCNT[10:0] L oss-of-Signal Detection Count. Control bits are the

number of consecutive all-0s/1s patte rn detected to

declare LOS stat e in the unscrambled STS-3/STM-1

(AU-4) input frame. A val ue of 0x02D equals 2.3 µs

while a value of 0x798 equals 100 µs.

0x02D

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

98 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 98. TM UX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W)

Address Bit Na m e Function Reset

Default

0x4001E 15:12 TMUX_CNTDK1K2FRAME[3:0] Continuous N-Times Detect for APS Frame

Bytes. S ets t he number o f CNTD frames within

which an inconsistent APS value is detected in the

incoming STS-3/STM-1 (AU-4). This val ue is used in

the APS babble algorithm. The valid range for this

a value of 0x3.

0xC

11:8 TMUX_CNTDK1K2[3:0] Continuous N-Times Detect for APS (K1, K2[7:3])

Bytes. S et s the number of CNTD occurrences of a

consistent APS value in the inc omi ng ST S-3/STM-1

(AU-4) frame. The valid range for thi s register is

0x3—0xF. Invalid values will be mapped to a value of

0x3.

0x3

7:4 TMUX_CNTDF1[3:0] Continuous N-Time s Detect for F1 Byte. S e ts the

number of CNTD occurrences of a consistent F1

value in the incoming STS-3/STM-1 (AU-4) frame.

The valid range for this regi s ter is 0x3—0xF. Inva lid

values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDJ0[3:0] Continuous N-Times Detect for J0 Byte. Sets the

number of CNTD occurrences of a consistent J0

value in the incoming STS-3/STM-1 (AU-4) frame.

The valid range for this regi s ter is 0x3—0xF. Inva lid

values will be mapped to a value of 0x3.

0x3

0x4001F 15:14 —Reserved. 00

13:12 TMUX_CTDLOPCNT[1:0] Continuous N-Times Detect for Loss of Pointe r

State . Control bits are the number of consecutive

conditions for invalid pointer and invalid concatena-

tion indication (pointer interpret at ion). Valid values

are the following: 00 = 8, 01 = 9, 10 = 10, and 11 = 8 .

0x0

11:8 TMUX_CNTDS1FRAME[3:0] Continuous N-Times Detect for S1 Fram e Bytes.

Sets the number of CNTD frames within which an

inconsistent S1 value is detected in the i nc oming

STS-3/ST M-1 (AU-4 ). This value is us ed in the S1

babble algorithm. The valid rang e for this regist er is

0x3—0xF. Invalid values will be mapped to a value of

0x3.

0x3

7:4 TMUX_CNTDS1[3:0] Continuous N-Times Detect for S1 Byte. Sets the

number of CNTD occurrences of a consistent S1

value in the incoming STS-3/STM-1 (AU-4) frame.

The valid range for this regi s ter is 0x3—0xF. Inva lid

values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDK2[3:0] Continuous N-Times Detect for K2[2:0] Byte.

Sets the number of CNTD occurrences of a consis-

tent K2[2:0] value in the incoming STS-3/ STM-1

(AU-4) frame. The valid range for thi s register is

0x3—0xF. Invalid values will be mapped to a value of

0x3.

0xC

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

99Agere Systems Inc.

8 TMUX Registers (continued)

Table 99. TM UX_CNTD_POH_[A—B], Contin uous N-Ti mes Detect Control Parameter s (R/W)

Address Bit Name Function Reset

Default

0x40020 15:12 TMUX_CNTDF2[3:0] Conti nuous N -Tim e s Detect for F2 By te . Sets the num-

ber of CNT D occurrence s of a consistent F2 value i n the

incomi ng STS-3/STM -1 (AU-4) frame. The valid range for

this reg is ter is 0x 3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

11:8 TMUX_CNTDRDIP[3:0] Continuous N-Times Detect for G1[3:1] Byte. Sets the

number of CNT D occurrences of a cons istent G1[3:1]

value in the incoming STS-3/ST M-1 (AU-4) fram e. The

valid range for this register is 0x3—0xF. Invalid values will

be mapped to a value of 0x3.

0x3

7:4 TMUX_CNTDC2[3:0] Continuous N-Times Detect for C2 Byte. Se ts the num-

ber of CNT D occurrence s of a consistent C2 value in the

incomi ng STS-3/STM -1 (AU-4) frame. The valid range for

this reg is ter is 0x 3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

3:0 TMUX_CNTDJ1[3:0] Continuous N-Times Detect for J1 Byte. S e ts the num -

ber of CNT D occurrence s of a consistent J1 value in the

incomi ng STS-3/STM -1 (AU-4) frame. The valid range for

this reg is ter is 0x 3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

0x40021 15:13 —Reserved. 000

12 TMUX_CTDB1SEL Continuous N- Times AUTO AIS Sele ct. Control bi t,

when s et to a logic 1, causes TOH CNTD counters to be

reset wh enever t he AUTO_AIS signal is asser ted.

11:8 TMUX_CNTDN1[3:0] Continuous N-Ti mes Detect for N1 Byte. Sets the nu m-

ber of CNT D occurrence s of a consistent N1 value in the

incomi ng STS-3/STM -1 (AU-4) frame. The valid range for

this reg is ter is 0x 3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

7:4 TMUX_CNTDK3[3:0] Continuous N-Times Detect for K3 Byte. Se ts th e num-

ber of CNT D occurrence s of a consistent K3 val ue in the

incomi ng STS-3/STM -1 (AU-4) frame. The valid range for

this reg is ter is 0x 3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

3:0 TMUX_CNTDF3[3:0] Conti nuous N - Times Detec t for F3 By t e. Sets the num-

ber of CNT D occurrence s of a consistent F3 value i n the

incomi ng STS-3/STM -1 (AU-4) frame. The valid range for

this reg is ter is 0x 3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
100 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Table 100. TMUX_C2EXP[1—2_3] , Cont inuous N-Times D etect Control Para m ete rs (R/ W)
Table 101. TMUX_RF1MON, Receive Monitor Values (RO)
Table 102. TMUX_RAPSMON, Receive Monitor Val ues (RO)
Table 103. TMUX_RS1MON, Receive Monitor Values (RO)
Address Bit N am e Function Re set 
Default
0x40022 15:8 —Reserved. 0x00
7:0 TMUX_C2EXP1[7:0] Expected C2 Byte for Port 1. Should be p rogrammed to 
contain expected signal la bel (C 2) for port 1. 0x00
0x40023 15:8 TMUX_C2EXP3[7:0] Expected C2 Byte for Port 3. Should be programmed to 
contain expected signal la bel (C 2) for port 3. 0x00
7:0 TMUX_C2EXP2[7:0] Expected C2 Byte for Port 2. Should be p rogrammed to 
contain expected signal la bel (C 2) for port 2. 0x00
Address Bit Name Function Reset 
Default
0x40024 15:8 TMUX_RF1MON1[7:0] Receive F1 Previous Mon ito r Value. See  Section 17.5.7 
F1 Monitor on page 371.  0x00
7:0 TMUX_RF1MON0[7:0] Receive F 1 Current Monitor Val ue. S ee Section 17.5.7 
F1 Monitor on page 371.  0x00
Address Bit Name Function Reset 
Default
0x40025 15:3 TMUX_
RAPSMON[12:0] Receive APS Monitor Value . See Section 17.5.9 Auto-
matic Protection Switch (APS) Monitor on page 371.  0x00
2:0 TMUX_K2MON[2:0] Receive K2 Monitor V alue. See Section 17.5.9 A utomatic 
Protection Switch (APS) Monitor on page 371.  0x0
Address Bit Name Function Reset 
Default
0x40026 15:8 —Reserved. 0x00
7:0 TMUX_RS1MON[7:0] Receive S1 Monito r Value. See Section 17.5.12 Sync 
Status Monitor on page 372.  0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
101Agere Systems Inc.  
8 TMUX Registers (continued)
Table 104. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO)
Address Bit Name Function Reset 
Default
0x40027 15:11 —Reserved. 0x00
10:8 TMUX_RDIPMON1[2:0] Receive Path RDI Monitor Valu e for Port 1.  See RDI-P  
Detection on page 379.0x0
7:0 TMUX_C2MON1[7:0] Receive C2 Monitor Valu e for Port 1.  See Signal Lab el 
C2 Byte Monitor on page 378.0x00
0x40028 15:8 TMUX_F2MON11[7:0] Receive F2 Previous Monitor Value for Port  1. See  
Pa th User By t e F2 Moni tor on page 380.0x00
7:0 TMUX_F2MON01[7:0] Receiv e F2 Current Monitor Value for Port  1.  See Path 
User Byte F2 Monitor on  page 380.0x00
0x40029 15:8 TMUX_F3MON11[7:0] Receive F3 Previous Monitor Value for Port  1. See  
Pa th User By t e F3 Moni tor on page 380.0x00
7:0 TMUX_F3MON01[7:0] Receiv e F3 Current Monitor Value for Port  1.  See Path 
User Byte F3 Monitor on  page 380.0x00
0x4002A 15:8 TMUX_N1MON1[7:0] Receive N1 Monitor Value for Port 1. See N1 Byte M on-
itor on page 381.0x00
7:0 TMUX_K3MON1[7:0] Receive K3 Monitor Value for Port 1.  See K3 By te Mon-
itor on page 381.0x00
0x4002B 15:11 —Reserved. 0x00
10:8 TMUX_RDIPMON2[2:0] Receive Path RDI Monitor Valu e for Port 2.  See RDI-P  
Detection on page 379.0x0
7:0 TMUX_C2MON2[7:0] Receive C2 Monitor Valu e for Port 2.  See Signal Lab el 
C2 Byte Monitor on page 378.0x00
0x4002C 15:8 TMUX_F2MON12[7:0] Receive F2 Previous Monitor Val ue for Port 2. See 
Pa th User By t e F2 Moni tor on page 380.0x00
7:0 TMUX_F2MON02[7:0] Receiv e F2 Current Monitor Value for Port  2.  See Path 
User Byte F2 Monitor on  page 380.0x00
0x4002D 15:8 TMUX_F3MON12[7:0] Receive F3 Previous Monitor Val ue for Port 2. See 
Pa th User By t e F3 Moni tor on page 380.0x00
7:0 TMUX_F3MON02[7:0] Receiv e F3 Current Monitor Value for Port  2.  See Path 
User Byte F3 Monitor on  page 380.0x00
0x4002E 15:8 TMUX_N1MON2[7:0] Receive N1 Monitor Value for Port 2. See N1 Byte M on-
itor on page 381.0x00
7:0 TMUX_K3MON2[7:0] Receive K3 Monitor Value for Port 2.  See K3 By te Mon-
itor on page 381.0x00
0x4002F 15:11 —Reserved. 0x00
10:8 TMUX_RDIPMON3[2:0] Receive Path RDI Monitor Valu e for Port 3.  See RDI-P  
Detection on page 379.0x0
7:0 TMUX_C2MON3[7:0] Receive C2 Monitor Valu e for Port 3.  See Signal Lab el 
C2 Byte Monitor on page 378.0x00
0x40030 15:8 TMUX_F2MON13[7:0] Receive F2 Previous Monitor Value for Port  3. See  
Pa th User By t e F2 Moni tor on page 380.0x00
7:0 TMUX_F2MON03[7:0] Receiv e F2 Current Monitor Value for Port  3.  See Path 
User Byte F2 Monitor on  page 380.0x00

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

102 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 104. TMUX_RPOHMON [1 —3][A—D], Receive Monitor Values (RO) (continued)

Table 105. TMUX_TLS_CTL, Transmit Low-speed Cont ro l Parameters (R/W)

Address Bit Name Function Reset

Default

0x40031 15:8 TMUX_F3MON13[7:0] Receive F3 Previous Monitor Value for Port 3. S ee

Path User Byte F3 Monitor o n page 380.0x00

7:0 TMUX_F3MON03[7:0] Recei ve F3 Current Monitor Value for Port 3. See Path

User Byt e F3 Moni tor on page 380.0x00

0x40032 15:8 TMUX_N1MON3[7:0] Receive N1 Mo ni tor Value for Port 3. See N1 Byte M on-

itor on page 381.0x00

7:0 TMUX_K3MON3[7:0] Receive K3 Monitor Value for Port 3. See K3 Byte Mon-

itor on page 381.0x00

Address Bit Name Function Reset

Default

0x40033 15:7 —Reserved. 0x000

6:4 TMUX_TLS_UNEQP[3:1] Transmit Low-speed Unequipped Insert Control.

Control bit, when set to a logic 1, causes an unequip

signal to be gener ated i n t he selecte d STS-1/AU-3 time

slot in the STS-3/STM-1 (AU-4) output signal; normal

data is sent when set t o a logic 0. Only

TMUX_TLS_UNEQP 1 is used i n AU-4 mode.

3:1 TMUX_TLS_PAISINS[3:1] T ransmit Low-speed P ath AIS Insert Contr ol. Control

bit, w hen set to a logic 1, causes path AIS to be

insert ed into the selected STS-1/TUG -3 time slot in th e

STS-3/STM-1 (AU-4) output signal; normal data is sent

when set to a logic 0. Only TM UX_TLS_PAISINS1 is

used in A U-4 mode.

0 TMUX_TLSVOEPAR Transmit Low-speed Verify Odd or Even Parity. Con-

trol bit, when set to a logic 0, causes odd parity to be

verified per byte transfer per STS-1/ AU-3 input; other-

wi se, even pa r it y i s ve rified.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

103Agere Systems Inc.

8 TMUX Registers (continued)

Table 106. T MUX_THS_PORT _CTL, Transmit High-speed P ort Control P a rameters (R/W)

Tabl e 1 0 7. TMUX _ T H S_ TOH_C TL , Transmit Hi gh-spe ed Control Param eters (R/W)

Address Bit Name Function Reset

Default

0x40034 15:4 —Reserved. 0x000

3 TMUX_TPSMUXSEL3 Transmit Hi gh-speed Protection MUX Selection . C ontrol

bit, when set to a logic 1, causes the receive side working

input STS-3/STM-1 (A U-4) signal to be s elect ed; otherwise,

the signal coming in from the transmit low-speed side (tele-

com bus) and POH MUX is selected. The output of this

MU X is sent to a transpor t overhead MUX and eventually

out the T P SD1 55P /N (pins AF13, AE 13) and TPSC155P/N

(pins AC12, AD13) outputs.

2 TMUX_TPSMUXSEL2 Transmit Hi gh-speed Protection MUX Selection . C ontrol

bit, when set to a logic 1, causes the receive side protection

input STS-3/STM-1 (A U-4) signal to be s elect ed; otherwise,

the signal coming in from the transmit low-speed side (tele-

com bus) and POH MUX is selected. The output of this

MU X is sent to a transpor t overhead MUX and eventually

out the THSDP/N (pins AF9, AE9) output.

1 TMUX_RHS2THSLB Receive High-speed to Transmit High-speed Loopback

Contro l. Control bit, whe n set to a logic 1, causes the

receive STS-3/STM- 1(AU-4) i nput signal to be looped bac k

to the transm it high-speed output; loopback is disabled

when set to a logic 0.

0TMUX_THSSCRTransmit High-speed Scramble Enab le. Control bit, when

set to a l ogic 1, c auses the output STS-3/STM-1

(A U- 4) signal to be scr ambl ed; the signal is not scramb led if

set to a logic 0.

Address Bit Name Function Reset

Default

0x40035 15:13 —Reserved. 0x0

12 TMUX_TCONCATMODE Transm it a Co ncaten ated Signal. Control bit, when set

to a logic 1, causes the outgoing STS-3/STM-1 signal to

be concatenated; otherwise, the outgoing signal is three

independent S T S-1 s (for a 155 M Hz signal).

11 TMUX_TPREIRDISEL Trans mit MU X S electio n C o ntro l for Outgoing Path

REI an d RDI. Control bit, when set to a logic 1, causes

the path REI and RDI signals to be selected from the

protection board; otherwise, they are de rived fro m the

receive side o f the same TMUX.

10 TMUX_TLREIRDISEL Tra ns mit MU X S election Contro l for Outgoing Line

REI an d RDI. Control bit, when set to a logic 1, causes

the line REI and RDI signal s to be sele cted from the pro-

tection board; otherwise, they are derived fr om the

receive side o f the same TMUX.

9:8 TMUX_TSS[1:0] Transmit SS (Bits). These bit s are inserted into the out-

going pointer value (b ut not in the concatenation values). 00

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
104 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Tabl e 1 0 7. TMU X _THS_TO H _C TL , Transmit Hi gh-spe ed Control  Param eters (R/W) (continued)
Address Bit Name Function Reset 
Default
0x40035 7 TMUX_THSLREIINH Transmit Line REI Inhibit. Cont rol bit, when s et to a  l ogic 1, 
disables hardware insertion of line REI (B2 errors) in the outgo-
ing STM-1 (AU-4) f rame M 1 b yte; a logic 0  enables hardware 
insertion of line REI.
0
6 TMUX_THSLAISINS Transmit High-speed Li ne AIS Ins e rtion. Control bit, when 
set to a logic 1, causes line AIS to be inserted into the outgoing 
STS-3/STM-1 (AU-4) signal; otherwise,   line AIS is not sent. 
0
5 TMUX_THSAPSINS Transmit APS Value Insert (Control). Control bi t, when set to 
a logic 1, inserts the value in TMUX_TAPSINS [12:0] 
(Table 113) into the outgoing K 1 and K2[7:3] byte s i n the STS-
3/STM-1 (A U-4) frame; a logic 0 inserts the defaul t value based 
on SMPR_OH_DEFLT  (Table 67).
0
4 TMUX_THSK2INS Transmit K2[2:0] Insert (Control). Co ntrol bit, when set to a 
logic 1, inser ts the value in TMUX_TK2INS[2: 0] (Table 113) 
into the outgoing K2 byte in the STS-3/STM-1 (AU-4) frame; a 
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0
3 TMUX_THSS1INS Transmit S1 Inser t (Control). Control bit, when set to a 
logic 1, inser ts the value in TMUX_TS1INS[7: 0] (Table 112) 
into the outgoing S1 byte in the STS-3/STM-1 (AU-4) frame; a 
logic 0 allows insert ion  fro m the TTOAC channel or a defau lt  
value.
0
2TMUX_THSF1INSTransmit F1 Insert (Co ntrol). Control bit, when set to a logic 
1, inserts the value in TMUX_TF1INS[7:0] (Table 112) into  the 
outgoing S1 byte in t he  STS-3/STM-1 (AU-4) frame; a logic 0 
allows insertion from the  TTOAC channel or a default value .
0
1TMUX_THSZ0INSTransmit Z0-2 and Z0-3 Insert (Contr ol). Control bit, when 
set to a logic 1, inserts the values in TMUX_TZ02INS[7:0] 
(Table 111) and TMUX_TZ03INS[7:0] (Table 111)  in to the out-
going Z0-2 and Z0-3 bytes in t he  STS-3/STM-1 (A U-4) f rame; a 
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0
0 TMUX_THSJ0INS Tran sm it J0 Inser t (Contr ol).  Control bit, when set to a logic 
1, inserts the 16-byte sequence TMUX_TJ0DINS[16—1][7:0] 
(Table 133) into the outgoing STS- 3/STM-1 (AU-4) frame; a 
logic 0 inserts the default value based on SMPR_OH_DEFLT.
0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

105Agere Systems Inc.

8 TMUX Registers (continued)

Table 108. TMUX_THS_PO H [1—3]_CTL, Transmit High-Speed Contr o l P arameter s (R/W)

Address Bit Name Function Reset

Default

0x40036 15:9 —Reserved. 0x00

8 TMUX_THSPREIINH1 Tr ansmit Pat h REI Inhibit for Port 1. Control bit, when set to

a logic 1, dis ables hardware insertion of path RE I ( B3 errors)

in the outgoing STM-1 (AU-4) frame G1 byte; a logic 0

enables hardware inser t ion of path REI. Only por t 1 control is

valid in AU-4 mode.

7 TMUX_TPOHTHRU1 Transmit High-speed Path Overhead Insert ion from Low-

speed Input ( Telecom Bus). Co ntrol bit, when set to a logic

1, causes all path overhead byt es, and H1, H2, and H3, to be

pas sed through from the l ow-speed telecom bus to the high-

speed output signal. On ly port 1 control is valid in AU-4 mode.

6 TMUX_THSN1INS1 Trans mit N1 Insert (Control) for Port 1. Control bit, when

set to a logic 1, inserts the value in TMUX_TN1INS1[7:0]

(Table 114) into the o utgoing N1 byte in the STS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

5TMUX_THSK3INS1Transmit K3 Inser t (C ontrol) for Port 1. Control bit , when

set to a logic 1, inserts the value in TMUX_TK3INS1[7:0]

(Table 114) into the o utgoing K3 byte in the S TS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

4TMUX_THSF3INS1Transmit F3 Insert (Control) for Port 1. Control bit, when set

to a l ogic 1, inserts the value i n TMUX_TF3INS1[7:0 ]

(Table 114) into the outgoing F3 byte in the STS-3/STM-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

3TMUX_THSF2INS1Transmit F2 Insert (Control) for Port 1. Control bit, when set

to a l ogic 1, inserts the value i n TMUX_TF2INS1[7:0 ]

(Table 114) into the outgoing F2 byte in the STS-3/STM-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

2 TMUX_THSRDIPINS1 Transm it Path RDI In sert (Control) for P ort 1. Control bit,

w hen set to a logic 1, inser ts th e value in

TMUX_TRDIPINS1[2:0] (Table 114) into t he outgoing G1[3:1]

bits in the STS-3/STM-1 (AU-4) frame; a logic 0 allows inser-

tion from the TPOA C channel or a default v alue . Only port 1

control is valid in AU-4 mode.

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

106 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Contr o l P arameter s (R/W) (continued)

Address Bit Name Function Reset

Default

0x40036 1 TMUX_THSC2INS1 Transmit C2 Insert (Contr ol) for Port 1. Control bit , when

set to a logic 1, inserts the value in TMUX_TC2INS1[7:0]

(Table 114) into the o utgoing C2 byte in the STS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

0TMUX_THSJ1INS1T ransmit J1 Insert (Control) f or P ort 1. Control bit, when set

to a l ogic 1, inserts the 64-byte s equence

TMUX_TJ1DINS1[64—1][7:0] (Table 140) into the outgoing

STS-3/STM-1 (A U-4) f rame; a logic 0 al lows i nsertion from the

TP OAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

0x40037 15:9 —Reserved.

8 TMUX_THSPREIINH2 Tr ansmit Pat h REI Inhibit for Port 2. Control bit, when set to

a logic 1, dis ables hardware insertion of path RE I ( B3 errors)

in the outgoing STS-3 /STM-1 (AU-4) fr ame G1 byte; a logic 0

enables hardware inser t ion of path REI. Only por t 1 con trol is

valid in AU-4 mode.

7 TMUX_TPOHTHRU2 Transmit High-speed Path Overhead Insert ion from Low-

speed Input ( Telecom Bus). Co ntrol bit, when set to a logic

1, causes all path overhead b ytes for port 2 and, H1, H2, and

H 3, to be passed through from the low-speed telec om bus to

the high- speed output signal. Onl y port 1 control is va lid in

AU-4 mo de.

6 TMUX_THSN1INS2 Trans mit N1 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inserts the value in TMUX_TN1INS2[7:0]

(Table 114) into the o utgoing N1 byte in the STS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

5 TMUX_THSK3INS2 Trans mit K3 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inserts the value in TMUX_TK3INS2[7:0]

(Table 114) into the o utgoing K3 byte in the S TS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

4TMUX_THSF3INS2Transmit F3 Insert (Control) for Port 2. Control bit, when set

to a l ogic 1, inserts the value i n TMUX_TF3INS2[7:0 ]

(Table 114) into the outgoing F3 byte in the STS-3/STM-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

107Agere Systems Inc.

8 TMUX Registers (continued)

Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Contr o l P arameter s (R/W) (continued)

Address Bit Name Function Reset

Default

0x40037 3 TMUX_THSF2INS2 T ransmit F2 Insert (Control) for Port 2. Control bit, when set

to a l ogic 1, inserts the value i n TMUX_TF2INS2[7:0 ]

(Table 114) into the outgoing F2 byte in the S TS-3/STM-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

2 TMUX_THSRDIPINS2 Transm it Path RDI In sert (Control) for P ort 2. Control bit,

w hen set to a logic 1, inser ts th e value in

TMUX_TRDIPI NS2[2: 0] (Table 114) into the outgoing G1[3:1]

bits in the STS-3/STM-1 (AU-4) frame; a logic 0 allows inser-

tion from the TPOA C channel or a default v alue . Only port 1

control is valid in AU-4 mode.

1 TMUX_THSC2INS2 Trans mit C2 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inserts the value in TMUX_TC2INS2[7:0]

(Table 114) into the outgoing C2 byte in the STS-3/STM-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default val ue. Only port 1 control is valid in AU-4

mode.

0TMUX_THSJ1INS2T ransmit J1 Insert (Control) f or P ort 2. Control bit, when set

to a l ogic 1, inserts the 64-byte s equence

TMUX_TJ1DINS2[64—1][7:0] (Table 141) into the outgoing

STS-3/STM-1 (A U-4) f rame; a logic 0 al lows i nsertion from the

TP OAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

0x40038 15:9 —Reserved. 0x00

8 TMUX_THSPREIINH3 Tr ansmit Pat h REI Inhibit for Port 3. Control bit, when set to

a logic 1, dis ables hardware insertion of path RE I ( B3 errors)

in the outgoing STS-3 /STM-1 (AU-4) fr ame G1 byte; a logic 0

enables hardware inser t ion of path REI. Only por t 1 control is

valid in AU-4 mode.

7 TMUX_TPOHTHRU3 Transmit High-speed Path Overhead Insert ion from Low-

speed Input ( Telecom Bus). Co ntrol bit, when set to a logic

1, causes all path overhead byt es f or port 3, and H1, H2, and

H 3, to be passed through from the low-speed telec om bus to

the high- speed output signal. Onl y port 1 control is va lid in

AU-4 m ode.

6 TMUX_THSN1INS3 Trans mit N1 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TN1INS3[7:0]

(Table 114) into the o utgoing N1 byte in the STS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default value . Only po r t 1 control is valid in

AU-4 m ode.

5TMUX_THSK3INS3Transmit K3 Inser t (C ontrol) for Port 3. Control bit , when

set to a logic 1, inserts the value in TMUX_TK3INS3[7:0]

(Table 114) into the o utgoing K3 byte in the S TS-3/ST M-1

(A U-4) frame; a logic 0 allows insertion f rom the TPOAC chan-

nel or a default value . Only po r t 1 control is valid in

AU-4 m ode.

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

108 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 108. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Contr o l P arameter s (R/W) (continued)

Address Bit Name Function Reset

Default

0x40038 4 TMUX_THSF3INS3 Transmit F3 Insert (Control) for P ort 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TF3IN S3[7:0]

(Table 114) into the outgoing F3 byte in the STS-3/STM-1

(AU-4) frame; a logic 0 allows insertion from the TPOAC

channel or a default value. Only port 1 control is valid in

AU-4 mode.

3 TMUX_THSF2INS3 Transmi t F2 Insert (Contr ol) for Port 3 . Control bit, when

set to a logic 1, inserts the value in TMUX_TF2IN S3[7:0]

(Table 114) into the outgoing F2 byte in the STS-3/STM-1

(AU-4) frame; a logic 0 allows insertion from the TPOAC

channel or a default value. Only port 1 control is valid in

AU-4 mode.

2 TMUX_THSRDIPINS3 Transmit Pat h RDI In sert (Con tr ol) for Port 3 . Control bit,

when set to a logic 1, inserts the value in

TMUX_TRDIPINS3[2:0] (Table 114) into the outgoing

G1[3 :1] bits in the STS-3/STM - 1 (AU-4) frame; a l ogic 0

allow s insertion f rom the TPOAC channel o r a def a u lt value.

Only port 1 control is va lid in AU-4 mode.

1 TMUX_THSC2INS3 Transmi t C2 Insert (Control) for P ort 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TC2INS3[7:0]

(Table 114) into the outgoing C2 byte in th e STS-3/ST M-1

(AU-4) frame; a logic 0 allows insertion from the TPOAC

channel or a default value. Only port 1 control is valid in

AU-4 mode.

0TMUX_THSJ1INS3Transmi t J1 Inser t (Control) for Port 3. Control bit, when

set to a logic 1, inserts the 64-byte sequence

TMUX_TJ1DINS3[64—1][7:0] (Table 142) int o the outgoing

STS-3/STM-1 (AU-4) fra me; a logic 0 allows insertion from

the TPOAC channel or a defaul t val ue. Only port 1 control is

valid in AU-4 mode.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

109Agere Systems Inc.

8 TMUX Registers (continued)

Table 109. TMUX_TLRDI_CTL , Tran sm it High-Speed Line RDI Control Parameters (R/W)

Table 110. T MUX_TPRDI_CTL, Transmit High-Speed Path RDI Control P arameters ( R/W)

Address Bit Name Function Reset Default

0x4003A 15:7 —Reserved. 0x000

6 TMUX_TRHSSD_LRDIINH Tran smit Receive High-speed Signa l

Degrade L-RDI Inhibit. Control bit, when

set to a logic 1, c auses the associated fail-

ure not to contribute to the automatic inser-

tion of RDI-L; otherwise, the associated

alarm cont rib utes to the generation of RDI-L.

5 TMUX_TRHSSF_LRDIINH Transmit Receive High-speed Signal Fail

L- R D I Inhibi t. Control bit, when set to a

logic 1, causes the associated fai lure not to

contr ibute to the automatic insert ion of RDI-

L; otherwise, the associated alarm contrib-

utes to the generation of RDI-L.

4 TMUX_TRLAISMON_LRDIINH Transm it Receive Line AIS Line RDI

Inhibit. Same as abov e. 0

3 TMUX_TRHSLOF_LRDIINH Transm it Receive High-sp eed Loss-of-

Frame Lin e RDI Inhibit. Same as above. 0

2 TMUX_TRHSOOF_LRDIINH Transmit Receive High-speed Out-of-

Frame Lin e RDI Inhibit. Same as above. 0

1 TMUX_TRHSLOS_LRDIINH Transm it Receive High-sp eed Loss-of-

Signal Line RDI Inhibit. Same as above. 0

0 TMUX_TRILOC_LRDIINH Tran sm it Receive Inpu t Loss-of-Clo ck

Line RDI I nhibit . Same as above. 0

Address Bit Name Function Reset

Default

0x4003B 15:8 —Reserved. 0x000

7:5 TMUX_TRTIM_PRDIINH[3:1] Transmit Receive T race Identifier Mismatch Path RDI

Inhibit. When a 1, causes the associated failure not to

contribut e to the automatic insertion of RDI-P; other-

wise, the associated alarm contributes to the generation

of RD I-P.

4 TMUX_TRUEQ_PRDIINH Transmit Receive Unequipped Path RDI Inhibit.

When a 1, causes the associated failure not to contrib-

ute to the automatic insertion of RDI-P; otherwise, the

associated alarm contrib utes to the generation of RDI-P.

3 TMUX_TRPLM_PRDIINH Transmit Recei ve Payload Label Mismatch Path RDI

Inhibit. When a 1, causes the associated failure not to

contribut e to the automatic insertion of RDI-P; other-

wise, the associated alarm contributes to the generation

of RD I-P.

2 TMUX_TRLOP_PRDIINH Tr an smit Receive L o ss-o f-Pointer R DI I nhibit . When

a 1, causes the associated failure not to contr ibute to

the automatic inserti on o f RDI-P; ot he rwise, the associ-

ated alarm contributes to the generation of RDI- P.

1 TMUX_TRPAIS_PRDIINH Transmit Receive Path AIS RDI Inhibit. Sa me as

above. 0

0 TMUX_TEPRDI_MODE Transmit E nh anc ed RDI M od e. When a 1, causes the

enhanc ed 3-bi t path RDI valu e to be transmitted in

G1[3:1]; otherwise, a one-bit value (G1[3]) i s sent.

TMXF 28155/51 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
110 Agere Sy stem s Inc.
 
8 TMUX Registers (continued)
Table 111. T MUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W)
Table 112. TMUX_TS1_F1_INS _VAL ,  Tra nsmi t TOH and POH In sert Values (R/W)
Table 113. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Valu es (R/W )
Address Bit Name Function Reset 
Default
0x4003C 15:8 TMUX_TZ03INS[7:0] Tran sm it Z0-3  Data Insert Value .  Register value is 
inserted into the STS-3/STM-1 (AU-4) output Z0-3 byte 
if TMUX_THSZ0INS (Table 107) is asserted.
0x00
7:0 TMUX_TZ02INS[7:0] Transmit Z0-2 Data Insert Value .  Re gister value is 
inserted into the STS-3/STM-1 (AU-4) output Z0-2 byte 
if TMUX_T HSZ0IN S is asser ted.
0x00
Address Bit Name Function Reset 
Default
0x4003D 15:8 TMUX_TS1INS[7:0] Transmit S1 Data Inser t Val ue. Register value is 
inserted into the STS-3/STM-1 (AU-4) output S1 by te if 
TMUX_THSS1INS (Table 107) is asserted.
0x00
7:0 TMUX_TF1INS[7:0] Transmit F1 Data Insert Value.  Register value is 
inserted into the STS-3/STM-1 (AU-4) output F1 byte if 
TMUX_THSF1INS (Table 107) i s asserted.
0x00
Address Bit Name Function Reset 
Default
0x4003E 15:3 TMUX_TAPSINS[12:0] Transmi t APS Data Insert Value .   Register value is 
inserted into the STS-3/S TM-1 (AU-4) out put K1[7:0] and 
K2[7:3] bits if  TMUX _ TH SAP SI N S (Table 107) is asser ted.
0x00
2:0 TMUX_TK2INS[2:0]  Transmit K2 Data Insert Value. Register value is inserte d 
into the STS-3/STM-1 (AU-4) output K2[2:0] bits if 
TMUX_ T HS K2 IN S (Table 107) is asserted.
000
Table 114. TMUX_TPO H[1—3]_INS_[A—C], Transmit T OH and POH Insert Values (R/W)
Address Bit Name Function Res et 
Default
0x4003F 15:11 —Reserved. 0x00
10:8 TMUX_TRDIPINS1[2:0] Tra nsmit  Path RDI Data Insert Value for Port 1.  Register 
value is inserted into the STS-3/STM-1 (AU-4) output 
G1[3:1] bits if T MUX_T HSRDIPINS1 (Table 108) is 
asserted, regardless of the value of TMUX_TEPRDI_MODE 
(Table 110).
000
7:0 TMUX_TC2INS1[7:0] Transmit  C2 Data Insert  V alue  for P ort 1. Register value is 
inserted into t he ST M-1(AU-4) out put C2 byte if 
TMUX_T HSC2INS1 (Table 108) is asser ted.
0x00
0x40040 15:8 TMUX_TF3INS1[7:0] Transmit F3 Data Insert V al ue for P ort 1. Register v alue is 
inserted into t he ST M-1(AU-4) output F3 byte i f 
TMUX_THSF3INS1 (Table 108) is asser t ed.
0x00
0x40040 7:0 TMUX_TF2INS1[7:0] Transmit F2 Data Insert V al ue for Po rt 1. Register v alue is 
inserted into t he ST M-1(AU-4) output F2 byte i f 
TMUX_THSF2INS1 (Table 108) is asser t ed.
0x00

Prelim inary Data Sheet TMXF28155 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers (continued)
111Agere Systems Inc.  
Address Bit Name Function Reset 
Default
0x40041 15:8 TMUX_TN1INS1[7:0] Transmit N1 Data I nsert Value for P o rt 1.  Register v alue is 
inserted into the STM-1(AU -4) out put N1  byte if 
TMUX _THSN1INS1 (Table 108) is assert ed.
0x00
7:0 TMUX_TK3INS1[7:0] Transmit  K3  Data Insert Value for Port 1.  Register v alue is 
inserted into t he STM-1(AU -4) output K3 byte if 
TMUX_T HSK3INS1 (Table 108) is asserted.
0x00
0x40042 15:11 —Reserved. 0x00
10:8 TMUX_TRDIPINS2[2:0] Transmit Path RDI Data Inser t Value  fo r Port 2. Register 
value is inserted into the STS-3/STM-1 (AU-4) output  
G1[3:1] bits if TMUX_T HSRDIPINS2 (Table 108) is 
asserted, regardless of the value of 
TMUX_TEPRDI_MODE.
000
7:0 TMUX_TC2INS2[7:0] Transmit C2 Data I nsert V alue f or P o rt 2.  Register v alue is 
inserted into the STM-1(AU -4) out put C2  byte if 
TMUX_THSC2INS1 is asserted.
0x00
0x40043 15:8 TMUX_TF3INS2[7:0] T ransmit F3 Dat a  Insert V alue f or Port 2. Register v alue is 
inserted into t he STM-1(AU-4) output  F3 byte if 
TMUX_THSF3INS1 is  as s erted.
0x00
7:0 TMUX_TF2INS2[7:0] Transmit F2 Data Insert V alue f or P ort 2.  Register v alue is 
inserted into t he STM-1(AU-4) output  F2 byte if 
TMUX_THSF2INS1 is  as s erted.
0x00
0x40044 15:8 TMUX_TN1INS2[7:0] Transmit N1 Data I nsert Value for P o rt 2.  Register v alue is 
inserted into the STM-1(AU -4) out put N1  byte if 
TMUX _THSN1INS1 (Table 108) is assert ed.
0x00
7:0 TMUX_TK3INS2[7:0] Transmit  K3  Data Insert Value for Port 2.  Register v alue is 
inserted into t he STM-1(AU -4) output K3 byte if 
TMUX_T HSK3INS1 (Table 108) is asserted.
0x00
0x40045 15:11 —Reserved. 0x00
10:8 TMUX_TRDIPINS3[2:0] Transmit Path RDI Data Inser t Value  fo r Port 3. Register 
value is inserted into the STS-3/STM-1 (AU-4) output  
G1[3:1] bits if TMUX_T HSRDIPINS3 (Table 108) is 
asserted, regardless of the value of 
TMUX_TEPRDI_MODE.
000
7:0 TMUX_TC2INS3[7:0] Transmit C2 Data I nsert V alue f or P o rt 3.  Register v alue is 
inserted into the STM-1(AU -4) out put C2  byte if 
TMUX _THSC2INS1 (Table 108) is assert ed.
0x00
0x40046 15:8 TMUX_TF3INS3[7:0] T ransmit F3 Dat a  Insert V alue f or Port 3. Register v alue is 
inserted into t he STM-1(AU-4) output  F3 byte if 
TMUX_THSF3INS1 (Table 108) is asserted.
0x00
7:0 TMUX_TF2INS3[7:0] Transmit F2 Data Insert V alue f or P ort 3.  Register v alue is 
inserted into t he STM-1(AU-4) output  F2 byte if 
TMUX_THSF2INS1 (Table 108) is asserted.
0x00
0x40047 15:8 TMUX_TN1INS3[7:0] Transmit N1 Data I nsert Value for P o rt 3.  Register v alue is 
inserted into the STM-1(AU -4) out put N1  byte if 
TMUX_THSN1INS1 is asserted.
0x00
7:0 TMUX_TK3INS3[7:0] Transmit  K3  Data Insert Value for Port 3.  Register v alue is 
inserted into t he STM-1(AU -4) output K3 byte if 
TMUX_THSK3INS1 is  asserted.
0x00
Table 114. TMUX_TPOH[1—3]_INS_[A—C],  Transmit TOH and POH Insert Values (R/W)  (continued)

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

112 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 115. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control P arameters (R/W)

Address Bit Name Function Reset

Default

0x40048 15:13 —Reserved. 0x0

12 TMUX_TPSLREIINS Transmit Protection Signal Line REI Insert. Con-

trol bit, when set to a logic 1, causes one line REI

error in the outgoing protection STS-3/STM-1 (A U-4)

signal when there is a rising edge observed on the

SMPR _ BER_ INSRT (Table 65) input s ignal.

11 TMUX_TPSB2EIINS Transmit Protection Signal B2 Error Insert. Con-

trol bit , when set to a logic 1, causes one B 2 e rror i n

the outgoing protection STS-3/STM-1 (AU-4) sign al

when there is a rising edge observed on the

SMPR _ BER_ INSRT (Table 65) input s ignal.

10:8 TMUX_TPREIINS[3:1] Transmit Pat h REI E r ror Insert. Control bit, when

set to a lo gic 1, causes one path RE I error in the out-

going STS-3/STM-1 (AU-4) signal when there is a

rising edge observed on the SMPR_BER_INSRT

(Table 65) input signal. Only port 1 control is va li d in

AU-4 mode.

7:5 TMUX_THSB3ERRINS[3:1] Transm it High-speed B3 Error Insert. Control bit,

when set to a lo gic 1, causes the output B 3 by te i n

the outgoing STS-3/STM-1 (AU-4) signal to be

in verted when there is a rising edge observed on the

SMPR _ BER_ INSRT (Table 65) input si gnal. O nly

po rt 1 control is val id in AU- 4 mode.

4 TMUX_TLREIINSTransmit Hi gh-speed Line REI Inse rt. Control bit ,

when set to a logic 1, causes one line REI error in

the outgoing STS-3/STM-1 (AU-4) signal when there

is a rising edge observed on the

SMPR_BER_INSR T (Tabl e 65) input signal.

3:1 TMUX_THSB2ERRINS[3:1] Transm it High-speed B2 Error Insert. Control bit,

when set to a lo gic 1, causes the output B 2 by t es i n

the outgoing STS-3/STM-1 (AU-4) signal to be

in verted when there is a rising edge observed on the

SMPR_BER_INSR T (Tabl e 65) input signal.

000

0 TMUX_THSB1ERRINS Transmit High-speed B1 Erro r I nsert. Control bit,

when set to a lo gic 1, causes the output B 1 by te i n

the outgoing STS-3/STM-1 (AU-4) signal to be

in verted when there is a rising edge observed on the

SMPR_BER_INSR T (Tabl e 65) input signal.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

113Agere Systems Inc.

8 TMUX Registers (continued)

Table 116. TMUX_THS _ERR_CTL, Transmi t High-Speed Error Insertion Contro l Par ameter s (R/W)

Address Bit Name Function Reset

Default

0x40049 15:10 —Reserved. 0x00

9 TMUX_TAPSBABINS Transmit APS Babble Insert . When 1, causes an

inconsistent APS byte (K1[7:0], K2 [7:3]) to b e inse r ted

into the outgoing S TS-3/ ST M-1 (AU-4) frame.

8:6 TMUX_TH1H2INVEN[3:1] Transm it H1 H2 Corrupt Enable. When 1, cause the

output H1 and H2 b ytes of the STS-3/STM-1 (AU-4) sig-

nal to be co rrupted on a p er STS-1 basis. In the AU-4

mode, only control bit 1 is used.

000

5 TMUX_TH1H2INVORNDF Transmit H1 H2 Corrupt or NDF. When 0 , causes an

invalid pointer to be inserted into the output H1 and H2

bytes; ot herwise , a continuous NDF condition (1001) is

sent.

4:0 TMUX_TA2ERRINS[4:0] Transmit Frame Error Insert Value. Thes e bits specify

the number of consecutive frames to be inserted with a

frame e rror is inser ted in the outgo ing A2 byte. This

number of errored fr ames is sent each time a rising edge

is observed on the SMPR_BER_INSRT (Table 65) input

signal.

0x0

Table 117. TMUX_T OAC_CT L, Receive/Transmit T OAC/ POAC Control Parameters (R/W )

Address Bit Name Function Reset

Default

0x4004A 15 TMUX_RTOAC_D412MODE Receive TOAC DCC4 to DCC12 Only Mode. When

1, causes t he RTOAC data signal to carry only a par-

ity byte f ollo wed b y DCC4 to DCC12 b ytes . The clock

rate is 640 kHz. If this control bit i s a logic 0 and

TMUX_RTOAC_D13MODE is a l ogic zero, the n the

receive TOAC channel is in ful l access mode.

14 TMUX_RTOAC_D13MODE Receive TOAC DCC1 to DCC3 Only Mode. W hen

1, causes t he RTOAC data signal to carry only a par-

ity byte followed by DCC1 to DCC3 bytes. The clock

rate is 260 kHz. If this control bit i s a logic 0 and

TMUX_RT O AC_D412MODE is a logic zero, t hen the

receive TOAC channel is in ful l access mode.

13 TMUX_RTOAC_OEPINS Receive TOA C Odd or Even P arity Insert. When 1,

forces receive t he ou tpu t TOAC pa rity bit to be even;

otherw ise, the parity is odd.

12:10 —Reserved. 000

9 TMUX_TTOAC_D412MODE Transmit TOAC DCC4 to DCC12 Only Mode.

When 1, causes DCC4 to D CC12 in the outgoing

frame to be inserted f rom the TTOAC ch annel. The

TTOAC c lock rate is 640 kHz. If this control b it is a

log ic 0 and TMUX_TTOAC_D13MODE i s a logi c

zero, t hen the transmit TOAC channel is in full

access m ode.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

8 TMUX Registers (continued)

114 Agere Systems Inc.

0x4004A 8 TMUX_TTOAC_D13MODE Transmit TOAC DCC1 to DCC3 Only Mode.

When 1, causes DCC1 to DCC3 in the outgoing

frame to be inserted f rom the TTOAC ch annel. The

TTOAC c lock rate is 260 kHz. If this control b it is a

log ic 0 and TMUX_TTOAC_D13MODE is a logic

zero, t hen the transmit TOAC channel is in full

access m ode.

7 TMUX_TTOAC_AVAIL Transmit TOAC Available Byte Con t rol. When 1,

causes the incoming TOAC values for undefined

bytes (bold-faced bytes i n Table 523) to b e inserted

into the o utgoing S TS-3/STM-1 frame. Otherwise,

their va lues depend on SMPR_ OH_D EFLT

(Table 67).

6 TMUX_TTOAC_S1 Tra nsmit TOAC S1 Byte Con trol. Whe n 1, causes

the incoming TOAC S1 value to be inserted i nto the

S1 byte of the outgoing STS-3/ S TM-1 frame if the

TMUX_THSS1INS (Table 107) cont rol bit is deas-

serted. If the S1 is n o t inserted fro m register co nt rol

or from the transmit TOAC c hannel, then its value

depends on SMP R_OH_DE FLT.

5TMUX_TTOAC_F1Transmit TOAC F1 Byte Control. When 1, causes

the incoming TOAC F1 value to be inserted into the

F1 byte of the outgoing STS-3/STM-1 frame if the

TMUX_THSF1INS (Table 107) control bit is desas -

serted. If the F1 is not inse rted fro m register control

or from the transmit TOAC c hannel, then its value

depends on SMP R_OH_DE FLT.

4 TMUX_TTOAC_E2 Tra nsmit TOAC E1 Byte Con trol. Whe n 1, causes

the incoming TOAC E1 value to be inserted i nto the

E1 byte of the outgoing S TS-3/S TM-1 frame. Other-

wise, the E1 value depends on SMPR_OH_DEFLT.

3 TMUX_TTOAC_E1 Tra nsmit TOAC E1 Byte Con trol. Whe n 1, causes

the incoming TOAC E1 value to be inserted i nto the

E1 byte of the outgoing S TS-3/S TM-1 frame. Other-

wise, the E1 value depends on SMPR_OH_DEFLT.

2 TMUX_TTOAC_D4TO12 Transmit TOAC D4 to D12 Byte Control. When 1,

causes the TTOAC values to be inserted into the D4

to D12 bytes of the outgoing frame. If this control bit

is a logic zero, then the outgoing D4 to D12 values

depend on SMPR_OH_DEFLT.

1 TMUX_TTOAC_D1TO3 Transmit TOAC D1 to D3 Byte Co ntrol. When 1,

causes the TTOAC values to be inserted into the D1

to D3 bytes of the outgoing f rame. If this control bit is

a logic zero, then the outgoing D1 to D3 values

depend on SMPR_OH_DEFLT.

0 TMUX_TTOAC_OEPMON T ransmit TO AC Odd or Even Parity Monitor . When

1, forces the input TOAC parity checker to check for

odd parity; otherwise, even parity is checked on the

transmit TOAC c hannel .

Table 117. TMUX_T OAC_CT L, Receive/Transmit T OAC/ POAC Control Parameters (R/W) (continued)

Address Bit Name Function Reset

Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

115Agere Systems Inc.

8 TMUX Registers (continued)

Table 118. TMUX_RPOAC_CTL, Receive/Transmit T OAC/POAC Contr ol Parameters (R/W)

Address Bi t Name Function Reset

Default

0x4004B 15:14 TMUX_RPOAC_SEL[1:0] Receive POAC STS-1 Port Selection. Des ign ates which

STS-1 inserts its path overh ead bytes onto the receive

POA C channel. V alues of 00 or 01 designate STS-1 #1, 10

designates STS-1 # 2, 11 designates STS-1 #3.

13 TMUX_RPOAC_OEPINS Receive POAC Odd or Even Parity Insert. W hen 1,

f orces receiv e the output POA C parity bit to be even; other-

wise, the par ity is odd.

12:10 —Reserved. 000

9:8 TMUX_TPOAC_SEL[1:0] Tran smit POAC STS-1 Port Sele ction. Designates whic h

STS-1 obtains path overhead b ytes from th e transmit

POA C channel. V alues of 00 or 01 designate STS-1 #1, 10

designates STS-1 # 2, 11 designates STS-1 #3.

7—Reserved. 0

6 TMUX_TPOAC_N1 Transm it POAC N1 Byte Control. When 1, causes the

incoming POA C N1 value to be inserted into the N1 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSN1INS (Table 108) cont rol bit is desasserted.

If the N1 is not inserted f rom register control or from the

transmit PO A C channel, then its value depends on

SMPR _OH_DEFLT (Table 67).

5 TMUX_TPOAC_K3 Transmit POAC K3 Byte Co ntrol. When 1, causes the

incoming POAC K3 val ue to be inserted into the K3 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_ T H SK3 IN S ( Table 108) control bit is des ass erted.

If the K3 is not inserted from register control or from the

transmit PO A C channel, then its value depends on

SMPR_OH_DEFLT.

4 TMUX_TPOAC_F3 Transmit POAC F3 Byte Control. When 1 , causes th e

incoming POAC F3 value to be inserted into the F3 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSF3INS (Table 108) control bit is desasserted. If

the F 3 is not inserted f rom register cont rol or from the

transmit PO A C channel, then its value depends on

SMPR_OH_DEFLT.

3 TMUX_TPOAC_F2 Transmit POAC F2 Byte Control. When 1 , causes th e

incoming POAC F2 value to be inserted into the F2 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSF2INS (Table 108) control bit is desasserted. If

the F 2 is not inserted f rom register cont rol or from the

transmit PO A C channel, then its value depends on

SMPR _OH_DEFLT (Table 67).

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

116 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/ W) (continued)

Table 119. T MUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W)

)

Address Bit Name Fu nction Reset

Default

0x4004B 2 TMUX_TPOAC_C2 Transmit POAC C2 Byte Control. When 1, causes

the incoming POA C C2 value to be inserted into the C2

byte of the selected TPOAC STS-1 if the correspond-

ing TMUX_THSC2INS (Table 108) control bit is desas -

serted. If the C2 is not inserted from register control or

from the transmit POAC channel, then its value

depends on SMPR_O H_DE FLT.

1TMUX_TPOAC_J1Transmit POAC J1 Byte Control. Control bit, when

set to a logic 1, causes the incoming POAC J1 value to

be inserted into the J1 byte of the selected TPOAC

STS-1 if the corresponding TMUX_THSJ 1INS

(Table 108) control bit is desas s erted. If the J 1 is not

inserted from register control or from the transmit

POAC channel, then its value depends on

SMPR_OH_DEFLT.

0 TMUX_TPOAC_OEPMON Transm it TOAC Odd o r Ev en P arit y Monit or. Cont rol

bit, when s et to a logic 1, forces the input TOAC parity

check er to check for odd parity; otherwise , ev en parity

is checked o n the transmit TOAC channel.

Address Bit Name Function Reset

Default

0x4004D 15:13 TMUX_TLBITCNT[2:0] Transmit Load Bit Count. Allows the output

STS-3/STM-1 (AU-4) frame to have any relationship to

the input frame sync pulse (THSSJ0J1V1I).

000

12:11 TMUX_TLSTSCNT[1:0] Transmit Load STS-1 Count. Same as above. 00

10:4 TMUX_TLCOLCNT[6:0] Transm it Load Col umn Count. Same as above. 0000000

3:0 TMUX_TLROWCNT[3:0] Transmit Load Row Cou nt. Same as above. 0000

Table 120. TMUX_SD_CT L[1—6], B1/B2 Signal Degrade S et/Clear Control Registers (R/W)

Address Bit Name Function Reset

Default

0x4004E

0x4004F 15:0

2:0 TMUX_SDNSSET[18:3]

TMUX_SDNSSET[2:0] Signal Degrade N s Set. Num ber of frames in a

monitorin g block for signal degrade (SD). 0x00000

0x4004F 14:7 TMUX_SDMSET[7:0] Signal Degrade M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the

number of bad bloc ks is above t his threshold, then SD is

set.

0x00

6:3 TMUX_SDLSET[3:0] Sig nal Degrade L Set. Error threshold for determining

if a m onitoring block is bad. 0x0

0x40050 15:0 TMUX_SDBSET[15:0] Signal De grade B Set. Num ber of monitor ing blocks. 0x0000

0x40051

0x40052 15:0

2:0 TMUX_SDNSCLEAR[18:3]

TMUX_SDNSCLEAR[2:0] Signal De grad e Ns Clear. Number of fram es in a

monitorin g block for SD. 0x00000

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

8 TMUX Registers (continued)

117Agere Systems Inc.

Table 121. TMUX_SF_CTL[1—6], B1/B2 Signal Fail Set/ Clear Contro l Registers (R/W )

0x40052

0x40052 14:7 TMUX_SDMCLEAR[7:0] S ignal Degrade M Clear. Threshold of the number of

bad monitoring blocks in an observation inte rval. I f the

number of bad bloc ks is below this threshold, then SD is

cleared.

0x00

6:3 TMUX_SDLCLEAR[3:0] Signal Degrade L Clea r. E rror threshold for

determining if a monitoring blo ck is bad. 0x0

0x40053 15:0 TMUX_SDBCLEAR[15:0] S ignal Degrade B Clear. Num ber of monitor ing blocks. 0x0000

Address Bit Name Function Reset

Default

0x40054

0x40055 15:0

2:0 TMUX_SFNSSET[18:3]

TMUX_SFNSSET[2:0] Signal Fail Ns Set. Number of frames in a m onitori ng

block for signal fa il (SF). 0x0000

0x40055 14:7 TMUX_SFMSET[7:0] Signal Fail M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the

n umber of bad bl ocks is abov e this threshold, then SF is

set.

0x00

0x40055 6:3 TMUX_SFLSET[3:0] Sig nal Fai l L S et . Error th re shold for determining if a

monitorin g block is bad. 0x0

0x40056 15:0 TMUX_SFBSET[15:0] Signal Fail B Set. Numbe r of moni tor ing blocks. 0x0000

0x40057

0x40058 15:0

2:0 TMUX_SFNSCLEAR[18:3]

TMUX_SFNSCLEAR[2:0] Signal Fail Ns Clear. Number of frames in a monitoring

block for SF. 0x0000

0x40058 14:7 TMUX_SFMCLEAR[7:0] S ignal Fail M Clear. Thresho ld of the number of bad

monitoring blocks in an observation interval. If the

number of bad bl oc ks is below this threshold, then SF is

cleared.

0x00

0x40058 6:3 TMUX_SFLCLEAR[3:0] Signal Fai l L Clear. Error threshold for determining if a

monitorin g block is bad. 0x0

0x40059 15:0 TMUX_SFBCLEAR[15:0] Signal Fail B Clear. Number of m onitoring blocks . 0x0000

Table 122. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Reg isters (R/W)

Address Bit Name Function Reset

Default

0x4005A

0x4005B 15:0

2:0 TMUX_B3SDNSSET[18:3]

TMUX_B3SDNSSET[2:0] B3 Si gn al Degrade Ns Set. Number of fram es i n a

monitorin g block for signal degrade (SD). 0x0000

0x4005B 14:7 TMUX_B3SDMSET[7:0] B3 Si gnal Degrade M Set. Threshold of the number

of bad monitoring blocks in an observation interval . If

the number of bad blocks is above this thres hold,

then SD is set.

0x00

0x4005B 6:3 TMUX_B3SDLSET[3:0] B3 S ignal Degrade L Set. Error threshold for

determining if a m onitoring block is bad. 0x0

0x4005C 15:0 TMUX_B3SDBSET[15:0] B3 Sign al Degrade B S et. Num ber of monitoring

blocks. 0x0000

0x4005D

0x4005E 15:0

2:0 TMUX_B3SDNSCLEAR[18:3]

TMUX_B3SDNSCLEAR[2:0] B3 Signal Degrade Ns Clear. Number of frames in a

monitorin g block for SD. 0x0000

Table 120. TMUX_SD_CTL[1—6], B1/B2 Signal Deg rad e Set/Cle ar Control Registers (R/W) (continued)

Address Bit Name Function Reset

Default

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

8 TMUX Registers (continued)

118 Agere Systems Inc.

Table 123. TMUX_B3SF _CTL [ 1 —6], B3 Signal Fail Set/Cle ar C ontrol Re gisters (R/ W)

Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO)

0x4005E 14:7 TMUX_B3SDMCLEAR[7:0] B3 Signal Degrade M Clear . Threshold of the

number of bad monitor ing blocks in an observation

inter val. If th e number of bad blocks is below this

threshold, then SD is cleared.

0x00

6:3 TMUX_B3SDLCLEAR[3:0] B3 Signal Degrade L Clear . Error threshold for

determ ining if a monitoring block is bad. 0x0

0x4005F 15:0 TMUX_B3SDBCLEAR[15:0] B3 Signal Degrade B Clear. Number of monitoring

blocks. 0x0000

Address Bit Name Function Reset

Default

0x40060

0x40061 15:0

2:0 TMUX_B3SFNSSET[18:3]

TMUX_B3SFNSSET[2:0] B3 Signal Fail Ns S e t. Num ber of frames in a

monitoring block for SF. 0x0000

0x40061 14:7 TMUX_B3SFMSET[7:0] B3 Signal Fail M Set. Threshold of the number of

bad monitoring blocks in an observation interval. If

the number of bad blo cks is above this threshold,

then SF is set.

0x00

0x40061 6:3 TMUX_B3SFLSET[3:0] B3 Signal Fail L Set. Error threshold for

determining if a m onitoring block is bad. 0x0

0x40062 15:0 TMUX_B3SFBSET[15:0] B3 Sign a l Fa il B Set. Number of monitoring blocks. 0x0000

0x40063

0x40064 15:0

2:0 TMUX_B3SFNSCLEAR[18:3]

TMUX_B3SFNSCLEAR[2:0] B3 Signal Fail Ns Clear. Number of frames in a

monitoring block for SF. 0x0000

0x40064 14:7 TMUX_B3SFMCLEAR[7:0] B3 Signal Fail M Clear. Threshold of the number of

bad monitoring blocks in an observation interval. If

the number of bad blo cks is b elow this threshold,

then SF is cleared.

0x00

0x40064 6:3 TMUX_B3SFLCLEAR[3:0] B3 Signal Fail L Clear. Error threshol d for

determining if a m onitoring block is bad. 0x0

0x40065 15:0 TMUX_B3SFBCLEAR[15:0] B3 Signal F ai l B Clear. Number of monitoring

blocks. 0x0000

Address Bit Name Function Reset

Default

0x40066 15:0 TMUX_B1ECNT[15:0] Receive High-speed B1 Error Count. Counts the number

of B1 errors in the received STS-3/STM-1 (AU-4) frame.

This co unte r can either count a ctual BIP errors or block

errors; s ee TM UX_BITBLKB1 (Table 95). T his counter

holds at its maximum value or rolls over depending on the

value o f SMPR_SAT_ROLLOVER (Table 67) and trans fers

its internal count to a holding regis ter when

SMPR_PMRESET (Table 65) t ransitions fro m a logic 0 to 1.

0x0000

Table 122. TMUX_B3SD_CT L[1—6], B3 Signal Degra de Set/Clear Control Registers (R/W) (continued)

Address Bit Name Function Reset

Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

119Agere Systems Inc.

8 TMUX Registers (continued)

Table 125. T MUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Erro r Counts (RO)

Table 126. TMUX_B3ECNT[1—3], Recei ve B3 Error Counts (RO)

Address Bit Name Function Reset

Default

0x40067 15:2 —Reserved. 0x000

0x40067—

0x40068 1:0

15:0 TMUX_B2ECNT[17:16]—

TMUX_B2ECNT[15:0] Receive High-speed B2 Error Count. C o unts th e

number of B 2 error s in the received ST S -3 /S TM-1

(AU-4) frame. Thi s count er can either count act ual BIP

errors o r bl ock errors; see TMUX _B ITBLKB2

(Table 95). T his counter holds a t its maximum value or

rolls over depe nding on the value of

SM PR_ SAT_ROLLOV E R and transfers it s internal

count to a holding r eg ister when S MPR_PM RESET

transitions from a logic 0 to 1.

0x0000

Address Bit Name Function Reset

Default

0x40069 15:0 TMUX_B3ECNT1[15:0] Receiv e High-speed B3 Error Count for Port 1. Counts

the number of B3 errors in the receive STS-3/STM-1

(AU- 4) frame for port 1. On ly counte r value 1 is valid in

AU-4 mode. This counter can either cou nt actual BI P errors

or block errors; see TMUX_BITBLKB3 (Table 95). This

coun ter holds a t its maximum value or r olls over depending

on the value of SMP R_SAT_ROLLOVER (Table 67) and

transfers it s i nte rnal co unt to a holding register when

SMPR_PMRESET (Table 65) transitions from a logic 0 to 1.

0x0000

0x4006A 15:0 TMUX_B3ECNT2[15:0] Receiv e High -spee d B3 Error Count for Port 2. Counts

the number of B3 errors in the receive STS-3/STM-1

(AU- 4) frame for port 2. On ly counte r value 1 is valid in

AU-4 mode. This counter can either cou nt actual BI P errors

or block errors; see TMUX_BITBLKB3 (Table 95). This

coun ter holds a t its maximum value or r olls over depending

on the value of SMPR_SAT_ROLLO VER and transfers i t s

internal count to a holding register when SMPR_PMRESET

transitions from a logic 0 to 1.

0x0000

0x4006B 15:0 TMUX_B3ECNT3[15:0] Receiv e High -spee d B3 Error Count for Port 3. Counts

the number of B3 errors in the receive STS-3/STM-1

(AU- 4) frame for port 3. On ly counte r value 1 is valid in

AU-4 mode. This counter can either cou nt actual BI P errors

or block errors; see TMUX_BITBLKB3 (Table 95). This

coun ter holds a t its maximum value or r olls over depending

on the value of SMPR_SAT_ROLLO VER and transfers i t s

internal count to a holding register when SMPR_PMRESET

transitions from a logic 0 to 1.

0x0000

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

120 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 127. TMUX_M1ECNT_17_16 and TMUX_M1EC NT_15_0, Receive M1 Error Counts (RO)

Table 128. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO)

Address Bit Name Function Reset

Default

0x4006C 15:2 —Reserved. 0x000

0x4006C—

0x4006D 1:0

15:0 TMUX_M1ECNT[17:16]—

TMUX_M1ECNT[15:0] Recei ve Line REI Count. Counts the number of

errors received in the M1 byte of the re ceive

STS-3/S TM- 1 (AU-4) frame. This counter can either

count actua l errors or block errors; see

TMUX_BITBLKM1 (Table 95). T his counte r holds at

its maximum value or rolls over depending on the

value of S MPR_SAT_RO LLO VE R and transfers its

internal count to a holding register when

SMPR_PMRESET t ransitions from a logic 0 to 1.

0x00000

Address Bit Name Function Reset

Default

0x4006E 15:0 TMUX_G1ECNT1[15:0] Receive P ath REI Count for Po rt 1. Counts the num ber of

B3 errors received in the G1[ 7:4] bits of port 1 in the

received ST S -3/STM- 1 (AU-4) frame. This counte r c an

either cou nt actual erro rs or block errors; see

TMUX_BITBLKB3 (Table 95). This counter holds at its max-

imum value or rolls over depending on the v alue of

SMPR_SAT_ROLLOVE R (Table 67) and t ransfers its inter-

nal count to a h olding re gister when SMPR_PMRESET

(Table 65) transitions from a logic 0 to 1.

0x0000

0x4006F 15:0 TMUX_G1ECNT2[15:0] Receive P ath REI Count for P ort 2. Coun ts the num ber of

B3 errors received in the G1[ 7:4] bits of port 2 in the

received ST S -3/STM- 1 (AU-4) frame. This counte r c an

either cou nt actual erro rs or block errors; see

TMUX_BITBLKB3 (Table 95). This counter holds at its max-

imum value or rolls over depending on the v alue of

SMPR_SAT_ROLLOVER and transfers its i nter nal count to

a holding register when SMPR _PMRE SET t ransitions from

a logic 0 to 1.

0x0000

0x40070 15:0 TMUX_G1ECNT3[15:0] Receive P ath REI Count f or Port 3. Counts the number of

B3 errors received in the G1[ 7:4] bits of port 3 in the

received ST S -3/STM- 1 (AU-4) frame. This counte r c an

either cou nt actual erro rs or block errors; see

TMUX_BITBLKB3 (Table 95). This counter holds at its max-

imum value or rolls over depending on the v alue of

SMPR_SAT_ROLLOVER and transfers its i nter nal count to

a holding register when SMPR _PMRE SET t ransitions from

a logic 0 to 1.

0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

121Agere Systems Inc.

8 TMUX Registers (continued)

Table 129. TMUX_RPTR_INCCNT[1 —3], Receive Pointer Increment Count (RO)

Table 130. TMUX_RPTR_DECCNT[1—3], Receive Point er Decrement Count (RO)

Table 131. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W)

Table 132. TMUX_RJ0 CAPTURE D[1—8], Captured J0 Receive Value (RO)

Table 133. TMUX_TJ0VALUE[1—8], J0 By te Transmit Ins ert (R/W)

Address Bit Name Function Reset

Default

0x40074—

0x40076 15:11 —Reserved. 0x000

0x40074—

0x40076 10:0 TMUX_RPTR_INC1[10:0]—

TMUX_RPTR_INC3[10:0] Receive Pointer Increment Count. Counts the

number of increments in the incoming pointer val-

ue s. This counter holds at its maximum value or

rolls over depending on the value of

SM PR _SAT _ROLLOV E R (Table 67) and transfe rs

its internal count to a holding register when

SMP R_PMRESET (Table 65) transitions fro m a

logic 0 to 1.

0x000

Address Bit Name Function Reset

Default

0x40077—

0x40079 15:11 —Reserved. 0x000

0x40077—

0x40079 10:0 TMUX_RPTR_DEC1[10:0]—

TMUX_RPTR_DEC3[10:0] Receive Pointer Decrement Count. Counts the

number of decrement s in the incoming pointer val-

ues. This counter holds at its maximum value or rolls

over depending on the value of

SMP R _S AT_ROLLOVE R and transfers its internal

count to a ho lding register when SMPR_PMRESET

transitions from a logic 0 to 1.

0x000

Address Bit Name Function Reset

Default

0x400A0—

0x400A7 15:0 TMUX_EXPJ0DMON[16—1][7:0] Expected Receive J0 Valu e. Registe rs con-

tain either the programmed expected J0 16-

byte sequence or the previously captured J0

sequence, depending o n the J0 mode.

0x0000

Address Bit Name Function Reset

Default

0x400A8—

0x400AF 15:0 TMUX_J0DMON[16—1][7:0] Received J0 Value. Regist ers capture a 16-byte

sequence from the J0 byte of the receive input signal. 0x0000

Address Bit Name Function Reset

Default

0x400B0—

0x400B7 15:0 TMUX_TJ0DINS[16—1][7:0] Transmit J0 Data Inser t. Registers al low a 16-byte

sequence to be inserted i nto the J0 by te of the

STS-3/ST M-1(AU-4) output si gnal.

0x0000

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

122 Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 134. TMUX_RJ1EXPECTED1_[1—32], Expected J1 Byte Value for Port 1 (R/W )

Table 135. TMUX_RJ1EXPECTED2_[1—32], Expected J1 Byte Value for Port 2 (R/W )

Table 136. TMUX_RJ1EXPECTED3_[1—32], Expected J1 Byte Value for Port 3 (R/W )

Table 137. TMUX_RJ1CAPT URE D1_[1—32], Captured J1 Valu e for STS #1 (RO)

Table 138. TMUX_RJ1CAPT URE D2_[1—32], Captured J1 Valu e for STS #2 (RO)

Address Bit Name Function Reset

Default

0x400E0—

0x400FF 15:0 TMUX_EXPJ1DMON1[64—1][7:0] Expected Receive J1 Value for P ort 1.

R egisters contain either the programmed

expected J1 16-byte/64-b yte sequence or the

pr ev iously c aptured J1 sequence, depending

on the J1 mode.

0x0000

Address Bit Name Function Reset

Default

0x40100—

0x4011F 15:0 TMUX_EXPJ1DMON2[64—1][7:0] Expected Receive J1 Value for Po rt 2 . Reg-

isters contai n e ither the programmed

expected J1 16-byt e/64-by t e sequenc e or the

previously captured J1 sequence, de pendin g

on the J1 mode.

0x0000

Address Bit Name Fu nction Reset

Default

0x40120—

0x4013F 15:0 TMUX_EXPJ1DMON3[64—1][7:0] Expected Receiv e J1 Value f or Port 3 . Regis-

ters contain either the programmed expected

J1 1 6-byte/64-by te sequence or the pr ev iously

captured J 1 s equence, depending on the J1

mode.

0x0000

Address Bit Name Function Reset

Default

0x40140—

0x4015F 15:0 TMUX_J1DMON1[64—1][7:0] Receive J1 Monitor Data for Port 1. Registers

capture a 16-byte/64-byte s equenc e from the port

1, J1 byte of the S TS-3/ST M-1 (AU-4) input signal.

Only port 1 inform ati on is valid in AU-4 mode.

0x0000

Address Bit Name Function Reset

Default

0x40160—

0x4017F 15:0 TMUX_J1DMON2[64—1][7:0] Receive J1 Monitor Data for Port 2 . Re gisters

capture a 64-byte sequence from the port 2, J1 byte

of the STS-3/STM-1 (AU-4) input signal. Only port 1

information is valid in AU-4 mode.

0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

123Agere Systems Inc.

8 TMUX Registers (continued)

Table 139. TMUX_RJ1CAPTURE D3_[1—32], Captured J1 Value for STS #3 (RO)

Table 140. TMUX_TJ1VAL UE_1[1—32], J1 Byte Transmit Insert for S TS #1 (R/W)

Table 141. TMUX_TJ1VAL UE_2[1—32], J1 Byte Transmit Insert for S TS #2 (R/W)

Table 142. TMUX_TJ1VAL UE_3[1—32], J1 Byte Transmit Insert for S TS #3 (R/W)

Address Bit Name Function Reset

Default

0x40180—

0x4019F 15:0 TMUX_J1DMON3[64—1][7:0] Receive J 1 Monitor Data for Po rt 3. Registers

capture a 64-byte sequence from the port 3 J1

byte of the STS-3 /S TM-1 (AU-4) input si gnal.

Only port 1 inform ati on is valid in AU-4 mode.

0x0000

Address Bit Name Function Reset

Default

0x401A0—

0x401BF 15:0 TMUX_TJ1DINS[64—1][7:0] Transmi t J1 Data Insert for Por t 1. Registers allow

a 64-byte sequence to be inserted into the port 1, J1

byte of the STS-3/STM-1(AU-4) output signal. Only

port 1 information is valid in AU-4 mode.

0x0000

Address Bit Name Function Reset

Default

0x401C0—

0x401DF 15:0 TMUX_TJ1DINS2[64—1][7:0] Transmit J1 Data Insert for Por t 2. Registers

allow a 64-byte sequence to be inserted into the

port 2, J1 byte of the STS-3/STM-1(AU-4) output

signal. Only port 1 informat ion is valid in AU-4

mode.

0x0000

Address Bit Name Function Reset

Default

0x401E0—

0x401FF 15:0 TMUX_TJ1DINS3[64—1][7:0] Transmit J1 Data Insert for Port 3. Registers allow

a 64-byte sequence to be inserted into the port 2,

J1 byte of th e STS-3/STM-1(AU-4) output signal.

Only port 1 information is valid in AU-4 mode.

0x0000

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

124 A

ere S

stems Inc.

8 TMUX Registers (continued)

8.2 TMUX Register Map

Tabl e 143. T MUX Register Map

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2Bit 1Bit 0

ID and Version—RO

0x40000 TMUX_ID_

RTMUX_VERSION[2:0] TMUX_TMUX_ID[7:0] = 0X04

One-Shot (0 to 1 transition Control Bit Parameters—R/W

0x40002 TMUX_ON

ESHOT TMUX_B3S

FCLEAR TMUX_B3S

FSET TMUX_B3S

DCLEAR TMUX_B3S

DSET TMUX_SFC

LEAR TMUX_SFS

ET TMUX_SD

CLEAR TMUX_SD

SET

Receive/Transmit Mode—R/W

0x40003 TMUX_RC

V_TX_MO

TMUX_STS

1MODE

Delta and Event Par ameters—COR/COW

0x40004 TMUX_TX

_DLT TMUX_TLS

PARE3 TMUX_TLS

PARE2 TMUX_TLS

PARE1 TMUX_TP

OAC_PE TMUX_TTO

AC_PE TMUX_THS

ILOFD TMUX_THS

ILOCD

0x40005 TMUX_

RPS_

DLT

TMUX_RP

SLOFD TMUX_RP

SOOFD TMUX_RP

SILOCD TMUX_RP

SB2E TMUX_RP

SLREIE

0x40006 TMUX_RH

S_DLT TMUX_RS

1BABE TMUX_RS

1MOND TMUX_RLRDI

MOND TMUX_RLAI

SMOND TMUX_RK2

MOND TMUX_RAP

SBABE TMUX_RAP

SMOND TMUX_RF1

MOND TMUX_RTI

MSD TMUX_RH

SSFD TMUX_RH

SSDD TMUX_RH

SLOSD TMUX_RH

SLOFD TMUX_RH

SOOFD TMUX_RH

SILOCD

0x40007 TMUX_RP

OH1_DLT TMUX_RS

FB3D1 TMUX_RS

DB3D1 TMUX_RU

NEQPD1 TMUX_RPLM

PD1 TMUX_RN1

MOND1 TMUX_RK3

MOND1 TMUX_RF3

MOND1 TMUX_RF2

MOND1 TMUX_RR

DIPD1 TMUX_RC2

MOND1 TMUX_RTI

MPD1 TMUX_RN

DFE1 TMUX_RD

ECE1 TMUX_RIN

CE1 TMUX_RPA

ISD1 TMUX_RL

OPD1

0x40008 TMUX_RP

OH2_

DLT

TMUX_RS

FB3D2 TMUX_RS

DB3D2 TMUX_RU

NEQPD2 TMUX_RPLM

PD2 TMUX_RN1

MOND2 TMUX_RK3

MOND2 TMUX_RF3

MOND2 TMUX_RF2

MOND2 TMUX_RR

DIPD2 TMUX_RC2

MOND2 TMUX_RTI

MPD2 TMUX_RN

DFE2 TMUX_RD

ECE2 TMUX_RIN

CE2 TMUX_RPA

ISD2 TMUX_RL

OPD2

0x40009 TMUX_RP

OH3_DLT TMUX_RS

FB3D3 TMUX_RS

DB3D3 TMUX_RU

NEQPD3 TMUX_RPLM

PD3 TMUX_RN1

MOND3 TMUX_RK3

MOND3 TMUX_RF3

MOND3 TMUX_RF2

MOND3 TMUX_RR

DIPD3 TMUX_RC2

MOND3 TMUX_RTI

MPD3 TMUX_RN

DFE3 TMUX_RD

ECE3 TMUX_RIN

CE3 TMUX_RPA

ISD3 TMUX_RL

OPD3

Interrupt Mask Parameters for INT Pin—R/W

0x4000A TMUX_

TX_

MSK

TMUX_TLS

PARM3 TMUX_TLS

PARM2 TMUX_TLS

PARM1 TMUX_TP

OAC_PM TMUX_TTO

AC_PM TMUX_THS

ILOFM TMUX_THS

ILOCM

0x4000B TMUX_RP

S_MSK TMUX_RP

SLOFM TMUX_RP

SOOFM TMUX_RP

SILOCM TMUX_RP

SB2M TMUX_RP

SLREIM

0x4000C TMUX_RH

S_MSK TMUX_RS

1BABM TMUX_RS

1MONM TMUX_RLRDI

MONM TMUX_RLAI

SMONM TMUX_RK2

MONM TMUX_RAP

SBABM TMUX_RAP

SMONM TMUX_RF1

MONM TMUX_RTI

MSM TMUX_RH

SSFM TMUX_RH

SSDM TMUX_RH

SLOSM TMUX_RH

SLOFM TMUX_RH

SOOFM TMUX_RH

SILOCM

0x4000D TMUX_RP

OH1_MSK TMUX_RS

FB3M1 TMUX_RS

DB3M1 TMUX_RU

NEQPM1 TMUX_RPLM

PM1 TMUX_RN1

MONM1 TMUX_RK3

MONM1 TMUX_RF3

MONM1 TMUX_RF2

MONM1 TMUX_RR

DIPM1 TMUX_RC2

MONM1 TMUX_RTI

MPM1 TMUX_RN

DFM1 TMUX_RD

ECM1 TMUX_RIN

CM1 TMUX_RPA

ISM1 TMUX_RL

OPM1

0x4000E TMUX_RP

OH2_MSK TMUX_RS

FB3M2 TMUX_RS

DB3M2 TMUX_RU

NEQPM2 TMUX_RPLM

PM2 TMUX_RN1

MONM2 TMUX_RK3

MONM2 TMUX_RF3

MONM2 TMUX_RF2

MONM2 TMUX_RR

DIPM2 TMUX_RC2

MONM2 TMUX_RTI

MPM2 TMUX_RN

DFM2 TMUX_RD

ECM2 TMUX_RIN

CM2 TMUX_RPA

ISM2 TMUX_RL

OPM2

0x4000F TMUX_RP

OH3_MSK TMUX_RS

FB3M3 TMUX_RS

DB3M3 TMUX_RU

NEQPM3 TMUX_RPLM

PM3 TMUX_RN1

MONM3 TMUX_RK3

MONM3 TMUX_RF3

MONM3 TMUX_RF2

MONM3 TMUX_RR

DIPM3 TMUX_RC2

MONM3 TMUX_RTI

MPM3 TMUX_RN

DFM3 TMUX_RD

ECM3 TMUX_RIN

CM3 TMUX_RPA

ISM3 TMUX_RL

OPM3

Interrupt Mask Parameters for APSINT Pin—R/W

0x40011 TMUX_AP

S_MSK TMUX_RH

SSF_APSM TMUX_

RHSSD_

APSM

TMUX_

RAPSMON

_APSM

TMUX_

RLAISMON

_APSM

TMUX_

RHSLOS_A

PSM

TMUX_

RHSLOF_A

PSM

TMUX_

RHSOOF_

APSM

TMUX_

RHSILOC_

APSM

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

125Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 143. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

State and Value Parameters—RO

0x40012 TMUX_TX_ST

ATE TMUX_THS

ILOF TMUX_THS

ILOC

0x40013 TMUX_RPS_

STATE TMUX_RP

SLOF TMUX_RP

SOOF TMUX_RP

SILOC

0x40014 TMUX_RHS_

STATE TMUX_RLR

DIMON TMUX_RLA

ISMON TMUX_RH

SLOSEXTI TMUX_RTI

MS TMUX_RH

SSF TMUX_RH

SSD TMUX_RH

SLOS TMUX_RH

SLOF TMUX_RH

SOOF TMUX_RH

SILOC

0x40015 TMUX_RPOH

1_STATE TMUX_RS

FB31 TMUX_RS

DB31 TMUX_RU

NEQP1 TMUX_RPL

MP1 TMUX_RTI

MP1 TMUX_RPA

IS1 TMUX_RL

OP1

0x40016 TMUX_RPOH

2_STATE TMUX_RS

FB32 TMUX_RS

DB32 TMUX_RU

NEQP2 TMUX_RPL

MP2 TMUX_RTI

MP2 TMUX_CONCAT_STATE2

[1:0] TMUX_RPA

IS2 TMUX_RL

OP2

0x40017 TMUX_RPOH

3_STATE TMUX_RS

FB33 TMUX_RS

DB33 TMUX_RU

NEQP3 TMUX_RPL

MP3 TMUX_RTI

MP3 TMUX_CONCAT_STATE3

[1:0] TMUX_RPA

IS3 TMUX_RL

OP3

Receive High-speed Control Parameters—R/W

0x40019 TMUX_RHS_

CTL TMUX_LOS

EXT_LEVE

TMUX_RP

SMUXSEL1 TMUX_THS

2RHSLB TMUX_RH

SDSCR

Receive Low-speed Control Parameters—R/W

0x4001A TMUX_RLS_

BITBLK_CTL TMUX_RCV_SS_EXP[1:0

]TMUX_RC

V_SS_ENB TMUX_BIT

BLKG1 TMUX_BIT

BLKM1 TMUX_BIT

BLKB3 TMUX_BIT

BLKB2 TMUX_BIT

BLKB1

0x4001B TMUX_RLS_

MODE_CTL TMUX_RPA

IS_INS TMUX_8O

RMAJOR-

ITY

TMUX_SD

B1B2SEL TMUX_SFB

1B2SEL TMUX_J1MONMODE[2:0] TMUX_J0MONMODE[2:0] TMUX_S1

MODE4 TMUX_RLS

PAROEG TMUX_

RCONCAT-

MODE

TMUX_

REPRDI_

MODE

0x4001C TMUX_RAISI

NH_CTL TMUX_R_

M1_BIT7 TMUX_

RSDB3_

AISINH

TMUX_RSF

B3_AISINH TMUX_RTIMP_AISINH[3:1] TMUX_

RUNEQP_

AISINH

TMUX_RPL

MP_AISINH TMUX_

RHSSD_

AISINH

TMUX_

RHSSF_

AISINH

TMUX_

RPAISLOP

_AISINH

TMUX_

RLAISMON

_AISINH

TMUX_RL

OF_AISINH TMUX_RO

OF_AISINH TMUX_

RHSLOS_

AISINH

TMUX_RIL

OC_AISINH

0x4001D TMUX_LOSD

ETCNT TMUX_FORCEC2DEF[2:0] TMUX_LOSDETCNT[10:0]

Continuous N-Times Detect Values—R/W

0x4001E TMUX_CNTD

_TOH_A TMUX_CNTDK1K2FRAME[3:0] TMUX_CNTDK1K2[3:0] TMUX_CNTDF1[3:0] TMUX_CNTDJ0[3:0]

0x4001F TMUX_CNTD

_TOH_B TMUX_CTDLOPCNT[1:0] TMUX_CNTDS1FRAME[3:0] TMUX_CNTDS1[3:0] TMUX_CNTDK2[3:0]

0x40020 TMUX_CNTD

_POH_A TMUX_CNTDF2[3:0] TMUX_CNTDRDIP[3:0] TMUX_C2[3:0] TMUX_CNTDJ1[3:0]

0x40021 TMUX_CNTD

_POH_B TMUX_CT

DB1SEL TMUX_CNTDN1[3:0] TMUX_CNTDK3[3:0] TMUX_CNTDF3[3:0]

0x40022 TMUX_C2EX

P1 TMUX_C2EXP1[7:0]

0x40023 TMUX_C2EX

P2_3 TMUX_C2EXP3[7:0] TMUX_C2EXP2[7:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

126 A

ere S

stems Inc.

8 TMUX Registers (continued)

Tabl e 143. TMUX Register Map (continued)

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive Monitor Values—RO

0x40024 TMUX_RF1M

ON TMUX_RF1MON1[7:0] TMUX_RF1MON0[7:0]

0x40025 TMUX_RAPS

MON TMUX_RAPSMON[12:0] TMUX_K2MON[2:0]

0x40026 TMUX_RS1M

ON TMUX_RS1MON[7:0]

0x40027 TMUX_RPOH

MON1A TMUX_RDIPMON1[2:0] TMUX_C2MON1[7:0]

0x40028 TMUX_RPOH

MON1B TMUX_F2MON11[7:0] TMUX_F2MON01[7:0]

0x40029 TMUX_RPOH

MON1C TMUX_F3MON11[7:0] TMUX_F3MON01[7:0]

0x4002A TMUX_RPOH

MON1D TMUX_N1MON1[7:0] TMUX_K3MON1[7:0]

0x4002B TMUX_RPOH

MON2A TMUX_RDIPMON2[2:0] TMUX_C2MON2[7:0]

0x4002C TMUX_RPOH

MON2B TMUX_F2MON12[7:0] TMUX_F2MON02[7:0]

0x4002D TMUX_RPOH

MON2C TMUX_F3MON12[7:0] TMUX_F3MON02[7:0]

0x4002E TMUX_RPOH

MON2D TMUX_N1MON2[7:0] TMUX_K3MON2[7:0]

0x4002F TMUX_RPOH

MON3A TMUX_RDIPMON3[2:0] TMUX_C2MON3[7:0]

0x40030 TMUX_RPOH

MON3B TMUX_F2MON13[7:0] TMUX_F2MON03[7:0]

0x40031 TMUX_RPOH

MON3C TMUX_F3MON13[7:0] TMUX_F3MON03[7:0]

0x40032 TMUX_RPOH

MON4D TMUX_N1MON3[7:0] TMUX_K3MON3[7:0]

Tr ansmit Low-sp eed Control Param eters—R/W

0x40033 TMUX_TLS_C

TL TMUX_TLS_UNEQP[3:1] TMUX_TLS_PAISINS[3:1] TMUX_TLS

VOEPAR

Transm it Hi gh-sp eed Port Contro l Parameters—R/W

0x40034 TMUX_THS_

PORT_CTL TMUX_TPS

MUXSEL3 TMUX_TPS

MUXSEL2 TMUX_RH

S2THSLB TMUX_THS

SCR

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

127Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 143. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transm it Hi g h-speed C ontrol Parameters—R/W

0x40035 TMUX_THS_

TOH_CTL TMUX_TC

ONCAT-

MODE

TMUX_TPR

EIRDISEL TMUX_TLR

EIRDISEL TMUX_TSS[1:0] TMUX_THS

LREIINH TMUX_THS

LAISINS TMUX_THS

APSINS TMUX_THS

K2INS TMUX_THS

S1INS TMUX_THS

F1INS TMUX_THS

Z0INS TMUX_THS

J0INS

0x40036 TMUX_THS_

POH1_CTL TMUX_THS

PREIINH1 TMUX_TP

OHTHRU1 TMUX_THS

N1INS1 TMUX_THS

K3INS1 TMUX_THS

F3INS1 TMUX_THS

F2INS1 TMUX_THS

RDIPINS1 TMUX_THS

C2INS1 TMUX_THS

J1INS1

0x40037 TMUX_THS_

POH2_CTL TMUX_THS

PREIINH2 TMUX_TP

OHTHRU2 TMUX_THS

N1INS2 TMUX_THS

K3INS2 TMUX_THS

F3INS2 TMUX_THS

F2INS2 TMUX_THS

RDIPINS2 TMUX_THS

C2INS2 TMUX_THS

J1INS2

0x40038 TMUX_THS_

POH3_CTL TMUX_THS

PREIINH3 TMUX_TP

OHTHRU3 TMUX_THS

N1INS3 TMUX_THS

K3INS3 TMUX_THS

F3INS3 TMUX_THS

F2INS3 TMUX_THS

RDIPINS3 TMUX_THS

C2INS3 TMUX_THS

J1INS3

Transmit High-speed Line RDI Control Parameters—R/W

0x4003A TMUX_TLRDI

_CTL TMUX_TRS

D_LRDIINH TMUX_TRS

F_LRDIINH TMUX_TRL

AISMON_L

RDIINH

TMUX_TRL

OF_LRDIIN

TMUX_TR

OOF_LRDII

TMUX_TRL

OS_LRDIIN

TMUX_TRI

LOC_LRDII

Transmit High-speed Path RDI Control Parameters—R/W

0x4003B TMUX_TPRDI

_CTL TMUX_TIM_PRDIINH[3:1] TMUX_TRU

EQ_PRDIIN

TMUX_TRP

LM_PRDIIN

TMUX_TRL

OP_PRDIIN

TMUX_TRP

AIS_PRDII

TMUX_TEP

RDI_MODE

Transmit TOH and POH Insert Values—R/W

0x4003C TMUX_TZ0_I

NS_VAL TMUX_TZ03INS[7:0] TMUX_TZ02INS[7:0]

0x4003D TMUX_TS1_F

1_INS_VAL TMUX_TS1INS[7:0] TMUX_TF1INS[7:0]

0x4003E TMUX_TAPS

_INS_VAL TMUX_TAPSINS[12:0] TMUX_TK2INS[2:0]

0x4003F TMUX_TPOH

1_INS_A TMUX_TRDIPINS1[2:0] TMUX_TC2INS1[7:0]

0x40040 TMUX_TPOH

1_INS_B TMUX_TF3INS1[7:0] TMUX_TF2INS1[7:0]

0x40041 TMUX_TPOH

1_INS_C TMUX_TN1INS1[7:0] TMUX_TK3INS1[7:0]

0x40042 TMUX_TPOH

2_INS_A TMUX_TRDIPINS2[2:0] TMUX_TC2INS2[7:0]

0x40043 TMUX_TPOH

2_INS_B TMUX_TF3INS2[7:0] TMUX_TF2INS2[7:0]

0x40044 TMUX_TPOH

2_INS_C TMUX_TN1INS2[7:0] TMUX_TK3INS2[7:0]

0x40045 TMUX_TPOH

3_INS_A TMUX_TRDIPINS3[2:0] TMUX_TC2INS3[7:0]

0x40046 TMUX_TPOH

3_INS_B TMUX_TF3INS3[7:0] TMUX_TF2INS3[7:0]

0x40047 TMUX_TPOH

3_INS_C TMUX_TN1INS3[7:0] TMUX_TK3INS3[7:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

128 A

ere S

stems Inc.

8 TMUX Registers (continued)

Tabl e 143. TMUX Register Map (continued)

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transm it H igh-sp eed Error Insertion Control P arameters—R/W

0x40048 TMUX_TBERI

NS_CTL TMUX_TPS

LREIINS TMUX_TPS

B2EINS TMUX_TPREIINS[3:1] TMUX_THSB3ERRINS[3:1] TMUX_TLR

EIINS TMUX_THSB2ERRINS[3:1] TMUX_THS

B1ERRINS

0x40049 TMUX_THS_

ERR_CTL TMUX_TAP

SBABINS TMUX_TH1H2INVEN[3:1] TMUX_TH1

H2INVORN

TMUX_TA2ERRINS[4:0]

Receive/Transmit TOA C/PO AC Control Paramet ers—R/W

0x4004A TMUX_TOAC

_CTL TMUX_RT

OAC_D412

MODE

TMUX_RT

OAC_D13

MODE

TMUX_

RTOAC_

OEPINS

TMUX_

TTOAC_

D412MODE

TMUX_

TTOAC_

D13MODE

TMUX_TTO

AC_AVAIL TMUX_TTO

AC_S1 TMUX_TTO

AC_F1 TMUX_TTO

AC_E2 TMUX_TTO

AC_E1 TMUX_

TTOAC_

D4TO12

TMUX_TTO

AC_D1TO3 TMUX_

TTOAC_

OEPMON

0x4004B TMUX_RPOA

C_CTL TMUX_RPOAC_

SEL[1:0] TMUX_

RPOAC_

OEPINS

TMUX_TPOAC_SEL[1:0] TMUX_TP

OAC_N1 TMUX_TP

OAC_K3 TMUX_TP

OAC_F3 TMUX_TP

OAC_F2 TMUX_TP

OAC_C2 TMUX_TP

OAC_J1 TMUX_

TPOAC_

OEPMON

Transmit H ig h-sp eed Offset Control Paramet ers—R/W

0x4004D TMUX_TFRA

MEOFFSET TMUX_TLBITCNT[2:0] TMUX_TLSTSCNT[1:0] TMUX_TLCOLCNT[6:0] TMUX_TLROWCNT[3:0]

B1/B2 Signal Degrade Set/Clear Control Registers—R/W

0x4004E TMUX_SD_C

TL1 TMUX_SDNSSET[18:3]

0x4004F TMUX_SD_C

TL2 TMUX_SDMSET[7:0] TMUX_SDLSET[3:0] TMUX_SDNSSET[2:0]

0x40050 TMUX_SD_C

TL3 TMUX_SDBSET[15:0]

0x40051 TMUX_SD_C

TL4 TMUX_SDNSCLEAR[18:3]

0x40052 TMUX_SD_C

TL5 TMUX_SDMCLEAR[7:0] TMUX_SDLCLEAR[3:0] TMUX_SDNSCLEAR[2:0]

0x40053 TMUX_SD_C

TL6 TMUX_SDBCLEAR[15:0]

B1/B2 Signal Fail Set/Cle ar Control Registers—R/W

0x40054 TMUX_SF_C

TL1 TMUX_SFNSSET[18:3]

0x40055 TMUX_SF_C

TL2 TMUX_SFMSET[7:0] TMUX_SFLSET[3:0] TMUX_SFNSSET[2:0]

0x40056 TMUX_SF_C

TL3 TMUX_SFBSET[15:0]

0x40057 TMUX_SF_C

TL4 TMUX_SFNSCLEAR[18:3]

0x40058 TMUX_SF_C

TL5 TMUX_SFMCLEAR[7:0] TMUX_SFLCLEAR[3:0] TMUX_SFNSCLEAR[2:0]

0x40059 TMUX_SF_C

TL6 TMUX_SFBCLEAR[15:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

129Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 143. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

B3 Signal Degrade Set/Clear Control Registers—R/W

0x4005A TMUX_B3SD

_CTL1 TMUX_B3SDNSSET[18:3]

0x4005B TMUX_B3SD

_CTL2 TMUX_B3SDMSET[7:0] TMUX_B3SDLSET[3:0] TMUX_B3SDNSSET[2:0]

0x4005C TMUX_B3SD

_CTL3 TMUX_B3SDBSET[15:0]

0x4005D TMUX_B3SD

_CTL4 TMUX_B3SDNSCLEAR[18:3]

0x4005E TMUX_B3SD

_CTL5 TMUX_B3SDMCLEAR[7:0] TMUX_B3SDLCLEAR[3:0] TMUX_B3SDNSCLEAR[2:0]

0x4005F TMUX_B3SD

_CTL6 TMUX_B3SDBCLEAR[15:0]

B3 Signal Fail Set/Clear Control Registers—R/W

0x40060 TMUX_B3SF_

CTL1 TMUX_B3SFNSSET[18:3]

0x40061 TMUX_B3SF_

CTL2 TMUX_B3SFMSET[7:0] TMUX_B3SFLSET[3:0] TMUX_B3SFNSSET[2:0]

0x40062 TMUX_B3SF_

CTL3 TMUX_B3SFBSET[15:0]

0x40063 TMUX_B3SF_

CTL4 TMUX_B3SFNSCLEAR[18:3]

0x40064 TMUX_B3SF_

CTL5 TMUX_B3SFMCLEAR[7:0] TMUX_B3SFLCLEAR[3:0] TMUX_B3SFNSCLEAR[2:0]

0x40065 TMUX_B3SF_

CTL6 TMUX_B3SFBCLEAR[15:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

130 A

ere S

stems Inc.

8 TMUX Registers (continued)

Tabl e 143. TMUX Register Map (continued)

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive B1, B2, B3, M1, G1, and N1 Error Counts—RO

0x40066 TMUX_B1EC

NT TMUX_B1ECNT[15:0]

0x40067 TMUX_B2EC

NT_17_16 TMUX_B2ECNT[17:16]

0x40068 TMUX_B2EC

NT_15_0 TMUX_B2ECNT[15:0]

0x40069 TMUX_B3EC

NT1 TMUX_B3ECNT1[15:0]

0x4006A TMUX_B3EC

NT2 TMUX_B3ECNT2[15:0]

0x4006B TMUX_B3EC

NT3 TMUX_B3ECNT3[15:0]

0x4006C TMUX_M1EC

NT_17_16 TMUX_M1ECNT[17:16]

0x4006D TMUX_M1EC

NT_15_0 TMUX_M1ECNT[15:0]

0x4006E TMUX_G1EC

NT1 TMUX_G1ECNT1[15:0]

0x4006F TMUX_G1EC

NT2 TMUX_G1ECNT2[15:0]

0x40070 TMUX_G1EC

NT3 TMUX_G1ECNT3[15:0]

Receive Pointer Increment and D ecrement Counts—RO

0x40074 TMUX_RPTR

_INCCNT1 TMUX_RPTR_INC1[10:0]

0x40075 TMUX_RPTR

_INCCNT2 TMUX_RPTR_INC2[10:0]

0x40076 TMUX_RPTR

_INCCNT3 TMUX_RPTR_INC3[10:0]

0x40077 TMUX_RPTR

_DECCNT1 TMUX_RPTR_DEC1[10:0]

0x40078 TMUX_RPTR

_DECCNT2 TMUX_RPTR_DEC2[10:0]

0x40079 TMUX_RPTR

_DECCNT3 TMUX_RPTR_DEC3[10:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

131Agere Sy stem s Inc.

8 TMUX Registers (continued)

Table 143. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Expected J0 Receive Value—R/W

0x400A0

—

0x400A7

TMUX_RJ0EX

PECTED

[1—8]

TMUX_EXPJ0DMON[2][7:0]

—

TMUX_EXPJ0DMON[16][7:0]

TMUX_EXPJ0DMON[1][7:0]

—

TMUX_EXPJ0DMON[15][7:0]

Captured J0 Receive Value—RO

0x400A8

—

0x400AF

TMUX_RJ0C

APTURED

[1—8]

TMUX_J0DMON[2][7:0]

—

TMUX_J0DMON[16][7:0]

TMUX_J0DMON[1][7:0]

—

TMUX_J0DMON[15][7:0]

J0 Byte Transmit Insert—R/W

0x400B0

—

0x400B7

TMUX_TJ0VA

LUE[1—8] TMUX_TJ0DINS[2][7:0]

—

TMUX_TJ0DINS[16][7:0]

TMUX_TJ0DINS[1][7:0]

—

TMUX_TJ0DINS[15][7:0]

Expected J1 Receive Value for STS #1—R/W

0x400E0

—

0x400FF

TMUX_RJ1EX

PECTED_1

[1—32]

TMUX_EXPJ1DMON1[2][7:0]

—

TMUX_EXPJ1DMON1[64][7:0]

TMUX_EXPJ1DMON1[1][7:0]

—

TMUX_EXPJ1DMON1[63][7:0]

Expected J1 Receive Value for STS #2—R/W

0x40100

—

0x4011F

TMUX_RJ1EX

PECTED_2

[1—32]

TMUX_EXPJ1DMON2[2][7:0]

—

TMUX_EXPJ1DMON2[64][7:0]

TMUX_EXPJ1DMON2[1][7:0]

—

TMUX_EXPJ1DMON2[63][7:0]

Expected J1 Receive Value for STS #3—R/W

0x40120

—

0x4013F

TMUX_RJ1EX

PECTED_3

[1—32]

TMUX_EXPJ1DMON3[2][7:0]

—

TMUX_EXPJ1DMON3[64][7:0]

TMUX_EXPJ1DMON3[1][7:0]

—

TMUX_EXPJ1DMON3[63][7:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

132 A

ere S

stems Inc.

8 TMUX Registers (continued)

Tabl e 143. TMUX Register Map (continued)

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Captured J1 Receive Value for STS #1—RO

0x40140

—

0x4015F

TMUX_RJ1C

APTURED_1

[1—32]

TMUX_J1DMON1[2][7:0]

—

TMUX_J1DMON1[64][7:0]

TMUX_J1DMON1[1][7:0]

—

TMUX_J1DMON1[63][7:0]

Captured J1 Receive Value for STS #2—RO

0x40160

—

0x4017F

TMUX_RJ1C

APTURED_2

[1—32]

TMUX_J1DMON2[2][7:0]

—

TMUX_J1DMON2[64][7:0]

TMUX_J1DMON2[1][7:0]

—

TMUX_J1DMON2[63][7:0]

Captured J1 Receive Value for STS #3—RO

0x40180

—

0x4019F

TMUX_RJ1C

APTURED_3

[1—32]

TMUX_J1DMON3[2][7:0]

—

TMUX_J1DMON3[64][7:0]

TMUX_J1DMON3[1][7:0]

—

TMUX_J1DMON3[63][7:0]

J1 Byte Transmit Insert for STS #1—R/W

0x401A0

—

0x401BF

TMUX_TJ1VA

LUE_1

[1—32]

TMUX_TJ1DINS1[2][7:0]

—

TMUX_TJ1DINS1[64][7:0]

TMUX_TJ1DINS1[1][7:0]

—

TMUX_TJ1DINS1[63][7:0]

J1 Byte Transmit Insert for STS #2—R/W

0x401C0

—

0x401DF

TMUX_TJ1VA

LUE_2

[1—32]

TMUX_TJ1DINS2[2][7:0]

—

TMUX_TJ1DINS2[64][7:0]

TMUX_TJ1DINS2[1][7:0]

—

TMUX_TJ1DINS2[63][7:0]

J1 Byte Transmit Insert for STS #3—R/W

0x401E0

—

0x401FF

TMUX_TJ1VA

LUE_3

[1—32]

TMUX_TJ1DINS3[2][7:0]

—

TMUX_TJ1DINS3[64][7:0]

TMUX_TJ1DINS3[1][7:0]

—

TMUX_TJ1DINS3[63][7:0]

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
133Agere Systems Inc.  
9 SPE Mapper Registers
Ta ble of Conte nts
Contents Page
9 SPE Mapper Registers ..................................................................................................................................... 133
9.1  SPE Mapper Register Desc riptions  .. ......................... . ......................... . ......................... . ........................... 134
9.2  SPE Mapper Register M ap ................................. . .............................. ........................................................ 149
Contents Page
Ta ble  144. SPE_VER SIO N _ R , SPE Versi o n an d Identification Register (RO) ......... . .................. . .................. .... 134
Tab le 145. SPE_ONESHOT, One-Shot (R/W) ....................................................................................................1 34
Table 146.  SPE_EVENT1 —SPE_EVENT3, SPE Delta s/Events (COR/ COW) ......................... ..........................134
Table 1 47. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) ................................................................................ 136
Table 148. S PE_STATE 1—SPE _STA T E2, Receive/Transm it S t ate and Value Paramet ers  (RO)  .................... 137
Table 1 49. SPE_RAOH_CTL1—SPE _RA OH_CTL3, Receive Control for Alarm and OH Functions (R/W) . ... ... 138
Table 150.  SPE_CNTD1—SPE_ CNTD2, C ontinuous N-Times Detect  Values (R/W) . ............................... ........139
Table 151. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W)  ......... ..... .. .......... .. ..... ....... ..... 140
Table 1 52. SPE_RMON1—SPE_RMON5, Receive Mon itor Values (RO) .......................................................... 1 40
Table 1 53. SP E_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) ........................140
Table 154. S PE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) .......................1 43
Table 155. SPE_TRDIREI_CTL, Transmi t Path RDI and REI Control Regi ster (R/W) .......................................1 45
Table 156. SPE_TERRINS_CTL, Transmit Erro r Insertio n Control (R/W) .......................................................... 145
Table 157. SPE_TOHINS1—SPE_TOHINS4, Transm it OH Insert Value (R/W) ................................................ 1 45
Table 1 58.  SPE_SIGDEG_CTL1—SPE_SIG DE G_CTL6, Signal Degrade BER Algorithm Parameters (R/W) .. 146
Table 159. S PE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Sign al Fail  BER Alg orithm Parameters (R/W) ..........1 46
Table 160.  SPE_ERRCNT1—SPE_ERRCNT6, B 3, G1, Bipol ar Viol ation, and Ex cess 
Zero Error Count (RO) ....................................................................................................................... 147
Table 161.  S P E_ PTRCNT1 —SPE_PTRCNT3, Rece ive Pointer Increment and Decrement Count  (RO) ..........1 47
Table 1 62.  SPE_R J1 MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO) .................................. 147
Table 163. SPE_ TJ1DI NS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W) ................................... 1 48
Table 164.  SPE_RJ1DEXP_R1—SPE_ RJ1DEXP_R32 , Receive J1 Expected Values (R/W) ........................... 148
Table 1 65. SPE_SCRATCH_R, Scratch Pad (R/W)  ........................................................................................... 148
Table 1 66.   SPE Mapper Register Map .. ....................... . ....................... .......................... ..................................... 149

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

134 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

9.1 SPE Ma pper Regis ter Descr iptions

This section gives a brief de scription of each register bit and its functionalit y. The abbreviations after each register

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/writ e (R/W) .

Table 144. SPE_VERSION_R, SPE V e r sion and Identification Register (RO)

Table 1 45. SP E_ONESHOT, One-Shot (R/W)

Note: In Table 122, the mask bits for these delta and event bits are in Table 147, state bits are in Table 148, and

monitor values are in Table 152.

Address Bit Name F un ction Reset

Default

0x30000 15:11 —Reserved. 0x00

10:8 SPE_VERSION[2:0] Block Versi on Number. Block version register will change

each time the device is changed. 0x0

7:0 SPEMPR_ID[7:0] Bloc k ID N umber. 0x03

Address Bit Name F un ction Reset

Default

0x30002 15:5 —Reserved. 0x000

4 SPE_BIPOL_ERR Bipolar Violation Error. A single bipolar violation error f or

DS3 output is transmitted each time this bit transitions from a

0 to 1.

3 SPE_SFCLEAR Signal Fail Clear. A llows the signal f ail algorithm to be f orced

into the normal state. 0

2 SPE_SFSET Signal Fail Set. Allows the signal fail algorithm to be forced

into the fail ed state. 0

1 SPE_SDCLEAR Signal Degrade Clear. Allows the signal degrade algo ri thm

to be forced into the normal state. 0

0 SPE_SDSET Signal Degrade Set. Allows t he signal degrade algorithm to

be forced into the degraded state. 0

Table 146. SPE_EVENT1—SPE_E VENT3, SP E Deltas/Ev e nts (COR/COW)

Address Bit N am e Function Reset

Default

0x30003 15:7 —Reserved. 0x000

6 SPE_RDATA_PE Received Data Parity Error Event. Event bit ind icates a parity

error was detected on the incoming data. 0

5 SPE_TPOAC_PE Transmit PO A C Parity Err or Event. Ev ent bit indicates a parity

error was detected on the incoming POAC. 0

4 SPE_K3DMOND K3 Data Monitor Delta Bit. The mask b it is SPE_K3DM ONM. 0

3 SPE_N1DMOND N1 Data Monitor Delta Bit. The mask bit is SPE_N1DMONM. 0

2 SPE_C2DMOND C2 Data Monitor Delta Bit. The mask bit is SPE_C2DMONM. 0

1 SPE_F2DMOND F2 Data Monito r Delta Bit. The mask bit is SPE_F 2DMONM. 0

0 SPE_F3DMOND F3 Data Monito r Delta Bit. The mask bit is SPE_F 3DMONM. 0

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

135Agere Systems In c.

0x30004 15:11 —Reserved. 0x00

10 SPE_PRDIDMOND Path RDI Delta. Delta bit indicates a change of state for the

path RDI state bit SPE_PRDIDMON. The delta bit is cleared

when read. The mask bit for this delta bit is

SPE_PRDIDMONM.

9 SPE_RNDFE Pointer Interpreter New Data Flag Event Bit. The mask bit is

SPE_RNDFM. 0

8 SPE_RDECE Pointer Interpreter Decrement Event Bit. The mask bit i s

SPE_RDECM. H oweve r, increment and decrement event indi-

cations should be ignored durin g LOP condition.

7 SPE_RINCE Pointer Interpreter I ncrement Event Bit. The mask bit is

SPE_RINCM. However, incremen t and dec rement event indica-

tions should be ignored du ring LOP condition.

0x30004 6 SPE_RAISD Delta Bit for the AIS Alarm Detect State Bit. The mask bit i s

SPE_RAISM. 0

5SPE_RLOPDDelta Bit for the Loss of Pointer Alarm State Bit. The mask

bit is SPE_RLOPM. 0

4 SPE_SFB3D Signal Fail BE R Algori thm D el t a. Indicates a change of s tate

for the signal fail BER algorithm state bit SFB3. This bit c lear s

when rea d. The mask bit i s SPE_SFB3 M.

3 SPE_SDB3D Signa l Degrade BER A lgorithm D elt a. Indicates a change of

state for the signal degrade BER algorit hm state bit SDB3. This

bit clears when read. The mask bit i s SPE_SDB3M.

2 SPE_RUNEQD Delta Bit for the Unequipp ed Alarm State Bit. T h e m as k bit i s

SPE_RUNEQM. 0

1 SPE_RPLMD Del ta Bit for the Payload Label Mismatch Alarm S tate Bit.

The mask bit is SPE_RPLM M . 0

0 SPE_RTIMD Trace Indicator M ismatch Event Bit (J1 Byte). The mask bit is

SPE_RTIMM. 0

0x30005 15 —Reserved. 0

14 SPE_RSY52LOSD Delta Bit for Loss of Sync 52 Signal from Tele c om Bus. 0

13 SPE_RV1LOSD Delta Bit for Loss of V1 Sync Signal fr om T elecom Bus. 0

12 SPE_RSPELOSD Delta Bit for Loss of SPE Sync Signal from Te lecom Bus. 0

11 SPE_RJ0J1V1LOSD Delta Bit for Loss of J0J1V1 Sync Signal from T elecom Bus. 0

10 SPE_RDS3LOCD Delta Bit for Loss of DS3 External Clock from External P in. 0

9 SPE_RC52LOCD Delta Bit for Loss of 52 MHz Clock from Telecom Bus. 0

8 SPE_RLSLOCD Delta Bit for Los s of 19 MH z Clock from Telecom Bus. 0

7—Reserved. 0

6 SPE_TSY52LOSD Delta Bit for Lo ss of Sy nc 52 Signal from Telecom Bus. 0

5 SPE_TV1LOSD Delta Bit for Loss of V1 Sync Signal from Telecom Bus. 0

4 SPE_TSPELOSD Delta Bit for Loss of SPE Syn c Signal from Teleco m Bus. 0

3 SPE_TJ0J1V1LOSD Delta Bit for Loss of J0J1V1 Sync Signal from T elecom Bus. 0

2 SPE_TDS3LOCD Delta Bit for Loss of DS3 External Clock from External Pin. 0

1 SPE_TC52LOCD De lta B it for L oss of 52 M Hz Clock from Telecom Bus. 0

0 SPE_TLSLOCD Delta Bit for Loss of 19 M Hz Clock from Telecom Bus. 0

Table 146. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW) (continued)

Address Bit Nam e Function Reset

Default

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

136 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 147. SPE_MASK1—SPE_MAS K3, Mask Bi ts (R/W)

Address Bi t Nam e Function Reset

Default

0x30006 15:7 —Reserved. 000000

000

6 SPE_RDATA_PM Received Data Parity Error Mask. Active-high. 1

5 SPE_TPOAC_PM Transmit P OAC Parity Error Mask. Active-high. 1

4 SPE_K3DMONM K3 Data Monitor Mask Bit. Active-high. 1

3 SPE_N1DMONM N1 Data M onitor Mask Bit. Active-high. 1

2 SPE_C2DMONM 1C2 Data Monitor Mask Bit. Active-high.

1 SPE_F2DMONM 1F2 Dat a Monitor Mas k B it. Active-high.

0 SPE_F3DMONM F3 Data Monitor Ma sk Bit. Active-high. 1

0x30007 15:11 —Reserved. 00000

10 SPE_PRDIDMONM Path RDI Mask Bit. Active-high. 1

9 SPE_RNDFM Pointer Interpreter Ne w Data Flag Mask Bit. Active-high 1

8 SPE_RDECM Pointer In te rpreter Decremen t Mask Bit. Active-high. 1

7 SPE_RINCM Pointer Interpreter Increment Mask Bit. Active-high 1

6 SPE_RAISM Mask Bit for the AI S Alarm Detect State Bit. Active-high. 1

5 SPE_RLOPM Mask Bit for the Loss of Pointer Alarm State Bit. Active-

high. 1

4 SPE_SFB3M Signal Fail Mask Bit. Active-high. 1

3 SPE_SDB3M S ignal Degrade Mask Bit. Active-high. 1

2 SPE_RUNEQM Mask Bit for the Unequipped Alarm State Bit. Active-high. 1

1 SPE_RPLMM Mask Bit for the Pa yload Label Mismatch Alarm State Bit.

Active-high. 1

0 SPE_RTIMM Trace Indicator Mismatch Mask Bits. Active-high. 1

0x30008 15 —Reserved. 0

14 SPE_RSY52LOSM Mask Bit for L oss of Sync 52 Signa l fro m Telecom Bus.

Active-high. 1

13 SPE_RV1LOSM Mask Bit for Loss of V1 Sync Signal from Telecom Bus.

Active-high. 1

12 SPE_RSPELOSM Mask Bit for Loss o f SPE Sync Signal from Tele com Bus.

Active-high. 1

11 SPE_RJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. Active-high. 1

10 SPE_RDS3LOCM Mask Bit for Loss of DS3 Exter nal C lock from External

PIN. Active-high. 1

9 SPE_RC52LOCM Mask Bit for Loss of 52 MHz Clock from Te leco m Bus.

Active-high. 1

8 SPE_RLSLOCM Mask Bit for Loss of 19 M H z Cl ock from Telecom Bus.

Active-high. 1

7—Reserved. 0

6 SPE_TSY52LOSM M ask Bit for Loss of Sync 5 2 Signal from Telecom Bus.

Active-high. 1

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

137Agere Systems Inc.

9 SPE Mapper Registers (continued)

Table 147. SPE_MASK1—SPE_MAS K 3, Mask Bits (R/ W) (continued)

Table 1 48. SPE_STATE1 —SPE_STATE2, Receive/Transmit State and Value Parameters (RO)

Address Bit Name F un ction Reset

Default

0x30008 5 SPE_TV1LOSM Mask Bit fo r Loss of V1 Syn c S ig nal fro m Telecom Bus.

Active-high. 1

4 SPE_TSPELOSM Mask Bit for Loss of SPE Sync Signal from Telecom

Bus. Active-high. 1

3 SPE_TJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal fr om Telecom

Bus. Active-high.

2 SPE_TDS3LOCM Mask Bit for Loss of DS3 Ex te rnal Clock from Extern al

PIN. Active-high. 1

1 SPE_TC52LOCM Mask Bit for Loss of 52 MHz Clock from Telecom Bus.

Active-high. 1

0 SPE_TLSLOCM M ask Bi t for Loss of 19 MHz Clock from Telecom Bus.

Active-high. 1

Address Bit Name F un ction Reset

Default

0x30009 15:7 —Reserved. 0x000

6 SPE_RAIS Path AIS State Bit. 0

5 SPE_RLOP Path Loss of Pointer State Bit. 0

4 SPE_SFB3 Signal Fai l State Bit. 0

3SPE_SDB3Signal Degrade State Bit. 0

2 SPE_RUNEQ Path Unequipped State Bit. 0

1 SPE_RPLM Path Payload Label Mismatch State Bit. 0

0SPE_RTIMPath Trace Indicator Mismatch State Bit. 0

0x3000A 15 —Reserved. 0

14 SPE_RSY52LOS State Bit for Loss of Sync 52 Signal from Tele com Bus. 0

13 SPE_RV1LOS State Bit for Loss of V1 Sync S i gn al fro m Telecom Bus. 0

12 SPE_RSPELOS State Bit for Loss of SP E Sync Signal from Telecom Bu s. 0

11 SPE_RJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Tel ecom

Bus. 0

10 SPE_RDS3LOC State Bit for Loss of DS3 Exter nal Clock from External

PIN. 0

9 SPE_RC52LOC State Bit for Loss of 52 MHz Clock from Telecom Bus. 0

8 SPE_RLSLOC State Bit for Loss of 19 MHz Clock from Telecom Bus. 0

7—Reserved. 0

6 SPE_TSY52LOS S tate Bit for Loss of Sync 52 Signal from Telecom Bus. 0

5 SPE_TV1LOS State Bit for Loss of V1 S ync Signal fro m Telecom Bu s. 0

4 SPE_TSPELOS State Bit for L oss o f SPE Sync Signal from Telecom Bus. 0

3 SPE_TJ0J1V1LOS State Bit for L oss of J0J1V1 S ync Signal from Telecom

Bus. 0

2 SPE_TDS3LOC St ate Bit for Loss of DS3 Exter nal Cl ock from External

Pin. 0

1 SPE_TC52LOC State Bit for Loss of 52 MHz Clock from Telecom Bus. 0

0 SPE_TLSLOC State Bit for Loss of 19 MHz Clock from Telecom Bus. 0

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

138 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

)

Table 149. SPE_RAOH_CTL1—SPE_RAOH_C T L3 , Recei v e Control fo r Ala r m an d OH Function s (R/W )

Address Bit Nam e F unc tion Reset

Default

0x3000B 15:8 —Reserved. 0x00

7 SPE_RD_OEPAR Received Data Odd/Even Parity Check. If 0, odd parity

check for received data; if 1, even p arity check. 0

6:4 SPE_J1MONMODE[2:0] J1 Monitoring Mode. There ar e f our monitoring modes

as defined in the do cument. 000

3 SPE_RPRDI_MODE Receive ERDI Mode. When 1, 3-bit enhanced ERDI

mode is supported; when 0, the 1-bi t RDI mode is

supported.

2 SPE_G1BITBLKCNT G1 Error Count in Bit or Bl oc k. When 0, G1(7:4)

check logic will count bit errors; otherwise, it counts

bl ock errors.

1 SPE_B3BITBLKCNT B3 Error Count in Bit or Block. When 0, B3 check

logic wi ll co unt bit errors; otherw ise, it count s blo ck

errors.

0 SPE_RPOAC_OEPINS Rece ive POAC Odd or Even Parity Insert. When 1,

the out put POAC p arit y bit is ev e n; ot he rwi se, the parity

is odd.

0x3000C 15:12 —Reserved. 0x0

11:10 SPE_CNTDLOPCNT[1:0] Continuous N-Times Detect for Loss o f Pointer. Two

bit programmable integration constant for the pointer

interpreter.

9—Reserved. 0

8 SPE_8ORMAJORITY TU- 3 Pointer Interpreter Mode Control. When 1, the

pointer interpret er transitions into the INC and DEC

states based on 8 of the 10 I and D bits. Otherwise, the

pointer interpret er transitions into the INC and DEC

states based on majority rule.

7 SPE_PAISINS Path AIS Software Insertion. When 1, path AIS

insertion is enabled. 0

6 SPE_PAIS_AISINH Pa th AIS Stat e bi t I n hi bi t Sig nal for Gene rati ng Path

AIS. When 1, the inhibit is on. 0

5 SPE_PAIS_LOPINH Loss of Pointer Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on. 0

4 SPE_PAIS_SFB3INH Sign a l Fail I nhibi t Sign al for G e ne r a ting P ath AIS.

When 1, the inhibit is on. 0

3 SPE_PAIS_SDB3INH Signal Degrade Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on. 0

2 SPE_PAIS_UNEQINH Path Unequipped Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on. 0

1 SPE_PAIS_PLMINH Path Label Mismatch Inhibit Signal for Generating

Path AIS. When 1, the inhi bit is on. 0

0 SPE_PAIS_TIMINH Path Trace Indicator Mismatch Inhibit Signal for

Generating Path AIS. When 1, the inhibit is on. 0

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

139Agere Systems In c.

Table 150. SPE_CNTD1—SPE _CNTD2, Continuous N-Times Detect Values (R/W)

0x3000D 15:7 —Reserved. 0x000

6 SPE_AIS_LOSSY52INH Loss of Sync 52 State Bit In hibi t Sign a l fo r Generat-

ing P at h AIS. When 1, the inhibit is on. 0

5 SPE_AIS_LOSV1INH Loss of V1 Sync Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on. 0

4 SPE_AIS_LOSSPEINH Loss of S PE Sy nc Inhibi t Sign a l for Ge ne rat ing Path

AIS. When 1, the inhibit is on. 0

3 SPE_AIS_LOSJ0J1V1INH Loss of J0J1V1 Sync Inhibit Signal for Generatin g

Path AIS. When 1, the inhibit is on. 0

2 SPE_AIS_LOCDS3INH Loss of Ext D S3 Clock Inhibit Signal for G e ne rat ing

Path AIS. When 1, the inhibit is on. 0

1 SPE_AIS_LOC52INH Loss of 52 MHz Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

0 SPE_AIS_LOCINH Loss of 19 MHz Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

Address Bit Nam e Fun ction R eset

Default

0x3000F 15:12 SPE_CNTDC2[3:0] Continuous N-Times Detect for C2 Byte. The valid range

f or this register is 0x3—0xF. Inv alid values will be mapped to

a value of 0x3.

0x3

11:8 SPE_CNTDF3[3:0] C ontinuous N-Times Detect for F3 Byte. The valid range

f or this register is 0x3—0xF. Inv alid values will be mapped to

a value of 0x3.

0x3

7:4 SPE_CNTDF2[3:0] Contin uous N -Times Detect for F2 By te . The valid range

f or this register is 0x3—0xF. Inv alid values will be mapped to

a value of 0x3.

0x3

3:0 SPE_CNTDJ1[3:0] Continuo us N-Times Detect fo r J1 Bytes. The valid range

f or this register is 0x3—0xF. Inv alid values will be mapped to

a value of 0x3.

0x3

0x30010 15:12 SPE_CNTDN1[3:0] Continuous N-Times Detect for N1 Byte. The valid range

f or this register is 0x3—0xF. Inv alid values will be mapped to

a value of 0x3.

0x3

11:8 SPE_CNTDPRDI[3:0] Co ntinuous N-Tim es Detect for G1 Byte. The valid range

f or this register is 0x3—0xF. Inv alid values will be mapped to

a value of 0x3.

0x3

7:4 SPE_CNTDK3[3:0] Continuous N-Times Detect for K3[6:4] Byte . The valid

range for this register is 0x 3—0xF. Inval i d val u es will b e

mapped to a value of 0x3.

0x3

3:0 —Reserved. 0x0

Table 149. SPE_RAOH_CTL1—SPE_RAOH_CTL3, R eceive Control for Alarm a nd OH Functio ns (R /W)

Address Bit Nam e F un ction Reset

Default

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

140 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 151. SPE_ROHC2, Receive Overhead Expected Value f or C2 Byte (R/W)

Table 152. SPE_RMON1—SPE_RMON5, Receive Monitor Values (RO)

Address Bit Name F un ction Reset

Default

0x30011 15:8 —Reserved. 0x00

7:0 SPE_C2DEXP[7:0] Programmable Expected Value for C2 Byte. The

prog rammed value is checked against the actual rec eived

value to determine payload label mis m at ch e r r or .

0x00

Address Bit Name Function Reset

Default

0x30012 15:3 —Reserved. 0x000

2:0 SPE_PRDIDMON[2:0] Received Byte G1[3:1] Monitor Value. 0x0

0x30013 15:8 SPE_N1DMON[7:0] Received Byte N1[7:0] Monitor Value. 0x00

7:0 SPE_K3DMON[7:0] Received Byte K3[7:0] Monitor Value. 0x00

0x30014 15:8 SPE_F2DMON1[7:0] Received Byte F2[7:0] Previous Mon itor Value. 0x00

7:0 SPE_F2DMON0[7:0] Received Byte F2[7:0] Current Monitor Value. 0x00

0x30015 15:8 SPE_F3DMON1[7:0] Received Byte F3[7:0] Previous Mon itor Value. 0x00

7:0 SPE_F3DMON0[7:0] Received Byte F3[7:0] Current Monitor Value. 0x00

0x30016 15:8 —Reserved. 0x00

7:0 SPE_C2DMON[7:0] Received Byte C2[7:0] Monitor Value. 0x00

Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W)

Address Bit Name Function Reset

Default

0x30018 15 SPE_T_STS1_MODE Transmi t STS-1 Mode . When 1, S TS-1 mod e is

selected for transmit data; when 0, STS-3/STM-1. 0

14 SPE_T_NSMI_MODE Tran smit Serial STS-1 SPE Mode. When 1, serial

data is ac c epted through an external serial interface

and mapped to STS-1 SP E.

13:12 SPE_TDS3SRCTYP[1:0] Transmit DS 3 Source Type. Two bit value selects one

of three DS3 input sources.

00 or 01 = DS3 data from M13 block.

10 = DS3 data from loopback (Rx to Tx).

11 = DS3 data from external clear channel.

11 SPE_T_VT_DS3 Transmit VT or DS3 In put. When 1, VT input data is

selected; when 0, DS3 input data is selected. 0

10 SPE_T_AU3_TUG3 Transmit AU-3/STS -1 or TUG-3 Mappin g. When 1,

AU-3/STS-1 mapping is selected; when 0, TUG-3 map-

ping is selected.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

141Agere Systems In c.

0x30018 9:8 SPE_TSTS3TMSLOT[1:0] Tra nsmit S TS-3 Time-Slot Va lue. Two-bit value

selects one of three STS-1 time slots with in an STS-3

in the transmit direction.

00 = No output .

01 = STS-1/ TUG-3 data for slot 1 in STS-3/STM-1.

10 = STS-1/ TUG-3 data for slot 2 in STS-3/STM-1.

11 = STS-1/ TUG-3 data for slot 3 in STS-3/STM-1.

7 SPE_R_STS1_MODE Receive STS- 1 Mode. When 1, STS-1 mode is

selected for receive data. W hen 0, STS-3/STM-1. 0

6 SPE_R_NSMI_MODE Recei v e Serial STS-1 SPE Mode. When 1, serial data

demapped from STS-1 SPE is sent out to an ex ternal

serial interface.

5:4 SPE_RDS3OUTTYP[1:0] Rece ive DS 3 Output Typ e. Two-bit value selects o ne

of th ree D S 3 output dev i ces.

00 or 01 = DS3 data to M13 block.

10 = DS3 data to loopback (RX to TX).

11 = DS3 data to external clear channel .

3SPE_R_VT_DS3Receive VT or D S3 Outp u t . When 1, VT data is out-

put; when 0, DS3 data is output. 0

2 SPE_R_AU3_TUG3 Receive AU-3/STS-1 or TUG-3 Demapping. When 1,

AU-3/STS-1 demapping is selected; when 0, TUG-3

demapping is selected.

1:0 SPE_RSTS3TMSLOT[1:0] Receive STS-3 Time Slot. Sel ec ts one of three ST S-1

time slots within an STS-3/STM-1 frame in the receive

direction.

00 = No selection.

01 = STS-1/ TUG-3 data from slot 1 in STS-3/STM-1 .

10 = STS-1/ TUG-3 data from slot 2 in STS-3/STM-1 .

11 = STS-1/ TUG-3 data from slot 3 in STS-3/STM-1 .

0x30019 15:13 SPE_T_NSMI_BIT[2:0] Transmit S e rial Syn c Position Within a Byte Bound-

ary. Selects one of eight posit ions f or t he bit sync of the

serial transmit data stream (previously known as the

NSMI interface data).

0x0

12:10 SPE_R_NSMI_BIT[2:0] Receive Serial Sync Posit ion Within a Byte Bound-

ary. Selects one of eight posit ions f or t he bit sync of the

serial receive data stream (previously known as the

NSMI interface data).

0x0

9:6 —Reserved. 0x0

5 SPE_TDS3CLK_EDGE External DS3 Clock Edge Select for DS3 Input Data

Retiming.

0 = Negative edge is selected.

1 = Positive edge is selected.

0x0

Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Cont rol for Mapping Functions (R/W) (continued)

Address Bit N am e Function R eset

Default

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

142 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 153. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W ) (continued)

Address Bit Name Function Reset

Default

0x30019 4 SPE_PHDETUP_INV Phase Detector Up Signal In vert. When 1, the phase

detector up signal requ ired for an external PLL in DS3

mode, is inverted from its current phase.

0x0

3 SPE_PHDETDN_INV Phase Detector Down Signal Invert. W hen 1, the

phase detector down signal required for an exte rnal

PLL in DS3 mode, is inverted from its current phase.

0x0

2 SPE_TDS3BPV_IN Transmit DS3 BP V/Data In. When 1, DS3NEGDATAIN

(K22) i nput pin i s used a s e xternal B3ZS bipolar viola-

tion indication instead of negative input pul se.

0x00

1 SPE_TDS3_BIPOLAR Transmit DS3 Bip olar/Unipolar. When 1, the DS3

inp u t is bipola r; when 0, the DS 3 input is unipolar. 0x00

0 SPE_RDS3_BIPOLAR Receive DS3 Bipolar/Unipolar. When 1, the DS3 out-

put is bipolar; when 0, the DS3 o utput is unipolar. 0x00

0x3001A 15 —Reserved.

14:8 SPE_T_NSMI_COL[6:0] Transm it Serial S ync Position . Selects one of

90 positions al igned with 90 SONET columns wit hin

SONET row 9 for the bit sync of the serial transmit data

stream (previously known as the NSMI interface d ata).

0x0

7—Reserved.

6:0 SPE_R_NSMI_COL[6:0] Receive Se rial S ync Po sition . Selects one of 90 posi-

tions aligned with 90 SONET columns within SONET

row 9 for the bit sync of the serial transmit dat a str eam

(prev iously kn own as the N SMI interface data).

0x0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
143Agere Systems Inc.  
9 SPE Mapper Registers (continued)
Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W)
Address Bit Name Function Reset 
Default
0x3001B 15:10 —Reserved. 0x00
9 SPE_TD_OEPAR Transmit Data Odd/Even Parity Gene rate. Whe n 0, odd 
par ity is generated for transm it data; when 1, even pa rity is 
generated.
00
8 SPE_ TREIRDISEL REI and RDI Input Select. Control bit, when 1, inserts 
REI/RDI val ue from the protected channel REI/RD I l in es ; 
otherwise, the  v a l u e is inserted from the direct  feedback 
(receive to trans mit) lines.
0
7 SPE_TAISPINS Force Path AIS in the Output. Active-high. 0
6SPE_TN1INSTransmi t N1 In ser t Con trol. Control bit, when 1, inserts 
the value i n SPE_TN1DINS[7:0] (Table 157) i nto the outgo-
ing N1 byte in the ST S-1 frame; otherwis e, the insert value 
depends  on SPE_TPOAC_N1 (Table 154) control bit.
1
5 SPE_TK3INS Tran sm it K3 In sert Control. Control bit, when 1, insert s 
the value i n SPE_TK3DINS[7:0] (Table 157) into the  outgo-
ing K3 bytes; otherwise, the inse r t value depends on 
SPE_TPOAC_K3 (Table 154) control bit.
0
4SPE_TH4INSTransmi t H4 In ser t Con trol. Control bit, when 1, inserts 
the overhead default value SMPR_OH_ DEFLT (Table 67) 
into the outgoing H 4 by te s; otherwise, t he insert value 
depends  on SPE_TPOAC_H4 (Table 154) control bit.
0
3  SPE_TF3INS Tran sm it F3 Inser t Control. Control bit, when 1, inserts 
the value i n SPE_TF3DINS[7:0] (Table 157) into the outgo-
ing F3 byte in the STS- 1 frame; otherwise, the ins ert  value 
depends  on SPE_TPOAC_F3 (Table 154) control bit .
1
2  SPE_TF2INS Tran sm it F2 Inser t Control. Control bit, when 1, inserts 
the value i n SPE_TF2DINS[7:0] (Table 157) into the outgo-
ing F2 byte in the STS- 1 frame; otherwise, the ins ert  value 
depends  on SPE_TPOAC_F2 (Table 154) control bit .
1
1  SPE_TC2INS Tran smi t C2 In ser t Con trol. Control bit, when 1, inserts 
the value i n SPE_TC2DINS[7:0] (Table 157) i nto the outgo-
ing C2 byte in the ST S-1 frame; otherwis e, the insert value 
depends  on SPE_TPOAC_C2 (Table 154) control bit.
1
0 SPE_TJ1INS Transmit J1 Insert Control. Control bit, when 1, inserts 
the value in SPE_TJ1DINS[1—64][7:0] (Table 163) into the 
outgoing  J1 bytes; otherwise, the insert value depends on 
SPE_TPOAC_J1 (Table 154) control bit.
0
0x3001C 15:8 —Reserved. 0x00
7 SPE_TPOAC_OEPMON Tra n s mi t P OAC Odd or Even Parity Mo nitor . When 1, 
even parity  i s checked   for transmit POAC channels; other-
wise, odd parity is checked.
0
6 SPE_TPOAC_N1 Tran sm it POAC  N1 Byte Control. Control bit, when 0, the 
default value i s inserted i nto the N1 byte in th e transmit  
frame. When 1, t he TP OAC value  is i ns erted in the N1 byte.
0

TMXF 28155/51 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

144 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 154. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) (continued)

Address Bit Name Function Reset

Default

0x3001C 5 SPE_TPOAC_K3 Transmit P OAC K3 Byte Control. Control bit, when 0, the

default value is ins erted int o the K3 byte in the tr an smit

frame. When 1, the TPOAC value is inserted in the K3 byte.

4 SPE_TPOAC_H4 Transmi t P OAC H4 Byte Control. Control bit, when 0, the

default value is inserted int o the H4 byte in the transmit

frame. When 1, the TPOAC value is inserted in the H4 byte.

3 SPE_TPOAC_F3 Tr ansmi t POAC F3 Byte Control. Control bit, when 0, the

default value is ins erted int o the F3 byte in the transmit

frame. When 1, the TPOAC value i s inserted in the F3 byte.

2 SPE_TPOAC_F2 Transmit POAC F2 Byte Control. Control bit, when 0, the

default value is ins erted int o the F2 byte in the transmit

frame. When 1, the TPOAC value i s inserted in the F2 byte.

1 SPE_TPOAC_C2 Transmi t P OAC C2 Byte Control. Control bit, when 0, the

default value is inserted int o the C2 byte in the transmit

frame. When 1, the TPOAC value is inserted in the C2 byte.

0 SPE_TPOAC_J1 Transmi t P OAC J1 Byte Control. Control bit, when 0, the

default value is ins erted int o the J1 byte in the transmit

frame. When 1, the TPOAC value is inserted in the J1 byte.

0x3001D 15:8 SPE_NPI_BYTE2[7:0] Transmit NPI Byte 2. Programmable value f o r NPI b yt e 2 to

be inserted into the NPI byte location. 0

7:0 SPE_NPI_BYTE1[7:0] Transmi t NP I Byte 1. Programmable value for NPI byte 1 to

be inserted into the NPI byte location. 0

0x3001E 15:8 —Reserved. 0x00

7 SPE_TPRDIINS Transmit RDI Software Insert. When 1, the value in

SPE_TG1DINS[3:1] is inser ted into G1[3:1] in the transmit

frame; otherwise, hardware insert is enabled for RDI-P inser-

tion.

6 SPE_TTIM_PRDIINH Transmit Trace Indicator Mismatch RDI Inhibit. Control

bit, when 1, the T IM failure will not contribute to the auto-

mat ic insertion of RDI-P; otherwi se, the associated a larm

contributes to the generation of RDI-P.

5 SPE_TPLM_PRDIINH Transmit Path Label Mismatch RDI Inhibit. Control bit,

when 1, the PLM failure will not contribute to the automatic

insert ion of RDI -P; otherwise, the associated alarm contrib-

utes to the generation of RDI-P.

4 SPE_TUNEQ_PRDIINH Transmit Path Unequipped RDI Inhibit. Control bit, when

1 , the unequipped failure will not con t ribute to the automatic

insert ion of RDI -P; otherwise, the associated alarm contrib-

utes to the generation of RDI-P.

3 SPE_TLOP_PRDIINH Tr ansmit Loss of Pointer RDI Inhibit. Control bit, when 1,

the loss of pointer failure will not cont ribut e to the automatic

insert ion of RDI -P; otherwise, the associated alarm contrib-

utes to the generation of RDI-P.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

145Agere Systems Inc.

9 SPE Mapper Registers (continued)

Table 155. SPE_TRDIREI_CTL, Transmi t Path RDI and REI Control Register (R/W)

Table 156. SPE_TERRINS_CTL, Transmit Err o r Insertion Contro l (R/W)

Table 1 57. SPE_TOHINS1—SP E_TOHINS4, Transmit OH Inser t Value (R/W)

Address Bit Name Function Res et

Default

0x3001E 2 SPE_TPAIS_PRDIINH Tr ansmi t Path AIS RDI I nhibi t. Control bit, when 1, the

path AIS failure will not contribut e to the automatic inser-

tion of RDI- P; otherwise, the ass ociated alarm co ntrib-

utes to the generation of RDI-P.

1 SPE_TPRDI_MODE Transmit PRDI Mode. When 1, 3-bit enhanced ERDI

mode is su pported; when 0, the 1-bit RDI mode is

supported.

0 SPE_TREIP_INH Transmit REI-P Inhib it. When 1, inhibits automatic inser-

tion of REI-P. 0

Address Bit Name F un ction Reset

Default

0x3001F 15:3 —Reserved. 0x000

2 SPE_BERR_INS Bit Error Insert Control Bit. When 1, bit error s w ill be

inserted on selected signals (whose error insert bits are set)

each tim e a pulse occurs on the BER_INS line.

1 SPE_TB3ERRINS Transmit B3 E rror Insertion. When 1, t he B3 output will be

inverted. 0

0 SPE_TREIERRINS Transmit G1 Er ror Insert. When 1, an error will be insert ed

continuously into the outgoing G1[7:4] bits , until reset to 0. 0

Address Bit Name F un ction Reset

Default

0x30020 15:8 SPE_TF3DINS[7:0] Transmit F3 Byte Value. This value is insert ed into the

tra nsmit F3 byte. 0x00

7:0 SPE_TF2DINS[7:0] Transmit F2 Byte Value . T his value is inserted into the

tra nsmit F2 byte. 0x00

0x30021 15:8 SPE_TC2DINS[7:0] Transmit C2 Byte Value . This value is inserted in to the

tran smit C 2 byte. 0x00

7:0 SPE_TK3DINS[7:0] Transmit K3 By te Value . This value is inserted in to the

tra nsmit K3 byte. 0x00

0x30022 15:8 SPE_TG1DINS[7:0] Transmit G1 Byte Value . This value is inserted into the

tra nsmit G1 byte. 0x00

7:0 SPE_TN1DINS[7:0] Transmit N1 By te Value . This value is inserted in to the

tran smit N 1 byte. 0x00

0x30023 15:8 —Reserved. 0x00

7:0 SPE_TH4DINS[7:0] Transmit H4 By te Value . This value is inserted in to the

tran smit H 4 byte. 0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

146 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 158. SPE_SIGDEG_CTL1—SPE_SIG DEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W)

Table 1 59. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signa l Fa il BER Algorithm Parameters (R/W)

Address Bit Name Function Reset

Default

0x30024

0x30025 15:0

2:0 SPE_SDNSSET[18:3]

SPE_SDNSSET[2:0] Signal Deg rad e Ns Set. Num ber of frames in a

monitoring block for SD. 0x0000

0x30025 15 —Reserved. 0

14:7 SPE_SDMSET[7:0] Signal Deg rad e M Se t. Threshold of the number of bad

monitoring bl ocks in an observation i nterval. If the

number of bad b locks is above this threshold, then signal

degrade (SD) is set.

0x00

6:3 SPE_SDLSET[3:0] Signal Degrade L Set. Error threshold for determining a

bad monitoring block. 0x0

0x30026 15:0 SPE_SDBSET[15:0] Signal Deg rad e B Set. Numb er of moni to ring blocks. 0 x0000

0x30027

0x30028 15:0

2:0 SPE_SDNSCLEAR[18:3]

SPE_SDNSCLEAR[2:0] Signal Deg rade Ns Clear. Number of frames in a

monitoring block for SD. 0x0000

0x30028 15 —Reserved. 0

14:7 SPE_SDMCLEAR[7:0] Signal Deg rad e M Clear. Threshold of the number of

bad monitoring blocks in an observation inte rval. If the

num ber of bad block s is below this thres hol d, then SD is

cleared.

0x00

0x30028 6:3 SPE_SDLCLEAR[3:0] Signal Degrade L Cl ear. Error threshold f or determining

a bad monitoring block. 0x0

0x30029 15:0 SPE_SDBCLEAR[15:0] Signal Deg rad e B Clear. Number of moni to ring bl ocks. 0x0000

Address Bit Name F un ction Reset

Default

0x3002A

0x3002B 15:0

2:0 SPE_SFNSSET[18:3]

SPE_SFNSSET[2:0] Sign a l Fail Ns Se t. Number of frames in a mo n ito rin g

block for SF. 0x0000

0x3002B 15 —Reserved. 0

14:7 SPE_SFMSET[7:0] Si gn a l Fa il M Se t. Threshold of the number of bad

monitoring bl ocks in an observation i nterval. If the

number of bad bloc ks is abov e this threshold, then signal

f ail (SF) is set.

0x00

0x3002B 6:3 SPE_SFLSET[3:0] Si gn a l Fail L Set. Error threshold for determining a bad

monitoring block. 0x0

0x3002C 15:0 SPE_SFBSET[15:0] Si gnal Fail B Set. Number of monitor ing blocks. 0x 0000

0x3002D

0x3002E 15:0

2:0 SPE_SFNSCLEAR[18:3]

SPE_SFNSCLEAR[2:0] Signal Fail Ns Cl ear. Number of frames in a monitoring

block for SF. 0x0000

0x3002E 15 —Reserved. 0

14:7 SPE_SFMCLEAR[7:0] Signal Fail M Clear. Threshold of the number of bad

monitoring bl ocks in an observation i nterval. If the

number of bad blocks is below this threshold, then SF is

cleared.

0x00

0x3002E 6:3 SPE_SFLCLEAR[3:0] Sign a l Fail L Clea r. Error threshold for d eter mining a

bad monitoring block. 0x0

0x3002F 15:0 SPE_SFBCLEAR[15:0] Signa l Fa il B Clear. Number of monitor ing blocks. 0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

147Agere Systems Inc.

9 SPE Mapper Registers (continued)

Table 160. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipo lar Violation, and Excess Zero Erro r Count (R O)

Table 161. SPE_PTRCNT1—SPE_PTRCNT3, Receive P o inter Increment and Decrement Count (RO)

Table 162. SPE_R J1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO)

Address Bit N am e Function Reset

Default

0x30030 15:0 SPE_B3ECNT[15:0] B3 Error Count. The v alue of internal running counter is

transferre d into this holding regi ster coinciden t with the

end of a perf ormanc e monitor interval.

0x0000

0x30031 15:0 SPE_G1ECNT[15:0] G1 Error Count. The val ue of internal running counter is

transferre d into this holding regi ster coinciden t with the

end of a perf ormanc e monitor interval.

0x0000

0x30033

0x30034

15:8

7:0

15:0

—

SPE_BIPOL_CNT[23:16]

SPE_BIPOL_CNT[15:0]

Reserved.

Bipolar Coding Violation Occurrence Count. The

value o f internal running counter is tran sferred into this

holding register coincident with the end of a

performance monitor interv al .

0x0000

0x30035

0x30036

15:8

7:0

15:0

—

SPE_EXZ_CNT[23:16]]

SPE_EXZ_CNT[15:0]

Reserved.

Excess Zero Occurrence Count. The value of internal

running count er is transferred into this holding reg ister

coincident with the end of a performance monitor

interval.

0x0000

Address Bit Nam e Function Reset

Default

0x30037 15:10 —Reserved. 0x00

9:0 SPE_STORED_PTR[9:0] Stored TU-3 Pointer Location. 0x000

0x30038 15:11 —Reserved. 0x00

10:0 SPE_RPTR_INC[10:0] Pointer Increment Count from P ointer Interpreter

Block. The value of inte rnal running counter is

transferred into this holding register coincident with

the end of a performance monitor interval.

0x000

0x30039 15:11 —Reserved. 0x00

10:0 SPE_RPTR_DEC[10:0] P o inter Decrement Count f rom Pointer

Interpreter Block. The value of internal running

counter is trans ferred in to this holding register

coincident with the end of a performance monitor

interval.

0x000

Address Bit Nam e Function Reset

Default

0x30042

—

0x30061

15:0 SPE_RJ1DMON[1—64][7:0] Receive J1 Monitor Value. These registers capture

a 64-byte sequence fro m the J1 byte of each frame. 0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

148 Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 163. SPE_TJ1DINS_R1—S PE_T J1DINS_ R32, Tra nsmit J1 Inser t Value s (R/W)

Table 164. SPE_RJ1DEXP_R1—SPE_RJ1D EXP_ R 3 2 , Recei v e J1 Exp ect e d Valu e s (R/W )

Table 165. SPE_SCRATCH_R, Scratch P ad (R/W)

Address Bit Name Function Reset

Default

0x30062

—

0x30081

15:0 SPE_TJ1DINS[1—64][7:0] Tran sm it J1 Insert Value. T hes e registers allow a

64-by te sequence to be inserted into the J1 byte of

each frame.

0x00

Address Bit Name Function Reset

Default

0x30082

—

0x300A1

15:0 SPE_RJ1DEXP[1—64][7:0] Receive J1 Expected V alue. These registers hol d a

programmable 64-b yte expected sequence f or the J1

byte of each frame.

0x00

Address Bit Name Function Reset

Default

0x300A2 15:0 SPE_SCRATCH[15:0] Scratc h Re gist er . Allo ws the control syst em to v erify

read and write operations to the device without

affec tin g de vi ce operation.

0x0000

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

149Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

9.2 SPE Mapp er Reg ister Map

Note: In Table 166, the reset default of all reserved bits is 0. Shading denotes reserved b its.

Ta ble 166. SPE Mapper Register Map

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPE Version and Identif ication Registers—RO

0x30000 SPE_

VERSION_R SPE_VERSION[2:0] SPEMPR_ID[7:0]

0x30001 —

One Shot (0 to 1 transition) Control Bit Parameters—R/W

0x30002 SPE_

ONESHOT SPE_

BIPOL_ERR SPE_

SFCLEAR SPE_SFSET SPE_

SDCLEAR SPE_SDSET

Delta and Event P arameters—COR/COW

0x30003 SPE_EVENT1 SPE_

RDATA_PE SPE_

TPOAC_PE SPE_

K3DMOND SPE_

N1DMOND SPE_

C2DMOND SPE_

F2DMOND SPE_

F3DMOND

0x30004 SPE_EVENT2 SPE_PRDI

DMOND SPE_RNDFE SPE_RDECE SPE_RINCE SPE_RAISD SPE_RLOPD SPE_SFB3D SPE_SDB3D SPE_

RUNEQD SPE_RPLMD SPE_RTIMD

0x30005 SPE_EVENT3 SPE_RSY5

2LOSD SPE_

RV1LOSD SPE_RSPE

LOSD SPE_RJ0J1

V1LOSD SPE_RDS3

LOCD SPE_

RC52LOCD SPE_

RLSLOCD SPE_

TSY52LOSD SPE_

TV1LOSD SPE_

TSPELOSD SPE_TJ0J1V

1LOSD SPE_

TDS3LOCD SPE_

TC52LOCD SPE_

TLSLOCD

Interrupt Mask Parameters for INT Pins—R/W

0x30006 SPE_MASK1 SPE_

RDATA_PM SPE_

TPOAC_PM SPE_

K3DMONM SPE_

N1DMONM SPE_

C2DMONM SPE_

F2DMONM SPE_

F3DMONM

0x30007 SPE_MASK2 SPE_PRDI

DMONM SPE_RNDFM SPE_

RDECM SPE_RINCM SPE_RAISM SPE_RLOPM SPE_SFB3M SPE_SDB3M SPE_

RUNEQM SPE_RPLMM SPE_RTIMM

0x30008 SPE_MASK3 SPE_RSY5

2LOSM SPE_

RV1LOSM SPE_RSPE

LOSM SPE_RJ0J1

V1LOSM SPE_RDS3

LOCM SPE_

RC52LOCM SPE_

RLSLOCM SPE_

TSY52LOSM SPE_

TV1LOSM SPE_

TSPELOSM SPE_TJ0J1V

1LOSM SPE_

TDS3LOCM SPE_

TC52LOCM SPE_

TLSLOCM

State and V alue Par ameter s—RO

0x30009 SPE_STATE1 SPE_RAIS SPE_RLOP SPE_SFB3 SPE_SDB3 SPE_RUNEQ SPE_RPLM SPE_RTIM

0x3000A SPE_STATE2 SPE_

RSY52LOS SPE_

RV1LOS SPE_

RSPELOS SPE_RJ0J1

V1LOS SPE_

RDS3LOC SPE_

RC52LOC SPE_

RLSLOC SPE_

TSY52LOS SPE_

TV1LOS SPE_

TSPELOS SPE_

TJ0J1V1LOS SPE_

TDS3LOC SPE_

TC52LOC SPE_

TLSLOC

Receive Control Parameters for Alarm and Overhead Functions—R/W

0x3000B SPE_RAOH_

CTL1 SPE_RD_

OEPAR SPE_J1MONMODE[2:0] SPE_RPRDI

_MODE SPE_G1BTB

LKCNT SPE_B3BTB

LKCNT SPE_RPOAC

_OEPINS

0x3000C SPE_RAOH_

CTL2 SPE_CNTDLOPCNT[1:0] SPE_8ORMA

JORITY SPE_

PAISINS SPE_PAIS_

AISINH SPE_PAIS_

LOPINH SPE_PAIS_

SFB3INH SPE_PAIS_

SDB3INH SPE_PAIS_

UNEQINH SPE_PAIS_

PLMINH SPE_PAIS_

TIMINH

0x3000D SPE_RAOH_

CTL3 SPE_AIS_LO

SSY52INH SPE_AIS_

LOSV1INH SPE_AIS_LO

SSPEINH SPE_AIS_LO

SJ0J1V1INH SPE_AIS_

LOCDS3INH SPE_AIS_

LOC52INH SPE_AIS_

LOCINH

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

150 A

ere S

stems Inc.

9 SPE Mapper Registers (continued)

Table 166. SPE Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Continuous N-Times Detect Values—R/W

0x3000E —

0x3000F SPE_CNTD1 SPE_CNTDC2[3:0] SPE_CNTDF3[3:0] SPE_CNTDF2[3:0] SPE_CNTDJ1[3:0]

0x30010 SPE_CNTD2 SPE_CNTDN1[3:0] SPE_CNTDPRDI[3:0] SPE_CNTDK3[3:0]

Receive Overh ead Expected Value for C 2 Byte—R/W

0x30011 SPE_ROHC2 SPE_C2DEXP[7:0]

Receive Monitor Values—RO

0x30012 SPE_RMON1 SPE_PRDIDMON[2:0]

0x30013 SPE_RMON2 SPE_N1DMON[7:0] SPE_K3DMON[7:0]

0x30014 SPE_RMON3 SPE_F2DMON1[7:0] SPE_F2DMON0[7:0]

0x30015 SPE_RMON4 SPE_F3DMON1[7:0] SPE_F3DMON0[7:0]

0x30016 SPE_RMON5 SPE_C2DMON[7:0]

0x30017 —

Transmit/Receive Control Parameters for Mapping Functions—R/W

0x30018 SPE_MAP_CTL1 SPE_T_ST

S1_MODE SPE_T_NS

MI_MODE SPE_TDS3SRCTYP[1:0] SPE_T_

VT_DS3 SPE_T_

AU3_TUG3 SPE_TSTS3TMSLOT[1:0] SPE_R_STS

1_MODE SPE_R_NS

MI_MODE SPE_RDS3OUTTYP[1:0] SPE_R_

VT_DS3 SPE_R_

AU3_TUG3 SPE_RSTS3TMSLOT[1:0]

0x30019 SPE_MAP_CTL2 SPE_T_NSMI_BIT[2:0] SPE_R_NSMI_BIT[2:0] SPE_TDS3

CLK_EDGE SPE_PHDE

TUP_INV SPE_PHDE

TDN_INV SPE_TDS3

BPV_IN SPE_TDS3

_BIPOLAR SPE_RDS3

_BIPOLAR

0x3001A SPE_MAP_CTL3 SPE_T_NSMI_COL[6:0] SPE_R_NSMI_COL[6:0]

Tr ansmit Control Param eters for Alarm and Overhead Functions—R/W

0x3001B SPE_TAOH_

CTL1 SPE_TD_

OEPAR SPE_TREIR

DISEL SPE_

TAISPINS SPE_

TN1INS SPE_

TK3INS SPE_

TH4INS SPE_

TF3INS SPE_

TF2INS SPE_

TC2INS SPE_

TJ1INS

0x3001C SPE_TAOH_

CTL2 SPE_TPOA

C_OEPMON SPE_

TPOAC_N1 SPE_

TPOAC_K3 SPE_

TPOAC_H4 SPE_

TPOAC_F3 SPE_

TPOAC_F2 SPE_

TPOAC_C2 SPE_

TPOAC_J1

0x3001D SPE_TAOH_

CTL3 SPE_NPI_BYTE2[7:0] SPE_NPI_BYTE1[7:0]

Transmit Path RDI and REI Control Parameters—R/W

0x3001E SPE_TRDIREI_

CTL SPE_TPRDII

NS SPE_TTIM_

PRDIINH SPE_TPLM

_PRDIINH SPE_TUNE

Q_PRDIINH SPE_TLOP

_PRDIINH SPE_TPAIS

_PRDIINH SPE_TPRDI

_MODE SPE_TREIP

_INH

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

151Agere Sy stem s Inc.

9 SPE Mapper Registers (continued)

Table 166. SPE Mapper Re gister Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transm it Err o r Insertion Con tr o l Parameters—R/W

0x3001F SPE_TERRINS_CTL SPE_BERR_INS SPE_TB3ERRINS SPE_TREIERRINS

Transm it OH Insert Value—R/W

0x30020 SPE_TOHINS1 SPE_TF3DINS[7:0] SPE_TF2DINS[7:0]

0x30021 SPE_TOHINS2 SPE_TC2DINS[7:0] SPE_TK3DINS[7:0]

0x30022 SPE_TOHINS3 SPE_TG1DINS[7:0] SPE_TN1DINS[7:0]

0x30023 SPE_TOHINS4 SPE_TH4DINS[7:0]

Signal Degrade Set/Clear Control Registers—R/W

0x30024 SPE_SIGDEG_CTL1 SPE_SDNSSET[18:3]

0x30025 SPE_SIGDEG_CTL2 SPE_SDMSET[7:0] SPE_SDLSET[3:0] SPE_SDNSSET[2:0]

0x30026 SPE_SIGDEG_CTL3 SPE_SDBSET[15:0]

0x30027 SPE_SIGDEG_CTL4 SPE_SDNSCLEAR[18:3]

0x30028 SPE_SIGDEG_CTL5 SPE_SDMCLEAR[7:0] SPE_SDLCLEAR[3:0] SPE_SDNSCLEAR[2:0]

0x30029 SPE_SIGDEG_CTL6 SPE_SDBCLEAR[15:0]

Signal Fail Set/Clear Control Registers—R/W

0x3002A SPE_SIGFAIL_CTL1 SPE_SFNSSET[18:3]

0x3002B SPE_SIGFAIL_CTL2 SPE_SFMSET[7:0] SPE_SFLSET[3:0] SPE_SFNSSET[2:0]

0x3002C SPE_SIGFAIL_CTL3 SPE_SFBSET[15:0]

0x3002D SPE_SIGFAIL_CTL4 SPE_SFNSCLEAR[18:3]

0x3002E SPE_SIGFAIL_CTL5 SPE_SFMCLEAR[7:0] SPE_SFLCLEAR[3:0] SPE_SFNSCLEAR[2:0]

0x3002F SPE_SIGFAIL_CTL6 SPE_SFBCLEAR[15:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

152 A

ere S

stems Inc.

9 SPE Mapper Registers (continued)

Table 166. SPE Mapper Register Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

B3 and G1 Error Counts—RO

0x30030 SPE_ERRCNT1 SPE_B3ECNT[15:0]

0x30031 SPE_ERRCNT2 SPE_G1ECNT[15:0]

0x30032 —

Bipolar Violation and Excess Zero Counts for DS3—RO

0x30033 SPE_ERRCNT3 SPE_BIPOL_CNT[23:16]

0x30034 SPE_ERRCNT4 SPE_BIPOL_CNT[15:0]

0x30035 SPE_ERRCNT5 SPE_EXZ_CNT[23:16]

0x30036 SPE_ERRCNT6 SPE_EXZ_CNT[15:0]

Receive Pointer Increment and Decrement Counts—RO

0x30037 SPE_PTRCNT1 SPE_STORED_PTR[9:0]

0x30038 SPE_PTRCNT2 SPE_RPTR_INC[10:0]

0x30039 SPE_PTRCNT3 SPE_RPTR_DEC[10:0]

0x3003A

—

0x30041

—

J1 Byte Receive Monitor—RO

0x30042

—

0x30061

SPE_RJ1MON_R1

—

SPE_RJ1MON_R32

SPE_RJ1DMON[2][7:0]

—

SPE_RJ1DMON[64][7:0]

SPE_RJ1DMON[1][7:0]

—

SPE_RJ1DMON[63][7:0]

J1 Byte Transmit Insert—R/W

0x30062

—

0x30081

SPE_TJ1DINS_R1

—

SPE_TJ1DINS_R32

SPE_TJ1DINS[2][7:0]

—

SPE_TJ1DINS[64][7:0]

SPE_TJ1DINS[1][7:0]

—

SPE_TJ1DINS[63][7:0]

J1 Byte Expected Values—R/W

0x30082

—

0x300A1

SPE_RJ1DEXP_R1

—

SPE_RJ1DEXP_R32

SPE_RJ1DEXP[2][7:0]

—

SPE_RJ1DEXP[64][7:0]

SPE_RJ1DEXP[1][7:0]

—

SPE_RJ1DEXP[63][7:0]

Scratch Register—R/W

0x300A2 SPE_SCRATCH_R SPE_SCRATCH[15:0]

0x300A3

—

0x301FF

—

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
153Agere Systems Inc.  
10 VT/TU Mapper Registers
Ta ble of Conte nts
Contents Page
10 VT/TU Mapper Registers ................................................................................................................................ 153
10.1  VT/TU Mapper Register Des c riptions ................... ..................... . .................. . .................. . ...................... 154
10.2  VT/TU Mapper Register Map .. ....................... .......................... ..................... . ......................................... 171
Tables Page
Table 167.  VT_V ERS ION _R, V T  Mapper Ready, V ersion , and Identification (RO) ................ ................... ......... 154
Table 168.  V T_G DELTA , V T Global Deltas (COR/COW) . ............................ .......................... ............................154
Table 1 69. VT_REVENT_ DELTA[1—28], Receive Event and Delta Per Channel (COR/COW) ..... .. ....... ..... .....155
Table 170. VT_LOPOHFAIL_EVENT, Low-Order Pa th Overhead Failure Event (COR/COW) ..........................155
Table 171. VT_TEVENT_DELTA[1—28], Transmit E vent  and  Delta Per Channel (COR/COW) ........................1 56
Table 172. V T_GMASK, VT Global Masks (R/W )  ........................... ....... ....... ............ ....... ....... ............ ................156
Table 173.  VT_RMASK[1—28], Receive Masks Per Channel (R/W) ................ ..... .. ..... .. ....... ..... ..... .. ..... .. ..... ..... 157
Table 174. VT_L OPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W)  .......................................158
Table 175. V T_TMASK[1—28], T ransm it Masks  Per Channel (R/W ) ................ ...................................... ........... 1 58
Table 176.  V T_G S TATE,  V T Global State (RO) .... ......................... ........................................ ............................ 158
Table 177. V T_RSTA TE [1—28], Recei ve State Per Channel (RO) .................... ............. .................... ............... 159
Table 178.  VT_RAPSSTATE[1—28], Rec eive APS St ate Per Channel (RO ) ....................... .......................... .... 159
Table 179. VT_TSTATE[1—28], Transm it S tate Per Channel (RO) .................. ................... ................... ........... 1 59
Tabl e 180. VT_ GCTL1, VT Global Control Regi ster 1 (R/W) .............................................................................. 160
Tabl e 181. VT_ GCTL2, VT Global Control Regi ster 2 (R/W) .............................................................................. 160
Tabl e 182. VT_ GCTL3, VT Global Control Regi ster 3 (R/W) .............................................................................. 161
Tabl e 183. VT_ GCTL4, VT Global Control Regi ster 4 (R/W) .............................................................................. 161
Tabl e 184. VT_ GCTL5, VT Global Control Regi ster 5 (R/W) .............................................................................. 162
Table 185.  VT_SI GDEG_CTL1, Signal Degrade Control Regi ster 1 (R/W) ............ ................. ................ ........... 1 63
Table 186.  VT_SI GDEG_CTL2, Signal Degrade Control Regi ster 2 (R/W) ............ ................. ................ ........... 1 63
Table 187.  VT_SI GDEG_CTL3, Signal Degrade Control Regi ster 3 (R/W) ............ ................. ................ ........... 1 63
Table 188.  VT_SI GDEG_CTL4, Signal Degrade Control Regi ster 4 (R/W) ............ ................. ................ ........... 1 63
Table 189.  VT_SI GDEG_CTL5, Signal Degrade Control Regi ster 5 (R/W) ............ ................. ................ ........... 1 64
Table 190.  VT_SI GDEG_CTL6, Signal Degrade Control Regi ster 6 (R/W) ............ ................. ................ ........... 1 64
Table 191.  VT_SI GDEG_CTL7, Signal Degrade Control Regi ster 7 (R/W) ............ ................. ................ ........... 1 64
Table 192. VT_SIGFAIL_CT L1, Signal Fail Control Register 1 (R/W) ................................................................ 164
Table 193. VT_SIGFAIL_CT L2, Signal Fail Control Register 2 (R/W) ................................................................ 164
Table 194. VT_SIGFAIL_CT L3, Signal Fail Control Register 3 (R/W) ................................................................ 164
Table 195. VT_SIGFAIL_CT L4, Signal Fail Control Register 4 (R/W) ................................................................ 165
Table 196. VT_SIGFAIL_CT L5, Signal Fail Control Register 5 (R/W) ................................................................ 165
Table 197. VT_SIGFAIL_CT L6, Signal Fail Control Register 6 (R/W) ................................................................ 165
Table 1 98. VT_T CTL[1—28], Transmit Control Per Channel (R/W)  ............ .......... ......... .......... .......................... 166
Table 199. V T_TTUOH_CTL[1—28], Transmit TU Overhead Control Per Channel (R/W) .............. ................... 167
Table 200. V T_TAPSRIVAL[1—28], Transmit APS and Remo te In dication Per Chan nel (R/W) ........................167
Table 201. VT_TSWOW[1—28],  Transmit Software Overwrite Per Channe l (R/W) .. ............. . ....................... . ... 167
Table 2 02. VT_T SIG_CTL[1—28], Transmit Signaling Control Per Channel (R/W)  ....... ....... ..... ..... ....... .. ..... .....168
Table 203. VT_J2BYTE_INS_R[1—28][1—16],  J2 Insert Values Per Channel (R/ W) .... ..... .. ..... ..... .. ..... .. ..... ..... 168
Table 204. VT_RCTL[1—28], Receive Control Per Channel (R/W) .................................................................... 168
Table 205. V T_RTUOH_CTL[1—28], Receive TU Overhead Control Per Channel (RO) .................. ....... .......... 169
Table 2 06. VT_RBIP2_CNT[1—28], Receive BIP-2 Error Count Per Channel (RO)  . .................. . .................. .... 169
Table 2 07.  VT_R REIV_CNT[1—28] , Receive REI-V Error Count Per Channe l (RO) ............. . ........................... 169
Table 2 08.  VT_R PTR_CNT[1—28], Receive Pointer and Count   P er Channel (RO)  ....... ..... ..................... . ........ 170
Table 2 09. VT_J2BYTE_EXP_R[1—28][1—16], J2  Expect ed Val ues P er Channe l (R/W, RO ) .............. ........... 1 70
Table 2 10. VT_THRES_CTL[1—28], Transmit Elastic Store Threshold Control (R/W) ...................................... 170
Table 2 11.   V T/TU M apper Regist er Map ........ ..................... . ................... .................. . .................. . ...................... 171

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

154 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

10.1 VT/TU Ma pper Regis te r Descr iptions

The following tables describe the functions of all bits in the register map. For each address, the register bits are

indicated as either read/write ( R/W) or read only (RO), and the value of the bits on reset is given.

Table 167. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO)

Table 168. V T_G DELTA, VT Global Delt as (COR/COW)

Address Bit Name Function Reset

Default

0x20000 15 VT_RDY VT/TU M app er Ready. A 1 indicates that the VT/TU map-

per is ready for microprocessor reads and writes. 0x0

14:11 —Reserved. 0x0

10:8 VT_VERSION[2:0] Block Version Number. These bits identify the versio n

number of the VT/TU mapper. NA

7:0 VT_ID[7:0] Bloc k ID Number. VT _ID returns a fixed value (0x02)

when read. 0x02

Address Bit Name Function Reset

Default

0x20001 15:3 —Reserved. 0x000

2VT_SD_DVT/TU Signal Degrade Delta Bit. Logic 1 indicates a

change in the signal degrade condition ba sed on the in ter-

nal bit error rate detector.

0x1

1VT_SF_DVT/TU Signal Fail Delta Bit. Logic 1 indicates a change

in the signal fail condition based on the internal bit error

rate detector.

0x1

0 VT_H4LOMF_D H4 Mismatch Delta Bit. Logic 1 indicates a change in the

H4 loss of multiframe condition . 0x1

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

155Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 169. VT_REVENT_D ELTA[1—28], Receive Event and Delta Per Channel (COR/COW)

Table 170. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/C OW)

Address Bit Name Function Reset

Default

0x20002

—

0x2001D

15 —Reserved. 0

14 VT_RX_VTREI_E[1—28] Recei ve REI-V Even t Bit. Logic 1 indica tes that

REI-V was received. 0x0

13 VT_RX_BIP2ERR_E[1—28] Receive BIP-2 Error Event Bit. Logic 1 indic ates

that BIP-2 errors have been detected. 0x0

12 VT_RX_ESOVFL_E[1—28] Receive Elastic Store Overflow Event Bit. Logic

one indicates an elastic store overflow. 0x0

11 VT_APS_D[1—28] ERDI-V Delta Bit. Logic 1 in dicat es a V TAPS

change of value. 0x1

10 VT_ERDI_D[1—28] ERDI-V Delta Bit. Logic 1 indicates an ERDI -V

change of value. 0x1

9 VT_RDI_D[1—28] RDI-V Delta Bit. Logic 1 i ndicates an RDI-V

change of value. 0x1

8 VT_RFI_D[1—28] RF I-V Delta Bit. Logic 1 indicates an RFI-V

change of value. 0x1

7—Reserved. 0

6 VT_LOPS_D[1—28] VT Loss of P hase Syn c Delta Bit. Logic 1 indi-

cates a change of VTLOPS state. 0x1

5VT_J2TIM_D[1—28] J2 Trace Identifier Mismatch. Logic 1 indicates a

change of J2TIM state. 0x1

4VT_PLM_D[1—28] VT Payload Label Mismatch Delta Bit. Lo gic 1

indicates a change of V TP LM state. 0x1

3 VT_UNEQ_D[1—28] VT Unequip Delta Bit. Logic 1 ind icates a change

of VTUNEQ state. 0x1

2 VT_SIZERR_D[1—28] VT Size Error Delta Bit. Logic 1 indicates a

change of VTSIZERR state. 0x1

1VT_AIS_D[1—28] AIS-V Delta Bi t. Logic 1 indicates a change of

VTAIS state. 0x0

0 VT_LOP_D[1—28] LOP-V Delta Bit . Logic 1 indicat es a change of

VTLOP state. 0x1

Address Bit Name Function Reset

Default

0x2001E 15:1 —Reserved. 0x000

0 VT_LOPOH_FAIL_E Low-Order Path Overhead Fai lure Event Bit. Log ic 1

indicat es that a failure has occurred on the LOPOH

serial access channel.

0x0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

156 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 171. VT_TEVENT _DELTA[1—28], Transmit Event and Delta Per Channel (COR/ COW)

Table 172. VT_GMASK, VT Global Masks (R/W)

Address Bit Name Function Reset

Default

0x2001F

—

0x2003A

15:5 —Reserved. 0x000

4 VT_TX_ESOVFL_E[1—28] Transmit Elastic Store Overflo w Event Bit. Logic

1 indicates an elastic store overflow. 0x0

3—Reserved. 0

2 VT_LOFS_D[1—28] Loss of Frame Sync Delta Bit. Logic 1 indicates a

change of VT_LOFS[1—28] (Table 179) state. 0x1

1 VT_TX_AIS_D[1—28] T ransmit AIS Delta Bit. Logic 1 indic ates a c hange

of VT_TX_AIS[1—28] (Table 179) state. 0x0

0VT_TX_LOC_D[1—28] Transmit Loss o f Clock Delta Bit. Logic 1 indi-

cates a change of VT_TX_LOC[1 —28] (Table 179)

state.

0x1

Address Bit Name Function Reset

Default

0x2003B 15:3 —Reserved. 0x000

2VT_SD_MVT/TU Signal Degrade M ask Bit. If set to a logic 1,

VT_SD_D (Table 168) will not con tribute to the interru p t. 0x1

1VT_SF_MVT/T U Si gnal F ai l Ma sk Bit . If set t o a log ic 1, V T_SF_D

(Table 168) will no t c o ntribute to the interrupt. 0x1

0 VT_H4LOMF_M H4 Mismatch Mask Bit. If set to a lo gic 1,

VT_H4L OM F_D (Table 168) will no t con tribute to the

interrupt.

0x1

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

157Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 173. VT_RMASK[1—28], Receive Masks Per Chann el (R/W)

Note: The event and delta bits for these mask bits are in Table 169.

Address Bit Name Function Reset

Default

0x2003C

—

0x20057

15 —Reserved. 0

14 VT_RX_VTREI_M[1—28] Receive REI-V Mask Bit. If se t to a l ogic 1,

VT_RX_VTREI_E[1—28] will not contribute to the inter-

rupt.

0x1

13 VT_RX_BIP2ERR_M[1—28] Receive B IP-2 Err or Mask Bi t. If se t to a logic 1,

VT_RX_BIP2ERR_E[1—28] will not c o ntribute to the

interrupt.

0x1

12 VT_RX_ESOVFL_M[1—28] Receive Elastic Store Overflow Mask Bit. If set to a

logic 1, VT _RX_E S OVFL_E [1—28] will not contribut e to

the interrupt.

0x1

11 VT_APS_M[1—28] VT APS Mask Bit. If set to a logic 1, VT_APS_D[1—28]

will not contribute to the interrupt. 0x1

10 VT_ERDI_M[1—28] ERDI-V Mask Bit. If se t to a logi c 1, VT _ERDI_D[1—28]

will not contribute to the interrupt. 0x1

9VT_RDI_M[1—28] RDI-V Mask Bi t. If set to a logic 1, VT_RDI_D[1—28] will

not contribute to the interrupt. 0x1

8VT_RFI_M[1—28] RFI-V Mask Bit. If set to a logic 1, VT_RFI_D[1—28] will

not contribute to the interrupt. 0x1

7—Reserved. 0

6 VT_LOPS_M[1—28] VT Loss of Phase Sync Mask Bit. If set to a logic 1,

VT_LOPS_D[1—28] will not contribute to the interrupt. 0x1

5 VT_J2TIM_M[1—28] J2 Mismatch Mask Bit. If s et to a logic 1,

VT_J2TIM_D[1—28] wi ll not contribute to the interrupt . 0x1

4 VT_PLM_M[1—28] VT Payload Label Mismatch Mask Bit. If set to a logic

1, VT _P LM_ D [1—28] will not co ntribute to the interrupt. 0x1

3 VT_UNEQ_M[1—28] VT Unequip Mask Bit. I f s et to a logic 1,

VT_UNEQ_D[1—28] will not cont ribute to the interrupt. 0x1

2 VT_SIZERR_M[1—28] VT Size Error Mask Bit. If set to a l ogic 1,

VT_SIZERR_D[1—28] will not contribute to the interrupt. 0x1

1VT_AIS_M[1—28] AIS- V Mask Bi t. If set to a logic 1, VT_AIS_D[1—28] will

not contribute to the interrupt. 0x1

0VT_LOP_M[1—28] LOP-V Mask Bit. If set to a logic 1, VT_ L O P_D[1—28]

will not contribute to the interrupt. 0x1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

158 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 174. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W)

Table 175. VT_TMASK[1—28], Transm it Masks Per Cha nne l (R/W )

Table 176. VT_GSTATE, VT Global State (RO)

Address Bit Name Function Reset

Default

0x20058 15:1 —Reserved. 0x000

0 VT_LOPOH_FAIL_M Low-Order Path Overhead Failure Mask Bit. If s e t to a

logic 1, VT _LOP O H_FA IL_ E (Table 170) will not contr ib -

ute to th e interrupt.

0x1

Address Bit Name Function Reset

Default

0x20059

—

0x20074

15:5 —Reserved. 0x000

4 VT_TX_ESOVFL_M[1—28] Transmi t Elastic Store Overflow Mask Bit. If set

to a logic 1, VT_TX_ESO VFL_E[1—28] (Table 171)

will not contribut e to the interrupt.

0x1

3 RESERVED Reserved. 0

2 VT_LOFS_M[1—28] Loss of Frame Sync Mask Bit. If se t to a logic 1,

VT_LOFS_D[1—28] (Table 171) wil l not c ontribute

to the interrupt.

0x1

1 VT_TX_AIS_M[1—28] Transmi t AI S Mask Bi t. If set to a logic 1,

VT_TX_AIS_D[1—28] (Table 171) will not contrib-

ute to the interr upt.

0x1

0 VT_TX_LOC_M[1—28] Transmi t Loss of Clock Mask Bit. If set to a logic

1, VT _TX_LOC_D[1—28] (Table 171) will not con-

tribute to the interrupt.

0x1

Address Bit Name Function Reset

Default

0x20075 15:3 —Reserved. 0x000

2VT_SDVT/TU Signal Degrade. Logic 1 indicates a signal

degrade condition on the selected c hannel. 0x1

1VT_SFVT/TU Si gna l Fai l. Logic 1 indicates a signal f ail condition

on the selected channel. 0x1

0 VT_H4LOMF H4 Loss of M ultifr am e. Logic 1 indicates a l oss of H4

multiframe alignment . 0x1

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

159Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 177. VT_RSTATE[1—28], Receive St ate Per Ch annel (RO)

Table 178. VT_RAPSSTATE[1—28], Receive APS State Per Channel (R O)

Table 1 79. VT_TS TATE[1—28], Transmit State Per Channel (RO)

Address Bit Name Function Reset

Default

0x20076

—

0x20091

15:13 VT_ERDI[1—28][2:0] Enhanced RDI-V Value. These bits are the stored ERDI-V

bits received in the Z7 byte. 0x000

12:10 VT_LAB[1—28][2:0] VT Signal Label. These bits are the stored VT signa l label

bits received in the V5 byte. 0x000

9 VT_RDI[1—28] RDI-V Value . This bit i s the accepted RDI-V bit received in

the V5 byte. 0x00

8VT_RFI[1—28] RFI-V Value. Thi s bit is the accepted RFI-V bit received in

the V5 byte. 0x00

7—Reserved. 0

6 VT_LOPS[1—28] VT Loss of Phase Sync. Logic 1 indicates a loss o f P-bi t

phase synch ronizat ion. 0x1

5VT_J2TIM[1—28] J2 Trace Identifier Mismatch. Logic 1 indicat es a m is-

match between the expected trace and t he detected trace. 0x1

4VT_PLM[1—28] VT Payload Label Mismatch. Logic 1 indica tes PLM-V. 0x1

3 VT_UNEQ[1—28] VT Unequip. L ogic 1 indicates UNEQ-V. 0x1

2 VT_SIZERR[1—28] VT Size Error. Logic 1 indicates a VT s ize error. 0x1

1VT_AIS[1—28] AIS-V. Logic 1 indic ates AIS-V. 0x0

0VT_LOP[1—28] LOP-V. Lo gic 1 indicates LOP-V. 0x1

Address Bit Name Function Reset

Default

0x20092

—

0x200AD

15:4 —Reserved. 0x000

3:0 VT_APS[1—28][3:0] VT APS Value. These bits are the s tored VT APS bits

received in th e Z7/K4 byte. 0x0

Address Bit Name Function Reset

Default

0x200AE

—

0x200C9

15:3 —Reserved. 0x000

2 VT_LOFS[1—28] Loss of Frame Sync. Logic 1 indicat es DS 1/ E 1 loss of

frame sync. 0x1

1VT_TX_AIS[1—28] Transmit AIS. L ogic 1 i ndicates DS 1/E 1 AI S. 0x0

0 VT_TX_LOC[1—28] Transm it Loss of Clock. Logic 1 indicates DS1/E1 los s

of cloc k. 0x1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

160 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 180. VT_GCTL1, VT Global Contr ol Reg ister 1 (R/W)

Table 181. VT_GCTL2, VT Global Contr ol Reg ister 2 (R/W)

Address Bit Name Function Reset

Default

0x200CA 15 —Reserved. 0

14:8 VT_RX_GRP_TYPE[6:0] Receive Group Ty pe. VT/TU group type selection.

Logic 1 selects V T1.5/TU -11 and logic 0 selects

V T2/TU-12 group type. Group 1 is the LSB.

0x7F

7—Reserved. 0

6:0 VT_TX_GRP_TYPE[6:0] Tran smit Group Type. V T/ TU group type selection.

Logic 1 selects V T1.5/TU -11 and logic 0 selects

V T2/TU-12 group type. Group 1 is the LSB.

0x7F

Address Bit Name Function Reset

Default

0x200CB 15:11 —Reserved. 0x00

10 VT_LOPS_AIS_INH VT/TU Loss of Phase Sy nc. Contribution to AIS inhibit

control. 0x0

9 VT_J2TIM_ERDI_INH J2 Trace Identifier Mismatch. Contribution to ERDI

inhibit cont rol. 0x0

8 VT_J2TIM_RDI_INH J2 Trace Identifier Mismatch. Contribution to RDI inhibit

control. 0x0

7VT_J2TIM_AIS_INHJ2 Trace Identifier Mismatch. Contribution to AIS inhibit

control. 0x0

6 VT_LOMF_AIS_INH Lo s s of Multiframe . Cont ribution to AIS inhibit control. 0x0

5 VT_PLM_AIS_INH Payload Label Mismatch. Contribution to AIS inhibit c on-

trol. 0x0

4 VT_UNEQ_AIS_INH UNEQ-V. Contribution to AIS inhibit control. 0x0

3—Reserved. 0

2VT_UPSRUnidir ectio nal P ath Swit c h Ring Mode Cont r ol. Logic 1

activ ates the UPSR mode of operation. When the device

is programmed for UPSR m ode, the transm itted REI-V,

RDI-V, RFI-V, and ERDI-V are based on the receive condi-

tions. Othe rwise, the trans mitted LO PO H is a copy of the

received overhead bytes.

0x0

1 VT_8ORMAJORITY VT Pointer Int erpreter Mode Control. Logic 1 tells the

pointer inter preter to transition into the inc and de c states

based on 8 of the 10 I and D bits. Other wise, the pointer

interpreter transitions into the inc and dec states based on

majority rule.

0x1

0 VT_BIT_BLOCK_CNT Performa nc e Monitor Coun t Mod e Cont rol. Logic 1

activates BIP-2, TC-BIP-2, REI , and TC-CRC-7 count s

bas ed on single bit errors. Otherwise, errors are counted

on a block basis.

0x1

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

161Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 182. VT_GCTL3, VT Global Contr ol Reg ister 3 (R/W)

Table 183. VT_GCTL4, VT Global Contr ol Reg ister 4 (R/W)

Address Bit Name Function Reset

Default

0x200CC 15:8 —Reserved. 0x00

7:4 VT_LOPS_NTIME[3:0] VT/TU Loss of Phase Sy nc NTIME Detection Control.

This nib ble is programmed to provision the number of con-

secutive errored phase indications required to transition

into the VT_LOPS[1—28] (Table 177) stat e. Only valid in

byte synchronous mode.

Note: The valid range of values i s 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x6

3:0 VT_H4_NTIME[3:0] H4 Multiframe Indication NT IME Det e ction Control.

This nib ble is programmed to provision the number of con-

secutive errored multif ra me ind ications required to transi-

tion into the VT_H4LOMF ( Table 176) s t ate.

Note: The valid range of values i s 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x6

Address Bit Name Function Reset

Default

0x200CD 15:11 VT_Z6_NTIME[3:0] Z6 Byte Monitor NTIME Detection Control. This nibble

is programmed to provision the number of consecutive

consistent Z6 byt es requ ired to accept a new value.

Note: The valid range of values i s 0x1—0 xF. A val ue of

0x0 will be mapped to 0x1.

0x3

11:8 VT_J2_NTIME[3:0] J2 Byte Monitor NTIM E Detection Control. This nibble

is programmed to provision the number of consecutive

consistent J2 sequences required f or the J2 byte monitor

to transition in and out of J2TIM.

Note: The valid range of values i s 0x1—0 xF. A val ue of

0x0 will be mapped to 0x1.

0x3

7:4 VT_INV_NTIME[3:0] Pointer Interpreter Invalid Pointer NTIME Detection

Control. This nibble is programme d to provisio n the

number of invalid pointers required for the pointer inte r-

preter to go into the VT_LOP[ 1—28] (Table 177) stat e.

Note: The valid range of values i s 0x1—0 xF. A val ue of

0x0 will be mapped to 0x1.

0x8

3:0 VT_NDF_NTIME[3:0] Pointer Interpreter NDF Pointer NTIME Detection

Control. This nibble is programme d to provisio n the

number of c onsecutive NDF poi nters required for the

pointer inter preter to go into the VT_LOP state.

Note: The valid range of values i s 0x1—0 xF. A val ue of

0x0 will be mapped to 0x1.

0x8

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

162 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 184. VT_GCTL5, VT Global Contr ol Reg ister 5 (R/W)

Address Bit Name Function Reset

Default

0x200CE 15:12 VT_APS_NTIME[3:0] APS NTIME Detection Contro l. This nibble is programmed

to provision the number of consecutiv e consistent new values

required to accept a new VT_APS[1—28][3:0] (Table 178).

Note: The valid range of values i s 0x1—0 xF. A val ue of 0x0

will be mapped to 0x1.

0x3

11:8 VT_LAB_NTIME[3:0] VT Sign al Label NTI ME D et ec tio n Control. This nibble is

programmed to provision the number of consecutive consis-

tent new val ues required to ac cept a ne w

VT_LAB[1—28][2:0] (Table 177).

Note: The valid range of values i s 0x1—0 xF. A val ue of 0x0

will be mapped to 0x1.

0x3

7:4 VT_ERDI_NTIME[3:0] ERDI -V NTIME Detection Control. This nibble is pro-

gramme d to provision the n umber of consecutive consistent

ne w val ues required to accept a new VT_ERDI[1—28][2:0]

(Table 177).

Note: The valid range of values i s 0x1—0 xF. A val ue of 0x0

will be mapped to 0x1.

0x3

3:0 VT_RDI_NTIME[3:0] RDI-V NTIME Detection Co ntro l. This nibble is pro-

gramme d to provision the n umber of consecutive consistent

ne w val ues required to accept a new VT_RDI[ 1—28]

(Table 177).

Note: The valid range of values i s 0x1—0 xF. A val ue of 0x0

will be mapped to 0x1.

0x3

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

163Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 185. VT_SIGDEG_CTL1, Signal Degrade Control Re gister 1 (R/W)

Table 186. VT_SIGDEG_CTL2, Signal Degrade Control Re gister 2 (R/W)

Table 187. VT_SIGDEG_CTL3, Signal Degrade Control Re gister 3 (R/W)

Table 188. VT_SIGDEG_CTL4, Signal Degrade Control Re gister 4 (R/W)

Address Bit Name Function Reset

Default

0x200CF 15:12 —Reserved. 0x00

11 VT_SFCLEAR VT Signal Fail Cl e a r. Allows the signal fail al gorithm to be

forced into the normal state. This is a one shot which is

activated by a 0 to 1 t ran si ti on.

0x0

10 VT_SFSET VT Signal Fail Set. Allows the signal fail algori thm to be

forced into the failed state. This is a one shot which is acti-

vated by a 0 to 1 transition.

0x0

9 VT_SDCLEAR S ignal De grade Clear. Allows the signal degrade algo-

rithm to b e forced into the normal state. This is a one shot

which is activat ed by a 0 to 1 transition.

0x0

8VT_SDSETS ignal Degrade Set. Allows the signal degrade algorithm

to be forced into the failed state. This is a one shot which

is activated by a 0 to 1 transition.

0x0

7:5 —Reserved. 000

4:0 VT_BER_CH_

SEL[4:0] Bit Erro r Rate Monitor Channel Select. Selects which

channel (1—28/21) is being monitored b y the internal

BER monitor. Valid inputs are 00001—11100.

0x00

Address Bit Name Function Reset

Default

0x200D0 15:0 VT_SDNSSET[18:3] Signal De grade Ns Set. Number of fra mes in a monitor-

ing block fo r SD. 0x0000

Address Bit Name Function Reset

Default

0x200D1 15 —Reserved. 0

14:7 VT_SDMSET[7:0] Signal Degrade M Set. Threshold of the number of bad

monitoring b locks in an observati on interval. If the number

of bad blocks is above this thres hol d, the n signal degrade

SD is set.

0x00

6:3 VT_SDLSET[3:0] Signal Degrade L Set. Error threshold for determining if a

monitoring block is bad. 0x0

2:0 VT_SDNSSET[2:0] S ignal Degrade Ns Set. Number of fra mes in a monitor-

ing block fo r SD. 0x0

Address Bit Name Function Reset

Default

0x200D2 15:0 VT_SDBSET[15:0] Signal Degrade B Set. Nu mbe r of moni tor ing bl ocks. 0x0000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

164 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 189. VT_SIGDEG_CTL5, Signal Degrade Control Re gister 5 (R/W)

Table 190. VT_SIGDEG_CTL6, Signal Degrade Control Re gister 6 (R/W)

Table 191. VT_SIGDEG_CTL7, Signal Degrade Control Re gister 7 (R/W)

Table 192. VT_SIGFAIL_CTL1, Signal Fail Contro l Register 1 (R/W)

Table 193. VT_SIGFAIL_CTL2, Signal Fail Contro l Register 2 (R/W)

Table 194. VT_SIGFAIL_CTL3, Signal Fail Contro l Register 3 (R/W)

Address Bit Name Function Reset

Default

0x200D3 15:0 VT_SDNSCLEAR[18:3] Signal Degrade Ns Clear. Number of frames in a moni-

toring block for SD. 0x0000

Address Bit Name Function Reset

Default

0x200D4 15 —Reserved. 0

14:7 VT_SDMCLEAR[7:0] Si gnal Degrade M Clear . Threshold of the number of bad

monitoring blocks in an observat ion interval . If the number

of bad blocks is below this threshold, then SD is cleared.

0x00

6:3 VT_SDLCLEAR[3:0] Signal Degrade L Clear . Error threshold for determining if

a monitoring block is b ad. 0x0

2:0 VT_SDNSCLEAR[2:0] Signal Degrade Ns Clear. Number of frames in a moni-

toring block for SD. 0x0

Address Bit Name Function Reset

Default

0x200D5 15:0 VT_SDBCLEAR[15:0] Signal Degrade B Clear. Number of m onitoring blocks . 0x 0000

Address Bit Name Function Reset

Default

0x200D6 15:0 VT_SFNSSET[18:3] Signal Fail Ns Set. Number of frames in a monitoring block for SF.0x0000

Address Bit Name Function Reset

Default

0x200D7 15 —Reserved. 0

14:7 VT_SFMSET[7:0] Signal Fail M Set. Threshold of the number of bad monitori ng

blocks in an observation interval. If the number of bad blocks is

above this threshold, then SF is set.

0x00

6:3 VT_SFLSET[3:0] S ignal Fail L Set. Error threshold for determ inin g if a monitor ing

block is bad. 0x0

2:0 VT_SFNSSET[2:0] Signal Fail Ns Set. Number of fr ames in a monitoring block for SF. 0x0

Address Bit Name Function Reset

Default

0x200D8 15:0 VT_SFBSET[15:0] Signal Fail B Set. Number of monitoring blocks. 0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

165Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 195. VT_SIGFAIL_CTL4, Signal Fail Contro l Register 4 (R/W)

Table 196. VT_SIGFAIL_CTL5, Signal Fail Contro l Register 5 (R/W)

Table 197. VT_SIGFAIL_CTL6, Signal Fail Contro l Register 6 (R/W)

Address Bit Name Function Reset

Default

0x200D9 15:0 VT_SFNSCLEAR[18:3] Signal Fail Ns Clear. Number of frames in a monitoring

block for SF. 0x0000

Address Bit Name Function Reset

Default

0x200DA 15 —Reserved. 0

14:7 VT_SFMCLEAR[7:0] Signal Fail M Cl ear. Threshold of the number of bad

monitoring blocks in an observation inte rval. If the

number of bad blocks is below this threshold, then SF is

cleared.

0x00

6:3 VT_SFLCLEAR[3:0] Signal Fail L Clear. Error threshold for determining if a

monitoring bloc k is bad. 0x0

2:0 VT_SFNSCLEAR[2:0] Sign al Fail Ns C lear. Number of frames in a m onitor ing

block for SF. 0x0

Address Bit Name Function Reset

Default

0x200DB 15:0 VT_SFBCLEAR[15:0] Signal Fail B Clear. Nu mbe r of monitoring bl ocks. 0x0000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

166 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 198. VT_TCTL[1—28], Transmit Control Per Channel (R/W)

Address Bit Name Function Reset

Default

0x200DC

—

0x200F7

15:13 —Reserved. 0x0

12 VT_TX_ERDI_EN[1—28] Transm it Path Enhanced RDI-V Enable. Logic one

enables enhanc ed R D I-V. 0x0

11 VT_ERDI_EN[1—28] Enhanced RDI-V Source Selection. Logic one ac ti-

vates software overwrite of the ERDI-V bits of the Z7

byte. Otherwise, i nsertion is based on the LOPOH

serial channel or automatic gener ation.

0x0

10 VT_RDI_EN[1—28] RDI-V So urc e Select ion . Logic one acti vates software

overwrite of the RD I-V bit of the V5 byte. Otherwise,

insertion is bas ed on the LOPOH seri al channel or

automat ic generation.

0x0

9 VT_RFI_EN[1—28] RFI-V Source Selection. Logic one activates software

overwrite of the R F I-V bit of the V5 byte. If

VT_V5_INS[1—28] = 0 (Table 199) and the mappi ng is

set to byt e synchronous DS1, a logic zero enables

auto ma tic i n serti on of RFI -V. If VT _ V 5_ IN S[1 —28] = 1,

a lo gic zero inserts RFI-V based on the L OPOH serial

channel.

0x0

8VT_REI_EN[1—28] REI-V Enab le. Logic one ac tivates automatic genera-

tio n of REI-V. If VT_V5_ INS[ 1 —28] = 0, the generation

is based on the receiv ed BIP-2 errors. Otherwise,

insertion is bas ed on the LOPOH serial channel.

0x0

7—Reserved. 0

6 VT_AIS_INS[1—28] AIS-V Insertion Control. Logic one forces AIS-V to be

transmi tted in the specified channel. 0x0

5VT_TX_CLKEDGE[1—28] Transmit Path DS1/E1 Clock Edge Selection. Logic

one forces the DS1/E1 signals to be retimed u sing the

r ising edge of the associated clock. Logic zero forces

the DS1/E1 signals to be ret imed using the falling edge

of the assoc iated clock.

0x0

4 VT_LB_SEL[1—28] Tributary Loopba ck Sele c tion. Logic one activates

tri butar y l oopback. 0x0

3:0 VT_TX_MAPTYPE

[1—28][3:0] Transmit Mapping Mode Control. See Table 558.0x6

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
167Agere Systems Inc.  
10 VT/TU Mapper Registers (continued)
Table 199. VT_TTUO H _CTL[1—28], Transmit TU Overhead Contro l P er Channel (R/W)
Table 200. VT_TAP SRIVAL[1—28], Transmit APS and Remote Indication P er Channel (R/W)
Table 201. VT_TSWOW[1—28], Transm it Software Overwrite Per Channel  (R/W)
Address Bit Name Function Reset
Default
0x200F8
— 
0x20113
15:11 —Reserved. 0x00
10:9 VT_O_INS[1—28][1:0] O-Bit Insertion Control. See Table 566 on page446 .0x0
8:7 VT_Z7_INS[1—28][1:0] Z7 Byte Insertion Control. See Table 5 65, Z7 /K4 Over-
head Byte Insertion M odes  Per Channel on page446 .0x0
6:5 VT_Z6_INS[1—28][1:0] Z6 Byte Insertion Control. See Table 5 64, Z6 /N2 Over-
head Byte Insertion M odes  Per Channel on page445 .0x0
4:3 VT_J2_INS[1—28][1:0] J2 Byte Insertion Control. See Table 563, J2 Overhead 
Byte Insertion Modes Per Channel on page 445.0x0
2VT_V5_INS[1—28] V5 Byte Insertion Control.  Logic one forces the V5 b yte 
to be programmed via the LOPOH serial channel. See 
Table 559 on pag e443.
0x0
1:0 VT_BIP2ERR_
INS[1—28][1:0] BIP-2 Error Insertion Control. See Table 560 on 
page 443.0x0
Address Bit Name Function Reset
Default
0x20114
—
0x2012F
15:12 —Reserved. 0x0
11:8 VT_APS_
INS[1—28][3:0] APS  Software Overwrite Value.  This nibble is  pro-
grammed  to utilize A PS bits in the Z7/K4 byte. This nibble 
will be tra nsmitted in  bits 1:4 of the Z7/K4 byte.
0x0
7:5 —Reserved. 0x0
4:2 VT_ERDI_
INS[1—28][2:0] Enhanced RDI-V Software Overwrite Values. If 
VT_ERDI_EN[1—28] (Table 198) is  a logi c one, these bits 
are written into the ERDI-V locations of the Z7 byte.
0x0
1 VT_RDI_INS[1—28] RDI-V Sof tware Overwrite Values. I f VT_RDI_EN[1—28] 
(Table 198) is a logi c one, this value will be written into the 
RDI-V locati on of the V5 byte.
0x0
0VT_RFI_INS[1—28] RFI-V Software Overwrite Values. If VT_RFI_EN[1—28] 
(Table 198) is a logi c one, this value will be written into the 
RFI-V loc ation of the V5 byte.
0x0
Address Bit Name Function Reset
Default
0x20130
—
0x2014B
15:8 VT_OBIT_
INS[1—28][7:0] Overhead Values for Software Overwrite in Asyn-
chronous Mappings . This  byte is progra mmed to uti lize 
the overhead bits in asynchronous VT/TU  mapp ings. 
VT_OBIT_I N S[7:4] wi ll be transmitted in the byte follow-
ing J2 and VT_OBIT_INS[3:0] will be tr ansmitted in the 
by te following Z6/N2.
0x00
7:0 VT_Z6BYTE_
INS[1—28][7:0]  Z 6 Softw are Overwrite Values. This  byte  is pr o -
grammed into the o utgoing Z6/N2 location when 
VT_Z6_INS[1—28][1:0]  (Table 199) = 01.
0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

168 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 202. VT_TSIG _CTL[1—28], Transmit Signaling Contro l Per Channel (R/W)

Table 203. VT_J2BYTE_INS_R [1 —28][1—16], J2 Insert Values Per Channel (R/W)

Address Bit Name Function Reset

Default

0x2014C

—

0x20167

15:11 —Reserved. 000000

10 VT_USE_FBIT[1—28] Frame Bit Use Control. Logic one provisions

use of th e F bit in the outgoing VT/TU. Other-

wise, the F bit is forced to the value of bit

SMPR _OH_DEFLT (Table 67) in the micropro-

cessor interface on the outgoin g VT/TU .

0x1

9 VT_USE_PBIT[1—28] Phase Bit Use Control. Logic one provisions

use of the P bits in the outgoing VT/T U. Other-

wise, the P bits are forced to the value of bit

SMPR_OH_DEFLT in the microprocessor inter-

face on the outgoing VT/TU.

0x1

8 VT_USE_SBIT[1—28] Signaling Bit Use Contr ol . Logic one p rovi-

sio ns us e of the S bits in the ou t going V T /TU.

Otherwise, the S bits are forced to the value of

bit SMPR_OH_DEFLT in t he mi croprocesso r

interface on the outgoing VT/TU.

0x1

7:5 —Reserved. 000

4:0 VT_TXSIG_CH_SEL[1—28][4:0] Tran smit Inp ut Ch ann el Selection. These bits

are programmed with the same value as the

cross connect for each i ndividual channel. The

bits are only used in byte synchronous mode

and can be set to 0xXX for all other modes. If an

invalid val ue is programm ed,

UNEQ-V will be transmitted in the specified

channel . Inv alid decimal values are 0, 2 9, 30,

and 31.

0x00

Address Bit Name Function Reset

Default

0x20168

—

0x20327

15:8 —Reserved. 0x00

7:0 VT_J2BYTE_

INS[1—28][1—16][7:0] J2 Software Overwrite Values. These values are written

into the outgoing J2 byte when VT_J2_INS[1—28][1:0] = 01

(Table 199).

0x00

Table 204. VT_RCTL[1—28], Re ceive Co ntrol Per Channel (R/ W)

Address Bit Name Function Reset

Default

0x20328

—

0x20343

15 VT_SF_ESF[1—28] DS1 Frame Type for Byte Synchronous Mode. Logic

one provisions an SF frame forma t. Otherwise, an ESF

frame format is prov isioned.

0x0

14 VT_WR_FBIT[1—28] F-Bit Provisioning Control. S ee Table 556, Rx Signal-

ing Behavior per Chann el on page 439.0x0

13 VT_SYNC_PBIT[1—28] P-Bit Provisioning Control. See Table 556, Rx S ignal-

ing Behavior per Chann el on page 439.0x0

Preliminary Data Sheet TMXF28155/51 Super Mapper

June 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

10 VT/TU Mapper Registers (continued)

169Agere Systems Inc.

Table 205. VT_RTUOH_CTL[1—28], Receive TU Overhead Control Per Channel (RO)

Table 206. VT_RBIP2_CNT[1—28], Receive BIP-2 Error Coun t Per Channel (RO)

Table 207. VT_RREIV_CNT[1—28], Receive REI-V Error Count Per Channe l (RO)

0x20328

—

0x20343

12:8 VT_RXSIG_CH_

SEL[1—28][4:0] Receive Output Ch annel Selection. These bi ts are pro-

grammed with the same value as the cross connect for

each individual channel. Th e bits are only use d in byte

synchronous mode and can be set to 0xXX for all other

modes. If an invalid value is programmed, UNEQ -V will

be transmitted in the specified channel. Invalid decimal

values are 0, 29, 30, and 31. See Rx Signaling Behav ior

per Channel on page 439.

0x00

7:5 VT_J2MON_

MODE[1—28][2:0] J2 Trace Monitoring Mode Control. See J2 Byte Moni-

tor and Termination (J2MON) on page 438. 0x00

4 VT_RX_ERDI_EN[1—28] Receive Path Enhanced RDI-V Enable. Logic on e

enables enhanced RDI-V. 0x0

3:0 VT_RX_

MAPTYPE[1—28][3:0] Receive Demapping Mode Control. See Table 555,

Receive VT/TU Demapping Selectio n on page 437.0x6

Address Bit Name Function Reset

Default

0x20344

—

0x2035F

15:8 VT_Z6_BYTE[1—28][7:0] Received Z6/N2 Byte Value. Accepted Z6/N2 value. 0x00

7:0 VT_OBITS[1—28][7:0] Received O Bits V al ue. Accepted overhead bits in asyn-

chronous and bit synchronous modes. VT_OBITS[7:4]

are the O bits received in the byte following J 2, and

VT_OBITS[3:0] are the O bits rec eived in the byte follow-

ing Z6/N2.

0x00

Address Bit Name Function Reset

Default

0x20360

—

0x2037B

15:12 —Reserved. 0x0

11:0 VT_BIP2ERR_

CNT[1—28][11:0] BIP-2 Error Count. BIP-2 error count updated on a 0 to

1 transition of SMPR_PMR ESET (Table 65). 0x000

Address Bit Name Function Reset

Default

0x2037C

—

0x20397

15:11 —Reserved. 0x00

10:0 VT_REI_

CNT[1—28][10:0] REI-V Error Count. REI - V error count updated on a 0 to 1

tr a n s ition of SMPR_PM R ESET. 0x000

Table 204. VT_RCTL[1—28], Receive Co ntrol Per Chan nel (R/W) (continued)

Address Bit Name Function Reset

Default

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

170 Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 208. VT_RPTR_CNT[1—28], Receive Pointer and Count Per Channel (RO)

Table 209. VT_J2BYTE_EXP_R[1—28][1—16], J2 Expected Values Per Chan nel (R/W, RO)

Address Bit Name Function Reset

Default

0x20398

—

0x203B3

15:8 VT_STORED_

PTR[1—28][7:0] Store VT/TU Pointer Locat ion. This value in dicat es th e

stored location of the V5 byte within the VT/T U m apping. 0x00

7:4 VT_PTR_

DEC[1—28][3:0] VT P ointer Decrement Count. VT pointer decrement

coun t updated on a 0 to 1 transition of

SMPR_PMRESET.

0x0

3:0 VT_PTR_

INC[1—28][3:0] VT P ointer Increment Count. VT pointer increment

coun t updated on a 0 to 1 transition of

SMPR_PMRESET.

0x0

Address Bit Name Function Reset

Default

0x203B4

—

0x20573

15:8 VT_J2BYTE_

EXP[1—28][1—16][7:0] J2 Expected Values. Th is value is programmed by the

user as an ex pected value for the J 2 byte. T he hardware

will com par e this value to the inco ming J2 sequence

when VT_J2MON_MODE[1—28][2:0] = 011 or 100

(Table 204 on pag e168).

0x00

7:0 VT_J2BYTE_

DET[1—28][1—16][7:0] J2 Detected Values. Accepted J2 seq uence or value. 0x00

Table 210. VT_THRES_CTL [1—28], Transm it Elastic Store Threshold Control (R/W)

Address Bit Name Function Reset

Default

0x20574

—

0x2058F

15 —Reserved. 0x0

14:8 VT_HIGH_

THRES[1—28][6:0] T ransmit Elastic Store High Threshold. Programm able

thresh old controlling positive justifica t io ns. 0x28

7—Reserved. 0x0

6:0 VT_LOW_

THRES[1—28][6:0] Tran sm it Ela stic Store L ow Threshold. Programmable

threshold controlling negative justifications. 0x27

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

171Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

10.2 VT/ T U Mapper Regis ter Ma p

Table 211. VT/TU Mapper Register Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VT Mapper ID—RO

0x20000 VT_VERSION_R VT_

RDY VT_VERSION[2:0] VT_ID[7:0]

VT Glob al Events—COR/COW

0x20001 VT_GDELETA VT_SD_D VT_SF_D VT_H4LOMF_

Receive Delta a nd Event Parameter s—COR/COW

0x20002 VT_REVENT_DELTA1 VT_RX_VTREI_E1 VT_RX_BIP2ERR_E1 VT_RX_ESOVFL_E1 VT_APS_D1 VT_ERDI_D1 VT_RDI_D1 VT_RFI_D1 VT_LOPS_D1 VT_J2TIM_D1 VT_PLM_D1 VT_UNEQ_D1 VT_SIZERR_D1 VT_AIS_D1 VT_LOP_D1

0x20003 VT_REVENT_DELTA2 VT_RX_VTREI_E2 VT_RX_BIP2ERR_E2 VT_RX_ESOVFL_E2 VT_APS_D2 VT_ERDI_D2 VT_RDI_D2 VT_RFI_D2 VT_LOPS_D2 VT_J2TIM_D2 VT_PLM_D2 VT_UNEQ_D2 VT_SIZERR_D2 VT_AIS_D2 VT_LOP_D2

0x20004 VT_REVENT_DELTA3 VT_RX_VTREI_E3 VT_RX_BIP2ERR_E3 VT_RX_ESOVFL_E3 VT_APS_D3 VT_ERDI_D3 VT_RDI_D3 VT_RFI_D3 VT_LOPS_D3 VT_J2TIM_D3 VT_PLM_D3 VT_UNEQ_D3 VT_SIZERR_D3 VT_AIS_D3 VT_LOP_D3

0x20005 VT_REVENT_DELTA4 VT_RX_VTREI_E4 VT_RX_BIP2ERR_E4 VT_RX_ESOVFL_E4 VT_APS_D4 VT_ERDI_D4 VT_RDI_D4 VT_RFI_D4 VT_LOPS_D4 VT_J2TIM_D4 VT_PLM_D4 VT_UNEQ_D4 VT_SIZERR_D4 VT_AIS_D4 VT_LOP_D4

0x20006 VT_REVENT_DELTA5 VT_RX_VTREI_E5 VT_RX_BIP2ERR_E5 VT_RX_ESOVFL_E5 VT_APS_D5 VT_ERDI_D5 VT_RDI_D5 VT_RFI_D5 VT_LOPS_D5 VT_J2TIM_D5 VT_PLM_D5 VT_UNEQ_D5 VT_SIZERR_D5 VT_AIS_D5 VT_LOP_D5

0x20007 VT_REVENT_DELTA6 VT_RX_VTREI_E6 VT_RX_BIP2ERR_E6 VT_RX_ESOVFL_E6 VT_APS_D6 VT_ERDI_D6 VT_RDI_D6 VT_RFI_D6 VT_LOPS_D6 VT_J2TIM_D6 VT_PLM_D6 VT_UNEQ_D6 VT_SIZERR_D6 VT_AIS_D6 VT_LOP_D6

0x20008 VT_REVENT_DELTA7 VT_RX_VTREI_E7 VT_RX_BIP2ERR_E7 VT_RX_ESOVFL_E7 VT_APS_D7 VT_ERDI_D7 VT_RDI_D7 VT_RFI_D7 VT_LOPS_D7 VT_J2TIM_D7 VT_PLM_D7 VT_UNEQ_D7 VT_SIZERR_D7 VT_AIS_D7 VT_LOP_D7

0x20009 VT_REVENT_DELTA8 VT_RX_VTREI_E8 VT_RX_BIP2ERR_E8 VT_RX_ESOVFL_E8 VT_APS_D8 VT_ERDI_D8 VT_RDI_D8 VT_RFI_D8 VT_LOPS_D8 VT_J2TIM_D8 VT_PLM_D8 VT_UNEQ_D8 VT_SIZERR_D8 VT_AIS_D8 VT_LOP_D8

0x2000A VT_REVENT_DELTA9 VT_RX_VTREI_E9 VT_RX_BIP2ERR_E9 VT_RX_ESOVFL_E9 VT_APS_D9 VT_ERDI_D9 VT_RDI_D9 VT_RFI_D9 VT_LOPS_D9 VT_J2TIM_D9 VT_PLM_D9 VT_UNEQ_D9 VT_SIZERR_D9 VT_AIS_D9 VT_LOP_D9

0x2000B VT_REVENT_DELTA10 VT_RX_VTREI_E10 VT_RX_BIP2ERR_E10 VT_RX_ESOVFL_E10 VT_APS_D10 VT_ERDI_D10 VT_RDI_D10 VT_RFI_D10 VT_LOPS_D10 VT_J2TIM_D10 VT_PLM_D10 VT_UNEQ_D10 VT_SIZERR_D10 VT_AIS_D10 VT_LOP_D10

0x2000C VT_REVENT_DELTA11 VT_RX_VTREI_E11 VT_RX_BIP2ERR_E11 VT_RX_ESOVFL_E11 VT_APS_D11 VT_ERDI_D11 VT_RDI_D11 VT_RFI_D11 VT_LOPS_D11 VT_J2TIM_D11 VT_PLM_D11 VT_UNEQ_D11 VT_SIZERR_D11 VT_AIS_D11 VT_LOP_D11

0x2000D VT_REVENT_DELTA12 VT_RX_VTREI_E12 VT_RX_BIP2ERR_E12 VT_RX_ESOVFL_E12 VT_APS_D12 VT_ERDI_D12 VT_RDI_D12 VT_RFI_D12 VT_LOPS_D12 VT_J2TIM_D12 VT_PLM_D12 VT_UNEQ_D12 VT_SIZERR_D12 VT_AIS_D12 VT_LOP_D12

0x2000E VT_REVENT_DELTA13 VT_RX_VTREI_E13 VT_RX_BIP2ERR_E13 VT_RX_ESOVFL_E13 VT_APS_D13 VT_ERDI_D13 VT_RDI_D13 VT_RFI_D13 VT_LOPS_D13 VT_J2TIM_D13 VT_PLM_D13 VT_UNEQ_D13 VT_SIZERR_D13 VT_AIS_D13 VT_LOP_D13

0x2000F VT_REVENT_DELTA14 VT_RX_VTREI_E14 VT_RX_BIP2ERR_E14 VT_RX_ESOVFL_E14 VT_APS_D14 VT_ERDI_D14 VT_RDI_D14 VT_RFI_D14 VT_LOPS_D14 VT_J2TIM_D14 VT_PLM_D14 VT_UNEQ_D14 VT_SIZERR_D14 VT_AIS_D14 VT_LOP_D14

0x20010 VT_REVENT_DELTA15 VT_RX_VTREI_E15 VT_RX_BIP2ERR_E15 VT_RX_ESOVFL_E15 VT_APS_D15 VT_ERDI_D15 VT_RDI_D15 VT_RFI_D15 VT_LOPS_D15 VT_J2TIM_D15 VT_PLM_D15 VT_UNEQ_D15 VT_SIZERR_D15 VT_AIS_D15 VT_LOP_D15

0x20011 VT_REVENT_DELTA16 VT_RX_VTREI_E16 VT_RX_BIP2ERR_E16 VT_RX_ESOVFL_E16 VT_APS_D16 VT_ERDI_D16 VT_RDI_D16 VT_RFI_D16 VT_LOPS_D16 VT_J2TIM_D16 VT_PLM_D16 VT_UNEQ_D16 VT_SIZERR_D16 VT_AIS_D16 VT_LOP_D16

0x20012 VT_REVENT_DELTA17 VT_RX_VTREI_E17 VT_RX_BIP2ERR_E17 VT_RX_ESOVFL_E17 VT_APS_D17 VT_ERDI_D17 VT_RDI_D17 VT_RFI_D17 VT_LOPS_D17 VT_J2TIM_D17 VT_PLM_D17 VT_UNEQ_D17 VT_SIZERR_D17 VT_AIS_D17 VT_LOP_D17

0x20013 VT_REVENT_DELTA18 VT_RX_VTREI_E18 VT_RX_BIP2ERR_E18 VT_RX_ESOVFL_E18 VT_APS_D18 VT_ERDI_D18 VT_RDI_D18 VT_RFI_D18 VT_LOPS_D18 VT_J2TIM_D18 VT_PLM_D18 VT_UNEQ_D18 VT_SIZERR_D18 VT_AIS_D18 VT_LOP_D18

0x20014 VT_REVENT_DELTA19 VT_RX_VTREI_E19 VT_RX_BIP2ERR_E19 VT_RX_ESOVFL_E19 VT_APS_D19 VT_ERDI_D19 VT_RDI_D19 VT_RFI_D19 VT_LOPS_D19 VT_J2TIM_D19 VT_PLM_D19 VT_UNEQ_D19 VT_SIZERR_D19 VT_AIS_D19 VT_LOP_D19

0x20015 VT_REVENT_DELTA20 VT_RX_VTREI_E20 VT_RX_BIP2ERR_E20 VT_RX_ESOVFL_E20 VT_APS_D20 VT_ERDI_D20 VT_RDI_D20 VT_RFI_D20 VT_LOPS_D20 VT_J2TIM_D20 VT_PLM_D20 VT_UNEQ_D20 VT_SIZERR_D20 VT_AIS_D20 VT_LOP_D20

0x20016 VT_REVENT_DELTA21 VT_RX_VTREI_E21 VT_RX_BIP2ERR_E21 VT_RX_ESOVFL_E21 VT_APS_D21 VT_ERDI_D21 VT_RDI_D21 VT_RFI_D21 VT_LOPS_D21 VT_J2TIM_D21 VT_PLM_D21 VT_UNEQ_D21 VT_SIZERR_D21 VT_AIS_D21 VT_LOP_D21

0x20017 VT_REVENT_DELTA22 VT_RX_VTREI_E22 VT_RX_BIP2ERR_E22 VT_RX_ESOVFL_E22 VT_APS_D22 VT_ERDI_D22 VT_RDI_D22 VT_RFI_D22 VT_LOPS_D22 VT_J2TIM_D22 VT_PLM_D22 VT_UNEQ_D22 VT_SIZERR_D22 VT_AIS_D22 VT_LOP_D22

0x20018 VT_REVENT_DELTA23 VT_RX_VTREI_E23 VT_RX_BIP2ERR_E23 VT_RX_ESOVFL_E23 VT_APS_D23 VT_ERDI_D23 VT_RDI_D23 VT_RFI_D23 VT_LOPS_D23 VT_J2TIM_D23 VT_PLM_D23 VT_UNEQ_D23 VT_SIZERR_D23 VT_AIS_D23 VT_LOP_D23

0x20019 VT_REVENT_DELTA24 VT_RX_VTREI_E24 VT_RX_BIP2ERR_E24 VT_RX_ESOVFL_E24 VT_APS_D24 VT_ERDI_D24 VT_RDI_D24 VT_RFI_D24 VT_LOPS_D24 VT_J2TIM_D24 VT_PLM_D24 VT_UNEQ_D24 VT_SIZERR_D24 VT_AIS_D24 VT_LOP_D24

0x2001A VT_REVENT_DELTA25 VT_RX_VTREI_E25 VT_RX_BIP2ERR_E25 VT_RX_ESOVFL_E25 VT_APS_D25 VT_ERDI_D25 VT_RDI_D25 VT_RFI_D25 VT_LOPS_D25 VT_J2TIM_D25 VT_PLM_D25 VT_UNEQ_D25 VT_SIZERR_D25 VT_AIS_D25 VT_LOP_D25

0x2001B VT_REVENT_DELTA26 VT_RX_VTREI_E26 VT_RX_BIP2ERR_E26 VT_RX_ESOVFL_E26 VT_APS_D26 VT_ERDI_D26 VT_RDI_D26 VT_RFI_D26 VT_LOPS_D26 VT_J2TIM_D26 VT_PLM_D26 VT_UNEQ_D26 VT_SIZERR_D26 VT_AIS_D26 VT_LOP_D26

0x2001C VT_REVENT_DELTA27 VT_RX_VTREI_E27 VT_RX_BIP2ERR_E27 VT_RX_ESOVFL_E27 VT_APS_D27 VT_ERDI_D27 VT_RDI_D27 VT_RFI_D27 VT_LOPS_D27 VT_J2TIM_D27 VT_PLM_D27 VT_UNEQ_D27 VT_SIZERR_D27 VT_AIS_D27 VT_LOP_D27

0x2001D VT_REVENT_DELTA28 VT_RX_VTREI_E28 VT_RX_BIP2ERR_E28 VT_RX_ESOVFL_E28 VT_APS_D28 VT_ERDI_D28 VT_RDI_D28 VT_RFI_D28 VT_LOPS_D28 VT_J2TIM_D28 VT_PLM_D28 VT_UNEQ_D28 VT_SIZERR_D28 VT_AIS_D28 VT_LOP_D28

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

172 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transm it Delt a and Event Parameters—COR/COW

0x2001E VT_LOPOHFAIL_EVENT VT_LOPOH_FAIL_

0x2001F VT_TEVENT_DELTA1 VT_TX_ESOVFL_E1 VT_LOFS_D1 VT_TX_AIS_D1 VT_TX_LOC_D1

0x20020 VT_TEVENT_DELTA2 VT_TX_ESOVFL_E2 VT_LOFS_D2 VT_TX_AIS_D2 VT_TX_LOC_D2

0x20021 VT_TEVENT_DELTA3 VT_TX_ESOVFL_E3 VT_LOFS_D3 VT_TX_AIS_D3 VT_TX_LOC_D3

0x20022 VT_TEVENT_DELTA4 VT_TX_ESOVFL_E4 VT_LOFS_D4 VT_TX_AIS_D4 VT_TX_LOC_D4

0x20023 VT_TEVENT_DELTA5 VT_TX_ESOVFL_E5 VT_LOFS_D5 VT_TX_AIS_D5 VT_TX_LOC_D5

0x20024 VT_TEVENT_DELTA6 VT_TX_ESOVFL_E6 VT_LOFS_D6 VT_TX_AIS_D6 VT_TX_LOC_D6

0x20025 VT_TEVENT_DELTA7 VT_TX_ESOVFL_E7 VT_LOFS_D7 VT_TX_AIS_D7 VT_TX_LOC_D7

0x20026 VT_TEVENT_DELTA8 VT_TX_ESOVFL_E8 VT_LOFS_D8 VT_TX_AIS_D8 VT_TX_LOC_D8

0x20027 VT_TEVENT_DELTA9 VT_TX_ESOVFL_E9 VT_LOFS_D9 VT_TX_AIS_D9 VT_TX_LOC_D9

0x20028 VT_TEVENT_DELTA10 VT_TX_ESOVFL_E10 VT_LOFS_D10 VT_TX_AIS_D10 VT_TX_LOC_D10

0x20029 VT_TEVENT_DELTA11 VT_TX_ESOVFL_E11 VT_LOFS_D11 VT_TX_AIS_D11 VT_TX_LOC_D11

0x2002A VT_TEVENT_DELTA12 VT_TX_ESOVFL_E12 VT_LOFS_D12 VT_TX_AIS_D12 VT_TX_LOC_D12

0x2002B VT_TEVENT_DELTA13 VT_TX_ESOVFL_E13 VT_LOFS_D13 VT_TX_AIS_D13 VT_TX_LOC_D13

0x2002C VT_TEVENT_DELTA14 VT_TX_ESOVFL_E14 VT_LOFS_D14 VT_TX_AIS_D14 VT_TX_LOC_D14

0x2002D VT_TEVENT_DELTA15 VT_TX_ESOVFL_E15 VT_LOFS_D15 VT_TX_AIS_D15 VT_TX_LOC_D15

0x2002E VT_TEVENT_DELTA16 VT_TX_ESOVFL_E16 VT_LOFS_D16 VT_TX_AIS_D16 VT_TX_LOC_D16

0x2002F VT_TEVENT_DELTA17 VT_TX_ESOVFL_E17 VT_LOFS_D17 VT_TX_AIS_D17 VT_TX_LOC_D17

0x20030 VT_TEVENT_DELTA18 VT_TX_ESOVFL_E18 VT_LOFS_D18 VT_TX_AIS_D18 VT_TX_LOC_D18

0x20031 VT_TEVENT_DELTA19 VT_TX_ESOVFL_E19 VT_LOFS_D19 VT_TX_AIS_D19 VT_TX_LOC_D19

0x20032 VT_TEVENT_DELTA20 VT_TX_ESOVFL_E20 VT_LOFS_D20 VT_TX_AIS_D20 VT_TX_LOC_D20

0x20033 VT_TEVENT_DELTA21 VT_TX_ESOVFL_E21 VT_LOFS_D21 VT_TX_AIS_D21 VT_TX_LOC_D21

0x20034 VT_TEVENT_DELTA22 VT_TX_ESOVFL_E22 VT_LOFS_D22 VT_TX_AIS_D22 VT_TX_LOC_D22

0x20035 VT_TEVENT_DELTA23 VT_TX_ESOVFL_E23 VT_LOFS_D23 VT_TX_AIS_D23 VT_TX_LOC_D23

0x20036 VT_TEVENT_DELTA24 VT_TX_ESOVFL_E24 VT_LOFS_D24 VT_TX_AIS_D24 VT_TX_LOC_D24

0x20037 VT_TEVENT_DELTA25 VT_TX_ESOVFL_E25 VT_LOFS_D25 VT_TX_AIS_D25 VT_TX_LOC_D25

0x20038 VT_TEVENT_DELTA26 VT_TX_ESOVFL_E26 VT_LOFS_D26 VT_TX_AIS_D26 VT_TX_LOC_D26

0x20039 VT_TEVENT_DELTA27 VT_TX_ESOVFL_E27 VT_LOFS_D27 VT_TX_AIS_D27 VT_TX_LOC_D27

0x2003A VT_TEVENT_DELTA28 VT_TX_ESOVFL_E28 VT_LOFS_D28 VT_TX_AIS_D28 VT_TX_LOC_D28

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

173Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VT Global Interrupt Masks—R/W

0x2003B VT_GMASK VT_SD_M VT_SF_M VT_H4LOMF_

Receive Interrupt Masks—R/W

0x2003C VT_RMASK1 VT_RX_VTREI_M1 VT_RX_BIP2ERR_M1 VT_RX_ESOVFL_M1 VT_APS_M1 VT_ERDI_M1 VT_RDI_M1 VT_RFI_M1 VT_LOPS_M1 VT_J2TIM_M1 VT_PLM_M1 VT_UNEQ_M1 VT_SIZERR_M1 VT_AIS_M1 VT_LOP_M1

0x2003D VT_RMASK2 VT_RX_VTREI_M2 VT_RX_BIP2ERR_M2 VT_RX_ESOVFL_M2 VT_APS_M2 VT_ERDI_M2 VT_RDI_M2 VT_RFI_M2 VT_LOPS_M2 VT_J2TIM_M2 VT_PLM_M2 VT_UNEQ_M2 VT_SIZERR_M2 VT_AIS_M2 VT_LOP_M2

0x2003E VT_RMASK3 VT_RX_VTREI_M3 VT_RX_BIP2ERR_M3 VT_RX_ESOVFL_M3 VT_APS_M3 VT_ERDI_M3 VT_RDI_M3 VT_RFI_M3 VT_LOPS_M3 VT_J2TIM_M3 VT_PLM_M3 VT_UNEQ_M3 VT_SIZERR_M3 VT_AIS_M3 VT_LOP_M3

0x2003F VT_RMASK4 VT_RX_VTREI_M4 VT_RX_BIP2ERR_M4 VT_RX_ESOVFL_M4 VT_APS_M4 VT_ERDI_M4 VT_RDI_M4 VT_RFI_M4 VT_LOPS_M4 VT_J2TIM_M4 VT_PLM_M4 VT_UNEQ_M4 VT_SIZERR_M4 VT_AIS_M4 VT_LOP_M4

0x20040 VT_RMASK5 VT_RX_VTREI_M5 VT_RX_BIP2ERR_M5 VT_RX_ESOVFL_M5 VT_APS_M5 VT_ERDI_M5 VT_RDI_M5 VT_RFI_M5 VT_LOPS_M5 VT_J2TIM_M5 VT_PLM_M5 VT_UNEQ_M5 VT_SIZERR_M5 VT_AIS_M5 VT_LOP_M5

0x20041 VT_RMASK6 VT_RX_VTREI_M6 VT_RX_BIP2ERR_M6 VT_RX_ESOVFL_M6 VT_APS_M6 VT_ERDI_M6 VT_RDI_M6 VT_RFI_M6 VT_LOPS_M6 VT_J2TIM_M6 VT_PLM_M6 VT_UNEQ_M6 VT_SIZERR_M6 VT_AIS_M6 VT_LOP_M6

0x20042 VT_RMASK7 VT_RX_VTREI_M7 VT_RX_BIP2ERR_M7 VT_RX_ESOVFL_M7 VT_APS_M7 VT_ERDI_M7 VT_RDI_M7 VT_RFI_M7 VT_LOPS_M7 VT_J2TIM_M7 VT_PLM_M7 VT_UNEQ_M7 VT_SIZERR_M7 VT_AIS_M7 VT_LOP_M7

0x20043 VT_RMASK8 VT_RX_VTREI_M8 VT_RX_BIP2ERR_M8 VT_RX_ESOVFL_M8 VT_APS_M8 VT_ERDI_M8 VT_RDI_M8 VT_RFI_M8 VT_LOPS_M8 VT_J2TIM_M8 VT_PLM_M8 VT_UNEQ_M8 VT_SIZERR_M8 VT_AIS_M8 VT_LOP_M8

0x20044 VT_RMASK9 VT_RX_VTREI_M9 VT_RX_BIP2ERR_M9 VT_RX_ESOVFL_M9 VT_APS_M9 VT_ERDI_M9 VT_RDI_M9 VT_RFI_M9 VT_LOPS_M9 VT_J2TIM_M9 VT_PLM_M9 VT_UNEQ_M9 VT_SIZERR_M9 VT_AIS_M9 VT_LOP_M9

0x20045 VT_RMASK10 VT_RX_VTREI_M10 VT_RX_BIP2ERR_M10 VT_RX_ESOVFL_M10 VT_APS_M10 VT_ERDI_M10 VT_RDI_M10 VT_RFI_M10 VT_LOPS_M10 VT_J2TIM_M10 VT_PLM_M10 VT_UNEQ_M10 VT_SIZERR_M10 VT_AIS_M10 VT_LOP_M10

0x20046 VT_RMASK11 VT_RX_VTREI_M11 VT_RX_BIP2ERR_M11 VT_RX_ESOVFL_M11 VT_APS_M11 VT_ERDI_M11 VT_RDI_M11 VT_RFI_M11 VT_LOPS_M11 VT_J2TIM_M11 VT_PLM_M11 VT_UNEQ_M11 VT_SIZERR_M11 VT_AIS_M11 VT_LOP_M11

0x20047 VT_RMASK12 VT_RX_VTREI_M12 VT_RX_BIP2ERR_M12 VT_RX_ESOVFL_M12 VT_APS_M12 VT_ERDI_M12 VT_RDI_M12 VT_RFI_M12 VT_LOPS_M12 VT_J2TIM_M12 VT_PLM_M12 VT_UNEQ_M12 VT_SIZERR_M12 VT_AIS_M12 VT_LOP_M12

0x20048 VT_RMASK13 VT_RX_VTREI_M13 VT_RX_BIP2ERR_M13 VT_RX_ESOVFL_M13 VT_APS_M13 VT_ERDI_M13 VT_RDI_M13 VT_RFI_M13 VT_LOPS_M13 VT_J2TIM_M13 VT_PLM_M13 VT_UNEQ_M13 VT_SIZERR_M13 VT_AIS_M13 VT_LOP_M13

0x20049 VT_RMASK14 VT_RX_VTREI_M14 VT_RX_BIP2ERR_M14 VT_RX_ESOVFL_M14 VT_APS_M14 VT_ERDI_M14 VT_RDI_M14 VT_RFI_M14 VT_LOPS_M14 VT_J2TIM_M14 VT_PLM_M14 VT_UNEQ_M14 VT_SIZERR_M14 VT_AIS_M14 VT_LOP_M14

0x2004A VT_RMASK15 VT_RX_VTREI_M15 VT_RX_BIP2ERR_M15 VT_RX_ESOVFL_M15 VT_APS_M15 VT_ERDI_M15 VT_RDI_M15 VT_RFI_M15 VT_LOPS_M15 VT_J2TIM_M15 VT_PLM_M15 VT_UNEQ_M15 VT_SIZERR_M15 VT_AIS_M15 VT_LOP_M15

0x2004B VT_RMASK16 VT_RX_VTREI_M16 VT_RX_BIP2ERR_M16 VT_RX_ESOVFL_M16 VT_APS_M16 VT_ERDI_M16 VT_RDI_M16 VT_RFI_M16 VT_LOPS_M16 VT_J2TIM_M16 VT_PLM_M16 VT_UNEQ_M16 VT_SIZERR_M16 VT_AIS_M16 VT_LOP_M16

0x2004C VT_RMASK17 VT_RX_VTREI_M17 VT_RX_BIP2ERR_M17 VT_RX_ESOVFL_M17 VT_APS_M17 VT_ERDI_M17 VT_RDI_M17 VT_RFI_M17 VT_LOPS_M17 VT_J2TIM_M17 VT_PLM_M17 VT_UNEQ_M17 VT_SIZERR_M17 VT_AIS_M17 VT_LOP_M17

0x2004D VT_RMASK18 VT_RX_VTREI_M18 VT_RX_BIP2ERR_M18 VT_RX_ESOVFL_M18 VT_APS_M18 VT_ERDI_M18 VT_RDI_M18 VT_RFI_M18 VT_LOPS_M18 VT_J2TIM_M18 VT_PLM_M18 VT_UNEQ_M18 VT_SIZERR_M18 VT_AIS_M18 VT_LOP_M18

0x2004E VT_RMASK19 VT_RX_VTREI_M19 VT_RX_BIP2ERR_M19 VT_RX_ESOVFL_M19 VT_APS_M19 VT_ERDI_M19 VT_RDI_M19 VT_RFI_M19 VT_LOPS_M19 VT_J2TIM_M19 VT_PLM_M19 VT_UNEQ_M19 VT_SIZERR_M19 VT_AIS_M19 VT_LOP_M19

0x2004F VT_RMASK20 VT_RX_VTREI_M20 VT_RX_BIP2ERR_M20 VT_RX_ESOVFL_M20 VT_APS_M20 VT_ERDI_M20 VT_RDI_M20 VT_RFI_M20 VT_LOPS_M20 VT_J2TIM_M20 VT_PLM_M20 VT_UNEQ_M20 VT_SIZERR_M20 VT_AIS_M20 VT_LOP_M20

0x20050 VT_RMASK21 VT_RX_VTREI_M21 VT_RX_BIP2ERR_M21 VT_RX_ESOVFL_M21 VT_APS_M21 VT_ERDI_M21 VT_RDI_M21 VT_RFI_M21 VT_LOPS_M21 VT_J2TIM_M21 VT_PLM_M21 VT_UNEQ_M21 VT_SIZERR_M21 VT_AIS_M21 VT_LOP_M21

0x20051 VT_RMASK22 VT_RX_VTREI_M22 VT_RX_BIP2ERR_M22 VT_RX_ESOVFL_M22 VT_APS_M22 VT_ERDI_M22 VT_RDI_M22 VT_RFI_M22 VT_LOPS_M22 VT_J2TIM_M22 VT_PLM_M22 VT_UNEQ_M22 VT_SIZERR_M22 VT_AIS_M22 VT_LOP_M22

0x20052 VT_RMASK23 VT_RX_VTREI_M23 VT_RX_BIP2ERR_M23 VT_RX_ESOVFL_M23 VT_APS_M23 VT_ERDI_M23 VT_RDI_M23 VT_RFI_M23 VT_LOPS_M23 VT_J2TIM_M23 VT_PLM_M23 VT_UNEQ_M23 VT_SIZERR_M23 VT_AIS_M23 VT_LOP_M23

0x20053 VT_RMASK24 VT_RX_VTREI_M24 VT_RX_BIP2ERR_M24 VT_RX_ESOVFL_M24 VT_APS_M24 VT_ERDI_M24 VT_RDI_M24 VT_RFI_M24 VT_LOPS_M24 VT_J2TIM_M24 VT_PLM_M24 VT_UNEQ_M24 VT_SIZERR_M24 VT_AIS_M24 VT_LOP_M24

0x20054 VT_RMASK25 VT_RX_VTREI_M25 VT_RX_BIP2ERR_M25 VT_RX_ESOVFL_M25 VT_APS_M25 VT_ERDI_M25 VT_RDI_M25 VT_RFI_M25 VT_LOPS_M25 VT_J2TIM_M25 VT_PLM_M25 VT_UNEQ_M25 VT_SIZERR_M25 VT_AIS_M25 VT_LOP_M25

0x20055 VT_RMASK26 VT_RX_VTREI_M26 VT_RX_BIP2ERR_M26 VT_RX_ESOVFL_M26 VT_APS_M26 VT_ERDI_M26 VT_RDI_M26 VT_RFI_M26 VT_LOPS_M26 VT_J2TIM_M26 VT_PLM_M26 VT_UNEQ_M26 VT_SIZERR_M26 VT_AIS_M26 VT_LOP_M26

0x20056 VT_RMASK27 VT_RX_VTREI_M27 VT_RX_BIP2ERR_M27 VT_RX_ESOVFL_M27 VT_APS_M27 VT_ERDI_M27 VT_RDI_M27 VT_RFI_M27 VT_LOPS_M27 VT_J2TIM_M27 VT_PLM_M27 VT_UNEQ_M27 VT_SIZERR_M27 VT_AIS_M27 VT_LOP_M27

0x20057 VT_RMASK28 VT_RX_VTREI_M28 VT_RX_BIP2ERR_M28 VT_RX_ESOVFL_M28 VT_APS_M28 VT_ERDI_M28 VT_RDI_M28 VT_RFI_M28 VT_LOPS_M28 VT_J2TIM_M28 VT_PLM_M28 VT_UNEQ_M28 VT_SIZERR_M28 VT_AIS_M28 VT_LOP_M28

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

174 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transm it Interr upt Masks—R/W

0x20058 VT_LOPOHFAIL_MASK VT_LOPOH_FAIL_

0x20059 VT_TMASK1 VT_TX_ESOVFL_M1 VT_LOFS_M1 VT_TX_AIS_M1 VT_TX_LOC_M1

0x2005A VT_TMASK2 VT_TX_ESOVFL_M2 VT_LOFS_M2 VT_TX_AIS_M2 VT_TX_LOC_M2

0x2005B VT_TMASK3 VT_TX_ESOVFL_M3 VT_LOFS_M3 VT_TX_AIS_M3 VT_TX_LOC_M3

0x2005C VT_TMASK4 VT_TX_ESOVFL_M4 VT_LOFS_M4 VT_TX_AIS_M4 VT_TX_LOC_M4

0x2005D VT_TMASK5 VT_TX_ESOVFL_M5 VT_LOFS_M5 VT_TX_AIS_M5 VT_TX_LOC_M5

0x2005E VT_TMASK6 VT_TX_ESOVFL_M6 VT_LOFS_M6 VT_TX_AIS_M6 VT_TX_LOC_M6

0x2005F VT_TMASK7 VT_TX_ESOVFL_M7 VT_LOFS_M7 VT_TX_AIS_M7 VT_TX_LOC_M7

0x20060 VT_TMASK8 VT_TX_ESOVFL_M8 VT_LOFS_M8 VT_TX_AIS_M8 VT_TX_LOC_M8

0x20061 VT_TMASK9 VT_TX_ESOVFL_M9 VT_LOFS_M9 VT_TX_AIS_M9 VT_TX_LOC_M9

0x20062 VT_TMASK10 VT_TX_ESOVFL_M10 VT_LOFS_M10 VT_TX_AIS_M10 VT_TX_LOC_M10

0x20063 VT_TMASK11 VT_TX_ESOVFL_M11 VT_LOFS_M11 VT_TX_AIS_M11 VT_TX_LOC_M11

0x20064 VT_TMASK12 VT_TX_ESOVFL_M12 VT_LOFS_M12 VT_TX_AIS_M12 VT_TX_LOC_M12

0x20065 VT_TMASK13 VT_TX_ESOVFL_M13 VT_LOFS_M13 VT_TX_AIS_M13 VT_TX_LOC_M13

0x20066 VT_TMASK14 VT_TX_ESOVFL_M14 VT_LOFS_M14 VT_TX_AIS_M14 VT_TX_LOC_M14

0x20067 VT_TMASK15 VT_TX_ESOVFL_M15 VT_LOFS_M15 VT_TX_AIS_M15 VT_TX_LOC_M15

0x20068 VT_TMASK16 VT_TX_ESOVFL_M16 VT_LOFS_M16 VT_TX_AIS_M16 VT_TX_LOC_M16

0x20069 VT_TMASK17 VT_TX_ESOVFL_M17 VT_LOFS_M17 VT_TX_AIS_M17 VT_TX_LOC_M17

0x2006A VT_TMASK18 VT_TX_ESOVFL_M18 VT_LOFS_M18 VT_TX_AIS_M18 VT_TX_LOC_M18

0x2006B VT_TMASK19 VT_TX_ESOVFL_M19 VT_LOFS_M19 VT_TX_AIS_M19 VT_TX_LOC_M19

0x2006C VT_TMASK20 VT_TX_ESOVFL_M20 VT_LOFS_M20 VT_TX_AIS_M20 VT_TX_LOC_M20

0x2006D VT_TMASK21 VT_TX_ESOVFL_M21 VT_LOFS_M21 VT_TX_AIS_M21 VT_TX_LOC_M21

0x2006E VT_TMASK22 VT_TX_ESOVFL_M22 VT_LOFS_M22 VT_TX_AIS_M22 VT_TX_LOC_M22

0x2006F VT_TMASK23 VT_TX_ESOVFL_M23 VT_LOFS_M23 VT_TX_AIS_M23 VT_TX_LOC_M23

0x20070 VT_TMASK24 VT_TX_ESOVFL_M24 VT_LOFS_M24 VT_TX_AIS_M24 VT_TX_LOC_M24

0x20071 VT_TMASK25 VT_TX_ESOVFL_M25 VT_LOFS_M25 VT_TX_AIS_M25 VT_TX_LOC_M25

0x20072 VT_TMASK26 VT_TX_ESOVFL_M26 VT_LOFS_M26 VT_TX_AIS_M26 VT_TX_LOC_M26

0x20073 VT_TMASK27 VT_TX_ESOVFL_M27 VT_LOFS_M27 VT_TX_AIS_M27 VT_TX_LOC_M27

0x20074 VT_TMASK28 VT_TX_ESOVFL_M28 VT_LOFS_M28 VT_TX_AIS_M28 VT_TX_LOC_M28

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

175Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive S tate Parameters—RO

0x20075 VT_GSTATE VT_SD VT_SF VT_H4LOMF

0x20076 VT_RSTATE1 VT_ERDI(1)[2:0] VT_LAB(1)[2:0] VT_RDI(1) VT_RFI1 VT_LOPS1 VT_J2TIM1 VT_PLM1 VT_UNEQ1 VT_SIZERR1 VT_AIS1 VT_LOP1

0x20077 VT_RSTATE2 VT_ERDI(2)[2:0] VT_LAB(2)[2:0] VT_RDI(2) VT_RFI2 VT_LOPS2 VT_J2TIM2 VT_PLM2 VT_UNEQ2 VT_SIZERR2 VT_AIS2 VT_LOP2

0x20078 VT_RSTATE3 VT_ERDI(3)[2:0] VT_LAB(3)[2:0] VT_RDI(3) VT_RFI3 VT_LOPS3 VT_J2TIM3 VT_PLM3 VT_UNEQ3 VT_SIZERR3 VT_AIS3 VT_LOP3

0x20079 VT_RSTATE4 VT_ERDI(4)[2:0] VT_LAB(4)[2:0] VT_RDI(4) VT_RFI4 VT_LOPS4 VT_J2TIM4 VT_PLM4 VT_UNEQ4 VT_SIZERR4 VT_AIS4 VT_LOP4

0x2007A VT_RSTATE5 VT_ERDI(5)[2:0] VT_LAB(5)[2:0] VT_RDI(5) VT_RFI5 VT_LOPS5 VT_J2TIM5 VT_PLM5 VT_UNEQ5 VT_SIZERR5 VT_AIS5 VT_LOP5

0x2007B VT_RSTATE6 VT_ERDI(6)[2:0] VT_LAB(6)[2:0] VT_RDI(6) VT_RFI6 VT_LOPS6 VT_J2TIM6 VT_PLM6 VT_UNEQ6 VT_SIZERR6 VT_AIS6 VT_LOP6

0x2007C VT_RSTATE7 VT_ERDI(7)[2:0] VT_LAB(7)[2:0] VT_RDI(7) VT_RFI7 VT_LOPS7 VT_J2TIM7 VT_PLM7 VT_UNEQ7 VT_SIZERR7 VT_AIS7 VT_LOP7

0x2007D VT_RSTATE8 VT_ERDI(8)[2:0] VT_LAB(8)[2:0] VT_RDI(8) VT_RFI8 VT_LOPS8 VT_J2TIM8 VT_PLM8 VT_UNEQ8 VT_SIZERR8 VT_AIS8 VT_LOP8

0x2007E VT_RSTATE9 VT_ERDI(9)[2:0] VT_LAB(9)[2:0] VT_RDI(9) VT_RFI9 VT_LOPS9 VT_J2TIM9 VT_PLM9 VT_UNEQ9 VT_SIZERR9 VT_AIS9 VT_LOP9

0x2007F VT_RSTATE10 VT_ERDI(10)[2:0] VT_LAB(10)[2:0] VT_RDI(10) VT_RFI10 VT_LOPS10 VT_J2TIM10 VT_PLM10 VT_UNEQ10 VT_SIZERR10 VT_AIS10 VT_LOP10

0x20080 VT_RSTATE11 VT_ERDI(11)[2:0] VT_LAB(11)[2:0] VT_RDI(11) VT_RFI11 VT_LOPS11 VT_J2TIM11 VT_PLM11 VT_UNEQ11 VT_SIZERR11 VT_AIS11 VT_LOP11

0x20081 VT_RSTATE12 VT_ERDI(12)[2:0] VT_LAB(12)[2:0] VT_RDI(12) VT_RFI12 VT_LOPS12 VT_J2TIM12 VT_PLM12 VT_UNEQ12 VT_SIZERR12 VT_AIS12 VT_LOP12

0x20082 VT_RSTATE13 VT_ERDI(13)[2:0] VT_LAB(13)[2:0] VT_RDI(13) VT_RFI13 VT_LOPS13 VT_J2TIM13 VT_PLM13 VT_UNEQ13 VT_SIZERR13 VT_AIS13 VT_LOP13

0x20083 VT_RSTATE14 VT_ERDI(14)[2:0] VT_LAB(14)[2:0] VT_RDI(14) VT_RFI14 VT_LOPS14 VT_J2TIM14 VT_PLM14 VT_UNEQ14 VT_SIZERR14 VT_AIS14 VT_LOP14

0x20084 VT_RSTATE15 VT_ERDI(15)[2:0] VT_LAB(15)[2:0] VT_RDI(15) VT_RFI15 VT_LOPS15 VT_J2TIM15 VT_PLM15 VT_UNEQ15 VT_SIZERR15 VT_AIS15 VT_LOP15

0x20085 VT_RSTATE16 VT_ERDI(16)[2:0] VT_LAB(16)[2:0] VT_RDI(16) VT_RFI16 VT_LOPS16 VT_J2TIM16 VT_PLM16 VT_UNEQ16 VT_SIZERR16 VT_AIS16 VT_LOP16

0x20086 VT_RSTATE17 VT_ERDI(17)[2:0] VT_LAB(17)[2:0] VT_RDI(17) VT_RFI17 VT_LOPS17 VT_J2TIM17 VT_PLM17 VT_UNEQ17 VT_SIZERR17 VT_AIS17 VT_LOP17

0x20087 VT_RSTATE18 VT_ERDI(18)[2:0] VT_LAB(18)[2:0] VT_RDI(18) VT_RFI18 VT_LOPS18 VT_J2TIM18 VT_PLM18 VT_UNEQ18 VT_SIZERR18 VT_AIS18 VT_LOP18

0x20088 VT_RSTATE19 VT_ERDI(19)[2:0] VT_LAB(19)[2:0] VT_RDI(19) VT_RFI19 VT_LOPS19 VT_J2TIM19 VT_PLM19 VT_UNEQ19 VT_SIZERR19 VT_AIS19 VT_LOP19

0x20089 VT_RSTATE20 VT_ERDI(20)[2:0] VT_LAB(20)[2:0] VT_RDI(20) VT_RFI20 VT_LOPS20 VT_J2TIM20 VT_PLM20 VT_UNEQ20 VT_SIZERR20 VT_AIS20 VT_LOP20

0x2008A VT_RSTATE21 VT_ERDI(21)[2:0] VT_LAB(21)[2:0] VT_RDI(21) VT_RFI21 VT_LOPS21 VT_J2TIM21 VT_PLM21 VT_UNEQ21 VT_SIZERR21 VT_AIS21 VT_LOP21

0x2008B VT_RSTATE22 VT_ERDI(22)[2:0] VT_LAB(22)[2:0] VT_RDI(22) VT_RFI22 VT_LOPS22 VT_J2TIM22 VT_PLM22 VT_UNEQ22 VT_SIZERR22 VT_AIS22 VT_LOP22

0x2008C VT_RSTATE23 VT_ERDI(23)[2:0] VT_LAB(23)[2:0] VT_RDI(23) VT_RFI23 VT_LOPS23 VT_J2TIM23 VT_PLM23 VT_UNEQ23 VT_SIZERR23 VT_AIS23 VT_LOP23

0x2008D VT_RSTATE24 VT_ERDI(24)[2:0] VT_LAB(24)[2:0] VT_RDI(24) VT_RFI24 VT_LOPS24 VT_J2TIM24 VT_PLM24 VT_UNEQ24 VT_SIZERR24 VT_AIS24 VT_LOP24

0x2008E VT_RSTATE25 VT_ERDI(25)[2:0] VT_LAB(25)[2:0] VT_RDI(25) VT_RFI25 VT_LOPS25 VT_J2TIM25 VT_PLM25 VT_UNEQ25 VT_SIZERR25 VT_AIS25 VT_LOP25

0x2008F VT_RSTATE26 VT_ERDI(26)[2:0] VT_LAB(26)[2:0] VT_RDI(26) VT_RFI26 VT_LOPS26 VT_J2TIM26 VT_PLM26 VT_UNEQ26 VT_SIZERR26 VT_AIS26 VT_LOP26

0x20090 VT_RSTATE27 VT_ERDI(27)[2:0] VT_LAB(27)[2:0] VT_RDI(27) VT_RFI27 VT_LOPS27 VT_J2TIM27 VT_PLM27 VT_UNEQ27 VT_SIZERR27 VT_AIS27 VT_LOP27

0x20091 VT_RSTATE28 VT_ERDI(28)[2:0] VT_LAB(28)[2:0] VT_RDI(28) VT_RFI28 VT_LOPS28 VT_J2TIM28 VT_PLM28 VT_UNEQ28 VT_SIZERR28 VT_AIS28 VT_LOP28

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

176 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive APS Value Paramete rs—RO

0x20092 VT_RAPSSTATE1 VT_APS(1)[3:0]

0x20093 VT_RAPSSTATE2 VT_APS(2)[3:0]

0x20094 VT_RAPSSTATE3 VT_APS(3)[3:0]

0x20095 VT_RAPSSTATE4 VT_APS(4)[3:0]

0x20096 VT_RAPSSTATE5 VT_APS(5)[3:0]

0x20097 VT_RAPSSTATE6 VT_APS(6)[3:0]

0x20098 VT_RAPSSTATE7 VT_APS(7)[3:0]

0x20099 VT_RAPSSTATE8 VT_APS(8)[3:0]

0x2009A VT_RAPSSTATE9 VT_APS(9)[3:0]

0x2009B VT_RAPSSTATE10 VT_APS(10)[3:0]

0x2009C VT_RAPSSTATE11 VT_APS(11)[3:0]

0x2009D VT_RAPSSTATE12 VT_APS(12)[3:0]

0x2009E VT_RAPSSTATE13 VT_APS(13)[3:0]

0x2009F VT_RAPSSTATE14 VT_APS(14)[3:0]

0x200A0 VT_RAPSSTATE15 VT_APS(15)[3:0]

0x200A1 VT_RAPSSTATE16 VT_APS(16)[3:0]

0x200A2 VT_RAPSSTATE17 VT_APS(17)[3:0]

0x200A3 VT_RAPSSTATE18 VT_APS(18)[3:0]

0x200A4 VT_RAPSSTATE19 VT_APS(19)[3:0]

0x200A5 VT_RAPSSTATE20 VT_APS(20)[3:0]

0x200A6 VT_RAPSSTATE21 VT_APS(21)[3:0]

0x200A7 VT_RAPSSTATE22 VT_APS(22)[3:0]

0x200A8 VT_RAPSSTATE23 VT_APS(23)[3:0]

0x200A9 VT_RAPSSTATE24 VT_APS(24)[3:0]

0x200AA VT_RAPSSTATE25 VT_APS(25)[3:0]

0x200AB VT_RAPSSTATE26 VT_APS(26)[3:0]

0x200AC VT_RAPSSTATE27 VT_APS(27)[3:0]

0x200AD VT_RAPSSTATE28 VT_APS(28)[3:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

177Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T ransmit State Parameters—RO

0x200AE VT_TSTATE1 VT_LOFS1 VT_TX_AIS1 VT_TX_LOC1

0x200AF VT_TSTATE2 VT_LOFS2 VT_TX_AIS2 VT_TX_LOC2

0x200B0 VT_TSTATE3 VT_LOFS3 VT_TX_AIS3 VT_TX_LOC3

0x200B1 VT_TSTATE4 VT_LOFS4 VT_TX_AIS4 VT_TX_LOC4

0x200B2 VT_TSTATE5 VT_LOFS5 VT_TX_AIS5 VT_TX_LOC5

0x200B3 VT_TSTATE6 VT_LOFS6 VT_TX_AIS6 VT_TX_LOC6

0x200B4 VT_TSTATE7 VT_LOFS7 VT_TX_AIS7 VT_TX_LOC7

0x200B5 VT_TSTATE8 VT_LOFS8 VT_TX_AIS8 VT_TX_LOC8

0x200B6 VT_TSTATE9 VT_LOFS9 VT_TX_AIS9 VT_TX_LOC9

0x200B7 VT_TSTATE10 VT_LOFS10 VT_TX_AIS10 VT_TX_LOC10

0x200B8 VT_TSTATE11 VT_LOFS11 VT_TX_AIS11 VT_TX_LOC11

0x200B9 VT_TSTATE12 VT_LOFS12 VT_TX_AIS12 VT_TX_LOC12

0x200BA VT_TSTATE13 VT_LOFS13 VT_TX_AIS13 VT_TX_LOC13

0x200BB VT_TSTATE14 VT_LOFS14 VT_TX_AIS14 VT_TX_LOC14

0x200BC VT_TSTATE15 VT_LOFS15 VT_TX_AIS15 VT_TX_LOC15

0x200BD VT_TSTATE16 VT_LOFS16 VT_TX_AIS16 VT_TX_LOC16

0x200BE VT_TSTATE17 VT_LOFS17 VT_TX_AIS17 VT_TX_LOC17

0x200BF VT_TSTATE18 VT_LOFS18 VT_TX_AIS18 VT_TX_LOC18

0x200C0 VT_TSTATE19 VT_LOFS19 VT_TX_AIS19 VT_TX_LOC19

0x200C1 VT_TSTATE20 VT_LOFS20 VT_TX_AIS20 VT_TX_LOC20

0x200C2 VT_TSTATE21 VT_LOFS21 VT_TX_AIS21 VT_TX_LOC21

0x200C3 VT_TSTATE22 VT_LOFS22 VT_TX_AIS22 VT_TX_LOC22

0x200C4 VT_TSTATE23 VT_LOFS23 VT_TX_AIS23 VT_TX_LOC23

0x200C5 VT_TSTATE24 VT_LOFS24 VT_TX_AIS24 VT_TX_LOC24

0x200C6 VT_TSTATE25 VT_LOFS25 VT_TX_AIS25 VT_TX_LOC25

0x200C7 VT_TSTATE26 VT_LOFS26 VT_TX_AIS26 VT_TX_LOC26

0x200C8 VT_TSTATE27 VT_LOFS27 VT_TX_AIS27 VT_TX_LOC27

0x200C9 VT_TSTATE28 VT_LOFS28 VT_TX_AIS28 VT_TX_LOC28

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

178 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VT Global Control Parameters—R/W

0x200CA VT_GCTL1 VT_RX_GRP_TYPE[6:0] VT_TX_GRP_TYPE[6:0]

0x200CB VT_GCTL2 VT_LOPS_AIS

_INH VT_J2TIM_ER

DI_INH VT_J2TIM_RDI

_INH VT_J2TIM_AIS

_INH VT_LOMF_AIS

_INH VT_PLM_AIS_I

NH VT_UNEQ_AIS

_INH VT_UPSR VT_8ORMAJO

RITY VT_BIT_BLO

CK_CNT

0x200CC VT_GCTL3 VT_LOPS_NTIME[3:0] VT_H4_NTIME[3:0]

0x200CD VT_GCTL4 VT_Z6_NTIME[3:0] VT_J2_NTIME[3:0] VT_INV_NTIME[3:0] VT_NDF_NTIME[3:0]

0x200CE VT_GCTL5 VT_APS_NTIME[3:0] VT_LAB_NTIME[3:0] VT_ERDI_NTIME[3:0] VT_RDI_NTIME[3:0]

Signal Degrade Control—R/W

0x200CF VT_SIGDEG_

CTL1 VT_SFCLEAR VT_SFSET VT_SDCLEAR VT_SDSET VT_BER_CH_SEL[4:0]

0x200D0 VT_SIGDEG_

CTL2 VT_SDNSSET[18:3]

0x200D1 VT_SIGDEG_

CTL3 VT_SDMSET[7:0] VT_SDLSET[3:0] VT_SDNSSET[2:0]

0x200D2 VT_SIGDEG_

CTL4 VT_SDBSET[15:0]

0x200D3 VT_SIGDEG_

CTL5 VT_SDNSCLEAR[18:3]

0x200D4 VT_SIGDEG_

CTL6 VT_SDMCLEAR[7:0] VT_SDLCLEAR[3:0] VT_SDNSCLEAR[2:0]

0x200D5 VT_SIGDEG_

CTL7 VT_SDBCLEAR[15:0]

Signal Fail Control—R/W

0x200D6 VT_SIGFAIL_

CTL1 VT_SFNSSET[18:3]

0x200D7 VT_SIGFAIL_

CTL2 VT_SFMSET[7:0] VT_SFLSET[3:0] VT_SFNSSET[2:0]

0x200D8 VT_SIGFAIL_

CTL3 VT_SFBSET[15:0]

0x200D9 VT_SIGFAIL_

CTL4 VT_SFNSCLEAR[18:3]

0x200DA VT_SIGFAIL_

CTL5 VT_SFMCLEAR[7:0] VT_SFLCLEAR[3:0] VT_SFNSCLEAR[2:0]

0x200DB VT_SIGFAIL_

CTL6 VT_SFBCLEAR[15:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

179Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T ransmit Contro l P aram et ers—R/W

0x200DC VT_TCTL1 VT_TX_ERDI_EN1 VT_ERDI_EN1 VT_RDI_EN1 VT_RFI_EN1 VT_REI_EN1 VT_AIS_INS1 VT_TX_CLKEDGE1 VT_LB_SEL1 VT_TX_MAPTYPE(1)[3:0]

0x200DD VT_TCTL2 VT_TX_ERDI_EN2 VT_ERDI_EN2 VT_RDI_EN2 VT_RFI_EN2 VT_REI_EN2 VT_AIS_INS2 VT_TX_CLKEDGE2 VT_LB_SEL2 VT_TX_MAPTYPE(2)[3:0]

0x200DE VT_TCTL3 VT_TX_ERDI_EN3 VT_ERDI_EN3 VT_RDI_EN3 VT_RFI_EN3 VT_REI_EN3 VT_AIS_INS3 VT_TX_CLKEDGE3 VT_LB_SEL3 VT_TX_MAPTYPE(3)[3:0]

0x200DF VT_TCTL4 VT_TX_ERDI_EN4 VT_ERDI_EN4 VT_RDI_EN4 VT_RFI_EN4 VT_REI_EN4 VT_AIS_INS4 VT_TX_CLKEDGE4 VT_LB_SEL4 VT_TX_MAPTYPE(4)[3:0]

0x200E0 VT_TCTL5 VT_TX_ERDI_EN5 VT_ERDI_EN5 VT_RDI_EN5 VT_RFI_EN5 VT_REI_EN5 VT_AIS_INS5 VT_TX_CLKEDGE5 VT_LB_SEL5 VT_TX_MAPTYPE(5)[3:0]

0x200E1 VT_TCTL6 VT_TX_ERDI_EN6 VT_ERDI_EN6 VT_RDI_EN6 VT_RFI_EN6 VT_REI_EN6 VT_AIS_INS6 VT_TX_CLKEDGE6 VT_LB_SEL6 VT_TX_MAPTYPE(6)[3:0]

0x200E2 VT_TCTL7 VT_TX_ERDI_EN7 VT_ERDI_EN7 VT_RDI_EN7 VT_RFI_EN7 VT_REI_EN7 VT_AIS_INS7 VT_TX_CLKEDGE7 VT_LB_SEL7 VT_TX_MAPTYPE(7)[3:0]

0x200E3 VT_TCTL8 VT_TX_ERDI_EN8 VT_ERDI_EN8 VT_RDI_EN8 VT_RFI_EN8 VT_REI_EN8 VT_AIS_INS8 VT_TX_CLKEDGE8 VT_LB_SEL8 VT_TX_MAPTYPE(8)[3:0]

0x200E4 VT_TCTL9 VT_TX_ERDI_EN9 VT_ERDI_EN9 VT_RDI_EN9 VT_RFI_EN9 VT_REI_EN9 VT_AIS_INS9 VT_TX_CLKEDGE9 VT_LB_SEL9 VT_TX_MAPTYPE(9)[3:0]

0x200E5 VT_TCTL10 VT_TX_ERDI_EN10 VT_ERDI_EN10 VT_RDI_EN10 VT_RFI_EN10 VT_REI_EN10 VT_AIS_INS10 VT_TX_CLKEDGE10 VT_LB_SEL10 VT_TX_MAPTYPE(10)[3:0]

0x200E6 VT_TCTL11 VT_TX_ERDI_EN11 VT_ERDI_EN11 VT_RDI_EN11 VT_RFI_EN11 VT_REI_EN11 VT_AIS_INS11 VT_TX_CLKEDGE11 VT_LB_SEL11 VT_TX_MAPTYPE(11)[3:0]

0x200E7 VT_TCTL12 VT_TX_ERDI_EN12 VT_ERDI_EN12 VT_RDI_EN12 VT_RFI_EN12 VT_REI_EN12 VT_AIS_INS12 VT_TX_CLKEDGE12 VT_LB_SEL12 VT_TX_MAPTYPE(12)[3:0]

0x200E8 VT_TCTL13 VT_TX_ERDI_EN13 VT_ERDI_EN13 VT_RDI_EN13 VT_RFI_EN13 VT_REI_EN13 VT_AIS_INS13 VT_TX_CLKEDGE13 VT_LB_SEL13 VT_TX_MAPTYPE(13)[3:0]

0x200E9 VT_TCTL14 VT_TX_ERDI_EN14 VT_ERDI_EN14 VT_RDI_EN14 VT_RFI_EN14 VT_REI_EN14 VT_AIS_INS14 VT_TX_CLKEDGE14 VT_LB_SEL14 VT_TX_MAPTYPE(14)[3:0]

0x200EA VT_TCTL15 VT_TX_ERDI_EN15 VT_ERDI_EN15 VT_RDI_EN15 VT_RFI_EN15 VT_REI_EN15 VT_AIS_INS15 VT_TX_CLKEDGE15 VT_LB_SEL15 VT_TX_MAPTYPE(15)[3:0]

0x200EB VT_TCTL16 VT_TX_ERDI_EN16 VT_ERDI_EN16 VT_RDI_EN16 VT_RFI_EN16 VT_REI_EN16 VT_AIS_INS16 VT_TX_CLKEDGE16 VT_LB_SEL16 VT_TX_MAPTYPE(16)[3:0]

0x200EC VT_TCTL17 VT_TX_ERDI_EN17 VT_ERDI_EN17 VT_RDI_EN17 VT_RFI_EN17 VT_REI_EN17 VT_AIS_INS17 VT_TX_CLKEDGE17 VT_LB_SEL17 VT_TX_MAPTYPE(17)[3:0]

0x200ED VT_TCTL18 VT_TX_ERDI_EN18 VT_ERDI_EN18 VT_RDI_EN18 VT_RFI_EN18 VT_REI_EN18 VT_AIS_INS18 VT_TX_CLKEDGE18 VT_LB_SEL18 VT_TX_MAPTYPE(18)[3:0]

0x200EE VT_TCTL19 VT_TX_ERDI_EN19 VT_ERDI_EN19 VT_RDI_EN19 VT_RFI_EN19 VT_REI_EN19 VT_AIS_INS19 VT_TX_CLKEDGE19 VT_LB_SEL19 VT_TX_MAPTYPE(19)[3:0]

0x200EF VT_TCTL20 VT_TX_ERDI_EN20 VT_ERDI_EN20 VT_RDI_EN20 VT_RFI_EN20 VT_REI_EN20 VT_AIS_INS20 VT_TX_CLKEDGE20 VT_LB_SEL20 VT_TX_MAPTYPE(20)[3:0]

0x200F0 VT_TCTL21 VT_TX_ERDI_EN21 VT_ERDI_EN21 VT_RDI_EN21 VT_RFI_EN21 VT_REI_EN21 VT_AIS_INS21 VT_TX_CLKEDGE21 VT_LB_SEL21 VT_TX_MAPTYPE(21)[3:0]

0x200F1 VT_TCTL22 VT_TX_ERDI_EN22 VT_ERDI_EN22 VT_RDI_EN22 VT_RFI_EN22 VT_REI_EN22 VT_AIS_INS22 VT_TX_CLKEDGE22 VT_LB_SEL22 VT_TX_MAPTYPE(22)[3:0]

0x200F2 VT_TCTL23 VT_TX_ERDI_EN23 VT_ERDI_EN23 VT_RDI_EN23 VT_RFI_EN23 VT_REI_EN23 VT_AIS_INS23 VT_TX_CLKEDGE23 VT_LB_SEL23 VT_TX_MAPTYPE(23)[3:0]

0x200F3 VT_TCTL24 VT_TX_ERDI_EN24 VT_ERDI_EN24 VT_RDI_EN24 VT_RFI_EN24 VT_REI_EN24 VT_AIS_INS24 VT_TX_CLKEDGE24 VT_LB_SEL24 VT_TX_MAPTYPE(24)[3:0]

0x200F4 VT_TCTL25 VT_TX_ERDI_EN25 VT_ERDI_EN25 VT_RDI_EN25 VT_RFI_EN25 VT_REI_EN25 VT_AIS_INS25 VT_TX_CLKEDGE25 VT_LB_SEL25 VT_TX_MAPTYPE(25)[3:0]

0x200F5 VT_TCTL26 VT_TX_ERDI_EN26 VT_ERDI_EN26 VT_RDI_EN26 VT_RFI_EN26 VT_REI_EN26 VT_AIS_INS26 VT_TX_CLKEDGE26 VT_LB_SEL26 VT_TX_MAPTYPE(26)[3:0]

0x200F6 VT_TCTL27 VT_TX_ERDI_EN27 VT_ERDI_EN27 VT_RDI_EN27 VT_RFI_EN27 VT_REI_EN27 VT_AIS_INS27 VT_TX_CLKEDGE27 VT_LB_SEL27 VT_TX_MAPTYPE(27)[3:0]

0x200F7 VT_TCTL28 VT_TX_ERDI_EN28 VT_ERDI_EN28 VT_RDI_EN28 VT_RFI_EN28 VT_REI_EN28 VT_AIS_INS28 VT_TX_CLKEDGE28 VT_LB_SEL28 VT_TX_MAPTYPE(28)[3:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

180 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit TU OH Control Parameters—R/W

0x200F8 VT_TTUOH_CTL1 VT_O_INS(1)[1:0] VT_Z7_INS(1)[1:0] VT_Z6_INS(1)[1:0] VT_J2_INS(1)[1:0] VT_V5_INS1 VT_BIP2ERR_INS(1)[1:0]

0x200F9 VT_TTUOH_CTL2 VT_O_INS(2)[1:0] VT_Z7_INS(2)[1:0] VT_Z6_INS(2)[1:0] VT_J2_INS(2)[1:0] VT_V5_INS2 VT_BIP2ERR_INS(2)[1:0]

0x200FA VT_TTUOH_CTL3 VT_O_INS(3)[1:0] VT_Z7_INS(3)[1:0] VT_Z6_INS(3)[1:0] VT_J2_INS(3)[1:0] VT_V5_INS3 VT_BIP2ERR_INS(3)[1:0]

0x200FB VT_TTUOH_CTL4 VT_O_INS(4)[1:0] VT_Z7_INS(4)[1:0] VT_Z6_INS(4)[1:0] VT_J2_INS(4)[1:0] VT_V5_INS4 VT_BIP2ERR_INS(4)[1:0]

0x200FC VT_TTUOH_CTL5 VT_O_INS(5)[1:0] VT_Z7_INS(5)[1:0] VT_Z6_INS(5)[1:0] VT_J2_INS(5)[1:0] VT_V5_INS5 VT_BIP2ERR_INS(5)[1:0]

0x200FD VT_TTUOH_CTL6 VT_O_INS(6)[1:0] VT_Z7_INS(6)[1:0] VT_Z6_INS(6)[1:0] VT_J2_INS(6)[1:0] VT_V5_INS6 VT_BIP2ERR_INS(6)[1:0]

0x200FE VT_TTUOH_CTL7 VT_O_INS(7)[1:0] VT_Z7_INS(7)[1:0] VT_Z6_INS(7)[1:0] VT_J2_INS(7)[1:0] VT_V5_INS7 VT_BIP2ERR_INS(7)[1:0]

0x200FF VT_TTUOH_CTL8 VT_O_INS(8)[1:0] VT_Z7_INS(8)[1:0] VT_Z6_INS(8)[1:0] VT_J2_INS(8)[1:0] VT_V5_INS8 VT_BIP2ERR_INS(8)[1:0]

0x20100 VT_TTUOH_CTL9 VT_O_INS(9)[1:0] VT_Z7_INS(9)[1:0] VT_Z6_INS(9)[1:0] VT_J2_INS(9)[1:0] VT_V5_INS9 VT_BIP2ERR_INS(9)[1:0]

0x20101 VT_TTUOH_CTL10 VT_O_INS(10)[1:0] VT_Z7_INS(10)[1:0] VT_Z6_INS(10)[1:0] VT_J2_INS(10)[1:0] VT_V5_INS10 VT_BIP2ERR_INS(10)[1:0]

0x20102 VT_TTUOH_CTL11 VT_O_INS(11)[1:0] VT_Z7_INS(11)[1:0] VT_Z6_INS(11)[1:0] VT_J2_INS(11)[1:0] VT_V5_INS11 VT_BIP2ERR_INS(11)[1:0]

0x20103 VT_TTUOH_CTL12 VT_O_INS(12)[1:0] VT_Z7_INS(12)[1:0] VT_Z6_INS(12)[1:0] VT_J2_INS(12)[1:0] VT_V5_INS12 VT_BIP2ERR_INS(12)[1:0]

0x20104 VT_TTUOH_CTL13 VT_O_INS(13)[1:0] VT_Z7_INS(13)[1:0] VT_Z6_INS(13)[1:0] VT_J2_INS(13)[1:0] VT_V5_INS13 VT_BIP2ERR_INS(13)[1:0]

0x20105 VT_TTUOH_CTL14 VT_O_INS(14)[1:0] VT_Z7_INS(14)[1:0] VT_Z6_INS(14)[1:0] VT_J2_INS(14)[1:0] VT_V5_INS14 VT_BIP2ERR_INS(14)[1:0]

0x20106 VT_TTUOH_CTL15 VT_O_INS(15)[1:0] VT_Z7_INS(15)[1:0] VT_Z6_INS(15)[1:0] VT_J2_INS(15)[1:0] VT_V5_INS15 VT_BIP2ERR_INS(15)[1:0]

0x20107 VT_TTUOH_CTL16 VT_O_INS(16)[1:0] VT_Z7_INS(16)[1:0] VT_Z6_INS(16)[1:0] VT_J2_INS(16)[1:0] VT_V5_INS16 VT_BIP2ERR_INS(16)[1:0]

0x20108 VT_TTUOH_CTL17 VT_O_INS(17)[1:0] VT_Z7_INS(17)[1:0] VT_Z6_INS(17)[1:0] VT_J2_INS(17)[1:0] VT_V5_INS17 VT_BIP2ERR_INS(17)[1:0]

0x20109 VT_TTUOH_CTL18 VT_O_INS(18)[1:0] VT_Z7_INS(18)[1:0] VT_Z6_INS(18)[1:0] VT_J2_INS(18)[1:0] VT_V5_INS18 VT_BIP2ERR_INS(18)[1:0]

0x2010A VT_TTUOH_CTL19 VT_O_INS(19)[1:0] VT_Z7_INS(19)[1:0] VT_Z6_INS(19)[1:0] VT_J2_INS(19)[1:0] VT_V5_INS19 VT_BIP2ERR_INS(19)[1:0]

0x2010B VT_TTUOH_CTL20 VT_O_INS(20)[1:0] VT_Z7_INS(20)[1:0] VT_Z6_INS(20)[1:0] VT_J2_INS(20)[1:0] VT_V5_INS20 VT_BIP2ERR_INS(20)[1:0]

0x2010C VT_TTUOH_CTL21 VT_O_INS(21)[1:0] VT_Z7_INS(21)[1:0] VT_Z6_INS(21)[1:0] VT_J2_INS(21)[1:0] VT_V5_INS21 VT_BIP2ERR_INS(21)[1:0]

0x2010D VT_TTUOH_CTL22 VT_O_INS(22)[1:0] VT_Z7_INS(22)[1:0] VT_Z6_INS(22)[1:0] VT_J2_INS(22)[1:0] VT_V5_INS22 VT_BIP2ERR_INS(22)[1:0]

0x2010E VT_TTUOH_CTL23 VT_O_INS(23)[1:0] VT_Z7_INS(23)[1:0] VT_Z6_INS(23)[1:0] VT_J2_INS(23)[1:0] VT_V5_INS23 VT_BIP2ERR_INS(23)[1:0]

0x2010F VT_TTUOH_CTL24 VT_O_INS(24)[1:0] VT_Z7_INS(24)[1:0] VT_Z6_INS(24)[1:0] VT_J2_INS(24)[1:0] VT_V5_INS24 VT_BIP2ERR_INS(24)[1:0]

0x20110 VT_TTUOH_CTL25 VT_O_INS(25)[1:0] VT_Z7_INS(25)[1:0] VT_Z6_INS(25)[1:0] VT_J2_INS(25)[1:0] VT_V5_INS25 VT_BIP2ERR_INS(25)[1:0]

0x20111 VT_TTUOH_CTL26 VT_O_INS(26)[1:0] VT_Z7_INS(26)[1:0] VT_Z6_INS(26)[1:0] VT_J2_INS(26)[1:0] VT_V5_INS26 VT_BIP2ERR_INS(26)[1:0]

0x20112 VT_TTUOH_CTL27 VT_O_INS(27)[1:0] VT_Z7_INS(27)[1:0] VT_Z6_INS(27)[1:0] VT_J2_INS(27)[1:0] VT_V5_INS27 VT_BIP2ERR_INS(27)[1:0]

0x20113 VT_TTUOH_CTL28 VT_O_INS(28)[1:0] VT_Z7_INS(28)[1:0] VT_Z6_INS(28)[1:0] VT_J2_INS(28)[1:0] VT_V5_INS28 VT_BIP2ERR_INS(28)[1:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

181Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transm it APS and Rem o te Indicatio n—R/W

0x20114 VT_TAPSRIVAL1 VT_APS_INS(1)[3:0] VT_ERDI_INS(1)[2:0] VT_RDI_INS1 VT_RFI_INS1

0x20115 VT_TAPSRIVAL2 VT_APS_INS(2)[3:0] VT_ERDI_INS(2)[2:0] VT_RDI_INS2 VT_RFI_INS2

0x20116 VT_TAPSRIVAL3 VT_APS_INS(3)[3:0] VT_ERDI_INS(3)[2:0] VT_RDI_INS3 VT_RFI_INS3

0x20117 VT_TAPSRIVAL4 VT_APS_INS(4)[3:0] VT_ERDI_INS(4)[2:0] VT_RDI_INS4 VT_RFI_INS4

0x20118 VT_TAPSRIVAL5 VT_APS_INS(5)[3:0] VT_ERDI_INS(5)[2:0] VT_RDI_INS5 VT_RFI_INS5

0x20119 VT_TAPSRIVAL6 VT_APS_INS(6)[3:0] VT_ERDI_INS(6)[2:0] VT_RDI_INS6 VT_RFI_INS6

0x2011A VT_TAPSRIVAL7 VT_APS_INS(7)[3:0] VT_ERDI_INS(7)[2:0] VT_RDI_INS7 VT_RFI_INS7

0x2011B VT_TAPSRIVAL8 VT_APS_INS(8)[3:0] VT_ERDI_INS(8)[2:0] VT_RDI_INS8 VT_RFI_INS8

0x2011C VT_TAPSRIVAL9 VT_APS_INS(9)[3:0] VT_ERDI_INS(9)[2:0] VT_RDI_INS9 VT_RFI_INS9

0x2011D VT_TAPSRIVAL10 VT_APS_INS(10)[3:0] VT_ERDI_INS(10)[2:0] VT_RDI_INS10 VT_RFI_INS10

0x2011E VT_TAPSRIVAL11 VT_APS_INS(11)[3:0] VT_ERDI_INS(11)[2:0] VT_RDI_INS11 VT_RFI_INS11

0x2011F VT_TAPSRIVAL12 VT_APS_INS(12)[3:0] VT_ERDI_INS(12)[2:0] VT_RDI_INS12 VT_RFI_INS12

0x20120 VT_TAPSRIVAL13 VT_APS_INS(13)[3:0] VT_ERDI_INS(13)[2:0] VT_RDI_INS13 VT_RFI_INS13

0x20121 VT_TAPSRIVAL14 VT_APS_INS(14)[3:0] VT_ERDI_INS(14)[2:0] VT_RDI_INS14 VT_RFI_INS14

0x20122 VT_TAPSRIVAL15 VT_APS_INS(15)[3:0] VT_ERDI_INS(15)[2:0] VT_RDI_INS15 VT_RFI_INS15

0x20123 VT_TAPSRIVAL16 VT_APS_INS(16)[3:0] VT_ERDI_INS(16)[2:0] VT_RDI_INS16 VT_RFI_INS16

0x20124 VT_TAPSRIVAL17 VT_APS_INS(17)[3:0] VT_ERDI_INS(17)[2:0] VT_RDI_INS17 VT_RFI_INS17

0x20125 VT_TAPSRIVAL18 VT_APS_INS(18)[3:0] VT_ERDI_INS(18)[2:0] VT_RDI_INS18 VT_RFI_INS18

0x20126 VT_TAPSRIVAL19 VT_APS_INS(19)[3:0] VT_ERDI_INS(19)[2:0] VT_RDI_INS19 VT_RFI_INS19

0x20127 VT_TAPSRIVAL20 VT_APS_INS(20)[3:0] VT_ERDI_INS(20)[2:0] VT_RDI_INS20 VT_RFI_INS20

0x20128 VT_TAPSRIVAL21 VT_APS_INS(21)[3:0] VT_ERDI_INS(21)[2:0] VT_RDI_INS21 VT_RFI_INS21

0x20129 VT_TAPSRIVAL22 VT_APS_INS(22)[3:0] VT_ERDI_INS(22)[2:0] VT_RDI_INS22 VT_RFI_INS22

0x2012A VT_TAPSRIVAL23 VT_APS_INS(23)[3:0] VT_ERDI_INS(23)[2:0] VT_RDI_INS23 VT_RFI_INS23

0x2012B VT_TAPSRIVAL24 VT_APS_INS(24)[3:0] VT_ERDI_INS(24)[2:0] VT_RDI_INS24 VT_RFI_INS24

0x2012C VT_TAPSRIVAL25 VT_APS_INS(25)[3:0] VT_ERDI_INS(25)[2:0] VT_RDI_INS25 VT_RFI_INS25

0x2012D VT_TAPSRIVAL26 VT_APS_INS(26)[3:0] VT_ERDI_INS(26)[2:0] VT_RDI_INS26 VT_RFI_INS26

0x2012E VT_TAPSRIVAL27 VT_APS_INS(27)[3:0] VT_ERDI_INS(27)[2:0] VT_RDI_INS27 VT_RFI_INS27

0x2012F VT_TAPSRIVAL28 VT_APS_INS(28)[3:0] VT_ERDI_INS(28)[2:0] VT_RDI_INS28 VT_RFI_INS28

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

182 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Tr ansmit Software O verwrite Parameters—R/W

0x20130 VT_TSWOW1 VT_OBIT_INS(1)[7:0] VT_Z6BYTE_INS(1)[7:0]

0x20131 VT_TSWOW2 VT_OBIT_INS(2)[7:0] VT_Z6BYTE_INS(2)[7:0]

0x20132 VT_TSWOW3 VT_OBIT_INS(3)[7:0] VT_Z6BYTE_INS(3)[7:0]

0x20133 VT_TSWOW4 VT_OBIT_INS(4)[7:0] VT_Z6BYTE_INS(4)[7:0]

0x20134 VT_TSWOW5 VT_OBIT_INS(5)[7:0] VT_Z6BYTE_INS(5)[7:0]

0x20135 VT_TSWOW6 VT_OBIT_INS(6)[7:0] VT_Z6BYTE_INS(6)[7:0]

0x20136 VT_TSWOW7 VT_OBIT_INS(7)[7:0] VT_Z6BYTE_INS(7)[7:0]

0x20137 VT_TSWOW8 VT_OBIT_INS(8)[7:0] VT_Z6BYTE_INS(8)[7:0]

0x20138 VT_TSWOW9 VT_OBIT_INS(9)[7:0] VT_Z6BYTE_INS(9)[7:0]

0x20139 VT_TSWOW10 VT_OBIT_INS(10)[7:0] VT_Z6BYTE_INS(10)[7:0]

0x2013A VT_TSWOW11 VT_OBIT_INS(11)[7:0] VT_Z6BYTE_INS(11)[7:0]

0x2013B VT_TSWOW12 VT_OBIT_INS(12)[7:0] VT_Z6BYTE_INS(12)[7:0]

0x2013C VT_TSWOW13 VT_OBIT_INS(13)[7:0] VT_Z6BYTE_INS(13)[7:0]

0x2013D VT_TSWOW14 VT_OBIT_INS(14)[7:0] VT_Z6BYTE_INS(14)[7:0]

0x2013E VT_TSWOW15 VT_OBIT_INS(15)[7:0] VT_Z6BYTE_INS(15)[7:0]

0x2013F VT_TSWOW16 VT_OBIT_INS(16)[7:0] VT_Z6BYTE_INS(16)[7:0]

0x20140 VT_TSWOW17 VT_OBIT_INS(17)[7:0] VT_Z6BYTE_INS(17)[7:0]

0x20141 VT_TSWOW18 VT_OBIT_INS(18)[7:0] VT_Z6BYTE_INS(18)[7:0]

0x20142 VT_TSWOW19 VT_OBIT_INS(19)[7:0] VT_Z6BYTE_INS(19)[7:0]

0x20143 VT_TSWOW20 VT_OBIT_INS(20)[7:0] VT_Z6BYTE_INS(20)[7:0]

0x20144 VT_TSWOW21 VT_OBIT_INS(21)[7:0] VT_Z6BYTE_INS(21)[7:0]

0x20145 VT_TSWOW22 VT_OBIT_INS(22)[7:0] VT_Z6BYTE_INS(22)[7:0]

0x20146 VT_TSWOW23 VT_OBIT_INS(23)[7:0] VT_Z6BYTE_INS(23)[7:0]

0x20147 VT_TSWOW24 VT_OBIT_INS(24)[7:0] VT_Z6BYTE_INS(24)[7:0]

0x20148 VT_TSWOW25 VT_OBIT_INS(25)[7:0] VT_Z6BYTE_INS(25)[7:0]

0x20149 VT_TSWOW26 VT_OBIT_INS(26)[7:0] VT_Z6BYTE_INS(26)[7:0]

0x2014A VT_TSWOW27 VT_OBIT_INS(27)[7:0] VT_Z6BYTE_INS(27)[7:0]

0x2014B VT_TSWOW28 VT_OBIT_INS(28)[7:0] VT_Z6BYTE_INS(28)[7:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

183Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Tr ansmit Signaling Control Parameters—R/W

0x2014C VT_TSIG_CTL1 VT_USE_FBIT1 VT_USE_PBIT1 VT_USE_SBIT1 VT_TXSIG_CH_SEL(1)[4:0]

0x2014D VT_TSIG_CTL2 VT_USE_FBIT2 VT_USE_PBIT2 VT_USE_SBIT2 VT_TXSIG_CH_SEL(2)[4:0]

0x2014E VT_TSIG_CTL3 VT_USE_FBIT3 VT_USE_PBIT3 VT_USE_SBIT3 VT_TXSIG_CH_SEL(3)[4:0]

0x2014F VT_TSIG_CTL4 VT_USE_FBIT4 VT_USE_PBIT4 VT_USE_SBIT4 VT_TXSIG_CH_SEL(4)[4:0]

0x20150 VT_TSIG_CTL5 VT_USE_FBIT5 VT_USE_PBIT5 VT_USE_SBIT5 VT_TXSIG_CH_SEL(5)[4:0]

0x20151 VT_TSIG_CTL6 VT_USE_FBIT6 VT_USE_PBIT6 VT_USE_SBIT6 VT_TXSIG_CH_SEL(6)[4:0]

0x20152 VT_TSIG_CTL7 VT_USE_FBIT7 VT_USE_PBIT7 VT_USE_SBIT7 VT_TXSIG_CH_SEL(7)[4:0]

0x20153 VT_TSIG_CTL8 VT_USE_FBIT8 VT_USE_PBIT8 VT_USE_SBIT8 VT_TXSIG_CH_SEL(8)[4:0]

0x20154 VT_TSIG_CTL9 VT_USE_FBIT9 VT_USE_PBIT9 VT_USE_SBIT9 VT_TXSIG_CH_SEL(9)[4:0]

0x20155 VT_TSIG_CTL10 VT_USE_FBIT10 VT_USE_PBIT10 VT_USE_SBIT10 VT_TXSIG_CH_SEL(10)[4:0]

0x20156 VT_TSIG_CTL11 VT_USE_FBIT11 VT_USE_PBIT11 VT_USE_SBIT11 VT_TXSIG_CH_SEL(11)[4:0]

0x20157 VT_TSIG_CTL12 VT_USE_FBIT12 VT_USE_PBIT12 VT_USE_SBIT12 VT_TXSIG_CH_SEL(12)[4:0]

0x20158 VT_TSIG_CTL13 VT_USE_FBIT13 VT_USE_PBIT13 VT_USE_SBIT13 VT_TXSIG_CH_SEL(13)[4:0]

0x20159 VT_TSIG_CTL14 VT_USE_FBIT14 VT_USE_PBIT14 VT_USE_SBIT14 VT_TXSIG_CH_SEL(14)[4:0]

0x2015A VT_TSIG_CTL15 VT_USE_FBIT15 VT_USE_PBIT15 VT_USE_SBIT15 VT_TXSIG_CH_SEL(15)[4:0]

0x2015B VT_TSIG_CTL16 VT_USE_FBIT16 VT_USE_PBIT16 VT_USE_SBIT16 VT_TXSIG_CH_SEL(16)[4:0]

0x2015C VT_TSIG_CTL17 VT_USE_FBIT17 VT_USE_PBIT17 VT_USE_SBIT17 VT_TXSIG_CH_SEL(17)[4:0]

0x2015D VT_TSIG_CTL18 VT_USE_FBIT18 VT_USE_PBIT18 VT_USE_SBIT18 VT_TXSIG_CH_SEL(18)[4:0]

0x2015E VT_TSIG_CTL19 VT_USE_FBIT19 VT_USE_PBIT19 VT_USE_SBIT19 VT_TXSIG_CH_SEL(19)[4:0]

0x2015F VT_TSIG_CTL20 VT_USE_FBIT20 VT_USE_PBIT20 VT_USE_SBIT20 VT_TXSIG_CH_SEL(20)[4:0]

0x20160 VT_TSIG_CTL21 VT_USE_FBIT21 VT_USE_PBIT21 VT_USE_SBIT21 VT_TXSIG_CH_SEL(21)[4:0]

0x20161 VT_TSIG_CTL22 VT_USE_FBIT22 VT_USE_PBIT22 VT_USE_SBIT22 VT_TXSIG_CH_SEL(22)[4:0]

0x20162 VT_TSIG_CTL23 VT_USE_FBIT23 VT_USE_PBIT23 VT_USE_SBIT23 VT_TXSIG_CH_SEL(23)[4:0]

0x20163 VT_TSIG_CTL24 VT_USE_FBIT24 VT_USE_PBIT24 VT_USE_SBIT24 VT_TXSIG_CH_SEL(24)[4:0]

0x20164 VT_TSIG_CTL25 VT_USE_FBIT25 VT_USE_PBIT25 VT_USE_SBIT25 VT_TXSIG_CH_SEL(25)[4:0]

0x20165 VT_TSIG_CTL26 VT_USE_FBIT26 VT_USE_PBIT26 VT_USE_SBIT26 VT_TXSIG_CH_SEL(26)[4:0]

0x20166 VT_TSIG_CTL27 VT_USE_FBIT27 VT_USE_PBIT27 VT_USE_SBIT27 VT_TXSIG_CH_SEL(27)[4:0]

0x20167 VT_TSIG_CTL28 VT_USE_FBIT28 VT_USE_PBIT28 VT_USE_SBIT28 VT_TXSIG_CH_SEL(28)[4:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

184 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Channel 1 Tr ansmi t J2 Val ue P a rameters—R/W

0x20168

—

0x20177

VT_J2BYTE_INS_R[1][1]

—

VT_J2BYTE_INS_R[1][16]

VT_J2BYTE_INS(1)(1)[7:0]

—

VT_J2BYTE_INS(1)(16)[7:0]

Channel 2 Tr ansmi t J2 Val ue P a rameters—R/W

0x20178

—

0x20187

VT_J2BYTE_INS_R[2][1]

—

VT_J2BYTE_INS_R[2][16]

VT_J2BYTE_INS(2)(1)[7:0]

—

VT_J2BYTE_INS(2)(16)[7:0]

Channel 3 Tr ansmi t J2 Val ue P a rameters—R/W

0x20188

—

0x20197

VT_J2BYTE_INS_R[3][1]

—

VT_J2BYTE_INS_R[3][16]

VT_J2BYTE_INS(3)(1)[7:0]

—

VT_J2BYTE_INS(3)(16)[7:0]

Channel 4 Tr ansmi t J2 Val ue P a rameters—R/W

0x20198

—

0x201A7

VT_J2BYTE_INS_R[4][1]

—

VT_J2BYTE_INS_R[4][16]

VT_J2BYTE_INS(4)(1)[7:0]

—

VT_J2BYTE_INS(4)(16)[7:0]

Channel 5 Tr ansmi t J2 Val ue P a rameters—R/W

0x201A8

—

0x201B7

VT_J2BYTE_INS_R[5][1]

—

VT_J2BYTE_INS_R[5][16]

VT_J2BYTE_INS(5)(1)[7:0]

—

VT_J2BYTE_INS(5)(16)[7:0]

Channel 6 Tr ansmi t J2 Val ue P a rameters—R/W

0x201B8

—

0x201C7

VT_J2BYTE_INS_R[6][1]

—

VT_J2BYTE_INS_R[6][16]

VT_J2BYTE_INS(6)(1)[7:0]

—

VT_J2BYTE_INS(6)(16)[7:0]

Channel 7 Tr ansmi t J2 Val ue P a rameters—R/W

0x201C8

—

0x201D7

VT_J2BYTE_INS_R[7][1]

—

VT_J2BYTE_INS_R[7][16]

VT_J2BYTE_INS(7)(1)[7:0]

—

VT_J2BYTE_INS(7)(16)[7:0]

Channel 8 Tr ansmi t J2 Val ue P a rameters—R/W

0x201D8

—

0x201E7

VT_J2BYTE_INS_R[8][1]

—

VT_J2BYTE_INS_R[8][16]

VT_J2BYTE_INS(8)(1)[7:0]

—

VT_J2BYTE_INS(8)(16)[7:0]

Channel 9 Tr ansmi t J2 Val ue P a rameters—R/W

0x201E8

—

0x201F7

VT_J2BYTE_INS_R[9][1]

—

VT_J2BYTE_INS_R[9][16]

VT_J2BYTE_INS(9)(1)[7:0]

—

VT_J2BYTE_INS(9)(16)[7:0]

Channel 10 Transmit J2 Value Parameters—R/W

0x201F8

—

0x20207

VT_J2BYTE_INS_R[10][1]

—

VT_J2BYTE_INS_R[10][16]

VT_J2BYTE_INS(10)(1)[7:0]

—

VT_J2BYTE_INS(10)(16)[7:0]

Channel 11 Transmit J2 Value Parameters—R/W

0x20208

—

0x20217

VT_J2BYTE_INS_R[11][1]

—

VT_J2BYTE_INS_R[11][16]

VT_J2BYTE_INS(11)(1)[7:0]

—

VT_J2BYTE_INS(11)(16)[7:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

185Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Channel 12 Transmit J2 Value Parameters—R/W

0x20218

—

0x20227

VT_J2BYTE_INS_R[12][1]

—

VT_J2BYTE_INS_R[12][16]

VT_J2BYTE_INS(12)(1)[7:0]

—

VT_J2BYTE_INS(12)(16)[7:0]

Channel 13 Transmit J2 Value Parameters—R/W

0x20228

—

0x20237

VT_J2BYTE_INS_R[13][1]

—

VT_J2BYTE_INS_R[13][16]

VT_J2BYTE_INS(13)(1)[7:0]

—

VT_J2BYTE_INS(13)(16)[7:0]

Channel 14 Transmit J2 Value Parameters—R/W

0x20238

—

0x20247

VT_J2BYTE_INS_R[14][1]

—

VT_J2BYTE_INS_R[14][16]

VT_J2BYTE_INS(14)(1)[7:0]

—

VT_J2BYTE_INS(14)(16)[7:0]

Channel 15 Transmit J2 Value Parameters—R/W

0x20248

—

0x20257

VT_J2BYTE_INS_R[15][1]

—

VT_J2BYTE_INS_R[15][16]

VT_J2BYTE_INS(15)(1)[7:0]

—

VT_J2BYTE_INS(15)(16)[7:0]

Channel 16 Transmit J2 Value Parameters—R/W

0x20258

—

0x20267

VT_J2BYTE_INS_R[16][1]

—

VT_J2BYTE_INS_R[16][16]

VT_J2BYTE_INS(16)(1)[7:0]

—

VT_J2BYTE_INS(16)(16)[7:0]

Channel 17 Transmit J2 Value Parameters—R/W

0x20268

—

0x20277

VT_J2BYTE_INS_R[17][1]

—

VT_J2BYTE_INS_R[17][16]

VT_J2BYTE_INS(17)(1)[7:0]

—

VT_J2BYTE_INS(17)(16)[7:0]

Channel 18 Transmit J2 Value Parameters—R/W

0x20278

—

0x20287

VT_J2BYTE_INS_R[18][1]

—

VT_J2BYTE_INS_R[18][16]

VT_J2BYTE_INS(18)(1)[7:0]

—

VT_J2BYTE_INS(18)(16)[7:0]

Channel 19 Transmit J2 Value Parameters—R/W

0x20288

—

0x20297

VT_J2BYTE_INS_R[19][1]

—

VT_J2BYTE_INS_R[19][16]

VT_J2BYTE_INS(19)(1)[7:0]

—

VT_J2BYTE_INS(19)(16)[7:0]

Channel 20 Transmit J2 Value Parameters—R/W

0x20298

—

0x202A7

VT_J2BYTE_INS_R[20][1]

—

VT_J2BYTE_INS_R[20][16]

VT_J2BYTE_INS(20)(1)[7:0]

—

VT_J2BYTE_INS(20)(16)[7:0]

Channel 21 Transmit J2 Value Parameters—R/W

0x202A8

—

0x202B7

VT_J2BYTE_INS_R[21][1]

—

VT_J2BYTE_INS_R[21][16]

VT_J2BYTE_INS(21)(1)[7:0]

—

VT_J2BYTE_INS(21)(16)[7:0]

Channel 22 Transmit J2 Value Parameters—R/W

0x202B8

—

0x202C7

VT_J2BYTE_INS_R[22][1]

—

VT_J2BYTE_INS_R[22][16]

VT_J2BYTE_INS(22)(1)[7:0]

—

VT_J2BYTE_INS(22)(16)[7:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

186 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Channel 23 Transmit J2 Value Parameters—R/W

0x202C8

—

0x202D7

VT_J2BYTE_INS_R[23][1]

—

VT_J2BYTE_INS_R[23][16]

VT_J2BYTE_INS(23)(1)[7:0]

—

VT_J2BYTE_INS(23)(16)[7:0]

Channel 24 Transmit J2 Value Parameters—R/W

0x202D8

—

0x202E7

VT_J2BYTE_INS_R[24][1]

—

VT_J2BYTE_INS_R[24][16]

VT_J2BYTE_INS(24)(1)[7:0]

—

VT_J2BYTE_INS(24)(16)[7:0]

Channel 25 Transmit J2 Value Parameters—R/W

0x202E8

—

0x202F7

VT_J2BYTE_INS_R[25][1]

—

VT_J2BYTE_INS_R[25][16]

VT_J2BYTE_INS(25)(1)[7:0]

—

VT_J2BYTE_INS(25)(16)[7:0]

Channel 26 Transmit J2 Value Parameters—R/W

0x202F8

—

0x20307

VT_J2BYTE_INS_R[26][1]

—

VT_J2BYTE_INS_R[26][16]

VT_J2BYTE_INS(26)(1)[7:0]

—

VT_J2BYTE_INS(26)(16)[7:0]

Channel 27 Transmit J2 Value Parameters—R/W

0x20308

—

0x20317

VT_J2BYTE_INS_R[27][1]

—

VT_J2BYTE_INS_R[27][16]

VT_J2BYTE_INS(27)(1)[7:0]

—

VT_J2BYTE_INS(27)(16)[7:0]

Channel 28 Transmit J2 Value Parameters—R/W

0x20318

—

0x20327

VT_J2BYTE_INS[28][1]

—

VT_J2BYTE_INS[28][16]

VT_J2BYTE_INS(28)(1)[7:0]

—

VT_J2BYTE_INS(28)(16)[7:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

187Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive Control Parameters—R/W

0x20328 VT_RCTL1 VT_SF_ESF1 VT_WR_FBIT1 VT_SYNC_PBIT1 VT_RXSIG_CH_SEL(1)[4:0] VT_J2MON_MODE(1)[2:0] VT_RX_ERDI_EN1 VT_RX_MAPTYPE(1)[3:0]

0x20329 VT_RCTL2 VT_SF_ESF2 VT_WR_FBIT2 VT_SYNC_PBIT2 VT_RXSIG_CH_SEL(2)[4:0] VT_J2MON_MODE(2)[2:0] VT_RX_ERDI_EN2 VT_RX_MAPTYPE(2)[3:0]

0x2032A VT_RCTL3 VT_SF_ESF3 VT_WR_FBIT3 VT_SYNC_PBIT3 VT_RXSIG_CH_SEL(3)[4:0] VT_J2MON_MODE(3)[2:0] VT_RX_ERDI_EN3 VT_RX_MAPTYPE(3)[3:0]

0x2032B VT_RCTL4 VT_SF_ESF4 VT_WR_FBIT4 VT_SYNC_PBIT4 VT_RXSIG_CH_SEL(4)[4:0] VT_J2MON_MODE(4)[2:0] VT_RX_ERDI_EN4 VT_RX_MAPTYPE(4)[3:0]

0x2032C VT_RCTL5 VT_SF_ESF5 VT_WR_FBIT5 VT_SYNC_PBIT5 VT_RXSIG_CH_SEL(5)[4:0] VT_J2MON_MODE(5)[2:0] VT_RX_ERDI_EN5 VT_RX_MAPTYPE(5)[3:0]

0x2032D VT_RCTL6 VT_SF_ESF6 VT_WR_FBIT6 VT_SYNC_PBIT6 VT_RXSIG_CH_SEL(6)[4:0] VT_J2MON_MODE(6)[2:0] VT_RX_ERDI_EN6 VT_RX_MAPTYPE(6)[3:0]

0x2032E VT_RCTL7 VT_SF_ESF7 VT_WR_FBIT7 VT_SYNC_PBIT7 VT_RXSIG_CH_SEL(7)[4:0] VT_J2MON_MODE(7)[2:0] VT_RX_ERDI_EN7 VT_RX_MAPTYPE(7)[3:0]

0x2032F VT_RCTL8 VT_SF_ESF8 VT_WR_FBIT8 VT_SYNC_PBIT8 VT_RXSIG_CH_SEL(8)[4:0] VT_J2MON_MODE(8)[2:0] VT_RX_ERDI_EN8 VT_RX_MAPTYPE(8)[3:0]

0x20330 VT_RCTL9 VT_SF_ESF9 VT_WR_FBIT9 VT_SYNC_PBIT9 VT_RXSIG_CH_SEL(9)[4:0] VT_J2MON_MODE(9)[2:0] VT_RX_ERDI_EN9 VT_RX_MAPTYPE(9)[3:0]

0x20331 VT_RCTL10 VT_SF_ESF10 VT_WR_FBIT10 VT_SYNC_PBIT10 VT_RXSIG_CH_SEL(10)[4:0] VT_J2MON_MODE(10)[2:0] VT_RX_ERDI_EN10 VT_RX_MAPTYPE(10)[3:0]

0x20332 VT_RCTL11 VT_SF_ESF11 VT_WR_FBIT11 VT_SYNC_PBIT11 VT_RXSIG_CH_SEL(11)[4:0] VT_J2MON_MODE(11)[2:0] VT_RX_ERDI_EN11 VT_RX_MAPTYPE(11)[3:0]

0x20333 VT_RCTL12 VT_SF_ESF12 VT_WR_FBIT12 VT_SYNC_PBIT12 VT_RXSIG_CH_SEL(12)[4:0] VT_J2MON_MODE(12)[2:0] VT_RX_ERDI_EN12 VT_RX_MAPTYPE(12)[3:0]

0x20334 VT_RCTL13 VT_SF_ESF13 VT_WR_FBIT13 VT_SYNC_PBIT13 VT_RXSIG_CH_SEL(13)[4:0] VT_J2MON_MODE(13)[2:0] VT_RX_ERDI_EN13 VT_RX_MAPTYPE(13)[3:0]

0x20335 VT_RCTL14 VT_SF_ESF14 VT_WR_FBIT14 VT_SYNC_PBIT14 VT_RXSIG_CH_SEL(14)[4:0] VT_J2MON_MODE(14)[2:0] VT_RX_ERDI_EN14 VT_RX_MAPTYPE(14)[3:0]

0x20336 VT_RCTL15 VT_SF_ESF15 VT_WR_FBIT15 VT_SYNC_PBIT15 VT_RXSIG_CH_SEL(15)[4:0] VT_J2MON_MODE(15)[2:0] VT_RX_ERDI_EN15 VT_RX_MAPTYPE(15)[3:0]

0x20337 VT_RCTL16 VT_SF_ESF16 VT_WR_FBIT16 VT_SYNC_PBIT16 VT_RXSIG_CH_SEL(16)[4:0] VT_J2MON_MODE(16)[2:0] VT_RX_ERDI_EN16 VT_RX_MAPTYPE(16)[3:0]

0x20338 VT_RCTL17 VT_SF_ESF17 VT_WR_FBIT17 VT_SYNC_PBIT17 VT_RXSIG_CH_SEL(17)[4:0] VT_J2MON_MODE(17)[2:0] VT_RX_ERDI_EN17 VT_RX_MAPTYPE(17)[3:0]

0x20339 VT_RCTL18 VT_SF_ESF18 VT_WR_FBIT18 VT_SYNC_PBIT18 VT_RXSIG_CH_SEL(18)[4:0] VT_J2MON_MODE(18)[2:0] VT_RX_ERDI_EN18 VT_RX_MAPTYPE(18)[3:0]

0x2033A VT_RCTL19 VT_SF_ESF19 VT_WR_FBIT19 VT_SYNC_PBIT19 VT_RXSIG_CH_SEL(19)[4:0] VT_J2MON_MODE(19)[2:0] VT_RX_ERDI_EN19 VT_RX_MAPTYPE(19)[3:0]

0x2033B VT_RCTL20 VT_SF_ESF20 VT_WR_FBIT20 VT_SYNC_PBIT20 VT_RXSIG_CH_SEL(20)[4:0] VT_J2MON_MODE(20)[2:0] VT_RX_ERDI_EN20 VT_RX_MAPTYPE(20)[3:0]

0x2033C VT_RCTL21 VT_SF_ESF21 VT_WR_FBIT21 VT_SYNC_PBIT21 VT_RXSIG_CH_SEL(21)[4:0] VT_J2MON_MODE(21)[2:0] VT_RX_ERDI_EN21 VT_RX_MAPTYPE(21)[3:0]

0x2033D VT_RCTL22 VT_SF_ESF22 VT_WR_FBIT22 VT_SYNC_PBIT22 VT_RXSIG_CH_SEL(22)[4:0] VT_J2MON_MODE(22)[2:0] VT_RX_ERDI_EN22 VT_RX_MAPTYPE(22)[3:0]

0x2033E VT_RCTL23 VT_SF_ESF23 VT_WR_FBIT23 VT_SYNC_PBIT23 VT_RXSIG_CH_SEL(23)[4:0] VT_J2MON_MODE(23)[2:0] VT_RX_ERDI_EN23 VT_RX_MAPTYPE(23)[3:0]

0x2033F VT_RCTL24 VT_SF_ESF24 VT_WR_FBIT24 VT_SYNC_PBIT24 VT_RXSIG_CH_SEL(24)[4:0] VT_J2MON_MODE(24)[2:0] VT_RX_ERDI_EN24 VT_RX_MAPTYPE(24)[3:0]

0x20340 VT_RCTL25 VT_SF_ESF25 VT_WR_FBIT25 VT_SYNC_PBIT25 VT_RXSIG_CH_SEL(25)[4:0] VT_J2MON_MODE(25)[2:0] VT_RX_ERDI_EN25 VT_RX_MAPTYPE(25)[3:0]

0x20341 VT_RCTL26 VT_SF_ESF26 VT_WR_FBIT26 VT_SYNC_PBIT26 VT_RXSIG_CH_SEL(26)[4:0] VT_J2MON_MODE(26)[2:0] VT_RX_ERDI_EN26 VT_RX_MAPTYPE(26)[3:0]

0x20342 VT_RCTL27 VT_SF_ESF27 VT_WR_FBIT27 VT_SYNC_PBIT27 VT_RXSIG_CH_SEL(27)[4:0] VT_J2MON_MODE(27)[2:0] VT_RX_ERDI_EN27 VT_RX_MAPTYPE(27)[3:0]

0x20343 VT_RCTL28 VT_SF_ESF28 VT_WR_FBIT28 VT_SYNC_PBIT28 VT_RXSIG_CH_SEL(28)[4:0] VT_J2MON_MODE(28)[2:0] VT_RX_ERDI_EN28 VT_RX_MAPTYPE(28)[3:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

188 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive TU Overhead—RO

0x20344 VT_RTUOH_CTL1 VT_Z6_BYTE(1)[7:0] VT_OBITS(1)[7:0]

0x20345 VT_RTUOH_CTL2 VT_Z6_BYTE(2)[7:0] VT_OBITS(2)[7:0]

0x20346 VT_RTUOH_CTL3 VT_Z6_BYTE(3)[7:0] VT_OBITS(3)[7:0]

0x20347 VT_RTUOH_CTL4 VT_Z6_BYTE(4)[7:0] VT_OBITS(4)[7:0]

0x20348 VT_RTUOH_CTL5 VT_Z6_BYTE(5)[7:0] VT_OBITS(5)[7:0]

0x20349 VT_RTUOH_CTL6 VT_Z6_BYTE(6)[7:0] VT_OBITS(6)[7:0]

0x2034A VT_RTUOH_CTL7 VT_Z6_BYTE(7)[7:0] VT_OBITS(7)[7:0]

0x2034B VT_RTUOH_CTL8 VT_Z6_BYTE(8)[7:0] VT_OBITS(8)[7:0]

0x2034C VT_RTUOH_CTL9 VT_Z6_BYTE(9)[7:0] VT_OBITS(9)[7:0]

0x2034D VT_RTUOH_CTL10 VT_Z6_BYTE(10)[7:0] VT_OBITS(10)[7:0]

0x2034E VT_RTUOH_CTL11 VT_Z6_BYTE(11)[7:0] VT_OBITS(11)[7:0]

0x2034F VT_RTUOH_CTL12 VT_Z6_BYTE(12)[7:0] VT_OBITS(12)[7:0]

0x20350 VT_RTUOH_CTL13 VT_Z6_BYTE(13)[7:0] VT_OBITS(13)[7:0]

0x20351 VT_RTUOH_CTL14 VT_Z6_BYTE(14)[7:0] VT_OBITS(14)[7:0]

0x20352 VT_RTUOH_CTL15 VT_Z6_BYTE(15)[7:0] VT_OBITS(15)[7:0]

0x20353 VT_RTUOH_CTL16 VT_Z6_BYTE(16)[7:0] VT_OBITS(16)[7:0]

0x20354 VT_RTUOH_CTL17 VT_Z6_BYTE(17)[7:0] VT_OBITS(17)[7:0]

0x20355 VT_RTUOH_CTL18 VT_Z6_BYTE(18)[7:0] VT_OBITS(18)[7:0]

0x20356 VT_RTUOH_CTL19 VT_Z6_BYTE(19)[7:0] VT_OBITS(19)[7:0]

0x20357 VT_RTUOH_CTL20 VT_Z6_BYTE(20)[7:0] VT_OBITS(20)[7:0]

0x20358 VT_RTUOH_CTL21 VT_Z6_BYTE(21)[7:0] VT_OBITS(21)[7:0]

0x20359 VT_RTUOH_CTL22 VT_Z6_BYTE(22)[7:0] VT_OBITS(22)[7:0]

0x2035A VT_RTUOH_CTL23 VT_Z6_BYTE(23)[7:0] VT_OBITS(23)[7:0]

0x2035B VT_RTUOH_CTL24 VT_Z6_BYTE(24)[7:0] VT_OBITS(24)[7:0]

0x2035C VT_RTUOH_CTL25 VT_Z6_BYTE(25)[7:0] VT_OBITS(25)[7:0]

0x2035D VT_RTUOH_CTL26 VT_Z6_BYTE(26)[7:0] VT_OBITS(26)[7:0]

0x2035E VT_RTUOH_CTL27 VT_Z6_BYTE(27)[7:0] VT_OBITS(27)[7:0]

0x2035F VT_RTUOH_CTL28 VT_Z6_BYTE(28)[7:0] VT_OBITS(28)[7:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

189Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receiv e BIP-2 Error Count Values—RO

0x20360 VT_RBIP2_CNT1 VT_BIP2ERR_CNT(1)[11:0]

0x20361 VT_RBIP2_CNT2 VT_BIP2ERR_CNT(2)[11:0]

0x20362 VT_RBIP2_CNT3 VT_BIP2ERR_CNT(3)[11:0]

0x20363 VT_RBIP2_CNT4 VT_BIP2ERR_CNT(4)[11:0]

0x20364 VT_RBIP2_CNT5 VT_BIP2ERR_CNT(5)[11:0]

0x20365 VT_RBIP2_CNT6 VT_BIP2ERR_CNT(6)[11:0]

0x20366 VT_RBIP2_CNT7 VT_BIP2ERR_CNT(7)[11:0]

0x20367 VT_RBIP2_CNT8 VT_BIP2ERR_CNT(8)[11:0]

0x20368 VT_RBIP2_CNT9 VT_BIP2ERR_CNT(9)[11:0]

0x20369 VT_RBIP2_CNT10 VT_BIP2ERR_CNT(10)[11:0]

0x2036A VT_RBIP2_CNT11 VT_BIP2ERR_CNT(11)[11:0]

0x2036B VT_RBIP2_CNT12 VT_BIP2ERR_CNT(12)[11:0]

0x2036C VT_RBIP2_CNT13 VT_BIP2ERR_CNT(13)[11:0]

0x2036D VT_RBIP2_CNT14 VT_BIP2ERR_CNT(14)[11:0]

0x2036E VT_RBIP2_CNT15 VT_BIP2ERR_CNT(15)[11:0]

0x2036F VT_RBIP2_CNT16 VT_BIP2ERR_CNT(16)[11:0]

0x20370 VT_RBIP2_CNT17 VT_BIP2ERR_CNT(17)[11:0]

0x20371 VT_RBIP2_CNT18 VT_BIP2ERR_CNT(18)[11:0]

0x20372 VT_RBIP2_CNT19 VT_BIP2ERR_CNT(19)[11:0]

0x20373 VT_RBIP2_CNT20 VT_BIP2ERR_CNT(20)[11:0]

0x20374 VT_RBIP2_CNT21 VT_BIP2ERR_CNT(21)[11:0]

0x20375 VT_RBIP2_CNT22 VT_BIP2ERR_CNT(22)[11:0]

0x20376 VT_RBIP2_CNT23 VT_BIP2ERR_CNT(23)[11:0]

0x20377 VT_RBIP2_CNT24 VT_BIP2ERR_CNT(24)[11:0]

0x20378 VT_RBIP2_CNT25 VT_BIP2ERR_CNT(25)[11:0]

0x20379 VT_RBIP2_CNT26 VT_BIP2ERR_CNT(26)[11:0]

0x2037A VT_RBIP2_CNT27 VT_BIP2ERR_CNT(27)[11:0]

0x2037B VT_RBIP2_CNT28 VT_BIP2ERR_CNT(28)[11:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

190 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive REI-V Count Values—RO

0x2037C VT_RREIV_CNT1 VT_REI_CNT(1)[10:0]

0x2037D VT_RREIV_CNT2 VT_REI_CNT(2)[10:0]

0x2037E VT_RREIV_CNT3 VT_REI_CNT(3)[10:0]

0x2037F VT_RREIV_CNT4 VT_REI_CNT(4)[10:0]

0x20380 VT_RREIV_CNT5 VT_REI_CNT(5)[10:0]

0x20381 VT_RREIV_CNT6 VT_REI_CNT(6)[10:0]

0x20382 VT_RREIV_CNT7 VT_REI_CNT(7)[10:0]

0x20383 VT_RREIV_CNT8 VT_REI_CNT(8)[10:0]

0x20384 VT_RREIV_CNT9 VT_REI_CNT(9)[10:0]

0x20385 VT_RREIV_CNT10 VT_REI_CNT(10)[10:0]

0x20386 VT_RREIV_CNT11 VT_REI_CNT(11)[10:0]

0x20387 VT_RREIV_CNT12 VT_REI_CNT(12)[10:0]

0x20388 VT_RREIV_CNT13 VT_REI_CNT(13)[10:0]

0x20389 VT_RREIV_CNT14 VT_REI_CNT(14)[10:0]

0x2038A VT_RREIV_CNT15 VT_REI_CNT(15)[10:0]

0x2038B VT_RREIV_CNT16 VT_REI_CNT(16)[10:0]

0x2038C VT_RREIV_CNT17 VT_REI_CNT(17)[10:0]

0x2038D VT_RREIV_CNT18 VT_REI_CNT(18)[10:0]

0x2038E VT_RREIV_CNT19 VT_REI_CNT(19)[10:0]

0x2038F VT_RREIV_CNT20 VT_REI_CNT(20)[10:0]

0x20390 VT_RREIV_CNT21 VT_REI_CNT(21)[10:0]

0x20391 VT_RREIV_CNT22 VT_REI_CNT(22)[10:0]

0x20392 VT_RREIV_CNT23 VT_REI_CNT(23)[10:0]

0x20393 VT_RREIV_CNT24 VT_REI_CNT(24)[10:0]

0x20394 VT_RREIV_CNT25 VT_REI_CNT(25)[10:0]

0x20395 VT_RREIV_CNT26 VT_REI_CNT(26)[10:0]

0x20396 VT_RREIV_CNT27 VT_REI_CNT(27)[10:0]

0x20397 VT_RREIV_CNT28 VT_REI_CNT(28)[10:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

191Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive VT Pointer and Count Values—RO

0x20398 VT_RPTR_CNT1 VT_STORED_VTPTR(1)[7:0] VT_PTR_DEC(1)[3:0] VT_PTR_INC(1)[3:0]

0x20399 VT_RPTR_CNT2 VT_STORED_VTPTR(2)[7:0] VT_PTR_DEC(2)[3:0] VT_PTR_INC(2)[3:0]

0x2039A VT_RPTR_CNT3 VT_STORED_VTPTR(3)[7:0] VT_PTR_DEC(3)[3:0] VT_PTR_INC(3)[3:0]

0x2039B VT_RPTR_CNT4 VT_STORED_VTPTR(4)[7:0] VT_PTR_DEC(4)[3:0] VT_PTR_INC(4)[3:0]

0x2039C VT_RPTR_CNT5 VT_STORED_VTPTR(5)[7:0] VT_PTR_DEC(5)[3:0] VT_PTR_INC(5)[3:0]

0x2039D VT_RPTR_CNT6 VT_STORED_VTPTR(6)[7:0] VT_PTR_DEC(6)[3:0] VT_PTR_INC(6)[3:0]

0x2039E VT_RPTR_CNT7 VT_STORED_VTPTR(7)[7:0] VT_PTR_DEC(7)[3:0] VT_PTR_INC(7)[3:0]

0x2039F VT_RPTR_CNT8 VT_STORED_VTPTR(8)[7:0] VT_PTR_DEC(8)[3:0] VT_PTR_INC(8)[3:0]

0x203A0 VT_RPTR_CNT9 VT_STORED_VTPTR(9)[7:0] VT_PTR_DEC(9)[3:0] VT_PTR_INC(9)[3:0]

0x203A1 VT_RPTR_CNT10 VT_STORED_VTPTR(10)[7:0] VT_PTR_DEC(10)[3:0] VT_PTR_INC(10)[3:0]

0x203A2 VT_RPTR_CNT11 VT_STORED_VTPTR(11)[7:0] VT_PTR_DEC(11)[3:0] VT_PTR_INC(11)[3:0]

0x203A3 VT_RPTR_CNT12 VT_STORED_VTPTR(12)[7:0] VT_PTR_DEC(12)[3:0] VT_PTR_INC(12)[3:0]

0x203A4 VT_RPTR_CNT13 VT_STORED_VTPTR(13)[7:0] VT_PTR_DEC(13)[3:0] VT_PTR_INC(13)[3:0]

0x203A5 VT_RPTR_CNT14 VT_STORED_VTPTR(14)[7:0] VT_PTR_DEC(14)[3:0] VT_PTR_INC(14)[3:0]

0x203A6 VT_RPTR_CNT15 VT_STORED_VTPTR(15)[7:0] VT_PTR_DEC(15)[3:0] VT_PTR_INC(15)[3:0]

0x203A7 VT_RPTR_CNT16 VT_STORED_VTPTR(16)[7:0] VT_PTR_DEC(16)[3:0] VT_PTR_INC(16)[3:0]

0x203A8 VT_RPTR_CNT17 VT_STORED_VTPTR(17)[7:0] VT_PTR_DEC(17)[3:0] VT_PTR_INC(17)[3:0]

0x203A9 VT_RPTR_CNT18 VT_STORED_VTPTR(18)[7:0] VT_PTR_DEC(18)[3:0] VT_PTR_INC(18)[3:0]

0x203AA VT_RPTR_CNT19 VT_STORED_VTPTR(19)[7:0] VT_PTR_DEC(19)[3:0] VT_PTR_INC(19)[3:0]

0x203AB VT_RPTR_CNT20 VT_STORED_VTPTR(20)[7:0] VT_PTR_DEC(20)[3:0] VT_PTR_INC(20)[3:0]

0x203AC VT_RPTR_CNT21 VT_STORED_VTPTR(21)[7:0] VT_PTR_DEC(21)[3:0] VT_PTR_INC(21)[3:0]

0x203AD VT_RPTR_CNT22 VT_STORED_VTPTR(22)[7:0] VT_PTR_DEC(22)[3:0] VT_PTR_INC(22)[3:0]

0x203AE VT_RPTR_CNT23 VT_STORED_VTPTR(23)[7:0] VT_PTR_DEC(23)[3:0] VT_PTR_INC(23)[3:0]

0x203AF VT_RPTR_CNT24 VT_STORED_VTPTR(24)[7:0] VT_PTR_DEC(24)[3:0] VT_PTR_INC(24)[3:0]

0x203B0 VT_RPTR_CNT25 VT_STORED_VTPTR(25)[7:0] VT_PTR_DEC(25)[3:0] VT_PTR_INC(25)[3:0]

0x203B1 VT_RPTR_CNT26 VT_STORED_VTPTR(26)[7:0] VT_PTR_DEC(26)[3:0] VT_PTR_INC(26)[3:0]

0x203B2 VT_RPTR_CNT27 VT_STORED_VTPTR(27)[7:0] VT_PTR_DEC(27)[3:0] VT_PTR_INC(27)[3:0]

0x203B3 VT_RPTR_CNT28 VT_STORED_VTPTR(28)[7:0] VT_PTR_DEC(28)[3:0] VT_PTR_INC(28)[3:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

192 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Channel 1 Receive J2 Expected/Monitor Values—R/W, RO

0x203B4

—

0x203C3

VT_J2BYTE_EXP_R[1][1]

—

VT_J2BYTE_EXP_R[1][16]

VT_J2BYTE_EXP(1)(1)[7:0]

—

VT_J2BYTE_EXP(1)(16)[7:0]

VT_J2BYTE_DET(1)(1)[7:0]

—

VT_J2BYTE_DET(1)(16)[7:0]

Channel 2 Receive J2 Expected/Monitor Values—R/W, RO

0x203C4

—

0x203D3

VT_J2BYTE_EXP_R[2][1]

—

VT_J2BYTE_EXP_R[2][16]

VT_J2BYTE_EXP(2)(1)[7:0]

—

VT_J2BYTE_EXP(2)(16)[7:0]

VT_J2BYTE_DET(2)(1)[7:0]

—

VT_J2BYTE_DET(2)(16)[7:0]

Channel 3 Receive J2 Expected/Monitor Values—R/W, RO

0x203D4

—

0x203E3

VT_J2BYTE_EXP_R[3][1]

—

VT_J2BYTE_EXP_R[3][16]

VT_J2BYTE_EXP(3)(1)[7:0]

—

VT_J2BYTE_EXP(3)(16)[7:0]

VT_J2BYTE_DET(3)(1)[7:0]

—

VT_J2BYTE_DET(3)(16)[7:0]

Channel 4 Receive J2 Expected/Monitor Values—R/W, RO

0x203E4

—

0x203F3

VT_J2BYTE_EXP_R[4][1]

—

VT_J2BYTE_EXP_R[4][16]

VT_J2BYTE_EXP(4)(1)[7:0]

—

VT_J2BYTE_EXP(4)(16)[7:0]

VT_J2BYTE_DET(4)(1)[7:0]

—

VT_J2BYTE_DET(4)(16)[7:0]

Channel 5 Receive J2 Expected/Monitor Values—R/W, RO

0x203F4

—

0x20403

VT_J2BYTE_EXP_R[5][1]

—

VT_J2BYTE_EXP_R[5][16]

VT_J2BYTE_EXP(5)(1)[7:0]

—

VT_J2BYTE_EXP(5)(16)[7:0]

VT_J2BYTE_DET(5)(1)[7:0]

—

VT_J2BYTE_DET(5)(16)[7:0]

Channel 6 Receive J2 Expected/Monitor Values—R/W, RO

0x20404

—

0x20413

VT_J2BYTE_EXP_R[6][1]

—

VT_J2BYTE_EXP_R[6][16]

VT_J2BYTE_EXP(6)(1)[7:0]

—

VT_J2BYTE_EXP(6)(16)[7:0]

VT_J2BYTE_DET(6)(1)[7:0]

—

VT_J2BYTE_DET(6)(16)[7:0]

Channel 7 Receive J2 Expected/Monitor Values—R/W, RO

0x20414

—

0x20423

VT_J2BYTE_EXP_R[7][1]

—

VT_J2BYTE_EXP_R[7][16]

VT_J2BYTE_EXP(7)(1)[7:0]

—

VT_J2BYTE_EXP(7)(16)[7:0]

VT_J2BYTE_DET(7)(1)[7:0]

—

VT_J2BYTE_DET(7)(16)[7:0]

Channel 8 Receive J2 Expected/Monitor Values—R/W, RO

0x20424

—

0x20433

VT_J2BYTE_EXP_R[8][1]

—

VT_J2BYTE_EXP_R[8][16]

VT_J2BYTE_EXP(8)(1)[7:0]

—

VT_J2BYTE_EXP(8)(16)[7:0]

VT_J2BYTE_DET(8)(1)[7:0]

—

VT_J2BYTE_DET(8)(16)[7:0]

Channel 9 Receive J2 Expected/Monitor Values—R/W, RO

0x20434

—

0x20443

VT_J2BYTE_EXP_R[9][1]

—

VT_J2BYTE_EXP_R[9][16]

VT_J2BYTE_EXP(9)(1)[7:0]

—

VT_J2BYTE_EXP(9)(16)[7:0]

VT_J2BYTE_DET(9)(1)[7:0]

—

VT_J2BYTE_DET(9)(16)[7:0]

Channel 10 Receive J2 Expected/Monitor Values—R/W, RO

0x20444

—

0x20453

VT_J2BYTE_EXP_R[10][1]

—

VT_J2BYTE_EXP_R[10][16]

VT_J2BYTE_EXP(10)(1)[7:0]

—

VT_J2BYTE_EXP(10)(16)[7:0]

VT_J2BYTE_DET(10)(1)[7:0]

—

VT_J2BYTE_DET(10)(16)[7:0]

Channel 11 Receive J2 Expected/Monitor Values—R/W, RO

0x20454

—

0x20463

VT_J2BYTE_EXP_R[11][1]

—

VT_J2BYTE_EXP_R[11][16]

VT_J2BYTE_EXP(11)(1)[7:0]

—

VT_J2BYTE_EXP(11)(16)[7:0]

VT_J2BYTE_DET(11)(1)[7:0]

—

VT_J2BYTE_DET(11)(16)[7:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

193Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Channel 12 Receive J2 Expected/Monitor Values—R/W, RO

0x20464

—

0x20473

VT_J2BYTE_EXP_R[12][1]

—

VT_J2BYTE_EXP_R[12][16]

VT_J2BYTE_EXP(12)(1)[7:0]

—

VT_J2BYTE_EXP(12)(16)[7:0]

VT_J2BYTE_DET(12)(1)[7:0]

—

VT_J2BYTE_DET(12)(16)[7:0]

Channel 13 Receive J2 Expected/Monitor Values—R/W, RO

0x20474

—

0x20483

VT_J2BYTE_EXP_R[13][1]

—

VT_J2BYTE_EXP_R[13][16]

VT_J2BYTE_EXP(13)(1)[7:0]

—

VT_J2BYTE_EXP(13)(16)[7:0]

VT_J2BYTE_DET(13)(1)[7:0]

—

VT_J2BYTE_DET(13)(16)[7:0]

Channel 14 Receive J2 Expected/Monitor Values—R/W, RO

0x20484

—

0x20493

VT_J2BYTE_EXP_R[14][1]

—

VT_J2BYTE_EXP_R[14][16]

VT_J2BYTE_EXP(14)(1)[7:0]

—

VT_J2BYTE_EXP(14)(16)[7:0]

VT_J2BYTE_DET(14)(1)[7:0]

—

VT_J2BYTE_DET()14(16)[7:0]

Channel 15 Receive J2 Expected/Monitor Values—R/W, RO

0x20494

—

0x204A3

VT_J2BYTE_EXP_R[15][1]

—

VT_J2BYTE_EXP_R[15][16]

VT_J2BYTE_EXP(15)(1)[7:0]

—

VT_J2BYTE_EXP(15)(16)[7:0]

VT_J2BYTE_DET(15)(1)[7:0]

—

VT_J2BYTE_DET(15)(16)[7:0]

Channel 16 Receive J2 Expected/Monitor Values—R/W, RO

0x204A4

—

0x204B3

VT_J2BYTE_EXP_R[16][1]

—

VT_J2BYTE_EXP_R[16][16]

VT_J2BYTE_EXP(16)(1)[7:0]

—

VT_J2BYTE_EXP(16)(16)[7:0]

VT_J2BYTE_DET(16)(1)[7:0]

—

VT_J2BYTE_DET(16)(16)[7:0]

Channel 17 Receive J2 Expected/Monitor Values—R/W, RO

0x204B4

—

0x204C3

VT_J2BYTE_EXP_R[17][1]

—

VT_J2BYTE_EXP_R[17][16]

VT_J2BYTE_EXP(17)(1)[7:0]

—

VT_J2BYTE_EXP(17)(16)[7:0]

VT_J2BYTE_DET(17)(1)[7:0]

—

VT_J2BYTE_DET(17)(16)[7:0]

Channel 18 Receive J2 Expected/Monitor Values—R/W, RO

0x204C4

—

0x204D3

VT_J2BYTE_EXP_R[18][1]

—

VT_J2BYTE_EXP_R[18][16]

VT_J2BYTE_EXP(18)(1)[7:0]

—

VT_J2BYTE_EXP(18)(16)[7:0]

VT_J2BYTE_DET(18)(1)[7:0]

—

VT_J2BYTE_DET(18)(16)[7:0]

Channel 19 Receive J2 Expected/Monitor Values—R/W, RO

0x204D4

—

0x204E3

VT_J2BYTE_EXP_R[19][1]

—

VT_J2BYTE_EXP_R[19][16]

VT_J2BYTE_EXP(19)(1)[7:0]

—

VT_J2BYTE_EXP(19)(16)[7:0]

VT_J2BYTE_DET(19)(1)[7:0]

—

VT_J2BYTE_DET(19)(16)[7:0]

Channel 20 Receive J2 Expected/Monitor Values—R/W, RO

0x204E4

—

0x204F3

VT_J2BYTE_EXP_R[20][1]

—

VT_J2BYTE_EXP_R[20][16]

VT_J2BYTE_EXP(20)(1)[7:0]

—

VT_J2BYTE_EXP(20)(16)[7:0]

VT_J2BYTE_DET(20)(1)[7:0]

—

VT_J2BYTE_DET(20)(16)[7:0]

Channel 21 Receive J2 Expected/Monitor Values—R/W, RO

0x204F4

—

0x20503

VT_J2BYTE_EXP_R[21][1]

—

VT_J2BYTE_EXP_R[21][16]

VT_J2BYTE_EXP(21)(1)[7:0]

—

VT_J2BYTE_EXP(21)(16)[7:0]

VT_J2BYTE_DET(21)(1)[7:0]

—

VT_J2BYTE_DET(21)(16)[7:0]

Channel 22 Receive J2 Expected/Monitor Values—R/W, RO

0x20504

—

0x20513

VT_J2BYTE_EXP_R[22][1]

—

VT_J2BYTE_EXP_R[22][16]

VT_J2BYTE_EXP(22)(1)[7:0]

—

VT_J2BYTE_EXP(22)(16)[7:0]

VT_J2BYTE_DET(22)(1)[7:0]

—

VT_J2BYTE_DET(22)(16)[7:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

194 A

ere S

stems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Channel 23 Receive J2 Expected/Monitor Values—R/W, RO

0x20514

—

0x20523

VT_J2BYTE_EXP_R[23][1]

—

VT_J2BYTE_EXP_R[23][16]

VT_J2BYTE_EXP(23)(1)[7:0]

—

VT_J2BYTE_EXP(23)(16)[7:0]

VT_J2BYTE_DET(23)(1)[7:0]

—

VT_J2BYTE_DET(23)(16)[7:0]

Channel 24 Receive J2 Expected/Monitor Values—R/W, RO

0x20524

—

0x20533

VT_J2BYTE_EXP_R[24][1]

—

VT_J2BYTE_EXP_R[24][16]

VT_J2BYTE_EXP(24)(1)[7:0]

—

VT_J2BYTE_EXP(24)(16)[7:0]

VT_J2BYTE_DET(24)(1)[7:0]

—

VT_J2BYTE_DET(24)(16)[7:0]

Channel 25 Receive J2 Expected/Monitor Values—R/W, RO

0x20534

—

0x20543

VT_J2BYTE_EXP_R[25][1]

—

VT_J2BYTE_EXP_R[25][16]

VT_J2BYTE_EXP(25)(1)[7:0]

—

VT_J2BYTE_EXP(25)(16)[7:0]

VT_J2BYTE_DET(25)(1)[7:0]

—

VT_J2BYTE_DET(25)(16)[7:0]

Channel 26 Receive J2 Expected/Monitor Values—R/W, RO

0x20544

—

0x20553

VT_J2BYTE_EXP_R[26][1]

—

VT_J2BYTE_EXP_R[26][16]

VT_J2BYTE_EXP(26)(1)[7:0]

—

VT_J2BYTE_EXP(26)(16)[7:0]

VT_J2BYTE_DET(26)(1)[7:0]

—

VT_J2BYTE_DET(26)(16)[7:0]

Channel 27 Receive J2 Expected/Monitor Values—R/W, RO

0x20554

—

0x20563

VT_J2BYTE_EXP_R[27][1]

—

VT_J2BYTE_EXP_R[27][16]

VT_J2BYTE_EXP(27)(1)[7:0]

—

VT_J2BYTE_EXP(27)(16)[7:0]

VT_J2BYTE_DET(27)(1)[7:0]

—

VT_J2BYTE_DET(27)(16)[7:0]

Channel 28 Receive J2 Expected/Monitor Values—R/W, RO

0x20564

—

0x20573

VT_J2BYTE_EXP_R[28][1]

—

VT_J2BYTE_EXP_R[28][16]

VT_J2BYTE_EXP(28)(1)[7:0]

—

VT_J2BYTE_EXP(28)(16)[7:0]

VT_J2BYTE_DET(28)(1)[7:0]

—

VT_J2BYTE_DET(28)(16)[7:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

195Agere Sy stem s Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT/TU Mapper Register M ap (continued)

Note: Registers from 0x20590 to 0x20969 are reserved and should not be read.

Addre ss Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Elastic St ore Thre shold C o ntrol—R/W

0x20574 VT_THRES_CTL1 VT_HIGH_THRES(1)[6:0] VT_LOW_THRES(1)[6:0]

0x20575 VT_THRES_CTL2 VT_HIGH_THRES(2)[6:0] VT_LOW_THRES(2)[6:0]

0x20576 VT_THRES_CTL3 VT_HIGH_THRES(3)[6:0] VT_LOW_THRES(3)[6:0]

0x20577 VT_THRES_CTL4 VT_HIGH_THRES(4)[6:0] VT_LOW_THRES(4)[6:0]

0x20578 VT_THRES_CTL5 VT_HIGH_THRES(5)[6:0] VT_LOW_THRES(5)[6:0]

0x20579 VT_THRES_CTL6 VT_HIGH_THRES(6)[6:0] VT_LOW_THRES(6)[6:0]

0x2057A VT_THRES_CTL7 VT_HIGH_THRES(7)[6:0] VT_LOW_THRES(7)[6:0]

0x2057B VT_THRES_CTL8 VT_HIGH_THRES(8)[6:0] VT_LOW_THRES(8)[6:0]

0x2057C VT_THRES_CTL9 VT_HIGH_THRES(9)[6:0] VT_LOW_THRES(9)[6:0]

0x2057D VT_THRES_CTL10 VT_HIGH_THRES(10)[6:0] VT_LOW_THRES(10)[6:0]

0x2057E VT_THRES_CTL11 VT_HIGH_THRES(11)[6:0] VT_LOW_THRES(11)[6:0]

0x2057F VT_THRES_CTL12 VT_HIGH_THRES(12)[6:0] VT_LOW_THRES(12)[6:0]

0x20580 VT_THRES_CTL13 VT_HIGH_THRES(13)[6:0] VT_LOW_THRES(13)[6:0]

0x20581 VT_THRES_CTL14 VT_HIGH_THRES(14)[6:0] VT_LOW_THRES(14)[6:0]

0x20582 VT_THRES_CTL15 VT_HIGH_THRES(15)[6:0] VT_LOW_THRES(15)[6:0]

0x20583 VT_THRES_CTL16 VT_HIGH_THRES(16)[6:0] VT_LOW_THRES(16)[6:0]

0x20584 VT_THRES_CTL17 VT_HIGH_THRES(17)[6:0] VT_LOW_THRES(17)[6:0]

0x20585 VT_THRES_CTL18 VT_HIGH_THRES(18)[6:0] VT_LOW_THRES(18)[6:0]

0x20586 VT_THRES_CTL19 VT_HIGH_THRES(19)[6:0] VT_LOW_THRES(19)[6:0]

0x20587 VT_THRES_CTL20 VT_HIGH_THRES(20)[6:0] VT_LOW_THRES(20)[6:0]

0x20588 VT_THRES_CTL21 VT_HIGH_THRES(21)[6:0] VT_LOW_THRES(21)[6:0]

0x20589 VT_THRES_CTL22 VT_HIGH_THRES(22)[6:0] VT_LOW_THRES(22)[6:0]

0x2058A VT_THRES_CTL23 VT_HIGH_THRES(23)[6:0] VT_LOW_THRES(23)[6:0]

0x2058B VT_THRES_CTL24 VT_HIGH_THRES(24)[6:0] VT_LOW_THRES(24)[6:0]

0x2058C VT_THRES_CTL25 VT_HIGH_THRES(25)[6:0] VT_LOW_THRES(25)[6:0]

0x2058D VT_THRES_CTL26 VT_HIGH_THRES(26)[6:0] VT_LOW_THRES(26)[6:0]

0x2058E VT_THRES_CTL27 VT_HIGH_THRES(27)[6:0] VT_LOW_THRES(27)[6:0]

0x2058F VT_THRES_CTL28 VT_HIGH_THRES(28)[6:0] VT_LOW_THRES(28)[6:0]

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
196 Agere Sy stem s Inc.
 
11 M13/M23 MUX/DeMUX Registers
Ta ble of Conte nts
Contents Page
11 M13/M23 MU X/DeMUX Registers .................................................................................................................. 196
11.1  M 13 Block Register Descriptions ............................................................................................................ 198
11.2  M13 Registe r Map .................................................................................................................................. 228
Tables Page
Table 212. M 13_ID_R, M 13 Block Ident ification (RO) ...................... . ......................... ..... .............. . ..................... 198
Table 213. M13_VERSION_R, M13 Version (RO) .............................................................................................. 198
Table 214. M 13_DELTA1, Delta (RO) ............. ....... . ......................... .......... ... ......................... . ............................ 199
Table 215. M13_DELTA2, Delta (RO)..................... ....... ............................................. ............ ....... .....................  200
Table 216. M13_DELTA3, Delta (RO)..................... ....... ............................................. ............ ....... .....................  200
Table 217. M 13_DELTA4, Delta (RO) ............. ....... . ......................... .......... ... ......................... . ............................ 201
Table 218. M 13_DELTA5, Delta (RO) ............. ....... . ......................... .......... ... ......................... . ............................ 202
Table 219.  M 13_M A SK1, Mask (R/W)  ............. .................. ........................ ................ . ................ ........................ 202
Table 220.  M 13_M A SK2, Mask (R/W)  ............. .................. ........................ ................ . ................ ........................ 203
Table 221.  M 13_M A SK3, Mask (R/W)  ............. .................. ........................ ................ . ................ ........................ 203
Table 222.  M 13_M A SK4, Mask (R/W)  ............. .................. ........................ ................ . ................ ........................ 204
Table 223.  M 13_M A SK5, Mask (R/W)  ............. .................. ........................ ................ . ................ ........................ 205
Table 224. M 13_DS3_STAT U S1, Status (RO)  .................. ........................ ............................ ..... ... ..................... 205
Table 225. M 13_DS3_STAT U S2, Status (RO)  .................. ........................ ............................ ..... ... ..................... 206
Table 2 26.   M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delt a (RO) . ............................................... ................. 206
Table 2 27. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO) ................ .......... 206
Table 2 28. M13_DS2_OOFD_R, DS 2 Out  of Frame Delta (RO) ........................ ..... ... ........................................ 207
Table 229.  M 13_DS2_LOFD_ R, DS 2 L oss of Fr ame Delta (RO) ................. ............. ................... ................... ... 207
Table 230.  M 13_DS2_A I S_DE TD_R, DS2 Alarm Indication Signal Detect Delta (RO) ..................... ................. 2 07
Table 2 31.  M13_DS2_RAI_DETD_ R, DS2 Remote Alarm Indication Detection De lta (RO)  ............. .................207
Table 232.  M 13_DS 2_L B_ DETD_R,  DS 2 Loopback Dete ct Delta (RO) .. ................ ................... ................... ..... 208
Table 233. M 13_DS 2_RS V_RCV D_R, DS2  Receive Reserved Bit Delta (RO) ......... .................................... ..... 208
Table 2 34.  M13_DS2DMX_LOCD_R, DS2 DeMUX Loss o f Clock Delta (RO) ........... . ........... . ...... . ........... . ........ 20 8
Table 2 35. M13_DS 1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO)  ......... .............. ... .. .. ... .. ... .. .. ... . 208
Table 2 36. M13_DS 1_AIS_DE TD_R[1—4 ], DS1 Alar m Ind ication Signal  Delta Regi sters (RO) ........................ 209
Table 2 37. M13_DS 1_LB_DETD _R[ 1—4], DS1 Loopback Detect Delta Registers (RO) ...... . .............. .............. 209
Table 238.  M 13__X C_DS2_LOC_R, DS2 Loss of Clock  Status (RO) ....... .............. ................... ........................ 2 09
Table 239.  M 13_XC_DS 2_A IS _DE T_R, DS2 Alarm  Indication Signal Detect St atus (RO) .......... ................... ... 209
Table 240.  M 13_DS 2_O OF_R, DS2 Out of  Fram e Status (RO ) ........... ............................... .......................... .....210
Table 241.  M 13_DS 2_L OF_R, DS 2 L oss of F rame  Status (RO) ........................ . .................. .......................... ...210
Table 242.  M 13_DS2_A I S_DE T_R, DS 2 Alarm Indication  Signal Detect St atus (RO) .......... ................... .......... 210
Table 2 43. M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Stat us (RO) ................... ................. 210
Table 244.  M 13_DS2_LB_DET_R, DS 2 Loopback Dete ct Status (RO)  ....... ........... ........................................ ... 211
Table 2 45. M13_DS 2_RSV_RCV_R, DS2 Recei ve Reserved Bit Delta Status (RO) ............ . .................. . ......... 211
Table 2 46.  M13_DS2DMX_LO C_R, DS2 DeMUX Loss of Clock S tatus (RO)  ........ .......................... ................. 211
Table 247. M 13_DS1_LOC_R[1—4], DS1  Loss of Clock Status Registers (RO) ............................................... 211
Table 248. M 13_DS1_AIS_DET_R[1—4], DS1 Alarm Indication Signal Detect Status Registers (RO) ............. 212
Table 2 49. M13_DS 1_LB_DET_R[ 1—4], DS1 Loopback Detect Status Registers (RO) .............. ...................... 2 12
Table 2 50. M13_DS 1_FEAC_LB _DETD_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Delta 
Registers (RO) ................................................................................................................................... 213
Table 2 51. M13_DS 1_FEAC_LB_DET_R[1—4], DS1 Far-End Alarm and Control Loopback Detect 
Statu s Registers (RO ) ....................................................................................................................... 213
Table 2 52. M13_RFEAC_C ODE_R, Receive Far-En d Alarm and Cont rol Co de Stat us  (RO) .... ........................ 214

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
197Agere Systems Inc.  
11 M13/M23 MUX/DeMUX Registers (continued)
Table o f Conten ts (continued)
Tables Page
Table 253. M13_RDL_STATUS, Receive  Data-Link Status (RO) .......................................................................214
Table 254. M13_RDL_DATA_R, Receive  Data-Link Data (RO) .........................................................................214
Table 2 55. M13_RDL_FRAME_SIZE_R, Receive Data-L ink Frame Size (RO) ..................................................214
Table 256. M13_RHDL C_STATUS_R, Receive High-Level Data-Link Control Status (RO) .............................. 215
Table 2 57. M13_DS2_FORCE_OOF_R, DS2 Force Out of  Frame (O ne Sh ot R/W) ............ ... .................. ..... .... 215
Table 2 58. M13_CONTRO L1, Con trol 1 (One Shot R/ W) ........................... ... ......................... .......... ..................215
Table 259.  M 13_CO NTROL2, Con trol 2 (R/W ) ............. .................. ................... ................... .............................. 215
Table 260.  M 13_CO NTROL3, Con trol 3 (R/W )  .... ................... ...................... .................. ................... ................ 216
Tab le 261. M13_SP_OFFSET_R, Sync Pulse Offset (R/W) ............................................................................... 216
Table 262. M13_SP_D_OFFSET_ R, Sync Pulse D Offset (R/W) ....................................................................... 216
Table 263. M 13_M12_MUX _CONTRO L1_R[1—7], M12 MUX CONTROL 1 Registers [1—7] (R/W) ................ 2 17
Table 264. M 13_M12_MUX _CONTRO L2_R[1—7], M12 MUX CONTROL 2 Registers [1—7] (R/W) ................ 2 17
Table 2 65. M13_DS 2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W ) ................. ..... ..... .................. 217
Table 2 66.  M13_DS2_RS V_SEND_R,  DS2 Reserve Bit Send (R/W) . ........................................ . ............. ......... 217
Table 2 67.  M13_DS2_MPINV_R , DS2 M  Frame Alignm ent   or Parity  Error (R/W) ............... ..................... . ........ 218
Table 2 68.   M13_DS2_F INV_R, DS2 Frame Error (R/W) ..................... ................... ..................... . ............. . ........ 218
Table 269. M 13_DS 2_P _BE R_R,  Parity  Bit Error Rate (R/W) .. .............................. .............. ............... ...............218
Table 2 70. M13_DS 2M12_EDG E_R, DS2 M12 Edge (R/W) ........................................... ..... .......................... .... 218
Table 2 71. M13_DS 2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W) .............. ..................... . ........ 218
Table 272. M 13_M12_DEM UX_CONTROL1_R[1—7], M12 DeM U X Control 1 Registers  [1—7] ( R /W)  ............219
Table 273. M 13_M12_DEM UX_CONTROL2_R[1—7], M12 DeM U X Control 2 Registers  [1—7] ( R /W)  ............219
Table 2 74. M13_M12_DEMUX_CONTROL3, DS 2 M12 DeMUX  Control 3 (R/W)  ............... ... ....................... .... 219
Table 2 75.  M13_DMD S 2_EDGE_R, DS2  Edge f or M12 DeMUX (R/W) ................. ................ . ................... ........ 220
Table 2 76. M13_DS 3_CONTRO L1, DS3 Control 1 (R/W) ........................................ ..... .......................... ........... 220
Table 2 77. M13_DS 3_CONTRO L2, DS3 Control 2 (R/W) ........................................ ..... .......................... ........... 221
Table 278.  M 13_T FEA C_CONTROL , Tx  FEA C Control (R/W) ..... ................. ................... ................... ............... 221
Table 279. M 13_THDLC_CONTRO L1,  T x HDLC Control 1 (R/W) .. ........... ............ ............................ ............... . 222
Table 280. M 13_THDLC_CONTRO L2,  T x HDLC Control 2 (R/W) .. ........... ............ ............................ ............... . 222
Table 281.  M13_DS 2_LB_REQ_R,  DS2 Loopback Reque st (R/W) ........... ................... ................... .................. 222
Table 282.  M 13_S EL_DS 2_LB _R, Se lect DS2 Loopback (R/W) ......... ..................... ................... ................... . ... 223
Table 2 83.  M13_RDS2_E DGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W) ..................................................223
Table 284.  M 13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W) . ................... ................... ................... ..................223
Table 285. M 13_DS2_OUT_AI S_R, DS 2 Out put Alarm Indication Sign al (R/W)  .................... ..... ....................... 223
Table 2 86. M13_TDS2_EDGE _R,  Tx  DS2 Edge (R/W) ........... ..... ..................... . .................. .............................. 224
Table 287. M13_RDL_CONTROL, RDL Control (R/W) ....................................................................................... 224
Table 288. M 13_P M _CNT_ ACT_R, P erforma nc e Cou nter (RO) ............ .............. ........... ................................... 224
Table 2 89.  M13_DS3_FERR_CNT _R[1—2], DS3  F-Bit Err o r Registers (RO) ....................................................224
Table 2 90. M13_DS 3_FEBE_CNT_R[1—2],  DS3 Far-End Block Error Registers  (RO) .....................................225
Table 2 91.  M13_DS3_CP ERR_CNT_R[1—2], DS3 C-Bit Parity Error Registers (RO) ...................................... 225
Table 2 92.  M13_DS3_PERR_CNT_R[ 1—2], DS3 P-Bi t Error Registers (RO) ...................................................2 25
Table 2 93.  M13_DS2_PERR_CNT[7—1]_R[1—2] , P- Bi t E rr or  C ounter Status  Registers (RO)  ...................... . .. 22 5
Table 2 94.  M13_DS2_FERR_CNT [7—1]_R, F-Bit Error Counter St atu s Registers (RO) ............. ............. . ........ 226
Table 2 95. M13_BPV_CNT_R[1—3], B ipolar Violation Counte r Status Registers (RO) ............... ...................... 226
Table 296. M 13_EXZ_CN T_R[1—3], Bipolar Violation Counter Status Registers (RO) ................... .................. 2 27
Table 297.   M 13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W) ........... ............................. ......................2 27
Table 298. M 13_TDL_0DATA_R[0—63], Tx Data for Path Maintenence Data-Link Buffer 0 Registers 
(64 Bytes x 8 Bi ts) (R/W) ................................................................................................................... 227
Table 299. M 13_TDL_1DATA_R[0—63], Tx Data for Path Maintenence Data-Link Buffer 1 Registers 
(64 Bytes x 8 Bi ts) (R/W) ................................................................................................................... 227
Table 300. Register Address Map ....................................................................................................................... 228

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

198 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

11.1 M13 Block Register Descriptions

T he followi ng tabl es desc ribe the functions o f al l bit s. For e ach add res s, the re gister bits are in dica ted a s either

read/wr ite (R/W ) or read on ly (RO), and the value of the bit s on rese t is gi ven.

Table 212. M13_ID_R, M13 Block Identification (RO)

Table 213. M13_VERSION_R, M13 Version (R O)

Address Bit Name Function Reset

Default

0x10000 15:8 —Reserved. 0x00

7:0 M 13_I D[7:0] The M13_ID_R register returns a fixed value (0x01) when read. 0x01

Address Bit Name Function Reset

Default

0x10001 15:3 —Reserved. 0x000

2:0 M13_VERSION[2:0] These bits identify the v er sion number of the M13. 0x 0

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
199Agere Systems Inc.  
11 M13/M23 MUX/DeMUX Registers (continued)
Table 214. M13_DELTA1, Delt a (RO)
Address Bit Name Function Reset
Default
0x10004 15:8 —Reserved. 0x00
7 M13_RDL_IDLED This delta b it is set if M 13_RDL_IDLE (Table 224) 
ch ange s s t ate. It can be  programm ed to b e eithe r cl ear 
on read (COR) or clear on write (COW), and it  is not  s et  
to 1 again until another state transition occurs.
0
6 M 13_DS3_LOFD T his delta b it is se t if  M 13_DS 3_LOF ( Table 224) 
ch ange s s t ate. It can be  programm ed to b e eithe r cl ear 
on read (COR) or clear on write (COW), and it  is not  s et  
to 1 again until another state transition occurs.
0
5 M13_DS3_OOFD This delta bit is set if M13_DS3_OOF (Table 224) 
ch ange s s t ate. It can be  programm ed to b e eithe r cl ear 
on read (COR) or clear on write (COW), and it  is not  s et  
to 1 again until another state transition occurs.
0
4 M13_DS 3_C1 _DE TD T his delta b it is set if M 13_DS 3_C1_DET (Table 224) 
changes state . It is cleared when read, and it is not set to 
1 again until another  state transition occu rs.
0
3 M 13_DS 3_RAI _DE TD This delta b it is set if  M 13_DS 3_RAI _DE T ( Table 224) 
ch ange s s t ate. It can be  programm ed to b e eithe r cl ear 
on read (COR) or clear on write (COW), and it  is not  s et  
to 1 again until another state transition occurs.
0
2 M13_DS3_A ISPAT_DETD This delta b it is set if M13_DS3_AI SPAT_DET 
(Table 224) changes state. It can be prog rammed  to be 
either clear on read (COR) or clear on writ e (COW), and it  
is not set to 1 again until another state transition occurs.
0
1 M13_DS 3_I DLEPAT_DE TD This delta bit is se t if M 13_DS 3_I DLE PAT_DET 
(Table 224) changes state. It can be prog rammed  to be 
either clear on read (COR) or clear on writ e (COW), and it  
is not set to 1 again until another state transition occurs.
0
0 M13_DS 3_CB Z _DE TD T his delta b it is set if M13_DS3_CBZ _DE T ( Table 224) 
ch ange s s t ate. It can be  programm ed to b e eithe r cl ear 
on read (COR) or clear on write (COW), and it  is not  s et  
to 1 again until another state transition occurs.
0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
200 Agere Sy stem s Inc.
 
11 M13/M23 MUX/DeMUX Registers (continued)
Table 215. M13_DELTA2, Delt a (RO)
Table 216. M13_DELTA3, Delt a (RO)
Address Bit Name Function Reset
Default
0x10005 15:8 —Reserved. 0x00
7 M13_DS1_LB_SD This delt a bit summarizes the state of 
M13_DS1_LB _DE T D[28:1] (Table 237) bi ts. 0
6 M13_DS1_ AIS_SD This delta bit  is set if a ny M13_DS1_AIS_DETD [28:1] 
(Table 236) bit is high . 0
5 M13_DS1_LOC_SD This delta bit is set if any M13_DS1_LOCD[28:1] 
(Table 235) bit is high . 0
4 M13_RD S3 _S EFD This delta bit i s set i f M13_RDS3_S EF (Table 225) 
changes state. I t can be programmed to be either cl ear on 
read (COR) or clear on write (COW), and it is not set   to 1 
again until another state transition occurs.
0
3 M13_RDS3_ALL1_DETD This delta bit is set if M13_RDS3_ALL1_DET (Table 225) 
changes state. I t can be programmed to be either cl ear on 
read (COR) or clear on write (COW), and it is not set   to 1 
again until another state transition occurs.
0
2 M13_R DS3 _LOSD T his delta bit i s s e t if  M1 3_RD S3_LOS  (Table 225) 
changes state. I t can be programmed to be either cl ear on 
read (COR) or clear on write (COW), and it is not set   to 1 
again until another state transition occurs.
0
1 M13_TDS3_LOCD This delta bit is set if M13_TDS3_LOC (Table 225) 
changes state. I t can be programmed to be either cl ear on 
read (COR) or clear on write (COW), and it is not set   to 1 
again until another state transition occurs.
0
0 M13_RDS3_LOCD This delta bit is set if M13_RDS3_LOC (Table 225) 
changes state. I t can be programmed to be either cl ear on 
read (COR) or clear on write (COW), and it is not set   to 1 
again until another state transition occurs.
0
Address Bit Name Function Reset
Default
0x10006 15:8 —Reserved.  0x00
7 M13_DS2_RSV_ SD This delta bit is high if any M13_DS2_RSV _RCVD[7:1] 
(Table 233) bi t is high. 0
6 M 13_DS2_LB_S D T his delta bit summarizes the state   of 
M13_DS2_LB_DETD[7:1] (Table 232). 0
5 M 13_DS2_RAI_SD This delta bi t su mm arizes the state of 
M13_ DS2_RAI_DETD[7:1] (Table 231). 0
4 M 13_DS2_AIS_SD This delta bit summarizes the state  of 
M13_DS2_AIS_D ETD[7:1] (Table 230). 0
3 M13_DS2_LOF_SD This delta bit is high i f any M13_DS2_LOFD[7:1] ( Table 229) 
bit is high. 0
2 M13_D S2_O OF_SD This  delta bit is high if any M13_DS2_OOFD[7:1] 
(Table 228) bi t is high. 0
1 M 13_XC_DS 2_AIS_SD T his  delta bit is set if any M13_XC_DS2_AIS_ D E TD[7:1] 
(Table 227) bi t is high. 0
0 M13_XC _D S2_LOC_SD This delta  bit is  set if any M 13_ XC_DS2_LO CD[7:1] 
(Table 226) bi t is high. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

201Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 217. M13_DELTA4, Delt a (RO)

Address Bit Name Function Reset

Default

0x10007 15:8 —Reserved. 0x00

7 M13_TFEAC_DONE This bit is se t when the M13 c ompletes tran smiss ion of a

sequence of FEAC con t rol code. It c an be programmed to

be either clear on read (COR) or clear on write (COW), and it

is not set to 1 again until the event reoccurs.

6 M13_TDL_DONE This b it is set when the M13 completes tran smission of a

data-link frame. It can be programmed to be either clear on

read (COR) or clear o n write (COW), and it is not s et to 1

again until the event reoccurs.

5 M13_TDL_BUF1_INT This bit is se t when the device completes transmission of

M13_TDL_1DATA63[7:0] (Table 299) (the last byte of buffer

1). It can be programmed to be either clear on read (COR) or

clear on wri te (COW), and it is not set to 1 again until the

event reo ccurs.

4 M13_TDL_BUF0_INT This bit is se t when the device completes transmission of

M13_TDL_0DATA63[7:0] (Table 298) (the last byte of buffer

0). It can be programmed to be either clear on read (COR) or

clear on wri te (COW), and it is not set to 1 again until the

event reo ccurs.

3 M13_RDL_FIFO_AFD This delta bit is set if M13_RDL_FIFO_AF (Table 225)

chang es state. It can be programmed to be either clear on

read (COR) or clear o n write (COW), and it is not s et to 1

again until another state transition occurs.

2 M13_RDL_FRM_INT This bit indicates that a new data-link frame closing f lag or

an abort byte has been received. It can be programmed to

be either clear on read (COR) or clear on write (COW), and it

is not set to 1 again until the event reoccurs.

1 M13_RFEAC_ALM_INT This bit indicates that a new DS3 FEAC alarm codeword has

been received. The new codew ord is a vailable in register

M13_RF E AC_CODE_R (Table 252). For loopbac k code-

words, the appr opriate M13_DS1_FEAC_LB_DETx

(Table 251) and M13_DS3_FLB_DET (Table 251) bits in reg-

isters 0x2F through 0x32 will be set or cleared. It can be pro-

grammed to be either clear on read (COR) or clear on wri te

(COW), and it is not set to 1 again until the event reoccur s.

0 M 13_RF E AC_LB_INT T his bit ind icates that a new DS3 FEAC loopback codeword

has been received. The new codeword is available in regis-

ter M13_RFEAC_ CODE _R. For loopback codewords, the

appropriate M13_DS1_F EAC_LB_DE Tx and

M13_DS3_FLB_DET bits will be set or cleared. It can be

programmed to be either clear on read (COR) or clear on

wr ite (COW), and it is not set to 1 again until the event reoc-

curs.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
202 Agere Sy stem s Inc.
 
11 M13/M23 MUX/DeMUX Registers (continued)
Table 218. M13_DELTA5, Delt a (RO)
Table 219. M13_MASK1, Mask (R/W)
Address Bit Name Function Reset
Default
0x10008 15:2 —Reserved. 0x0000
1 M13 _D S2D MX_LOC_SD This delt a bit is set  if any M13_DS2DMX_LOCD[7:0] 
(Table 234) bi t register is high. 0
0 M13_RD L _FIFO_UFD This delta bit is set  if bit M13_RDL_FIFO_UF (Table 225) 
changes  stat e. It can be programmed to be  either clear on  
read (COR) or c lear on write (COW), and it is no t set t o 1 
again until another state transition occurs.
0
Address Bit Name Function Reset
Default
0x1000A 15:8 —Reserved. 0x00
7 M1 3_RDL_IDLE M Setting this mas k bi t high prevents the delta 
M13_RDL_IDLE D ( Table 214) f rom causing the block 
output interrupt (INT) to be ac tive.
1
6 M1 3_DS 3_LO FM Setting th is mask bi t high prevents the delta 
M13_DS3_LOFD (Table 214) from causing the block ou t -
put INT t o be active.
1
5 M13_DS3_O OFM Setting this m ask  bi t high prevents the delta 
M13_DS3_OOFD (Table 214) from cau sing the block 
output INT to be act ive.
1
4 M13_DS3_C1_DETM Setting this mas k bi t high prevents the delta 
M13_DS3_C1_DETD (Table 214) from causing the b lock 
output INT to be act ive.
1
3 M13_DS3_ R AI_DETM Se tting this mask  bi t high prevents the delta 
M13_DS3_RA I_DETD ( Table 214) f rom causing  the 
block output INT to be active.
1
2 M 13_DS 3_AI SPAT_ DETM Setting this mask  bi t high prevents the delta 
M13_DS3_A ISPAT_DET D (Table 214) from  c aus ing the 
block output INT to be  Active.
1
1 M13_DS3_IDLE PAT_DETM Setting this mask  bi t high prevents the delta 
M13_DS3_IDLEPAT_DETD (Table 214) from causing the 
block output INT to be active.
1
0 M 13_DS3_CBZ_DE TM Setting this mas k  bi t high prevents the delta 
M13_DS3_CB Z_DET D (Table 214) from causing the 
block output INT to be active.
1

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
203Agere Systems Inc.  
11 M13/M23 MUX/DeMUX Registers (continued)
Table 220. M13_MASK2, Mask (R/W)
Address Bit Name Function Reset
Default
0x1000B 15:8 —Reserved. 0x00
7 M13_DS1_ L B_SM S e ttin g t h is ma sk  b it h ig h  p reve nts the summary delta 
M13_DS1_LB _S D ( Table 215) from causing the block out-
put inte rrupt  (INT) to be active.
1
6 M 13_DS1_ AIS_S M Set ting this mask bit high prevents the summary delta 
M13_DS1_A I S_ SD (Table 215) from causing the block out-
put IN T to be active.
1
5 M 13_DS 1_LOC_SM S etting  this mask bit high prevents the su mmary delta 
M13_DS1_LOC_SD ( Table 215) f rom causing  the block 
output INT to be active.
1
4 M1 3 _ RD S3_ SE F M Se t ti n g this ma sk  b it h ig h  p reve nts the delta 
M13_RDS3_S E FD (Table 215) from caus ing the block  out-
put IN T to be active.
1
3 M13_RDS 3_A LL1_DE T M Set ting this mask bit high prevents the delta 
M13_RDS3_A LL1_DETD (Table 215) fr om causing the 
block  output  IN T  to be active.
1
2 M1 3_RDS 3_LOSM S etting this mask bit high prevents the delta 
M13_RDS3_LOSD (Table 215) from causing t he block out-
put IN T to be active.
1
1 M13_TDS3_LOCM Setting this mask bit high prevents the delta 
M13_T DS3 _LOCD (Table 215) from ca us ing the block  out-
put IN T to be active.
1
0 M13_RDS3_LOCM Setting this mask bit high prevents the delta 
M13_RDS3_LOCD (Table 215) from causing t he block o ut-
put IN T to be active.
1
Table 221. M13_MASK3, Mask (R/W)
Address Bit Name Function Reset
Default
0x1000C 15:8 —Reserved. 0x00
7 M13 _DS2_RS V_ SM Setting this mas k  bit hi gh p revents t he sum mary delta 
M13_DS2_RS V _S D (Table 216) from causing the blo ck out-
put interr upt (I NT) to be ac tiv e.
1
6 M13_DS2_LB _S M Setting  this mas k bit high prevents t he sum mary delta 
M13_DS2_LB _S D ( Table 216) f r om causing the block out-
put INT to be activ e.
1
5 M13 _DS 2_RA I_SM S etting this m ask  bit hi gh p revents t he sum mary delta 
M13_DS2_RA I _S D (Table 216) from caus ing th e block out-
put INT to be activ e.
1
4 M13_DS2_A IS_S M Setting  this mas k bit high prevents t he sum mar y  delta 
M13_DS2_A I S_SD (Table 216) from causing the block   out -
put INT to be activ e.
1
3 M13_DS 2_LOF_SM Setting this mas k bit high prevents t he sum mary delta 
M13_DS2_LOF_SD (Table 216) from causing the block out-
put INT to be activ e.
1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
11 M13/M23 MUX/DeMUX Registers (continued)
204 Agere Sy stem s Inc.
 
0x10 00C 2 M13_DS 2_OOF _S M Setting this m ask  bit hig h prevents the sum mar y  delta 
M13_DS2_OOF_ SD (Table 216) from caus ing the block 
output INT to be activ e.
1
1 M 13_X C_DS 2_AIS_SM Setting this mas k bit  hig h p revents t he sum mar y  delta 
M13_XC_DS 2_A I S_SD (Table 216) from causing the block 
output INT to be activ e.
1
0 M13_X C_DS 2_LO C_S M Setting this mas k bit hig h prevents the sum mar y delt a 
M13_XC_DS2_LOC_SD (Table 216) from causing the block 
output INT to be activ e.
1
Table 222. M13_MASK4, Mask (R/W)
Address Bit Name Function Reset
Default
0x1000D 15:8 —Reserved. 0x00
7 M13_TFEAC_DONEM Setting this mask  bi t high prevents M13_T FEAC_DONE 
(Table 217) from causing the bloc k output interrupt (INT) to 
be active.
1
6 M13_TDL_ D ONEM Setting this mas k bit high  prevents M 13_T DL_DONE 
(Table 217) from causing the bl ock output INT to be active. 1
5 M1 3_TDL _BUF1_INTM Se tting this mask bit high  prevents M13_TDL_BUF1_INT 
(Table 217) from causing the bl ock output INT to be active. 1
4 M1 3_TDL _BUF0_INTM Se tting this mask bit high  prevents M13_TDL_BUF0_INT 
(Table 217) from causing the bl ock output INT to be active. 1
3 M13_RDL_F I FO_ AFM Se tting this mask  bi t high prevents M13_RDL _FIFO_AFD 
(Table 217) from causing the bl ock output INT to be active. 1
2 M 13_RDL_FRM_I NTM Se tting this mask bi t high prevents M13_RDL _FRM _INT 
(Table 217) from causing the bl ock output INT to be active. 1
1 M 13_RF E AC_ALM_INTM Setting this mask  bi t high prevents 
M13_RFEAC_ALM_INT (Table 217) from causing the block 
output INT to be active.
1
0 M13_RFEAC_LB_IN TM Setting this mask  bi t high prevents M13_RF E AC_LB_INT 
(Table 217) from causing the bl ock output INT to be active. 1
Table 221. M13_MASK3, Mask (R/W) (continued)
Address Bit Name Function Reset
Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

205Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 223. M13_MASK5, Mask (R/W)

Address Bit Name Function Reset

Default

0x1000E 15:2 —Reserved. 000000

000000

1 M13_DS2DMX _LOC_SM Setting this mask bit high prevents the summary delta

M13_DS2DMX_LO C_S D (Table 218) f rom causing the

bloc k output interrupt (INT) to be active.

0 M13_RDL_FIFO_UFM Setting this m ask bi t high prevents M13_RDL _FIFO_UFD

(Table 218) from causing the block output INT to be act ive. 1

Table 224. M13_DS3_STATUS1, Status (RO)

Address Bit Name Function Reset

Default

0x1000F 15:8 —Reserved. 0x00

7 M13_RDL_IDLE This bit is set if 15 c onsecutive ones are received on the

path maintenance data link. it is cleared when a flag b yte is

received.

6 M13_DS 3_LOF This bit is set if M13 _DS3_OOF is high continuously for

28 frame periods (approximately 3 ms). Once set,

M13_DS3_LOF is not cleared until M13_DS3_OOF is con-

tinuously low for 28 frame p eriods.

5 M13_DS3_OOF The DS3 framer out-of-frame state bit. (See DS3 Framer

on page 469) This bit i s high while out-of-frame. 1

4 M13_DS3_C1_DET This bit is set if t he first C bit of each DS3 frame is received

high f or 8 consecutiv e frames. Once M13_DS3_C1_DET is

set , 3 consec utive frames with C1 = 0 must be received

before it is cleared.

3 M13_DS3_RAI_DET If both X bits in 2 consecutive frames are received as 0, the

M13 sets t his bit to 1 . Once it is set , it is not cleared u nti l

both X bits in 2 consecutive frames are received as 1.

2 M13_DS3_AISPAT_DET The 4704 information bits in each M frame are checked for

the presence of the AIS (1010) pattern. A patt ern detection

bit is set if fewe r t han 5 pattern errors are received in each

of 2 co ns ec uti ve frames. Onc e a bit is set, it is not cleared

until at least 16 p attern errors are received i n e ach of

2 consecutive frames.

1 M 13_DS3_IDLEPAT_DET The 4704 inform ation bits in each M frame are checked for

the presenc e of the idle (1100) pattern. A pattern detection

bit is set if fewe r t han 5 pattern errors are received in each

of 2 co ns ec uti ve frames. Onc e a bit is set, it is not cleared

until at least 16 p attern errors are received i n e ach of

2 consecutive frames.

0 M 13_DS 3_CBZ_DET This bit is set if every C bit in 3 cons ecutive DS3 frames is

0. It is cleared if the three C bits in a single

M-subframe are all 1.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

206 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 225. M13_DS3_STATUS2, Status (RO)

Table 226. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)

Table 227. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)

Address Bit Name Function Reset

Default

0x10010 15:7 —Reserved. 000000

000

6 M13_RDL_FIFO_UF This bit is 1 if t he receiv e HDLC FIFO is underflow. 0

5 M13_RDL_FIFO_AF This bit is 1 if the number of unread bytes in the receive

HDLC FIFO is greater than t he fill-up level set by bits

M13_RDL_FILL[1:0] (Table 287).

4 M13_R DS3 _SEF This bit is 1 if there a re three or more F-bit errors in

16 consecutive F bits. It is not terminated until the signal is

in-frame and t here are less than three F-bit errors in 16 con-

secutive F bits.

3 M 13_RDS3_A LL1_DET This bit is 1 if the input data is 0 for fewer than 9 out o f

8192 clock periods. 0

2 M 13_RDS 3_LOS T his bit is 1 if t here are 175 ±75 contiguous pulse positions

with no pulses of either positive or neg ative pol arity at the

DS3 Input . An LOS is cleared upon detecting an average

pulse d ens ity of at least 33% over a per iod of

17 5 ±75 contiguous pulse positions, starti ng with the receipt

of a pulse.

1 M 13_TDS3_LO C T his bit is 1 if t he SM PR_TDS3CLK signal fail s to have tran-

sitions for at least 10 periods of SMPR_RDS3CLK. A single

transition o n SMPR_TDS 3CLK resets this bit.

0 M13_R DS 3_LOC T h is bit is 1 if the S M PR _R D S3CL K signal fa ils to have tran-

sitions for at least 10 periods of SMPR_TDS3CLK. A single

transition o n S MPR_RDS3CLK resets this bit.

Address Bit Name Function Reset

Default

0x10011 15:7 —Reserved. 0x000

6:0 M13_XC_DS2_

LOCD[7:1] These individual delta bits are set as the result o f the corre-

sponding state bits M13_XC_DS2_LOC[7:1] (Table 238) transi-

tioning either from 0 to 1 or from 1 to 0. They can be

programmed to be either clear on read (COR ) or c lear on write

(COW), and they are not set to 1 again unt il the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10012 15:7 —Reserved. 0x000

6:0 M13_XC_DS2_

AIS_DETD[7:1] These indiv idual delta bits are set as the result of the corre-

sponding state bits M13_XC_DS2_AIS_DET[7:1]

(Table 239) tran sitioning either from 0 to 1 or from 1 to 0.

They can be programme d to be either clear on read (COR)

or clear on write (COW), and they ar e not set to 1 again u ntil

the event reoccurs.

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

207Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 228. M13_DS2_OOFD_R, DS2 Out of Frame Delta (RO)

Table 229. M13_DS2_LOFD_R, DS2 Loss of Frame Delta (RO)

Table 230. M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO)

Table 231. M13_DS2_RAI_DETD_R, DS 2 Remote Alarm I ndication Detection Delta (RO)

Address Bit Name Function Reset

Default

0x10013 15:7 —Reserved. 0x000

6:0 M13_DS2_OOFD[7:1] Th ese individua l delta bits are set as the result of the corre-

sponding s tate bit s M13_DS2_OOF[7:1] (Table 240) transition-

ing either from 0 to 1 or from 1 to 0. Delta bi ts can be

programmed to be either clear on read (COR) or clear on write

(COW), and they are n ot set to 1 again until the event r eoc-

curs.

0x00

Address Bit Name Function Reset

Default

0x10014 15:7 —Reserved. 0x000

6:0 M13_DS2_LOFD[7:1] These individual delta bits are set as the result of th e corre-

spond ing s tate bits M13_DS2_LO F[7:1] (Table 241) transition-

ing either f rom 0 to 1 or fro m 1 to 0. They c an be programmed

to be either clear on read (COR) or clear on write (COW), and

they are not set to 1 again until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10015 15:7 —Reserved. 0x000

6:0 M13_DS2_AIS_

DETD[7:1] These individual delta bits are set as the result of the corre-

spond ing s tate bits M13_DS2_AI S_ D ET[7:1] (Table 242) tran-

sitioning either from 0 to 1 or from 1 to 0. Delta bits can be

prog rammed to be either clear on read (COR) or clear on write

(COW), and they are not set to 1 again until the event reoc-

curs.

0x00

Address Bit Name Function Reset

Default

0x10016 15:7 —Reserved. 0x000

6:0 M13_DS2_

RAI_DETD[7:1] These individual delta bits are set as the result of the corre-

spond ing s tate bits M13_DS2_ RAI _DET[7:1] (Table 243) tran-

sitioning either from 0 to 1 or from 1 to 0. Delta bits can be

prog rammed to be either clear on read (COR) or clear on write

(COW), and they are not set to 1 again until the event reoc-

curs.

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

208 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 232. M13_DS2_L B_DETD_R, DS2 Loo pb ack Detect Delta (RO)

Table 233. M13_DS2_RSV_RCVD_R, DS 2 Receive Reserved Bit Delta (RO)

Table 234. M13_DS2DMX _LOCD_R, DS2 DeMUX Loss of Clock Del ta (RO)

Table 235. M13_DS1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO)

Address Bit Name Function Reset

Default

0x10017 15:7 —Reserved. 0x000

6:0 M13_DS2_LB_

DETD[7:1] These individual delta bits are set as the result of the corre-

sponding state bits M13_DS2_LB_DET[7:1] ( Table 244) transi-

tioning either from 0 to 1 or from 1 to 0. Delta bits can be

prog rammed to be either clear on read (COR) or clear on write

(COW), and they are not set to 1 again until the event reoc-

curs.

0x00

Address Bit Name Function Reset

Default

0x10018 15:7 —Reserved. 0x000

6:0 M13_DS2_RSV_

RCVD[7:1] These individual delta bits are set as the resul t of the corre-

spond ing s tate bits M13_DS2_ RSV _RC V[7:1] (Table 245)

transit ioning either from 0 to 1 or from 1 to 0. Delta bits can be

prog rammed to be either clear on read (COR) or clear on write

(COW), and they are not set to 1 again until the event reoc-

curs. (G.747).

0x00

Address Bit Name Function Reset

Default

0x10019 15:7 —Reserved. 0x000

6:0 M13_DS2DMX_

LOCD[7:1] These individual delta bits are set as the result of the corre-

spond ing s tate bits M13_DS2DMX_LOC[7:1] (Table 246) tran-

sitioning either from 0 to 1 or from 1 to 0. Delta bits can be

prog rammed to be either clear on read (COR) or clear on write

(COW), and they are not set to 1 again until the event reoc-

curs.

0x00

Address Bit Name Function Reset

Default

0x1001E 15:4 —Reserved. 0x000

0x1001F—

0x10021 15:8 —Reserved. 0x00

0x1001E

0x1001F

0x10020

0x10021

3:0

7:0

M13_DS1_LOCD[28:25]

M13_DS1_LOCD[24:17]

M13_DS1_LOCD[16:9]

M13_DS1_LOCD[8:1]

These individual delta bits are set as the result of the

corresponding state bits M13_DS1_LOC[28:1]

(Table 247) transitioning either from 0 to 1 or from 1 to

0 . Delta bi ts can be programmed to b e either clear on

read (COR) or clear on write (COW), and they are not

set to 1 again until the event reoccurs.

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

209Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 236. M13_DS1_AIS _DETD_R[1 —4], DS 1 Al arm Indication Signal De lta Registers (RO)

Table 237. M13_DS1_LB_DETD_R[1—4], DS1 Loopback Detect Delta Registers (RO)

Table 238. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (R O)

Table 239. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)

Address Bit Name Function Reset

Default

0x10022 15:4 —Reserved. 0x000

0x10023—

0x10025 15:8 —Reserved. 0x00

0x10022

0x10023

0x10024

0x10025

3:0

7:0

M13_DS1_AIS_DETD[28:25]

M13_DS1_AIS_DETD[24:17]

M13_DS1_AIS_DETD[16:9]

M13_DS1_AIS_DETD[8:1]

These individual delta bits are set as the result of the

correspondi ng state bits M13_DS 1_AIS_DET[28 :1]

(Table 248) transitioning either from 0 to 1 or from 1

to 0. Delta bits can be pr og rammed to be eit her clear

on read (COR) or c lear on write (CO W), and the y are

not set to 1 again until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10026 15:4 —Reserved. 0x000

0x10027—

0x10029 15:8 —Reserved. 0x00

0x10026

0x10027

0x10028

0x10029

3:0

7:0

M13_DS1_LB_DETD[28:25]

M13_DS1_LB_DETD[24:17]

M13_DS1_LB_DETD[16:9]

M13_DS1_LB_DETD[8:1]

These individual delta bits are set as the result of the

correspondin g s tate bits M13_DS 1_LB_DET[28:1]

(Table 249) transitioning either from 0 to 1 or From 1

to 0. Delta bit s can be programmed to be either clear

on read (COR ) or clear on write (COW), and they are

not s et to 1 again until the event r eoccurs.

0x00

Address Bit Name Function Reset

Default

0x1002F 15:7 —Reserved. 0x000

6:0 M13_XC_DS2_

LOC[7:1] A logic 1 of M13_XC_DS2_LOCy bit indicates that loss o f

clock is detected on the DS2 clock input. 0x00

Address Bit Name Function Reset

Default

0x10030 15:7 —Reserved. 0x000

6:0 M13_XC_DS2_

AIS_DET[7:1] The M13_XC_DS2_AIS_DETy bit is set high i f the input

XC_DS2 M23 DATAy is 0 for fewer than 5 clock cycles in each

of two consecutive 840 clock p eriods , And cleared if there are

more than four zeros in each of two consecutive 840- bit peri-

ods.

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

210 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 240. M13_DS2_OOF_R, DS2 Out of Frame Status (RO)

Table 2 41. M13_DS2_LOF_R, DS 2 Loss of Frame Status (RO)

Table 242. M13_DS2_AIS_DE T_R, DS2 Alarm Indication Signal Detect Statu s (RO)

Table 243. M13_DS2_RAI_DET_R, DS2 Rem ote Alarm Indication Detect Status (RO)

Address Bit Name Function Reset

Default

0x10031 15:7 —Reserved. 000000

000

6:0 M13_DS2_O OF[7: 1] This register cont ains th e st ate bits for the DS2 framers. A 1

indicates out-of-frame. 0x7F

Address Bit Name Function Reset

Default

0x10032 15:7 —Reser ved. —

6:0 M13_DS2_LOF [7:1] The M13_ DS2 _LOF y bit is set if M13 _ DS 2_O OFy (Table 240)

is high c ontinuously for 28 DS3 f rame pe riod s (approximately

3 ms). Onc e set, M13_DS 2_LOF y i s not cle ared until

M13_DS2_OOFy is continuously low for 28 DS3 frame peri-

ods. DS3 frame periods are not counted while M13_DS3_OOF

= 1 (Table 224).

0x00

Address Bit Name Function Reset

Default

0x10033 15:7 —Reserved. 0x000

6:0 M13_DS2_AIS_

DET[7:1] The M13_DS 2_AIS_DETy bi t is se t high if the input to t he yth

M12 demultiplexer is logic 0 for fewer than 5 clock cy cles in

each of two consecutive 840 clock periods and cleared if there

are mor e than fou r zer o s in each of two con sec utiv e 840-bit

periods.

0x00

Address Bit Name Function Reset

Default

0x10034 15:7 —Reserved. 0x000

6:0 M13_DS2_RAI_

DET[7:1] The M13_DS2_RAI_DETy bit changes state only after the X bit

in the DS1 mode (M13_DS1_E1Ny = 1 (Table 263)), or the

RAI bit in the E1 mode is received as the same value for four

consecutive DS2 frames. DS2 fra me periods are not counted

while M13_DS3_OOF = 1 (Table 224). In the DS1 mode,

M13_DS 2_RA I_DETy is set t o the inverse of the X b i t. In the

E1 mode, it is set equal to th e RAI bit.

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

211Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 244. M13_DS 2_LB_DET_R, DS2 Loopback Detect Status (RO)

Table 245. M13_DS 2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO)

Table 246. M13_DS 2DMX_LOC_R, DS2 DeMUX Loss of Clock Status (RO)

Table 247. M13_DS1_LOC_R[1—4], DS1 Loss of Clock Status Registers (RO)

Address Bit Name Function Reset

Default

0x10035 15:7 —Reserved. 0x000

6:0 M13_DS2_LB_

DET[7:1] In the M23 mode (M13_M23_CBP = 1 (Table 260)), the C bits

in each received DS3 M-sub frame are checked for loopback

requests. I f the third C bit differs fr om the first and second C

bits in the yth M-subframe for 5 successive DS3 frames,

M13_DS2_LB_DE Ty is set to 1. M13_D S2_LB _D ETy is

cleared when t he third C bit does not differ from the first t w o C

bits in subfram e y for 5 successive DS3 frames. In the C-bit

parity mode, M13_DS2_LB_DETy i s fixed at 0.

0x00

Address Bit Name Function Reset

Default

0x10036 15:7 —Reserved. 0x000

6:0 M13_DS2_RSV_

RCV[7:1] The M13_DS2_RS V _RCVy bi t changes state only after the

reserve d bit in the E1 mod e (M13_DS1_E1Ny = 0) i s received

as the same value for 4 co ns ecutive DS2 frames. DS 2 frame

periods are not counted while M13_DS3_OOF = 1. It i s set

equal to the reserved bit.

0x00

Address Bit Name Function Reset

Default

0x10037 15:7 —Reserved. 0x000

6:0 M13_DS2DMX_

LOC[7:1] A logic 1 of M13_DS2DMX_LOC y bit indicates that loss of

clock is detected on the DS2 clock input, XC _DS2DMXC LKy. 0x00

Address Bit Name Function Reset

Default

0x1003C

0x1003D

0x1003E

0x1003F

0x1003C

0x1003D

0x1003E

0x1003F

15:4

15:8

3:0

7:0

—

M13_DS1_LOC[28:25]

M13_DS1_LOC[24:17]

M13_DS1_LOC[16:9]

M13_DS1_LOC[8:1]

Reserved.

The M13 _DS1_LOCx bits indicate wh en loss of clo ck is

detect ed on a low-speed clock input, X C_DS1CLKx.

0x000

0x00

0x0

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

212 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 248. M13_DS1_AIS_DET_R[1 —4], DS 1 Ala rm I ndication Si gnal Detect Status Registers (RO)

Table 249. M13_DS1_L B_DET_R[1—4], DS 1 Lo opback Detect St atus Reg isters (RO)

Address Bit Name Function Reset

Default

0x10040

0x10041

0x10042

0x10043

0x10040

0x10041

0x10042

0x10043

15:4

15:8

3:0

7:0

—

M13_DS1_AIS_DET[28:25]

M13_DS1_AIS_DET[24:17]

M13_DS1_AIS_DET[16:9]

M13_DS1_AIS_DET[8:1]

Reserved.

The M13_DS1_A IS _DE Tx bits indicate when AIS is

detected on a low-speed data input, XC_DS1DATAx.

0x000

0x00

0x0

0x00

Address Bit Name Function Reset

Default

0x10044

0x10045

0x10046

0x10047

0x10044

0x10045

0x10046

0x10047

15:4

15:8

3:0

7:0

—

M13_DS1_LB_DET[28:25]

M13_DS1_LB_DET[24:17]

M13_DS1_LB_DET[16:9]

M13_DS1_LB_DET[8:1]

Reserved.

The M13_DS1_LB _DETx bits indicate when a loopback

request has been received through inversion of the third

C bit in rec eived DS2 fram es.

0x000

0x00

0x0

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

213Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 250. M13_DS1_F EAC_LB_DETD_R[1—4], DS1 Far-E nd Alarm and Contro l L oopback Detect Delta

Registers (RO)

Table 251. M13_DS1_FEAC_LB _DET_R[1—4], DS1 Far-End Alarm and Control L oopback Detect Status

Registers (RO)

A ddress Bit Name Functi on Reset

Default

0x10049

0x1004A

0x1004B

0x1004C

0x10049

0x1004A

0x1004B

0x1004C

15:8

6:4

15:8

3:0

7:0

—

M13_DS3_FLB_DETD

—

M13_DS1_FEAC_LB_DETD[28:25]

M13_DS1_FEAC_LB_DETD[24:17]

M13_DS1_FEAC_LB_DETD[16:9]

M13_DS1_FEAC_LB_DETD[8:1]

Reserved.

This d elta bit is set if M13_DS3_FLB_DET

(Table 251) changes state. It can be pro-

grammed to be either clear on read (COR) or

clear on write (COW), and it is not set to 1

again until another state transition occurs.

Reserved.

These individual delta bits are set as the

result of the corresponding state bits

M13_DS1_FEAC_LB_DET[28:1] (Table 251)

transitioning either from 0 to 1 or from 1 to 0.

Del ta bits c an be programmed to be either

clear on read (COR) or clear on write

(COW), and they are not set to 1 again until

the event reoc c urs.

0x00

0x0

000

0x00

0x0

0x00

Address Bit Name Function Reset

Default

0x1004D

0x1004E

0x1004F

0x10050

0x1004D

0x1004E

0x1004F

0x10050

15:8

6:4

15:8

3:0

7:0

—

M13_DS3_FLB_DET

—

M13_DS1_FEAC_LB_DET[28:25]

M13_DS1_FEAC_LB_DET[24:17]

M13_DS1_FEAC_LB_DET[16:9]

M13_DS1_FEAC_LB_DET[8:1]

Reserved.

When an FEAC l oopback activate codeword for

DS3 is received four consecutive times, the bit is

set high. Th e bit is cleared when a loopback deacti-

vate codeword is received four c ons ec ut ive times.

Reserved.

When an FEAC l oopback activate codeword for

DS1 is received four consecutive times, the appro-

priate bit(s) is set high. T he bit(s) is cleared when a

loopback deactiv ate codeword f or that channel(s) is

received four cons ecu tive times.

0x00

000

0x00

0x0

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

214 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 252. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status ( RO)

Table 253. M13_RDL_S TATUS, Receive Data-Link S tatus (RO)

Table 254. M13_RDL_DATA_ R, Receive Data-Link Data (RO)

Table 255. M13_RDL_FRAM E_SIZE_R, Receive Data-Link Frame Size (RO)

Address Bit Name Function Reset

Default

0x10051 15:6 —Reserved. 000000

0000

5:0 M13_RFE AC_CODE[5:0] When the same codeword is received through the FEAC

channe l four consecutive times, the M 13 wil l set

M13_RF EAC_CODE [5:0] = x5x4x3x 2x1x 0, where the

received FEAC c odewo rd is 0x5x4x 3x 2x 1x 0 0 11111111,

and it is received r ight to left.

0x3F

Address Bit Name Function Reset

Default

0x10052 15:5 —Reserved. 0x000

4 M13_RDL_FLAG This bit is high if the closing flag or an ab ort byte has been

received. 0

3 M13_ RDL_A BORT This bit i s high if the fram e was ended wit h an abort byte

rather than a closing flag . 0

2 M13_RDL_NOT_BYTE T his bit is set if the number of bits i n the frame (after removal

of stuff ed zeros) is not a multiple of 8. 0

1 M13_ RDL_OVFL Thi s bi t i s set if a t lea s t 1 byte of the frame was ov er written by

a byte from a s uc ceeding frame before being read. 0

0 M13_RDL_FCS_ERR This bit is set if the CRC-16 check fails and M13_RDL_FCS =

1 (Table 287). 0

Address Bit Name Function Reset

Default

0x10053 15:8 —Reserved. 0x00

7:0 M13_RDL_DATA[7:0] Bytes received via the path maintenance data link are stored

in a 128-byte FIFO. They can be read out of t h e FIFO through

this register, M13_RDL_DATA_R. On reset, the FIFO is emp-

tied, and reading from this register returns an undetermined

value.

0xXX

Address Bit Name Function Reset

Default

0x10054 15:7 —Reserved. 0x000

6:0 M13_RDL_FRAME_

SIZE[6:0] The number of bytes in the frame modulo-128 is in dicated by

this register . This is the number of bytes from the frame that

have b een written into the FIFO, not the number of byt es

remaining in the FIFO. All bytes bet ween the opening flag and

the FCS bytes are included (unless M13_RDL_FCS

(Table 287) is low , in which case the FCS b ytes are included in

the count).

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

215Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 256. M13_RHDLC_S TATUS_R, Receive High-Level Data-Link Control Status (RO)

Table 257. M13_DS2_F ORCE_OOF_R, DS 2 Force Out of Frame (One Shot R/W)

Table 258. M13_CO N TROL1, Control 1 (One Sh ot R/W )

Address Bit Name Function Reset

Default

0x10055 15:8 —Reserved. 0x00

7:0 M13_RHDLC_

STATUS[7:0] This register provides information on the earliest HDLC frame

still in the FIFO . A value of 1 in bit 7 indicates that the closing

flag or an abort byte for the current frame has been received; a

1 in bit 6 indic ates the c urrent frame is cor rupted; bits 5 to 1

indicate the size of t he current frame modulo-32; and bit 0 is

set to 1 i f there are l ess than 32 by tes of th e earl iest frame left

in the FIFO.

0x00

Address Bit Name Function Reset

Default

0x10059 15:7 —Reserved. 0x000

6:0 M13_DS2_FORCE_

OOF[7:1] When M13_DS 2_FORCE_OOFy transitions from 0 to 1, the

DS2 framer in M12 demultiplexer Y is forced out of frame. 0x00

Address Bit Name Function Reset

Default

0x1005A 15:3 —Reserved. 0x000

2 M13_RDL_FRM_CLR I f M13_RDL_FRM_CLR is set to 1, the portion of the earli-

est frame still in the receive HDLC FIFO will be deleted.

The user must reset M13_R DL_FRM_CLR before another

frame can be deleted. If M13_RDL_FRM_CLR is set bef ore

the closing flag of the frame currently being read from the

FIFO has been received, all subsequent bytes of the frame

will be discarde d without being written into the FIFO.

1 M13_DS 3_FORCE_OOF When this bit transitions fro m 0 to 1, the DS 3 framer is

forced ou t -of-frame. 0

0 M1 3_BIPOL_E RR A single bipolar violation error is transmi tted each time this

bit transitions from 0 to 1. 0

Table 259. M13_CONTROL2, Control 2 (R/W)

Address Bit Name Function Reset

Default

0x1005C 15:8 —Reserved. 0x00

7 M13_BP V_ IN If this bit is 1, the SMP R_RDS3NEG _B PV input is used as an

external B3ZS bipolar violation indication instead of a negativ e

input pu lse.

6 M13_LOO P_TIME T he M23 multiplexer uses the SMPR_TDS3CLK if this bit is 0,

otherwise, the SM PR_RD S3CL K is used. 0

5 M13_LOOP_T_TO_R S et ti ng this bit to 1 causes the M23 MUX output to be looped

back to the M 23 DEMUX input. 0

4 M13 _LOOP_R _TO_T S et ting this bit to 1 causes the received DS3 input to be

looped back to the transmit DS3 output. 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

11 M13/M23 MUX/DeMUX Registers (continued)

216 Agere Sy stem s Inc.

Table 260. M 13_CONTROL3, Control 3 (R/W)

Table 261. M13_SP _OFFSET_R, Sync Pu ls e Offset (R/W)

Table 262. M13_SP _D_OFFSET_ R , Sync Pulse D Offset (R/W)

0x1005C 3 M13_AUTO_AIS_LOF If this bit is 1, the M13 will automatically insert AIS in all DS2

outputs of the M23 demultiplexer when M 13_DS3_LOF = 1

(Table 224), and it will automatically insert AIS in all DS1 or E1

outputs of M12 demultiplexer

when M13_DS2_LOFy = 1

(Table 241).

2 M13_AUTO_AIS_OOF If this bit is 1, the M13 will automatically insert AIS in all DS2

outputs of the M23 demultiplexer when M 13_DS3_OOF = 1

(Table 224), and it will automatically insert AIS in all DS1 or E1

outputs of M12 demultiplexer Y when M13_DS2_OOFy = 1

(Table 240).

1 M13_AUTO_FLB If this bit Is 1, the device will automatically loop the received

DS3 input to the transmit DS3 output when

M13_DS3_FLB_DET = 1 (Table 251), and it will automatically

select DS1 /E1 output

from an M12 demultiplexer in place of

the DS1/E1 output from input selector

when

M13_ DS1 _FEAC_LB_DETx = 1 (Table 251).

0 M13_A UTO_LB When M13_A UTO_LB = 1, loopback of DS1 channel x is ac ti-

vated if M13_DS1_LB_DETx = 1 (Table 249). 0

Address Bit Name Function Reset

Default

0x1005D 15:2 —Reserved. 0x0000

1 M13_M23_CBP If th is Bit Is 1, the M13 Operates in the M23 mo de. Other-

wis e, it is in t he C-Bit Parity Mode. 0

0 M13_BIPOLAR The M13 P erforms B3ZS Encoding And Decoding if this

Bit is High. 0

Address Bit Name Function Reset

Default

0x1005E 15:8 —Reserved. 0x00

7:0 M13_NSMI_SP_

OFFSET[7:0] The Register De termines the Offset Value (0—255) for the

Transmit NSMI sync Pulse ahe ad of the M 1 Bit In a DS 3

Frame.

0x00

Address Bit Name Function Reset

Default

0x1005F 15:8 —Reserved. 0x00

7:0 M13_NSMI_SP_D_

OFFSET[7:0] The Register De termines the Offset Value (0—255) for the

Receive NSM I Sync Pulse ahead of the M1 Bit In a DS3

Frame.

0x00

Table 259. M 13_CONTROL2, Control 2 (R/W) (continued)

Address Bit Name Function Reset

Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

217Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 263. M13_M12_MUX_CONTROL1_R[1—7], M12 MU X CONTROL 1 Re gisters [1—7] (R/W)

Table 264. M13_M12_MUX_CONTROL2_R[1—7], M12 MU X CONTROL 2 Re gisters [1—7] (R/W)

Table 265. M13_DS2_RAI_SEND_R, DS2 Remot e Alarm Indication Send (R/W)

Table 266. M13_DS2_RSV _S E ND_R, DS2 Reserve Bit Send (R/W)

Address Bit Name Function Reset

Default

0x10060

0x10062

0x10064

0x10066

0x10068

0x1006A

0x1006C

15:8 —Reserved. 0x00

7:6 M13_M12_

MODE[1—7][1:0] 00 = The M12 M U X Operates as the First Sta ge Of M 13

Multiplexing. Th e DS1/E1 clocks are inputs to the block.

01 = The M12 MUX oper ates as an independent mul tiple xer .

The DS1/E1 clocks are inputs to the block.

10 = The M12 MUX oper ates as an independent mul tiple xer .

The DS1/E1 clocks are output s from the block.

11 = The M12 is idle.

5 M13_MUXCH2_4_

INV[1—7] If these bits are 1, the second and fourth DS1 inputs to the

M12 multiple x ers are inverted before the y are MUXed into DS2

signals.

4 M13_DS1_E1N[1—7] If these bits are 1, the M12 m ultiplexers operate on DS1

inputs; otherwise, they operate on E1 inputs. 1

3:0 M13_DS1_LB_

REQ[1:28] If these bits are 1, t he t hird C bit for DS1 or E1 channels is

inverted in the generated DS2 frames to indicate loopback

requests.

0x0

Address Bit Name Function Reset

Default

0x10061

0x10063

0x10065

0x10067

0x10069

0x1006B

0x1006D

15:8 —Reserved. 0x00

7:4 M13_SEL_DS1_

LB[1:28] A 1 in the se bits will f orce D eMUXed DS1 o r E1 signals to b e

looped back. 0x0

3:0 M13_RDS1_

EDGE[1:28] A 1 in these bits me ans that the received D S1/E1 signals are

retimed by the rising edge of the associated clocks; a l ogic 0

mea ns that the d ata is re timed by the f alling edge.

0x0

Address Bit Name Function Reset

Default

0x1006E 15:7 —Reserved. 0x000

6:0 M13_DS2_RAI_

SEND[7:1] The Remote Al arm Indication is Acti vated if These Bits are

Set t o 1. 0x00

Address Bit Name Function Reset

Default

0x1006F 15:7 —Reserved. 0x000

6:0 M13_DS2_RSV_

SEND[7:1] In the E1 Mode, the Reserved Bit Of DS2 is set to the V alue

of These Bits. 0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

218 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 267. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W)

Table 268. M13_DS2_FINV_R, DS2 Frame Error (R/W)

Table 269. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W)

Table 270. M13_DS2M 12_EDGE_R , DS2 M12 E dg e (R/W)

Table 271. M13_DS2_F ORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W)

Address Bit Name Function Reset

Default

0x10070 15:7 —Reserved. 0x000

6:0 M13_DS2_

MPINV[7:1] These Bits Determine whether the DS2 M frame Alignment

Signals in the DS1 Mo de, or the DS2 Parity Bits In the E1

Mode are Generated in Error.

0x00

Address Bit Name Function Reset

Default

0x10071 15:7 —Reserved. 0x000

6:0 M13_DS2_FINV[7:1] These Bits Determine whether the DS2 M-Subframe Align-

ment Signals in the DS1 Mode , or the Frame Alignment

Signal in the E1 Mode are Generated in Error.

0x00

Address Bit Name Function Reset

Default

0x10072 15:7 —Reserved. 0x000

6:0 M13_DS2_P_

BER[7:1] The DS2 Pa rity Bits in the E1 Mo de Immediately Following

Each 0 to 1 Transition of the Input SMPR_BER_I NSRT

(Table 65) are Inverted if these Register Bits are Set to 1.

0x00

Address Bit Name Function Reset

Default

0x10073 15:7 —Reserved. 0x000

6:0 M13_DS2M12_

EDGE[7:1] A 1 in these Bits Means that th e Output DS2 Signals From

M12 MUXs are Retimed by the Rising Edge o f the Assoc i-

ated Clocks; A 0 Means that the Data is Retimed by the

Fal ling Edge.

0x00

Address Bit Name Function Reset

Default

0x10074 15:7 —Reserved. 0x000

6:0 M13_DS2_FORCE_

AIS[7:1] A 1 in these Bits Means that the Output DS2 Signals From

M12 MUXs are Forced to be A IS (All Ones). 0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

219Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 272. M13_M12_DE MUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W )

Table 273. M13_M12_DE MUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W )

Table 274. M13_M12_DE MUX_CONT ROL3, DS2 M12 DeMUX Con t rol 3 (R/W)

Address Bit Name Function Reset

Default

0x1007B

0x1007D

0x1007F

0x10081

0x10083

0x10085

0x10087

15:8 —Reserved. 0x00

7:6 M13_M12DMX_

MODE[1—7][1:0] 00 = The M12 DeMUX Recei ves DS2 Signal From the M23

DeMUX.

01 = The M12 deMUX operates as a n independ ent demulti-

plexer.

10 /11 = T he M12 deMUX is idle and outputs a re held low.

5 M13_DEMUXCH2_

4_INV[1—7] The Second and Fourth DS1 Outputs from the M12 Demul-

tip lexers are I n verted if these Bits are 1. 1

4 M13_OUT_

TYPE[1—7] Each DS1/E1 Output Selector Number, x, can be

Expressed as Either 4y – 3, 4y – 2, 4y – 1, or 4y, where y

Ranges From 1 to 7. For a given y, the 4 selectors in the

g r o u p outp u t DS1 si g nal s if M 13_ O UT_TYPEy = 1, or E1 sig-

nals if M13_OUT_T YPEy = 0.

3:0 M13_TDS1_

EDGE[28:1] The Tra nsmit DS1/E 1 Signals ar e Retimed by the Rising

Edge of the Associated Clocks if these Bits are Set High;

Otherwise, the Data is Retimed B y the Falling Edge.

0xF

Address Bit Name Function Reset

Default

0x1007C

0x1007E

0x10080

0x10082

0x10084

0x10086

0x10088

15:4 —Reserved. 0x000

3:0 M13_DS1_OUT_

AIS[28:1] A logic 1 of these bits will cause the corresponding DS1 output

all ones AIS. 0x0

Address Bit Name Function Reset

Default

0x10089 15:2 —Reserved. 0x0000

1 M13_DS2_MODE This Bit Controls the DS2 Framing Algorithm I n the DS1

Mo de O nly. Out of frame is declared if the F bits co ntain two

errors in 4 bits if M 13_D S2_ MODE = 0, or at leas t 1 F-bit error

in four co ns ecutive M-subframe pairs if M13_DS2_MODE = 1 .

0 M13_DS2_FERR_

MODE This Bit Controls Frame Error Cou nti ng for the M12

Demulti pl exers in the E1 Mode Onl y. If this bit is 0, the frame

erro r counters incre ment for each frame alignment signal bit

error. Otherwise, the counter increments once for each frame

alignment signal that contains at l east 1 bit erro r .

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

220 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 275. M13_DMDS2_EDGE_R, D S2 Edg e for M12 DeMU X (R/W)

Table 276. M13_DS3_CONTROL1, DS3 Control 1 (R/W)

Address Bit Name Function Reset

Default

0x1008A 15:7 —Reserved. 0x000

6:0 M13_DMDS2_

EDGE[7:1] A logic 1 of these bits means that the input DS2 signals to M12

demultiplexers are retimed by the rising edge of the associated

clocks; a lo gic 0 means tha t the data is retimed by the falling

edge.

0x00

Address Bit Name Function Reset

Default

0x10092 15:8 —Reserved. 0x00

7 M13_DS3_FINV For t esting purposes , this bit is high to allo w the F bit to be

generated with errors. 0

6 M13_DS3_MINV For testing purposes, this bit is high to allow the M bit to

be generated with errors. 0

5 M13_DS3_PINV For testing purposes, this bit is high to allow the P Bit to

be generated with errors. 0

4 M13_DS3_FORCE_AI S This bit causes the M 13 to generate DS3 AIS in place of

the trans mit DS3 s ignal from the M23 multiplexer. 0

3 M 13_DS3_FORCE_IDLE This bit causes the M13 to ge nerate DS3 idle (unless

M13_DS3_FORCE_AIS (Table 276) is also s et) in place

of the transmit DS3 signal from the M23 multiplexer.

2 M13_TDS3_FO RCE_ALL1 This bit c aus es the M 13 to generate unframed all ones

DS3 output. 0

1 M 13_M23CLK _MODE If thi s bit is 1, DS2 clocks associated with DS2 signals

being MUXed into DS3 are outputs from the block; other-

wise, they are inputs to the b lock.

0—Reserved. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

221Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 277. M13_DS3_CONTROL2, DS3 Control 2 (R/W)

Table 278. M13_TFEAC_CONTROL, Tx FEAC Control (R/W)

Address Bit Name Function Reset

Default

0x10093 15:7 —Reserved. 0x000

6 M23_STUFF_MODE A Logic 0 on this Bit Will Cause the M23 St uffing to be

Determined by the External Stuff Request; Otherwise,

Fixed Stuffing i s Used.

5 M13_NSMI_MODE A L ogic 1 of this Bit wi ll Enable M 1 3 to Re ceive and O ut -

put Ds3 Payload Through a Serial Link. 0

4 M13_DS3_P_BER Th e P Bits a nd, in CB P Mod e, th e C P Bit s in the DS3

Frame Immediately Following Eac h 0 to 1 Transition of the

In put SMPR_ BER_INSERT (Table 65), are Inverted if this

Bit is Set to 1.

3 M13_CBIT2_ACT This Bit is Used Only in the C-Bit Parity Mode. In this

mode, i f it i s 0, the second c-bit of each ds3 frame, c2, I s Set

To 1. Otherwise, the transmit value of C2 is input through pin

TCBDATA (E12).

2 M13_UNUSED_ACT This Bit is Used Only in the C-Bit Parity Mode. In this

mode, if it i s 0, the unus ed C b its of each DS3 frame (t he

fourth through sixth and the s ixteenth through twenty-f irs t) are

set to 1. Otherw ise, the transmit values of these bits ar e input

through pin TCBDATA (E12).

1 M13_DS3_RAI_SEND The Transmitted DS3 X Bits are Set to t he Inverse of this

Bit During Normal Transmission. 0

0 M13_FEBE_ERR This Bit is Used to For ce Errors i n the Transm itted DS3

FEBE Indic ation. If the Bit is Set, al l DS3 Frames are

Transmitted with the FEBE Bit s Set t o 000.

Address Bit Name Function Reset

Default

0x10094 15:8 —Reserved. 0x00

7:6 M13_TFEAC_CTL[1:0] The User Can Provision the M13 to Transmit Continuous

One s by Sett ing M13_TF EAC_C TL to 0 0 . 0x0

5:0 M13_TFEAC_CODE[5:0] F EAC Signals. TFEAC sign als are transmitted continuously

by setting M13_TFE AC_CTL to 01, and M13_TFEAC_CODE

= x5x4x3x2x1x0, where x5x4x3x2x1x0 Is the appropriate

value for the ala rm or status codeword.

In order to activate a loopback, the user may set

M13_TF EAC_CTL = 11, A nd M13_TFEAC_CODE =

x5x4x3x2x1x0, where x5x4x3x2x1x0 Is the Appropriate value

for the loopback codeword. The M13 will then transmit 10 rep-

etitions of the activate codeword, 0 000111 0 11111111, fo l-

lowed by 10 repetitions o f 0 x5x4x3x2x 1x0 0 11111111. A fter

transmitting this 40 octet sequence , it wi ll set

M13_TFEAC_DONE (Table 217) to 1.

In order to deactivate a loopback, the user may set

M13_TF EAC_CTL = 10, and M13_TFEAC_CODE =

x5x4x3x2x1x0, where x5x4x3x2x1x0 is the appropri ate value

for the loopback codeword. The M13 will then transmit 10 rep-

etitions of t he deactivate c ode word, 0 011100 0 11111111, fol-

lowed by 10 repetitions o f 0 x5x4x3x2x 1x0 0 11111111. A fter

transmitting this 40 octet sequence , it wi ll set

M13_TFEAC_DONE to 1.

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

222 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 279. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W)

Table 280. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W)

Table 281. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W)

Address Bit Name Function Reset

Default

0x10095 15:6 —Reserved. 0x000

5 M13_TDL_BUF1_END If this Bit is 0, a ll By tes from H DLC Buffer 1 a nd at Least

One Byte from HDLC Buffer 0 are Transmitted. If it is 1,

bytes from buffer 1 a re transmitte d sequent ially up to and

including the byt e s et by M13_TDL_BYTE_END[5:0]

(Table 280).

4 M13_TDL_BUF0_END If this Bit is 0, a ll By tes from H DLC Buffer 0 a nd at Least

One Byte from HDLC Buffer 1 are Transmitted. If it is 1,

bytes from buffer 0 a re transmitte d sequent ially up to and

including the byt e s et by M13_TDL_BYTE_END[5:0].

3 M13_TDL_ACT If the Data Link is not Used, the Us er Should set

M13_TDL_A CT to 0, Which Causes all Ones to be Trans-

mitted. Ot herwise, this bi t should be set to 1.

2 M13_TDL_NTRNL If M13_TDL_NTRN L = 0, the Data Transmitted on the

Data Link Comes Directly from the M13 Input Pin TDL-

DATA (E8); Otherwi se (M13_TDL_NTRNL = 1), the Data

Link is Contr o lled b y the Inter nal HDLC Transmit ter. This

bit is valid only when M13_TDL_ACT = 1 (Table 279).

1 M13_TDL_NTRNL_ACT Once M13_TDL_NTRNL _ACT is Set to 1, the HDL C

Transmitter Begins Transmitting the First Byte of the

First Data Buffer Following the Completion of the Next

Flag Byte. The user ma y abort the transmission of an HDLC

frame b y clearing M13_TDL_NTRNL_ACT to 0 prior to com-

pleting transmission of the last byte from the data buffers. If

so, t he HDLC c ontroller will stop t ransmission from the buff-

ers and send an abort byte (0 1111111). The abort byte will

then be followed by flag bytes until M13_TDL_NTRNL_ACT

is again set to 1, starting transmission of a new frame .

0 M13_TDL_FCS If M13_TDL_FCS = 1, the HDLC Controller Appends the

Two-Byte ITU-T F CS with the Necessary Zero Stuffing

Be fore Se ndin g t he Closing Fl ag; Ot he rwi se, no FCS

Bytes will b e Trans mitted.

Address Bit Name Function Reset

Default

0x10096 15:6 —Reserved. 0x000

5:0 M13_TDL_BYTE_

END[5:0] These Bits Define the Position of the Last Byte to be

Transmitted from the Buff er. 0x00

Address Bit Name Function Reset

Default

0x10097 15:7 —Reserved. 0x000

6:0 M13_DS2_LB_

REQ[7:1] I f M1 3_DS2_ L B_REQy = 1, the Third C Bit in the yth DS3

M-S ubframe i s Transmitte d as the Inverse o f the First Two

C Bits (Whi ch Indicates a Loopback Request for DS2

Channel y).

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

223Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 282. M13_SEL_DS2_LB_R, Select DS2 Loopbac k ( R/W)

Table 283. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W)

Table 284. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W)

Table 285. M13_DS2_O UT_AIS_R, DS2 Output Alarm Indication Si gn al (R/W)

Address Bit Name Function Reset

Default

0x10098 15:7 —Reserved. 0x000

6:0 M13_SEL_DS2_

LB[7:1] If M13_SEL_DS2_LBy = 1, the DS2 S ig nal from Time Slot y

in the Received DS3 Sign a l is Loope d Back into Time

Slot y of th e Tran sm itted DS3 Signal.

0x00

Address Bit Name Function Reset

Default

0x10099 15:7 —Reserved. 0x000

6:0 M13_RDS2_

EDGE[7:1] A logic 1 of these Bits Means that the Received DS2 Sig-

nals are Retimed by the Rising Edge of the Associated

Clocks. A logic 0 me ans that the data is ret imed by the falling

edge. When used in the demand clocking mode of the M23

mapping, M13_ RDS2_EDGE[7:1] = 1 shoul d be set if the

delay from the output clock to the incoming data (the maximum

should be less than 8 STS-1 clock cycles) i s less than 4 STS-1

clock cycles; otherwise, M13_RDS2_EDGE[7:1] = 0 should be

used.

0x00

0x1009A 15:7 —Reserved. 0x000

6:0 M13_DS2ALCO_

RTM_EDGE[7:1] In the Demand Clock ing Mode of the M23 Ma pping, this

ity, in Addition to M13_RDS2_EDGE[7:1], for Retiming

Input D S2 Data . It should normally be set to logic 1 (defa ult).

A logi c 0 is suggested on ly to be used with

M1 3_ RD S 2_ED G E[7:1] = 0 when neces sary.

0x7F

Address Bit Name Function Reset

Default

0x1009E 15:7 —Reserved. 0x000

6:0 M13_DS2_OUT_

IDLE[7:1] If M13_DS2_OUT _IDLEy = 1 , the Output from DS2 Output

Selection Block y is Held Low. 0x00

Address Bit Name Function Reset

Default

0x1009F 15:7 —Reserved. 0x000

6:0 M13_DS2_OUT_

AIS[7:1] If M13_DS2_OUT _IDLEy = 0 (Table 284), a Logic 1 of this

Bit Ca us es D S2 AIS to be Output From the DS2 Ou tput

Selector y; Otherwise, the DS2 Sign al From Time Sl ot y in

the Received DS3 Signal will be Output.

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

224 Agere Sy stem s Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 286. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W)

Table 287. M13_RDL_CONTROL, RDL Control (R/W)

Table 288. M13_PM_CNT_ACT_R, Performance Counter (RO)

Table 289. M13_DS3_F ERR_CNT_R[1—2], DS3 F-Bit Error Registers (RO)

Address Bit Name Function Reset

Default

0x100A0 15:7 —Reserved. 000000

000

6:0 M13_TDS2_EDGE[7:1] A logic 1 of these Bits Means that the Transmit DS2 Sig-

nals are Retimed by t he Rising Edge of the A ssoc iated

Clocks. A logic 0 means that the data is retimed by the falling

edge.

0x7F

Address Bit Name Function Reset

Default

0x100A1 15:5 —Reserved. 0x000

4:3 M13 _ RDL_FI L L [1:0] 00 = se ts the receive HDL C FIFO fill leve l to 16 bytes.

01 = set s th e rece ive HD L C FIFO fill leve l to 32 bytes.

10 = set s th e rece ive HD L C FIFO fill leve l to 64 bytes.

11 = set s th e rece ive HD L C FIFO fill leve l to 96 bytes.

The M13_RDL_F IFO_AF (Table 225) bit i s se t if the buffer

reaches t he fill level.

2 M13_RDL_FCS If M13_RDL_FCS = 1, the FCS Bytes will be Checked at

HDLC Receiver. Otherwise, the FCS is not che cked and the

last 2 bytes of the HDLC frame are writ ten into the FIFO.

1 M13_DS3_MODE This Bit Controls the DS3 Framing Algorithm. Out-of-frame is

declared if the F bits contain 3 errors in 16 bits if

M13_DS3_M ODE = 0, or at least 1 F-bit error in fo ur cons ecu-

tive M-subframes if M13_DS3 _MODE = 1.

0 M13_RDS3_EDGE A logic 1 of t hi s Bit Means that the Received DS3 Data is

Retimed by the Rising Edge of the Associated Clock. A

logic 0 means the d ata is retimed by the falling edge.

Address Bit Name Function Reset

Default

0x100A5 15:1 —Reserved. 0x0000

0 M13_PM_CNT_ACT This Bit Returns a 0 When Read if all Perform ance

Counter Values are 0; Otherwise, it’s Set to 1. 0

Address Bit Name Function Reset

Default

0x100A6 15:4 —Reserved. 0x000

0x100A7 15:8 —Reserved. 0x00

0x100A6

0x100A7 3:0

7:0 M13_DS3_FERR_CNT[11:8]

M13_DS3_FERR_CNT[7:0] This Register Holds the Results fro m a Counter

th at Increments each T i me an Error is Dete cted in

Either a DS3 F Bit, or M Bit.

0x0

0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

225Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 290. M13_DS3_F EBE_CNT_R[1—2], DS3 Far-End Bl ock Error Registers (RO)

Table 291. M13_DS3_CPE RR_CNT_R[1—2], DS3 C-Bit Parity Error Registe rs (RO)

Table 292. M13_DS3_PE RR_CNT_R[1—2], DS3 P-Bit Error Registers (RO)

Address Bit Name Function Reset

Default

0x100A8 15:6 —Reserved. 0x000

0x100A9 15:8 —Reserved. 0x00

0x100A8

0x100A9 5:0

7:0 M13_DS3_FEBE_CNT[13:8]

M13_DS3_FEBE_CNT[7:0] This Register Holds the Results from a Counter

that Accumulates FEBE Error I ndications (1 Error

Indica tion for each DS3 Frame wi th at Least One

FE BE Bit Equal to Z ero ) .

0x00

Address Bit Name Function Reset

Default

0x100AA 15:6 —Reserved. 0x000

0x100AB 15:8 —Reserved. 0x00

0x100AA

0x100AB 5:0

7:0 M13_DS3_CPERR_CNT[13:8]

M13_DS3_CPERR_CNT[7:0] This Register is Used Only in the C -B it Pari ty

Mode. It indicates the number of fr ames with two or

more C-bit parity errors.

0x00

Address Bit Name Function Reset

Default

0x100AC 15:6 —Reserved. 0x000

0x100AD 15:8 —Reserved. 0x00

0x100AC

0x100AD 5:0

7:0 M13_DS3_PERR_CNT[13:8]

M13_DS3_PERR_CNT[7:0] This Register Indicates the Numb er of Frames

with at Least One P Bit that Disagrees with the

Parity of the Previ ous Fram e.

0x00

Table 293. M13_DS2_PE RR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO)

Address Bit Name Function Reset

Default

0x100B2

0x100B3

0x100B4

0x100B5

0x100B6

0x100B7

0x100B8

0x100B9

0x100BA

0x100BB

0x100BC

0x100BD

0x100BE

0x100BF

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

—Reserved. 0x000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

11 M13/M23 MUX/DeMUX Registers (continued)

226 Agere Sy stem s Inc.

Table 294. M13_DS2_F ERR_CNT[7—1]_R, F-Bit Error Coun ter Statu s Registers (RO)

Table 295. M13_BPV_CNT_ R[1—3], Bipolar Violation Counter Status Registers (RO)

0x100B2

0x100B3 4:0

7:0 M13_DS2_PERR_CNT7[12:8]

M13_DS2_PERR_CNT7[7:0] These Register s are Used by M12 Demulti-

plexers that Operate i n the G.747 (E1)

mode. They indicate the number of received

DS2 frames with P-bit errors.

0x00

0x100B4

0x100B5 4:0

7:0 M13_DS2_PERR_CNT6[12:8]

M13_DS2_PERR_CNT6[7:0] 0x00

0x00

0x100B6

0x100B7 4:0

7:0 M13_DS2_PERR_CNT5[12:8]

M13_DS2_PERR_CNT5[7:0] 0x00

0x00

0x100B8

0x100B9 4:0

7:0 M13_DS2_PERR_CNT4[12:8]

M13_DS2_PERR_CNT4[7:0] 0x00

0x00

0x100BA

0x100BB 4:0

7:0 M13_DS2_PERR_CNT3[12:8]

M13_DS2_PERR_CNT3[7:0] 0x00

0x00

0x100BC

0x100BD 4:0

7:0 M13_DS2_PERR_CNT2[12:8]

M13_DS2_PERR_CNT2[7:0] 0x00

0x00

0x100BE

0x100BF 4:0

7:0 M13_DS2_PERR_CNT1[12:8]

M13_DS2_PERR_CNT1[7:0] 0x00

0x00

Address Bit Name Function Reset

Default

0x100C6

—

0x100CC

15:8 —Reserved. 0x00

0x100C6

—

0x100CC

7:0 M13_DS2_FERR_CNT[7—1][7:0] These Registers Hold the Results From DS2

Frame Alignment Signal Err or Counters. In t he

DS1 mode, these counters in crement each time

an error is detected in either an F bit or M bit. In

the E1 mode, the cou nters increment either for

eac h frame alignment signal bit error

(if M13_DS2_FERR_MODE (Table 274) is 0), or

onc e for each frame alignment signal that con -

tains at le ast one bit error

(if M13_DS2_FERR_MODE = 1).

0x00

Address Bit Name Function Reset

Default

0x100CD

—

0x100CF

15:8 —Reserved. 0x00

0x100CD

—

0x100CF

7:0 M13_BPV_CNT[23:0] This Register is Only Used In the DS3 Bipolar

Mode. It holds the results from a counter that incre-

ments each t im e a received B3ZS bipolar cod ing

violat ion is detected.

0x00

Table 293. M13_DS2_PE RR_CNT[7—1]_R[1—2], P-Bit Error Cou nter S tatus Registers (RO) (continued)

Address Bit Name Function Reset

Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

227Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 296. M13_EXZ_CNT_R[1—3], Bipolar Violation Counter Status Register s (RO)

Table 297. M13_TDL_BUFFE R_R, Tx Data-Link Buffer Control (R/W)

Table 298. M13_TDL_0DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 0 Registers

(64 Bytes x 8 Bits) (R/W)

Table 299. M13_TDL_1DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 1 Registers

(64 Bytes x 8 Bits) (R/W)

Address Bit Name Function Reset

Default

0x100D0

—

0x100D2

15:8 —Reserved. 0x00

0x100D0

—

0x100D2

7:0 M13_EXZ_CNT[23:0] Thi s Register is only Used in the DS3 Bipolar Mod e. It

holds the results f rom a counter t hat inc re ments each time an

excessive zeros stri ng is dete cted.

0x00

Address Bit Name Function Reset

Default

0x100FF 15:1 —Reserved. 0x0000

0 M13_TDL_BUFFER If this Bit is 0, Data Written to Registers

M13_TDL_0DATA_R[0—63] Address 0x10100—0x1013F

(Table 297) is Stored in the Pat h Maintenance Data-Link

Buffer 0. Otherwise, the data is wri tten to buf fer 1.

Address Bit Name Function Reset

Default

0x10100

—

0x1013F

15:8 —Reserved. 0x00

0x10100

—

0x1013F

7:0 M13_TDL_

0DATA[0—63][7:0] This 64-Byte Buffer for the Transmit Path Maintenance

Data Link is Accessible whe n M13_TDL_BUFFER = 0

(Table 297). On reset, reading from these registers retur ns an

undetermined value.

0xXX

Address Bit Name Function Reset

Default

0x10100

—

0x1013F

15:8 —Reserved. 0x00

0x10100

—

0x1013F

7:0 M13_TDL_

1DATA[0—63][7:0] This 64-Byte Buffer for the Transmit Path Maintenance

Data Link is Accessible whe n M13_TDL_BUFFER = 1. On

reset, reading from these registers ret urns an undetermined

value.

0xXX

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

228Lucent Technologies Inc.

11 M13/M23 MUX/DeM UX Registers (continued)

11.2 M1 3 Register Ma p

Table 300. Register Address Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Sym bol Bits [15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Block-level Status—RO

0x10000 M13_ID_R M13_ID[7:0]

0x10001 M13_VERSION_R M13_VERSION[2:0]

0x10002

0x10003 —

DS3 Deltas, Summary Deltas, FEAC, a nd DL Interrupts—RO

0x10004 M13_DELTA1 M13_RDL_IDLED M13_DS3_LOFD M13_DS3_OOFD M13_DS3_C1_DETD M13_DS3_RAI_DETD M13_DS3_AISPAT_DETD M13_DS3_IDLEPAT_DETD M13_DS3_CBZ_DETD

0x10005 M13_DELTA2 M13_DS1_LB_SD M13_DS1_AIS_SD M13_DS1_LOC_SD M13_RDS3_SEFD M13_RDS3_ALL1_DETD M13_RDS3_LOSD M13_TDS3_LOCD M13_RDS3_LOCD

0x10006 M13_DELTA3 M13_DS2_RSV_SD M13_DS2_LB_SD M13_DS2_RAI_SD M13_DS2_AIS_SD M13_DS2_LOF_SD M13_DS2_OOF_SD M13_XC_DS2_AIS_SD M13_XC_DS2_LOC_SD

0x10007 M13_DELTA4 M13_TFEAC_DONE M13_TDL_DONE M13_TDL_BUF1_INT M13_TDL_BUF0_INT M13_RDL_FIFO_AFD M13_RDL_FRM_INT M13_RFEAC_ALM_INT M13_RFEAC_LB_INT

0x10008 M13_DELTA5 M13_DS2DMX_LOC_SD M13_RDL_FIFO_UFD

0x10009 —

Interrup t Masks—R/W

0x1000A M13_MASK1 M13_RDL_IDLEM M13_DS3_LOFM M13_DS3_OOFM M13_DS3_C1_DETM M13_DS3_RAI_DETM M13_DS3_AISPAT_DETM M13_DS3_IDLEPAT_DETM M13_DS3_CBZ_DETM

0x1000B M13_MASK2 M13_DS1_LB_SM M13_DS1_AIS_SM M13_DS1_LOC_SM M13_RDS3_SEFM M13_RDS3_ALL1_DETM M13_RDS3_LOSM M13_TDS3_LOCM M13_RDS3_LOCM

0x1000C M13_MASK3 M13_DS2_RSV_SM M13_DS2_LB_SM M13_DS2_RAI_SM M13_DS2_AIS_SM M13_DS2_LOF_SM M13_DS2_OOF_SM M13_XC_DS2_AIS_SM M13_XC_DS2_LOC_SM

0x1000D M13_MASK4 M13_TFEAC_DONEM M13_TDL_DONEM M13_TDL_BUF1_INTM M13_TDL_BUF0_INTM M13_RDL_FIFO_AFM M13_RDL_FRM_INTM M13_RFEAC_ALM_INTM M13_RFEAC_LB_INTM

0x1000E M13_MASK5 M13_DS2DMX_LOC_SM M13_RDL_FIFO_UFM

DS3 Status—RO

0x1000F M13_DS3_STATUS1 M13_RDL_IDLE M13_DS3_LOF M13_DS3_OOF M13_DS3_C1_DET M13_DS3_RAI_DET M13_DS3_AISPAT_DET M13_DS3_IDLEPAT_DET M13_DS3_CBZ_DET

0x10010 M13_DS3_STATUS2 M13_RDL_FIFO_UF M13_RDL_FIFO_AF M13_RDS3_SEF M13_RDS3_ALL1_DET M13_RDS3_LOS M13_TDS3_LOC M13_RDS3_LOC

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

229 Lucent Techn olo

ies Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 300. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Individual DS2 and DS1 Deltas—RO

0x10011 M13_XC_DS2_LOCD_R M13_XC_DS2_LOCD[7:1]

0x10012 M13_XC_DS2_AIS_DETD_R M13_XC_DS2_AIS_DETD[7:1]

0x10013 M13_DS2_OOFD_R M13_DS2_OOFD[7:1]

0x10014 M13_DS2_LOFD_R M13_DS2_LOFD[7:1]

0x10015 M13_DS2_AIS_DETD_R M13_DS2_AIS_DETD[7:1]

0x10016 M13_DS2_RAI_DETD_R M13_DS2_RAI_DETD[7:1]

0x10017 M13_DS2_LB_DETD_R M13_DS2_LB_DETD[7:1]

0x10018 M13_DS2_RSV_RCVD_R M13_DS2_RSV_RCVD[7:1]

0x10019 M13_DS2DMX_LOCD_R M13_DS2DMX_LOCD[7:1]

0x1001A

—

0x1001D

—

0x1001E M13_DS1_LOCD_R1 M13_DS1_LOCD[28:25]

0x1001F M13_DS1_LOCD_R2 M13_DS1_LOCD[24:17]

0x10020 M13_DS1_LOCD_R3 M13_DS1_LOCD[16:9]

0x10021 M13_DS1_LOCD_R4 M13_DS1_LOCD[8:1]

0x10022 M13_DS1_AIS_DETD_R1 M13_DS1_AIS_DETD[28:25]

0x10023 M13_DS1_AIS_DETD_R2 M13_DS1_AIS_DETD[24:17]

0x10024 M13_DS1_AIS_DETD_R3 M13_DS1_AIS_DETD[16:9]

0x10025 M13_DS1_AIS_DETD_R4 M13_DS1_AIS_DETD[8:1]

0x10026 M13_DS1_LB_DETD_R1 M13_DS1_LB_DETD[28:25]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

230Lucent Technologies Inc.

11 M13/M23 MUX/DeM UX Registers (continued)

Table 300. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10027 M13_DS1_LB_DETD_R2 M13_DS1_LB_DETD[24:17]

0x10028 M13_DS1_LB_DETD_R3 M13_DS1_LB_DETD[16:9]

0x10029 M13_DS1_LB_DETD_R4 M13_DS1_LB_DETD[8:1]

0x1002A

—

0x1002E

—

DS2 and DS1 Status—RO

0x1002F M13_XC_DS2_LOC_R M13_XC_DS2_LOC[7:1]

0x10030 M13_XC_DS2_AIS_DET_R M13_XC_DS2_AIS_DET[7:1]

0x10031 M13_DS2_OOF_R M13_DS2_OOF[7:1]

0x10032 M13_DS2_LOF_R M13_DS2_LOF[7:1]

0x10033 M13_DS2_AIS_DET_R M13_DS2_AIS_DET[7:1]

0x10034 M13_DS2_RAI_DET_R M13_DS2_RAI_DET[7:1]

0x10035 M13_DS2_LB_DET_R M13_DS2_LB_DET[7:1]

0x10036 M13_DS2_RSV_RCV_R M13_DS2_RSV_RCV[7:1]

0x10037 M13_DS2DMX_LOC_R M13_DS2DMX_LOC[7:1]

0x10038

—

0x1003B

—

0x1003C M13_DS1_LOC_R1 M13_DS1_LOC[28:25]

0x1003D M13_DS1_LOC_R2 M13_DS1_LOC[24:17]

0x1003E M13_DS1_LOC_R3 M13_DS1_LOC[16:9]

0x1003F M13_DS1_LOC_R4 M13_DS1_LOC[8:1]

0x10040 M13_DS1_AIS_DET_R1 M13_DS1_AIS_DET[28:25]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

231 Lucent Techn olo

ies Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 300. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bi t 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10041 M13_DS1_AIS_DET_R2 M13_DS1_AIS_DET[24:17]

0x10042 M13_DS1_AIS_DET_R3 M13_DS1_AIS_DET[16:9]

0x10043 M13_DS1_LB_DET_R4 M13_DS1_AIS_DET[8:1]

0x10044 M13_DS1_LB_DET_R1 M13_DS1_LB_DET[28:25]

0x10045 M13_DS1_LB_DET_R2 M13_DS1_LB_DET[24:17]

0x10046 M13_DS1_LB_DET_R3 M13_DS1_LB_DET[16:9]

0x10047 M13_DS1_LB_DET_R4 M13_DS1_LB_DET[8:1]

0x10048 —

FEAC Loopback Individual Deltas—RO

0x10049 M13_DS1_FEAC_LB_DETD_R1 M13_DS3_FLB_DETD M13_DS1_FEAC_LB_DETD[28:25]

0x1004A M13_DS1_FEAC_LB_DETD_R2 M13_DS1_FEAC_LB_DETD[24:17]

0x1004B M13_DS1_FEAC_LB_DETD_R3 M13_DS1_FEAC_LB_DETD[16:9]

0x1004C M13_DS1_FEAC_LB_DETD_R4 M13_DS1_FEAC_LB_DETD[8:1]

FEAC

Status,

RDL Sta-

tus, and

RDL

FIFO—

0x1004D M13_DS1_FEAC_LB_DET_R1 M13_DS3_FLB_DET M13_DS1_FEAC_LB_DET[28:25]

0x1004E M13_DS1_FEAC_LB_DET_R2 M13_DS1_FEAC_LB_DET[24:17]

0x1004F M13_DS1_FEAC_LB_DET_R3 M13_DS1_FEAC_LB_DET[16:9]

0x10050 M13_DS1_FEAC_LB_DET_R4 M13_DS1_FEAC_LB_DET[8:1]

0x10051 M13_RFEAC_CODE_R M13_RFEAC_CODE[5:0]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

232Lucent Technologies Inc.

11 M13/M23 MUX/DeM UX Registers (continued)

Table 300. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10052 M13_RDL_STATUS M13_RDL_FLAG M13_RDL_ABOR

TM13_RDL_NOT_

BYTE M13_RDL_OVFL M13_RDL_FCS_

ERR

0x10053 M13_RDL_DATA_R M13_RDL_DATA[7:0]

0x10054 M13_RDL_FRAME_SIZE_R M13_RDL_FRAME_SIZE[6:0]

0x10055 M13_RHDLC_STATUS_R M13_RHDLC_STATUS[7:0]

0x10056

—

0x10058

—

One Shot Signals—R/Wl

0x10059 M13_DS2_FORCE_OOF_R M13_DS2_FORCE_OOF[7:1]

0x1005A M13_CONTROL1 M13_RDL_FRM_

CLR M13_DS3_FORC

E_OOF M13_BIPOL_ER

0x1005B —

Block-level Controls—R/W

0x1005C M13_CONTROL2 M13_BPV_IN M13_LOOP_TIME M13_LOOP_T_T

O_R M13_LOOP_R_T

O_T M13_AUTO_AIS_

LOF M13_AUTO_AIS_

OOF M13_AUTO_FLB M13_AUTO_LB

0x1005D M13_CONTROL3 M13_M23_CBP M13_BIPOLAR

0x1005E M13_SP_OFFSET_R M13_SP__OFFSET[7:0]

0x1005F M13_SP_D_OFFSET_R M13_SP_D_OFFSET[7:0]

M12 MUX’s Control—R/W

0x10060 M13_M12_MUX_CONTROL1_R1 M13_M12_MODE1[1:0] M13_MUXCH2_4

_INV1 M13_DS1_E1N1 M13_DS1_LB_REQ[4:1]

0x10061 M13_M12_MUX_CONTROL2_R1 M13_SEL_DS1_LB[4:1] M13_RDS1_EDGE[4:1]

0x10062 M13_M12_MUX_CONTROL1_R2 M13_M12_MODE2[1:0] M13_MUXCH2_4

_INV2 M13_DS1_E1N2 M13_DS1_LB_REQ[8:5]

0x10063 M13_M12_MUX_CONTROL2_R2 M13_SEL_DS1_LB[8:5] M13_RDS1_EDGE[8:5]

0x10064 M13_M12_MUX_CONTROL1_R3 M13_M12_MODE3[1:0] M13_MUXCH2_4

_INV3 M13_DS1_E1N3 M13_DS1_LB_REQ[12:9]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

233 Lucent Techn olo

ies Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 300. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 B it 11 Bit 10 B it 9 Bit 8 Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10065 M13_M12_MUX_CONTROL2_R3 M13_SEL_DS1_LB[12:9] M13_RDS1_EDGE[12:9]

0x10066 M13_M12_MUX_CONTROL1_R4 M13_M12_MODE4[1:0] M13_MUXCH2_4_INV4 M13_DS1_E1N4 M13_DS1_LB_REQ[16:13]

0x10067 M13_M12_MUX_CONTROL2_R4 M13_SEL_DS1_LB[16:13] M13_RDS1_EDGE[16:13]

0x10068 M13_M12_MUX_CONTROL1_R5 M13_M12_MODE5[1:0] M13_MUXCH2_4_INV5 M13_DS1_E1N5 M13_DS1_LB_REQ[20:17]

0x10069 M13_M12_MUX_CONTROL2_R5 M13_SEL_DS1_LB[20:17] M13_RDS1_EDGE[20:17]

0x1006A M13_M12_MUX_CONTROL1_R6 M13_M12_MODE6[1:0] M13_MUXCH2_4_INV6 M13_DS1_E1N6 M13_DS1_LB_REQ[24:21]

0x1006B M13_M12_MUX_CONTROL2_R6 M13_SEL_DS1_LB[24:21] M13_RDS1_EDGE[24:21]

0x1006C M13_M12_MUX_CONTROL1_R7 M13_M12_MODE7[1:0] M13_MUXCH2_4_INV7 M13_DS1_E1N7 M13_DS1_LB_REQ[28:25]

0x1006D M13_M12_MUX_CONTROL2_R7 M13_SEL_DS1_LB[28:25] M13_RDS1_EDGE[28:25]

0x1006E M13_DS2_RAI_SEND_R M13_DS2_RAI_SEND[7:1]

0x1006F M13_DS2_RSV_SEND_R M13_DS2_RSV_SEND[7:1]

0x10070 M13_DS2_MPINV_R M13_DS2_MPINV[7:1]

0x10071 M13_DS2_FINV_R M13_DS2_FINV[7:1]

0x10072 M13_DS2_P_BER_R M13_DS2_P_BER[7:1]

0x10073 M13_DS2M12_EDGE_R M13_DS2M12_EDGE[7:1]

0x10074 M13_DS2_FORCE_AIS_R M13_DS2_FORCE_AIS[7:1]

0x10075

—

0x1007A

—

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

234Lucent Technologies Inc.

11 M13/M23 MUX/DeM UX Registers (continued)

Table 300. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

M12 DeMUX’s Control—R/W

0x1007B M13_M12_DEMUX_CONTROL1_R1 M13_M12DMX_MODE1[1:0] M13_DEMUXCH2_4_

INV1 M13_OUT_TYPE1 M13_TDS1_EDGE[4:1]

0x1007C M13_M12_DEMUX_CONTROL2_R1 M13_DS1_OUT_AIS[4:1]

0x1007D M13_M12_DEMUX_CONTROL1_R2 M13_M12DMX_MODE2[1:0] M13_DEMUXCH2_4_

INV2 M13_OUT_TYPE2 M13_TDS1_EDGE[8:5]

0x1007E M13_M12_DEMUX_CONTROL2_R2 M13_DS1_OUT_AIS[8:5]

0x1007F M13_M12_DEMUX_CONTROL1_R3 M13_M12DMX_MODE3[1:0] M13_DEMUXCH2_4_

INV3 M13_OUT_TYPE3 M13_TDS1_EDGE[12:9]

0x10080 M13_M12_DEMUX_CONTROL2_R3 M13_DS1_OUT_AIS[12:9]

0x10081 M13_M12_DEMUX_CONTROL1_R4 M13_M12DMX_MODE4[1:0] M13_DEMUXCH2_4_

INV4 M13_OUT_TYPE4 M13_TDS1_EDGE[16:13]

0x10082 M13_M12_DEMUX_CONTROL2_R4 M13_DS1_OUT_AIS[16:13]

0x10083 M13_M12_DEMUX_CONTROL1_R5 M13_M12DMX_MODE5[1:0] M13_DEMUXCH2_4_

INV5 M13_OUT_TYPE5 M13_TDS1_EDGE[20:17]

0x10084 M13_M12_DEMUX_CONTROL2_R5 M13_DS1_OUT_AIS[20:17]

0x10085 M13_M12_DEMUX_CONTROL1_R6 M13_M12DMX_MODE6[1:0] M13_DEMUXCH2_4_

INV6 M13_OUT_TYPE6 M13_TDS1_EDGE[24:21]

0x10086 M13_M12_DEMUX_CONTROL2_R6 M13_DS1_OUT_AIS[24:21]

0x10087 M13_M12_DEMUX_CONTROL1_R7 M13_M12DMX_MODE7[1:0] M13_DEMUXCH2_4_

INV7 M13_OUT_TYPE7 M13_TDS1_EDGE[28:25]

0x10088 M13_M12_DEMUX_CONTROL2_R7 M13_DS1_OUT_AIS[28:25]

0x10089 M13_M12_DEMUX_CONTROL3 M13_DS2_MODE M13_DS2_FERR_MODE

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

235 Lucent Techn olo

ies Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 300. Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x1008A M13_DMDS2_EDGE_R M13_DMDS2_EDGE[7:1]

0x1008B

—

0x10091

—

M23 MUX Controls—R/W

0x10092 M13_DS3_CONTROL1 M13_DS3_FINV M13_DS3_MINV M13_DS3_PINV M13_DS3_FORCE

_AIS M13_DS3_FORCE

_IDLE M13_TDS3_

FORCE_ALL1 M13_M23CLK_

MODE

0x10093 M13_DS3_CONTROL2 M13_NSMI_MODE M13_DS3_P_BER M13_CBIT2_ACT M13_UNUSED_AC

TM13_DS3_RAI_

SEND M13_FEBE_ERR

0x10094 M13_TFEAC_CONTROL M13_TFEAC_CTL[1:0] M13_TFEAC_CODE[5:0]

0x10095 M13_THDLC_CONTROL1 M13_TDL_BUF1_

END M13_TDL_BUF0_

END M13_TDL_ACT M13_TDL_NTRNL M13_TDL_

NTRNL_ACT M13_TDL_FCS

0x10096 M13_THDLC_CONTROL2 M13_TDL_BYTE_END[5:0]

0x10097 M13_DS2_LB_REQ_R M13_DS2_LB_REQ[7:1]

0x10098 M13_SEL_DS2_LB_R M13_SEL_DS2_LB[7:1]

0x10099 M13_RDS2_EDGE_R1 M13_RDS2_EDGE[7:1]

0x1009A M13_RDS2_EDGE_R2 M13_DS2ALCO_RTM_EDGE[7:1]

0x1009B

—

0x1009D

—

M23 DeMUX Controls—R/W

0x1009E M13_DS2_OUT_IDLE_R M13_DS2_OUT_IDLE[7:1]

0x1009F M13_DS2_OUT_AIS_R M13_DS2_OUT_AIS[7:1]

0x100A0 M13_TDS2_EDGE_R M13_TDS2_EDGE[7:1]

0x100A1 M13_RDL_CONTROL M13_RDL_FILL[1:0] M13_RDL_FCS M13_DS3_MODE M13_RDS3_EDGE

0x100A2

—

0x100A4

—

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

236Lucent Technologies Inc.

11 M13/M23 MUX/DeM UX Registers (continued)

Table 300. Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Performance Monitoring Counters—RO

0x100A5 M13_PM_CNT_ACT_R M13_PM_C

NT_ACT

0x100A6 M13_DS3_FERR_CNT_R1 M13_DS3_FERR_CNT[11:8]

0x100A7 M13_DS3_FERR_CNT_R2 M13_DS3_FERR_CNT[7:0]

0x100A8 M13_DS3_FEBE_CNT_R1 M13_DS3_FEBE_CNT[13:8]

0x100A9 M13_DS3_FEBE_CNT_R2 M13_DS3_FEBE_CNT[7:0]

0x100AA M13_DS3_CPERR_CNT_R1 M13_DS3_CPERR_CNT[13:8]

0x100AB M13_DS3_CPERR_CNT_R2 M13_DS3_CPERR_CNT[7:0]

0x100AC M13_DS3_PERR_CNT_R1 M13_DS3_PERR_CNT[13:8]

0x100AD M13_DS3_PERR_CNT_R2 M13_DS3_PERR_CNT[7:0]

0x100AE

—

0x100B1

—

0x100B2 M13_DS2_PERR_CNT7_R1 M13_DS2_PERR_CNT7[12:8]

0x100B3 M13_DS2_PERR_CNT7_R2 M13_DS2_PERR_CNT7[7:0]

0x100B4 M13_DS2_PERR_CNT6_R1 M13_DS2_PERR_CNT6[12:8]

0x100B5 M13_DS2_PERR_CNT6_R2 M13_DS2_PERR_CNT6[7:0]

0x100B6 M13_DS2_PERR_CNT5_R1 M13_DS2_PERR_CNT5[12:8]

0x100B7 M13_DS2_PERR_CNT5_R2 M13_DS2_PERR_CNT5[7:0]

0x100B8 M13_DS2_PERR_CNT4_R1 M13_DS2_PERR_CNT4[12:8]

0x100B9 M13_DS2_PERR_CNT4_R2 M13_DS2_PERR_CNT4[7:0]

0x100BA M13_DS2_PERR_CNT3_R1 vDS2_PERR_CNT3[12:8]

0x100BB M13_DS2_PERR_CNT3_R2 M13_DS2_PERR_CNT3[7:0]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

237 Lucent Techn olo

ies Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 300. Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x100BC M13_DS2_PERR_CNT2_R1 M13_DS2_PERR_CNT2[12:8]

0x100BD M13_DS2_PERR_CNT2_R2 M13_DS2_PERR_CNT2[7:0]

0x100BE M13_DS2_PERR_CNT1_R1 M13_DS2_PERR_CNT1[12:8]

0x100BF M13_DS2_PERR_CNT1_R2 M13_DS2_PERR_CNT1[7:0]

0x100C0

—

0x100C5

—

0x100C6 M13_DS2_FERR_CNT7_R M13_DS2_FERR_CNT7[7:0]

0x100C7 M13_DS2_FERR_CNT6_R M13_DS2_FERR_CNT6[7:0]

0x100C8 M13_DS2_FERR_CNT5_R M13_DS2_FERR_CNT5[7:0]

0x100C9 M13_DS2_FERR_CNT4_R M13_DS2_FERR_CNT4[7:0]

0x100CA M13_DS2_FERR_CNT3_R M13_DS2_FERR_CNT3[7:0]

0x100CB M13_DS2_FERR_CNT2_R M13_DS2_FERR_CNT2[7:0]

0x100CC M13_DS2_FERR_CNT1_R M13_DS2_FERR_CNT1[7:0]

0x100CD M13_BPV_CNT_R1 M13_BPV_CNT[23:16]

0x100CE M13_BPV_CNT_R2 M13_BPV_CNT[15:8]

0x100CF M13_BPV_CNT_R3 M13_BPV_CNT[7:0]

0x100D0 M13_EXZ_CNT_R1 M13_EXZ_CNT[23:16]

0x100D1 M13_EXZ_CNT_R2 M13_EXZ_CNT[15:8]

0x100D2 M13_EXZ_CNT_R3 M13_EXZ_CNT[7:0]

0x100D3

—

0x100FE

—

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

238Lucent Technologies Inc.

11 M13/M23 MUX/DeM UX Registers (continued)

Table 300. Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TDL Buffer Selection—R/W

0x100FF M13_TDL_BUFFER_R M13_TDL_B

UFFER

TDL Buffers—R/W

When M13_TDL_BUFFER = 0

0x10100

—

0x1013F

M13_TDL_0DATA_R[0—63] M13_TDL_0DATA[0—63][7:0]

When M13_TDL_BUFFER = 1

0x10100

—

0x1013F

M13_TDL_1DATA_R[0—63] M13_TDL_1DATA[0—63][7:0]

0x10140

—

0x101FF

—

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
239Agere Systems Inc.  
12 28-Channel Framer Registers
Ta ble of Conte nts
Contents Page
12 28-Channel Framer Registers ............... .................. . ................ ..................... . ............. . .................................. 239
12.1  Framer Global Register Descriptions  ..................................................................................................... 243
12.2  Arbiter (Framer) Global Registers  ................. ... ......................... . ......................... ....... . ........................... 245
12.3  Performance Monitor Global Registers  ............................ ... ......................... ..... ... .................................. 247
12.4  HDLC Global Configuration and Statu s Regist ers ... .... ............... .... ... .... ..... ... .... ... ........... ... .... ... ..... .... ... . 253
12.5  System Interface Global Registers ......................................................................................................... 257
12.6  Signaling Global Registers  ..................................................................................................................... 262
12.7  Frame Formatter (Transmit Framer) Global Register ............................................................................. 266
12.8  Facility Data Link Global Registers ......................................................................................................... 267
12.9  Super Mapper Framer Per Link Configurat ion and Status R egisters   .... . .................. ................... ........... 26 7
12.9.1 Signal ing Pe r Link Registers  ........ ....... ....... ....... ....... ....... ....... ...... ....... ....... ....... ....... ....... ............. 267
12.10  Performance Monitor Per Link Registers ....... . ........... ................... ............... ........... .............. . ............... 273
12.11  Receive Facility Data Link Configuration and Status Registers  . ..................... ................... .................. 288
12.12  Tran smit Facility Data Link Configuration and Status Registers ..........................................................290
12.13  System  Interface, Arbiter,  and Fram e Formatter Mapping ................................................................... 292
12.14  System  Interface Per Link Registers .................................................................................................... 293
12.15  Arbiter Framer Per Link Registers ........................................................................................................ 295
12.16  Frame Formatte r Per Link  Registers .................................................................................................... 300
12.17  Line Decoder/Encoder P er Link Registers  ......... ...................................... .......................... ... ............... 302
12.18  Line Encode r/Decoder P er Link Registers  ..................... ... ......................... . ......................... ................ 303
12.19  HDLC Per Channel Configuration and  Status Registers .............. ..................... . .................. ..... ... ........ 304
12.20  28-Channel Framer Bloc k Register Map   .............. . ....................... ... ....................... ... ........................... 311
Tables Page
Table 301. FRM_SF GR1, Superframer G lobal Registe r 1 (R/W) ........................................................................ 243
Table 302. FRM_SF GR2, Superframer G lobal Registe r 2 (R/W) ........................................................................ 244
Table 303. FRM_SF GR3, Superframer G lobal Registe r 3 (RO) ......................................................................... 245
Table 304.  F RM_SF GS R4,  Superf ram er G lobal  Register 4 (R/W) .. .................. ..................... ........................ ....245
Table 305. FRM_FGR1 , Framer G lobal Re gister 1 (R/W)  .................................................................................. 245
Table 306. FRM_FGR2 , Framer G lobal Re gister 2 (R/W)  .................................................................................. 246
Table 307. FRM_FGR3 , Framer G lobal Re gister 3 (R/W)  .................................................................................. 246
Table 308. FRM_FGR4 , Framer G lobal Re gister 4 (COR)  .................................................................................246
Table 309. FRM_FGR5 , Framer G lobal Re gister 5 (COR)  .................................................................................247
Table 310.  F RM_PM GR1_B, Performance Monitor Global Register 1_B (R/W)  .... ..................... . ............. ......... 247
Table 3 11.  FRM_PM GR1, Performance Monitor Global Register 1 (COR) ................... ... .................. . ............... 2 47
Table 3 12.  FRM_PM GR2, Performance Monitor Global Register 2 (COR) ................... ... .................. . ............... 2 48
Table 3 13.  FRM_PM GR3, Performance Monitor Global Register 3 (R/W) ............. ..................... . ......................2 48
Table 3 14.  FRM_PM GR4, Performance Monitor Global Register 4 (R/W) ............. ..................... . ......................2 49
Table 3 15. FR M_PMGR5, Performance Monitor Global Register 5—PMGR5 (R/W ) . .............. ..........................249
Table 3 16.  FRM_PM GR6, Performance Monitor Global Register 6 (R/W) ............. ..................... . ......................2 49
Table 3 17.  FRM_PM GR7, Performance Monitor Global Register 7 (R/W) ............. ..................... . ......................2 49
Table 3 18.  FRM_PM GR8, Performance Monitor Global Register 8 (R/W) ............. ..................... . ......................2 50
Table 3 19.  FRM_PM GR9, Performance Monitor Global Register 9 (R/W) ............. ..................... . ......................2 50
Table 3 20.  FRM_PM GR10, Performance Monitor Global Register 10 (R/W) .................. . ....................... ........... 250
Table 3 21.  FRM_PM GR11, Performance Monitor Global Register 11 (R/W) .................. . ....................... ........... 250
Table 3 22.  FRM_PM GR12, Performance Monitor Global Register 12 (R/W) .................. . ....................... ........... 251
Table 3 23.  FRM_PM GR13, Performance Monitor Global Register 13 (R/W) .................. . ....................... ........... 251
Table 3 24. FR M_PMGR14, Performance Monitor Global Register 14 (R/W)  .... . .................... . ........................... 252

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
240 Agere Sy stem s Inc.
 
12 28-Channel Framer Registers (continued)
Table of Conten ts (continued)
Tables Page
Table 3 25.  FRM_PM GR15, Performance Monitor Global Register 15 (R/W) ............ . .................. ..... ................. 252
Table 3 26.  FRM_PM GR16, Performance Monitor Global Register 16 (R/W) ............ . .................. ..... ................. 252
Table 327. FRM_HGR1, Transmit HDLC Glo bal Register 1 (R/W) .....................................................................253
Table 328. FRM_HGR2, Transmit HDLC Glo bal Register 2 (R/W) .....................................................................253
Table 329. FRM_HGR3, Transmit HDLC Glo bal Register 3 (R/W) .....................................................................253
Table 330. FRM_HGR4, Transmit HDLC Glo bal Register 4 (R/W) .....................................................................253
Table 331. FRM_HGR5, Transmit HDLC Glo bal Register 5 (R/W) .....................................................................254
Table 332. FRM_HGR6, Transmit HDLC Glo bal Register 6 (R/W) .....................................................................254
Table 333. FRM_HGR7, Transmit HDLC Glo bal Register 7 (R/W) .....................................................................254
Table 334. FRM_HGR8, Transmit HDLC Glo bal Register 8 (R/W) .....................................................................254
Table 335. FRM_HGR9, Transmit HDLC Glo bal Register 9 (R/W) .....................................................................254
Table 336.  F RM_HGR10, Tr ansm it HDLC Gl obal Register 10 (R/W) ...................... ................... ...................... .. 255
Table 337.  F RM_HGR11, T ransm it HDLC Global Register 11 (RO)  .... ................... ................... ...................... .. 2 55
Table 338.  F RM_HGR12, Tr ansm it HDLC Gl obal Register 12 (R/W) ...................... ................... ...................... .. 255
Table 339.  F RM_HGR13, Tr ansm it HDLC Gl obal Register 13 (R/W) ...................... ................... ...................... .. 255
Table 340.  F RM_HGR14, Tr ansm it HDLC Gl obal Register 14 (R/W) ...................... ................... ...................... .. 255
Table 341. FRM_HGR15, R eceive H DLC Global Register 15 (R/W) .................................................................. 255
Table 342. FRM_HGR16, R eceive H DLC Global Register 16 (R/W) .................................................................. 256
Table 343. FRM_HGR17, R eceive H DLC Global Register 17 (R/W) .................................................................. 256
Table 344. FRM_HGR18, R eceive H DLC Global Register 18 (R/W) .................................................................. 256
Table 345. FRM_HGR19, R eceive H DLC Global Register 19 (R/W) .................................................................. 256
Table 346. FRM_HGR20, R eceive H DLC Global Register 20 (R/W) .................................................................. 256
Table 347. FRM_SYSGR1, System Interface Glob al Register 1 (R/W) .............................................................. 257
Table 348. FRM_SYSGR2, System Interface Glob al Register 2 (R/W) .............................................................. 258
Table 349. FRM_SYSGR3, System Interface Glob al Register 3 (R/W) .............................................................. 259
Table 350. FRM_SYSGR4, System Interface Glob al Register 4 (R/W) .............................................................. 259
Table 351. FRM_SYSGR5, System Interface Glob al Register 5 (R/W) .............................................................. 259
Table 352. FRM_SYSGR6, System Interface Glob al Register 6 (COR) ............................................................. 259
Table 353. FRM_SYSGR7, System Interface Glob al Register 7 (COR) ............................................................. 260
Table 354. FRM_SYSGR8, System Interface Glob al Register 8 (R/W) .............................................................. 260
Table 355. FRM_SYSGR9, System Interface Glob al Register 9 (R/W) .............................................................. 260
Table 356.  FRM_SYSGR10—FRM_SYSGR14, System Interface Global Register 10—14 (R/W) .................... 261
Ta ble  357. FRM_SYSGR 1 5,  System Int erface Gl obal Regi ste r 15 (COR)  ......................................................... 261
Ta ble  358. FRM_SYSGR 1 6,  System Int erface Gl obal Regi ste r 16 (R/W) .......................................................... 261
Table 3 59. FR M_SGR1, Receiv e S ignaling Global Register 1 (R/W) .... .................. ... ....................... .................262
Table 3 60. FR M_SGR2, Receiv e S ignaling Global Register 2 (R/W) .... .................. ... ....................... .................262
Table 3 61. FR M_SGR3, Receiv e S ignaling Global Register 3 (R/W) .... .................. ... ....................... .................263
Table 3 62. FR M_SGR4, Receiv e Signaling Global Register 4 (RO ) .......................... . ................................... ... .. 263
Table 3 63. FR M_SGR5, Receiv e Signaling Global Register 5 (RO ) .......................... . ................................... ... .. 263
Table 364. FRM_SGR6, Receive Signaling Global Register 6   ....... . ................................... ... ............................ 264
Table 3 65. FR M_SGR7, Receiv e S ignaling Global Register 7 (R/W) .... .................. ... ....................... .................264
Table 366.  F RM_SGR8, Tran smit Signali ng Globa l Registe r 8 (R/W) ......... ........................ ..................... ..........265
Table 367. FRM_FFG R1, Transmit Framer Global Register 1 (R/W ) ................................................................. 266
Table 3 68. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W) ................................................ 267
Table 369.  FRM_FDLG R2, Transmit Facility Data Link Global Register 2 (R/W) ............ ......... ............ ............ .. 267
Table 3 70. Receive Path Signaling Register Addressing Map ............................................................................ 267
Table 371. Receive Path Signaling Registers Addres s Index ing  ................. ....... . ......................... ....... . .............. 267
Table 372. FRM_RSLR0—FRM_RSLR31, Receiv e Signali ng Link Registers 0—31 (R/W) ............... ................ 268
Table 3 73. FRM_RSLR32, Receive Signaling Link Register 32 (COR) ................... ..................... ..... ................. 269

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
241Agere Systems Inc.  
12 28-Channel Framer Registers (continued)
Table o f Conten ts (continued)
Tables Page
Table 3 74. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) ..................... . ....................... .................. 269
Table 375. Transmit Path Signaling Register A ddres s ing Map . ......................... ....... ..... ... .................................. 270
Table 376. Transmit Path Signaling Registers  Address  Indexing .......... ....... .......... ... ................................ ......... 270
Table 377. FRM_TSLR0—FRM _T SLR 31, Transmit Signaling L ink Registers 0—31 (R/W)  ..............................271
Table 3 78.  FRM_TSLR32, T r ans mit Signaling Link Regist er 32 (R/W)  .................... . .................. ..... ..................272
Table 3 79.  FRM_TSLR33, T r ans mit Signaling Link Regist er 33 (CO R) . .................. ..... .......................... ........... 273
Table 380. Performance Monitor Per Link  R egister Addressing Map  ............................ ... .................................. 273
Table 381. Performance Monitor Per Link  R egister Address Indexing .......... ................... . .............................. .... 274
Table 382.   FRM_PMLR1,  P erformance Moni tor Link Register 1 (R/W) ................ ........... . ............ .............. ........274
Table 383.   FRM_PMLR2,  P erformance Moni tor Link Register 2 (R/W) ................ ........... . ............ .............. ........274
Table 384.   FRM_PMLR3,  P erformance Moni tor Link Register 3 (R/W) ................ ........... . ............ .............. ........275
Ta ble  385 . FR M _P MLR 4,  Pe rfo r man ce  M on itor  L i nk  Register 4 (COR)  ........ . ........... . ............. . ........... . ........... . .. 27 5
Ta ble  386 . FR M _P MLR 5,  Pe rfo r man ce  M on itor  L i nk  Register 5 (COR)  ........ . ........... . ............. . ........... . ........... . .. 28 2
Ta ble  387 . FR M _P MLR 6,  Pe rfo r man ce  M on itor  L i nk  Register 6 (COR)  ........ . ........... . ............. . ........... . ........... . .. 28 4
Ta ble  388 . FR M _P MLR 7,  Pe rfo r man ce  M on itor  L i nk  Register 7 (COR)  ........ . ........... . ............. . ........... . ........... . .. 28 4
Ta ble  389 . FR M _P MLR 8,  Pe rfo r man ce  M on itor  L i nk  Register 8 (COR)  ........ . ........... . ............. . ........... . ........... . .. 28 5
Ta ble  390 . FR M _P MLR 9,  Pe rfo r man ce  M on itor  L i nk  Register 9 (COR)  ........ . ........... . ............. . ........... . ........... . .. 28 5
Tab le 391. FRM_PMLR10, Performance Monitor Link Register 10 (COR) ......................................................... 285
Tab le 392. FRM_PMLR11, Performance Monitor Link Register 11 (COR) ......................................................... 285
Tab le 393. FRM_PMLR12, Performance Monitor Link Register 12 (COR) ......................................................... 285
Tab le 394. FRM_PMLR13, Performance Monitor Link Register 13 (COR) ......................................................... 286
Tab le 395. FRM_PMLR14, Performance Monitor Link Register 14 (COR). ........................................................287
Tab le 396. FRM_PMLR15, Performance Monitor Link Register 15 (COR) ......................................................... 287
Tab le 397. FRM_PMLR16, Performance Monitor Link Register 16 (COR) ......................................................... 287
Tab le 398. FRM_PMLR17, Performance Monitor Link Register 17 (COR) ......................................................... 287
Tab le 399. FRM_PMLR18, Performance Monitor Link Register 18 (COR) ......................................................... 287
Tab le 400. FRM_PMLR19, Performance Monitor Link Register 19 (COR) ......................................................... 288
Tab le 401. FRM_PMLR20, Performance Monitor Link Register 20 (COR) ......................................................... 288
Table 402. Re cei ve Facility Data Link Re gist e r  Addr e ssing Map ....................... ................. ............ .................... 288
Table 403. Receive Path F ac ility D ata Link Registers A ddress Indexing ................ ... ......................... ....... . ........ 289
Table 4 04. FR M_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1—5 (RO)  ................................... 2 89
Table 4 05. FRM_RFDLLR6 , Receive FDL Link Register 6 (R/W) ....................................................................... 289
Table 4 06. FRM_RFDLLR7, Receive FDL Link Reg ister 7 (R O) ........................................................................ 289
Table 4 07. FRM_RFDLLR8, Receive FDL Link Reg ister 8 (COR) ......................................................................290
Table 4 08. FRM_RFDLLR9 , Receive FDL Link Register 9 (R/W) ....................................................................... 290
Table 409. Transmit Facility Data Link Register Addressing Map ............................. ..... ... ......................... ......... 290
Table 410.  T rans mit Path Facility Data Link Registers A ddress  Index in g ...................... ..................... . ............... 290
Table 4 11.  FRM_TFDLLR1—FRM_TFDLR5,   Transmit FDL Link Registers 1—5  (COR )  .... .. ... ..... .. .. ... .... ... .. ... .. 290
Table 412. FRM_TFDL LR6, Transmit FDL Link Register 6 (R/W) ...................................................................... 291
Table 413. FRM_TFDL LR7, Transmit FDL Link Register 7 (R/W) ...................................................................... 291
Table 414. FRM_TFDL LR8, Transmi t FDL Link Register 8 (RO/CO W) ..............................................................292
Table 415. FRM_TFDL LR9, Transmit FDL Link Register 9 (R/W) ...................................................................... 292
Table 416. S y s tem Interface, Arbiter, and Frame Formatter Link Register Addressing Map .............................. 292
Table 417. S y s tem Interface, Arbiter, and Frame Formatter Link Register Address Indexing  ............ ....... ......... 293
Tab le 418. FRM_SYSLR1, System Interface Link Registe r 1 (R/W) ................................................................... 293
Tab le 419. FRM_SYSLR2, System Interface Link Registe r 2 (R/W) ................................................................... 294
Table 420.  FRM_SYSLR3—FRM_SYSLR6 , Sys te m Inte r face Link Reg isters 3—6 (R/W) ................................294
Table 421. FRM_ARLR 1, Arbiter Link Regi ster 1 (R/W) ..................................................................................... 295
Table 422. FRM_ARLR 2, Arbiter Link Regi ster 2 (R/W) ..................................................................................... 296

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
242 Agere Sy stem s Inc.
 
12 28-Channel Framer Registers (continued)
Table of Conten ts (continued)
Tables Page
Table 423. FRM_ARLR 3, Arbiter Link Regi ster 3 (R/W) ..................................................................................... 299
Table 424.   FRM_FFLR1, Frame Formatter Link Register 1 (R/W) .............. . ............................ ........... . ........... . .. 300
Table 425.   FRM_FFLR2, Frame Formatter Link Register 2 (R/W) .............. . ............................ ........... . ........... . .. 301
Table 4 26. Line Decoder Per LIn k Register Addressing Map ............................................................................. 302
Table 427. Li ne Decoder P er Link  R egisters Address Indexing .......................... . ................................ . .............. 302
Table 428. Line Encoder Per Link Register Addressing Map .............................................................................. 302
Table 429.  Li ne E ncoder Per Link Registers Address I ndexing . ......................... .......................... ...................... 302
Table 430.  F RM_L DLR1,  Li ne Decoder L ink Register 1 (R/W ) ............. ................... ...................... ..................... 303
Table 4 31. FRM_LDLR2,  Line Encoder Link Register 2 (R/W) ........................................................................... 303
Table 4 32.   HDLC P er Channel Regis ter Addressing Map   .. ................... .................. ................... ........................ 304
Table 433.  F RM_H CR1, Transmit HDLC Channel Register 1 (R/ W) ................................... ................. .............. 3 04
Table 434.  F RM_H CR2, Transmit HDLC Channel Register 2 (R/ W) ................................... ................. .............. 3 04
Table 435.  F RM_H CR3, Transmit HDLC Channel Register 3 (R/ W) ................................... ................. .............. 3 05
Table 436.  F RM_H CR4, Transmit HDLC Channel Register 4 (RO) .............. ............. .................... ................ ..... 306
Table 437.  F RM_H CR5, Transmit HDLC Channel Register 5 (R/ W) ................................... ................. .............. 3 06
Table 438.  F RM_HCR6, Tran smit HDLC Channel Register 6 (WO) ................. ...................... ........... ................. 3 07
Table 439.  F RM_H CR7, Transmit HDLC Channel Register 7 (RO) .............. ............. .................... ................ ..... 307
Table 440.   FRM_HCR8, Receive HDLC Channel Register 8 (R/W) ............... ........... . ........... . .............. ........... . .. 307
Table 441.   FRM_HCR9, Receive HDLC Channel Register 9 (R/W) ............... ........... . ........... . .............. ........... . .. 307
Table 442.  F RM_H CR10,  Recei ve  HDLC Channel Register 10 (R/W) ................................................. ........... ... 308
Table 443.  F RM_H CR11,  Recei ve  HDLC Channel Register 11 (R O) ................................................... ........... ... 3 08
Table 444.  F RM_H CR12,  Recei ve  HDLC Channel Register 12 (R/W) ................................................. ........... ... 309
Table 445.  F RM_H CR13,  Recei ve  HDLC Channel Register 13 (R O) ................................................... ........... ... 3 10
Tab le 446. FRM_HGR14,   Rec e iv e HDLC  Channel Register 14 (COR )  . ....... .......................... .......................... .. 310
Table 4 47. Framer Register Map ......................................................................................................................... 311

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

243Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.1 Fra m er Gl oba l Register D e scription s

Table 301. FRM_SFGR1, Superframer Global Register 1 (R/W)

Address Bit Name Function Reset Default

0x80000 15 FRM_SW_TRN Superframer Configuration Modes.

0 = Transport mode.

1 = Switching mode.

14:13 FRM_LC_

CNTRL[1:0] Line Enc oder/Decoder Control.

00 = Line encoder and line decoder blocks are not used in

either the fra mer Tx or Rx paths. This s etting i s used in the

follow ing switching modes:

■STS-3/STS-1/DS3/DS2 to CHI/parallel system bus/SMI.

■STS-3/ STS-1/DS3 to line data rate mode.

01 = Line decoder is used in the R x path and line encoder is

used in the Tx path. This setting is used in the framer-only

switching modes:

■DS1 to CHI/parallel system bus/SMI channelized.

10 = Line decoder is used in the Tx path and line encoder is

used in the Rx path. This setting is used in the following

transport m odes:

■DS1 to DS2/DS3/STS-1/STS -3.

11 = Re served.

12 FRM_LOOP_

TIMING Loop Timing.

0 = Superframer is programmed for normal mode.

1 = Superframer is programmed f or loop timing; i.e., all receiv ed

line clocks are looped back to the corresponding transmit

line clocks.

11 FRM_DS1_

CEPTN DS1/C EPT Terminal Count.

0 = Superframer is programmed for CEPT mode, which has a

maximum of 21 operational links. Links 22 to 28 are

disabled.

1 = Superframer is programmed for DS1 mode, which has a

maximum of 28 operational links.

Note: For fewer links or DS 1/CEPT mixed modes, use

FRM_TC_ EN and FRM_TC [7:0] ( Table 306) parame-

ters to select an accurate link count.

10 FRM_PLL_

BYPAS PLL Bypass.

0 = Internal P LL is used to generate the line clock in the

transmi t path.

1 = The PLL is bypassed. External line clock is required in this

mode.

9:1 —Reserved. Must wr ite to 0. 0

0 FRM_LG_BUF_

MODE HDLC Buffer M ode.

0 = HDLC channel buffers are configured for 128-byte storage.

Up to 64 (32) channels can be supported in the switching

(transport) mode.

1 = HDLC channel buffers are combined for 512-byte storage.

Up to 16 (8) channels can be supported in the switching

(transport) mode.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

244 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 302. FRM_SFGR2, Superframer Global Register 2 (R/W)

Address Bi t Name Function Reset

Default

0x80001 15:14 —Reserved. M ust write to 0. 0

13 FRM_TP_SIG_PWDN Transmit Path Receive Signaling Powerdown . When set

to 0 , the transmit path receive signaling block for th e trans -

port mode is p owered down.

12 FRM_RP_SIG_PWDN Receive Path Transmit Signal ing Powerdown. When set

to 0, the receive path transmit signaling block for the trans-

port mode is p owered down.

11 FRM_TP_RDL_PWDN Transmit Path Receive Datalink P owerdown. W hen set to

0, the tra n smit path receive data link block for the transport

mode is powered down.

10 FRM_RP_TDL_PWDN Rece ive Path Tran sm it Datalink Powerdown. When set to

0, the receive path transmit data link block for the transport

mode is powered down.

9 FRM_TP_RH_PWDN Transmit Path Receive HDLC Powerdown. When set to 0,

the transmit path receiv e HDLC block f or the tr ansport mode

is powered down.

8 FRM_RP_TH_PWDN Receive Path Tra nsm it HDLC Powerdown. When set to 0,

the receiv e path transmit HDLC blo ck for the transport mode

is powered down.

7 FRM_TS_PWDN Transm it Path Sy stem Bl ock Pow erdown. When set to 0,

the transmit path system block is powered down. 1

6 FRM_RS_PWDN Receive Path System Block Pow erdown. When set to 0,

the receive path system block is powered down. 1

5 FRM_TP_PM_PWDN Tran smit Pat h Performance Monit or Powerdown. Wh en

set t o 0, the transmit path performance monitor block is pow-

ered down.

4 FRM_RP_FF_PWDN Rece ive Path Frame Formatter Powerdow n. When set to

0, the receive pa th frame formatter block is powered down. 1

3 FRM_TP_RA_PWDN Transmit Path Receive Aligner Powerdown. When set to

0, the transmit path receive align er block is powered down. 1

2:0 —Reserved. Must write to 0. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

245Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 303. FRM_SFGR3, Superframer Global Register 3 (RO)

Table 304. FRM_SF GS R4, Sup erfram er Global Register 4 (R/W)

12.2 Arbiter (Framer ) Globa l Registers

Table 305. FRM_FGR1, Framer Global Register 1 (R/W)

Address Bit Name Fun ction Reset

Default

0x80002 15 FRM_RP_SIG A 1 indicates the change of signaling state FIFO contains

state change information. 0

14 FRM_AR _IS A 1 indicat es the FRM _A R_I S block has generat ed a n

interrupt. 0

13 FRM_TP_RDL_IS A 1 indicates the FRM_TP_RDL_IS block has generated

an interrupt. 0

12 FR M_TP_TDL_IS A 1 indicates the FRM_TP_TDL_IS block has generated

an interrupt. 0

11 FRM _RH_IS A 1 indicates t he FRM _RH_IS block has generated an

interrupt. 0

10 FRM_TH_I S A 1 i ndicates the FRM _TH _IS block has generated an

interrupt 0

9 F RM_ TS_I S A 1 indicat es t he FRM_TS _IS block h as generated an

interrupt. 0

8 FRM_RS _I S A 1 indicat es t he FRM_RS _I S block has generated a n

interrupt. 0

7 FRM_TP_P M _IS A 1 i ndicates t he FRM_TP_P M _I S block has generat ed

an interrupt. 0

6 F RM_ RP_ PM_I S A 1 i ndicates t he FRM_RP _P M _IS block has generated

an interrupt. 0

5 FRM_RP_RDL_IS A 1 indicates the FRM_RP_RDL_IS b lock has generated

an interrupt. 0

4 FRM_RP_TDL_IS A 1 indicates the FRM_RP_TDL_IS block has generated

an interrupt. 0

3:0 —Reserved. Reads 0. 0

Address Bit Name Fun ction Reset

Default

0x80003 15 —Reserved. Must wr ite to 0. 0

14:12 FRM_VERSION[2:0] Superframer Version Number. 000

11:0 —Reserved. Must write to 0. 0x000

Address Bit Name Function Reset

Default

0x80010 15:8 —Reserved. Must write to 0. 000000000

7:0 FRM_TO[7:0] Time-Out Count. The number of frames to wait before

declaring a time out. See FRM_OPT[1:0] ( Table 422). T he

default is 40 fram es (5 ms).

00101000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

246 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 306. FRM_FGR2, Frame r Glo bal Register 2 (R/W)

Table 307. FRM_FGR3, Frame r G lobal Register 3 (R/W)

Table 308. FRM_FGR4, Frame r G lobal Register 4 (COR)

Address Bit N am e Function Reset

Default

0x80011 15 FRM_TC_EN Terminal Count Enable.

0 = Terminal count disabled use defaults.

1 = Terminal count enabled.

14:8 —Reserved. Must write to 0. 0000000

7:0 FRM_TC[7:0] Terminal Count. When enabled, the link counter will count

from 1 to the terminal count. The terminal count determines

the number of links a vailab le for use. The operational links are

link 1 to the l ink determined by the terminal count. By default ,

the count is determined by the option bit, FRM _DS1_CEPTN

(Table 301). In an applica tio n , where there is a mix of DS1

and CEPT links or a small number of l inks, the te r minal count

may be set by enabling FRM_T C_EN and setting the terminal

count, FRM_TC[7:0].

00000000

Address Bit Nam e Fu nction Reset

Default

0x80012 15 FRM_TPSSE_IM T ransmit P ath System Synchronization Error Interrupt

Mask. A tra ns mi t pat h syst e m synch ro niza tion error inter-

rupt is generated when synchronizat ion is lost between

the receive syst em interfac e and the transm it path line

c lock. FRM_TP SSE_ IM is a global mask for the interrupt

status from each link. T he individual link tr ansmit path

system error interrupt st atus bits, FRM_TPSSEI[28:1] are

summarized in FRM_AR_IS bit 14 of FRM_SFGR3

(Table 303).

0 = Allows any synchronization error, as report ed in the

synchronization status r egisters, to generate a n interrupt.

1 = Masks any synchronization error , as reported in the

synchronization s tatus registers, from generating an inter-

rupt.

14:0 —Reserved. Must write to 0. 000000000

000000

Address Bit Name Function Reset

Default

0x80014 15:0 FRM_TPSSEI[16:1] Transmit Path System Synchronization Error Inter-

rupt.

1 = Indicates a transmit path system synchronization

error on links 16 to 1.

00X0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

247Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 309. FR M_F GR5, Frame r G lobal Register 5 (COR)

12.3 Performance Monitor Global Registers

Table 310. FR M_PMGR1_ B, Performance Monitor Global Register 1_B (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 11. FRM_PMGR1, Performance Monitor Global Register 1 (COR)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address Bit Name Function Reset

Default

0x80015 15:12 —Reserved. Must write to 0. 000

11:0 FRM_TPSSEI[28:17] Transmit Path System Synchronization Error Inter-

rupt.

1 = Indicates a transmit path system sync hronization

error on links 28 t o 1 7.

000000000

000

Address*Bit Nam e Function Reset

Default

0x80P20 15 FRM_SEC_SEL Framer PMRESET Source. The source of the performance

monitoring interval (generally one second) may be select ed to

be inter nal to the framer block or external to the framer block.

0 = Exter nal.

1 = Int ernal.

14:13 —Reserved. Must write to 0. 000

12:0 FRM_CT125[12:0] Framer Terminal Count. This is the terminal count for an inter-

nal 125 µs timer th at is multipl ied by 8000 to determ ine the int er-

nal performance monitoring interval. This count is based on the

T DM cl oc k s peed. The default count is b ased on a 51.84 MHz

clock. This terminal count i s calculated by the following equa-

tion.

Timer term inal count = (125 µs)(fTDM clock).

0x1950

Address*Bit Name Function Reset

Default

0x80P30 15:2 —Reserved. Must write to 0. 0x0000

1 FRM_DETECT Test-Pattern Detect. A 1 indicates the pattern detector has

locked onto the pattern specified by the FRM _PTR N _SEL[3:0]

(Table 324) configuration bits. There is only one test-pattern

detector. S ee O.151 Section 2. Both framed and unframed test-

pattern generation/detection are supp orted.

0 FRM_PTRNBER Test-Pattern Bit Error. A 1 i ndicates the rec eive framer pattern

detector has found one or more sing le-bit errors in the pattern

that it is currently locked on t o. There is only one te st-pattern

BER counter for all links.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

248 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 3 12. FR M_PM GR2, Performance Monitor Global Reg ister 2 (COR)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 13. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)

* P = 0x 0 for th e rec eive pat h, an d P = 0x 1 for the tr an sm it pa th.

†FRM_RACF RM_ RDC Standard.

Address*Bit Name Function Reset

Default

0x80P31 15:0 FRM_TPERR_CT[15:0] Test Pattern Error Count R egister. This regi ster con-

tains the 16-bit count of test-pattern errors. 0

Address*Bit Name Fu nction Reset

Default

0x80P32 15:14 —Reserved. Must write to 0. 00

13:11 FRM_RAC[2:0] CEPT Mode RAI Activation Count†. 001

10:8 FRM_RDC[2:0] CEPT Mode RAI Deactivation Count†. RAC and RDC

can be set to mee t various standards. 001

7 FRM_FSFBEEN FS Frame Bit E rror Enable. Allows a signaling frame (FS)

bit error to set the FBE status bit, FRM_FBE (Table 386).

In DDS, a 0 means do not count TS24 framing and FS as

FB Es; a 1 means count TS24 framing and Fs as FB Es.

0 = FS bit errors disabled.

1 = FS bit errors enabled.

6FRM_CMFRFENCEPT Multiframe Reframe Enable.

0 = CEPT CRC-4 multiframe reframe disabled.

1 = CEPT CRC-4 multiframe reframe enabled. A research

for multiframe alignment is initiated upon a loss of CEPT

CRC-4 mult ifram e alignment.

5 FRM_CRCRFEN CRC Reframe Enable.

0 = CRC errors do not cause a reframe or LOF conditi on.

1 = The receive performance monitor will force a reframe

an d LOF condition on excessi ve CRC errors.

4:3 FRM_CEPTAISM[1:0] CEPT AIS Mode.

00 = Option 0: G.775 section I.2; G.965 section 16.1. 2.

01 = Option 1: G.775 section 5.2.

10 = Option 2: G.775 section I.2.

11 = Option 3: G.775 section I.2.

2 FRM_DS1AISM DS1 AIS Mode.

0 = Option 0: T1.231 section 6.1.2.2.3, T 1.403 section H,

G.775 section 5.4.

1 = Option 1: G.775 section I.2.

1 FRM_ESFRAIM ESF RAI Mode.

0 = Alternating eight ones followed by eight zer os.

1 = All ones.

0 FRM_RAICLR Clear RAI on Reception of DS1 Idle Signal.

0 = Ignore DS1 idle signal for RAI clearing.

1 = Clear failure on reception of DS1 idle signal:

ANSI

T1.231 se ction 6. 2.2.2.1.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

249Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 3 14. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 15. FRM_PMGR5, Performan ce Monitor Global Register 5—PMGR5 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 16. FRM_PMGR6, Performance Monitor Global Register 6 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 17. FRM_PMGR7, Performance Monitor Global Register 7 (R/W)

These bit s enable the errored events used to determ ine errored and severely errored seconds in the D S1 modes.

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name F unction Reset

Default

0x80P33 15:0 FRM_SFSEST[15:0] SF Severely Errored Second Threshold for All SF Format-

ted Channels.

Note: A burs t y errored second wi ll be recorded if the number

of events is greater than the errored second threshold

but less than the severely errored second threshold.

There is a separate threshold for ESF and SF because

of t he bi t e rror prov ision in g in ESF (Ft or Fs).

0x0140

Address*Bit Nam e Function Reset

Default

0x80P34 15:0 FRM_DCT[15:0] DS1 Excessive CRC Threshold—Default 320. This register

sets the one second CRC threshold at which an excessive CRC

error condition is reported and the one second CRC threshold at

which a reframe may be forced.

0x0140

Address*Bit Name Fu nction Reset

Default

0x80P35 15:0 FRM_ESFSEST[15:0] ESF Severely Errored Second Threshold fo r All ESF

Formatted Channels. A bursty erro red second will be

recorded if t he number o f event s is greater than the errored

second threshold but less than the severely errored second

threshold.

0x0140

Address*B it N am e Fun ctio n R eset

Default

0x80P36 15:9 —Reserved. Must write to 0. 0x00

8FRM_DSEFDS1 Severely Errored Frame E nable. See FRM_SEFS (Table 400). 0

7FRM_DLFADS1 Loss of Fram e Alignment Enable. 0

6 FRM_DRFA DS1 Remote Frame Alarm Enable. 0

5FRM_DSLIPDS1 Slip Enable. 0

4 FRM_DLOS DS1 Lo ss of Signal Ena ble. 0

3FRM_DAISDS 1 Alarm Indication Signal Enable. 0

2 FRM_DCRC DS1 CRC-6 Error Enable. 0

1FRM_DFSDS1 Fs F raming Bit Error En able (SF Only). 0

0FRM_DFTDS1 Ft Fram ing Bit Error Ena ble (SF and ESF). 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

250 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 3 18. FR M_PM GR8, Performance Monitor Global Reg ister 8 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 19. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 20. FRM_PMGR10, Perform ance Monitor Global Register 10 (R/W)

These bits enab le the errored events used to determi ne errored and severely errore d seconds in the CEPT modes.

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 21. FRM_PMGR11, Perform ance Monitor Global Register 11 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name Function Reset

Default

0x80P37 15:0 FRM_CCT[15:0] CEPT Excessive CRC Threshold—Default 915. This register

sets the one second CRC threshold at which an excessive CRC

error condition is reported and the one second CRC threshold at

which a reframe may be forced.

0x0393

Address*Bit N am e Fu nction Reset

Default

0x80P38 15:0 FRM_CSEST[15:0] CEPT Severely Errored Second Threshold for All CEPT

Formatte d Ch anne l s. 0x0000

Address*Bit Name F unction Reset

Default

0x80P39 15 FRM_CSA6_F CEPT Sa6 = F Enable and Sa5 = 1. (Reception of AIS.) 1

14 FRM_CSA6_E CEPT Sa6 = E Enable and Sa5 = 1. (FC3 and FC4.) 1

13 FRM_CSA6_C CEPT Sa6 = C Enable and Sa5 = 1. (LOS/LFA.) 1

12 FRM_CSA6_8 CEPT Sa6 = 8 Enable an d Sa5 = 1. (Loss of power.) 1

11 FRM_CSA6_1X CEPT Sa6 = 001x Ev ent Enable. 1

10 FRM_CSA6_X1 CEPT Sa6 = 00x1 Event Enable. 1

9FRM_CEBITCEPT E bit = 0 Event Enable . 1

8 FRM_CLMFA CEPT Loss of Multiframe Alignment Enable. 1

7 FRM_CLFA CEPT Loss of Frame Alignment Enable. 1

6 FRM_CRFA CEPT Remote Frame Alarm Enable. 1

5FRM_CSLIPCEPT Slip Enable. 1

4FRM_CLOSCEPT Loss of Signal Enable. 1

3FRM_CAISCEPT Alarm Indication Signal Enable. 1

2 FRM_CCRC CEPT CRC-4 Error Enabl e. 1

1 FRM_CNOTFAS CEPT Non-FAS Bit Error Enable. 1

0FRM_CFASCEPT FAS Bit Error Enable. 1

Address*Bit Name Function Reset

Default

0x80P3A 15:0 FRM_CRET[15:0] Co ntinuous Re ce ived E- B i t Th resh old—Default 9 9 1. This

ting the CRE b it status indication.

0x03DF

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

251Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 3 22. FRM_PMGR12, Performance Monitor Global Regist er 12 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 23. FRM_PMGR13, Perform ance Monitor Global Register 13 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name Function R eset

Default

0x80P3B 15 FRM_CRAI_AIS Send RAI Upon Detection of AIS Enable in CEPT Mode. 0

14 FRM_CRAI_OOF Send RAI Upon Detection of OOF Enable in CEPT Mode. 0

13 FRM_CRAI_LOS Send RAI Upon Detection of LOS Enable in CEPT Mode. 0

12 FRM_CRAI_SA6EQC Send RAI Upon Detection of Sa6 = (0xC) Enable in CEPT

Mode. 0

11 FRM_CRAI_SA6EQ8 Send RAI Upon Detection of Sa6 = (0x8) Enable in CEPT

Mode. 0

10 FRM_CRAI_CRCTX Send RAI Upon Detection of CRCTX Enable in CEPT

Mode. 0

9 FRM_CRAI_LTS0MFA Send RAI Upon Detection of LTS0MFA Enable in CEPT

Mode. 0

8 FRM_CRAI_LTS16MFA Send RAI Upon Det ection o f LTS16MFA Enable in CEPT

Mode. 0

7 FRM_CRAI_8MSEX Send RAI Upon Detection of 8 ms Timer Expiration

Enable in CEPT Mode. 0

6:3 —Reserved. Must write to 0. 0

2 FRM_DSRAI_LOS Send RAI Upon Detection of LOS Enable in DS1 Mode. 0

1 FRM_DSRAI_OOF Send RAI Upon Detection of OOF Enable in DS1 Mode. 0

0 FRM_DSRAI_AIS Send RAI Upon Detection of AIS Enable in DS1 Mode. 0

Address* Bi t Name Fun ction Res et

Default

0x80P3C 15:4 —Reserved. Must write to 0. 0x000

3 FRM_CFBE_MODE CEPT FBE Mode.

0 = Count onl y FBEs received in FAS frame.

1 = Count F BEs received in both FAS and NOTFAS

frames.

2 FRM_CEBIT_LTS0MFA Set E Bits Upon Detection of LTS0MFA Enable (CEPT

Only). 0

1 FRM_CEBIT_ESMF Set E B its Upon Detecti o n of an Erro re d CEPT _CRC4

SMF (Submultiframe) Enable. 0

0 FRM_CEBIT_CRCTX Set E Bits Upon Detection of CRCTX Enable (CEPT

Only). 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

252 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 3 24. FRM_PMGR14 , Performance Monitor Global Register 14 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 25. FRM_PMGR15, Per formance Monitor Global Register 15 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 3 26. FRM_PMGR16, Per formance Monitor Global Register 16 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address* Bit Name Functi on Reset

Default

0x80P3D 15:12 —Reserved. Must write to 0. 0x0

11 FRM_PTRN_EN Enables the Detector Circu itr y. FRM_PTRN_LNK[4:0]

should be set to 1 before enabling the detection circuitry. 0

10 FRM_PTRN_INV Receive Pattern Normal/Inver t Mode. Selects whether to

check for the selected pattern or its inverse.

0 = Selected pattern.

1 = Inverse.

9 FRM_PTRN_FRMT Receive Pattern Framed/Unframed Mode. Selects moni-

toring for either framed or unframed test pattern.

0 = Unframed.

1 = Framed.

8:4 FRM_PTRN_LNK[4:0] Pattern Detector Link Select. 5-bit link selection to indi-

cate which link to moni tor for test patter ns. 0

3:0 FRM_PTRN_SEL[3:0] Receive Pattern Select.

0000 = Pattern detector deactivate.

0001 = MARK (a ll ones AIS ) .

0010 = QRSS (220 – 1 with zero s uppres s ion).

0011 = 25 – 1.

0100 = 63(2 6 – 1).

0101 = 511(2 9 – 1) (V.52).

0110 = 29 – 1.

0111 = 2047(211 – 1) (O.151).

1000 = 211 – 1 (reve rsed).

1001 = 215 – 1 (O.151).

1010 = 220 – 1 (V.57).

1011 = 220 – 1 (CB113/CB114).

1100 = 223 – 1 (O.151).

1101 = 1:1 (alter nating).

0x00

Address* Bit Name Function Reset

Default

0x80P3E 15: 0 FRM_LN_I S[16:1] Per-Link PM Su mmary Interru pts for Links 16 Down to 1 . 0x0000

Address* Bit Nam e Fun ction Reset

Default

0x80P3F 15:12 —Reserved. Must writ e to 0. 0x0

11:0 FRM_LN_IS[28:17] Per-Link PM Summary Interrupts for Links 28 Down to 17. 0x000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

253Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.4 HDLC Glo bal Configuration a nd Status Registers

Table 327. FR M_HGR1, Tr ansmit HDLC Global Register 1 (R/W)

Table 328. FR M_HGR2, Tr ansmit HDLC Global Register 2 (R/W)

Table 329. FR M_HGR3, Tr ansmit HDLC Global Register 3 (R/W)

Table 330. FR M_HGR4, Tr ansmit HDLC Global Register 4 (R/W)

Address Bit Nam e Function Reset

Default

0x80140 15:10 —Reserved. Must write to 0. 0x00

9:0 FRM_HTTHRSH0[9:0] HDL C Trans mit FIFO T hre shold 0. T hese bits indicate

the threshold levels for the Tx FIFOs. When a channel is

enabled an d the number of bytes in its FI FO decrements

to this val ue, its FRM_HTTHRSH (Table 436) bit i s set

(optionally causes in terrupt ). FRM_HTTHRS H0[9:0] or

FRM_HTTHRSH1[9:0] is selected on a per-channel basis

with the FRM_HTTHRSEL (Table 436) parameter.

0x000

Address Bit Nam e Function Reset

Default

0x80141 15:10 —Reserved. Must write to 0. 0x00

9:0 FRM_HTTHRSH1[9:0] HDL C Trans mit FIFO T hre shold 1. T hes e bi ts indicate

the threshold levels for the Tx FIFOs. When a channel is

enabled an d the number of bytes in its FI FO decrements

to this va lue, its FRM_HTTHRSH bit is set (option a lly

causes interrupt). FRM_HTTHRSH0[9:0] or

FRM_HTTHRSH1[9:0] is selected on a per-channel basis

with the FRM_HTTHRSEL (Table 436) parameter.

0x000

Address Bit Nam e Function Reset

Default

0x80142 15:8 —Reserved. Must write to 0. 0x00

7:0 FRM_TXICHAR0[7:0] Transparent Mode Transmit Idle Char 0. These bits are

used in tra ns parent mo de. They represent the firs t 8-bit pat -

tern the t ra ns mi tter s hould send when there is no data

available in the FIFO. One of the four patterns can be

selected on a per-channel basis with the

FR M_ H XPIDLE[1 :0] (Table 436) param eter.

0x00

Address Bit Nam e Function Reset

Default

0x80143 15:8 —Reserved. Must write to 0. 0x00

7:0 FRM_TXICHAR1[7:0] Transparent Mode Transmit Idle Char 1. These bits are

used in transparent mode. They represent the second 8-bit

patter n the transmitter will send when there is no data avail-

able in the FIFO. One of the four p atterns c an be selected

on a per-chann el basis with the FRM_HXPIDLE[1:0]

(Table 436) parameter.

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

254 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 331. FRM_HGR5, Transmit HDLC Global Reg ister 5 (R/W)

Table 332. FRM_HGR6, Transmit HDL C Gl obal Register 6 (R/W)

Table 333. FRM_HGR7, Transmit HDL C Gl obal Register 7 (R/W)

Table 334. FRM_HGR8, Transmit HDL C Gl obal Register 8 (R/W)

Table 335. FRM_HGR9, Transmit HDL C Gl obal Register 9 (R/W)

Address Bit Name Function Reset

Default

0x80144 15:8 —Reserved. Mus t write to 0. 0x00

7:0 FRM_TXICHAR2[7:0] Transparent Mode Transmi t Idle Char 2. These bits

are used in transpare nt mode. They represent the third

8-bit patter n th e transmitter will send when t here is no

data available in the FIFO. One of the four patterns can

be selected on a per-channel basis with the

FRM_HXPIDLE[1:0] (Table 435) parameter.

0x00

Address Bit Name Function Reset

Default

0x80145 15:8 —Reserved. Mus t write to 0. 0x00

7:0 FRM_TXICHAR3[7:0] Transparent Mode Transmi t Idle Char 3. Thes e bi t s

are used in transparent mode. They represent the fourth

8-bit patter n th e transmitter will send when t here is no

data available in the FIFO. One of the four patterns can

be selected on a per-channel basis with the

FRM_HXPIDLE[1:0] (Table 435) parameter.

0x00

Address Bit Name Function Reset

Default

0x80146 15:5 —Reserved. M ust write to 0. 0x 000

4:0 FRM_FCNT0[4:0] HDLC Flag Count 0. These v alues are the number of addi-

tional idle flags to be sent between HDLC packets. One of

the four values can be selected on a per-channel basis with

the F R M_CFLAGS[1:0] (Table 435) parameter.

00000

Address Bit Name Function Reset

Default

0x80147 15:5 —Reserved. M ust write to 0. 0x 000

4:0 FRM_FCNT1[4:0] HDLC Flag Count 1. These v alues are the number of addi-

tional idle flags to be sent between HDLC packets. One of

the four values can be selected on a per-channel basis with

the F R M_CFLAGS[1:0] parameter.

00000

Address Bit Name Function Reset

Default

0x80148 15:5 —Reserved. Must write to 0. 0x000

4:0 FRM_FCNT2[4:0] HDL C Flag Cou nt 2. These va lues are the number of addi-

tional idle flags to be sent between HDLC packets. One of

the four values can be selected on a per-channel basis with

the F RM_CFLAGS[1:0] (Table 435) parameter.

00000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

255Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 336. FRM_HGR10, Transmit HDLC Global Register 10 (R/W)

Table 337. FRM_HGR11, Transmit HDLC Global Register 11 (RO)

Table 338. FRM_HGR12, Transmit HDLC Global Register 12 (R/W)

Table 339. FRM_HGR13, Transmit HDLC Global Register 13 (R/W)

Table 340. FRM_HGR14, Transmit HDLC Global Register 14 (R/W)

Table 341. FR M_HGR15, Receive HDLC Global Register 15 (R/W)

Address Bit Name Function Reset

Default

0x80149 15:5 —Reserved. Must write to 0. 0x 000

4:0 FRM_FCNT3[4:0] HDLC Flag Cou nt 3 . These values are the number of

additional idle flags to be sent between HDLC packets.

One of the four values can be selected on a per-channel

basis wi th the FRM_CFLAGS[1:0] parameter.

00000

Address Bit Nam e Function Reset

Default

0x8014A 15:0 FRM_TH_IS[15:0] Trans mit HDLC Interrupt Su mmary. This bitmap

shows what channels have interrupts. This register

maps channe ls 15—0 to bits 15:0 .

0x0000

Address Bit Name Function Reset

Default

0x8014B 15:0 FRM_TH_IS[31:16] Transmit HDLC Interrupt Summary. T his bitmap

shows what channels have interrupts. This register

ma p s ch a nnel s 31 —16 to bits 15:0.

0x0000

Address Bit Name Function Reset

Default

0x8014C 15:0 FRM_TH_IS[47:32] Transmit HDLC Interrupt Summary. T his bitmap

shows what channels have interrupts. This register

ma p s ch a nnel s 47 —32 to bits 15:0.

0x0000

Address Bit Name Function Reset

Default

0x8014D 15:0 FRM_TH_IS[63:48] Transmit HDLC Interrupt Summary. T his bitmap

shows what channels have interrupts. This register

ma p s ch a nnel s 63 —48 to bits 15:0.

0x0000

Address Bit Nam e Function Reset

Default

0x80040 15:10 —Reserved. Must write to 0. 0x00

9:0 FRM_HRTHRSH0[9:0] Indicates the Thresh ol d Levels for the Rx FIFOs.

When a channel i s enabled and its F IFO count incre-

ments to this val ue, its FRM_HRTHRSH (Table 443)

status bit is se t. FRM _HRTHRS H0 or

FRM_HRTHRSH1 is selected on a per- channe l basis

with the FRM_RTHRSEL (Table 442) parameter.

0x000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

256 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 342. FRM_HGR16, Receiv e HDLC Global Register 16 (R/W)

Table 343. FRM_HGR17, Receive HDL C Global Register 17 (R/W)

Table 344. FRM_HGR18, Receive HDL C Global Register 18 (R/W)

Table 345. FRM_HGR19, Receive HDL C Global Register 19 (R/W)

Table 346. FRM_HGR20, Receive HDL C Global Register 20 (R/W)

Address Bit Nam e Function Rese t

Default

0x80041 15:10 —Reserved. Must write to 0. 0x00

9:0 FRM_HRTHRSH1[9:0] Indicates the Thresh ol d Levels for the Rx FIFOs.

When a channel i s enabled and its F IFO count incre-

ments to t his value, its FRM_HRTHRSH status bit is

set. FRM _HRTHRSH0[9:0] or FRM _HRTHRSH1[9:0]

is sele cted on a per-channel basis with the

FRM_RTHRSEL (Table 442) parameter.

0x000

Address Bit Nam e Function Rese t

Default

0x80042 15:0 FRM_RH_IS[15:0] Receive HDLC Interru pt Sum m ary. Thi s bitmap

shows what channels have interrupts. This register

maps channels 15—0 to bits 15:0.

Address Bit Name Function R eset

Default

0x80043 15:0 FRM_RH_IS[31:16] Receive HDLC Interrupt Summary. This bitmap

shows what channels have interrupts. This register

maps ch annels 31—16 to bits 15:0.

Address Bit Name Function R eset

Default

0x80044 15:0 FRM_RH_IS[47:32] Receive HDLC Interrupt Summary. This bitmap

shows what channels have interrupts. This register

maps ch annels 47—32 to bits 15:0.

Address Bit N am e Function Reset

Default

0x80045 15:0 FRM_RH_IS[63:48] Rece ive HDLC I nter rupt Summary. This bitmap

shows what channels have interrupts. This register

ma p s ch a nnel s 63 —48 to bits 15:0.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

257Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.5 System Interface Global Registers

Table 347. FRM_SYSGR1, System Interface Global Register 1 (R/W)

Address Bit Name Function Reset

Default

0x80050 15:12 FRM_SYSMOD[3:0] System Interface M ode Associated Signaling Mode.

0000 = 2.048 Mbits /s CHI.

0001 = 4.096 Mbits /s CHI.

0010 = 8.192 Mbits /s CHI.

0100 = 19.44 Mbits /s PSB (device 0 mode).

0101 = 19.44 Mbits /s PSB (device 1 mode).

0110 = 19.44 Mbits /s PSB (device 2 mode).

1 000 = SM I.

All others: Reserv ed.

0000

11 FRM_ASM System Interface Mode Assoc iated Si gnaling Mode.

0 = CHI is configured to carry payload data only.

In P SB mode, transmit signaling is 3-s tated, and receive sig-

naling ignored.

1 = CH I is configured to carr y both payload data and signaling

information. Each time slot consists of 16 bits where 8 bits are

data and the remaining 8 bits are signaling information. CHI

must be programmed for 4.096 Mbits/s or 8.192 Mbits/s

modes.

In PSB m ode , tra nsmi t signaling is driven and receiv e signaling

is fo rwarded to the signaling block.

10 FRM_CMS CHI Clock Mode. This bit is only applicable in the CHI mode.

Otherwise , it should be set to 0.

0 = CH I clock and CHI data have the same rate.

1 = CH I clock is twic e the rate of CHI data.

9 FRM_CHIDTS CHI Dual Time-Slot Mode. This bit is only applicable in the

C H I 4.096 Mbits/s (no ASM) and 8 .192 Mbits/s (without ASM)

modes.

0 = Enables 32 contiguous time slots.

1 = Enables double time slot mode in which the transmit CHI

drives data for one time s lot and 3-states for the subsequent

time slot.

8 FRM_STUFFL/

FRM_LNKSTART Stuff Position/Link Start. CHI m ode s onl y: determ in e s t he

position of th e stuffed time slo ts in co njuncti on with the byte off-

set.

0 = SDDDSDDDSDDDS.. . . . . . . (TS0—TS31).

1 = SDDDDD D. . . . . . . SSSSSSS (TS0—TS31).

N SM I modes only: this bit determines how lin ks are numbered

on the NSMI. Internally, links are numbered starting at 1.

0 = NSMI link numbering starts at 0.

1 = NSMI link numbering starts at 1.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

258 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 347. FRM_SYSGR1, System Interface G lobal R egister 1 (R/W) (continued)

Table 348. FRM_SYSGR2, System Interface Global Register 2 (R/W)

Address Bit Name Function Reset

Default

0x80050 7 FRM_AISLFA System AIS on Loss of Frame Alignme nt.

0 = No action .

1 = System AIS is transmitted when the r eceive framer or the mapper

loss of frame alignment (MFA for DS1, BFA for CEPT) is detected.

6 FRM_AISCRCT S ystem AIS on CEPT Ti m er Expiration .

0 = No action.

1 = S ystem AIS is transmitted when the r ec eiv e fr amer loss of multifram e

alignment timer expiration is detected. (C EPT only.)

5 FRM_DNOTFAS CEPT Dual No t FAS. This bit is applicable in all system modes.

0 = FAS and NOTFAS time slots are transmitted to the system. The

receive system interface expects both FAS and NOTFAS time slots.

1 = NO TFAS is transmi tted twice to the system (in the NOTFAS and FAS

time slots). The receive system expects time slots 0 to carry

NOTFAS that is repeated twice.

4 FRM_TFSCKE System Interface Transmit Frame Sync Clock Edge Select.

0 = Transmit frame sync is sampled on the falling edge of transmit clock.

1 = Transmit frame sync is sampled on t he rising edge of t ransmit clock.

In PSB mode, this bit also determines the clock edge used to drive

data. The sampling p oin t of trans mit f rame s ync defi nes the zero off-

se t for CHI mode.

3 FRM_FSPOL Frame Sync Polarity.

0 = Transmit and receive frame sync is active low.

1 = Transmit and receive frame sync is active-high.

2:0 —Reserved. Must wr ite to 0. 0

Address Bi t Name Function Res et

Default

0x80051 15 FRM_HWYENA Tran sm it System In terface Highway Enable.

0 = Transmit data is forced into a high-impedance state for all

transmitted time slots. Receive system ignores receive data and

inserts the idle code in all time slots transmitted to the line. This

allows the fram er to be fully configured before transmission.

1 = Transmit and receive data is enabled.

14 FRM_RSTDONE

(Read Only) Framer Reset Status.

0 = Indicates internal reset is still in process.

1 = Indicates internal reset is complete.

Generally, the FRM_HWYENA bit should not be set to1 until this bit

13:0 —Reserved. Must wr ite to 0. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

259Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 349. FRM_SYSGR3, System Interface Global Register 3 (R/W)

Table 350. FRM_SYSGR4, System Interface Global Register 4 (R/W)

Table 351. FRM_SYSGR5, System Interface Global Register 5 (R/W)

Table 352. FRM_SYSGR6, System Interface Glo bal Register 6 (COR)

Address Bit Name F unc tion Reset

Default

0x80052 15:8 FRM_STUFF[7:0] Stuffed Time-Slot Code. 7F

7:0 FRM_IDLE[7:0] CHI Time-Slot Loopback Idle Code. 7F

Address Bit Name Function Reset

Default

0x80053 15 FRM_STSSLB CHI Time Slot System Loopback

0 = No action.

1 = Receive CHI time slot is looped back to th e system.

Idle code, FRM_IDLE[7:0] (Table 349), is inserted in place

of the looped back time slot to the line.

14 FRM_STSLLB C HI Time-Slot Line Loop Back.

0 = No action.

1 = Transmit CHI time slot is looped back to the line. Idle

code, FRM_ID LE[7:0], is inserted in place of the looped

back time slot to the system.

13 —Reserved. Must write to 0. 0

12:8 FRM_TSLBA[4:0] CHI Time-Slot Loopback Address. 00000

7:5 —Reserved. Must w rite to 0. 0

4:0 FRM_TSLBL[4:0] CHI Time- Slot Loopback Link Number. 00000

Address Bit Name Function Reset

Default

0x80054 15 FRM_TS_DPAR Transmit P SB Data P arity. This bit is only applicab le in the

parallel syste m bus mode. Otherwise, it should be set to

zero.

0 = Odd data parity is transmitted by the system.

1 = Even data parity i s transmitted by the sy stem.

14 FRM_TS_SPAR Transmit Sign alin g Pari t y. This bit applies to the signaling

information in the parallel system bus mode. It al so det er-

mines the parity for CHI ASM mode. Otherwise, i t should be

set to 0.

0 = Odd signaling parity is transmitted by th e sys tem.

1 = Even signaling parity is transmitted by the system.

13:0 —Reserved. Mus t write to 0. 0

Address Bit Name Function R eset

Default

0x80055 15:0 —Reserved. Must wr ite to 0. 0x0000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

260 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 353. FRM_SYSGR7, System Interface Global Register 7 (CO R)

Table 354. FRM_SYSGR8, System Interface Global Register 8 (R/W)

Table 355. FRM_SYSGR9, System Interface Global Register 9 (R/W)

Address Bit Name F unc tion Reset

Default

0x80056 15:1 —Reserved. Must write to 0. 0x0

0 FRM_TPSB_FS_IS Transmit P S B Frame Sync Error Interrupt. A 1 i ndi-

cates a f rame sync error was detected in PSB mod e.

The frame sync was either detec ted when it should

not have been (misplaced) or was not detected when

it should have (missing). This bit is cleared on read/

write unless the condition that set it still exists after

the read.

Address Bit Nam e Function R eset

Default

0x80057 15:1 —Reserved. Must write to 0. 0

0 FRM_PSB_FS_IM Transmit PS B Frame Sync Inter rup t Mask. A 1 pre-

vents the FRM_T PSB _F S_IS (Table 353) st atus from

causin g an i nterrupt. A 0 al lows the interr upt.

Address Bit Name Function Reset

Default

0x80150 15 FRM_RS_DPAR Receive PSB Data Parit y Select. This bit is only applicable in

the parallel system bus interface mode. Otherwise, it should

be set to 0.

0 = O dd data parit y is expected by the receive system.

1 = Even data parity is ex pected by the receive syste m.

14 FRM_RS_SPAR Receive Signaling Parity Select. This bit ap plies to the sig-

nalin g information in the parallel syst em bus mode. It also

determines the parity f or CHI ASM mode. Otherwise, it should

be set to 0.

0 = Odd signaling parity is expecte d by the receive system.

1 = Even si gnali ng parity is expected by the receive system.

13 FRM_RFSCKE Sys tem Interface Receive Frame Sync Clock Edge Select.

0 = Receive frame sync (and data) is sampled o n the falling

edge of receive clock.

1 = Recei ve frame sync (and data) is sample on the rising

edge of receive clock.

In para llel syst em bu s mode , thi s bit a lso determines the clo ck

edge used to sample data.

In CHI mode, the sample point of frame sync defines the zero

offset for the CHI.

12:0 —Reserved. Must write to 0. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

261Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 356. FRM_SYSGR10—FRM _ SYSG R14, Sy stem Interface Global Register 10—14 (R/W)

Table 357. FRM_SYSGR15, System Interface Glo bal Register 15 (COR)

Table 358. FRM_SYSGR16, System Interface Global Register 16 (R/W)

Address Bit Name Function Reset

Default

0x80151

—

0x80155

15:0 —Reserved. Mus t write to 0. 0x0000

Address Bit Name Function Reset

Default

0x80156 15 FRM_DPAR_IS Data P arity Interrupt. I n PSB mode, a 1 indicates a data parity

erro r was detected. Thi s bi t is cl eared on read unless the con-

d ition that set it still exists after the read.

14 FRM_SPAR_IS Signaling Parity Interrupt. In PSB mode, a 1 i ndic ates a sig-

naling parity error w as detected. In CHI ASM mode, a 1 indi-

cates a parity error was detected.

T h is bit is cleared on read unless the condition that se t it still

exis t s af t er t he read.

13:1 —Reserved. Must write to 0. 0

0 FRM_PSB_FS_IS Receive PSB frame Sy nc Interrupt. A 1 indicates a frame

sync error was detected in PSB mode. The frame sync was

either detected when it should n ot have been (misplaced) or

was not detec ted when it should have ( missing). This bit is

cleared on read unless t he condition that s et it still exists after

the read.

Address Bit Name Function Reset

Default

0x80157 15 FRM_DPAR_IM Data Parity Interrup t Mask. A 1 p reve nts the FRM _ DP A R _ IS

status from causing an interrupt. A 0 allow s the interru pt. 1

14 FRM_SPAR_IM Signaling Parity Interrupt Mask. A 1 pre vents the

FRM_SPAR_IS status from causing an inter rupt. A 0 allo ws the

interrupt.

13:1 —Reserved. Must write to 0. 0

0 FRM_PSB_FS_IM Recei ve PSB frame Sync Interrupt Mask. A 1 prevents the

FRM_PSB_F S_IS status f rom causing an interru pt. A 0 allows

the interru pt.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

262 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

12.6 Signa ling G lobal Registe rs

Table 359. FRM_SGR1, Receive Signaling Glob al Reg ister 1 (R/W)

Table 360. FRM_SGR2, Receive Signaling Glob al Reg ister 2 (R/W)

A ddress Bit Name Function Reset

Default

0x80060 15 FRM_R_TSAISHG S ystem AIS for Handling Group s. When set to 1, this

configuration bit forces AIS to the system interface for

those signaling bits which cor respond to a handling group ,

which is out of a lignment . A 0 d isables thi s feature. This

feature is only applied to those links which are enabled for

byte sync mappin g and handli ng groups us ing the pe r-li n k

signaling configuration registe rs.

14:10 FRM_R_LINKCNT[4:0] Rece ive Link Count. Indicates the number of links ser-

viced by the signaling b lock. This value should be set to 28

when the Super Mapper is interfac ing with only DS1 links;

it should be set to the actual number of links active for

mixed mode applications.

9—Reserved. Must write to 0. 0

8:6 FRM_TEST_BIT[2:0] Test Bits. 000

5:2 —Reserved. Must write to 0. 0

1 FRM_R_AFZFBE Au tomati c Signaling Freeze on Framing Bit Err ors. Set

to 1 in order to freeze signaling regis te r updates based on

framing bit errors.

0—Reserved. Must write to 0.

Address Bit Name Function Reset

Default

0x80061 15 FRM_R_SCOSEN Receive Signaling Change of State F IF O E nable. When set

to 1, this configuration bit enables the maintenance of the sig-

naling ch ange of state FIFO. When set to 0, no entries will be

made into t he FI FO. T his bit applies to all of the links. If an

individual time slot is programmed f or no signaling, then no

entri es wil l be made fo r that time slo t. Also, if the si gnal ing

source in the receive path is set to host, then no entries will be

made for that time slot.

14:10 —Reserved. Must write to 0. 0

9:0 FRM_R_

SCOSDTH[9:0] Receive Signaling Change of State FIFO Depth Threshold.

Th is number can be prog ramm e d fr om 0 to 672. If the number

of entries in the signal ing change of s tate FI FO e xceeds the

value programmed here, then the associ ated interrupt status

bit w ill be se t.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

263Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 361. FRM_SGR3, Receive Signaling Global Regis ter 3 (R/ W )

Table 3 62. FRM_SGR4, Receive Signaling Glob al Reg ister 4 (RO)

Table 3 63. FRM_SGR5, Receive Signaling Glob al Reg ister 5 (RO)

Address Bit Name F unction R eset

Default

0x80062 15:0 FRM_

R_SCOSTTH[15:0] Receive Signalin g Chan ge of Stat e FIFO T i m er Threshold.

This number can be programmed from 0 to 0xFFFF. The value

indicates the number of 125 µs increments that the timer

counts before int errupting the processor. The associated inter-

r upt status bit will be set only if there are valid entries in the

FIFO. When set to 0, the timer is disabled and no interrupt will

be generated. The maximum timer setting is 8 s.

0x0000

Address Bit Name Function Reset

Default

0x80063 15:14 FRM_

R_COSFIFOS[1:0] Receive Signaling Chan g e of Stat e FIFO Status. These

bits are located at the addr ess for t he signaling c hange of

state F IFO. Th ese status bits have the followin g de finitio ns:

01 = Th e ent ry being read is the last valid en try.

11 = Th e ent r y being rea d is not the last valid entry.

00 = The entry being read is not valid and should be ignored.

13:9 FRM_

R_COSFIFOL[4:0] COS Li nk Numb er. These bits are located at the address for

the signaling ch ange of state FIFO. This number indicates

the particular link from which a signaling change of state has

been detected.

8:4 FRM_

R_COSFIFOTS[4:0] COS T ime-Sl ot Number. These bits are located at the

addres s for the signaling change of state FIFO. This number

indicates the par ticular time slot in wh ich a signaling cha nge

of state has been detected.

3:0 FRM_

R_COSFIFOSIG[3:0] New Signaling Code. Th ese bits are located at the address

for the signaling change of state FIFO. This value indicates

the new signaling state received.

Address Bit N am e Fun ction R eset

Default

0x80064 15:1 —Reserved. 0X0000

0FRM_

R_COSDTHS Receiv e Signaling Change of State FIFO Depth Thre shold

Overflo w Status. This status bit reflects the actual depth of the

FIFO entries as compared t o the threshold programmed by the

host. When set to 1, the threshold is currently e xceeded. When

set to 0, the number of FIFO entries is less than the programmed

threshold.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

264 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 364. FRM_SGR6, Receive Signaling Global Register 6

Table 365. FRM_SGR7, Receive Signaling Glob al Reg ister 7 (R/W)

Address Bit Name F unction Reset

Default

0x80065 15:3 —Reserved. Reads 0. 0

2 FRM_R_COSDTHI Re ceiv e Signal i ng Cha nge of State FIFO Dep th Threshold

Overflow Interrupt. This interru pt stat us bit wil l be set when

the programmed threshold for the FIFO capacity has been

exceeded. This interrupt bit can be reset based on a clear-on-

read protocol, w hich is provisioned in the Super Mapper global

registers.

1FRM_R_COSTTHIRe c eive Signal i ng Cha nge of State FIFO Timer Thres hol d

Interrupt. This interrupt status bit wi l l be set when the pro-

gr ammed interrupt timer has expired and there are valid entries

in the FIFO to be processe d. This interrupt bit can be reset

based on a clear-on-read protocol, which is provisioned in the

Super Mapper global registers.

0 FRM_R_COSOFI Re ceive Signal ing Cha nge o f State FIFO Overflow I nt er-

rupt. This interrupt status bit will be set when the signaling

change of state FIFO overflows. The contents of the FI FO will

be lost and programmed threshold for the FIF O c apac it y has

been exceeded. This interrupt bit can be reset based on a

clear-on-rea d protocol, which is provisioned in the Super Map-

per global registers.

Address Bit Name F un ction R eset

Default

0x80066 15:3 —Reserved. Reads 0. 0

2FRM_

R_COSDTHM Receive Signaling Change of State FIFO Depth Threshold

Overflow Interrupt Mask. The corresponding interrupt status bit

will cause a processor interrupt if this bit is set to 0. The corre-

sponding interrupt status bi t will be mas ked from causing a pro-

cessor i nterr upt if this bit is set to 1.

1FRM_

R_COSTTHM Receive Signaling Change of State FIFO Tim er Thresho ld

Interrupt Mask. The corresponding interrupt status bit will cause

a processor interrupt if this bit is set to 0. The corresponding

interrupt status bit will be masked from causing a processor inter-

r upt if this bit is set t o 1.

0FRM_

R_COSOFM Receive Signaling Change of State FIFO Overflo w Interrupt

Mask. The corresponding interrupt status bit will cause a proces-

sor interrupt if this bit is set to 0. The corresponding interrupt sta-

tus bit will be masked from causing a processor interrupt if this bit

is set to 1.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

265Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 366. FRM_SGR8, Transmit Signaling Global Register 8 (R/W)

Address Bi t Name Function Reset

Default

0x80160 15 —Reserved. Must wr ite to 0. 0

14:10 FRM_T_LINKCNT[4:0] Transmit Li nk Count . Indicates the number of links ser-

viced by the signaling block. Th is value should be set to 28

when the Super Mapper is interfacing with only DS1 links; it

should be set to t he actual number of links activ e for mixed

mode applications.

9:6 —Reserved. Must write to 0. 0000

5 FRM_T_SUBZERO Substitute Zero. A 1 forces signaling data to be 0000 for

those time s lots which have a signaling state mode of no

signaling. This only applies to the signaling data trans ferred

to the VT mapper.

4 FRM_T_FAS_NOTFAS FAS/NO T FAS Transmission. Use d to force alignment of

the CEPT TS16 multiframe to a FAS or NO TF AS frame. A 0

indicates alignment to a FAS frame . A 1 indicates alignment

to a NOTFAS frame.

3:2 —Reserved. Must write to 0. 00

1 FRM_T_AFZFBE Auto matic Signaling Fre eze on Fr aming Bi t Errors. Set

to 1 in order to freeze signaling register updates based on

framing bit errors .

0—Reserved. Must wr ite to 0. 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

266 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

12.7 Frame Forma tter (Transmi t Fr amer) G loba l Register

Table 367. FRM_FFGR1, Transmit Framer Global Register 1 (R/W)

Address Bit Nam e Function Reset

Default

0x80170 15 FRM_TXFSOOF Transmit Frame S ync when Out-Of-F ram e Valid in

Transport Modes Only.

0 = Do not transmit FS when out-of-frame. (FS is

present when in frame.)

1 = Transmit an arbitrary FS when out-of-frame.

14:12 —Reserved. Must write to 0. 0

11 FRM_PTRN_EN Transm it Pattern.

0 = Pattern generator off.

1 = Patter n generator on.

10 FRM_PTRN_INV Transm it Pattern Normal/Inver t Mode.

This bit inverts the patte rn.

0 = No rmal.

1 = Invert.

9 FRM_PTRN_FRMT Transmit Pattern Framed/Unframed Mode.

This bit selects ei the r a framed (1) or un framed (0) pat-

tern.

8:4 FRM_PTRN_LNK[4:0] Pattern Generator Link Select.

5-bit link selection to indicate link for pattern insertion. 00001

3:0 FRM_PTRN_SEL[3:0] Transmit Pa ttern Select.

0000 = Pattern generator deactivated.

0001 = MARK (all ones AIS) .

0010 = QRSS (220 – 1 with zero suppression).

0011 = 25 – 1.

0100 = 63 (265 – 1).

0101 = 511(2 9 – 1) (V.52).

0110 = 29 – 1.

0111 = 2047 (211 – 1) (O.151).

1000 = 211 – 1 (rev ersed).

1001 = 215 – 1 (O. 151) .

1010 = 220 – 1 (V.57).

1011 = 220 – 1 (CB113/CB114).

1100 = 223 – 1 (O. 151) .

1101 = 1:1 (al ternating ).

1110 = Reserved.

1111 = Reserved.

0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

267Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.8 Facility Data Li nk Global R egisters

Table 368. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/ W )

Table 369. FRM_FDLGR2, Tra nsmit Facility Data Link G lo bal Regi ster 2 (R /W)

12.9 Super Mapp er Fra me r Per Link Con figura tion and Stat us Registe rs

12.9.1 Signaling Per Link Registers

Table 370. Receive Path Signaling Register Addressing Map

* L and R represent hexidecimal digits used for absolute addressing in Table 372, Table 373, and Table 374.

Table 371. Receive Path Signaling Registers Address Indexing

Read: for link 1, the hexidecim al digi t L is 0x0 and the hexidecimal digit R is 0x2.

Address Bit Nam e Function Reset

Default

0x80090 15:0 —Reserved. Must wr ite to 0. 0x0000

Address Bit Nam e Function Reset

Default

0x801A1 15:0 —Reserved. Must write to 0. 0x0000

Address Pins (ADDR1 5—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 L NK2 LNK 1 LNK0 R XP = 0 0 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0

L* R* —

Link L R Link L R Link L R Link L R

1 0x0 0x2 8 0x1 0x0 16 0x2 0x0 24 0x3 0x0

2 0x0 0x4 9 0x1 0x2 17 0x2 0x2 25 0x3 0x2

3 0x0 0x6 10 0x1 0x4 18 0x2 0x4 26 0x3 0x4

4 0x0 0x8 11 0x1 0x6 19 0x2 0x6 27 0x3 0x6

5 0x0 0xA 12 0x1 0x8 20 0x2 0x8 28 0x3 0x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA ———

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC ———

———15 0x1 0xE 23 0x2 0xE ———

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

268 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 372. F RM_RSLR0—FRM_RS LR31, Receive Signaling Link Registers 0—31 (R/W)

* See Table 371 for values of L and R.

Notes:Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.

For DS1 links, address locations 1 through 24 will contain valid data.

F or CE PT l inks , loca tio ns 1 throu gh 15 and 1 7 t hro ug h 3 1 wil l con tai n v a li d data . W rit es fr o m t he syst e m in t erface to a dd ress 0 and 16 will

be accepted and stored in signaling registers.

Address*Bit N ame Function Reset

Default

0x8LR00 6:0 FRM_RPSR0[6:0] Time Slot 0 Receive Signaling Data. 0000000

0x8LR01 6:0 FRM_RPSR1[6:0] Time Slot 1 Receive Signaling Data. 0000000

0x8LR02 6:0 FRM_RPSR2[6:0] Time Slot 2 Receive Signaling Data. 0000000

0x8LR03 6:0 FRM_RPSR3[6:0] Time Slot 3 Receive Signaling Data. 0000000

0x8LR04 6:0 FRM_RPSR4[6:0] Time Slot 4 Receive Signaling Data. 0000000

0x8LR05 6:0 FRM_RPSR5[6:0] Time Slot 5 Receive Signaling Data. 0000000

0x8LR06 6:0 FRM_RPSR6[6:0] Time Slot 6 Receive Signaling Data. 0000000

0x8LR07 6:0 FRM_RPSR7[6:0] Time Slot 7 Receive Signaling Data. 0000000

0x8LR08 6:0 FRM_RPSR8[6:0] Time Slot 8 Receive Signaling Data. 0000000

0x8LR09 6:0 FRM_RPSR9[6:0] Time Slot 9 Receive Signaling Data. 0000000

0x8LR0A 6:0 FRM_RPSR10[6:0] Time Slot 10 Receive Sig naling Data. 0000000

0x8LR0B 6:0 FRM_RPSR11[6:0] Time Slot 11 Receive Sig naling Data. 0000000

0x8LR0C 6:0 FRM_RPSR12[6:0] Time Slot 12 Receive Signaling Data. 0000000

0x8LR0D 6:0 FRM_RPSR13[6:0] Time Slot 13 Receive Signaling Data. 0000000

0x8LR0E 6:0 FRM_RPSR14[6:0] Time Slot 14 Receive Sig naling Data. 0000000

0x8LR0F 6:0 FRM_RPSR15[6:0] Time Slot 15 Receive Signaling D a ta. 0000000

0x8LR10 6:0 FRM_RPSR16[6:0] Time Slot 16 Receive Signaling Data. 0000000

0x8LR11 6:0 FRM_RPSR17[6:0] Time Slot 17 Receive Signaling Data. 0000000

0x8LR12 6:0 FRM_RPSR18[6:0] Time Slot 18 Receive Signaling Data. 0000000

0x8LR13 6:0 FRM_RPSR19[6:0] Time Slot 19 Receive Signaling Data. 0000000

0x8LR14 6:0 FRM_RPSR20[6:0] Time Slot 20 Receive Signaling Data. 0000000

0x8LR15 6:0 FRM_RPSR21[6:0] Time Slot 21 Receive Signaling Data. 0000000

0x8LR16 6:0 FRM_RPSR22[6:0] Time Slot 22 Receive Signaling Data. 0000000

0x8LR17 6:0 FRM_RPSR23[6:0] Time Slot 23 Receive Signaling Data. 0000000

0x8LR18 6:0 FRM_RPSR24[6:0] Time Slot 24 Receive Signaling Data. 0000000

0x8LR19 6:0 FRM_RPSR25[6:0] Time Slot 25 Receive Signaling Data. 0000000

0x8LR1A 6:0 FRM_RPSR26[6:0] Time Slot 26 Receive Sig naling Data. 0000000

0x8LR1B 6:0 FRM_RPSR27[6:0] Time Slot 27 Receive Sig naling Data. 0000000

0x8LR1C 6:0 FRM_RPSR28[6:0] Time Slot 28 Receive Signaling Data. 0000000

0x8LR1D 6:0 FRM_RPSR29[6:0] Time Slot 29 Receive Signaling Data. 0000000

0x8LR1E 6:0 FRM_RPSR30[6:0] Time Slot 30 Receive Sig naling Data. 0000000

0x8LR1F 6:0 FRM_RPSR31[6:0] Time Slot 31 Receive Signaling D a ta. 0000000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

269Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 373. FRM_RSLR32, Receive Signaling Link Register 32 (COR)

* See Table 371 for values of L and R.

Address*Bit Name Fun ction Reset

Default

0x8LR20 15:12 FRM_R_HGAIS[3:0] HG AIS Detection. Indicat es t he detection of AIS i n the

correspondi ng HG. 0000

11:8 FRM_R_HGA[3:0] HG Alignment. Indicates the alignment status for the cor-

responding HG. A 0 indicates no ali gnment. A 1 indicates

alignment for the correspo nding group.

0000

7:4 FRM_R_HGRDI[3:0] HG RDI. Indicates the detection of three consecutive

zeros in the Sp bit position of the corresponding HG. 0000

3 FRM_R_TS16A Time Slot 16 Multiframe Alignment St atus. A 0 indi-

cates that currently, time slot 16 m ult iframe alignment is

not established. A1 indicates that currently, time slot 16

multiframe alignment has been establi s hed.

2 FRM_R_TS16AIS Time Slot 16 AIS Detection Status. If time slot 16 multi-

frame alignme nt is lo st, this bit will reflect the detection of

AIS in ti me slot 16.

1:0 —Reserved. Must write to 0. 0

Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W)

Address*Bit Name F unction Reset

Default

0x8LR21 15 FRM_R_FZCON Freeze C onversion. When s et to1, this enables the conver-

sion of cer tain signaling codes w hen the signaling buffers

have been f rozen. The code translation is 00 to 01 and 0000

to 0101 for 4-state and 16- state signaling, respective ly.

14:9 —Reserved. Must write to 0. 0

8 FRM_R_SIGI Signaling Insertion. A 1 enables the insertion of signaling

data into th e Tx line. A 0 disables the inser tion of si gnaling

data into the Tx line. This bit is valid in t he Rx path o nly when

in transport mode; otherwise, it shoul d be set to 0.

7FRM_R_RXSTOMPR x Path Stomping. For DS1 links, thi s bit indi cates to s tomp

all robbed bi t signaling on voice time slots on the correspond-

ing link. Stomping of time slot 16 for CEPT links is performed

in the system interface block.

1 = Will enable stomping .

0 = Will disable stom ping for the corresponding link.

6—Reserved. Must wr ite to 0.

5 FRM_R_SIGDEB Signaling Debounce.Thi s bit enables signal debounce on

signaling when extracted from the Rx line. 0

4 FRM_R_HGEN Handling Group Enable. When set to 1 i n combination w ith

selecting the s ource of signaling data to be the VT mapper,

this indicates to the signaling block that the signaling for this

link is byte sy nc mapped and us es the handling group format.

3 FRM_R_MSIGFZ Manua l S i gnali ng Fr eez e. Used to manually h a lt the signal-

ing register upd ates w hen the source of sign aling data is

either the VT mapper or when t he s ignaling is extracted from

the Rx line. A 1 halts the updates.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ju ne 2001

270 Agere Sy stem s Inc.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

12 28-Channel Framer Registers (continued)

* See Table 371 for values of L and R.

Table 375. Transmit Path Signaling Register Addressing Map

* L and T represent hexidecimal digits used for absolute addressing in Table 377, Table 378, and Table 379.

Read: for link 1 (pertaining to Table 376), the hexidecimal digit L is 0x0 and the hexidecimal dig it T is 0x 3.

Table 376. Transmit Path Signaling Registers Address Indexing

0x8LR21 2 FRM_R_FGSRC F and G Source. Indicates which enti t y will be the source for

the F and G values used in handling the ABCD bits.

0 = Host programmed.

1 = Implied by the T x path ASM.

The Tx path option can only be selected when the Tx path is

configured with an ASM CHI or parallel system bus interface.

Also, the Tx path option can only be selected when the Rx

path is extracting da ta from the receive line interface v s. byte

sync VT mapped mode.

1:0 FRM_R_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will be

the source for the ABCD bits.

00 = Signali ng programmed b y the host.

01 = Signaling e xt racted from the Rx line .

10 = Signaling read from VT mapper in byte sync mode (valid

only for DS1).

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 TXP=1 0 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0

L* T* —

Link L T Link L T Link L T Link L T

1 0x0 0x3 8 0x1 0x1 16 0x2 0x1 24 0x3 0x1

2 0x0 0x5 9 0x1 0x3 17 0x2 0x3 25 0x3 0x3

3 0x0 0x7 10 0x1 0x5 18 0x2 0x5 26 0x3 0x5

4 0x0 0x9 11 0x1 0x7 19 0x2 0x7 27 0x3 0x7

5 0x0 0xB 12 0x1 0x9 20 0x2 0x9 28 0x3 0x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB ———

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD ———

———15 0x1 0xF 23 0x2 0xF ———

Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) (continued)

Address*Bit Name F unction Reset

Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

271Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 377. FRM_TSLR0—FRM _T SL R31, Transm it Signaling Link Registers 0 —31 (R/W)

* See Table 376 for values of L and T.

Notes:Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.

For DS1 links, address locations 1 through 24 will contain valid data.

F or CE PT l i nks, loca t ions 1 thr ough 15 an d 17 t hr oug h 31 will cont ai n v a li d dat a. Wri tes fr om th e syst em i nte r face to ad dres s 0 and 16 will

be accepted and stored in signaling registers. For CEPT links, inser ted time slot 16 X bits are written to locates 0.

Address*Bit Nam e Function R eset

Default

0x8LT00 6:0 FRM_TPSR0[6:0] Time Slot 0 Tr ansmit Sig naling Data. 0000000

0x8LT01 6:0 FRM_TPSR1[6:0] Time Slot 1 Tr ansmit Sig naling Data. 0000000

0x8LT02 6:0 FRM_TPSR2[6:0] Time Slot 2 Tr ansmit Sig naling Data. 0000000

0x8LT03 6:0 FRM_TPSR3[6:0] Time Slot 3 Tr ansmit Sig naling Data. 0000000

0x8LT04 6:0 FRM_TPSR4[6:0] Time Slot 4 Tr ansmit Sig naling Data. 0000000

0x8LT05 6:0 FRM_TPSR5[6:0] Time Slot 5 Tr ansmit Sig naling Data. 0000000

0x8LT06 6:0 FRM_TPSR6[6:0] Time Slot 6 Tr ansmit Sig naling Data. 0000000

0x8LT07 6:0 FRM_TPSR7[6:0] Time Slot 7 Tr ansmit Sig naling Data. 0000000

0x8LT08 6:0 FRM_TPSR8[6:0] Time Slot 8 Tr ansmit Sig naling Data. 0000000

0x8LT09 6:0 FRM_TPSR9[6:0] Time Slot 9 Tr ansmit Sig naling Data. 0000000

0x8LT0A 6:0 FRM_TPSR10[6:0] Time Slot 10 Transmit Signaling D a ta. 0000000

0x8LT0B 6:0 FRM_TPSR11[6:0] Time Slot 11 Transmit Signaling D a ta. 0000000

0x8LT0C 6:0 FRM_TPSR12[6:0] Time Slot 12 Transmit Signaling Data. 0000000

0x8LT0D 6:0 FRM_TPSR13[6:0] Time Slot 13 Transmit Signaling Data. 0000000

0x8LT0E 6:0 FRM_TPSR14[6:0] Time Slot 14 Transmit Signaling D a ta. 0000000

0x8LT0F 6:0 FRM_TPSR15[6:0] Time Slot 15 Transmit Signaling Data. 0000000

0x8LT10 6:0 FRM_TPSR16[6:0] Time Slot 16 Transmit Signaling Data. 0000000

0x8LT11 6:0 FRM_TPSR17[6:0] Time Slot 17 Transmit Signaling Data. 0000000

0x8LT12 6:0 FRM_TPSR18[6:0] Time Slot 18 Transmit Signaling Data. 0000000

0x8LT13 6:0 FRM_TPSR19[6:0] Time Slot 19 Transmit Signaling Data. 0000000

0x8LT14 6:0 FRM_TPSR20[6:0] Time Slot 20 Transmit Signaling Data. 0000000

0x8LT15 6:0 FRM_TPSR21[6:0] Time Slot 21 Transmit Signaling Data. 0000000

0x8LT16 6:0 FRM_TPSR22[6:0] Time Slot 22 Transmit Signaling Data. 0000000

0x8LT17 6:0 FRM_TPSR23[6:0] Time Slot 23 Transmit Signaling Data. 0000000

0x8LT18 6:0 FRM_TPSR24[6:0] Time Slot 24 Transmit Signaling Data. 0000000

0x8LT19 6:0 FRM_TPSR25[6:0] Time Slot 25 Transmit Signaling Data. 0000000

0x8LT1A 6:0 FRM_TPSR26[6:0] Time Slot 26 Transmit Signaling D a ta. 0000000

0x8LT1B 6:0 FRM_TPSR27[6:0] Time Slot 27 Transmit Signaling D a ta. 0000000

0x8LT1C 6:0 FRM_TPSR28[6:0] Time Slot 28 Transmit Signaling Data. 0000000

0x8LT1D 6:0 FRM_TPSR29[6:0] Time Slot 29 Transmit Signaling Data. 0000000

0x8LT1E 6:0 FRM_TPSR30[6:0] Time Slot 30 Transmit Signaling D a ta. 0000000

0x8LT1F 6:0 FRM_TPSR31[6:0] Time Slot 31 Transmit Signaling Data. 0000000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

272 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 378. FRM_TS LR32, Trans mit Si gn aling Link Register 32 (R/W)

*See Table 376 fo r value s of L an d T.

Address*Bit N am e Function Reset

Default

0x8LT21 15 —Reserved. Must write to 0. 0

14 FRM_T_ATS16RFA Au tomat ic TS16 Remote Frame Alarm. Enab les automatic

transmission of a 1 in the Y-bit position in the tran smit path

when the receive path ha s lo st TS16 alignment.

13 —Reserved. Must write to 0. 0

12 FRM_T_ASPLB Automatic Sp Loopback. When set, the Sp bi t transm itted

for each individual HG will be set to 0 when the HG ali gn-

ment is lost in the Rx pat h. Each Sp in the Tx path corre-

sponds to the same HG in the Rx path.

11 FRM_T_MSP Ma nua l S p. Used to manually force the transmission of a 0

in each of the Sp bit s of the HG s on each link. 0

10 FRM_T_ZCSM Zero Code Suppression Mode. When set to 1, the signal-

ing block wil l give an indication to the frame formatter for

each of the data channels. This indication should disabl e the

zero-code suppression for the associated t ime slot. Signal-

ing insertion must be enabled for FRM_T_ZCSM to take

effect. FRM_T_ZCSM will not work when byte sync mapping

is enabled.

9 FRM_T_VTSIGE VT Sign aling Enabl e. A 1 enables the transport of signaling

to the VT mapp er from the programmed s ignaling source in

byte sync mode. Byte sync mode cannot be enabled in c on-

junction with signaling insertion (bit 8, FRM_T_SIGI). The

robbed-bit p ositions can be stomped while in byte sync

mode but no signaling data can be inserted.

8 FRM_T_SIGI Signaling Insertion. A 1 enables the insertion of signaling

data i nto the Tx line. A 0 disable s the insert ion of signaling

data i nto the Tx line.

7—Reserved. Must write to 0. 0

6 FRM_T_TXSTOMP Tx Path Stomping. F or DS1 l inks , t his bit indi cates to st omp

all robbed-bit signaling on voice time slots on the corre-

sponding link to 0. Stomping time slot 16 for CEPT links i s

done by inserting all ones using the signaling registers. A 1

will enable stomping. A 0 will disabl e stomping f or the corre-

sponding link.

5—Reserved. Must write to 0. 0

4 FRM_T_HGEN Handling Group Enable. When set to 1 in com binat ion with

(bit 9, FR M _ T_V T SIGE ) , thi s bit indi cate s to the signaling

block that the signaling for this link is byte sync mappe d and

uses the handling group format.

3 FRM_T_MSIGFZ Manua l Signal in g F r ee ze . Used to manually halt the signal-

ing register updates when the source of signali ng data is

eith er the Rx system or the R x line. A 1 ha lt s t he updates .

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

273Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 3 78. FRM_TS LR32, Transmit Signaling Link Register 32 (R/W) (continued)

*See Table 376 fo r value s of L an d T.

Table 379. FR M_T SLR33, Transm it Signaling Link Register 33 (COR)

*See Table 376 fo r value s of L an d T.

12.10 Performanc e Monitor Pe r Link Re gisters

The following ta bles describe the functions of all bits in the regi s ter map. Counters are programmable to either roll-

over or saturate, and may be programmed to clear on rea d.

Registers are only provisionable to cl ear-on-read (COR) .

For each address, the register bits are identified as either read/write (R/W) or read only (RO), and the value of the

bits on reset are give n.

Table 3 80. Performance Monitor Per Link Register Addressing M ap

* L and P rep re sent hex idec im al digi ts u se d for abso lute ad dres sing in Table 382 through Table 401.

Address*Bit N am e Function Reset

Default

0x8LT21 2 FRM_T_FGSRC F and G Source. Indicates which entity will be the source for

the F an d G values used in handling the ABCD bits.

0 = Host programmed.

1 = Sourced from the Rx system interface.

The F and G programming can be implied by the system

interface only when u sing th e A SM CHI or the parallel sys-

tem interface.

1:0 FRM_T_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will

be the source for the ABCD b its.

00 = Signaling programmed by the host.

01 = Signaling extracted from the Rx line.

10 = Signaling received from the s ystem interface.

Address*Bi t Nam e Function Reset

Default

0x8LT20 15:4 —Reserved. Must write t o 0. 0x000

3 FRM_T_TS16A Time Slot 16 Multifra me Alignment Status. A 0 indicat es

that currently, time slot 16 multiframe alignment i s not estab-

lished. A1 indica tes that c urre ntl y, time slot 16 multiframe

alignment has been established.

2 FRM_T_TS16AIS Time Slot 16 AIS Detecti on S tatus. If time slot 16 multi-

frame alignment is lost, this bit will reflect the detection of AIS

in time slot 16.

1:0 —Reserved. Must write to 0. 00

A ddress Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 RXP = 0

TXP = 1 1 0 PM5 PM4 PM3 PM2 PM1 PM0

L* P* —

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

274 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 3 81. Performance Monitor Per Link Register Address Indexing

Read: for link 1 on the receive p ath, the hexidecimal digit L is 0x0 and the he xidecimal digit P is 0x2.

Table 382. FRM_PMLR1, P erformance Monitor Link Register 1 (R/W)

*See Table 381 fo r value s of L an d P.

Tabl e 383. FRM_PMLR2, Performance Monitor Link Register 2 (R/W)

*See Table 381 fo r value s of L an d P.

Link L P Link L P Link L P Link L P

Receiv e Path (P is even)

1 0x0 0x2 8 0x1 0x0 16 0x2 0x0 24 0x3 0x0

2 0x0 0x4 9 0x1 0x2 17 0x2 0x2 25 0x3 0x2

3 0x0 0x6 10 0x1 0x4 18 0x2 0x4 26 0x3 0x4

4 0x0 0x8 11 0x1 0x6 19 0x2 0x6 27 0x3 0x6

5 0x0 0xA 12 0x1 0x8 20 0x2 0x8 28 0x3 0x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA ———

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC ———

———15 0x1 0xE 23 0x2 0xE ———

Transmit Path (P is odd))

1 0x0 0x3 8 0x1 0x1 16 0x2 0x1 24 0x3 0x1

2 0x0 0x5 9 0x1 0x3 17 0x2 0x3 25 0x3 0x3

3 0x0 0x7 10 0x1 0x5 18 0x2 0x5 26 0x3 0x5

4 0x0 0x9 11 0x1 0x7 19 0x2 0x7 27 0x3 0x7

5 0x0 0xB 12 0x1 0x9 20 0x2 0x9 28 0x3 0x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB ———

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD ———

———15 0x1 0xF 23 0x2 0xF ———

Address*Bi t Nam e Function Re set

Default

0x8LP80 15:0 FRM_PM_IM4[15:0] Pe rf ormance Mo nitoring Registe r FRM_PMLR 4 I nter-

rupt Mask. A 1 masks the corres ponding status bit in the

interrupt status registers (Table 386) from generating an

interr upt. A 0 allows a n interrupt to be generated.

0xFFFF

Address*Bi t Nam e Function Res et

Default

0x8LP81 15:0 FRM_PM_IM5[15:0] Performance Monitor Register FRM_PMLR5 Interrupt

Mask. A 1 masks the corresponding status bit i n interrupt

status registe rs (Table 386) from generating an interrupt. A

0 allows a n interrupt to be generated.

0xFFFF

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
275Agere Systems Inc.  
12 28-Channel Framer Registers (continued)
Table 384. FRM_PMLR3, P erformance Monitor Link Register 3 (R/W)
*See Table 381 fo r  value s of  L an d P.
Address*Bit Name Function Reset 
Default
0x8LP82 15:11 —Reserved. Must write to 0. 00000
10:7 FRM_MHGALIGN[3:0] Handling Group  Alignment Interrupt Mask. A 1 masks 
the corresponding status bit in the interrupt status register 
(Table 400) from generating an interrupt. A 0 allows an 
interrupt to be generated.
0xF
6 FRM_MSEFS Severely Errored Fram e Interrupt Mask. A 1 masks the 
correspondi ng status bit in the interrupt  status register 
(Table 400) from generating an interrupt. A 0 allows an 
interrupt to be generated.
1
5FRM_MFECEPT Functional Element Status Interrupt Mask. A 1 
mask s any and all of the FE status bits in Table 394 and 
Table 395 from generating an interru pt. A 0 allows an 
interrupt to be generated.
1
4:0 FRM_PM_IM6[15:0] Perfor mance Monitor Register FRM_PMLR6 Interrupt 
Mask. A 1 masks th e corresponding status bit in the inter-
rupt st atus register (Table 387) from generating an inter-
r upt.  A 0 allows  an interrupt to be generated.
0x001F
Table 385. FRM_PMLR4, P erformance Monitor Link Register 4 (COR)
Address*Bit Nam e F unction Re set 
Default
0x8LP83 15 FRM_SLIPO Receive Elastic Store Slip Overflow. A 1 indicates that the 
receive elastic store performed a control slip  due to an  ela stic 
store ov erflow c ondition. This signal is set  when  the error occurs 
and is cleared when it is read, if there is not another error during 
the read.
0
14 FRM_SLIPU Recei ve Elastic Store Slip Underflow. A 1 indicates that the 
receive elastic store performed a control slip  due to an  ela stic 
store underflow condition. T his signal is set when the error 
occurs and is cleared when it is read, if there is not another 
error during the read.
0
13 FRM_OOF Out O f Frame. A 1 indicates that the receive framer has lost 
frame alignme nt and is cu rrently searching for a new fra me 
alignment.  Se ction  21.6.1 L os s of Frame Alignment  Criteria on 
page 488 lis ts t he loss  of frame c rite r ia for  the framing bit. 
(T1.231 section 6.1.2.2.1,  G. 706 section 4.1). Excessi ve  
(exceeding the provisionable CRC error count) CR C errors may 
optionally cause a reframe.
In ESF or J-ES F, more than 320 CRC-6 errors in 1 second 
result i n loss of frame alignment. The CRC error count is  p r ov i-
sionable. 
In the CEPT CRC-4 multiframe formats, more than 915 CRC-4 
errors in 1 second result in  loss of frame alignmen t. (G.706 se c-
tion 4.3.2). The CRC error count is provisionabl e.
0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ju ne 2001

276 Agere Sy stem s Inc.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

12 28-Channel Framer Registers (continued)

*See Table 381 fo r value s of L an d P.

0x8LP83 12 FRM_LSFA Loss of Si gnaling Frame Align m ent. DS1: A 1 indicates that

the receive framer is in a loss of signaling superframe alignment

in the

SLC

-96 framing f ormat. This bit is a 0 in all other DS1

framing modes.

SLC

-96 signaling alignment is assumed to hav e

been lo st when multiframe al ignment is lost.

CEPT: A 1 indicat es that the los s o f the CEPT time slot 16

channel associated signaling multiframe structure. CEP T time

slot 16 multiframe alignment is assumed lost when two consec-

utive time slot 16 multiframe alignment patterns (0000) are

received in error, or when time s lot 16 is all zeros for one or two

multiframes. Time slot 16 multiframe alignment is assumed to

have occurred when the fir st time slot 16 m ultiframe alignment

pattern is found in time slot 16 and optionally, the precedin g

time slot 16 contained at least one. (G.732 section 5.2; O.162

section 2.1.3.) This i s the time slot 16 align input from the sig-

naling block.

11 FRM_OAIS O the r Al arm I ndi ca ti on Si gn als . DS1 AIS-CI: A 1 indicates the

receive framer detected alarm i ndication signal customer instal-

lation (AIS-CI). AIS-CI is a repetitive pattern wi th a 1.2 6 s

per iod. It consists of 1.11 s of unframed all ones interleaved

with 0.15 s of all ones mod ified by the A IS-CI signature pattern.

The A IS s ignature pattern is 01111100 11111111 (transmitted

right-to-left at 3 86-bit inter vals). It takes 4 ms to detect AI S-CI.

(T1.231 section D.1.3.)

CEPT RT S16AIS: A 1 indicates the receive framer detected

time slot 16 AIS. Time slot 16 AIS is defined to be fewer than

three zeros in each of two consecutive time slot 16 multiframe

per iods, (G775 section 5.1.1). This i s the tim e slot 16 AIS input

from the signaling block.

Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

Address*Bi t Name Fun ction Reset

Default

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

277Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

*See Table 381 fo r value s of L an d P.

Address*Bit Nam e F unction Re set

Default

0x8LP83 10 FRM_AIS Alarm Indi cation Signal. A 1 ind icates the framer is currently

receiv ing an AIS pattern or receiving an AIS indication on the

TDM bus from the mapper.

DS1: Opti on 0: AIS occurs upon detection of an unframed sig-

nal with a ones density of at least 99.9% for a time between

3 ms and 75 ms. AIS is removed if the signal does not meet the

99.9% ones density or the unframed criteria for a period

between 3 ms and 7 5 ms. (

ANSI

T1.231 section 6.1.2.2.3,

T1.403 section H, G.775 sec tion 5.4.)

Option 1: AIS is detected if the signal has one or less zeros in

24 frames (3 ms/4632 bits). AIS is removed i f the signal has tw o

or more zeros in 24 frames. (

ANSI

G.775 section I.2.)

CEPT: Option 0:AIS is detected when loss of frame alignme nt

occurs and there are two or less zeros in a double frame pe riod

(512 bits per double frame period). AIS is cleared on receipt of a

signal not conforming to the AIS defect criteria. (

ANSI

G.775

section I .2; G. 965 s ection 16.1.2.)

Option 1: AIS is detected when there are two or fewe r zeros in

each of two consecutive double fra me p eriods (512 bits per

double frame period). A I S is cleared w hen ea ch of two consecu-

tive double frame periods contain three or more zeros or the

frame alignme nt signal (FAS) is found. (

ANSI

G.775 section

5.2.)

O pt i on 2 : AIS i s det e ct ed w he n t h e re ar e t hr e e o r le ss zero s in a

four frame period (0.5 ms/1024 bits) and th e signal i s out o f

frame. AIS is cleared i f t her e are fo ur or more zeros in a four-

frame period or the signal is in frame alignment. (

ANSI

G.775

section I.2.)

Option 3: AIS is detected when there are one or fewer zeros in

each of two consecutive double fra me p eriods (512 bits per

double frame period) a nd the FAS i s not dete cted. AIS is

cle ared when each of t wo c onsecutive doubl e fr ame periods

contain three or more zeros or the frame alignment sig nal (FAS)

is found . (

ANSI

G.775 section I.2.)

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

278 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 385. FRM_PMLR4, Performance Monitor Link Regist er 4 (COR) (continued)

*See Table 381 fo r value s of L an d P.

Address*Bi t Name Fun ction Reset

Default

0x8LP83 9 FRM_ORAI Other Remote Alarm Indi cation. A 1 indicates the receive

framer detected an other remote (yellow) alar m. This bit is a 0 in

the modes not indicated below. This bit is s et when the alarm is

detected, and is cleared on a read of this register if the alarm is

not detected during the read.

J-D4 RJYA: The frame bit in frame 12 is a 1 two out of three

consecutive t imes.

ESF, J-ESF RAI-CI:

Option 0: A 1 indicates the receive fram er detected remote

alarm indication cust omer installation (RAI-C I) in the ESF data

link. RAI-CI is a repetitive pattern with a 1.08 second period. It

consists of 0. 99 s of the unscheduled message 00000000

11111111 (RAI in the data link) interleaved with

0.09 s of the RAI-CI signature pattern. The RAI-CI signature

pattern is 00111110 11111111 (transmitted rig ht-to-left). (

ANSI

T1.231 section D.1.2.)

Option 1: A 1 indicates the receive framer detected RAI-CI in

the ES F data link. RAI-CI is a repetitive pattern wi th a 1.0 8 s e c -

ond period. I t consists of 0.99 s of all ones (RAI in the data link)

interleaved with 0.09 s of the RAI-CI signature pattern. The RAI-

CI signature pattern is 00111110 11111111 (transmitted right-

to-left). (

ANSI

T1.231 section D.1.2.)

CEPT RTS16 MFA : Bit 6 of time slot 16 of signaling frame 0 is a

1 for three consecut ive occurrences. The alarm is considered

inactive when bit 6 of time slot 16 of signaling frame 0 is 1 in

less than two consecutive occasions. This is true if time slot 16

is not carrying a payload, e.g., common channel signaling. If

time slot 16 is used f or common channel s ignaling, bit 6 will be

continuously 1. In this case, it will b e possible to inhibit the

remote alarm to prevent false alarm conditions. (O.162 section

2.1.5.) This is t he y - bit input from the signaling blo ck.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

279Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

*See Table 381 fo r value s of L an d P.

Address*Bit Nam e F unction Re set

Default

0x8LP83 8 FRM_RAI Remote Alarm Indication. A 1 indicates the receive framer

detected a remote (yellow) alarm o r det ec ted an RAI i ndication

on the T D M bus from the mapper.

D4: Bit 2 of all time slots is a 0 for one fra me. (

ANSI

T1.403 sec-

tion 9.1.)

DDS: Bit 6 of time s lot 24 is a 0 for 12 frames.

ESF: Option 0: An alternating pattern of eight ones foll owe d by

eight zeros in the ESF data link for 10 cons ec utive times. (

ANSI

T1.403 section 9.1.)

Option 1: A pattern of all ones in the ESF data link for 10 con-

secutive times.

CEPT Basic Frame: RAI is activated when bit 3 of the NOTFAS

frame is 1 RA C consecutive times. RAI is deactiv ated when bit 3

of the NOTFAS fr a m e is a 0 RDC consecu t iv e tim es. RAI ac t iv a-

tion co unt (RAC) and RAI dea ctivation count (RDC) are provi-

sionable in Section Table 313. FRM_PMGR3, Performance

Monit or Global Register 3 (R/W) on page 248.

Option 0: Bit 3 of the NOTFAS frame is a 1 one consecutive

time. RAI is inac tive when bi t 3 is set to a 0.

Option 1: RAI is set on three consecutive ones and deactivated

on three cons ec utive zeros.

Option 2: Bit 3 of the NO TFAS frame is a 1 four consecutive

times. RAI is inact ive when bit 3 is set to a 1 in less than two

consecut ive occasions. (O.162 s ection 2.1.4.)

Option 3: RAI is set on five consecutive ones and deactivated

on five consecutive zeros. (ETS 300.417-1-1.)

CEPT CRC-4 Multiframe: Reception of 1 bit A with a content of

1. (G .965 section 16.1.2)

7 FRM_SA600X1E Sa6 = 00x1 Event. This bit indicates detection of an Sa6 = 00x1

event. The S a6 code is detected synchronously to the CRC-4

multiframe and is no t counted during loss of CRC-4 multiframe

alignment. This det ection is not qualified by Sa5 = 1, unlike bits

6 and 8 of S ec tion Table 394. FRM_PM LR13, Perform anc e

Monitor L ink Re gister 13 (COR) on page 286.

6 FRM_SA6001XE Sa6 = 001x Event. This bit indicates detection of an Sa6 = 001x

event. The S a6 code is detected synchronously to the CRC-4

multiframe and is no t counted during loss of CRC-4 multiframe

alignment. This detection is not qualified by Sa5 = 1, unlike bits

7 and 8 of Table 394

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

280 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

* See Table 381 for values of L and P.

Tabl e 385. FRM_ PMLR4, Performance Monitor Link Register 4 (COR) (continued)

Address*Bit Name Function Reset

Default

0x8LP83 5 FRM_CRCTX CRC-4 Multiframe Alignment Timer Expired. A 1 indicates

th at either the 100 ms or the 400 ms interworki ng timer expired.

It is only active immediately after bas ic fram e alignment is f ound

in CEPT CRC-4 modes. This signal is set when the error

occurs, and is cleared when it is read if there is not another

error during the read.

4 FRM_LTS0MFA Loss of Time Slot 0 CRC-4 Multifr ame Alignment. A 1 indi-

cates the a bsence of CRC-4 multiframe alignment. This bit is

set when basi c fram e alignment has been found and multiframe

alignment is being searched for, or when mul tiframe alignment

is lost but basic frame alignment remains good, or when multi-

frame a lignment is lost.

Note: This is a stored version of the status. It is c leared after

one good multiframe bit is seen.

CRC-4 multifram e alignment is assumed lost when there are

three consecutive errors i n the CRC-4 mult iframe alignment bits

(bit 0 of not-F A S frames 1, 3, 5, 7, 9, and 11). Loss of CRC-4

multiframe alignment may optionall y cause a research for CRC-

4 multiframe alignment without affecting t he current basic frame

alignment.

CEPT with CRC-4 only. In all other modes, this bit is a 0.

3 FRM_TS0MFABE Time Slot 0 Multiframe Alignment Signal Bit Error. A 1

indicates that the rec eive framer detected an error in the CRC-4

multiframe alignment signal. A 0 indicates no errors . Bit 0 of

NO TFAS frames (1, 3, 5, 7, 9, and 11).

2FRM_SESSeverely Errored Secon d (G.826 Annex B). A 1 indicates the

receive framer detected a severely errored second. The events

that can cause an errored second are provisionable for DS1

links in Table 317 and for CEPT links in Table 320. The severely

errored second threshold is provisionable; DS1-SF links in

Table 314 on page249 , DS1- E SF links in Table 316 on

page 249 and CEPT links in Table 319.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
281Agere Systems Inc.  
12 28-Channel Framer Registers (continued)
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)
*See Table 381 fo r  value s of  L an d P.
Address*Bit Nam e F unction Re set 
Default
0x8LP83 1 FRM_BES Burs ty Errored Seco nd. A 1 indicates the receive framer 
detected a bursty errored second. The ev ents that can cause an 
errored s econd are provisionable for D S1 lin ks in Tab le 317 on 
page 249 an d for CEPT links in Table 320 on page 250 .  T he 
severely errored second threshold is provis ionable;  DS1-SF 
lin ks in  Table 314 on page249 , DS1-ESF links in Table 316 on 
page 249 an d CE PT links in Table 319 on page250 .
BES is not valid in any CEPT mode. 
Note: The SES threshold must always  be greater than the ES 
threshold because BES li es  in between (i .e., ES < BES < 
SES).
0
0FRM_ESErrored Second (G.826 Annex B). A 1 indicates the receive 
framer d etected an errored sec ond. T he even ts that can cause 
an errored second are provisionable for DS1  links in S ec ti on 
Tabl e 317. FRM_PMGR7, Performance Monitor Global Register 
7 (R/W) on page 249 and for CEPT links in Section Table 320. 
FRM_PMGR10, P erf ormance Monitor Global Register 10 (R/W) 
on page 250.
0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

282 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 386. FRM_PMLR5, Performance Monitor Link Regist er 5 (COR)

*See Table 381 fo r value s of L an d P.

Address*Bit Nam e Function Reset

Default

0x8LP84 15:14 —Reserved. Must write to 0. 0

13 FRM_LFV Line Form a t Viol ation. A 1 indicates the rec eive framer detected

a bipolar line codin g or excessive zeros vio lat ion. The p erfor -

mance monitor counts all pulses on the BPV signal from the frame

aligner block . This s ignal is s et when the error occ urs and is

cleared when it is read, if there is not another error du r ing the

read. (G.703 Annex A and O.161 section 2.)

12 FRM_FBE Frame-Bit Erro red. A 1 indicates the receive framer detected a

frame bit or frame alignment pattern error. For SF f ormats, either

FT, or FT and FS bits are used and are pr ogr ammabl e. T hi s signal

is set when the error occurs and is cleared when it is read, if the r e

is not another error during the read. In DDS, FT and FS are always

counted as FBEs. The PMON is, however, con figurable as to

whether T S 24 is also counted as a FBE. In CEPT, FAS words can

only generate one FBE .

11 FRM_CRCE CRC Errored. A 1 indicates the receive framer detected a CRC

error. I t is the occurrence of a received CRC code that is no t iden-

tical to the locally calculated code . This signal is set when the error

occurs and is cleared when it is read, if there is n ot another error

during the read. This signal is only v alid in ESF(G.704 s ection A.1)

and CEPT CRC-4 (G.70 4 section A.3) modes.

10 FRM_ECRCE Excessive CRC Errors. A 1 indicates the receive framer detected

an excessive CRC error condition. This signal is set when the

error occurs and is cleared when it is read, if there is not another

error during the read. This signal i s onl y valid in ESF and CEPT

CRC-4 modes. The CRC error count is provisionable. In ESF, an

e xcessive CRC error is defined as ≥320 CRC errors in one sec-

ond. In CEPT, an excessi ve CRC error is def ined as ≥915 CRC

errors i n one second.

9FRM_REBITReceived E Bit = 0. A 1 indicates the receive framer detected an

E bit = 0 in the CEPT CRC-4 modes. This signal is set when the

error occurs and is cleared when it is read if there is not anot her

error during the read. This signal is onl y va lid in CEP T CRC-4

modes.

8 FRM_CREBIT Contin uous Received E Bits. A 1 indicates the detection of a five

second interval containing ≥991 E bit = 0 events in each second.

The E - bit error count is provisionable. The defaults of 991 are

shown.

7FRM_LTFALoss of Transm it Frame Alignment. DS1: Always 0.

CEPT FRM_LTFA: A 1 indicates that the CEPT bifra me a lignment

pattern (alternating 0, 1 in bit 2 of time slot 0) receiv ed from the

system is in error. This alignmen t pattern is required when trans-

mitting the Si or Sa bits transparently. Detection of this condition

may opt iona lly b e disabled.

6FRM_NFANew Frame Alignment. A 1 indicates th e rec eive framer has

reframed. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

283Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 386. FRM_PMLR5, Performance Monitor Link Register 5 (COR) (continued)

*See Table 381 fo r value s of L an d P.

Address*Bit Nam e Function Rese t

Default

0x8LP84 5 FRM_SA7LID Sa7 Link Identification. A 1 indicates that a sequence was fou nd

such that two out of three Sa7 bits are 0. (G.965 secti on 16.1.2.) 0

4 FRM_LLBON Lin e Lo op bac k O n Co de Det ec t. A 1 indicates the receiv e framer

detected the DS1 l ine loopback enable code. The activation signal

consis ts of repetitions on th e pattern 00001 wi th the framing bits

replacing the pattern bits. (T1.403 section 9.3.1.1.) Only applica-

ble in DS1 SF formats.

3 FRM_LLBOFF Line Loopback Off Code Detect. A 1 indicates the receive framer

detected the DS1 line loopback disable code. The deactivation sig-

nal consists of rep etitions on the pattern 001 with the framing bits

replacing the pattern bits. (T1.403 section 9.3.1.2.) Only applica-

ble in DS1 SF formats.

2FRM_AUXPAuxiliary Pattern. DS1 IDLEID: Each of the 24 time slots in a

frame contain the DS1 idle signal, 00010111. (T1.231 s ec tion

6.4.8.)

CEPT AUX P: A 1 indicates the detection of a val id auxiliary pa t -

tern (unframed 10 . . . pattern) in the CEPT mode . When in loss o f

frame alignment state, a n auxiliary patt ern is detected when more

than 255 10 patterns are detected in a 512-bit interval. The alarm

is disabled when three or more non-10 patterns a r e detec ted in a

512-bit interval. The s earc h for AUX P is synchro n ized t o th e fi rst

alternating 10 pa ttern found. (ETS 300 233 section 8.2.2.2, O.151

section 2.4.)

0x8LP84 1 FRM_LOS Lo s s of Sign a l. A 1 indicates that the receive line decoder has

detecte d a loss of signal condition. T his s tatu s i s only v alid in the

dual-rail mode of operation.

DS1: Loss of signal occurs when, for 100 contiguous pulse posi-

tions, there are no pul ses of eithe r the positive or negative polarity

at the line interface. The loss of signal defect is removed upon

detecting 13 pulses over 10 0 pulse positions following the receipt

of a pulse, and there is no 100 pulse position interval where there

were no pulses. (T1.231 s ection 6 .1.2. 1.1, G.775 section 4.3.)

CEPT: Loss of signal occurs when, for 100 consecutive pulse

positions, there are no pulses of either the positive or negative

polarity at the line interface. The loss of signal defect is r emoved

when there are puls es in a 100 consecutive pulse positi on period

(G.775 section 4.2.). Note that the defect is set and cleared at the

end define d sample period.

0FRM_BOMRBit Or iented Message Received . A 1 indicates a B OM has been

received in th e ESF data link bits and FRM_RBOM[7:0]

(Table 399) should be read. A BOM i s defined in

ANSI

T1.403 as a

0xxxxxx0 11111111 pattern (received right-to-left) repeated

10 consecutive t imes. The 0 x x xxxx0 pattern is saved in the

FRM_RBOM[7:0] regi ster (Table 399 on page287 ) upon t he

10th occurrence of the BOM message.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

284 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 387. FRM_PMLR6, Performance Monitor Link Regist er 6 (COR)

*See Table 381 fo r value s of L an d P.

Tabl e 388. FRM_ PMLR7, Performance Monitor Link Register 7 (COR)

*See Table 381 fo r value s of L an d P.

Address*Bi t Name Fu nction Reset

Default

0x8LP85 15:5 —Reserved. 0

4 FRM_FDL_RAI ESF_FDL_RAI/Yellow Alarm. A 1 indicates the receive

framer detected the ESF_FDL_RAI/yell ow alarm code in the

payload. T his code is de fined in

ANSI

T1.403-1995 as a

00000000 11111111 pattern in the fa cility data link (received

r igh t-to-left). T his si gnal is set when the patte rn is de tected

(10 consecutiv e times) and is cleared when it is read if the pat-

tern is n o longer being detect ed.

3 FRM_FDL_PLBON ESF_FDL Payload Loopback Enab l e. A 1 indicates the

receive framer detected the ESF_FDL pa yload loopback

enable code in the payload. This code is defined in

ANSI

T1.4 03-1995 as a 00010100 11111111 pattern in the

facilit y data link ( r eceived right -t o- le f t ). This si gnal is set when

the pattern is dete cte d (10 consecutive times) and is cleared

w hen it is read if the pattern is no longer being det ected. T his

could also be set by FF_PLB (manual PLB indication) input.

2 FRM_FDL_PLBOFF ESF_FDL Payload Loopback Di sa bl e. A 1 indicates the

receive framer detected the ESF_FDL pa yload loopbac k d i s-

a ble code in the payload. This code is defined in

ANSI

T1.4 03-1995 as a 00110010 11111111 pattern in the

facilit y data link ( r eceived right -t o- le f t ). This si gnal is set when

the pattern is dete cte d (10 consecutive times) and is cleared

w hen it is read if the pattern is no longer being det ected.

1 FRM_FDL_LLBON ESF_FDL Line Loopback Enable. A 1 indicates the receive

framer detecte d the ESF_FDL line loopback enable code in

the payload. This code is defined in

ANSI

T1. 403-1995 as a

00001110 11111111 pattern in the fa cility data link (received

r igh t-to-left). T his si gnal is set when the patte rn is de tected

(10 consecutiv e times) and is cleared when it is read if the pat-

tern is n o longer being detect ed.

0 FRM_FDL_LLBOFF ESF_ FDL Line Loopback Disable. A 1 indicates the receive

framer detecte d the ESF_FDL line loopback disable code in

the payload. This code is defined in

ANSI

T1. 403-1995 as a

00111000 11111111 pattern in the fa cility data link (received

r igh t-to-left). T his si gnal is set when the patte rn is de tected

(10 consecutiv e times) and is cleared when it is read if the pat-

tern is n o longer being detect ed.

Address*Bi t Name Function Reset

Default

0x8LP86 15:0 FRM_BPV[15:0] Bipolar Violation Counter. This reg ister contains the 16-bit

count of received bipolar violations, line code violations, and

excessive zeros.

0x0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

285Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 389. FRM_PMLR8, Performance Monitor Link Register 8 (COR)

*See Table 381 fo r value s of L an d P.

Tabl e 390. FR M_PMLR9, Performance Monitor Link Register 9 (COR)

*See Table 381 fo r value s of L an d P.

Table 391. FRM_PMLR10, Performance Monitor L in k Register 10 (COR)

*See Table 381 fo r value s of L an d P.

Table 392. FRM_PMLR11, Performance Monitor L in k Register 11 (COR)

*See Table 381 fo r value s of L an d P.

Table 3 93. FRM_PMLR12, Performance Monitor Link Regi ster 12 (COR)

*See Table 381 fo r value s of L an d P.

Address*Bit Name Function Reset Defau lt

0x8LP87 15:0 FRM_FBEC[15:0] Frame Bit Error Coun ter.

DS1: This reg ister contains the 16-bit count of received

frami ng bit errors. Framing bit errors are not counted dur-

ing loss of frame alignment. (T1.231 section 6.1.1.2.2.)

CEPT: This register contains the 16-b it count of received

frame alignment signal errors. Optionally, bit 2 of non-FAS

fram es can be counted.

Note: A FAS with errors in two or more bit positions is

only counted once.

0x0

Address*Bit Name Function Reset Default

0x8LP88 15:0 FRM_CEC[15:0] CRC Err or Counter . T his register contains t he 16-bit count

of receiv ed CRC errors. CRC errors are not counted during

loss of CRC mult iframe alignment.

0x0

Address*Bit Name Function Reset Default

0x8LP89 15:0 FRM_REC[15:0] Rece ive E-bit Counter. This register contains the 16-bit

count of received E bit = 0 events. E bit = 0 eve nts are n ot

counted during loss of CEPT CRC-4 multiframe alignment.

0x0

Address*Bit Name F un ction Reset Default

0x8LP8A 15:0 FRM_CETE[15:0] Sa6 = 00x1 Event Co un ter. This register con tains the

16-bit cou nt of received Sa6 = 00x 1 events. The Sa6

code is detected synchronously to the CRC-4 multiframe

and is not counted during loss of CRC-4 multiframe align-

ment. T his detec tion is not qualified by S a5 = 1.

0x0000

Address*Bit Name Function Reset Default

0x8LP8B 15:0 FRM_CENT[15:0] Sa6 = 001x Event Counter. This register contains the

16-bit count of receiv ed Sa6 = 001x ev ents. The Sa6 code

is detected synchronously to the CRC-4 multiframe and is

not counted during loss of CRC-4 multiframe alignment.

This detection is not qualified by S a5 = 1.

0x0000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

286 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

The regis ter in Table 394 provides a status indication of functional elements (FE) exchanged between the access

digital section and the exchange te rmination (ET) as de fined in ETS 300 233 sec tion 9.3 and T a bl e 2. T he s e are

decoded from the A, Sa5, and Sa6 bits. The Sa6 code words are synchro nized to the CRC-4 multiframe.

Table 394. FRM_PMLR13, Performance Monitor Link Regi ster 13 (COR)

*See Table 381 fo r value s of L an d P.

Address*Bit Name Function

(A, SA5, S A6[1:4]) Reset

Default

0x8LP8C 15:14 —Reserved. Mu st write to 0. 0 0

13 FRM_FE_OP Defect FCET in the ET or FCDLd in the Digital Link Between V3

and V3 or Defect FCDLu Between the V3 and V3. AIS. 0

12 FRM_FE_N Recepti on of AIS at V3 Reference Point of LT and FC4 Simulta-

neously. (0, 1, 1111.) 0

11 FRM_FE_M Reception of AIS at V3 Reference Point of LT (Reaction to FCDL

or FCET). (1, 1, 1111.) 0

10 FRM_FE_L LOS at Line Side of LT (FC1). AUXP. 0

9FRM_FE_KLos s of Power at NT1 and LOS/LFA a t TE Simult aneously. (1, 1,

1000.) 0

8FRM_FE_ILoss of Power at NTT. (0, 1, 1000.) 0

7FRM_FE_HSimultaneous FC3 and FC4. (0, 1, 1110.) 0

6FRM_FE_GLOS/LFA at T Reference Point of NT1. (0, 1, 1100.) 0

5FRM_FE_FLOS/LFA at V3 Reference Point of ET. (1, 0, 0000. ) 0

4FRM_FE_ELOS at Line Side of NT1 or at V3 Reference Po int of LT Only. (1,

1, 1 110. ) 0

3FRM_FE_DLOS/LFA at TE. (1, 1, 00xx.) 0

2FRM_FE_CUnintentional Loopback. (x, 0, xxxx.) 0

1FRM_FE_BNorm al Operation of t he ET. (x, 0, 0000.) 0

0FRM_FE_ANormal Operation of t he D S. (x, 1, 00xx.) 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

287Agere Systems Inc.

12 28-Channel Framer Registers (continued)

The regis ter in Table 395 provides a status indication of functional elements ( FE) exchanged between the access

digital section and the e xchange termination (ET) as defined in ETS 300 233 sec tion 9.3 and Tables 3 and 4 .

Table 395. FRM_PMLR14, Performance Monitor Link Regi ster 14 (COR)

*See Table 381 fo r value s of L an d P.

Table 396. FRM_PMLR15, Performance Monitor L in k Register 15 (COR)

*See Table 381 fo r value s of L an d P.

Table 397. FRM_PMLR16, Performance Monitor L in k Register 16 (COR)

*See Table 381 fo r value s of L an d P.

Table 398. FRM_PMLR17, Performance Monitor L in k Register 17 (COR)

*See Table 381 fo r value s of L an d P.

Table 399. FRM_PMLR18, Performance Monitor L in k Register 18 (COR)

*See Table 381 fo r value s of L an d P.

Address*Bit Name Function

(A, Sa5, Sa6[1:4], E) Reset

Default

0x8LP8D 15:9 —Reserved. Must write to 0. 0x000

8FRM_FE_YSimultaneous Occurrence of FE_W and F E_ X. (x, 1 , 0011, x.) 0

7FRM_FE_XCRC Error Detected at T Reference Point of N T1. (x, 1, 0 010, x. ) 0

6FRM_FE_WCRC Error Reported fro m T E . (x , 1, 0001, x. ) 0

5FRM_FE_VCRC Error Information from ET. (x, 0, 0000, 0.) 0

4FRM_FE_UCRC Error Report from NT1 Line S i de. (x, 1, xxxx, 0.) 0

3FRM_FE_TLoo pback Rel ease Command . (x, 0, 0000, x.) 0

2FRM_FE_SLoopback Ack nowledge. (1, 0, xxxx, x.) 0

1FRM_FE_RLoopb a ck 2 Command. (1, 0, 1010, x.) 0

0FRM_FE_QLoo pback 1 Co mm and . (1, 0, 1111, x.) 0

Address*Bit Name Function Reset

Default

0x8LP8E 15:0 FRM_ESC[15:0] Errored Second Counter. This register contains the 16-bit count

of errored seconds. 0x0000

Address*Bit Na me Fun ction Reset

Default

0x8LP8F 15:0 FRM_BESC[15:0] Bursts Errored Second Counter. This register contains the

16-bit count of bursty errored seconds. 0x0000

Address*Bit N am e Function Reset

Default

0x8LP90 15:0 FRM_SESC[15:0] Severely Err ored Second Counter. This regis ter contains the

16-bit count of se verely errored seconds. 0x0000

Address*Bit Nam e Function Reset

Default

0x8LP91 15:8 —Reserved. Must write to 0. 0 x00

7:0 FRM_RBOM[7:0] Received Bit-Oriented Messa ge (0xxxxxx0). Note that only

storing the 8 bits that contain actual data, the first eight ones are

not stored.

0x00

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

288 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 400. FRM_PM LR19, Performance Monitor L ink Register 19 (COR)

This register a pplies to the receive path only.

*See Table 381 fo r value s of L an d P.

Table 401. FRM_PMLR20, Performance Monitor L in k Register 20 (COR)

*See Table 381 fo r value s of L an d P.

12.11 R ece ive Fac ility Data Lin k Configur ation and Sta tus Regi sters

Table 4 02. Receive Facili t y Data Link Register A ddressing Map

* L and R represent hexidecimal digits u sed for absolu t e a ddr ess ing in Table 404 through Table 408.

Address*Bit Name Function Reset

Default

0x8LP92 15:5 —Reserved. Must write to 0. 0x000

4:1 FRM_HGALIGN[3:0] Indicates HG Alignment f or the Associated HG on Each

Link. The status will be given for a particular link a ny time

that link appears on the TDM bus. A 1 in any bit position indi-

cates that al ignm ent ha s been achieved. 0 indicates al ign-

ment is lost or handl ing groups are disabled.

0000

0FRM_SEFSSeverely Errored Frame Status. (See

ANSI

T1.403

9.4.2.2.2 for ESF and T1.231 6.1.2.2.2 fo r SF.) 0

Address*Bit Name Fu nction R eset

Default

0x8LP93 15:13 —Reserved. Must write to 0. 000

12:7 FRM_G[6:1] PRM Message Bit G6—G1. 0

6FRM_SEPRM Message Bit SE. 0

5FRM_FEPRM Message Bit FE. 0

4FRM_LVPRM Message Bit LV. 0

3FRM_SLPRM Message Bit SL. 0

2FRM_LBPRM Message Bit LB. 0

1FRM_N1PRM Message Bit N1. 0

0FRM_N0PRM Message Bit N0. 0

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 RXP = 0 1100RDL3RDL2RDL1RDL0

L* R* —

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

289Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 403. Rece ive Path Facility Data Link Registers Address Indexing

Read: for link 1, the hexidecim al digi t L is 0x0 and the hexidecimal digit R is 0x2.

Table 404. FRM_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1 —5 (RO)

*See Table 403 fo r value s of L an d R .

Table 405. FR M_RF DLLR6, Receive FDL Link Register 6 (R/W)

*See Table 403 fo r value s of L an d R .

Table 406. FR M_RF DLLR7, Receive FDL Link Register 7 (RO)

*See Table 403 fo r value s of L an d R.

Link L R Link L R Link L R Link L R

1 0x0 0x2 8 0x1 0x0 16 0x2 0x0 24 0x3 0x0

2 0x0 0x4 9 0x1 0x2 17 0x2 0x2 25 0x3 0x2

3 0x0 0x6 10 0x1 0x4 18 0x2 0x4 26 0x3 0x4

4 0x0 0x8 11 0x1 0x6 19 0x2 0x6 27 0x3 0x6

5 0x0 0xA 12 0x1 0x8 20 0x2 0x8 28 0x3 0x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA ———

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC ———

———15 0x1 0xE 23 0x2 0xE ———

Address*Bit Name F unction Reset

Default

0x8LRC0 15:0 FRM_RXS0[15:0] Rx Stack Data 0. 0x0

0x8LRC1 15:0 FRM_RXS1[15:0] Rx Stack Data 1. 0x0

0x8LRC2 15:0 FRM_RXS2[15:0] Rx Stack Data 2. 0x0

0x8LRC3 15:0 FRM_RXS3[15:0] Rx Stack Data 3. 0x0

0x8LRC4 15:0 FRM_RXS4[15:0] Rx Stack Data 4. 0x0

Address*Bit Na m e Fun ction Reset

Default

0x8LRC5 15:1 —Reserved. Must write to 0. 0x0

0 FRM_RXCRCSM CEPT CRC-4 Stack Mode. When se t to 0, the Sa bits will

be stored based on multiframe alignment. If multiframe

alignment is lost, the stack will not be made avai lable to the

host. W hen set to 1, the Sa bits will be stored based on an

arbitrary multiframe al ignment when only basic frame

alignment can be established.

Address*Bit Nam e Fun ction Reset

Default

0x8LRC6 15:1 —Reserved. Reads 0. 0x0

0 FRM_RXSA Rx Stack Available. A 1 indicates that the Rx stack is available

for reading. 0 indicat es t hat the stack is being updated and

should not be read. In order to prevent a mix of old and new

data being read the host should ver ify that this bit is set to 1

before continuing to read the stack.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

290 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 407. FRM_RFDLLR8, Receive FDL Link Register 8 (COR)

*See Table 403 fo r value s of L an d R .

Table 408. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W)

*See Table 403 fo r value s of L an d R .

12.12 Transmit Facility Data Link Configuration and Status Registers

Table 409. Transm it Facility Data Lin k Register Addressing Map

* L and R represent hexidecimal digit s used for absolu t e a ddr ess ing in Table 411 through Table 415.

Table 410. Transm it Path Facility Data Link Registers Address Indexing

Read: for link 1, the hexidecim al digi t L is 0x0 and the hexidecimal digit T is 0x3.

Tabl e 411. FRM_TFDLLR 1—FRM_TFDLR5, Transmit FD L Link Registers 1—5 (COR)

*See Table 410 fo r value s of L an d T.

Address*Bit Name Fu nction Reset

Default

0x8LRC7 15:1 —Reserved. Reads 0. 0x0

0 FRM_RXSR_IS Rx Stack Ready In terrupt. A 1 indicates that the Rx stack has

been filled with data following the format of the associated lin k. 0

Address*Bit Name F un ction Re set

Default

0x8LRC8 15:1 —Reserved. Must write to 0. 0x0

0 FRM_MRXSR Mask Rx Stack Ready Interrupt. A 1 masks the Rx stack

ready interrupt. 1

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 TXP = 1 1101TDL3TDL2TDL1TDL0

L* T* —

Link L T Link L T Link L T Link L T

1 0x0 0x3 8 0x1 0x1 16 0x2 0x1 24 0x3 0x1

2 0x0 0x5 9 0x1 0x3 17 0x2 0x3 25 0x3 0x3

3 0x0 0x7 10 0x1 0x5 18 0x2 0x5 26 0x3 0x5

4 0x0 0x9 11 0x1 0x7 19 0x2 0x7 27 0x3 0x7

5 0x0 0xB 12 0x1 0x9 20 0x2 0x9 28 0x3 0x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB ———

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD ———

———15 0x1 0xF 23 0x2 0xF ———

Address*Bit Na me Function Reset Default

0x8LTD0 15:0 FRM_TXS0[15:0] Tx Stack Data 0. 0x0000

0x8LTD1 15:0 FRM_TXS1[15:0] Tx Stack Data 1. 0x0000

0x8LTD2 15:0 FRM_TXS2[15:0] Tx Stack Data 2. 0x0000

0x8LTD3 15:0 FRM_TXS3[15:0] Tx Stack Data 3. 0x0000

0x8LTD4 15:0 FRM_TXS4[15:0] Tx Stack Data 4. 0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

291Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 412. FRM_TFDL LR6, Transmit FDL Link Register 6 (R/W)

*See Table 410 fo r value s of L an d T.

Table 413. FRM_TFDL LR7, Transmit FDL Link Register 7 (R/W)

*See Table 410 fo r value s of L an d T.

Address*Bi t Nam e Function Reset

Default

0x8LTD5 15:8 —Reserved. Must write to 0. 0x0

7 FRM_SA8SC Sa8 Source Contro l. A 1 indicates that Sa8 is sourced from t his

block. 0 indicates that S a8 is so urce d from the framer Sa stack. 0

6 FRM_SA7SC Sa7 Source Contro l. A 1 indicates that Sa7 is sourced from t his

block. 0 indicates that S a7 is so urce d from the framer Sa stack. 0

5 FRM_SA6SC Sa6 Source Contro l. A 1 indicates that Sa6 is sourced from this

block. 0 indicates that S a6 is so urce d from the framer Sa stack. 0

4 FRM_SA5SC Sa5 Source Contro l. A 1 indicates that Sa5 is sourced from t his

block. 0 indicates that S a5 is so urce d from the framer Sa stack. 0

3 FRM_SA4SC Sa4 Source Contro l. A 1 indicates that Sa4 is sourced from t his

block. 0 indicates that S a4 is so urce d from the framer Sa stack. 0

2 FRM_TXCRCSM CEPT CRC-4 Stack Mod e. When set to 0, the Sa bits will be

tr a n smi tted based on bei ng act ive . If MFA is lost, the stac k w ill

not be transmitted. When set to 1, the Sa bits will be transmitted

based on BFA on ly .

1FRM_ASRCAlignment S ou rce. A 1 indicates that the MFA and BFA will be

used to determine if a BOM or stack is transmitted. A 0 indicates

that, when enabled for insertion, BO Ms and st acks will be

inserted whenever the TDM data is reques ted.

0FRM_DS1IDS1 Insertion. A 1 enables this block to insert the contents of

the stack into the associated DS1 lin k. For

SLC

-96 li nks, D bits

will be inserted given the associated stac k forma t. For DDS

links, data-link bits will be i ns erted given the associated stack

format. For other DS 1 link types, this bit has no eff ect . A 0 d is-

ables this block from inserting D bits or data link bits into the

associated link.

Address*Bit Name Function Reset

Default

0x8LTD6 15:7 —Reserved. Mu st write to 0. 0x000

6FRM_BOMETransmit Bi t Oriented Message Enable. A 1 indicates that the

BOM message register has been initialized and should be transmit-

ted on the data link of the ESF frame. The pattern will continue to

be transmitted until the enable is removed. When set to 0, the BOM

transmission will stop immed iately without completing the current

pattern transmission or wit hout completing the serie s of 10 pa t-

terns.

5:0 FRM_TBOM[5:0] Transmit Bi t Oriented Messag e. Indicat es t he conte nts of t he

BOM to be tra n smitted when enabled with FRM_B OME. A pattern

of 111110 implies a BOM of 0111110 011111111 with the right

most bit b eing transmitted first.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

292 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 414. FRM_TFDL LR8, Transmit FDL Link Register 8 (RO/COW)

*See Table 410 fo r value s of L an d T.

Table 415. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W)

*See Table 410 fo r value s of L an d T.

12.13 System Interface, Arbiter, and Frame Formatter Mapping

Table 416. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map

* L and P represent hexidecimal digi ts use d for absolute addressing in Table 419 through Table 425.

Address*Bi t Name Function Reset

Default

0x8LTD7 15:2 —Reserved. Must write to 0. 0000000

0000000

1 FRM_BOMC_IS BOM Complete I nterrupt. ( Clear on write. ) A 1 indicates that the

BOM register contents have been transmitt ed 10 tim es over the

data link of the ES F frame.

0 FRM_TXSE_IS Tx Stack Empty Interrupt. (Clear on write.) A 1 i ndicates t hat

the Tx st a ck is e mp ty. 0 i ndi c a te s th a t the host has fin i s hed

updati ng the stack. The Tx dat a l ink block sets this bit when the

stack is empty and needs to be filled if the D bits or Sa bits

require c hanging. If th e stack is not refilled, the old data wi ll be

retran smitted.The new data ca n b e written anytime without inter-

fering with the current transmission. The stack needs to be

update d within 9 ms for a

SLC-

96 link or 4 ms for a CEPT link in

order for the new information to be transmitted in the next double

multiframe.

Address*Bi t Name Function Reset

Default

0x8LTD8 15:2 —Reserved. Must writ e to 0. 0000000

0000000

1 FRM_BOMC_IM Mask BO M Complete Interrupt. A 1 masks the BOM complete

interrupt, FRM_ BOMC. 1

0 FRM_TXSE_IM Mask Tx Stack Empty Interrupt. A 1 masks the Tx stack empty

interrupt, FRM_TXSE. 1

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 RXP=0/TXP=1 1 1 1 0 0 SYS2 SYS1 SYS0

L* P* —

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

293Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 417. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing

Read: for link 1 on the receive p ath, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.

12.14 System Interface Per Link Registers

Table 418. FRM_SYSLR1, System Interface Link Register 1 (R/W)

*See Table 417 fo r value s of L an d P.

Link L P Link L P Link L P Link L P

Receiv e Path (P is even)

1 0x0 0x2 8 0x1 0x0 16 0x2 0x0 24 0x3 0x0

2 0x0 0x4 9 0x1 0x2 17 0x2 0x2 25 0x3 0x2

3 0x0 0x6 10 0x1 0x4 18 0x2 0x4 26 0x3 0x4

4 0x0 0x8 11 0x1 0x6 19 0x2 0x6 27 0x3 0x6

5 0x0 0xA 12 0x1 0x8 20 0x2 0x8 28 0x3 0x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA ———

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC ———

———15 0x1 0xE 23 0x2 0xE ———

Transmit Path (P is odd))

1 0x0 0x3 8 0x1 0x1 16 0x2 0x1 24 0x3 0x1

2 0x0 0x5 9 0x1 0x3 17 0x2 0x3 25 0x3 0x3

3 0x0 0x7 10 0x1 0x5 18 0x2 0x5 26 0x3 0x5

4 0x0 0x9 11 0x1 0x7 19 0x2 0x7 27 0x3 0x7

5 0x0 0xB 12 0x1 0x9 20 0x2 0x9 28 0x3 0x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB ———

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD ———

———15 0x1 0xF 23 0x2 0xF ———

Address*Bit Nam e Function Reset

Default

0x8LPE0 15 —Reserved. Must write to 0. 0

14:8 FRM_BYOFF[6:0] CHI Byte Offset. Thi s bit is on ly applicable in t he CHI m ode. 0000000

7—Reserved. Must write to 0. 0

6:4 FRM_OFF[2:0] CHI Bit Offset. 000

3:2 —Reserved. Must write to 0. 0

1FRM_HALFOFFHalf Bit O ffset. When set to 1, an offset of 1/2 bit is added to

offsets. 0

0FRM_QUAROFFQuarter Bit Offset. When set to 1, a n offset of 1/4 bit is

added to the offsets. CHI CM S mode only. 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

294 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 419. FRM_SYSLR2, System Interface Link Register 2 (R/W)

This regis ter applies t o the receive path only, insert ed in the transmit system int er face on demand.

*See Table 417 fo r value s of L an d P.

Address*Bit Nam e Function Reset

Default

0x8LPE1 15 FRM_CEPTMAIS Transmit CEPT TS16 AIS.

0 = No act ion.

1 = Time slot 16 is forced to all o nes.

14 FRM_CEPTAAIS Transmit CEPT TS16 AIS on Loss of MFA.

0 = No act ion.

1 = Time slot 16 is forced to all o nes when time s lot 16 mul -

tiframe alignment i s lost.

13 FRM_MANAIS Transm it System AIS.

0 = No act ion.

1 = Transmit system AIS to the system.

12 FRM_CEPTSTMP Transmit System CEPT TS1 6 S tomp.

0 = No act ion.

1 = If upper or lower nibble of time slot 16 is 0000 then it is

changed to 1111 toward the transmit system interface.

11:0 —Reserved. Must wri te to 0. 0x000

Table 420. FRM_SYSLR3—FRM_SYSLR6, System Interface Link Registers 3—6 (R/W)

Address*Bit Name Function Reset

Default

0x8LPE2 15:0 —Reserved. Must wri te to 0. 0x0000

0x8LPE3 15:0 —Reserved. Must wri te to 0. 0x0000

0x8LPE4 15:0 —Reserved. Must wri te to 0. 0x0000

0x8LPE5 15:0 —Reserved. Must wri te to 0. 0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

295Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.15 Arbiter Framer Per Link Registers

Table 421. FRM_ARLR1, Ar bite r Link Register 1 (R/W)

*See Table 417 fo r value s of L an d P.

Address*Bit Nam e Function Rese t

Default

0x8LPF0 15 FRM_LNK_ENA Link Enable .

0 = Link is disable d.

1 = Link is enabled.

14 FRM_LNK_TRANSP Tr ansp arent Mode Selection.

Switching:

0 = The link is in a nontransp arent mode. (Regenerate

framing bits and CRC bits.)

1 = The link is in transparent mode. (Flow through

framing bits and CRC bits.)

Transport:

0 = Nontransparent mode (regenerate CRC bits and

flow through framing bits).

1 = Trans parent mode (flow t hrough f raming bits and

CRC bits).

13 FRM_LNK_RESTARTN Re start Link.

0 = Restart the link.

1 = Nor mal operational mode for the link.

12 FRM_LNK_REFRAME Force Reframe.

0 = Nor mal operational mode for the link.

1 = Link is forced to reframe.

11:10 —Reserved. Must write to 0. 0

9 FRM_ICKEDGE Input Clock Edge Selection.

0 = Sample data on risi ng edge of input clock.

1 = Sam ple data on falling edge of input clock.

8:0 —Reserved. Must writ e to 0. 000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

296 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W)

*See Table 417 fo r value s of L an d P.

Address*Bi t Name Function Reset

Default

0x8LPF1 15 FRM_ESF_CRC_EN CRC Framing Enable .

D S1 Modes: ESF CRC framing algorithm enable:

0 = ESF CRC fr aming disabled.

1 = ESF CRC fram ing enab led. (Enables inclusion of CRC

in t he frame search algorithm.)

CE PT Modes: CRC-4 Multifra me:

0 = Multiframe reframe disabled.

1 = Multiframe r eframe enabled. (Enables the inclusion of

the following criteria to the CEPT loss of multiframe crite-

r ia. Three consecutive multiframe a lignment pattern bit

error s will cause a search for a new multiframe alignment.

Basic frame alignment is no t lost. )

14 FRM_FAST Fast Frame M ode.

D S1 M odes :

0 = Disable qui ck fra me recovery.

1 = Enable quick frame recovery as follows:

D 4 and J-D4: 36 fewer frame bits are checked.

SLC-96: Eighteen fewer FT bits are checked during the

search for FT framing.

D DS: No chan ge.

CEPT Modes:

0 = Disable qui ck fra me recovery.

1 = This bit enables the (n + 2) framing research algorithm

as defined in the note in Recommendation G.706 section

4.1.2. W hen an FAS is found in fram e n, frame (n + 1) is

checked to ensure that it is a non-FAS frame and frame

(n + 2) is checked for FAS. Failure to meet either of these

con dit ions results in a new search in frame (n + 2).

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

297Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)

*See Table 417 fo r value s of L an d P.

Address*Bi t Name Function Reset

Default

0x8LPF1 13:12 FRM_OPT[1:0] Frame Op tio ns.

D S1 M ode:

00 = The frame aligner will not frame up until all mimics

are gone.

01 = Tim e-out algorithm is enabled. A counter is started

w hen, for the f irst time, one of th e 1 9 3-bit p ositions con-

tain s a sequence long enough to declare fr ame but is pre-

vented from doing so b y the presence of a mimic. The

p rovisionable counter sets a tim e limit for mimics to go

away. If there are still mimics, a candidate bit position that

has me t th e minimum fra ming requirements i s chosen and

fram e alignment is made t o that position. See

FRM_TO[7:0] (Table 305).

Oth ers reserved.

CEPT Mode:

00 = No change.

01 = Enables an ex tra NOTFA S frame check. This can

prevent frame alignment on PRBS patt erns which contain

a pseudoframing pattern. The CEPT fra ming sequence

now becomes:

Find FAS (n).

Verify NOTFAS frame (n + 1).

Verify second FAS in frame (n + 2).

Verify second NOTFAS frame (n + 3).

Oth ers reserved.

11 FRM_FBE_MODE DDS FBE Mode.

0 = Allows t w o FBEs to be detected in a frame in DDS

mode. One FBE for t he frame bit (FT and FS) and one

FBE for the time slot 24 f rame alignment s i gnal.

1 = Only 1 FBE is detected in a frame in DDS mode.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

298 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)

*See Table 417 fo r value s of L an d P.

Address*Bi t Name Function Reset

Default

0x8LPF1 10:8 FRM_LF_CRT[2:0] Loss of Frame Criteria.

D S1 M ode:

000 = 2 errored framing bits o ut of 4 FT and FS bits.

001 = 2 errored framing bits o ut of 5 FT and FS bits.

010 = 2 errored framing bits o ut of 6 FT and FS bits.

011 = 3 errored framing bits out of 12 FT, F s, a nd channel

24 FA S bits (DDS only).

100 = 2 errored framing bits o ut of 4 FT bits only.

101 = 2 errored framing bits o ut of 5 FT bits only.

110 = 2 errored framing bits o ut of 6 FT bits only.

111 = 4 errored framing bits out of 12 FT, FS, and channel

24 FA S bits (DDS only).

CEPT Mode:

000 = 3 consecutive errored FAS patterns.

x01 = 3 consecutiv e errored FAS patterns or 3 consecu-

tive errored NOTF AS bits (bit 2).

x10 = 3 consecutive errored frames (FAS and NOTFAS).

Oth ers reserved.

7—Reserved. Must write to 0. 0

6 FRM_AUTO_AIS Auto AIS.

0 = Auto AIS is disa bled.

1 = Auto AIS is enabled.

W hen auto AIS is enabled, the receive arbiter data is

forced to 1 when out of frame.

5:4 FRM_RAIL3_DEC[1:0] Th i rd Rai l Option.

00 = Third input signal to the frame aligner is ignored.

01 = Third input is bipolar violations (in the CMI mode,

C RVs are also inc luded on the RBPV input, but not

pas se d through the frame aligner).

10 = Third rail is frame sync used to indicate time s lot

alignment. The multiframe alignment is determined b y the

frame sync.

11 = Third rail is frame sync used to indicate framing bit

position. Multiframe alig nment i s searched for expedited

by the fram e sync.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

299Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)

*See Table 417 fo r value s of L an d P.

Table 423. FRM_ARLR3, Ar bite r Link Register 3 (R/W)

This register applies to the transmit path only.

*See Table 417 fo r value s of L an d P.

Address*Bi t Name Function Reset

Default

0x8LPF1 3:0 FRM_MODE[3:0] Framing Mode.

0000 = Nonalign 256 bit.

0001 = CEPT basic frame.

0010 = CEPT with CRC-4 and 100 ms timer.

0011 = CMI.

0100 = CEPT with CRC-4 and 400 ms timer.

0101 = Reserved. (Future J2 - G.704.)

0110 = Reserved. (Future J2 - NTT Y.)

0111 = Reserved.

1000 = Nonalign 193 bits.

1001 = SF (FT bits only).

1 010 = J-ESF.

1 011 = ESF.

1100 = D4.

1101 = J-D4 (SF with Japanese Yellow Ala rm).

1110 = DDS.

1 111 = SLC-96.

1011

Address*Bit Name Function R eset Default

0x8LPF2 15 FRM_TP_CK_

SRC_EN Framer Transmi t Path Clock Source En able.

0 = FRM_T P_ C K_SRC bit is disabled. FRM_SW_T RN

(Table 301) bit controls clock source.

1 = FRM_TP_ CK_ SRC bit is enabled. FRM_SW_T RN bit

is ignored.

Transmit path clock and data is selected with bits

FRM_ TP_CK _S RC and FRM_TP_DD_SRC.

14 FRM_TP_CK_

SRC Transmit Path Clock Source.

0 = Transmit clock comes from the frame aligner (transport

applications).

1 = Transmit clock comes from the system interface

(switching applications).

13 FRM_TP_DD_

SRC Transmit Path Default Data Source.

0 = Transmit data comes from the frame aligner (transport

applications).

1 = Transmit data comes from the system interf ace (switc h-

ing applications).

12:1 —Reserved. Must write to 0. 0000

0 FRM_SYSFSM System Fram e Sync Mas k. A 1 masks th e system frame

synchronizat ion signal in the transmit framer formatter.

Note: For those applications that ha ve ji tter on the transmit

clock signal relative to the system clock signal,

enable this b it so that the jitter is isolated fro m the

transmit framer.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

300 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

12.16 Frame Form atter Per Link Registers

Table 4 24. FRM_FFLR1, Frame Formatter Link Register 1 (R/W)

*See Table 417 fo r value s of L an d P.

Address*Bit N am e Function Reset

Default

0x8LPF4 15:12 —Reserved. Must write to 0. 0000

11 FRM_ESFRAMD ESF Remote Alarm Indicator Mode.

0 = Data link remote alarm sequence is 1111 1111 0000 0000.

1 = Data link remo te alarm is all ones.

10:8 FRM_ZCSMD[2:0] Zero Cod e Suppression Mo des.

000 = ZCS off.

001 = Set bit 6 (numbered 0—7) of all time slots.

011 = Set bit 6 of all 0-byte time slots.

101 = Set bit 6 of all voice t ime slots.

111 = Set bit 6 of all 0-byte voice time slots.

110 = Set 0-byte time sl ots to 1001 1000.

100, 010 = Reserved.

(Signali ng F and G bits identify voice time slots.)

000

7—Reserved. Must write to 0. 0

6 FRM_OCKEDGE Output Clock Edge Selection.

0 = Dat a clocked out on rising clock edge.

1 = Data clocked out on fallin g clock edge.

5:4 —Reserved. Must write to 0. 0

3 FRM_AUTOPLB Automatic Payloa d Loopback (ESF Framing Only).

0 = Ignore received pa yload loopback requests.

1 = Automatically start pa yload loopback when pa yload loop-

ba ck signal is received.

2 FRM_AUTOLLB Automatic L ine Loo pback (S F and ES F F raming Only).

0 = Ignore rec eived line loopback req ues ts.

1 = Automatically st art line loopback when line loopback signal

is received.

1 FRM_AUTOEBIT Automatic E-Bit Inserti on (CEPT Framing Only).

0 = Ignore E-bit insertion requests from PM.

1 = Auto matically inser t E bits when indicated by PM.

0 FRM_AUTORAI Au tomatic RAI Insertion.

0 = Ignore RAI insertion requests from PM.

1 = Auto matically insert RA I when indicated by P M.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

301Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 4 25. FRM_F FLR2, Frame Formatter Link Register 2 (R/W)

*See Table 417 fo r value s of L an d P.

Address*Bit N am e Function Reset

Default

0x8LPF5 15:14 FRM_TXLBMD[1:0] Transmit Loopback Modes.

00 = Loopbacks off.

01 = Line loopback.

10 = Payload line loopback pass through. (T he received p ay-

load data, the CRC bits, and the frame alignment bits are

loopback to the line. The data link bi ts are inserted.)

11 = Payload line loopback regenerate. (The rece ived pay-

load data is looped back t o the line. The CRC bi ts, the frame

alignment bits, and data link bits are regenerated and

inserted.)

13:10 —Reserved. Must write to 0. 0000

9 FRM_TXLLBOFF Tr ansmit D 4 SF Line Loopback Off Code .

0 = Do not transmit the D4 SF line loopbac k off code.

1 = Transmit the D4 SF line loopback off code. (Repeated 001

patterns with the framing bits overwriting the pattern T1.403

section 9.3. 1.2.)

8FRM_TXLLBONTransmit D4 SF Line Loopback On Code.

0 = Do not transmit the D4 SF line loopback on code.

1 = Transmit the D4 SF line loopback on code. (Repeated

00 001 patterns wit h the framing bits overwriting the pattern

T1.40 3 section 9 .3.1.1.)

7:6 —Reserved. Must write to 0. 0

5FRM_TXIIDTransmit DS1 Idle ID (Fixed pattern defined inT1.403 sec-

tion D.2).

0 = On demand idle ID off.

1 = On demand idle ID on ( send idle ID).

4 FRM_TXAUXP Transmi t AUXP.

0 = On demand AUXP off.

1 = On demand AUX P on ( send AUXP).

3 FRM_TXRAICI Transmit RAI-CI (E SF modes only).

0 = On demand RAI-CI off.

1 = On demand RAI-CI on (send RAI-CI).

2 FRM_TXRAI Tr ansmi t RAI .

0 = On demand RAI off.

1 = On demand RAI on (send RAI).

1 FRM_TXAISCI Transmit AIS-CI (E SF modes only).

0 = On demand AIS-CI off.

1 = On demand AIS-CI on (send AIS-CI).

0 FRM_TXAIS Transmi t AI S .

0 = On demand AIS off.

1 = On demand AIS on (send AIS).

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

302 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

12.17 Line De code r/E ncode r Per Link R e gisters

Table 426. Line Decoder Per LInk Register Addressing Map

* L and R represent hexadecimal digits used for absolute a d d re ssing in Table 411 through Table 415.

Table 4 27. Line Decoder Per Link Registers Address Indexing

Read: for link 1, the hexadecimal digit L is 0x0 and the hexadecimal digit T is 0x 3.

Table 428. Line Encoder Per Link Register Addressing Map

* L and R represent hexadecimal digits used for absolute addressing in Table 404 through Table 408.

Table 429. Line Encoder Per Link Registers Address Indexing

Read: for l ink 1, the hexadecimal digit L is 0x0 and the hexidecimal digit R is 0x2.

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 TXP=1 1111 1 1 0 0

L* T* —

Link L T Link L T Link L T Link L T

1 0x0 0x3 8 0x1 0x1 16 0x2 0x1 24 0x3 0x1

2 0x0 0x5 9 0x1 0x3 17 0x2 0x3 25 0x3 0x3

3 0x0 0x7 10 0x1 0x5 18 0x2 0x5 26 0x3 0x5

4 0x0 0x9 11 0x1 0x7 19 0x2 0x7 27 0x3 0x7

5 0x0 0xB 12 0x1 0x9 20 0x2 0x9 28 0x3 0x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB ———

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD ———

———15 0x1 0xF 23 0x2 0xF ———

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 RXP = 0 1111 1 1 0 0

L* R* —

Link L R Link L R Link L R Link L R

1 0x0 0x2 8 0x1 0x0 16 0x2 0x0 24 0x3 0x0

2 0x0 0x4 9 0x1 0x2 17 0x2 0x2 25 0x3 0x2

3 0x0 0x6 10 0x1 0x4 18 0x2 0x4 26 0x3 0x4

4 0x0 0x8 11 0x1 0x6 19 0x2 0x6 27 0x3 0x6

5 0x0 0xA 12 0x1 0x8 20 0x2 0x8 28 0x3 0x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA ———

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC ———

———15 0x1 0xE 23 0x2 0xE ———

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

303Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.18 L i ne E ncode r/De code r Pe r Link R e gisters

Tabl e 4 30. FR M_LD LR1, Line Decoder L ink Register 1 (R/W)

*See Table 427 fo r value s of L an d T.

Tabl e 4 31. FR M_LD LR2, Line Encoder L ink Register 2 (R/W)

*See Table 429 fo r value s of L an d R.

Address*Bi t N am e Function Reset

Default

0x8LTFC 15:6 —Reserved. Must write to 0. 0x000

5 FRM_EXCZERO Lin e Format Vi olation Op t i on.

0 = Excessive zeros are not included in bipolar viola-

tions.

1 = Excess ive zeros are in cl uded in bipola r violations.

4 FRM_RLCLK_EDGE Recei ve Line Clock Edge Select.

0 = Data and bipolar violations are latch ed in o n the pos-

itive edge of the receive lin e i nterface clock (RLCLK).

1 = Data and bipolar violations are latched in on the neg-

ative edge of the receive line interface clock (RLCLK0).

3—Reserved. Must write to 0. 0

2:0 FRM_LD_MODE[2:0] Line Decoder Mode.

000 = Single rail (CMI use s ingle rail).

001 = HDB3.

010 = B8ZS.

011 = AMI.

100 = Reserved.

101 = Reserved.

110 = Reserved.

111 = Reserved.

000

Address*Bit Name Function Reset

Default

0x8LRFC 15:5 —Reserved. Must write to 0. 0x000

4 FRM_TLCLK_EDGE Transmit Line Clock E dge S el ect.

0 = Data and frame sync are latched out on the positive

edge of the transmit line inter face clock (TL_CLK).

1 = Data and fr ame sync are latched out on the negativ e

edge of the transmit line inter face clock (TL_CLK).

3—Reserved. Must write to 0. 0

2:0 FRM_LE_MODE[2:0] Line Encoder Mode.

000 = Single rail (CMI use s ingle rail).

001 = HDB3.

010 = B8ZS.

011 = AMI.

100 = Reserved.

101 = Reserved.

110 = Reserved.

111 = Reserved.

000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

304 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

12.19 HDLC Per Channel Configuration and Status Registers

Table 432. HDLC Per Channel Register Addressing Map

* H and P represent hexidecimal digits used for absolute addressing in Table 433 through Table 446.

Table 433. F RM_HCR1, Transmit HDLC Channe l Register 1 (R/W)

*See Table 432 for mapping of H and P.

Table 434. F RM_HCR2, Transmit HDLC Channe l Register 2 (R/W)

*See Table 432 for mapping of H and P.

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

01HDLC Channels 1—64 (000000—111111) RXP= 0/

TXP = 1 000 Per Channel Register

HDL9 HDL8 HDL7 HDL6 HDL5 HDL4 HDL3 HDL2 HDL1 HDL0

H* P* —

Address*Bit Name Function Rese t

Default

0x8HP80 15:13 —Reserved. M us t write to 0. 000

12:8 FRM_TTIMESLOT[4:0] Tra nsmit HDLC T ime-Slot.

These bits indicate (in binary) the time s lot number

assigned to this channel.

0x0

7:0 FRM_TBIT_IM[7:0] Tra nsmit HDL C Bit Assignment.

Thes e bits indicate which bits of a time slot are to be

assigned to this channel (1 = bit assigned).

In loopback mode, set as follows:

00000000 = slowest (~6 kbits/s at 52MHz)

10000000 = faster (~ 2x above)

110 00000 = fas ter st ill (~4x slowes t rate)

. . . .

11111111 = fastest (~1.5 Mbi ts/s at 52MHz)

Note: I f running a mix of loopback and nonloopback

channels, the loopback speed should not be set

fa ster than 111 00000.

0x00

Address*Bi t Name Function Res et

Default

0x8HP81 15:14 FRM_TFRAME_

SEL[1:0] Transmit HDLC Frame Select.

These bits a re enc oded to sele ct odd and/or even num-

bered frames assigned to this channel.

00 = No data select ed.

01 = Data to even frames selected (FS, FAS) .

10 = Data to odd frames selected (FT, NOTFAS, ESF-D L).

11 = Data to all (even and odd) frames selected.

13:5 —Reserved. Must write to 0. 0x000

4:0 FRM_TLINK[4:0] Transmit HDLC Link S el ect.

These bits indicate (in b inary) the link number assigned to

this channel.

00000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

305Agere Systems Inc.

12 28-Channel Framer Registers (continued)

*See Table 432 for mapping of H and P.

Table 435. F RM_HCR3, Transmit HDLC Channel Register 3 (R/W )

Address*Bit Na m e Function Reset

Default

0x8HP82 15 FRM_THC_RESET Transmi t HDLC Reset. When this bit is 1, the channel is

held in reset.

This cle a rs st atus for the c hannel, disables the channel,

and clears the FIFO for the channel.

14 FRM_TENABL Transmit HDLC Enable. When this bit is 0, and written to

1, the channel is reinitialized and enabled. When this bit is

1, and written to 0, no fu rther data will be transmitted and

any partial data being seria lized will be los t. The channel

is disabled.

The user s hould reset the FIFO to p revent partial packets

from being tr ansmitted once re-enab led. Writing the same

value as currently programmed has no effect.

13:11 —Reserved. Must write to 0. 000

Bits 10:0, 3, 1:0 can only be wr itten as the channel is being enabled, (i.e., bit 14 held 0 and is now being

wr itten to 1).

0x8HP82 10:9 FRM_CFLAGS[1:0] C losin g Flags. Only valid in HDLC mode. These bits

select on e of four v alues ( 00 = FRM_FCN T0[4: 0],

01 = FRM_FCNT1[4:0], 10 = F R M_FCNT2[4:0],

11 = FRM_FCNT3[4:0 ] (Table 333—Table 336)). T his

value indicates the number of additional closing flags

inserted after an HDLC packet (e.g., if FRM_F CNT2[4: 0]

is selected an d it i s set to 00100, then five flags are

inserted).

8 FRM_PRMEN PRM Enable. When 1, this channel is enable d t o se n d

PRM packets automatically. When 0, this feature is dis-

abled. (Bit only f or channels 1—28, o r else reser ved.)

When enabled, PRMs will not be sent until all four sec-

onds of PRM information are valid.

7 FRM_TLOOP HDLC Controll er Loopback. When this bit is set to 1, the

channel will operate in loopback mode . When 0, the chan-

nel operates normally.

Note: The corresponding Rx channel should be enabled

before enabling the Tx channel for loopback.

6 FRM_C_R PRM C/R Bit. This bit is inser ted as the C/R bit when

sending a PRM pack et on this channel. (Bit only for chan-

nels 0—27, or else reserved.)

5 FRM_HTTHRSEL Tran sm i t Threshol d Select. T his bit selects which of the

two programmabl e FIFO threshold values to use for this

channel (0 selects FRM_HTTHRSH0 (Table 327), 1

selects FRM_HTTHRSH1 (Table 328)).

4FRM_IFCSFCS Insert. Only valid in HDLC mode. When 0 , this bit

indica tes the FCS at the end of an HDLC packet should

be inserted . A 1 indicates that the internally computed

FCS will not be inserted at the end of the packet.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

306 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 435. FRM_HCR3, Transmit HDLC Channel Reg ister 3 (R/W) (continued)

*See Table 432 for mapping of H and P.

Table 436. FRM_HCR 4, Tran sm it HDLC Channel Register 4 (RO)

*See Table 432 for mapping of H and P.

Table 437. FRM_HCR 5, Transm i t HDLC C han nel Register 5 (R/W)

*See Table 432 for mapping of H and P.

Address*Bit Name Function Reset

Default

0x8HP82 3 FRM_HTIDLE HDLC Idle Select. On l y valid in HDLC mode. This bit indicates

the idle fill chara cter w hen the Tx FIFO is empty. A 0 m eans fill

with flags (01111110). A 1 means f ill with idle (11111111).

2FRM_HTMODETransmit Ch annel M od e Se lect. A 0 indicates the channel is

in HDLC mode. A 1 indicates the channel is in transparent

mode.

1:0 FRM_HXPIDLE[1:0] Transparent Idle Mode Character Select. Only valid in trans-

parent mode . These bits indicate one of the four possible 8-bit

patterns to be sent when the Tx FIFO is empty.

(00 selects TXICHAR0 (Table 329), 01 selects TXICHAR1

(Table 330), e t c. )

Address*Bit Name Fu nction R eset

Default

0x8HP83 15:3 —Reserved. Reads 0. 0x000

2 FRM_HTUND Transm i t FIFO Underrun . A 1 indicates this channel has

run out of data in the middle of an HDLC pack et. In trans-

parent mode, it simply means the channel has run out of

data.

1FRM_HTDONETran sm it Done . A 1 indicate s a complete p acket has been

sen t o n t his cha nnel . 0

0 FRM_HTTHRSH Transmit FIFO Threshold Interrupt. A 1 indicates this

channels F IF O level has dropp ed below the programmed

threshold value.

Address*Bit Name F unc tion Reset

Default

0x8HP84 15:3 —Reserved. Must write to 0. 0x0

2 FRM_MHTUND Trans m it FIFO Und errun Interrupt M ask. A 1 masks the

corresponding channel’s F RM_HTUND status from caus-

ing an interr upt.

1 FRM_MHTDONE Transmit Done I nterrupt Mask. A 1 masks the corre-

sponding channel’s F RM _HTDO NE status from causing

an interrupt.

0 FRM_MHTTHRSH Tra n smi t F IF O Thre sh ol d I nte r rup t Ma sk. A 1 masks the

corresponding channel’s F RM_HTT HRSH status from

causing an interrupt.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

307Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 438. FRM_HCR6, Transmit HDLC Channel Register 6 (WO)

*See Table 432 for mapping of H and P.

Table 439. FRM_HCR 7, Tran sm it HDLC Channel Register 7 (RO)

*See Table 432 for mapping of H and P.

Table 440. FRM_HCR8, Receive HDLC Channel Register 8 (R/W)

*See Table 432 for mapping of H and P.

Table 441. FRM_HCR9, Receive HDLC Channel Register 9 (R/W)

*See Table 432 for mapping of H and P.

Address*Bit Name Function R eset

Default

0x8HP85 15:10 —Reserved. Must wr ite to 0. 0x00

9:8 FRM_HTFUNC[1:0] Transmit Data F unction. These two bits indicate the

action to be taken by writing this register:

00 = Add DATA to the Tx FIFO (non-EOP).

01 = Add DATA to the Tx FIFO as EOP data (i.e., last byte

of pa cke t) .

10 = Abort last incomplete data packet in FIFO. (If written

after an E OP byte, this may abort the p revious packet.)

11 = Reserved.

7:0 FRM_HTDATA[7:0] Transmit Data Register. When FRM_HTFUNC[1:0] = 00

or 01, then these bits contain a byte of data to be written to

the FIFO.

0x00

Address*Bit Name Function Reset Default

0x8HP86 15:10 —Reserved. Must write to 0. 0x0

9:0 FRM_HTCOUNT[9:0] Transmit FIFO Byte Count. These bit s indicate

the number of bytes available to be filled in the Tx

FIFO for the specific channel.

x80 (x200 in large

buffer mode)

Address*Bit N am e Function Reset

Default

0x8HP00 15:13 —Reserved. Must write to 0. 000

12:8 FRM_RTIMESLOT[4:0] Received HDLC Time Slot. These bits indicate (in

binary) the time slot number assigned to this channel. 00000

7:0 FRM_RBIT_IM[7:0] Received HDLC Bit A ssignme nt. These bits indicate

which bits of a t ime slot are to be assigned to this

channel (1 = bit assigned).

0x00

Address*Bit Name Fu nction Reset

Default

0x8HP01 15:14 FRM_RFRAME_

SEL[1:0] Receive HDLC Frame Select. These bits are enc oded to

select odd and/or even numbered frames as signed to this

channel.

00 = No dat a selected. (Use for loopback mode.)

01 = Data from even frames selected (Fs, FAS).

10 = Data from odd frames selected (FT, NOTFAS, ESF-DL).

11 = Data from all (even and odd) f rames selected.

000

13:5 —Reserved. Must w rite to 0. 0x0

4:0 FRM_RLINK[4:0] Receive HDL C Link Select. These bits indicate (in binary)

the l ink number assigned to t his channel. 00000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

308 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 442. FRM_HCR10, Receive HDLC Channel Register 10 (R/W)

*See Table 432 for mapping of H and P.

Table 443. FRM_HCR11, Receive HDLC Channel Register 11 (RO)

*See Table 432 for mapping of H and P.

Address*Bit Nam e Function Reset

Default

0x8HP02 15 FRM_RHC_RESET Receiv e HDL C Reset. When this bit is 1, the channel is

held in reset. 0

14 —Reserved. Must write to 0. 0

13 FRM_RENABL Receive HDLC Enable. When this bit is 0 and written to 1,

the channel is reinitialized (i. e., HDLC searching for open-

ing flag, transparent searching for alignment char acter if so

programmed) and enabled. When thi s bit is 1 and written t o

0, any current HDLC packet will be aborted and the chan-

nel disabled. Writing the same value as curr ently pro-

grammed has no effect.

12 —Reserved. Must w rite to 0. 0

Bits 11:0 c an onl y b e written as the channel is being enabled, (i .e. , bi t 13 held 0 and is now being

w ritten to 1).

11 FRM_RTHRSEL Receiv e FIFO Threshold Selec t. This bi t selects which of

the two programmable FIFO threshold values to use for this

chan nel. (0 selects FRM_HRT HRS H0[9:0] (Table 341), 1

selects FRM_HRTHRSH1[9:0] (Table 342)).

10 FRM_RFCS Re ceiv e FCS Option. Only valid in HDLC mode. When 1,

this bit indicate s the FCS at the end of an H DLC packet

should be removed. A 0 indicates it s hould kept as part of

the packet.

9 FRM_HRMODE Re ceiv e Chan nel Mode S elect. A 0 indicates the chan nel

is in HDLC mode. A 1 indicates the channel is in trans par-

ent mode.

8FRM_BYTALByte Alig nment. This bit is only used in trans parent mode

(forced to 1 in HDLC mode). A 0 indicates no byte align-

ment is done by the rece iver. A 1 indicate s that byte align-

me nt will be done by the receiver once the

FRM_ MAT CH[7:0] code is found.

7:0 FRM_MATCH[7:0] Transparent Mode Pattern Match. Only valid in transpar-

ent mode with by te alignment. These bits indicate the pat-

tern to match to begin receiving transparent data (forced to

ones in HDLC mode).

0x0

Address*Bit Name Function Reset

Default

0x8HP03 15:4 —Reserved. Reads 0. 0x000

3FRM_RIDLEReceive Channel Id le. A 1 indicates th is channel has been

detecte d as idle. 0

2FRM_OVRReceive FIFO Overflow. A 1 indicates this channel’s FIFO

has overflowed. 0

1FRM_EOPEnd of P ac ket . A 1 indicates an end-of-packet has been

detecte d on this ch annel. 0

0 FRM_HRTHRSH Receive FIFO Thresho ld Interrupt. A 1 indicates this

channel’s FIFO has exceeded the programmed threshold

value.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

309Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 444. FRM_HCR12, Receive HDLC Channel Register 12 (R/W)

*See Table 432 for mapping of H and P.

Address*Bit Name Function R eset

Default

0x8HP04 15:4 —Reserved. Must write to 0. 0x000

3 FRM_MIDLE Receive Channel I dle Interrupt Mask. A 1 masks this

channel’s idle detection interrupt. 1

2FRM_MOVRReceive FIFO Overflow Interrupt Mask. A 1 masks this

channel’s FIFO overflow interrupt. 1

1FRM_MEOPE nd of Packet Interru pt Mask. A 1 masks this channel’s

end-of-packet interrupt. 1

0 FRM_MHRTHRSH Receive FIFO Threshold Interrupt Mask. A 1 masks this

channel’s exceeded FIFO threshold interrupt. 1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

310 Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 445. FRM_HCR13, Receive HDLC Channel Register 13 (RO)

*See Table 432 for mapping of H and P.

Table 446. FRM_HG R14, Re ceiv e HDLC Channel Register 14 (COR)

*See Table 432 for mapping of H and P.

Address*Bit Name Fu nction Reset

Default

0x8HP05 15:11 —Reserved. Reads 0. 00000

10 FRM_HMDA M ore Data Available. A 1 indicates that if the FIFO is

read aga in, valid data will be returned. A 0 indicates no

more data is available.

9FRM_HRVALIDReceive FIFO Valid Data. A 1 indicates the information

read from the FIFO is val id. A 0 indicates the FIFO was

empty and no inf ormation was avai l able.

8 FRM_HRTYPE Receiv e FIFO D ata Type. A 0 in dicat es

FRM_HR_DATA[7:0] is data. A 1 indicates

FRM_ HR_DATA[7:0] is stat us in formation.

7:0 FRM_HR_DATA[7:0] Re cei ve F IFO Data. When FRM_HRTYPE = 0, these bits

co ntain a byte of data. Whe n FR M_HRTYPE = 1 , the bits

are defined below.

7FRM_HOVRFIFO Overflow. A 1 indic ates the FIFO overflowed. 0

6FRM_HEOPEnd of P acket. A 1 indicates end of packet (normal

packet). 0

5 FRM_HCRCERR HDL C CRC Error. A 1 indicates a CRC error was

detected. 0

4FRM_HABRTHDLC Abort. A 1 indicates an abo rt was r eceived. 0

3FRM_HIDLHDLC Idle. A 1 indicates id le (as defi ned by HDLC proto-

col) condition detect ed. 0

2:0 FRM_HBIT[2:0] Complete Byte Status. 111 indicates the last data

received was a compl ete byte.

These bit s should be igno red if EOP is 0.

Address*Bit Name Function Re set

Default

0x8HP06 15:10 —Reserved. Must write to 0. 0x00

9:0 FRM_HRCOUNT[9:0] Receive FIFO Byte Count. These bit s indicate the

number of valid bytes contained in the Rx FIFO for the

spe c if ic cha nnel .

0x000

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SONET/S DH x28/x21 DS1/E1

311Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

12.20 28-Ch annel Framer Block Register Map

Table 447. Framer Reg ister Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Superframer Global Registers—R/W

0x80000 FRM_SFGR1 FRM_

SW_TRN FRM_LC_CNTRL[1:0] FRM_LOOP_

TIMING FRM_DS1_

CEPTN FRM_PLL_

BYPAS FRM_

LG_BUF_M

ODE

0x80001 FRM_SFGR2 FRM_TP_

SIG_PWDN FRM_RP_

SIG_PWDN FRM_TP_

RDL_PWDN FRM_RP_

TDL_PWDN FRM_TP_R

H_PWDN FRM_RP_T

H_PWDN FRM_TS_

PWDN FRM_RS_

PWDN FRM_TP_P

M_PWDN FRM_RP_F

F_PWDN FRM_TP_

RA_PWDN

0x80002 FRM_SFGR3

(RO) 0 FRM_AR_IS FRM_TP_

RDL_IS FRM_TP_

TDL_IS FRM_RH_IS FRM_TH_IS FRM_TS_

IS FRM_RS_

IS FRM_TP_

PM_IS FRM_RP_

PM_IS FRM_RP_R

DL_IS FRM_RP_T

DL_IS 0000

0x80003 FRM_SFGR4 FRM_VERSION[2:0]

0x80004

—

0x80009

—

Arbi te r (Framer) Global Regis ters—R/W

0x80010 FRM_FGR1 FRM_TO[7:0]

0x80011 FRM_FGR2 FRM_TC_

EN FRM_TC[7:0]

0x80012 FRM_FGR3 FRM_

TPSSE_IM

0x80014 FRM_FGR4

(COR) FRM_TPSSEI[16:1]

0x80015 FRM_FGR5

(COR) FRM_TPSSEI[28:17]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

312 A

ere S

stems Inc.

12 28-Channel Framer Registers (continued)

Table 447. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P e rf ormanc e Mon i t o r Gl ob al Re g i ster s—R/W

0x80P20 FRM_PMGR1_

BFRM_

SEC_SEL FRM_CT125[11:0]

0x80P30 FRM_PMGR1

(COR) FRM_

DETECT FRM_

PTRNBER

0x80P31 FRM_PMGR2 FRM_TPERR_CT[15:0]

0x80P32 FRM_PMGR3 FRM_RAC[2:0] FRM_RDC[2:0] FRM_

FSFBEEN FRM_

CMFRFEN FRM_

CRCRFEN FRM_CEPTAISM[1:0] FRM_

DS1AISM FRM_

ESFRAIM FRM_

RAICLR

0x80P33 FRM_PMGR4 FRM_SFSEST[15:0]

0x80P34 FRM_PMGR5 FRM_DCT[15:0]

0x80P35 FRM_PMGR6 FRM_ESFSEST[15:0]

0x80P36 FRM_PMGR7 FRM_

DSEF FRM_DLFA FRM_DRFA FRM_

DSLIP FRM_

DLOS FRM_DAIS FRM_

DCRC FRM_DFS FRM_DFT

0x80P37 FRM_PMGR8 FRM_CCT[15:0]

0x80P38 FRM_PMGR9 FRM_CSEST[15:0]

0x80P39 FRM_PMGR10 FRM_

CSA6_F FRM_

CSA6_E FRM_

CSA6_C FRM_

CSA6_8 FRM_

CSA6_1X FRM_

CSA6_X1 FRM_

CEBIT FRM_

CLMFA FRM_CLFA FRM_CRFA FRM_

CSLIP FRM_

CLOS FRM_CAIS FRM_

CCRC FRM_

CNOTFAS FRM_

CFAS

0x80P3A FRM_PMGR11 FRM_CRET[15:0]

0x80P3B FRM_PMGR12 FRM_

CRAI_AIS FRM_

CRAI_OOF FRM_

CRAI_LOS FRM_CRAI_S

A6EQC FRM_CRAI_

SA6EQ8 FRM_CRAI_C

RCTX FRM_CRAI

_LTS0MFA FRM_CRAI

_LTS16MFA FRM_CRAI_

8MSEX FRM_DSR

AI_LOS FRM_DSR

AI_OOF FRM_DSR

AI_AIS

0x80P3C FRM_PMGR13 FRM_CFBE

_MODE FRM_

CEBIT_

LTS0MFA

FRM_

CEBIT_

ESMF

FRM_

CEBIT_

CRCTX

0x80P3D FRM_PMGR14 FRM_PTRN_

EN FRM_PTRN_

INV FRM_PTRN

_FRMT FRM_PTRN_LNK[4:0] FRM_PTRN_SEL[3:0]

0x80P3E FRM_PMGR15 FRM_LN_IS[16:1]

0x80P3F FRM_PMGR16 FRM_LN_IS[28:17]

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

313Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 447 . F ram er Regist er Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

HDLC Global Configuration and Status Registers—R/W

Tr ansmit HDLC Global Register s

0x80140 FRM_HGR1 FRM_HTTHRSH0[9:0]

0x80141 FRM_HGR2 FRM_HTTHRSH1[9:0]

0x80142 FRM_HGR3 FRM_TXICHAR0[7:0]

0x80143 FRM_HGR4 FRM_TXICHAR1[7:0]

0x80144 FRM_HGR5 FRM_TXICHAR2[7:0]

0x80145 FRM_HGR6 FRM_TXICHAR3[7:0]

0x80146 FRM_HGR7 FRM_FCNT0[4:0]

0x80147 FRM_HGR8 FRM_FCNT1[4:0]

0x80148 FRM_HGR9 FRM_FCNT2[4:0]

0x80149 FRM_HGR10 FRM_FCNT3[4:0]

0x8014A FRM_HGR11 FRM_TH_IS[15:0]

0x8014B FRM_HGR12 FRM_TH_IS[31:16]

0x8014C FRM_HGR13 FRM_TH_IS[47:32]

0x8014D FRM_HGR14 FRM_TH_IS[63:48]

Receive HDLC Global Registers

0x80040 FRM_HGR15 FRM_HRTHRSH0[9:0]

0x80041 FRM_HGR16 FRM_HRTHRSH1[9:0]

0x80042 FRM_HGR17 FRM_RH_IS[15:0]

0x80043 FRM_HGR18 FRM_RH_IS[31:16]

0x80044 FRM_HGR19 FRM_RH_IS[47:32]

0x80045 FRM_HGR20 FRM_RH_IS[63:48]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

314 A

ere S

stems Inc.

12 28-Channel Framer Registers (continued)

Table 447. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

System Inter fac e Global Reg isters—R/W

Receive System Interface Global Registers

0x80050 FRM_SYSGR1 FRM_SYSMOD[3:0] FRM_ASM FRM_CMS FRM_

CHIDTS FRM_

STUFFL or

FRM_

LNKSTART

FRM_

AISLFA FRM_

AISCRCT FRM_

DNOTFAS FRM_

TFSCKE FRM_

FSPOL

0x80051 FRM_SYSGR2 FRM_HWYE

NA FRM_RSTDO

NE (read

only)

0x80052 FRM_SYSGR3 FRM_STUFF[7:0] FRM_IDLE[7:0]

0x80053 FRM_SYSGR4 FRM_

STSSLB FRM_

STSLLB FRM_TSLBA[4:0] FRM_TLSBL[4:0]

0x80054 FRM_SYSGR5 FRM_TS_

DPAR FRM_TS_

SPAR

0x80055 FRM_SYSGR6

0x80056 FRM_SYSGR7 FRM_TPSB

_FS_IS

(COR)

0x80057 FRMSYSGR8 FRM_PSB_

FS_IM

Transmit System Interface Global Registers

0x80150 FRM_SYSGR9 FRM_RS_

DPAR FRM_RS_

SPAR FRM_

RFSCKE

0x80151 FRM_SYSGR1

0x80152 FRM_SYSGR1

0x80153 FRM_SYSGR1

0x80154 FRM_SYSGR1

0x80155 FRM_SYSGR1

0x80156 FRM_SYSGR1

5FRM_

DPAR_IS FRM_

SPAR_IS FRM_PSB_

FS_IS

0x80157 FRM_SYSGR1

6FRM_

DPAR_IM FRM_

SPAR_IM FRM_PSM

_FS_IM

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

315Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 447 . F ram er Regist er Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Signaling Global Registers—R/W

0x80060 FRM_SGR1 FRM_R_

TSAISHG FRM_R_LINKCNT[4:0] FRM_TEST_BIT[2:0] FRM_R_

AFZFBE

0x80061 FRM_SGR2 FRM_R_

SCOSEN FRM_R_SCOSDTH[9:0]

0x80062 FRM_SGR3 FRM_R_SCOSTTH[15:0]

0x80063 FRM_SGR4

(RO) FRM_R_COSFIFO[1:0] FRM_R_COSFIFOL[4:0] FRM_R_COSFIFOTS[4:0] FRM_R_COSFIFOSIG[3:0]

0x80064 FRM_SGR5

(RO) ???????????????FRM_R_

COSDTHS

0x80065 FRM_SGR6

(COR) 0000000000000FRM_R_

COSDTHI FRM_R_

COSTTHI FRM_R_

COSOFI

0x80066 FRM_SGR7 0 0 0 0 0 0 0 0 0 0 0 0 0 FRM_R_C

OSDTHM FRM_R_

COSTTHM FRM_R_

COSOFM

0x80160 FRM_SGR8 FRM_T_LINKCNT[4:0] FRM_T_

SUBZERO FRM_T_FA

S_NOTFAS FRM_T_

AFZFBE

Frame Formatter Global Regis ter —R/W

0x80170 FRM_FFGR1 FRM_

TXSOOF FRM_

PTRN_EN FRM_

PTRN_INV FRM_PTRN

_FRMT FRM_PTRN_LNK[4:0] FRM_PTRN_SEL[3:0]

Facility Data Link Glo bal Registers—R/W

0x80090 FRM_FDLGR1

0x801A1 FRM_FDLGR2

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

316 A

ere S

stems Inc.

12 28-Channel Framer Registers (continued)

Table 447. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive S ignaling Link Register s—R/W

See Table 370 for Values of L and R in the Register Address Field

0x8LR00 FRM_RSLR0 FRM_RPSR0[6:0]

0x8LR01 FRM_RSLR1 FRM_RPSR1[6:0]

0x8LR02 FRM_RSLR2 FRM_RPSR2[6:0]

0x8LR03 FRM_RSLR3 FRM_RPSR3[6:0]

0x8LR04 FRM_RSLR4 FRM_RPSR4[6:0]

0x8LR05 FRM_RSLR5 FRM_RPSR5[6:0]

0x8LR06 FRM_RSLR6 FRM_RPSR6[6:0]

0x8LR07 FRM_RSLR7 FRM_RPSR7[6:0]

0x8LR08 FRM_RSLR8 FRM_RPSR8[6:0]

0x8LR09 FRM_RSLR9 FRM_RPSR9[6:0]

0x8LR0A FRM_RSLR10 FRM_RPSR10[6:0]

0x8LR0B FRM_RSLR11 FRM_RPSR11[6:0]

0x8LR0C FRM_RSLR12 FRM_RPSR12[6:0]

0x8LR0D FRM_RSLR13 FRM_RPSR13[6:0]

0x8LR0E FRM_RSLR14 FRM_RPSR14[6:0]

0x8LR0F FRM_RSLR15 FRM_RPSR15[6:0]

0x8LR10 FRM_RSLR16 FRM_RPSR16[6:0]

0x8LR11 FRM_RSLR17 FRM_RPSR17[6:0]

0x8LR12 FRM_RSLR18 FRM_RPSR18[6:0]

0x8LR13 FRM_RSLR19 FRM_RPSR19[6:0]

0x8LR14 FRM_RSLR20 FRM_RPSR20[6:0]

0x8LR15 FRM_RSLR21 FRM_RPSR21[6:0]

0x8LR16 FRM_RSLR22 FRM_RPSR22[6:0]

0x8LR17 FRM_RSLR23 FRM_RPSR23[6:0]

0x8LR18 FRM_RSLR24 FRM_RPSR24[6:0]

0x8LR19 FRM_RSLR25 FRM_RPSR25[6:0]

0x8LR1A FRM_RSLR26 FRM_RPSR26[6:0]

0x8LR1B FRM_RSLR27 FRM_RPSR27[6:0]

0x8LR1C FRM_RSLR28 FRM_RPSR28[6:0]

0x8LR1D FRM_RSLR29 FRM_RPSR29[6:0]

0x8LR1E FRM_RSLR30 FRM_RPSR30[6:0]

0x8LR1F FRM_RSLR31 FRM_RPSR31[6:0]

0x8LR21 FRM_RSLR32 FRM_R_

FZCON FRM_R_

SIGI FRM_R_

RXSTOMP FRM_R_

SIGDEB FRM_R_

HGEN FRM_R_

MSIGFZ FRM_R_

FGSRC FRM_R_SIGSRC[1:0]

0x8LR20 FRM_RSLR33 FRM_R_HGAIS[3:0] FRM_R_HGA[3:0] FRM_R_HGRDI[3:0] FRM_R_

TS16A FRM_R_

TS16AIS

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

317Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 447 . F ram er Regist er Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Signaling Link Registers—R/W

See Table 375 for Values of L and T in the Register Address Field

0x8LT00 FRM_TSLR0 FRM_TPSR0[6:0]

0x8LT01 FRM_TSLR1 FRM_TPSR1[6:0]

0x8LT02 FRM_TSLR2 FRM_TPSR2[6:0]

0x8LT03 FRM_TSLR3 FRM_TPSR3[6:0]

0x8LT04 FRM_TSLR4 FRM_TPSR4[6:0]

0x8LT05 FRM_TSLR5 FRM_TPSR5[6:0]

0x8LT06 FRM_TSLR6 FRM_TPSR6[6:0]

0x8LT07 FRM_TSLR7 FRM_TPSR7[6:0]

0x8LT08 FRM_TSLR8 FRM_TPSR8[6:0]

0x8LT09 FRM_TSLR9 FRM_TPSR9[6:0]

0x8LT0A FRM_TSLR10 FRM_TPSR10[6:0]

0x8LT0B FRM_TSLR11 FRM_TPSR11[6:0]

0x8LT0C FRM_TSLR12 FRM_TPSR12[6:0]

0x8LT0D FRM_TSLR13 FRM_TPSR13[6:0]

0x8LT0E FRM_TSLR14 FRM_TPSR14[6:0]

0x8LT0F FRM_TSLR15 FRM_TPSR15[6:0]

0x8LT10 FRM_TSLR16 FRM_TPSR16[6:0]

0x8LT11 FRM_TSLR17 FRM_TPSR17[6:0]

0x8LT12 FRM_TSLR18 FRM_TPSR18[6:0]

0x8LT13 FRM_TSLR19 FRM_TPSR19[6:0]

0x8LT14 FRM_TSLR20 FRM_TPSR20[6:0]

0x8LT15 FRM_TSLR21 FRM_TPSR21[6:0]

0x8LT16 FRM_TSLR22 FRM_TPSR22[6:0]

0x8LT17 FRM_TSLR23 FRM_TPSR23[6:0]

0x8LT18 FRM_TSLR24 FRM_TPSR24[6:0]

0x8LT19 FRM_TSLR25 FRM_TPSR25[6:0]

0x8LT1A FRM_TSLR26 FRM_TPSR26[6:0]

0x8LT1B FRM_TSLR27 FRM_TPSR27[6:0]

0x8LT1C FRM_TSLR28 FRM_TPSR28[6:0]

0x8LT1D FRM_TSLR29 FRM_TPSR29[6:0]

0x8LT1E FRM_TSLR30 FRM_TPSR30[6:0]

0x8LT1F FRM_TSLR31 FRM_TPSR31[6:0]

0x8LT21 FRM_TSLR32 FRM_T_

ATS16RFA FRM_T_

ASPLB FRM_T_MSP FRM_T_

ZCSM FRM_T_

VTSIGE FRM_T_

SIGI FRM_T_

TXSTOMP FRM_T_

HGEN FRM_T_

MSIGFZ FRM_T_

FGSRC FRM_T_SIGSRC[1:0]

0x8LT20 FRM_TSLR33 FRM_T_

TS16A FRM_T_

TS16AIS

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

318 A

ere S

stems Inc.

12 28-Channel Framer Registers (continued)

Table 447. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Performance Monitor Link Regi sters—COR

See Table 381 for Values of L and P in the Register Address Field

0x8LP80 FRM_P MLR1

(R/W) FRM_PM_IM4[15:0]

0x8LP81 FRM_P MLR2

(R/W) FRM_PM_IM5[15:0]

0x8LP82 FRM_P MLR3

(R/W) FRM_MHGALIGN[3:0] FRM_

MSEFS FRM_MFE FRM_PM_IM6[4:0]

0x8LP83 FRM_PMLR4 FRM_SLIPO FRM_SLIPU FRM_OOF FRM_LSFA FRM_OAIS FRM_AIS FRM_ORAI FRM_RAI FRM_

SA600X1E FRM_

SA6001XE FRM_

CRCTX FRM_

LTS0MFA FRM_

TS0MFABE FRM_SES FRM_BES FRM_ES

0x8LP84 FRM_PMLR5 FRM_LFV FRM_FBE FRM_CRCE FRM_ECRCE FRM_

REBIT FRM_

CREBIT FRM_LTFA FRM_NFA FRM_

SA7LID FRM_

LLBON FRM_

LLBOFF FRM_AUX

PFRM_LOS FRM_

BOMR

0x8LP85 FRM_PMLR6 FRM_

FDL_RAI FRM_FDL_

PLBON FRM_FDL_

PLBOFF FRM_FDL_

LLBON FRM_FDL_

LLBOFF

0x8LP86 FRM_PMLR7 FRM_BPV[15:0]

0x8LP87 FRM_PMLR8 FRM_FBEC[15:0]

0x8LP88 FRM_PMLR9 FRM_CEC[15:0]

0x8LP89 FRM_PMLR10 FRM_REC[15:0]

0x8LP8A FRM_PMLR11 FRM_CETE[15:0]

0x8LP8B FRM_PMLR12 FRM_CENT[15:0]

0x8LP8C FRM_PMLR13 FRM_FE_OP FRM_FE_N FRM_FE_M FRM_FE_L FRM_FE_K FRM_FE_I FRM_FE_H FRM_FE_G FRM_FE_F FRM_FE_E FRM_FE_D FRM_FE_C FRM_FE_B FRM_FE_A

0x8LP8D FRM_PMLR14 FRM_FE_Y FRM_FE_X FRM_FE_W FRM_FE_V FRM_FE_U FRM_FE_T FRM_FE_S FRM_FE_R FRM_FE_Q

0x8LP8E FRM_PMLR15 FRM_ESC[15:0]

0x8LP8F FRM_PMLR16 FRM_BESC[15:0]

0x8LP90 FRM_PMLR17 FRM_SESC[15:0]

0x8LP91 FRM_PMLR18 FRM_RBOM[7:0]

0x8LP92 FRM_PMLR19 FRM_HGALIGN[3:0] FRM_SEFS

0x8LP93 FRM_PMLR20 FRM_G6 FRM_G5 FRM_G4 FRM_G3 FRM_G2 FRM_G1 FRM_SE FRM_FE FRM_LV FRM_SL FRM_LB FRM_N1 FRM_N0

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

319Agere Sy stem s Inc.

12 28-Channel Framer Registers (continued)

Table 447 . F ram er Regist er Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive FDL Link Re gisters—R/W

See Table 403 for Values of L and R in the Register Address Field

0x8LRC0 FM_RFDLLR1 FRM_RXS0[15:0]

0x8LRC1 FM_RFDLLR2 FRM_RXS1[15:0]

0x8LRC2 FM_RFDLLR3 FRM_RXS2[15:0]

0x8LRC3 FM_RFDLLR4 FRM_RXS3[15:0]

0x8LRC4 FM_RFDLLR5 FRM_RXS4[15:0]

0x8LRC5 FM_RFDLLR6 FRM_RXC

RCSM

0x8LRC6 FM_RFDLLR7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRM_

RXSA

0x8LRC7 FM_RFDLLR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRM_

RXSR_IS

0x8LRC8 FM_RFDLLR9 FRM_

RXSR_IM

Transmit FDL Li nk Regis ters—R/W

See Table 410 for Values of L and T in the Register Address Field

0x8LTD0 FM_TFDLLR1 FRM_TXS0[15:0]

0x8LTD1 FM_TFDLLR2 FRM_TXS1[15:0]

0x8LTD2 FM_TFDLLR3 FRM_TXS2[15:0]

0x8LTD3 FM_TFDLLR4 FRM_TXS3[15:0]

0x8LTD4 FM_TFDLLR5 FRM_TXS4[15:0]

0x8LTD5 FM_TFDLLR6 FRM_

ABITSRC FRM_

MBITSRC FRM_

SBITSRC FRM_

CBITSRC FRM_

SA8SC FRM_

SA7SC FRM_

SA6SC FRM_

SA5SC FRM_

SA4SC FRM_

TXCRCSM FRM_

ASRC FRM_DS1I

0x8LTD6 FM_TFDLLR7 FRM_BOME FRM_TBOM[5:0]

0x8LTD7 FM_TFDLLR8

(RO/COW) FRM_

BOMC_IS FRM_

TXSE_IS

0x8LTD8 FM_TFDLLR9 FRM_

BOMC_IM FRM_

TXSE_IM

System Interface Link Registers—R/W

See Table 417 for Va lues of L and P in the Register Address Field

0x8LPE0 FRM_SYSLR1 FRM_BYOFF[6:0] FRM_OFF[2:0] FRM_

HALFOFF FRM_

QUAROFF

0x8LPE1 FRM_SYSLR2 FRM_CEPT

MAIS FRM_CEPTA

AIS FRM_MANAI

SFRM_CEPTS

TMP

0x8LPE2 FRM_SYSLR3

0x8LPE3 FRM_SYSLR4

0x8LPE4 FRM_SYSLR5

0x8LPE5 FRM_SYSLR6

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

320 A

ere S

stems Inc.

12 28-Channel Framer Registers (continued)

Table 447. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Arbiter Link Registers—R/W

See Table 417 for Values of L and T in the Regist er Address Field

0x8LPF0 FRM_ARLR1 FRM_

LNK_ENA FRM_LNK_

TRANSP FRM_LNK_

RESTARTN FRM_LNK_

REFRAME FRM_

ICKEDGE

0x8LPF1 FRM_ARLR2 FRM_ESF_

CRC_EN FRM_FAST FRM_OPT[1:0] FRM_FBE_

MODE FRM_LF_CRT[2:0] FRM_AUTO

_AIS FRM_RAIL3_DEC[1:0] FRM_MODE[3:0]

0x8LPF2 FRM_ARLR3 FRM_TP_C

K_SRC_EN FRM_TP_

CK_SRC FRM_TP_

DD_SRC

Frame Formatter Link Registers—R/W

See Table 417 for Values of L and T in the Regist er Address Field

0x8LPF4 FRM_FFLR1 FRM_

ESFRAMD FRM_ZCSMD[2:0] FRM_

OCKEDGE FRM_

AUTOPLB FRM_

AUTOLLB FRM_

AUTOEBIT FRM_

AUTORAI

0x8LPF5 FRM_FFLR2 FRM_TXLBMD[1:0] FRM_

TXLLBOFF FRM_

TXLLBON FRM_TXIID FRM_

TXAUXP FRM_

TXRAICI FRM_

TXRAI FRM_

TXAISCI FRM_

TXAIS

Line Decoder/Encoder Link Registers—R/W

See Table 427 and Tabl e429 for Values of L and T in the Register Address Field

0x8TPFC FRM_LDLR1 FRM_

EXCZERO FRM_RLCL

K_EDGE FRM_LD_MODE[2:0]

0x8LPFD FRM_LDLR2 FRM_TLCL

K_EDGE FRM_LE_MODE[2:0]

HDLC Channel Registers—R/W

See Table 432 for Mapping of H and P in the Register Address Field

Trans mit HDLC Chann el Re gisters

0x8HP80 FRM_HCR1 FRM_TTIMESLOT[4:0] FRM_TBIT_IM[7:0]

0x8HP81 FRM_HCR2 FRM_TFRAME_SEL[1:0] FRM_TLINK[4:0]

0x8HP82 FRM_HCR3 FRM_THC_

RESET FRM_

TENABL FRM_CFLAGS[1:0] FRM_

PRMEN FRM_

TLOOP FRM_C_R FRM_

HTTHRSEL FRM_IFCS FRM_

HTIDLE FRM_

HTMODE FRM_HXPIDLE[1:0]

0x8HP83 FRM_HCR4

(RO) 0000000000000FRM_

HTUND FRM_

HTDONE FRM_

HTTHRSH

0x8HP84 FRM_HCR5 FRM_

MHTUND FRM_

MHTDONE FRM_MHT

THRSH

0x8HP85 FRM_HCR6

(WO) FRM_HTFUNC[1:0] FRM_HTDATA[7:0]

0x8HP86 FRM_HCR7 FRM_HTCOUNT[9:0]

Receive HDLC Channel Registers

0x8HP00 FRM_HCR8 FRM_RTIMESLOT[4:0] FRM_RBIT_IM[7:0]

0x8HP01 FRM_HCR9 FRM_RFRAME_SEL[1:0] FRM_RLINK[4:0]

0x8HP02 FRM_HCR10 FRM_RHC_

RESET FRM_

RENABL FRM_

RTHRSEL FRM_RFCS FRM_

HRMODE FRM_

BYTAL FRM_MATCH[7:0]

0x8HP03 FRM_HCR11

(RO) 000000000000FRM_

RIDLE FRM_OVR FRM_EOP FRM_

HRTHRSH

0x8HP04 FRM_HCR12 FRM_

MIDLE FRM_

MOVR FRM_

MEOP FRM_MHR

THRSH

0x8HP05 FRM_HCR13

(RO) 0 0 0 0 0 FRM_HMDA FRM_

HRVALID FRM_

HRTYPE FRM_HR_DATA[7:0]

FRM_HOVR FRM_HEOP FRM_

HCRCERR FRM_

HABRT FRM_HIDL FRM_HBIT[2:0]

0x8HP06 FRM_HCR14

(COR) FRM_HRCOUNT[9:0]

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
321Agere Systems Inc.  
13 Cross Connect (XC) Registers
Ta ble of Conte nts
Contents Page
13 Cross Connect (XC) Registers   ...... .............. ................. .............. .............. ................. ..................................... 321
13.1  Cross Connect Register Descrip tions ..................................................................................................... 322
13.2  Cross Connect Register Map  ................................................................................................................. 328
Tables Page
Table 448. XC_ID_R, XC Global R egister 1 (RO) ...............................................................................................322
Table 449.  X C_CHI_MODE1_R, X C S ystem  Interface Global Regist er 1  (R/W) .................. ................... ........... 3 22
Table 450.  X C_CHI_MODE2_R, X C S ystem  Interface Global Regist er 2  (R/W) .................. ................... ........... 3 22
Table 4 51.  XC_PIND_SRC[1—15], XC1 External I/O TXDAT A and TXCLK Source Configuration (R/W) ..... . ... 323
Table 452. XC_FRP_SRC[1—14], X C 1 Framer Rec eive Path Data Source Configuration (R/W)  ..................... 323
Table 4 53. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W) .................................................323
Table 4 54. XC_V T_SRC[1—14], XC1 VT  Mapper Source Configuration (R/W) ..................... . ........................... 3 24
Table 4 55.  XC_DJA _S RC[1—14], X C 1 Digital Jitter Attenuator Source Configuration (R/ W) ........................ . ... 324
Table 4 56. XC_FTP_SRC[1—14], XC1 Framer Transmit P ath Data Source Configuration (R/W) ..................... 324
Table 457. XC_FRS_SRC[1—14], X C 1 Framer Rec eive System Interfac e Source Configuration (R/W)  . ..... ....324
Table 4 58. XC_TPM_SRC[1—4],  XC1 Test-Pattern Monitor Source Configuration (R/W) ................................. 325
Table 459. XC 2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data Source Configuration (R/W)  ........ ..... ...........325
Table 460. XC 2_M23_SRC[1—7], XC2 M23 DS2 Data Source Configuration (R/W) .........................................325
Table 4 61. XC2_TPM_SRC, XC2 Te st-Pattern Mo nitor Source Configuration (R/W)  ........................................ 3 26
Table 462. XC_MISC, XC Global Register 2 (R/W) ............................................................................................ 326
Table 4 63. XC3_TPM_SRC, XC3 Te st-Pattern Mo nitor Source Configuration (R/W)  ........................................ 326
Table 4 64. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W) ................................................................ 327
Table 4 65. XC_P INS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W) ............................ 327
Table 4 66. XC_A LCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W) ............. 327
Table 467. Register Address Map ....................................................................................................................... 328

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

322 Agere Sy stem s Inc.

13 Cross Connect (XC) Registers (continued)

13.1 Cross Connect Register Descriptions

Table 448. XC_ID_R, XC Global Register 1 (RO)

Table 449. XC_CHI_M ODE1_R, X C S ystem Inter face Global Register 1 (R/W)

Table 450. XC_CHI_M ODE2_R, X C S ystem Inter face Global Register 2 (R/W)

DS1/E1 crosspoint conne ctivity i s determined by a set of source identifiers (SOURCE_IDs), one for each channel

leaving the crossp oint switch. A DS1/E1 SOURCE_ID is therefore defined as follows:

Address Bit Name Function Reset

Default

0x50000 15:11 —Reserved. 0x0005

10:8 XC_VERSION[2:0] Version. Th ese bits identify the version number of th e XC.

7:0 XC_ID[7:0] XC_ID. XC_ID register returns a fixed valu e (0x05) when

read.

Address Bit Name Function Reset

Default

0x5000E 15:3 —Reserved. 0x0000

2—Reserved. Must write to 0.

1 XC_SYNC_FOR_DATA Sync For Data. This bit should set to 1 if the transmit sys-

tem interface is in use (CHI, PSB, and NSMI). Se tting this

bit allows the ext ernal I/O pins LINETX SYNC[29—1] to

outpu t tra n smi t system data . Otherwise, se t to 0.

0 XC_SI_CHI PSB/CHI. This bit should be set t o 1 if the tran smit system

interface is in PSB mode; otherwise, 0 in CHI m ode.

Address Bit Name Function Reset

Default

0x5000F 15:14 —Reserved. 0x0000

13:0 XC_CHI_MODE

[1—7][1:0] CHI Mode. The 28 tra nsmit system links are broken down

into seven groups o f four. Each group is co ntrolled b y two

bits XC_CHI_MODE[1—7][1:0]. XC_CHI_MODE[1—7][1:0]

cont rols th e group of li nks 4i – 3, 4i – 2, 4i – 1, and 4i, where

i = 1 to 7. T he definition of C HI _MODE [1—7][1:0] is as fol-

lows:

00 = All four links within the group are normal outputs at

2 Mbits/s or 4 Mbits/s.

01 = Link s 4i – 3 and 4i – 2 are normal outputs; links 4i – 1

and 4i are combined into a single output on 4i; a nd out-

put 4i – 1 is used as T1/E1 line output.

10 = Links 4i – 1 and 4i are combined into a si ngle output on

4i; links 4i – 3 and 4i – 2 are combi ned into a single out-

put on 4i – 2; and outputs 4i – 1 and 4i – 3 a re used as

T1/E1 line o utputs.

11 = Al l four links are combined into a single output on 4i;

and the other three outputs are used as T1/ E1 line out-

puts.

Bit 76543210

SOURCE_ID SOURCE_BLOCK[2:0] CHANNEL_ID[4:0]

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

323Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

The SOURCE_BLOCK is defined as:

The CHANNEL_ ID ty pically ranges from 1 to 28 (29 for external). Values 0, 30, and 31 (and usually 29 as well) are

unused. The above definition is valid for X C _PDATA[1—2 9], XC_RP_RDAT A[1—28], XC_MDS1DATA[1—29]

(Table 453), XC_VD ATA[1—28] (Table 454), XC_SYNC[1—29] (Table 465), and XC_ALCO [1—29] (Table 466).

Table 452. XC_FRP_SRC[1—14], XC1 Framer Receive Path Data Source Configuration (R/W)

Table 453. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W)

Index Block Identifier Index Block Identifier

000 TPG (Test-Pattern Generat or)/Spec ial 100 VTMPR (VT Mapper)

001 PIN (External I/O) 101 DJA (J itter Attenuator)

010 FRM TP (Superframer) 110 FRM RP (Framer Line Interface)

011 M13 (M1 3 MUX) 111 FRM TS (Framer Sy s tem Interface)

Table 451. XC_PIND_SRC[1—15], XC1 External I /O TXDATA and TXCLK Sou rce Con f i guration ( R /W)

Address Bit Name Function Reset

Default

0x50010

—

0x5001D

15:8 XC_PDATA

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

Source Identi fier fo r External I/ O Pin LINETXDATA and

LINET XCLK Conn e c tio n. Exte rnal I /O DS1/E1 data and

clock (even cha nnels).

0x1E

(invalid)

0x5001E 15:8 —Reserved.0x00

0x50010

—

0x5001E

7:0 XC_PDATA

[1, 3, . . . 29][ 7:0]

(SOURCE_ID)

Source Identi fier fo r External I/ O Pin LINETXDATA and

LINET XCLK Conn e c tio n. Exte rnal I /O DS1/E1 data and

clock (odd channels).

Note: Exter nal I/O has 29 channels.

0x1E

(invalid)

Address Bit Name Function Reset

Default

0x50020

—

0x5002D

15:8 XC_RP_RDATA

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

So urce Identifier for Framer Receive Path Connecti on.

Framer receive path DS1/E1 input signals RP_RDATA,

RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (e ven channels).

0xFF

(invalid)

0x50020

—

0x5002D

7:0 XC_RP_RDATA

[1, 3, . . . 27][ 7:0]

(SOURCE_ID)

So urce Identifier for Framer Receive Path Connecti on.

Framer receive path DS1/E1 input signals RP_RDATA,

RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (odd channels ).

0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50030

—

0x5003D

15:8 XC_MDS1DATA

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

So urce Identifier for M13 MUX Connection. M13 DS1/E1

data and cloc k inputs (e v en channels). Also f or stuff request

inputs if operating in LOW_CLOC K_OUT mode.

0xFF

(invalid)

0x50030

—

0x5003D

7:0 XC_MDS1DATA

[1, 3, . . . 27][ 7:0]

(SOURCE_ID)

So urce Identifier for M13 MUX Connection. M13 DS1/E1

data and clock inputs (odd channels). Also f o r stuff request

inputs if operating in LOW_CLOC K_OUT mode.

0xFF

(invalid)

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

324 Agere Sy stem s Inc.

13 Cross Connect (XC) Registers (continued)

Table 454. XC_VT_SRC[1—14], XC1 VT Mappe r S ource Configu ration (R/W)

Table 455. XC_DJA_SRC[1—14], XC1 Digital Jitter Attenuator Source Configurat ion ( R/W)

Table 456. XC_FTP_SRC[1—14], XC1 Framer Transmit Path Data Source Configurati on (R/W)

Table 457. XC_FRS_SRC[1—14], XC1 Framer Receive System Interface Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x50040

—

0x5004D

15:8 XC_VDATA

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

Source Identifier for VT Mapper Connection. VT mapper

DS1/E1 data, clock, sync, and RA I i nputs (even channels). 0xFF

(invalid)

0x50040

—

0x5004D

7:0 XC_VDATA

[1, 3, . . . 27][ 7:0]

(SOURCE_ID)

Source Identifier for VT Mapper Connection. VT mapper

DS1/E1 data, clock, sync, and RA I i nputs (odd channels). 0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50050

—

0x5005D

15:8 XC_JDATA

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

So urce Identifier for Jitter Attenuator Connectio n. DJA

DS1/E1 data, clock, pointer adjustme nt, and autoA IS i nputs

(even channel s ).

0xFF

(invalid)

0x50050

—

0x5005D

7:0 XC_JDATA

[1, 3, . . . 27][ 7:0]

(SOURCE_ID)

So urce Identifier for Jitter Attenuator Connectio n. DJA

DS1/E1 data, clock, pointer adjustme nt, and autoA IS i nputs

(odd c hannels).

0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50060

—

0x5006D

15:8 XC_TP_RDATA

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

Source Identifier for Framer Transm it Path Connection.

Framer transmit pat h DS1/E1 input signals (even chan nels). 0xFF

(invalid)

0x50060

—

0x5006D

7:0 XC_TP_RDATA

[1, 3, . . . 27][ 7:0]

(SOURCE_ID)

Source Identifier for Framer Transm it Path Connection.

Framer transmit path DS1/E1 input signals (odd channels). 0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50070

—

0x5007D

15:8 XC_RS_D

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

Source Identifier for Framer Receive System Interface

Connection. Fram er receive syste m (RS) data i nput (even

channels).

0x00

(invalid)

0x50070

—

0x5007D

7:0 XC_RS_D

[1, 3, . . . 27][ 7:0]

(SOURCE_ID)

Source Identifier for Framer Receive System Interface

Connection. Fram er receive syste m (RS) data i nput (odd

channels).

0x00

(invalid)

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

325Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 458. XC_TP M_SRC[1—4], XC1 Test-P attern Monitor Source Configuration (R/W)

The DS2 crosspoint’s connectivity is determined by a smaller set of source2 identifie rs (SOURCE2_IDs), one for

each channel leaving the DS2 crossp oint swi tch XC2. A DS2 SOURCE2_ID is therefore defined as follows:

The SOURCE2_BLOCK is defined as f ol lows:

The CHANNEL2_ID typically ranges from 1 to 7. For test data ( SOURCE2_BLOCK = 0), value 4 represents the

DS2 test p a tte rn. F o r DS2 sig nal s route d from external pins to the input of M23 MUX o r TPM, the CHANNEL2_ID

can range from 1 to 29 .

Table 459. XC2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data S ource Config uration (R/W)

Table 460. XC2_M23_SRC[1—7], XC 2 M23 DS2 Data Source Confi guration (R/W)

Address Bit Name Function Reset

Default

0x50080 15:8 —Reserved. 0x00

7:0 XC_TPM_DS1_DATA[7:0]

(SOURCE_ID) Source Identifier for TPM DS1 Data Pattern . Source

identifier f or te st-pattern monitor (TPM) DS1 test channel

inputs.

0xFF

(invalid)

0x50081 15:8 —Reserved. 0x00

7:0 XC_TPM_DS1_IDLE[7:0]

(SOURCE_ID) Sou rce Identifier for TPM DS1 Idle Pattern. S ourc e

iden tifier for TPM DS1 idl e channel inputs. 0xFF

(invalid)

0x50082 15:8 —Reserved. 0x00

7:0 XC_TPM_E1_DATA[7:0]

(SOURCE_ID) Source Identifier for TPM E1 Data Pattern. Source

identifier for TPM E1 test channel inputs. 0xFF

(invalid)

0x50083 15:0 —Reserved. 0x0000

Bit 7 6 5 43210

SOURCE2_ID 0 SOURCE2_BLOCK[1:0] CHANNEL2_ID[4:0]

Index Block2 Identifier

00 TPG (DS2 Test -Pattern Generat or)

01 M13:M12 MUX

10 M13:M23 DeM U X

11 External I/O

Address Bit Name Function Reset

Default

0x50090

—

0x50096

15:8 XC2_DS2M12CLK

[1—7][7:0]

(SOURCE_ID)

So urce Ide ntifier for High-speed DS2 Clock Input to

M12 M ult iplexers Connection. DS2 clock input to M12

multiplexers. Refer to M12 MUX section for more details.

0x0040

(invalid)

0x50090

—

0x50096

7:0 XC2_M21[1—7][7:0]

(SOURCE_ID) Source Ide ntifier for High-speed DS2 Data and Clock

Connection. DS2 data and clock inputs to M12 demulti-

plexers. Refer to M12 de M U X sec tion for more details.

Address Bit Name Function Reset

Default

0x500A0

—

0x500A6

15:8 —Reserved. 0x0040

(invalid)

7:0 XC2_MDS2M23DATA

[1—7][7:0]

(SOURCE2_ID)

Source Identifier for M23 I nput DS2 Signals Connec-

tion. When SOURCE2_B LOCK = 11, CHANNEL2_ID

can range from 1 to 29.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

326 Agere Sy stem s Inc.

13 Cross Connect (XC) Registers (continued)

Table 461. XC2_TPM_S RC, XC2 Test-Pattern Monitor Source Configuration (R/W)

Table 462. XC_MISC, XC Global Register 2 (R/W)

Table 463. XC3_TPM_S RC, XC3 Test-Pattern Monitor Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x500A8 15:8 —Reserved. 0x0000

(invalid)

7:0 XC2_TSOURCE_ID[7:0] XC 2 TPM Sou rce Co nne cti on . Source2 identifier f or TPM

DS2 test data. When externa l I/ O is selected

(SOURCE2_BLOCK = 11), CHANNEL2_ID can r ange

from 1 to 29.

Address Bit Name Function Reset

Default

0x500C0 15:6 —Reserved. 0

5 XC_DS2ALCOEN M 23 DS2 Clock Out. Setting this bit to 1 enables DS2 low

clock-out mode from M23. Setting this bit to 0 sele cts t he nor-

mal DS2 clock and data input mode.

4 XC_DS1ALCOEN M 12/M13 DS1 Clock Out. Setting this bit to 1 enables DS1

low clock-out mode from M12/M13. Setting this bit to 0 selects

the no rmal DS1 clock and data input m ode.

3 XC_RPOAC_EN Receive POAC Enable. Setting this bit to 1 enables RPOAC

channel output and 0 to disable. 0

2 XC_TPOAC_EN Tr ansm it POAC Ena b le. Setting this bit to 1 enables TP OAC

channel output and 0 to disable. 0

1 XC_RSTS1_TUG3 Receive P OAC Channel Select. Sele ctor for TMUX (logic 1)/

SPEMPR (logic 0) receive POAC channel. 0

0 XC_TSTS1_TUG3 T ransmit POA C Channel Select. Selector for TMUX (logic 1)/

SPEMPR (logic 0) transmit POAC channel. 0

Address Bit Name Function Reset

Default

0x500D3 15:8 —Reserved. 0x0000

7—Reserved. Must write to 0.

6:5 XC3_TSOURCE_ID[1:0] TPG/TP M D S 3 Source. Source identifier for TP M DS3 test

data.

00 = TPM rec eives DS3 from external pins.

01 = TPG a nd TPM are connected t o M13 through NSMI

interface.

10 = TPM rec eives DS3 from SPE.

11 = Reserved.

4:0 —Reserved. Must write to 0.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

327Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 464. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W)

Table 465. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC S ource Config uration (R/W)

Table 466. XC_ALCO_SRC[1—15], XC1 Ex ternal I/O RXCLK Clock Out Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x500D4 15:2 —Reserved. 0x0000

1:0 XC3_SOURCE_ID[1:0] DS3 Level Con nections. This reg ister defines the conne c-

tivity at DS3 level among external I/O, M13, and SPE.

00 = M13 inputs/out puts DS3 through external pins .

01 = M1 3 an d SPE pass data to each other .

10 = SPE inputs /outputs DS3 through external pins and M13

is u se d as a monitor for t he transmit DS3.

11 = SPE inputs /outputs DS3 through external pins and M13

is u se d as a monitor for the receive D S3.

Address Bit Name Function Reset

Default

0x500E0

—

0x500ED

15:8 XC_SYNC

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

Source Identifier for External I/ O Pin LINETXSYNC. (Even

channels.) In the LIU mode, these registers must be pro-

grammed the same as XC_PIND_ SRC[1—15] (Table 451)

regist ers; in th e syste m interf ac e mode (CHI, PSB, and f ramer

o nly), these re gisters w ill be programmed separately to

ensure the system data output properly.

0xFF

(invalid)

0x500EE 15:8 —Reserved. 0x00

0x500E0

—

0x500EE

7:0 XC_SYNC

[1, 3, . . . 29][ 7:0]

(SOURCE_ID)

Source Identifier f o r External I/O Pin LINETXSYNC (Odd

channels).

Note: Exter nal I/O has 29 channels.

0xFF

(invalid)

Address Bit Name Function Reset

Default

0x500F0

—

0x500FD

15:8 XC_ALCO

[2, 4, . . . 28][ 7:0]

(SOURCE_ID)

Source Identifier f o r External I/ O Pin LINE RXCLK when

Operating in Low Clock Output Mode. (Either DS1/E1 or

D S2.) For D S1/E1 c hannels, the programmed value of these

registers should be consistent with those of r egisters

XC_PIND_SRC[1—15] (Table 451) to ensure that clock and

data for the sam e channel always will be routed together;

w hile for DS2 c hannels, the value of these registers should

matc h t hos e of reg isters XC2_M23_SRC[1—7] (Table 460)

(even channel s ).

0xFF

(invalid)

0x500FE 15:8 —Reserved. 0x00

0x500F0

—

0x500FE

7:0 XC_ALCO

[1, 3, . . . 29][ 7:0]

(SOURCE_ID)

Source Identifier f o r External I/ O Pin LINE RXCLK when

Operating in Low Clock Output Mode. (Either DS1/E1 or

D S2.) For D S1/E1 c hannels, the programmed value of these

registers should be consistent with those of r egisters

XC_PIND_SRC[1—15] (Table 451) to ensure that clock and

data for the sam e c hannel will always be routed together;

w hile for DS2 c hannels, the value of these registers should

matc h t hos e of reg isters XC2_M23_SRC[1—7] (odd chan-

nels).

Note: Exter nal I/O has 29 channels.

0xFF

(invalid)

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

328 A

ere S

stems Inc.

13 Cross Connect (XC) Registers (continued)

13.2 Cross Connect Register Map

Table 467. Register Address Map

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addr Symbo l Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Cross Connect Global—RO

0x50000 XC_ID_R XC_VERSION[2:0] XC_ID[7:0]

0x50001

—

0x5000D

—

Framer System Interface Control—R/W

0x5000E XC_CHI_MODE1_

R0 XC_SYNC_

FOR_DATA XC_SI_CHI

0x5000F XC_CHI_MODE2_

RXC_CHI_MODE7[1:0] XC_CHI_MODE6[1:0] XC_CHI_MODE5[1:0] XC_CHI_MODE4[1:0] XC_CHI_MODE3[1:0] XC_CHI_MODE2[1:0] XC_CHI_MODE1[1:0]

DS1/E1 Crosspoint Configuration—R/W

External I/O (LINETXDATA[1—29] and LINETXCLK[1—29] Pins) Data and Clock Output Selects

0x50010

—

0x5001D

XC_PIND_SRC[1—

14] XC_PDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_PDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5001E XC_PIND_SRC15 XC_PDATA29[7:0] Source_ID

0x5001F —

DS1/E1 Crosspoint Configuration—R/W

Framer Receiv e P ath Selects

0x50020

—

0x5002D

XC_FRP_SRC[1—

14] XC_RP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_RP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5002E

0x5002F

DS1/E1 Crosspoint Configuration—R/W

M13 MUX Selects

0x50030

—

0x5003D

XC_M13_SRC[1—

14] XC_MDS1DATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_MDS1DATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5003E

0x5003F

DS1/E1 Crosspoint Configuration—R/W

VT Mapper Sel ects

0x50040

—

0x5004D

XC_VT_SRC[1—

14] XC_VDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_VDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5004E

0x5004F

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

329Agere Sy stem s Inc.

13 Cross Connect (XC) Registers (continued)

Table 467. Register Address Map (continued)

AddrSymbol Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

DS1/E1 Crosspoint Configurati on —R/W

Jitter Attenu ation Selec ts

0x50050

—

0x5005D

XC_DJA_SRC[1—

14] XC_JDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_JDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] So urce_ID

0x5005E —

0x5005F —

DS1/E1 Crosspoint Configurati on —R/W

Framer Transmit Path Selects

0x50060

—

0x5006D

XC_FTP_SRC[1—

14] XC_TP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_TP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5006E

—

0x5006F

—

DS1/E1 Crosspoint Configurati on —R/W

Fram er RS (System Interfac e) Selects

0x50070

—

0x5007D

XC_FRS_SRC[1—

14] XC_RS_D[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_RS_D[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5007E

—

0x5007F

—

Test-Patte rn Moni to r (TPM) Input s

0x50080 XC_TPM_SRC1 XC_TPM_DS1_DATA[7:0] Source_ID

0x50081 XC_TPM_SRC2 XC_TPM_DS1_IDLE[7:0] Source_ID

0x50082 XC_TPM_SRC3 X C_TPM_E1_DATA[7:0] Source_ID

0x50083 XC_TPM_SRC4

0x50084

0x5008F

—

DS2 Crosspoint Configuration—R/W

M12 MUX/DeMUX Selec ts

0x50090

—

0x50096

XC2_M12_SRC[1—

7] XC2_DS2M12CLK[1—7][7:0] Source_ID XC2_M21_[1—7][7:0] Source_ID

0x50097

—

0x5009F

—

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

330 A

ere S

stems Inc.

13 Cross Connect (XC) Registers (continued)

Table 467. Register Address Map (continued)

Addr Symbo l Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DS2 Crosspoint Configuration—R/W

M23 MUX Selects

0x500A0

—

0x500A6

XC2_M23_SRC[1—

7] XC2_MDS2M23DATA[1—7][7:0] Source2_ID

0x500A7 —

DS2 Crosspoint Configuration—R/W

Test-Pattern Monitor (TPM) Inputs

0x500A8 XC2_TPM_SRC XC2_TSOURCE_ID[7:0] Data Source2_ID

0x500A9

—

0x500BF

—

Miscellaneous

0x500C0 XC_MISC XC_DS2

ALCOEN XC_DS1

ALCOEN XC_RPOAC

_EN XC_TPOAC

_EN XC_RSTS1_

TUG3 XC_TSTS1_

TUG3

0x500C1

—

0x500D2

—

DS3 Crosspoint Configuration—R/W

0x500D3 XC3_TPM_SRC 0 XC3_TSOURCE_ID[1:0] 00000

0x500D4 XC3_MDS3_SRC XC3_SOURCE_ID[1:0]

0x500D5

—

0x500DF

—

DS1/E1 Crosspoint Configuration—R/W

Ex ternal I/O (LINETXSYNC Pins) Sync Selects

0x500E0

—

0x500ED

XC_PINS_SRC[1—

14] XC_SYNC[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] SOURCE ID XC_SYNC[1, 3 , 5 , 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] SOURCE_ID

0x500EE XC_PINS_SRC15 XC_SYNC29[7:0] S OURCE_ID

0x500EF —

DS1/E1 Crosspoint Configuration—R/W

Low Clock Out Selects

0x500F0

—

0x500FD

XC_ALCO_SRC[1

—14] XC_ALCO[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_ALCO[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x500FE XC_ALCO_SRC15 XC_ALCO29 Source_ID

0x500FF —

Prelim inary Data Sheet TMXF28155 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
331Agere Systems In c.  
14 Digital Jitter Attenuation Co ntroller Registers
Ta ble of Con tents
Contents Page
14 Digital Jitter Attenuation Control ler Registers  .................... ..... .. ..... ....... .. ..... ..... .. ....... ..... .. ..... .........................331
14.1  Digital  Jitter Attenuation Controller Register Descriptions .......................................................................332
14.2  Digital Jitter Attenuation Controller Register Map ...................................................................................335
Tables Page
Table 468. DJA_VERSION, DJA Version and Identification (RO) .............. ... ....................... ... ............................332
Table 469. DJA_EVENT1—DJ A_EVE NT2 , Loss of Clock an d O v erflow/Und erflow De lta 
(COR/COW) .......................................................................................................................................332
Table 470. DJA_MASK1—DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W) . . ........... ............332
Table 471. DJA_STATE1—DJA _STATE2, Loss of Clock and VT Pointer Adjustm ent Indicators 
(R/W) ..................................................................................................................................................333
Table 472. DJA_E1GAINH—DJA_E1 G AINL, E 1 A ccumulator G ain Threshold (R/W) ............................ ............333
Table 473. DJA_DS1GAINH—DJA_DS1G AINL, DS1 Accumulator  Gain Threshold (R /W) ................................333
Table 474. DJA_E1SCALE, E1 Scale Factor (R /W) ........................................................................ ......... ...........333
Table 475. DJA_DS1SCALE, DS1 Scale Factor (R/W) .......................................................................................333
Table 476. DJA_E1PTRH—DJA_E1PTRL, E1 First-Order Loop Counter (R/W)   ...............................................334
Table 477. DJA_DS1PTRH—DJA_DS1PTRL, DS1  First-Order Loop Counter (R/W)  ........... . .................. ..........334
Table 478. DJA_DS1SELH—DJA_DS1SEL L, DS1 E1 Mode Select (R/W)   ................... ................. ... ................334
Table 479. DJA_CLK_CTL1—DJA _CLK_CTL4, Reference Clo ck  Rate and Edge Transitions (R/W)  ...............334
Table 480. DJA Register Map ..............................................................................................................................335

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

332 Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

14.1 Dig ita l Jitter Atte nuation Controller R egis ter Des cription s

This section gives a brief de scription of each register bit and its functionalit y. The abbreviations after each register

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/writ e (R/W) .

Table 468. DJ A_VERSION, DJA Versi on and Identif ication (R O)

Table 469. DJA_ EVE NT1—DJA_EVENT2, Lo ss of Clock and Overflow/Underflow Delta

(COR/COW)

Table 470. DJA_ MASK 1—DJA _MASK 2, Loss of Clock and Ov er f low/Underflow Masks (R/W)

Address Bit Na m e Function Reset

Default

0x70000 15:11 —Reserved. 00000

10:8 DJA_VERSION[2:0] Block Version Num ber. Block ve rsion register

wi ll change each time the device is changed. 0x0

7:0 DJA_ID[7:0] Block ID Number. 0x7

Address Bit N am e Function Reset

Default

0x70003 15 DJA_G_DS1_DLT G_PIN_DS1XCLK Loss of Clock Delta. 0

14 DJA_DS1_DLT P IN_DS1 XCLK L oss of Clock Delta. 0

13 DJA_G_E1_DLT G_PIN_E1XCLK Loss of Clock Delta . 0

12 DJA_E1_DLT PIN_E1XCLK Loss of Clock Delta. 0

0x70003

0x70004 11:0

15:0 DJA_ESOVFL[28:17]

DJA_ESOVFL[16:1] Elastic Store Overflow/Underflow Event. 0x0

Address Bit N am e Function Reset

Default

0x70006 15 DJA_G_DS1_MSK G_ PIN_DS1X CLK Loss of Clock In dication

Mask. 1

14 DJA_DS1_MSK PIN_DS1XCLK L os s of Clock Indication

Mask. 1

13 DJA_G_E1_MSK G_PIN _ E1XC LK Los s of C lock Indic ation

Mask. 1

12 DJA_E1_MSK PIN _E1XC LK Lo ss of Clock Indication Mask. 1

0x70006

0x70007 11:0

15:0 DJA_ESOVFL_MSK[28:17]

DJA_ESOVFL_MSK[16:1] Elastic Store Over/Underflow Indication

Mask. 0xFFFFFFF

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

333Agere Systems In c.

14 Digital Jitter Attenuation Controller Registers (continued)

Table 471. DJA_STATE1—DJA_STATE 2, Loss o f Cloc k and VT Pointer Ad jus tment Indicator s

(R/W)

Table 472. DJA_E1GAINH—DJ A_E1GAINL, E1 Accumulator Gain Threshold (R/W)

Table 473. DJA_DS1GAINH—DJ A_DS1GAINL, DS1 Accumulator Gain Threshold (R/W)

Table 474. DJA_E1SCALE, E1 Scale Factor (R/W)

Table 475. DJA_DS1SCALE, DS1 Scale Factor (R/W)

Address Bit N am e Fun ction Re set

Default

0x70009 15 DJA_G_DS1LOC G_PIN_DS1XCLK Loss of Cl ock Ind ic ation. (1 = LOC.) 0

14 DJA_DS1LOC PIN_DS1XCLK Loss of Clock Indication. (1 = LOC.) 0

13 DJA_G_E1LOC G_PIN_E1 XCLK Loss of Clock Indication. (1 = LOC.) 0

12 DJA_E1LOC PI N _ E1X C LK Los s of Clock Indication. (1 = LOC.) 0

0x7000A

15:11

11:0

15:0

—

DJA_PTRADJS[28:17]

DJA_PTRADJS[16:1]

Reserved.

VT P ointer Adjustment Indicator State. When this state

is high, the associated PLL has experienced a VT pointer

adjustment within the last PTRADJCNT register specified

time interval.

Address Bit Name Function Reset

Default

0x7000B

0x7000C

15:11

10:0

15:0

—

DJA_E1GAIN[26:16]

DJA_E1GAIN[15:0]

Reserved.

E1 Gain. Accu mulator gain thresh old at which a

clock adjustment takes place for E1 signals (see

Table 622, PLL B andwidth Control Parameters

on page573 ).

0x7FFFFFF

Address Bit Name Function Reset

Default

0x7000D

0x7000E

15:11

10:0

15:0

—

DJA_DS1GAINTHR[26:16]

DJA_DS1GAINTHR[15:0]

Reserved.

DS1 Gain. Accumulator gain threshold at which

a clock adjustment takes place for DS1 signals

(see Table 622).

0x7FFFFFF

Address Bit Name Fu nction Reset

Default

0x7000F 15:0 DJA_E1SCALE[15:0] E1 Scale. Scale factor that controls clock adjust-

ment rate s for E1 signals (see Table 622). 0xFFFF

Address Bit Name Fu nction Reset

Default

0x70010 15:0 DJA_DS1SCALE[15:0] DS1 Scale. Scale factor that control s clock

adjustment rates for DS1 si gnals (see

Table 622).

0xFFFF

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

334 Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

Table 476. DJA_E1PTRH—DJA_E1PTRL, E1 First-Or der Loop Counter (R/W)

Table 477. DJA_DS1PTRH—DJA_DS1PTRL, DS1 First-O rder Loop Counter (R/W)

Table 478. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W)

Table 479. DJA_CLK_CT L1—DJA_CLK_CTL4, Referen ce Clock Rat e and Edge Transitions (R/W)

Address Bit N am e Function Reset

Default

0x70011

0x70012

15:5

4:0

15:0

—

DJA_E1PTRADJCNT[20:16]

DJA_E1PTRADJCNT[15:0]

Reserved.

E1 First-Order Loop Count. Count val ue that

determines the amount of time spent as a fir st -

order loop following a VT pointer adjustment in

E1 mode (see Table 623, F irst-Order Mode Dura-

tion Control on page573 ).

0x177000

Address Bit N am e Function Reset

Default

0x70013

0x70014

15:5

4:0

15:0

—

DJA_DS1PTRADJCNT[20:16]

DJA_DS1PTRADJCNT[15:0]

Reserved.

DS 1 First-Order Loop Count . Count value that

determines the amount of time spent as a fir st -

order loop following a VT pointer adjustment in

DS1 mode (see Table 623).

0x11AB70

Address Bit Name Function Reset

Default

0x70015

0x70016

15:12

11:0

15:0

—

DJA_DS1SEL[28:17]

DJA_DS1SEL[16:1]

Reserved.

DS1 E1 Mode Select. Control signal that deter-

mines the operating mode of each jitter attenua-

tion block (1 = DS1, 0 = E1).

0xFFFFFFF

Address Bit Name Function Res et

Default

0x70017 15:14 —Reserved.

13:12 DJA_BLUECLKD1[1:0] Ref e rence Clock Rate. Control signal that indi-

cates that the input XCL K runs at 32 X (11) or

16 X (01) t he lin e rate or exactly the line rate

(00).

111

0x70017

0x70018 11:0

15:0 DJA_TXEDGE[28:17]

DJA_TXEDGE[16:1] Transmit Edge Sel ect. Control signal that deter-

mines on which edge of the clo ck the output

DS1/E1 data transitions (1 = rising edge).

0xFFFFFFF

0x70019

0x7001A

15:12

11:0

15:0

—

DJA_RXEDGE[28:17]

DJA_RXEDGE[16:1]

Reserved.

Receive Edg e Select. Control signal that det er-

mines on which edge of the clock the input

DS1/E1 data is re timed (1 = rising edge).

0xFFFFFFF

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

335Agere Sy stem s Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

14.2 Digital Jitter Attenuation Controller Register Map

The registe r bank arc hitecture of the microproces sor interface is shown in Table 76 on page73 .

Table 480. DJA Register Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 1 2 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ID and Interrupt Registers (RO)

0x70000 DJA_VERSION DJA_VERSION[2:0] DJA_ID[7:0]

0x70001

0x70002 —

Del ta and E ven t Pa ramet ers (COR/COW)

0x70003 DJA_EVENT1 DJA_G_DS1DLT DJA_G_E1DLT DJA_DS1DLT DJA_E1DLT DJA_ESOVFL[28:17]

0x70004 DJA_EVENT2 ESOVFL[16:1]

0x70005 —Interrup t M ask Para me ters for INT Pins (R/W )

0x70006 DJA_MASK1 DJA_G_DS1MSK DJA_G_E1MS

KDJA_DS1MS

KDJA_E1MSK DJA_ESOVFL[28:17]

0x70007 DJA_MASK2 ESOVFL[16:1]

0x70008 —State and Value Parameters (RO)

0x70009 DJA_STATE1 DJA_G_DS1LOC DJA_G_E1LO

CDJA_DS1LOC DJA_E1LOC DJA_PTRADJS[28:17]

0x7000A DJA_STATE2 DJA_PTRADJS[16:1]

Control Parameters for PLL Bandwidth and Mode (R/W)

0x7000B DJA_E1GAINH DJA_E1GAIN[26:16]

0x7000C DJA_E1GAINL DJA_E1GAIN[15:0]

0x7000D DJA_DS1GAINH DJA_DS1GAIN[26:16]

0x7000E DJA_DS1GAINH DJA_DS1GAIN[15:0]

0x7000F DJA_E1SCALE DJA_E1SCALE[15:0]

0x70010 DJA_DS1SCAL

EDJA_DS1SCALE[15:0]

0x70011 DJA_E1PTRH DJA_E1PTRADJCNT[20:16]

0x70012 DJA_E1PTRL DJA_E1PTRADJCNT[15:0]

0x70013 DJA_DS1PTRH DJA_DS1PTRADJCNT[20:16]

0x70014 DJA_DS1PTRL DJA_DS1PTRADJCNT[15:0]

0x70015 DJA_DS1SELH DJA_DS1SEL[28:17]

0x70016 DJA_DS1SELL DJA_DS1SEL[16:1]

0x70017 DJA_TXEDGEH DJA_BLUECLKD[1:0] DJA_TXEDGE[28:17]

0x70018 DJA_TXEDGEL DJA_TXEDGE[16:1]

0x70019 DJA_RXEDGEH DJA_RXEDGE[28:17]

0x7001A DJA_RXEDGEL DJA_RXEDGE[16:1]

0x7001B

—

0x700FF

—

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
336 Agere Sy stem s Inc.
 
15 Test-P attern Generation/Detection Registers
Ta ble of Conte nts
Contents Page
15 Test-Pattern Generation/Detection Registers ....................... ....... ..... ....... . ......................... ....... . ..................... 336
15.1  Test-P attern Generation/Detection Register Descriptions ........................... ... ....................... ... .............. 337
15.2  Test-P attern Generation/Detection Register Map  ............. ... ......................... ..... ....... ..... ... ..................... 350
Tables Page
Table 481. TPG_ID , Status Re giste r (RO) .......................................................................................................... 337
Table 4 82. TPG_ISRC_OOF D, Delta Register (RO) ........................................................................................... 337
Table 483. TPG_ISRC_ OOSD, Delta  Register (RO) .......................................................................................... 337
Table 484. TPG_ISRC_ BERE, Event Reg ister (RO) .......................................................................................... 338
Tabl e  485. TP G_ISRC_FERE, Event Reg ister (RO) .. ......................................................................................... 338
Ta ble  486. TPG_ISR C_B PVE, Event Register (RO) .... ........................................... ............................................ 338
Table 4 87. TPG_ISRC_AISD, Delta Register (RO) ............................................................................................. 339
Table 488. TPG_I SRC_CRCE, Event Register (RO) ......................... .......................... .......................... ............. 339
Table 489. TPG_IMSK_OOFD, Register (R/W) .................................................................................................. 339
Table 4 90. TPG_IM SK_OOSD, Register (R/W) .................................................................................................. 339
Table 491. TPG_IMSK_BERE, Register (R/W) ................................................................................................... 340
Table 492. TPG_IMSK_FERE, Regi ster (R/W) ................................................................................................... 340
Table 493. TPG_IMSK_BPV, Register (R/W) ..................................................................................................... 340
Table 494. TPG_IMSK_AISD, Reg ister (R/W) .................................................................................................... 341
Table 495. TPG_IMS K_CRCE, Register (R/W)  .................................................................................................. 341
Table 496. TPG_VAL _OOF, Register (RO) ........................................................................................................ 341
Table 497. TPG_VAL_OOS, Register (RO) ........................................................................................................ 342
Table 4 98. TPG_VAL_AIS, Register (RO)  .......................................................................................................... 342
Table 499. TPG_VAL _FER, Register (RO) ......................................................................................................... 342
Table 500. TPG_VAL_CRCE, Register (RO) ...................................................................................................... 343
Table 5 01. TPG_BER_INSRT, Register (R/W) ................................................................................................... 343
Table 502. TPG_FER_INSRT, Registe r (R/W) ................................................................................................... 343
Table 5 03. T PG_CRCE_INSRT, Register (R/W)  ................................................................................................ 343
Table 504. TPG_ESFDL_TX, Register (R/W) ..................................................................................................... 344
Table 505. TPG_E1SA_TX12, Reg ister (R/W) .................................................................................................... 344
Table 506. TPG_E1SA_TX34, Reg ister (R/W) .................................................................................................... 344
Table 507. TPG_CONFIG0, Register (R/W) ....................................................................................................... 345
Table 508. TPG_CONFIG2, Register (R/W) ....................................................................................................... 346
Table 509. TPG_CONFIG4, Register (R/W) ....................................................................................................... 347
Table 510. TPG_CONFIG5, Register (R/W) ....................................................................................................... 348
Table 5 11. TPG_USER, Register (R/W) ............................................................................................................. 348
Table 5 12. TPM_USER, Register (R/W) ............................................................................................................. 348
Table 513. TPG_BER CNT0, Register (RO) ........................................................................................................ 348
Table 514. TPG_BER CNT2, Register (RO) ........................................................................................................ 349
Table 515. TPG_BER CNT4, Register (RO) ........................................................................................................ 349
Table 516. TPG_BER CNT5, Register (RO) ........................................................................................................ 349
Table 517. TPM_ESFDL_RX, Register (RO) ...................................................................................................... 349
Table 518. TPM_E1SA_RX12, Register (RO) ..................................................................................................... 349
Table 519. TPM_E1SA_RX34, Register (RO) ..................................................................................................... 349
Table 5 20. Test-Pattern Generation/Detection Register Map  ............................................................................. 350

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

337Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

15.1 Te st-Pattern Generation/Dete ction Re gister D esc riptions

The following ta bles describe the function s of all bits in the microproc es s or register map. For each address, the

Table 481. TPG_ID , Status Regist er (RO)

Table 482. TPG_ISRC_OOFD, Delta Register (RO)

Table 483. TPG_ISRC_OOSD, Delta Register (RO)

A ddress Bi t Nam e Fun ction Reset

Default

0x60000 15 TPG _RE ADY This bit signifies that TPG reset/initialization is complete. 1

14:11 —Reserved. 0x0

10:8 TPG_

VERSION[2:0] These bits identify the version number of the TPG. 0x0

7:0 TPG_ID[7 :0] TPG_ID returns a fixed value (0x06) when read. 0x06

Address Bit Name Function Reset

Default

0x60004 15:3 —Reserved. 0x0000

2 TPM _OO F2D This bit is set when the TPM mo n itor E1 test signal out-of-frame

detector changes state (tra n sitio ns ). 0

1—Reserved. 0

0 TPM_OOF0D This bit is set when the TPM monitor DS1 test signal out-of-frame

detector changes state (tra n sitio ns ). 0

Address Bit Name Function Reset

Default

0x60005 15:6 —Reserved. 0x000

5 TPM_OOS5 D This bit is set when the TPM mo n itor DS3 test signal out-of-sync

detector changes state (tra n sitio ns ). 0

4 TPM_OOS4 D This bit is set when the TPM mo n itor DS3 test signal out-of-sync

detector changes state (tra n sitio ns ). 0

3—Reserved. 0

2 TPM_OOS2 D This bit is set when the TPM mon itor E1 test signal out-of-sync

detector changes state (tra n sitio ns ). 0

1—Reserved. 0

0 TPM_OOS0 D This bit is set when the TPM mo n itor DS1 test signal out-of-sync

detector changes state (tra n sitio ns ). 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

338 Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 484. TP G_ISRC_BERE, E vent Register (RO)

Table 485. TPG_ISRC_FERE, Event Register (RO)

Table 486. TPG_I SR C _ BPVE, Event Regis ter (RO)

Address Bit Name Function Reset

Default

0x60006 15:6 —Reserved. 0x000

5 T PM_BERE 5 This bit is se t when the TPM monitor determines that the incom-

ing DS3 test signal has a s ingl e bit error. 0

4 T PM_BERE 4 This bit is se t when the TPM monitor determines that the incom-

ing DS2 test signal has a s ingl e bit error. 0

3—Reserved. 0

2 T PM_BERE 2 This bit is se t when the TPM monitor determines that the incom-

ing E1 test signal has a singl e bit error. 0

1—Reserved. 0

0 T PM_BERE 0 This bit is se t when the TPM monitor determines that the incom-

ing DS1 test signal has a s ingl e bit error. 0

Address Bit Name Function Reset

Default

0x60007 15:3 —Reserved. 0x000

2 TPM _FE R E2 This bit is set when the TPM monitor dete rm ines that the incom-

ing E1 test signal has a framing error. 0

1—Reserved. 0

0 TPM _FE R E0 This bit is set when the TPM monitor dete rm ines that the incom-

ing DS1 test signal has a f raming error. 0

Address Bit Name Function Reset

Default

0x60008 15:3 —Reserved. 0x0000

2 TPM_BPVE2 This bit is set when the TPM monitor determines that the inco m-

ing E1 test signa l has a bipolar violation error. 0

1—Reserved. 0

0 TPM_BPVE0 This bit is set when the TPM monitor determines that the inco m-

ing DS1 test signal has a bipolar violation error. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

339Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 487. TPG_ISRC_AISD, Delta Register (RO)

Table 488. TP G_ISRC_CRCE, Event Register (RO)

Table 489. TPG_IMSK_OOFD, Register (R/W)

Table 490. TPG_IMSK_OOSD, Register (R/W)

Address Bit Name Function Reset

Default

0x60009 15:6 —Reserved. 0x000

5 TPM_AIS5D This bit is set when the TPM monitors DS3 test signal A I S detec-

tor changes state (transitions). 0

4 TPM_AIS4D This bit is set when the TPM monitors DS2 test signal A I S detec-

tor changes state (transitions). 0

3—Reserved. 0

2 TPM_AIS2D This bit is set when the TPM monitors E1 test signal AI S de te cto r

changes state (transitions). 0

1—Reserved. 0

0 TPM_AIS0D This bit is set when the TPM monitors DS1 test signal A I S detec-

tor changes state (transitions). 0

Address Bit Name Function Reset

Default

0x6000A 15:3 —Reserved. 0x000

2 TPM_CRCE2 This bit is set when the TPM mo n itors E 1 CRC errors. 0

1—Reserved. 0

0 TPM_CRCE0 This bit is se t when the TPM monitors DS1 CRC errors. 0

Address Bit Name Function Reset

Default

0x60010 15:3 —Reserved. 0x000

2 TPM_OOF2DM This mask bit is set t o suppress an interrupt when the TPM moni-

tor E1 test sign al out-of-frame indicator cha nges. 1

1—Reserved. 0

0 TPM_OOF0DM This mask bit is set t o suppress an interrupt when the TPM moni-

tor DS1 test sign al out-of-frame indicat or changes. 1

Address Bit Name Function Reset

Default

0x60011 15:6 —Reserved. 0x000

5 T PM_OOS5DM Thi s mask bit is set to suppress an interrupt when the TPM moni-

tor DS3 test s ign al out-of-sync in dicator changes. 1

4 T PM_OOS4DM Thi s mask bit is set to suppress an interrupt when the TPM moni-

tor DS2 test s ign al out-of-sync in dicator changes. 1

3—Reserved. 0

2 T PM_OOS2DM Thi s mask bit is set to suppress an interrupt when the TPM moni-

tor E1 test sign al out-of-sync ind icato r change s. 1

1—Reserved. 0

0 T PM_OOS0DM Thi s mask bit is set to suppress an interrupt when the TPM moni-

tor DS1 test s ign al out-of-sync in dicator changes. 1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

340 Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 491. TPG_IMSK_BERE, Register (R/W)

Table 492. TPG_IMSK_FERE, Register (R/W)

Table 493. TPG_IMSK_BPV, Reg ister (R/W)

Address Bit Name Function Reset

Default

0x60012 15:6 —Reserved. 0x000

5 TPM_BE RE5M This m as k bit is set t o suppress an interrupt when the TPM moni-

tor determines that the incoming DS3 test signal has a bit error. 1

4 TPM_BE RE4M This m as k bit is set t o suppress an interrupt when the TPM moni-

tor determines that the incoming DS2 test signal has a bit error. 1

3—Reserved. 0

2 TPM_BE RE2M This m as k bit is set t o suppress an interrupt when the TPM moni-

tor determines that the incomin g E1 test si gnal has a bit error. 1

1—Reserved. 0

0 TPM_BE RE0M This m as k bit is set t o suppress an interrupt when the TPM moni-

tor determines that the incoming DS1 test signal has a bit error. 1

Address Bit Name Function Reset

Default

0x60013 15:3 —Reserved. 0x0000

2 TPM_FE R E2M This mas k bit is set to suppress an interrupt when the TPM moni-

tor determines that the E1 test signal has a framing error. 1

1—Reserved. 0

0 TPM_FE R E0M This mas k bit is set to suppress an interrupt when the TPM moni-

tor determines that the DS1 test sig nal has a framing error. 1

Address Bit Name Function Reset

Default

0x60014 15:3 —Reserved. 0x0000

2 TPM_BPV2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determi nes that the E1 test signal has a bipolar v iolation erro r. 1

1—Reserved. 0

0 TPM_BPV0M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the DS1 test sig nal has a bipolar violation

error.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

341Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 494. TPG_IMSK_AISD, Register (R/W)

Table 495. TPG_IMSK_CRCE, Register (R/W)

Table 4 96. TPG_VAL_OOF, Register (RO)

Address Bit Name Function Reset

Default

0x60015 15:6 —Reserved. 0x000

5 T PM_AIS5DM This mask bit is set t o suppress an interrupt when the TPM moni-

tor DS3 test sign al AIS indicator changes. 1

4 T PM_AIS4DM This mask bit is set t o suppress an interrupt when the TPM moni-

tor DS2 test sign al AIS indicator changes. 1

3—Reserved. 0

2 T PM_AIS2DM This mask bit is set t o suppress an interrupt when the TPM moni-

tor E1 test sign al AIS in dicat or changes. 1

1—Reserved. 0

0 T PM_AIS0DM This mask bit is set t o suppress an interrupt when the TPM moni-

tor DS1 test sign al AIS indicator changes. 1

Address Bit Name Function Reset

Default

0x60016 15:3 —Reserved. 0x0000

2 TPM_CRCE2M This mask bit is set to suppress an interr upt when the TPM moni-

tor detects an E1 test signal CRC-4 erro r. 1

1—Reserved. 0

0 TPM_CRCE0M This mask bit is set to suppress an interr upt when the TPM moni-

tor detects a DS1 test signal CRC-6 erro r. 1

Address Bit Name Function Reset

Default

0x60020 15:3 —Reserved. 0x0000

2 TPM_OO F2 This status bit is set whenever the TPM E1 test m onitor h as

encountered an out -of-frame condition. 1

1—Reserved. 0

0 TPM_OO F0 This status bit is set whenever th e T PM DS1 test m onitor has

encountered an out -of-frame condition. 1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

342 Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 4 97. TPG_VAL_OO S, Register (RO)

Table 498. TPG_VAL_AIS, Register (RO)

Table 499. TPG_VAL_FER, Register (RO)

Address Bit Name Function Reset

Default

0x60021 15:6 —Reserved. 0x000

5 TPM_OO S 5 This status bit is set whe never t he TPM DS3 test monitor has

encountered an out-of-sy nc condition. 1

4 TPM_OO S 4 This status bit is set whe never t he TPM DS2 test monitor has

encountered an out-of-sy nc condition. 1

3—Reserved. 0

2 TPM_OOS 2 Thi s sta tus bit is set whenever the TPM E1 test monitor has

encountered an out-of-sy nc condition. 1

1—Reserved. 0

0 TPM_OO S 0 This status bit is set whe never t he TPM DS1 test monitor has

encountered an out-of-sy nc condition. 1

Address Bit Name Function Reset

Default

0x60022 15:6 —Reserved. 0x000

5 TPM_AIS5 This status bit is set wh e never t he TPM DS3 test monitor has

encountered an AIS condition. 0

4 TPM_AIS4 This status bit is set wh e never t he TPM DS2 test monitor has

encountered an AIS condition. 0

3—Reserved. 0

2 TPM_ AIS2 This sta tus bit is set whenever the TPM E1 test monitor has

encountered an AIS condition. 0

1—Reserved. 0

0 TPM_AIS0 This status bit is set wh e never t he TPM DS1 test monitor has

encountered an AIS condition. 0

Address Bit Name Function Reset

Default

0x60023 15:3 —Reserved. 0x0000

2 TPM_FER2 Thi s sta tus bit is set whenever the TPM E1 test monitor has

encounter ed an FER condition. 0

1—Reserved. 0

0 TPM_FER0 This status bit is set whe never the T PM DS1 test monitor has

encounter ed an FER condition. 0

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

343Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 500. T PG_VAL_CRCE, Register (RO)

Table 501. TPG_BER_INSRT, Register (R/W)

Tabl e 502. TPG_ FER_INSRT, Register (R/W)

Table 503. T PG_CRCE_INSRT, Register (R/W)

Address Bit Name Function Reset

Default

0x60024 15:3 —Reserved. 0x0000

2 TPG_CR C EINS 2 This bit is set when the user desires to inject a single CRC error

into the E 1 test signal (via 0 to 1 transition). 0

1—Reserved. 0

0 TPG_CR C EINS 0 This bit is set when the user desires to inject a single CRC error

into the DS1 test signal (Via 0 to 1 transition ). 0

Address Bit Name Function Reset

Default

0x60028 15 TPG_B E R_E N This bit, whe n set , all ows automatic bit error insertion by the

microprocessor. 0

14:6 —Reserved. 0x000

5 TPG_BERINS5 This bit is set when the user desires to inject a single bit error into

the DS3 test signal via SMPR_B ER_INSRT (Table 65,

SMPR_G TR, Global Trigger Re gister (RW) o n pag e 66).

4 TPG_BERINS4 This bit is set when the user desires to inject a single bit error into

the DS2 test signal via SMPR_B ER_INSRT. 0

3—Reserved. 0

2 TPG_BERINS2 This bit is set when the user desires to inject a single bit error into

the E1 test signal via SMPR_BER_IN SRT. 0

1—Reserved. 0

0 TPG_BERINS0 This bit is set when the user desires to inject a single bit error into

the DS1 test signal via SMPR_B ER_INSRT. 0

Address Bit Name Function Reset

Default

0x60029 15:3 —Reserved. 0x0000

2 T PG_FERI NS2 T h is bit i n jects a s i ng l e fr a mi ng e rror into the E1 test signal (v i a 0

to 1 transition). 0

1—Reserved. 0

0 TPG_FERINS0 Thi s bit injects a single framing error into the DS1 test signal (via

0 to 1 transition ). 0

Address Bit Name Function Reset

Default

0x6002A 15:3 —Reserved. 0x0000

2TPG_

CRC4EINS2 Th is bit is set when the user desires to inject a single CRC-4 error

into the E 1 test signal (via 0 to 1 transition). 0

1—Reserved. 0

0TPG_

CRC6EINS0 This bit is set when the user desires to inject a single

CRC-6 error Into the DS1 test signal (via 0 to 1 transition). 0

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

344 Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 504. TPG_ESFDL_TX, Register (R/W)

Table 5 05. TPG_E1SA_TX12, Register (R/W)

Table 5 06. TPG_E1SA_TX34, Register (R/W)

A ddress Bit Name Function Reset

Default

0x6002C 15:0 TPG_ESFDL[15:0] Data -Link Field to be Sent with Each DS1 Idle Fra m e. 0x7E7E

Address Bit Name Function Reset

Default

0x6002E 15:13 —Reserved . 0x0

12:8 TPG_E1SA2[4:0] Sa (sp are bits [8:4]) to be Sent with E1 Idle Fram e. 0x00

7:5 —Reser ved. 0x0

4:0 TPG_E1SA1[4:0] Sa (spare bits [8:4]) to be Sent with E1 Idle Frame. 0x00

A ddress B it Name Function Reset

Default

0x6002F 15:13 —Reserved. 0x0

12:8 TPG_E1SA4[4:0] Sa (spare bits [8:4]) to be Sent with E1 Test Frame. 0x00

7:5 —Reserved. 0x0

4:0 TPG_E1SA3[4:0] Sa (spare bits [8:4]) to be Sent with E1 Test Frame. 0x00

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

345Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 507. T PG_CONFIG0, Register (R/W)

A ddres s Bit Name Function Reset

Default

0x60030 15: 13 TPM_ SEQ0[2:0] These bits select the test pattern to be monitored by the TPG on

the DS1 test input. 000

12 TPM_TPINV0 This bit, if set, inverts the received data for DS1 test si gnals. 0

11 TPG_TPIN V0 This bit, if set, inve rts t he transmitted data for DS1 t est signals. 0

10 TPM_EDGE0 This bit, if set, selects the rising edge of XC_TCLK[0] for use as

the retim ing clock edge; or else selects falling edge. 1

9 TPG_E DGE 0 This bit, if set, selects the rising edge of TPG_CLK[0] for use as

the trans m it clo ck edge; or else selects falling edge. 1

8TPG_TPM_

ESF_0 This bit sel ec ts extended superframe mode for DS 1 Test s ignals. 0

7:6 TPG_TPM_

CODE0[1:0] Don’t Use Line Coding/decoding when 00.

Use HDB3 coding/decoding when 01.

Use B8ZS coding/decoding when 10.

Use AMI coding/decoding when 11.

This code is common to the generator and monitor sides.

5 TPM_FRAME 0 This bit is set to select a framed DS1 Test pattern in the monito r. 0

4 TPG_FINV0 If this bit is set, the frame bit in the 12th fr ame of each superframe

is inverted in the DS1 test pattern. 0

3 T PG_FRAME0 This bit is set to select a framed DS1 test pattern in the genera-

tor. 0

2:0 TPG_SEQ0[2:0] These Bits Select the Test Pattern to be Generated and

Transmitted by the TPG on the DS1 Test Output.

000 = PRBS15

001 = PRBS20

010 = QRSS

011 = PRBS23

100 = Alternating 01

101 = All ones

110 = Unused

111 = User defined

000

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

346 Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 508. T PG_CONFIG2, Register (R/W)

Address Bit Name Function Re set

Default

0x60032 15:13 TPM_SEQ2[2:0] These Bits Select th e Test Pattern to be Monitored by the

TPG on the E1 Test Input. 000

12 TPM_TPINV2 This Bit, if Set, Inverts the Received Data for E1 Test Signals. 0

11 TPG_TPINV2 This Bit, if Set, Inve rts the Transmitted D ata f or E1 Test Sig-

nals. 0

10 TPM_EDGE2 This Bit, if Set, Selects the Rising Edge of XC_TCLK[2] for

Use as the Retiming Clock Edge; or Else Selects Falling

Edge.

9TPG_EDGE2This Bit, if Set, S el ects the Rising Edge of TPG_CLK[2] for

Use as the Trans mit Clock Edge; or Else Selects Falling

Edge.

8TPG_TPM_

CRC4_EN2 This Bit, if Set, E nables CR C-4 Insertion if E1 Framing is

Selected.

This bit i s common to the generator and monitor sides.

7:6 TPG_TPM_

CODE2[1:0] Don’t uSe Line Coding/decoding when 0 0 .

Use HDB3 coding/decoding when 01.

Use B8ZS coding/decoding when 10.

Use AMI coding/decoding when 11.

This code is common to the generator and monitor sides.

5TPM_FRAME2Th is Bit is Set to Select a Framed E1 Test Pattern. 0

4TPG_FINV2If this Bit is Set, the Frame Alignment Sequence (Normally

0011011) is Transmitted with the Last Bit Inverted (0011010). 0

3TPG_FRAME2This Bit i s S et to Select a Fram ed E1 Test Pattern. 0

2:0 TPG_SEQ2[2:0] These Bits Select the Test Pattern to Be Generated and

Transmitted by the TPG on the E1 Test Output

(TPG_DATA[2]).

000 = PRBS15

001 = PRBS20

010 = QRSS

011 = PRBS23

100 = Alternating 01

101 = All ones

110 = Unused

111 = User defined

000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

347Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 509. T PG_CONFIG4, Register (R/W)

Address Bit Name Function Reset

Default

0x60034 15:13 TPM_SEQ4[2:0] These Bits Select th e Test Pattern to be Monitored by the

TPG on the DS2 Test Input. 000

12 TPM_TPINV4 This Bit, if Set, Inverts the Received Data for DS2 Test Sig-

nals. 0

11 TPG_TPINV4 This Bit, if Set, Inverts the Transmitted Data for DS2 Test Sig-

nals. 0

10 TPM_EDGE4 This Bit, if Set, Selects the Rising Edge of XC_TCLK[4] for

Use as the Retiming Clock Edge; or Else Selects Falling

Edge.

9TPG_EDGE4This Bit, if Set, Selects the Rising Edge of TPG_CL K[4] for

Use as the Trans mit Clock Edge; or Else Selects Falling

Edge.

2:0 TPG_SEQ4[2:0] These Bits Select the Test Pattern to be Generated and

Transmitted by the TPG on the DS2 Output (TPG_DATA[4]).

000 = PRBS15

001 = PRBS20

010 = QRSS

011 = PRBS23

100 = Alternating 01

101 = All ones

110 = Unused

111 = User defined

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

348 Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 510. T PG_CONFIG5, Register (R/W)

Table 511. TPG_USER, Register (R/W)

Table 512. T PM_USER, Register (R/W)

Table 513. TPG_BERCNT0, Register (RO)

Address Bit Name Function Re set

Default

0x60035 15:13 TPM_SEQ5[2:0] These Bits Select th e Test Pattern to be Monitored by the

TPG on the DS3 Test Input. 000

12 TPM_TPINV5 This Bit, if Set, Inve rts the Receive d Data for DS3 Test Sig-

nals. 0

11 TPG_TPINV5 This Bit, if Set, Inverts the Transmitted Data for DS3 Test Sig-

nals. 0

10 TPM_EDGE5 This Bit, if Set, Selects the Rising Edge of XC_TCLK[5] for

Use as the Retiming Clock Edge; or Else Selects Falling

Edge.

9TPG_EDGE5This Bit, if Set, S el ects the Rising Edge of TPG_CLK[5] for

Use as the Trans mit Clock Edge; or Else Selects Falling

Edge.

8:3 —Reserved. —

2:0 TPG_SEQ5[2:0] These Bits Select the Test Pattern to be Generated and

Transmitted by the TPG on the DS3 Output (TPG_DATA[5]).

000 = PRBS15

001 = PRBS20

010 = QRSS

011 = PRBS23

100 = Alternating 01

101 = All ones

110 = Unused

111 = User defined

Address Bit Name Function Reset

Default

0x60036 15:0 TPG_USER[15:0] User Programmed Test Pattern Generator Data. 0xDEAD

Address Bit Name Function Reset

Default

0x60037 15:0 TPM_USER[15:0] User Pr o grammed Test Pa ttern Monitor Data. 0xBEEF

Address Bit Name Function Re set

Default

0x60040 15:0 TPM_CNT0[15:0] This Fi el d Holds the Current Counter Va lue for DS1 Test Pa t-

tern Bit Errors as Detected by the TP M. 0x0000

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

349Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 514. TPG_BERCNT2, Register (RO)

Table 515. TPG_BERCNT4, Register (RO)

Table 516. TPG_BERCNT5, Register (RO)

Table 517. TPM_ESFDL_RX, Register (RO)

Table 5 18. TPM_E1SA_RX12, Regi ster (RO)

Table 519. TPM_E1S A_RX34, Register (RO)

Address Bit Name Function Reset

Default

0x60042 15:0 TPM_CNT2[15:0] This Fi el d Holds the Current Counter Value for E1 Test Pat-

tern Bit Errors as Detected by the TP M. 0x0000

Address Bit Name Function Reset

Default

0x60044 15:0 TPM_CNT4[15:0] This Fi el d Holds the Current Counter Value for DS2 Test Pat-

tern Bit Errors as Detected by the TP M. 0x0000

Address Bit Name Function Reset

Default

0x60045 15:0 TPM_CNT5[15:0] This Fi el d Holds the Current Counter Value for DS3 Test Pat-

tern Bit Errors as Detected by the TP M. 0x0000

Address Bit Name Function Reset

Default

0x6004C 15:0 TPM_

ESFDL[15:0] Data-Link Field Received from L ast DS1 Idle Frame. 0x0000

Address Bit Name Function Reset

Default

0x6004E 15:13 —Reserved . 0x0

12:8 TPM_E1SA2[4:0] Sa (spare bits [4:8]) Received from E1 Frame . 0x00

7:5 —Reser ved. 0x0

4:0 TPM_E1SA1[4:0] Sa (spare bits [4:8]) Recei ved from E1 Frame. 0x00

Address Bit Name Function Reset

Default

0x6004F 15:13 —Reserved. 0x0

12:8 TPM_E1SA4[4:0] Sa (spare bits [4:8]) Received from E1 Frame . 0x00

7:5 —Reserved. 0x0

4:0 TPM_E1SA3[4:0] Sa (spare bits [4:8]) Recei ved from E1 Frame. 0x00

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

350 A

ere S

stems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

15.2 Test-Pattern Generation/Detection Re gister Map

Tabl e 520. Test-Pattern Generation/Detection Register Map

Note: The reset default o f all res erved bits i s 0. Shading denotes reserved bits.

Addre ss Symbol Bit 1 5 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bi t 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Block-Level Status—RO

0x60000 TPG_ID TPG_

READY 0 0 0 0 TPG_VERSION[2:0] TPG_ID[7:0]

0x60001

—

0x60003

—

TPM Interrupt Sources (Deltas and Events)—RO

0x60004 TPG_ISRC_

OOFD TPM_

OOF2D TPM_

OOF0D

0x60005 TPG_ISRC_

OOSD TPM_

OOS5D TPM_

OOS4D TPM_

OOS2D TPM_

OOS0D

0x60006 TPG_ISRC_

BERE TPM_

BERE5 TPM_

BERE4 TPM_

BERE2 TPM_

BERE0

0x60007 TPG_ISRC_

FERE TPM_

FERE2 TPM_

FERE0

0x60008 TPG_ISRC_

BPVE TPM_

BPV2 TPM_

BPV0

0x60009 TPG_ISRC_

AISDE TPM_

AIS5D TPM_

AIS4D TPM_

AIS2D TPM_

AIS0D

0x6000A TPG_ISRC_

CRCE TPM_

CRCE2 TPM_

CRCE0

0x6000B

—

0x6000F

—

TPM Interrupt Masks—R/W and Edge Controls

0x60010 TPG_IMSK_

OOFD TPM_

OOF2DM TPM_

OOF0DM

0x60011 TPG_IMSK_

OOSD TPM_

OOS5DM TPM_

OOS4DM TPM_

OOS2DM TPM_

OOS0DM

0x60012 TPG_IMSK_

BERE TPM_

BERE5M TPM_

BERE4M TPM_

BERE2M TPM_

BERE0M

0x60013 TPG_IMSK_

FERE TPM_

FERE2M TPM_

FERE0M

0x60014 TPG_IMSK_

BPV TPM_

BPV2M TPM_

BPV0M

0x60015 TPG_IMSK_

AISD TPM_

AIS5DM TPM_

AIS4DM TPM_

AIS2DM TPM_

AIS0DM

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

351Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 520. Test-Pattern Gene rat ion/Detec tion Regis t e r Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x60016 TPG_IMSK_

CRCE TPM_

CRCE2M TPM_

CRCE0M

0x60017

—

0x6001F

—

TPM S tate and V alue Parameters—RO

0x60020 TPG_VAL_

OOF TPM_

OOF2 TPM_

OOF0

0x60021 TPG_VAL_

OOS TPM_

OOS5 TPM_

OOS4 TPM_

OOS2 TPM_

OOS0

0x60022 TPG_VAL_

AIS TPM_

AIS5 TPM_

AIS4 TPM_

AIS2 TPM_

AIS0

0x60023 TPG_VAL_

FER TPM_

FER2 TPM_

FER0

0x60024 TPG_VAL_

CRCE TPG_CR

CEINS2 TPG_CR

CEINS0

0x60025

—

0x60027

—

TPG Err o r Insert Enables —R/W

(Error injection triggered by SMPR_BER_INSRT (Table 65, SMPR_GTR, Global Trigger Register (RW) on page 66))

0x60028 TPG_BER_

INSRT TPG_

BER_EN TPG_

BERINS5 TPG_

BERINS4 TPG_

BERINS2 TPG_

BERINS0

TPG Er ror Insert Triggers (rising edge)—R/W

0x60029 TPG_FER_

INSRT TPG_

FERINS2 TPG_

FERINS0

0x6002A TPG_CRCE_

INSRT TPG_

CRC4EIN

TPG_

CRC6EIN

0x6002B —

TPG (Transmi t) ESF Dat a Li nk and E1 SA-B its Content s—R/W

0x6002C TPG_

ESFDL_TX TPG_ESFDL[15:0]

0x6002D —

0x6002E TPG_E1SA_

TX12 TPG_E1SA2[4:8] TPG_E1SA1[4:8]

0x6002F TPG_E1SA_

TX34 TPG_E1SA4[4:8] TPG_E1SA3[4:8]

TMX F2 8155 Super Ma pp er Pre liminary Data Sheet

155/51 Mbits/s SONET/ SDH x28/x21 D S1/ E1 May 2 001

352 A

ere S

stems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Tabl e 520. Test-Pattern Generation/Detection Register Map (continued)

Addre ss Symbol Bit 1 5 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bi t 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TPG/TPM Configuration—R/W

(Test Channels Only)

0x60030 TPG_

CONFIG0 TPM_SEQ0[2:0] TPM_

TPINV0 TPG_

TPINV0 TPM_

EDGE0 TPG_

TPM_

ESF_0

TPG_TPM_

CODE0[1:0] TPM_

FRAME0 TPG_

FINV0 TPG_

FRAME0 TPG_

SEQ0[2:0]

0x60031 —

0x60032 TPG_

CONFIG2 TPM_

SEQ2[2:0] TPM_

TPINV2 TPG_

TPINV2 TPM_

EDGE2 TPG_

TPM_

CRC4_

EN2

TPG_TPM_

CODE2[1:0] TPM_

FRAME2 TPG_

FINV2 TPG_

FRAME2 TPG_SEQ2[2:0]

0x60033 —

0x60034 TPG_

CONFIG4 TPM_SEQ4[2:0] TPM_

TPINV4 TPG_

TPINV4 TPM_

EDGE4 TPG_

EDGE4 TPG_SEQ4[2:0]

0x60035 TPG_

CONFIG5 TPM_SEQ5[2:0] TPM_

TPINV5 TPG_

TPINV5 TPM_

EDGE5 TPG_

EDGE5 TPG_SEQ5[2:0]

0x60036 TPG_USER TPG_USER[15:0]

0x60037 TPM_USER TPM_USER[15:0]

0x60038

—

0x6003F

—

TPM B it Error Counters—RO

(see also PMRST (Table 3, High-speed I/O Pin Descriptions on page 29), SMPR_SAT_ROLLOVER and SMPR_COR_COW (Table 67, SMPR_GCR, Global Control Register (RW) on page 68))

0x60040 TPG_

BERCNT0 TPM_CNT0[15:0]

0x60041 —

0x60042 TPG_

BERCNT2 TPM_CNT2[15:0]

0x60043 —

0x60044 TPG_

BERCNT4 TPM_CNT4[15:0]

0x60045 TPG_

BERCNT5 TPM_CNT5[15:0]

0x60046

—

0x6004B

—

nary

tTMXF28155

uper

apper

May 2001 155/51 Mbits/s SO NET /SDH x 28/x2 1 DS1/E1

353Agere Sy stem s Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 520. Test-Pattern Gene rat ion/Detec tion Regis t e r Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TP M Received DS1-ESF Dat a Link and E1 Sa-Bits Contents—RO

0x6004C TPM_

ESFDL_RX TPM_ESFDL0[15:0]

0x6004D —

0x6004E TPM_E1SA_

RX12 TPM_E1SA2[4:8] TPM_E1SA1[4:8]

0x6004F TPM_E1SA_

RX34 TPM_E1SA4[4:8] TPM_E1SA3[4:8]

0x60050

—

0x600FF

—

354 Agere Sy stem s Inc.
TMXF 28155 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
Functional Descriptions
16 Microprocessor Interface Functional Description
Ta ble of Conte nts
Contents Page
16 Microprocessor Interface Functional Description  ............................. .............. . ......................... . ..................... 354
16.1  In troduction ............................................................................................................................................. 355
16.2  Features  ................................................................................................................................................. 355
16.3  Microprocessor Interface ........................................................................................................................ 355
16.4  M PU Block  Di agram ............................................................................................................................... 356
16.5  Super Mapper Register Address M apping  .................................... .......................... ............................... 356
16.6  Performance Monitoring (PM) Counters Operation ............. ..... .............. . ......................... ..... ... .............. 356
16.7  Super Map per Global Interrupt Stat us  and Cont ro l  ....................... ... ......................... . ............................ 358
16.8  Gl obal Control ......................................................................................................................................... 358
Figures Page
Fig ure 18. Microprocessor  Interface..................................................................................................................... 356
Fig ure 19. PM Reset  Cou nter............................................................................................................................... 357
Figure 20. PM Reset  Signal Generation.................. ....... ..... ....... ................. ... ......................... ....... ...................... 357
Tables Page
Table 5 21.   S uper Mapper Register Address  Map ping  .............. . .................. . .................. . .................. ................. 356

355Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

16 Microprocessor Interface Functional Description (continued)

16.1 Introductio n

The Super Mapper micr opr ocessor int e r face consists of a 20-bit address and a 16-bit data bus. In addition, this

block contains global control and status regis te rs. These registe r s include the summar y of interrupt status o f m ajor

functional blocks and the control to enable them or power them down.

16.2 Features

■20-bit address/16-bit data bus m icroproces sor interfa ce.

■Synchronous (16 MHz to 66 MHz)/asynchronous microprocessor interface modes.

■Microproces sor data bus parity monitoring.

■Summar y of interrupt s f rom major functional blocks/maskable.

■Separate device interrupt outputs for automatic protection sw itch and the Super Mapper global interrupt.

■Global conf iguration of network performance m onitoring co unters operation.

■Global software resets.

■Global enabling and poweri ng down of major functional blocks.

■Miscellaneous global configuration and control.

16.3 Micro p roc e ss o r In t er f ac e

This device is equipped with a generic 20-bit address/16-bit dat a microprocessor interface that allows operation

with most commercially avai lable microprocesso rs. Device input pin M PMODE (pin AD17) is used to configure this

interface into one of tw o possible modes (syn c hronous or asynchronous). In synchronous m ode (MPMODE = 1),

the microprocessor interface can ope rate at speeds from 1 6 MHz up to 66 MHz. In asynchronous mode

(MPMODE = 0), a 16 MHz to 66 MHz clock is required on the MPCLK (pin AE17) pin for proper operation.

Two parity detectors are provided for th e microproc essor data bus, one for the higher-order byte an d one for the

low er-order byte . The parity sense is programmed as even or od d with register bit SMPR_PARITY_EVEN_ODD

(Table 67 on page68 ). The composite status of both pa rity det ecto rs is indicated in regi ster bit S MPR_PARITY_IS

(Table 63 on page64 ). The interrupt from this status indicator may b e masked with register bit SMPR_PARITY_IM

(Table 64 on page65 ). A bad p a rity event does not inhibit a dat a transfer. The microproc essor interface is fully

func tional without parity supplied by the host pr oc essor.

The inter rupt status from each of the major blocks, the au tomatic prot ection switch, and the mic roprocessor data

bus pari ty are summ ari zed in Table 63 on page 64 . Each interrupt is maskabl e with the complementary bit set in

the interrupt m as k regi ster, s ee Table 64 on page65 .

356 Agere Sy stem s Inc.

TMXF 28155 Super Mapper Preliminary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

16 Microprocessor Interface Functional Description (continued)

16.4 MPU Block Diagram

5-9039(F)r.2

Figure 18. Microprocessor Interfa ce

16.5 Super Mapp er R eg ister A ddress M a ppi ng

Each of the Super Mapper’s major fun ctional b locks is selected with an address mapping of the highest order nib-

ble, device pins ADDR[19:16], and allocated a 16-bit address ra nge, pins ADDR[15:0], as defined in Table 521.

Table 521. Super Mapper Register Address Mapping

16.6 Perfo rman ce Mon itoring (PM) Counters Operation

PM counters are error counters or other statist ics counters. In general, t wo i nt erna l registers are ne eded to imple-

ment a PM count er: a running count register (1), m aintained by the core logi c, which i s incremented by 1, every

time an error (or statistics event) happens. At a defined interval, one second for example, the content of the running

counter is transferred to a holding register (2), while the running count register is reset t o 0 and star t s to count

anew. The cou nt holding register holds the data that microprocessor actually reads.

ADDR[19:16] Block ID Block Name ADDR

0000 0 TOP [15:0]

0001 1 M13 [15:0]

0010 2 VTMPR [15:0]

0011 3 SPEMPR [15:0]

0100 4 TMUX [15:0]

0101 5 XC [15:0]

0110 6 TPG [15:0]

0111 7 DJA [15:0]

1000 8 FRAMER [15:0]

MPCLK

ADDR[19:0]

CSN

ADSN

DSN

RWN

DATA[15:0]

DTN

MPMODE

INTN

APS_INTN

INTERNAL

ADDRESS

INTERNAL

DATA

INTERNAL

CONTROL

PAR[1:0]

357Agere Systems Inc.

Prelim inary Data Sheet TMXF28155 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

16 Microprocessor Interface Functional Description (continued)

5-9040(F)r.3

Figure 19. PM Reset Counter

The PM counter control signal c ontrols the transf er and reset of all performance monitoring registers (collec ting

events/statistics). The s ource of this signal is configurable and can come from e xternal pin (PMRST pin T25), an

inter nal timer, or be cont rolled by software, depending on the SMPR_PMMODE[1:0] bits (Table 67, bits 9:8),

describ ed as follows:

SMPR_PMMODE[1:0] = 00, 10: PM counter control is sourced from external pin PMRST .

SMPR_PMMODE[1:0] = 01: PM counter control is sourc ed from internal 1 second timer. Writing a logic one to the

SMPR _ PMR ESET bit (Table 65, bit 8 ) will reset the timer s o tha t a transiti on o cc urs on th e internal PM counter

control signal within 10 MPCLK clock cycles. The ti mer is based on the period of the MPCLK and the programmed

value of the re gisters in Table 72 and Table 73. Once initially reset and synchronized, the PM counter reset interval

is determined by the combined delay of the programme d registers. The device pin, PMRST, is enab led as an out-

put.

SMPR _P M MO D E[1:0] = 11: The PM counter con trol signa l is sof tware cont ro ll ed. Writ ing a logic one to the

SMPR _PMR ESET bi t will cause a P M reset within 10 MPCL K cycle times after writing. This pulse will be

100 cycles high and 100 cycles low at the MPCLK frequency. D uri ng this 200 cycle time, writing to PM bit w ill have

no effect. The device pi n, PMRST, is enabled as an output.

5-9931(F)

Figure 20. P M Reset Sig nal Generation

PM COUNT EVENT RUNNING HOLDING

MPU READABLE MPUCLK

MPU RE A D HOLDING

(ONE PER BLO CK)

COUNTER COUNTER

PM COUNT EVENT CLOCK

RESET

PM COUNTER CONTROL

PM CO UNTER

BUFFERED

ENABLE

MPUCLK DELAY

1/ 2 S E C O N D

COUNTERS

SMPR_PMRESET_HIGH_COUNT

SMPR_PMRESET_LOW_COUNT

SMPR_PMMODE

(REG ISTER SMPR_ GC R bit s [9 :8 ])

SMPR_PMRESET

(REGISTER SMPR_GTR bit 8)

FREE RUNNING

(SMPR_PMMODE[1:0] = 01)

SOFTWARE CONTROLLED

(SMPR_PMMODE[1:0] = 11)

EXTERNAL

(SMPR_PMMODE[1:0] = 00, 10)

MPUCLK

OUTPUT ENABLED

SMPR_PMMODE[1:0] = 01, 11

OUTPUT DISABLED

SMPR_PMMODE[1:0] = 00, 10

PMRST (TO BLOCKS)

PMRSTO

PMRSTI

MPU BLO CK

358 Agere Sy stem s Inc.
TMXF 28155 Super Mapper Preliminary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
16 Microprocessor Interface Functional Description (continued)
16.7  Su pe r Mapp er Globa l Interrupt Status and Control
The Super Mapper provides two hardware inter rupt output pins: one global (INTN pin AB24) and one for the 
SONET automatic protection switc h ing ( APS_INTN pin AC25). B oth interrupt pins are active-low and are open-
drain outp uts to allow a wired OR wit h complementary devices.
Interrupt status for major functional bloc ks are summariz ed in Table 63 and maskable in Table 64.
16.8   Glo b al  Con trol
Several registers in this block provide global control of Super  Mapper features. The register descriptions are self- 
explanator y, but  so me highlights are listed as follows:
■Global enabling and poweri ng down of major functional blocks is shown in Table 71 SMP R_CP CR, Clock and 
Power Control Regist er (RW) on page 71.
■Software resets for major functional blocks are s hown in Table 66 SMPR_MSRR, Block Software  Reset Register 
(RW) on page66 .
■Global reset of the Super Mapper is controlled with SMPR_SWRS, bit 8 in Table 65 SMPR_GTR, Global Trigger 
Register (RW) on page 66.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
359Agere Systems Inc.  
TMUX Functional Description
Ta ble of Conte nts
Contents Page
TMUX Func tional Description . ..... ... ....................... ... .......................................... ... ......................................... 359
1  TMUX Introduction ............................................................................ ............ .......................................... 361
2  TMUX Features  ...................................................................................................................................... 361
3  TMUX Receive Path Overview ............................................................................................................... 362
3.1 Receive Line Framer a nd Trans port O v erhead Term ination  . .......... ... .............................. ... ........ 362
3.2 Receive T r ans port   Overhead Mo nitor and RTOAC Drop  .... ............................ . ........................... 362
3.3 Receive MSP 1 + 1 Payload Switch ............................................................................................. 363
3.4 R eceive Pointer Interpreter .......................................................................................................... 363
3.5 Receive High-Order Path Overhead Termination and  RPOAC Drop  .......................................... 363
3.6 R eceive Byte Interleave Demultiplexer ........................................................................................ 363
3.7 R eceive T elecom Bus .................................................................................................................. 363
4   TMUX Transmi t Path Overview .............................................................................................................. 364
4 .1  Transmi t Tele co m Bus ................ ....................................................................... .......................... 364
5  Receive Direction (Receive Path from Sonet Global/SDH) ........................ ............................................ 368
5.1 I nput Clock and L oss-of-Signal Monitoring ............................ .......... ... ......................... ....... ..... .... 369
5.2 High-Speed Loopba ck Sele ct Logic ................................ ....... ............ ....... .......................... ......... 369
5.3 Frame Alignment—STS-3/STM-1 (AU-4) Framing or  STS-1 Framing ......................................... 369
5.4 B1 BIP-8 Check  ........................................................................................................................... 369
5.5 J0 Monitor .................................................................................................................................... 370
5.6 D escrambler ................................................................................................................................. 370
5.7 F1 Monitor .................................................................................................................................... 371
5.8 B2 BIP-8 Check  ........................................................................................................................... 371
5.9 Automatic Protection Switch (APS) Monitor ................................................................................. 371
5.10 K2 Monitor,   AIS-L and RDI-L Detect ...................... . ....................... .......................... .................. 371
5.11 M1 REI-L Detect  ........................................................................................................................ 372
5.12 Sync Status Monitor ................................................................................................................... 372
5.13 Receive Transport   Overhead Access C hannel (RTOAC) ......... . ............................................ . ... 372
5.14 MSP 1 + 1 Payload Switch ......................................................................................................... 374
5.15 Pointer Interpreter ...................................................................................................................... 374
5.16 Path Monitoring Functions  ......................................................................................................... 377
6  Transmit  Di rection (Transmit Path to SONET/SDH Line) ....................................................................... 386
6.1 Transmit Side Telecom Bus Interface .......................................................................................... 386
6.2 Transmit Path and Transport Overhead Insertion Diagram  ......................................................... 386
6.3 POAC Insert ................................................................................................................................. 388
6.4 A IS Path Generation ............................. ....... ............ ....... ....... ...................................... ................ 389
6.5 J1 Insert Control ........................................................................................................................... 389
6.6 B3 BIP-8 Calculation  and Insert ................................................................................................... 389
6.7 C2 Signal Label Byte Insert  ............................................................... ....... ................................... 389
6.8 Path RDI (RDI-P) Insert  ............................................................................................................... 390
6.9 R EI-P: G1(7:4) Insert ................................................................................................................... 390
6.10 F2 Byte Insert ............................................................................................................................. 391
6.11 H4 Insert Control ........................................................................................................................ 391
6.12 F3 Byte Insert ............................................................................................................................. 391
6.13 K3 Byte Insert  ............................................................................................................................ 391
6.14 N1 Byte Insert ............................................................................................................................ 391
6.15 MSP 1 + 1 Payload Switch ......................................................................................................... 391
6.16 Transmit T ransport Overhead Access Channel (TTOAC)  ............................. ............................ 391
6.17 Sync Status Byte (S1) Insert ...................................................................................................... 393
6.18 REI-L: M1 Insert ......................................................................................................................... 393

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
360 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
Table of Conten ts (continued)
Contents Page
17 .6.19 APS Val ue and K2  Insert Control Parameters ........................................................................... 393
17.6.20 Criteria for Insert  Line RDI ......................................................................................................... 394
17.6.21 Line A IS Generation ................................................................................................................... 394
17.6.22 B2 BIP-8 Calculation and Insert ................................................................................................. 394
17.6.23 F1 Byte Insert ............................................................................................................................. 394
17.6.24 B1  Generate and  Error Insert ............... ........................ ....... ........................ ... ............................ 395
17.6.25 Scrambler ................................................................................................................................... 395
17.6 .2 6  J 0 Inse rt Contro l ....................... ....................................................................... ........................... 395
17.6.27 Z0-2, Z0-3 Insert Control  ............................................................................................................ 395
17.6.28 A2 Error Insert ............................................................................................................................ 395
Figures Page
Fi gure  21.  T MUX RTOAC Ti mi n g Diagra m.......................................................................................................... 362
Fi gure  22.  T MUX TTOA C and RTOAC Timing Di a gr am.... .................................................................................. 365
Fig ure 23. High-Le vel TMUX Interconnect........................................................................................................... 365
Figure 24. Detailed Block Diagram of the TMUX.................................................................................................. 366
Figure 25. Receive Direction Functional Block Diagram...................................................................................... 367
Fig ure 26. Pointer Interpretation State Dia gram................................................................................................... 374
Figure 27. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals................................................ 385
Figure 2 8. Transmit Low-Speed Bu s Interface Signals for STS-3/STM-1 Signals .................. .............. . .............. 386
Fi gure  29. Transmi t Direction POH and TOH In se r ti o n  Di ag r am . ........................................................................ 387
Tables Page
Table 5 22. Receive  TOAC Modes ....................................................................................................................... 373
Table 523. Transport Overhead By te Acces s—Receiv e Dire ction ......................................................................373
Table 524. STS Signal Label Defect Conditions ............................. ..... ..... ......... ..... .............. ..... ......................... 379
Table 525. STS - 1 P-REI  Interpretation ................................................................................................................ 380
Table 5 26.   Signal Degrade (SD) Parameters ................ . ................ ................... ................... ............................... 382
Table 527. Signal Fail  Parameters ...................................................................................................................... 383
Table 528. Signal Fail or Signal Degrade Re commended Programming Values ................... . ......................... . .. 3 84
Table 529. P ath Overhead Byte Access ... ....... ....... ....... ................... ............ ....... ................... ....... ...................... 384
Table 530. P ath Overhead Byte Access—Transmit Direction ............................................................................. 388
Table 5 31. TPOAC Control Bits  ........................................................................................................................... 389
Table 532.  RDI-P Defects fo r Enhanced  RDI-P M ode  ...................................... .............. .............. ...................... 390
Table 533.  Transmit TOAC Modes  ......................... . ....................... ............................ . .................. ...................... 392
Table 534.  T ra nsmit Transport Overhead Byte Full Access Mode  .... ......................... ......................................... 392
Table 535.   TTOAC Control Bits in Full Access Mode ....... .............. .............. . ........... .............. . ........... ................. 393

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

361Agere Systems Inc.

17 TMUX Functional Description (continued)

17.1 TMUX I ntroductio n

The TMUX multiplexer block implements SDH/ SONE T-com pli ant, byte-i nter leave multiplexing/dem ultiplexing, over-

head insertion and termination, multiplex section protectio n (MS P) 1 + 1 switc h capability, and s erializer/des eria l-

izer for 155.52 Mbits/s and 51.84 Mbits/s t raffic.

As shown i n Figure 23 on page 365, the TMUX provides three modes of operation: STS-3 mode, STM-1 mode, and

STS- 1 mode. In STS-3 mode, the TMUX im plements the functions nec es sar y to mult iplex and demultiplex up to

three STS-1 signals to/from a SONET STS-3 signal. In STM-1 (VC-4) mode, the TMUX provides the functionality to

multiplex and demultiplex up to three TUG-3 signals to/ f rom an STM-1(VC-4) sign al. The dev i ce can also build/

extract up to three AU-3 signals to/from an STM-1(VC-3) stream. In STS-1 mode, the TMUX imple ments the func-

tions necessary to interface a single S TS-1 to/from an external serial link.

On the high-speed side or line side, the bloc k can be configured for either a 155.52 Mbits/s (STS-3/STM-1) or

51.84 Mbits/s (STS-1) serial data interface. On the low-speed side or tributary side, t he TMUX provides a byte-wide

bus that can communicate with up to three STS-1/TUG-3/AU-3 devices at a 19.44 MHz rate. If single STS-1 mode

is employed, the bus rate will be 6.48 MHz. Th e TM UX th erefore provides complete multiplexing/demultiplexing

to/from an STS-3/STM-1 signal for up to 8 4 DS1, 84 JT1, or 63 E1 signals. I n S TS-1 mode, the TMUX provides

multiplexing/ demultiplexing for up to 28 DS1, 28 JT1, or 21 E 1 streams. In STS-3/S T M-1 mode, the TMUX from

only one device is required . The TMUX in other c onnect ed devices may be powered d own t o reduce consu med

power. T his architecture allo ws flexible and modular growth in equipment capacity for both 51.84 Mbits/s and

155.52 Mbits/s links.

17.2 TMUX Featur es

■Multiplexes three STS- 1 signals into a SONET STS-3 signal.

■Multiplexes three VC-3 si gnals into an SDH STM-1 (AU-4) sig nal via a TUG-3 c ons truction.

■Multiplexes three VC-3 signals into an SDH STM-1 (AU-3) sig nal.

■Demultiple xes three STS-1 signals f rom a SONET STS-3 signal.

■Demulti plexes three VC-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstructi on.

■Demultiple xes three VC-3 signals from an SDH STM- 1 (AU-3) signal.

■Provides STS-1-only m ode for receive and transmit directions .

■Provides complete functionality for SDH MSP 1 + 1 pro tection switching.

■Detects STS-3/ STM-1 loss-of-signal (LOS) conditions.

■Det ec ts STS- 3/ S TM-1 o ut -o f-fram e and loss-of-frame (OOF/LOF) conditions.

■Provides an 8-bi t parallel bus interface that can accomm odate up to three STS-1/AU-3s.

■Provides S TS - 3/ STM-1/STS-1 select able scrambler/descrambler func t ions and B1/B2/B3 generation/detection.

■Provides S TS-3/ S TM -1/STS-1 poi nter interpretat ion . Detec ts AIS-P an d LOP.

■Complies wi th GR-253-CORE , T 1.10 5, G.707, G.7 83, G. 806, G.821, and ETSI 417-1-1.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

362 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

17.3 TMUX Re ce iv e Path O ve r v iew

A detailed drawing of t he TMUX receive pa th is provided in the bottom half of Figure 24 on page366 . For the

receive path, the T MUX imp lements tw o serial inp uts for both the work and protect streams of an MSP 1 + 1 net-

work interface. Synchronous data (SDH/SONET) framers are implemented to frame on the incoming receive data

streams. One or both may be employed depending on system architecture. The incoming traffic is converted from

serial to byte- wide parallel. The tr anspo rt overhead bytes of the incoming tra ffic are moni tored and dropped vi a the

receive path TOAC drop interface. A multiplexer i mplements the receive M SP 1 + 1 payload switch and only one of

the incoming stream s is passed to the downstream processing blocks. The pointer interpreter passes pointer infor-

ma tion to the 1:3 demultiplexer logic, and bus control circuitry provides functions necessary to manage traffi c o n

the telecom bus drop interface which drops traffic from up to three S TS-1/TU G- 3 paths on the TMUX receive path.

T he path overhead bytes are monitored by t he path overhead monitor and are dropped v ia the re ceive path POAC

drop interface.

17.3.1 Receive Line Framer and Transport Overhead Termination

Input receive data is received at the TMUX synchronous dat a framer from the high-speed line interface block. The

framer performs a multitude of fu nctio ns includin g frame alignment (S TS-3/ STM-1 o r STS-1), B1 BIP-8 check,

J0 byte monitoring, d escrambling, F1 byte monitoring, B 2 BI P -8 check, autom atic protection switch (APS) and K2

by te monitoring, AI S-L and RDI-L detection, M1 byte REI-L detection, S1 byte sync status monitoring, and receive

transport overhead access channel (RTOAC) drop. T he states of the framer as well as all state changes are

reported, and, if not mas ked, c ause an interrupt. The B1 and B2 byte p a rity check supports bit and block modes.

The TMUX implements internal performance monitor counters. These counters can count up to one second worth

of B IP errors. The counters operate in either a saturation mode, such that the maximum value is retained once

reached, o r in a rollover mode. These counters s hould be optimally read (and cleared) at least once per second.

The J0 monitor supports non-fr amed, SONET-fr amed, and SDH-framed 16-byte sequences as well as single

J0 by te monit orin g mode. APS monitoring is perf orme d on by tes K 1[7:0] and K 2 [7:3]. The value of each is stored

and changes are repor ted. Bits [2:0] of the K2 byte are monitored independently. Line AIS (AIS-L/MS-AIS ) and

RDI-L/MS-RDI are monitored separately and changes are reported. This AIS-L/MS-AIS and RDI-L/MS-RDI infor-

ma tio n is also sent to the prot ec tion device for add/drop m ultiplex (ADM) appl ications . The M1 byte monitor oper-

ates either in bit or block mode and allows access to the REI-L/MS-REI errored bit count. The S1 byte can be

mo nitored in two modes: as an entire 8-bi t w or d or as one 4 -bit nibble (bits 7 t o 4). Contin u o us N-times detection

counters are i mplemented for these monitoring functions. All auto mat ic receive monitoring functions ca n be config-

ured to prov ide an interrupt to the c ontrol system, or the device can be operated in a polled mode.

17.3.2 Receive Transport Overhead Monitor and RTOAC Drop

The receive RTOAC provides access to all of the line section overhead byt e s . Even or odd parity is calculated over

all b ytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and an 8 kHz sync pul se. In an alternate

operating mode, the data communication channel byte s D1—D3 or D4—D12 may transmit a se rial 192 kbi ts/s or a

576 kbits/s data stream onto the RTOAC drop channel.

0783(F)

Figure 21. TM UX RTOAC Timing Diagram

rtoac clk

rtoac sync

r toa c data

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

363Agere Systems Inc.

17 TMUX Functional Description (continued)

17.3.3 Receive MSP 1 + 1 Payload Switch

Output from both receive framer b locks pr ov id e s the input to the MSP 1 + 1 payload switch.This portion of the

TMUX implements a payload 1 + 1 prote ction switch. In the receive dire ct ion, this occur s pri or to pointer interpreta-

tion. If the protection s witch is activat ed, then the data is selected from the receive protection interface rather than

from the hig h-sp eed input path. Only the selec ted input traf fic is provided down stream to the pointer i nterpr eter.

The interfac e consists of a 155.52 MHz or 51.84 MHz clock , data, and sync pulse.

17.3.4 Receive Pointer Interpreter

The pointer interpreter is implemented via a state machine which implements the pointer interpretation algorithm

described in ETS 300 417-1-1: January 1996 -Annex B. The p ointer interpreter evaluates the current pointer state

for t he normal state, path AIS state, or LOP conditions, as well as pointer increments and decrements. The current

poi nter st ate and any changes in pointer condition are reported to the control system. The number of consecutive

frames for invalid pointer and invalid concatenati on indication is fixed at nine.

17.3.5 Receive High-Or der P ath Overhead Termination and RPOAC Drop

Path overhead (POH) ter mina tion is p e rformed in the rece ive path on either al l three STS -1s or on the VC - 4 POH

only. The recei ve POH circuitry includes: J1 byte moni toring, B3 byte BIP-8 checking, C2 byt e s ignal label m oni t o r-

ing, REI-P and RDI-P detection, H4 byte multiframe monitoring; F2, F3, and K3 byte APS monitoring, N1 byte tan-

dem connection monit oring (TCM), signal degrade BER and signal f ai l BER detection; receive path ov erhead

access channel (RPOAC) drop, and AIS-P/HO-A I S insert ion and automatic AIS genera tion (with individual inhibit) .

The J1 monitor provides five modes of operation for a programmable length (1 byte to 6 4 bytes) of the t race identi-

fier. These five modes are comprised of: cyclic checking against the last received sequence, compare against a

programmed sequence, SONET framing mode, SDH framing mode, and consecutive consistent occurrenc es of a

new pattern. B3 is monitored eit her in bit or bloc k mode. Provisionabl e N-times detection counters are implemented

for the C2, F2, F3, N1, an d K3 bytes. The K3 APS byte and N1 TCM byte can be monitored as an entire 8-bit word

or two 4-bit nibbles.

T he r e ce ive RPO AC p rovid e s ac c e ss to a ll th e p at h overhead bytes. Even or odd parity is calculated over all bytes.

The RPOAC has a data rate of 9 bytes per 8 k H z frame and consis t s of cloc k, data, and an 8 kHz sync pulse.

17.3.6 Receive Byte Interleave Demultiplexer

The byte interleav e demultiple xer accepts serial traf fic and demultiplexes that information into one (STS-1 mode) or

three (STS-3/STM- 1 mode) t raffic streams for input via the telecom bus to th e VT/VC ma pper. The demultiplexer

takes the bytes in the order t h ey are pres e nted and places that traffic onto the telecom bus.

17.3.7 Receive Telecom Bus

The TMUX can communicate with up to three SPE mappers via the telecom bus interface. In typical applications,

si nce one SPE mapper is in cluded in the Super Mapper device , two ext ernal SPE m appers re side on the telecom

bus. The bus operates at 19.44 MH z for STS- 3/ STM-1 m odes and at 6.48 MHz for STS-1 mode . In the receive

di rectio n, t he Super M apper o utputs one para lle l cloc k at 19.44 MHz, t hr ee sync si gnals ( SPE, J0J1V1, and V1), an

8-bit data bus , and an odd/even parit y bit. The data bus carries either three STS-1/TUG-3 signals, each in their own

time slot, or it carries one STS-1 signal. A 51.84 MHz low-speed clock and sync signal is also output from this cir-

cuit.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

364 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

17.4 TMUX Tr ans mit Path Over v iew

The TMUX transmit path is depicted in the t op half of Fi gur e 24 on page366 . The transmit path of the TMUX imple-

ments the inverse function to the receive path. Transmit input traffic at the telecom bus interface from up to three

STS-1/TU G-3 path s is managed v i a the transmit path bus control circuitry. Transmit traffic, al arms, or unequipped

indication information is inserted as needed depending on the status and provisioning of the device. The 3:1 multi-

ple xer pro vides byte interleav e multiple xing of the incoming tr affic and insertion of the path overhead bytes. A serial

path provides input for the transmit protection traffic and the framer and serial-to-parallel converter fo rmats this t raf-

fic for input to the transmit MSP 1 + 1 payload switch. The select ed output from the transmit MSP 1 + 1 s witch is

input to the trans port overhead insert block and the parallel to se rial converter sends a seria l stream to the device

output. The TMUX transmit path provides path overhead byte insertion and transport overhead byte insertion via

the respective POA C insert and TOA C insert interfaces.

Local clock and frame generation control circuitry is imp lem ented in the TM UX for controlling the STS-1, S TS-3,

and STM-1 termination and generation functions. Internal loopbacks in the TMUX provid e near-end line l oopback

and far-end line loopback capability.

17.4.1 Transmit Telecom Bus

The transmit side of Super Mapper drives a clock and thre e sync signals (SPE, J0J1V1, and V1) onto the telecom

bus. These signals control when the internal SPE mapper or one of the mate devices talks on the data bus.

Because it is on the receive side, the transmit telecom bus operates at 19.44 MHz for STS-3/STM-1 modes and at

6.48 MH z for STS-1 mode. The TMUX communicates with up to three VT/VC mappers, via an 8-bit data word and

an odd/ev en parity bit from the telecom bus . The data consists of the STS-1/TUG-3 from up to three mappers; each

in its own time slot, or it c arries one single STS- 1 signal. A 51.84 MHz low-speed clock and sync are also output .

Transmit High-Order P ath Overhead Generation and TPO A C Insert. In the transmit direction, J1 path trace byte

insertion, B3 byte calculation and insertion, C2 signal l abel byte insertion, REI-P and RDI-P insertion; F2 byte

insertion, H4 multiframe byte insertion, F3 path user byte insertion, K 3 byte insertion, N1 b yte insertion, and AIS-P

insertion via POAC or software control is supported. The transmit TPOAC allows insertion of all overhead bytes

other t han the B3 byt e, which is automatically calculated. Even or odd parity is checked over all bytes. Bytes which

are not enabled for insertion are set to an all-ones or all-zeros stuff value. Transport path o verhead bytes are added

to the payload stream during multiplexing in the byte interleave multiplexer.

Transmit Byte Interleave Mult iplexer. In STS- 3/S TM-1 m ode, th e transmit byte interleave multiplexer block multi-

plexes up to three STS-1/TU G3 s ignals to form a SONET/S DH STS-3/STM-1 struc tured signal. The S TS-3/STM-1

multi plexer func tion p ro ce sses the input bytes in the order in which they are presented on the transmit telecom bus

and multipl exes these bytes into a single high-speed stream. Gro oming of the VTs/VCs is perf ormed in the SPE

mapper of each of the three devices. High-order path ov erhead bytes are interlea ved with the data traffic during the

byt e interleave multiplexing.

Transmit Payload Framer and MSP 1 + 1 Payload Switch. In the transmit direct ion, the MSP 1 + 1 switch fu n c -

tion inc orporates dual MSP 1 + 1 p ayload switch structures. In operation, the traffic from t he transmit byte inter-

leave multiplexer are presented to both M SP 1 + 1 payload switches. The output of the signal from the 3:1 multip lex

is broadcast to both switch paths, and the output of the receive payload framers is also input respectively to one of

the two swi tch paths. For normal op eration, one of the two outputs from th e two MSP 1 + 1 blocks is selected. The

path from the receive f ra mer to t he MSP switc h structures provides a means t o perform far-end loopback.

Transmit Tran spo rt O verhead Genera tion a nd TTOAC Insert. Th e t ransmit transport overhead generator per-

forms T TOAC byte insertio n, sync sta tus byte (S1) inser tion, M0/M1—REI-L insertion, K1 and K2 byte insertion,

AIS-L i ns ert ion, B2 byte calculation and insertion , F1 byte insertio n, B1 byte generation and error insertion, scram-

bli ng, J0 byte insertion control, and A2 byte error insertion. All insert control functions that are inhibited will insert

optionally either an all-zeros or an all-one s word.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

365Agere Systems Inc.

17 TMUX Functional Description (continued)

The transmit TTOAC allows the users to insert the following overhead b ytes: E1, F1, D1—D3, D4—D12, S1, and

E2. Even or odd parity is checked over all b ytes. Bytes which are not enabled for i nser tion are set to an all-ones or

al l-zeros stuff va lu e.

The data communication channels D1—D3 or D4—D12 may als o be received via the TTOAC interface. In this

mo de, the TTOAC channel will comprise a serial 192 kbits/s or a 576 kbits/s data stream.

The insertion (overwri te by TOAC) of programmed S 1, F1, J0, Z0-2, and Z0 -3 bytes can be enabled via registers.

Automatic in se rtion of M0 /M1 may also be inhibited via registers. A prot ection switch selects the REI-L value for

insertion to be taken from the protection board rather t han from the receive side. The entire APS v alue or K2[2:0]

can b e inserted via wr itable re gisters. Automatic RDI insertion is supporte d with indivi dual inhib it for each cont ri bu-

tor. A prote ction switch selects the RDI-L value for insertion to be t aken from the protection board rather than fr om

the receive side. B1 and B2 BIP-8 valu es a re calculated and inser ted. Both valu e s can be optio nally inverted.

0784(F)

Figure 22. TMUX TTOAC an d RTOAC Timing Dia gram

5-9004(F)

Figure 23. Hi gh-Level TM UX Inte r connect

ttoac clk

ttoac sync

t toac data

TMUX

SPE

TELECOM

BUS

VT/TU

MAPPER

M13

TUG-2DS3

MAPPER

STS-1/TUG-3

(TIME S LO T # 1)

STS-1/TUG-3

(TIME S L O T # 2 )

STS-1/TUG-3

(TIME SLOT #3)

STS-3/STM-1

OR STS-1

DEVICE #1

DEVICE #2

DEVICE #3

HIGH-SPEED

SONET/SDH INTERFACE

VT MPR RDI_P, REI_P

VT MPR RDI_L, RE I_L

TMUX RDI_L, REI_L

TMUX RDI_P, REI_P

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

366 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

5-9005(F)r.1

Figur e 24. Detailed Block Diagram of t he TM UX

PATH RDI

POAC

DROP

1:3

DEMUX

LOGIC

MSP 1+1

STS#1

STS#2

STS#3

TOAC

INSERT

TRANSMIT DIRECTION

RECEIVE DIRE CTION

STS#3

TLSCLK

PAIS, UEQ

INSERT

BUS

CONTROL

TLSPAR

TLSDATA[7:0]

RLSCLK

BUS

CONTROL

RLSPAR

RLSDATA[7:0]

TTOACCLKO,

POINTER

INTERPRETER

TTOACSYNCO,

TTOACDATI

TLSV1

(19.44 MHz)

(19.44 MHz )

RTPOACSYNC,

RTPOACDATA

THSD

RLSJ0J1V1

RLSV1

RLSSPE

TLSJ0J1V1

TLSSPE

TLSSYNC52

TLSCLK52

RLSSYNC52

RLSCLK52

TOH

MONITOR

TOAC

DROP

RTOACCLK,

RTOACSYNC,

RTOACDATA

POAC

INSERT

TPOACCLK,

TPOACSYNC,

TPOACDATA

POH

MONITOR

STM-1

TOH

STS#2

P A IS , U E Q

INSERT

STS#1

PAIS, UEQ

INSERT

FRAMER

PAYLOAD

SWITCH 1

AND S/P

3:1

AND

POH

INSERT

MUX

LOGIC

PATH REI

INSERT

MSP 1+1

PAYLOAD

SWITCH 2

LINE RDI

LINE REI

P/S

VTMPR RDI_L, REI_L

VTMPR RDI_P,

AUTO_AISO[1—3] RHSC

RPSD155

FRAMER,

S/P, AND

RPSC155

TPSC155

RHSD

B2 ERR

INSERT,

MSP 1+1

PAYLOAD

SWITC H 3

TPSD155

P/S

L-REI INS

B2 MON,

LOC, OOF,

LOF, B2E

LOC, OOF,

LOF, B2E

L-REI MON

LOCAL CLOCK

GENERATION

THSC THSSYNC

AND FRAME

RPSC155R PSSY NC155 (FRO M RECEIVE SIDE)

TPSMUXSEL2

RPSSYNC155

TIM ING SIG N ALS TO TX SIDE

RTPOACCLK,

REI_P

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

367Agere Systems Inc.

17 TMUX Functional Description (continued)

The following block diagram describes t he receive side transport overhead functions. Data is received from the

high-speed i nterface at 155 Mb its/s (51.84 Mbits/s for STS-1 mode) a nd the output is d riven on to the low-speed

telecom bus in a parallel format. The TOH receive side f unctional blocks are shown in Figure 25.

5-9006(F)r.2

Figure 25. Receive Directio n F unctional Block Diagram

INSERT

MONITOR

BIP N K3

CHECK

RDI-P G1

REI-L

DETECT

APS

MONITOR

B3 K3

DETECT

G1 G1N1C2

POAC

DROP

RECEIVE DATA

REI

COUNTER

AIS-P

BER

ALGORITHM

FRAME DESCR-

AMBLER

BIP-8

MONITOR

LOS

CHECK

MONITOR

BIP N K1/K2

CHECK

AIS-L

RDI-L M1

REI-L SYNC

MONITOR

DETECT

APS

MONITOR

B2 K1

DETECT

K2 M1 S1

STATUS

DETECTOR

J0 F1

TOAC

DROP

LOF

MONITOR

OOF

ALIGN

MONITOR

INPUT

REI

COUNTER

BER

ALGORITHM

MONITOR

H1, H2, H3

INTERPRETER

POINTER

TELECO M BU S

MONITOR

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

368 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

17.5 Receive Direction (Receive Path from Sonet Global/SDH)

All functions supported by the TMUX in the receive direction are summarized here:

■Input clock m onitori ng and loss-of-signal mon ito rin g

■High-speed loopback

■Frame al ignm ent

■Receive side frame sync output

■B1 BIP-8 check

■J0 monitor

■Descrambler

■F1 monitor

■B2 BIP-8 check

■APS (au to matic pro te ction swit ch ) mon itor

■K2 monitor, AIS- L and RDI-L detect

■M1 REI-L detect

■Sync s tat us monitor

■Receiv e transport ov erhead access channel (RTOAC)

■MS P 1 + 1 payload switc h

■Pointer inter preter

■J1 monitor

■B3 BIP-8 check

■Signal label C2 b yte monitor

■RDI-P detect

■REI-P detect

■Path user byte F2 monitor

■H4 mu ltiframe ind icator

■Path user byte F3 monitor

■K3 byte monitor

■N1 tandem connection byte monitor

■Signal degrade BER algorithm

■Signal fail BER algorithm

■Path overhead access c hannel (POAC) drop

■AIS-P insertion and AUTO_AISO[1—3] generation

■Receive side telecom bu s interface

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
369Agere Systems Inc.  
17 TMUX Functional Description (continued)
17.5.1 Input Cloc k and  Loss-of-Signal Monitoring
The TMUX det ects and repor ts the loss of the 155 MH z i nput c lock for STS-3 mode  and the loss of the 
51.84 MHz clock for S T S-1 mode with register bits TMUX_RHSILOC —state (Table 91, s tarting on page92 ), 
TMUX_RHSILOCD—delta state (Table 91, s tarti ng on page 92), TMUX_RHSILOCM—interrupt  m as k ( Table 91, 
starting on page 92 ). LOC is determined by a stuck high or stuck low for a time greater than 10 µs and uses the 
micro processor clock as its reference.
The TMUX will detect and report a loss-of-signal condition with register bits TMUX_RHSLOS—st ate (Table 91 on 
page 92), TMUX_RHSLOSD—delta state (Table 91, s t ar t ing  on pa g e9 2), TMUX_RHSLOSM —i nterrupt  m ask  
(Table 86 on page88 ), b y monitoring the e xternal input signal pin,  LOSEXT (pin AE5), or detecting a conti nuous 
all-zeros/ones patte r n for 51.44 ns  to 105 µs  in 51.44 ns steps before data is descrambled. The detect ion time is 
determined by the value programmed in register bits,  TMUX_LOSDETCNT[10:0] (Table 97 on pag e97). The LOS 
state will clear after reception of two consecutive receive frames with th e correct framing pattern spaced 125 µs 
apart wit hout an incomi ng L OS  all-zeros/ones p attern. T his rec overy  applies to both internal and external LOS fail-
ure causes.
17.5.2 High-Speed Loopback Select Logic
The device can be configured to loopback the tran smit S TS-3/STM-1 (AU-4) TMUX_TH S2RHSLB = 1  (Table 93 on 
page 94) or accept  the local STS-3/S TM -1 (AU-4) signal TMUX_THS2RHSLB = 0.
17.5.3 Frame Alignment—STS-3/STM-1 (A U-4) Framing or STS-1 Framing
The device will frame on the  incomi ng signal. The state of the framer, out of frame (OOF) (register bit 
TMUX_RHSOOF,  see Table 91 on page92 ) as well as any changes to this state (register bits TMUX_RHSOOFD—
delta state, see Table 91, starting on pag e 92 and TMUX_RHSOOFM—i n te rr upt  ma sk; s ee Table 86 on page88 ) 
will be reported.
The 32-bit (A1-2, A1-3, A2-1, and A2-2) framing pattern will be used in the frame detection for the 
STS-3/STM-1 case and a 16-bit pattern will be used for the STS-1 case. The device will be considered out of frame 
until two successive framing patterns separated in time b y 125 µs  occur  withou t framing b yte e rrors. 
The device will be consi d ered in  fr a me until five
 
successive frames, separated in time by 125 µs, occur with errored 
framing patterns. If the framer transitions to the out of frame state, the framer  will remain synchronized to the last 
known frame boundary or the latest detected unerrored framing pattern.
A loss of fr ame (LOF) (register bit T MUX_RHSLOF; see Table 91 on p age 92) state bit as well as an y changes to 
this state (register bits TMUX_RHSLOFD—delta state ,  see Table 91, start ing on page92 , TMUX_RHSLOFM—
in ter r u pt  m ask; see Table 86 on page88 ) will be reported. These state and mask and delta bits are the same for 
both types of input data, STS-3/STM-1 or STS-1.
The device will be considered in the LOF state when an OOF condition persists for 24 consecut ive frames (3 ms). 
The device will transition out of the LOF state after receiving 24 co n secutive frames  w ith the correct framing pat-
tern s spaced 125 µs apart and the OOF condition is cl ear.
17.5.4 B1 BIP-8 Check
A BIP-8 even parity will be computed over all the incoming bits  of the STS- 3/STM-1 frame (STS-1 f rame in STS -1 
mode), which are scrambled (except for the bits in the A1, A2, a nd J 0/Z0 by t es) and c ompared to t he B1 byte 
received in the  next frame.
The total number of B1 BIP-8 bit errors (raw count) , or bl ock  errors (as determined by register bit 
TMUX_B ITBLKB1;  see Table 95 on page 95),  are cou nted . Upon t he assertion of the perfo rmance monitor control 
signal as configured in the microprocessor interface block,  the raw  count will be reset to zero and the value trans-
ferred to a 16-bit counter for B1 error counts B1ECNT[15:0] (Table 124 on pag e118). 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
370 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
In case of overflow, depending on the value programmed in the microprocessor interface register bit  
SMPR_SAT_ROLLOVE R (Table 67 SMPR_GCR, Global Control Register (RW) on page 68), the B1 error counter 
will either roll over or  saturat e at the maximum value until cleared. 
17.5.5 J0 Monitor
J0 (section trace overhead) monitoring is done via register bits T MU X_J0 MON MOD E [2:0]  (Table 95 on pag e95). 
This J0 monitoring has six d ifferent monitoring modes, a s follows:
■TMUX_J 0MONMODE[2:0] = 000: the TMUX latch es the value of  the J0 byte ev e ry frame for  a total of  
16 by tes into registers TMUX_J0DMON[16—1][7 :0]; s ee Table 132 on page121 . The TMUX compares the 
in coming J 0  byte w ith the n ext expected value (the expected value is obtained by cycling through the  previously 
stored 16 recei ved bytes in round-robin fashion) and, if different, setting the section trace identifier mi sma t ch  
state register bit, TMUX_RTIMS,  see Table 91 on page92 . A ny   change to T MUX_RT IMS  will be reported via 
delta and inter rupt regi s ter  bits TMUX_RTIMSD; see  Table 82, starting on pag e79 and TMUX_RTIMSM; see 
Table 86 on page88 .
■TMUX_J0MONMODE[2:0] = 001:  this  is the SONET framing mode. The hardware looks for a 0x0A character  to 
indicate that the next b yte is the first byte of the path trace message. The J 0 byte message is continuously  writ-
ten into TMUX_J0DMON[1—16][7: 0] registers with the first  byte residing at the first address. If any received byte 
does not match the previ ously receiv ed byte f or its location, then the state register bit, TMUX_R TIMS, is set. An y 
change to RTIMS  will be reported  via d elta and interrupt mask regi ster bits T MUX_RTIMSD and 
TMUX_RTIMSM.
■TMUX_J0MONMODE[2:0] = 010:  this   is  the SDH framing mode. The hardware looks for the byte with the most 
significant bit (MSB) set to one, w hich in dicates that the next byte is the second byte o f the message. The rest of 
operation is the same as in SONET framing mode.
■TMUX_J0MONMODE[2:0] = 011: a new J0   byte (TMUX_J0DMON[1][7: 0] ) will be  detected after the number of 
consecutive consistent occurrences of a new pattern in the J0 overhead byte as determined by the valu es  in reg-
isters TMUX_CNTDJ0[3:0]; see Table 98 on page98 . Any changes to this byte are reported via de lta and inter-
rupt  mask registers TMUX_RTIMSD and TMUX_R TIMSM. The TMUX_RT IMSD delta bit  in this mode indicates a 
chang e in state  for the TMUX_J 0DMON[1][7:0] byte and the  state regis ter bit,  TMU X_RTIMS, is not used.
■TMUX_J0MONMO DE[2:0] = 100: the user will program the 16 expected values of J0 in the SONET frame into 
registers TM UX_ EXPJ0DM ON[ 1—1 6][7:0]; se e Table 131 on page 121.  The fir st e xp ec ted b yte, the byte follow-
ing t he 0x0A character, is written into the f i rst location TMUX_J0DMON[1] [ 7:0] . T he T M U X  compare s the inco m-
ing J0 s equence with the stored expected value and sets the state  register bit, TMUX_RTIMS (Table 91 on 
page 92), if they are different. Any change to  TMUX_RTIMS is reported via regis ter bit s  TMUX _RTIMSD (d elta 
state) and TMUX_RTIMSM (interrupt   mask).
■TMUX_J0M ONMODE[1:0] = 101: the user will program the 1 6 expected values o f J0 in the SDH  frame in regis-
ters TMUX_EXPJ0DMON[1 —16][7:0]. The first  b yte of  the message has the MSB set to 1. The TMU X comp ares 
the incoming J0 sequence with the stored e xpected value, setting the state register bit,  TMUX_R TIMS, if they are 
different. Any change to TMUX_RTIMS wil l be reported  via register bits TMU X_RTIMSD (delta state) and 
TMUX_RTIMSM (interrupt mask).
■TMUX_J0MONMODE[1:0] = 110 and 111 are currently undefined. 
17.5.6 Descrambler
A frame synchronous descramb l er of length 127 and generating polynomial x7 + x6 + 1 w ill descramble th e en tire 
STS-3/ST M-1 (or S TS-1) signal except for the first row of overhead. The s c rambler will be set to 1111111 on the 
first byte following the last section overhead byte in the first row (i.e., after byte J0 for STS-1). The descrambler 
operates in a byte-wide mode.
The frame descramb ler can be enabled or disabled using register bit TMUX_RHSDSCR (Table 93 on page94 ).

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
371Agere Systems Inc.  
17 TMUX Functional Description (continued)
17.5.7 F1 Monitor
The TMUX  monitors the fault location b yte TMUX_RF1MON0[ 7:0] (Table 101 on p age 100). A new f aul t location 
state will be detected after the number of consecutive consistent occurrences of  a new pa ttern in the F1 overhead 
byte as determined by t he value programmed in TMUX_CNTDF1[3:0] (Table 98 o n pag e98). 
The TMUX maintains a history of the previous, valid F1 byte in TMUX_RF1MON 1[7:0] (Table 101 on pag e100), 
and any changes will be repor ted v ia TMUX_RF 1M OND (delt a state) (Table 82, starting on pag e79) and 
TMUX_RF1MONM— (interrupt mask) (Table 86 on page88 ).
This continuous  N -times detection counter will be reset to 0 upon the transition of the framer into the out of frame 
state.
17.5.8 B2 BIP-8 Check
A B2 BIP-8 even pa rity is computed over all the incoming bits (except for  the nine section overhead byt es) of the 
STS-1 frame after descrambling, and compared to the B2 byte received in the next frame.  The total  number of B2 
BIP-8 bit errors (ra w count), or bloc k errors (as determined by T MUX_BITBLKB2;  Table 94 on page 94), i s counted. 
Upon the assertion of the  perf ormance monitor control signal as configured in the micr oprocessor interface , the raw 
count  w ill be reset to zero and the value transferred to an 18-bit holding register for  B2 error  c ounts 
(TMUX_B2EC NT[17: 0]; see  Table 125 on page119 ). In case of overflow,  dependin g on the value programmed in 
the microprocessor interface register bit SMPR_SAT_ROLLOVER (Ta ble 6 7 on pag e68), the B2 e rror counter  will 
either roll over or  saturate at the maxim um value unt il cleared.
17.5.9 Automatic Protection Switch (APS)  Monitor
The TMUX monitors the receive APS value (the K1 byte , and the five most significant bi ts of the K2 byte) and 
stores this value in TMUX_RAPSMON[1 2:0] (Table 102 on page100 ). Th is register is updated after the reception 
of a programmed number o f identical consecutive  frames as determined by the  value i n  TMUX_CNTDK1K2[3:0] 
(Table 98 on page98 ). Whenever the contents of TMUX_RAPSMON[12:0] changes , a delta bit,  
TMUX_RAPSMOND will be set (Table 82, starting on page 79)  and the interrupt can be masked using 
TMUX_RAPSMONM (Table 8 6 on pag e88). This indication also contributes to a separate device inter rupt indica-
tion specific ally inten ded for automatic protection switching.
The  T MUX monitors this  same 13-bit APS val ue (K1[7:0],  K2[7:3]) in the receive dir ect ion and reports when the 
APS va lue is i nconsistent,  usi ng TMUX_RAPSBABE—Rec eive APS Babble Even t (Table 82 on pag e79) and 
TMUX_RAPSBABM—Receive APS Babble Mask (Table 86 on page 88). Incon si s tent AP S b ytes are defined as 
the number of successive frames of ASP data where no frames s atisfy the criteria for updating the 
TMUX_RAP SMON register (Table 102 on page100). The number of inconsistent frames allowed before reporting 
is programmed in TMUX_CNTDK1K2FRAME[3:0] (default = 12, see Table 98 on page98). This continuous N-
times det ection counter will be  reset to 0 upon the  transition of the framer into the out-of-f rame s t ate or  upon the 
detection of a B1 error.
17.5.10 K2 M on itor, AIS-L and RDI-L Detect
The three least significant bits of  K2 are independently monitored and the current value is stored in 
TMUX_K2M ON[ 2:0] (Table 102 on page100 ). The  r egi st er wil l  be updated after the  programmed number of con-
secutive identical K2[2:0] bits.  This number is programmed by  the value in TM U X_CNTDK2[3:0] (Table 98 on 
page 98). Whenever the c ontents of T MUX _K2MON[2: 0] changes, a delta bit, TM UX_RK2MOND will be set 
(Table 82, starting on page79 ),  and the interrupt ca n be mas ked using TMUX_RK2MONM (Table 8 6 on pag e88).
T he TMUX m oni tors for line AI S (AIS-L/ MS-AIS) in the K2[2:0] b its (K2[2:0] = 111 ). When line AIS is  detected, 
TMUX_RLAISMON (Table 91 on page92) will be set t o 1 after a number of consecutive occurrences of line AIS as 
determined by t he value programmed in TMUX_CNTDK2[3:0]. Once set, AIS-L will be c leared after a number of 
consecutive frames of no line AIS as  deter mined by  this same value in TMUX_CNTDK2[3:0]. 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
372 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
Any change to TMUX_RLAISMO N will be reported in TMUX_RLAISMOND (Tab le 82, starting on page 79 ) and the 
interrupt can be masked using TMUX_RLAISMONM (Table 86 on page 88).
The  T MUX monitors for  a re mote defect indication  ( RDI-L/ MS-RDI) condition in the K2[2:0] bi t s  (K2[2:0] = 110) .A 
line RDI condition will be detected and TMUX_R LRDIMON (Table 91 on page92 ) w ill be set to  1 af ter a number of 
consecutive occurrences of RDI as determined by the value in TMUX_CNTDK2[3:0]. Once set, RDI-L will be 
cleared after a number of consecu tive frames of n o  RDI as determined by  this same value  programme d i n 
TMUX_CNTDK2[3:0]. Any change to TMUX_RLRDI MON, will be reported in TMUX_RLRDIMOND (Table 82, start-
ing on page79 ) and the interrupt can be masked using TMUX_RLRDIMONM (Table 86 on page 88). T his continu-
ous N-times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state.
17.5.11 M 1 REI-L Detect
One byt e (M1) is allocated for use as a line remote error indication funct io n  (REI-L).  For STS-3/STM-1 signals, all 
eight bits  of the M1 byte are allocated for REI-L information. The  REI-L value reflects the error count  detected by 
the line terminating equipment (LTE) (using the line BIP-8 code) back to its peer LTE. F or STS-3/STM-1 signals, the 
value of the error  count can be  up t o 24. A value of 25 and above will  be interpreted as no  errors. If 
TMUX_R_M1_BIT7 (Table 9 6 on pag e96) is 1, then th e  most significant bit of the by te is i gnored .
The  TMUX allo ws ac cess to t he acc umul ated  M1-REI  err ored bi t co unt from the M1 byte via TMUX_M1ECNT[17:0] 
(Table 126 on page 119). The counter will count in bit or block mode, depending upon the v a lue of 
TMUX_BITBLKM1 (Table 94 on page94 ). At the s elect ed perfor mance monitor ( PM) inte rval, the value of the inter-
nal running raw counter is placed into a holding register, TMUX_M1ECNT[ 17: 0], and then c leared. Depending on 
the va l ue of SMPR_SAT_ROLLOVER (Table 67 on pag e68) in the microprocessor interface, the intern al counter 
will either roll over or saturat e a t its maximum value until cleared.
17.5.12 Sync Status Monitor
The S1 by te is allocated for synchronization status. S1 bits [7:4] are used to convey  a 4-bi t code of which o n ly  six  
patterns are defined with the remaini ng codes rese rved for qual ity levels defined by individual administrations.
The S1 byte can be monitored in   two modes: (1) as an entir e 8-bit word  or (2) as one 4-bit nibble (bits [7:4]), as pro-
grammed by  TMUX_S1MODE4 (Table 95 on page 95).
■TMUX_S1MODE4 = 0 the associated state, delta, and mask registers are TMUX_RS1MON[7:0] (Table 103 on 
page 100), TMUX_RS1MOND (Table 82,  s tar ting on page79 ),  an d TM UX_ RS1MO NM (Table 86 on page 88), 
respectively.
■TMUX_S1MODE4 = 1 the associated state, delta, and mask registers are TMUX_RS1MON[7:4], 
TMUX_RS1MOND, and TMUX_RS1MONM.
A new value will be detected after  a programmed number of consecutive occurrences of a consistent new value in 
the incoming S1 byte as det ermine by the value in  TMUX_CNTDS1[3:0] (Table 98 on page98 ). A maskable event, 
TMUX_ R S1 BABE (Table 82, starting on page79 ), is set if a programmed number of consecutiv e fr ames pass with-
out a validated mes sage occurring as determined by the value in TMUX_CNTDS1FRA ME[3:0] (Table 98). 
In 8-bit mode, the entire value is monitored for an inconsist ent value, while in 4-bi t mode, only th e most  sig ni ficant 
nibbl e is moni tored for  a n inc ons ist ent value. This continuous N-times detection counter will be reset to 0 upon the 
transition of the framer into the out-of-frame state.
17.5.13 Receive Tr ansport Over head Access Channe l (RTOAC)
A transport overhead access channel (TOAC) is provided on-chip to drop the transport overhead ( T OH) por tion of 
the incoming S DH or SO NET frame.  The TOAC channel supports   three modes of operati on based on the conf igu-
ration of TMUX_RTOAC_D13MODE and TMUX _RTOAC_D412 MOD E (Table 117 on page113).

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

373Agere Systems Inc.

17 TMUX Functional Description (continued)

The TOAC channel consist s of the fo llow ing s ignal s :

■A clock signal sourced by the de vice pin, RT O A CCLK (external output pin AD1). The clock frequency depends on

the values of TMUX_RTOAC_D13M ODE and TMUX_RTOAC_D412MODE. See Table 522 below.

■A data signal out of RTOACDATA (exte rnal output pin A D 3). The data rate and the values transmitted depend on

the values of TMUX_RTOAC_D13M ODE and TMUX_RTOAC_D412MODE. See Table 522 below.

■An 8 kHz synchron ization signal, out to output pin, RTOACSYNC (external output pin AA5). The sync signal is

nor mally low. During the last clo ck period of each frame coincident with the least signifi cant bit of the last byte

(the eight y-first byte for all TOH modes), the sync signal is driven high.

Receive TOAC DCC1—DCC3 Mode. In this m ode, DCC byte s 1 to 3 are transmitted ser ially on the data pin. The

clock rate is 192 K H z . The data bytes are transmitted MSB first, and the data bytes are driven out in sequential

order: DCC1, DCC2, and DCC3. The da ta signal is partitioned into frames of 3 bytes with a repetit ion rate of 8 kHz.

Receive TOAC DCC4—DCC12 Mode . In this mode, DCC bytes 4 —12 are transmitted se rially on the data output.

The clock rate is 576 K H z . The data bytes are transmitte d MSB first, and the data bytes are dri ven out in sequential

order: DCC4, DCC5, DCC6, DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. The data signal is partitioned into

frames of 9 bytes . The frame repetiti on rate is 8 kHz .

Receive TOAC Fu ll TOH Ac cess Mo de . In this mode, the data signal is partitioned int o frames of 8 1 byte s. The

frame rep etition rate is 8 kHz. Each byte consi sts of 8 bits that are transmitted/rec eived most significant bit first.

T he M SB of th e fi r st b yt e o f each frame contains an odd/even parity bit over the 648 bits of the previous frame. The

remaining 7 bits of this byte are not specified.

Bytes shown in Table 523 below s ummar ize the access capabilities of the receive TAO C in full access mode. The

transport overhead bytes shown in this table are always dropped by the receive side. There is programmability on

the transmit side regarding the insertion of these bytes. Bytes indicated in bo ld type are not specified in the stan-

dard, but are available on the receive TOAC dat a sig nal.

Table 522. Receive TOAC Modes

TOAC Mod e TMUX_RTOAC_D13MODE

Value TMUX_RTOAC_D412M ODE

Value Number of Data

Bytes per Frame Clock Rate

DCC1—DCC3 1 X 3 1 92 KHz

DCC4—DCC12 0 1 9 576 K H z

Full TOH Mode 0 0 81 5.184 MHz

Table 523. Transport Overhead Byte Access—Recei ve Di rection

OH Parity A 1-2 A1-3 A2-1 A2-2 A2-3 J0 Z 0-2 Z0-3

B1 B1-2 B1-3 E1 E1-2 E1-3 F1 F1-2 F1-3

D1 D1-2 D1-3 D2 D2-2 D2-3 D3 D3-2 D3-3

H1-1 H1-2 H1-3 H2 H2-2 H2-3 H3 H3-2 H3-3

B2-1 B2-2 B2-3 K1 K1-2 K1-3 K2 K2-2 K2-3

D4 D4-2 D4-3 D5 D5-2 D5-3 D6 D6-2 D6-3

D7 D7-2 D7-3 D8 D8-2 D8-3 D9 D9-2 D9-3

D10 D10-2 D10-3 D11 D11-2 D11-3 D12 D12-2 D12-3

S1 Z1-2 Z1-3 Z2-1 Z2-2 M1 E2 E2-2 E2-3

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

374 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

Receive TOAC—OH Parity. Even or odd parit y can be i nserted into the fi rst bit of the M SB byte of the TOAC out-

going frame by program mi ng TM UX_RTOAC_OEPINS (Table 117 o n pag e113).

17.5.14 MSP 1 + 1 Payload Switch

The TMUX suppor ts a payload 1 + 1 protecti on switch. In the receive direction, this occurs prior to pointer interpre-

tation. If TMUX_RPSMUXS EL1 = 1 (Table 93), then the input receive data and c lock are selecte d from the pr otec-

tion path : device pins RPS D 155P /N (pins A D 10/ AE10) an d RPSC155P/N (pins AC10/AD11), rather than from the

normal (wor king) path device pins, RHSDP/N (pins AF7/AE7) and RHSCP/N (pins AC7/AD8).

17.5.15 Pointer Interpreter

The STS-3/STM-1 pointer interpreter logic block performs all necessary functions to support STS-3/STM-1, as well

as STS-1, pointer i nte rpretation. The pointer interpreter operates as one machi ne in STM-1 m ode and as three

independent machines in STS-3 mode. The following features a re implemented:

■The pointer interpreter consists of the follo wing st ates:

— LOP: loss of pointer

— AIS: al arm indiction s ignal (all ones in H1 and H2 )

— NDF: new data flag enabled (1001,0001,1101,1011, and 1000)

— NORM: normal (disabled NDF, normal pointer)

— INC: increment (in verted I bits)

— DEC: decrement (in verted D bits)

* This st ate diagram is based on the E TS-417-1-1 pointer interpretation state diagram (Figure B.1). T ransitions of eight invalid pointers from the

INC, DEC, and NDF states into the LOP state have been added. 5-9007(F)

Figure 2 6. Pointer Interpretation St ate D i agra m

NORM

DECINC

NDF

AISLOP

FROM ALL ST ATE S

8 INVA LID POINTERS

FROM ALL ST AT ES

3 NEW POINTERS

INCREMENT DECREMENT

8 NDF ENABLE

NDF ENABLE

NDF

3 ANY 3 ANY

3 NEW POINTERS

3 ANY PO IN TER S

3 NEW POINTERS

8 INVALID

8 INVALID POINTERS*

INDICATION INDICATION

3 AIS INDICATIONS ENABLE

ENABLE

POINTERS POINTERS

POINTERS ENABLE

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

375Agere Systems Inc.

17 TMUX Functional Description (continued)

■The pointer inte rpreter transitions into the LOP state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received in 8, 9, or 10 consecutive frames, as

determined by the value in TMUX_CTDLOPCNT[1:0] (Table 98 on page98 ), then LOP will be declared.

— Invalid pointer values. If 8, 9, or 10 consecutive frames (determined by TMUX_CTDLOPCNT[1:0]) are received

with a pointer that is not a normal value, NDF, AIS, increment, or decrement, then LOP will be decl ared.

■The pointer interpreter will transition out of the LOP state based on the following con ditions:

— Following three conse cutive frames with all one s in the H1 and H2 bytes, the pointer interpr e ter will transition

from the LOP state into the A IS state.

— Followi ng three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

LOP state into the NORM stat e.

— The pointer interpreter

will not tra ns iti on fro m the L OP stat e int o the NDF state.

■The pointe r inte rpreter will tran sit ion into the AIS state based on the following conditions:

— Following three consecutive f rames with al l ones in the H1 and H2 bytes, AIS will be declared .

■The pointer interpreter will tran sit ion out of the AIS s t ate based on the following conditions:

— Followi ng three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

AIS state into the NORM state.

— Following eight consecutive invalid pointers, the po inter interpreter will transition from t he AIS st ate into the

LOP state.

— If ND F is enabled on the incoming H1 and H2 bytes, the pointer interpr e ter will transition from the AIS state

into the NDF state.

■The pointe r inte rpreter will transit ion into the NDF state based on the following condition:

— If ND F is enabled on the incoming H1 and H2 bytes, the pointer interpre ter will transitio n from t h e N ORM,

NDF, AIS, INC, and DEC states into the NDF state.

■The pointer inte rpreter will transition out of the NDF s tate based on the following conditions:

— Continuous NDF. I f NDF (1001, 0001, 1101, 1011, and 1000) is received for eight c onsecutive frames, the

pointer interpreter will transition from the NDF state into the LOP state.

— Following any three consecutive, consist ent, and valid pointers, the pointer interpreter will transition f rom the

NDF state into the NORM state.

— Following three conse cutive frames with all one s in the H1 and H2 bytes, the pointer interpr e ter will transition

from the NDF state into the AIS state.

— Followi ng three new , consecutive , consistent, and valid pointers, the pointer interpreter will transition from the

NDF state into the NORM state.

— Following eight consecutive invalid pointers, the po inter interpreter will transition f rom the NDF state into the

LOP state.

■The pointer inte rpreter will transition int o the N O RM state based on the fol lowing conditio ns:

— Following three new consecutive, consistent, and v alid pointers, the pointer interpreter will transition into the

NORM state.

— Foll owi ng any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the

NORM state, i .e., transitioning from the INC, DEC, and NDF states.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

376 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

■The pointer inte rpreter will transit ion out of t he N ORM state based on the foll owing conditions:

— Following eight consecutive invalid pointers, the po inter interpreter will transition from the NORM state into

the LOP state.

— If ND F is enabled on the incoming H1 and H2 bytes, the pointer interpre ter will transitio n from t h e NORM

state into the NDF state.

— Following three conse cutive frames with all one s in the H1 and H2 bytes, the pointer interpr e ter will transition

from the NO RM state into the AIS state.

— When operating in the 8 of 10 mode, controlled by TMUX_8ORMAJORITY = 1 ( Table 95 on page95 ), if 8 of

the 10 I and D bits are correct for a pointer decrement on the incomi ng H1 and H2 bytes, the pointer inte r-

preter will transition from the NORM state into the DEC s tate. Otherwise, if 3 of the 5 I bits and 3 of the 5 D

bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition

from the NORM state into the DEC stat e.

— When operating in the 8 of 10 mode (TMUX _8ORMAJORITY = 1), if 8 of the 10 I and D bit s are cor r ect for a

pointer increment on the incoming H1 and H2 bytes , the pointer interpreter will transition from th e NORM

state into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment

on the incoming H1 and H2 by tes, the pointer interpreter will transition fr om the NORM state into the INC

state.The p ointer interpreter will transition into the INC state based on the following conditions:

— When operating in the 8 of 10 mode (TMUX _8ORMAJORITY = 1), if 8 of the 10 I and D bit s are cor r ect for a

pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition into the INC state.

Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and

H2 bytes, the pointer interpreter will transition into the INC state.

■The pointer inte rpreter will transition out of the INC sta te based on t h e following conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will tr ansition from the INC state

into the NDF state.

— Following three conse cutive frames with all one s in the H1 and H2 bytes, the pointer interpr e ter will transition

from the INC state into the AIS state.

— Followi ng three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

INC sta te into the NORM state.

— Following any three consecutive, consist ent, and valid pointers, the pointer interpreter will transition f rom the

INC sta te into the NORM state.

— Following eight consecu tive invalid pointers, the pointer interpreter will t ra nsition from the INC state into the

LOP state.

■The pointer inte rpreter will transit ion into the DEC state based on the following conditions:

— When operating in the 8 of 10 mode (TMUX _8ORMAJORITY = 1), if 8 of the 10 I and D bit s are cor r ect for a

pointer decrem ent on the incoming H1 and H2 bytes, the poi nter interp reter will transition into the DEC state.

Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and

H2 bytes, the pointer interpreter will transition into the DEC state.

■ The poi nter interpreter w ill t ransit ion out of the D EC st ate based on the f ollowin g conditions:

— If N D F is enabled on the inc oming H1 and H2 bytes, the pointer interpreter will transition from the DEC state

into the NDF state.

— Following three conse cutive frames with all one s in the H1 and H2 bytes, the pointer interpr e ter will transition

from the DEC state into the AIS state.

— Followi ng three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

DEC state into th e NORM state.

— Following any three consecutive, consist ent, and valid pointers, the pointer interpreter will transition f rom the

DEC state into th e NORM state.

— Following eight consecutive invalid pointers, the pointer interpreter will transition from the DEC state into the

LOP state.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
377Agere Systems Inc.  
17 TMUX Functional Description (continued)
■Pointer  increments and d ecrements will be counted and presented to the microprocesso r as  fol lo ws :
— Pointer increments  and decrements   will be monitored and counte d internally.
— The internal and latched counts will be forced to clear (0x00) if TMUX_RLOP[3—1] = 1 (Table 92 on page 92 ) 
or TMUX_RPAIS[3—1] = 1 (Table 92), where [3—1] des ignates the tributary number.
— Upon the configured  performance monitor ing interval, raw counts are transferred to holding registers for 
pointer increments (TMUX_RPTR_I NC[1—3][10:0] (Table 129 on page121 )) and decrements 
TMUX_RPTR_DEC[1—3][10:0] (Table 130), a llowing access by the microprocessor. The raw counters will 
reset (t o 0x00).
— Dependi ng on the value of SMPR_SAT_ROLLOVER (Table 67 on page68 ) in the microprocessor interface 
block, the internal running counts saturate at their maximum value or rollover.
— However, increment and decrement event indications should be  ignored during  LOP station.
■The current  pointer state is read from  TMUX_RLOP[3—1]  and TMUX_RPAIS[3—1]. Any  change s in pointer con-
dition are read from the d elta s tate bits TMUX_RLOPD[3—1] and TMUX_RPAISD[3—1] (Table 83). T he associ -
ated interru pt mask bits are TMUX_RLOPM[3—1] (Table 87 on page89 ) and TM UX_RPAI S M[3—1] (Table 87). 
W hen th e devi ce  is receiving a con catenated s ignal (STM-1(AU-3)), the receive concatenation mode register bit, 
TMUX_ RC ONCATMODE (Table 95 on page 95), must be set  for the conc atenation state machines (register bits 
TMUX_CONCAT_STATE[3—2][1:0] (Ta ble 92 on page92 )) on p orts  2 and 3 to contribute to pointer e valuation. 
This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996 
- Ann ex  B.
17.5.16 Path Monitoring Functions
The following s ec tions describe the path monitoring functions. For STM-1 signals, the values corresponding to  
STS-1 #1 are the relevant signal s. F o r STS -3  input data, there are th ree versions of each path monitor, one corre-
sponding to each STS- 1. The mode bits are applied to the moni tors of all three STS-1s.
J1 Monitor. J1 (path trace) monitoring has six different  monitoring modes controlled by TMUX_J1MONMODE[2:0] 
(Table 95 on page95 ). The J1 monitoring mode fo r all three STS -1s within an STS-3 signal is the same.
■TMUX_J1M ONMODE[2:0] = 000: The TMUX latches the value of the J1 byte ever y frame for a total of 64 bytes 
in TMUX_J1DMON[1—3][1—64][7:0] (Table 137 on page122 , Table 138, and Table 139). The  TMUX  compares 
the incoming J1 byte with the next expected value (the expected value is obtained by cycling through the previ-
ous store d 64  received bytes in round -r obin fashion) and setting the path trace identifie r state regi ster b it(s ),  
TMUX_RTIMP[1—3] (Table 92 on page92 ), if different. Any   change to the path trace identifier is reported  in  
TMUX_RTIMPD[1—3] (Table 83), with interrupt mask bits, TMUX_RTIMPM[1—3] (Table 87 on page89 ).
■TMUX_J 1MONMODE[2:0] = 001: This is the SONE T framing mode. The hardware looks for the 0x0A char acter 
to indicate that the next byte is the first byte of the  path trace message. The J1 byte message is continuously 
wr itten into registers, TMUX_J1DMON[1—3][1—64][7:0], with the first byte residing at the first address. If any 
receiv ed b yte does not match  the previously received byte  for its location, then the state  bit(s), 
TMUX_RTIMP[1—3], is set. Any change to the path trace identi fier is reported in TMUX_RT IMPD[1—3], with 
interr upt m as ks bits, TMU X_RTIMPM[1—3].
■TMUX_J1MONMODE[2:0] = 010:   This is the SDH framing mode. The hardware looks for the byte with the MSB 
set to one , which indicates that the next byte is the s econd byte of the mess age.  The rest of operation is the 
same as in SO NET fr am ing mode, except that th ere are 16 bytes   instead of 64. 
■TMUX_J1MONMODE[2:0] = 011: A new J1 byte (TMUX_J1DMON[1][7:0]) will be detected after a number of 
consecutive consistent occurrences of a new pattern (determined by the v alue in TMUX_CNTDJ 1[3:0] (Table 99 
on pag e99)) in the J1 overhead byte.  Any changes to t his byte must be reported in TMUX_RTIMPD[1—3], with 
the interrupt mask bits, TMUX_RTIMPM[1—3]. The delta bit(s) in this mode i ndicate a change in state for the 
TMUX_J1DMON [1][7:0] by te, and the state bits, TMUX_RTIMP[1—3], are not used.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
378 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
■TMUX_J 1MONMODE[1:0] = 100: The user will program the 64 expected values of J1 in 
TMUX_EXPJ1DMON[1—3][1—64][7:0] (Table 134 on page122 , Table 135, and Table 136), in SONET  framing 
mode, where the first expected byte, the byte following the 0 x 0A character, is written into the first location of 
TMUX_EXPJ 1DM ON[1][7 :0] . The T MUX wil l compare  the i ncomi ng J 1 sequence with the stored expected value, 
setting the path trace identifier state bit(s), TMUX_RTIMP[1—3] if they are different. Any change to the path trace 
identifier is reported in TMUX_RTIMPD[1—3], with inter rupt mask bits, T MUX_RTIMPM[1—3]. 
■TMUX_J 1MONMODE[1:0] = 101: The user will program the 16 expected values of J1 in 
EXPJ1DMON[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. The 
TMUX  c ompares the incoming J1 sequ enc e with the stored expected value,  setting the state register bit(s), 
TMUX_RTIMP[1—3], if they are different.  Any change to path trace i dentifier i s  reported  in re gister  bit s, 
TMUX_RTIMPD[1—3], wi th interrupt mask bits, T MUX_RTIMPM[1—3].
■TMUX_J1MONMODE[1:0] = 110 and 111 are currently undefined. 
B3 BIP-8 Check. A B3 BIP-8 even pari ty is comput ed over all the incoming s y nchronous payload envelope bits of 
the STS-3/S TM-1/STS-1 signal after descrambling, and compared to the B3 byte received in the next frame. The 
total number of B3 BIP-8 bit errors (raw count), or block errors (as  determined b y TMUX_B ITBLKB3 (Table 95 on 
page 95),  is counted.  Upon the configured performance monitor  (PM)  int erval, the v alue of the internal running 
counter  is placed into holding registers TMUX_B3ECNT[1—3][15:0] (Table 126 on page119 ) and then cleared. 
Depending on the value of SMPR_SAT_ROLLOVER (Table 67 on pa ge68) in the microprocessor interface block, 
the internal counter will  either roll ove r or stay at its maximum value until cleared.
Signal Label C2 Byte Monitor. The C2 byte per STS -1/STM-1 is stored in TMUX_C2MON[1—3][7:0] (Table 104 
on page101 ). Eac h regist er will be updated after a number, de termined by the  value in TMUX_CNT DC2[3:0] 
(Table 99 on pag e99), of  consecutive frames of identical C2 bytes for a  given STS-1/STM-1, i.e., the 8-bit pattern 
must be ide ntica l for a programmed number frames prior to u pdating t he C2 register. Any  change to C2 byte moni-
tor is  reported via the corresponding delta and mask register bits, TMUX_RC2M O ND[1—3] (Table 83) and 
TMUX_RC2MONM[1—3]  (Table 87 on pag e89).
In addition,  there are prog rammable expected value(s) for the C2 bytes of each  STS-1/STM-1 in 
TMUX_C2EXP[1—3][7:0] (Table 100 on page100 ).   If the current value of a C2 byte in TMUX_C2MON[1—3][7:0] 
does not equal the expec ted C2 value in TMUX_C2EXP[1—3][7:0]), then a payload label mi smat ch def e ct may  b e  
declared f or that STS-1/STM-1 in TMUX_RPLMP[1—3] (Table 92 on page92 ).  A lso, if the current value  of a 
C2 byte is all 0s, then the corresponding unequipped defect is  declared in TMUX_R UN EQP[1—3] (Table 92). 
Note: The payload label mismatch and unequipped defects are mutually exclusive and unequipped  t akes  pr iority.
The  following table desc ribes the condition s for generating payload label mi smatch (TMUX_RPL MP[1—3]) and  
unequipped defects (TMUX_RUNEQP).

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

379Agere Systems Inc.

17 TMUX Functional Description (continued)

Table 524. S TS Signal L abel D efect Conditions

TMUX_FO RCEC2DEF[2:0] will force path pa yload label mismatch defects on those conditi ons that are shown on

in Table 524 above.

The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame

state.

RDI-P Detection. A remote defect i ndicati on-path (RDI-P) signal indicates to STS path terminating equipment

(PTE ) that its peer STS PTE has detected a defe ct on the signal that it origi nated. The TMUX supports a 1-bit

RDI-P code as well as a 3-bit enhanc e d R D I-P code; the mode is selectable using the TMUX_REPRDI_MODE

(Table 95 on page95 ). If TMUX_REPRDI_ MODE = 0, then the 1-bit code is supported, and if

TMUX_REPRDI_MODE = 1, then the 3-bit enhanced path RDI code is supported.

The TMUX monitors f or a 1- bit RDI -P code in G1[3] or a 3-bit enhanced remote defect indication (RDI-P) conditi on

in G1[3:1]. The curr ent value of the path RDI state will be detected after a number of consecu ti ve occurrences

determined by the value in TMUX_CNTDRDIP[3:0] (Table 99 o n page 99). T he current value(s) will be stored in

TMUX_RDIPMON[1—3][2:0]] (Table 104 on page 101), f or nonenhanced RDI-P mode , and the current va lue(s) will

be stored in TMUX_RDIPMON[1—3][2:0], for e nhanced RDI-P mode. A ny change to T MU X_RDI PMO N [1—3][2:0]

will be reported in TMUX_RRDIPD[ 1—3] wit h interrupt mask bits,T MUX_RRDIP M[1—3] (Table 87 on page89 ).

The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame

state.

REI-P Detection. Bits [7:4] of the G1 byte are al located for use as a path remote error indication function (REI-P).

■For S T S -1 and STM-1 signals, b its [7:4] of the G1 byte are allocated for REI-P which conveys the error count

detected by the PT E (using the path BIP-8 code B3) back to its peer PTE as shown in Table 525.

Provisione d ST S PTE

Functionality, Expected C2 Received Payload Label

(C2 in h ex) Defect TMUX_FORCEC2DEF = 1

(Table 97)

Any Equipped Functionality Unequipped (00) TMUX_R UNEQP No Change

Any E quip ped Functionality Equip ped—Nonspec ific (01) None No Change

Equipped—Nonspecific Any Value (02 to E0, FD t o FE) N one No Change

Any Payload Specific C ode The Same Payload Specific

Code (02 to E0, FD to FE) None No Change

Any Payloa d Specific C ode A Different Pay loa d Spec ific

Code (02 to E0, FD to FE) TMUX_RPLMP No Change

Equipped—Nonspecific (01) or

VT-Structured STS-1 (02) PDI, 1 to 27 VTx Defects

(E1 to FB) None TMUX_RPLMP

Any Payloa d Spec ific Code

Except VT-Stru ctured

ST S-1 (02)

PDI, 1 to 27 VTx Defects

(E1 to FB) TMUX_RPLMP No Change

Any Equipped Functionality P DI, 28 VT1.5 Defects or 1

Non-VT Payload Defect (F C) None TMUX_RPLMP

Any Equipped Functionality Reserved (FF) None TMUX_RPLMP

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
380 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
Table 525. STS-1 P-REI  Interpretat ion
The TMUX allows acc es s   to the G1-RE I errored bit count for each STS-1/ STM-1 in TMUX_G1E CNT[1 —3][15:0] 
(Table 128 on page 120), which is the accumulated error c ount from G 1[3:0] by te of the STS-1/STM-1 signal. The 
counter(s) will count in bit or block mode , depending on the value of TMUX_B ITBLKG1 (Table 95 on page95 ). 
Upon the c onfigured p er formance monitor (PM) inte rval, the value of the internal running counter is placed into the 
holding registers TMUX_G1ECNT[1—3][15:0] and then cleared. Dep ending on the val ue of 
SMPR_SAT_ROLLOVER (Table 67 o n pag e68)  in the microproc essor int er face block, the int ernal counter will 
either roll over or stay at its  maximum value   until cleared.
Path User Byte F2 Monitor. The TMUX monitors the path user channel in the F2 byte of each STS-1/STM-1. The 
F2 byt e(s) will be stored in TMUX_F2MON0[1—3][7:0] (Table 104, starting on page 101). Each r egister will be 
updated after a number of consec utive frames o f ident ical F2[7:0] as determined by the value in 
TMUX_CNTDF2[3:0] (Table 99 on page 99). That is , the 8-bit pattern must be identical for  the programmed number 
of f rames  prior to updat ing the  F2 register. Any change to F2 monitor registers will be reported in 
TMUX_RF2MOND[1—3]  (Table 83), with interrupt mask bits, TMUX_RF2MONM[1—3] ( Table 87 on page89 ). The 
TMUX also maintains a history   of  the previous valid F2   b yte in TMUX _F2MON1[ 1—3][7:0] (Table 104). The contin-
uous N-times detection counter(s) will be reset to 0 upon the tra nsiti on of th e framer int o the out of  frame state.
H4 Multiframe Indicator. The H4 byte is allocated for use as a mapping specific indicator byte. For VT-structured 
SPEs, this byte is used as a multiframe  indicator.
The TMUX passes  the H4 byte of each STS-1 onto the low- speed telecom bus so that it can be monitored by the 
VT mapper block. The TMUX also indicates when the H4 byte(s) has a value of 0x 01 by assert ing the RLSV 1 out-
put pin (pin number W4) on the telecom bus during  that frame.
Note: The three H 4 bytes of an S TS-3 signal can occ ur at  any time with respect to  one another within a frame. 
Path User Byte F 3 Monitor. The  TMUX monitors the second path user channel in the F3 byte for each 
STS-1/ST M-1. The F3 byte(s) for each STS-1/STM-1 is stored in TMUX_F3MON0[1—3][7:0] ( Table 1 04 on 
page 101). Each register will be updated after a number determined by the v alue in TMUX_CNTDF3[3: 0] (Table 99 
on pag e99) of c onsecutive frames of identical F3[7: 0] monitor bytes on that particular STS-1. That is, the 8-bit pat-
tern must be identical for the programmed number of frames prior to   updating the F3 regi ster. 
G1[7:4] Code Code Interpretation
0000 0 (no errors)
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 0 (no errors)
. . . . . .
1111 0 (no errors)

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
381Agere Systems Inc.  
17 TMUX Functional Description (continued)
Any change to F3 b yte monitor registers is reported in TMUX_RF3MOND[1—3] (Table 83),  wi th  inte rr upt  mask bits, 
TMUX_RF3MONM[1—3]  (Table 87 on page89 ). 
T he TMUX also maintains a history o f the previous valid F3 byte in TMUX_ F3MON1[1—3][7:0] (Table 104 on 
page 101).  T he con tinuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the 
out of frame state.
K3 Byte Monitor. The TMUX   monitors the K3 byte for each STS-1/STM -1 . The K3 by te(s) are stored in 
TMUX_K3MON[1—3][7:0] (Table 104). Each register will  be updated after a number determi ned  by the value in 
TMUX_CNTD K3[3:0]  (Table 99 on page99 ) of consecutive frames of identical K3[7:0] f or that particular 
STS-1/STM-1. T hat is, the 8 -bit patte rn must be identical for a number of frames prior to updating the  K3 register. 
Any change to K3 monitor registers is   reported in TMUX_RK 3MOND[1—3] (Table 83), with interrupt mask bits, 
TMUX_RK3MONM[1—3]  (Table 87 on page89 ). The continuous N-t imes detection counter(s) will be reset  to 0 
upon the transition of  the framer i nto the out of frame state.
N1 Byte Monitor. The TMUX monitors the N1  byte for each S TS-1/STM-1. The N1  byte(s) are stored in 
TMUX_N1MON[1—3][7:0]  (Table 104 on page101 ) . Each register  w ill be updated after  a number determined by 
the valu e in TMUX_CNTDN1[3:0] (Table 99 on page 99) of consecutive fr ames of identical N1[7:0] f or that particu-
lar STS -1 /STM-1. That  is, the 8-bit pattern  must be identical f or a number of frames prior to updating the N1 regis-
ter. Any change to N1 monitor registers will be reported in TMUX_RN1MOND[1—3] (Table 83), with interrupt  mask 
bits, TMUX_RN1M O NM[1—3]  (Table 87 on page89). The continuous N - times detection counter(s) will be reset to 
0 upon the trans ition of the framer into the out of frame state.
Signal Degrad e BER A lg orithm. A signal degrade state in register bit TMUX_RHSSD (Table 91 on page 92) and 
change of s tat e  indication is rep orted in register bit, TMUX_RHSSDD (Table 82, s tarting on page79 ), with the 
i nt e rr upt ma sk  bi t ,  T MU X_ RH SS DM  (Table 87 on page 89). This bit err or rate algorithm can operate on either B1 or 
B2 errors, det er mined by the value of TMUX_SDB1B2 SEL (Table 95 on page95 ).  E ac h B3 monitor has an i nde-
pendent signal deg rade function as w ell in TMUX_RSDB3[1 —3] (Table 92 on page92 ).
Declaring the signal degrade state requires the de finition of two measurement window s, a monitoring block consist-
ing of a number of frames in TMUX_SDNSSET[18:0] (Table 120 on page116 ) and a measurement interv al consist-
ing of a number of monitoring blocks in TMUX _SDBSET [11:0] (Table 120). A block is  determined bad when the 
number of bit errors equals or ex ceeds  a threshold set in TMUX_S DLSE T[3: 0] (Table 120). Signal degrade is 
declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SDMSET[7:0] 
(Table 526) for the meas urement interval.
Clearing the signal degrade st ate requires t he definition of two measurement windows, a monitoring block  consist-
ing of a number of frames in  TMUX_SDNSCLEAR[18:0] ( Table 120) and a measurement interval c ons isting of a 
number of m oni tor ing bl ocks in TMUX _S DBCLE AR [11:0] (Table 120). A block is det ermined good when the num-
ber of bit errors is less than a threshold set in TMUX_SDLCLEAR[3:0] ( Table 120). Signal deg rade is cleared when 
a number of good monitoring block s equals or  exceeds the threshold in TMUX_SDMCLEAR[7:0] ( Table 120) f or the 
measurement interval.
The set  parameters are used when th e signal degra de state is clear, and the clear p arameters are used when the 
signal degrade state is declared.
The signal degrade state may  be forced t o the declared state with TMUX_SDSET ( Table 78 on page 77) and forced 
to the cleared state with TMUX_SDCLEAR (Table 78). One shot sign al must be provided to force the BER algo-
rithm into the failed state or normal state, respectively.
The algorithm described above can detect bit error rates from 1 x 10–3 to 1 x 10–9.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
382 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
Table 526. Signal Degra de (SD) Parameters
Note: T h e  thr e sho lds written by  the co ntrol s ys t e m  will b e o ne  les s  t han  the des ired nu mb er, except   for  th e TMUX _SDLS ET[ 3 : 0 ]  and 
TMUX_SDLCLEAR[3:0] parameters.
Signal Fail BER Alg orithm. A signal degrade state in register bit TMUX_RHSSF (Table 91) and change o f state 
indication is reported in register bit, TMUX_RHSSFD (Table 82, starting on page79 ), with the interrupt m ask bi t, 
TMUX_RHSSFM (Table 86 on page88 ). Th is   bit error rate algorithm can operate on either  B1 or  B 2 e r rors 
selected with register b it, TMUX _SDB1B2SEL (Table 95 on pag e95). Eac h B 3 mo nitor has its own bit error rate 
algorithm as well with the failure i ndicat ed in TMUX _RSFB3[1—3]  (Table 92 on pag e92).
Declaring the signal degrade state requires the de finition of two measurement window s, a monitoring block consist-
ing of a number of frames in TM UX_SFNSSET[18:0] (Table 121 on page117) and a measurement interval consist-
ing of a number of monitoring blocks in TMUX_SFBSET[11:0] (Table 121). A  block is determ ine d bad w hen the 
number of  bit errors equals or exceeds a threshold set in T MUX_S F LS ET[3 :0] (Table 121). Signal degra de is 
declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SFMSET[7:0] 
(Table 121) for the meas urement interval.
Clearing the signal degrade st ate requires the d efinition of  two measurement windows, a monitoring block  consist-
ing of a number of frames in TMUX_SFNSCLEAR[18:0] (Table 121) a nd a measurem ent  i nterval consisting  of a 
number of m oni tor ing bl ocks in TM UX_S FBCLE AR [11:0 ] (Table 121). A block is determined good when the num-
ber of bit e rrors is less than a threshold set in T MUX_S F LCLE AR [3:0] (Table 121). 
Name Function
TMUX_SDNS SET [18:0] (Table 120)Signal Degrad e Ns  Set. Number of frames in a monitoring block for SD.
TMUX_S DLSET[3:0] (Table 120)Signal Deg rad e L Set. Error threshold for determining if a monitoring 
block is b ad.
TMUX_SDM SET [7:0] (Table 120)Signal Degrade M Set. Threshold of the number of bad  monitoring   blocks 
in an observation interval. If the number of bad bloc ks is below this thresh-
old, then SD is cleared.
TMUX_SDBSE T[15:0]  (Table 120)Signal Deg rad e B Set. Number of monitoring blocks in a measurement 
interval.
TMUX_SDNS CLE A R[1 8:0] 
(Table 120)Signal  Deg rade Ns  Clear. Number of frames in a monitoring b l oc k for 
SD.
TMUX_SDLCLEA R[3:0] (Table 120)Signal  Deg rad e L C lear. Error threshold  for deter mining if a monitoring 
block is b ad.
TMUX_SDMCLEAR[7:0]  (Table 120)Sign al  Deg rade M  Clea r. Threshold of the number of bad m o nitoring 
blocks in an observation interval. If t he number of bad blocks is below this 
thr e s h ol d ,  t hen SD is cl e ared .
TMUX_SDBCLE AR[15:0] (Table 120)Signal Degrade B Clear . Number of monitoring blocks in a measurement 
interval.
TMUX_SDSET (Table 78)Si gnal  Deg rad e Set. Allows the signal degrade algorithm to be forced 
into the failed state (active 0 t o 1).
TMU X_SDCL EAR (Table 78)Signal Deg rad e Clear. Allows the signal degrade algorithm to be forced 
into the normal state (active 0 to 1).
TM UX_ SDB1B 2S EL (Table 95)Sign al  Degrad e B1/B2 Error Count Select. Control bit, when set to a 
logic 0, caus es   the signal fail bit error rate algorithm to use B1 errors; oth-
erwise,  B2 errors are used to calculate the error rate.
TMUX_RHSSD (Table 91)Signal Deg rad e BE R Alg orithm  State Bit. 
TMUX_RHSSDD (Table 82)Signal Degrade BER Algorithm Delta Bit. 
TMUX_ RHSSDM (Table 86)Signal Degrade BER Algorithm Mask Bit. 

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
383Agere Systems Inc.  
17 TMUX Functional Description (continued)
Signal degrade is cleared when a number of good m on i t oring  blo c ks equals or exceeds the threshold in 
TMU X _ S FM C LEAR [7: 0]  (Table 121) for the measurem ent  interval.
The  set parameters are used when the signal fail state is clear, and the  clea r parameters are used when the signal 
f ail state is declared.
The signal degrade s ta te may be forced to the declared state wi th TMUX_SFSET (Table 78) and forced to the 
cleared state with TMUX_ SFC LE AR (Table 78).   One shot signal must be p r ovided to force the BER algorithm  into 
th e f ailed stat e or normal state, respecti v e ly .
The above algor ithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.
Table 527. Signal F ail P arameters
Note: T h e  thr e sho lds written by  the co ntrol s ys t e m  will b e o ne  les s  t han  the des ired nu mb er, except   for  th e TMUX _SFLSET [3:0 ]  and 
TMUX_SFLCLE AR[3:0] parameters.
Name Function
TMUX_ SFNSSET[18 :0 ] (Table 121)Signa l  Fail  N s Se t . Number of frames in a monitoring block for SF.
TMUX_SFLSET[3:0] (Table 121)Signal  Fail  L Set. Error threshold for determining if a monitoring block is 
bad.
TMUX_SFMSET[7:0] (Table 121)Sign al  Fa il M Se t . Threshold of the number of bad monitoring blocks in 
an observation interval. If the number of bad blo cks is below this thresh-
old, then SF is  cleared.
TMUX_ SFBSET[15 :0 ] (Table 121)Sign al Fail B  S et . Number of monitoring blocks.
TMUX_SFNSCLEAR[18:0] 
(Table 121)Signal Fail Ns Clear. Number of frames in a monitoring block for SF.
TMUX_SFLCLEAR[3:0] (Table 121)Sign al  Fa il L Clear. Error threshold for determining if a mon itoring block 
is bad.
TM U X _SFMCLEAR [ 7: 0] (Table 121)Signal Fai l M Clear . Threshold of the number of bad monitoring blocks  in 
an observation interval. If the number of bad blo cks is below this thresh-
old, then SF is  cleared.
TMUX_SFBCLEAR[15:0]  (Table 121)Signal Fail B  C lear. Number of monitoring blocks.
TMUX_S FB1B2SEL (Table 95)Signal Fail B1/B2 Error Count Select. Control bit, when set to a logic 0, 
causes the signal fail bit  error rate algorithm to use B1 errors; when set to 
a logic 1, causes the signal fail bit error rat e algorithm to use B2 errors.
TMUX_SFSET (Table 78)Signal Fail Set. Allows the signal degrade algorithm to be forced into the 
failed state (active 0 to 1).
TMU X_S FC LEAR  (Table 78)Signal  Fa il C lear. All ows the signal degrade algorithm  to be forced into 
the normal  state. (active 0 to  1).
TMUX_RHSSF (Table 91)Signal Fail BER A lgorithm  State Bit. 
TMUX_RHSSFD (Table 82)Signal Fail BER Algorithm Delta Bit. 
TMUX_RHSSFM (Table 86)Signal Fail BER Algorithm   Mask Bit. 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

384 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

Path Overhead Access Channel (POAC) Drop. The TMUX provides one path overhead access channel (POAC

output channel). The TMUX can receive up to three S TS-1 signals. There ar e tw o re g i ster bits,

TMUX_RPOAC_SEL[1:0] (Tabl e 118 on page 115), to designate which STS-1s POH will be dropped onto the

POAC channel. TMUX_RPOAC_SEL[1:0] = 01 designates STS-1 #1, TMUX_RPOAC_SEL[1:0] = 10 designat es

STS-1 #2, and TM UX_RPOAC_S EL[1:0] = 11 designates ST S -1 #3. TMUX_RPOAC_SEL[1:0] = 00 de signates

t hat th e RP OAC channel is not dr iven b y the TMUX.

The POAC ch annel consis t s of the follow ing s ignal s :

■A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3).

■A 576 kb its/s data signal sourced by the TMUX (RPOACDATA, pin AD4).

■An 8 kHz synchronization signal, sourced by the TMUX (RPOACSYNC, pin AF4). The sync signal is normally

low. During the last clock period of each frame coincident with the least signifi cant bit of the last byte, the sync

signal is high.

The data s ig na l i s pa rtitioned in to f ra mes of 9 bytes. The frame rep etition rate is 8 kHz. Each byte consists of 8 bits

that are transmitted/received most significant bi t first. The MSB of the second byte of each frame contains an

odd/even parity b it over the 72 bits of the previous frame. The remaining 7 bits o f this by te are not specified.

Bytes shown in Table 529 summarize the a ccess capabilities of the receive POAC.

Table 529. P ath Overhead Byte Access

Even or o dd pari ty can be inserted into the first bit of the MSB byte of the POAC outgoing frame. P ari ty i s selected

with TMUX_RPOAC_OEPINS (Table 118 o n page115 ).

AIS-P Insertion and AUTO_AISO Generation. Upon detecting cert ain fai lure conditions, the TMUX asserts the

external output signals named AUTO_AIS[1—3] (pins AD 6, AE6, and AC6). The AUTO_A IS[ 1—3] si gnals, one per

STS-1, als o informs th e other blocks within the Super Mapper to insert A IS downstream d ue to detected failures .

The followi ng conditions ca n cause AUTO_AISO[1—3] signals to be as serted: line AIS, LOC (STS -1 mode o nly),

LOS, LOF, OOF, L OP-P, SF (B1, B2, or B3), SD (B1, B2, or B3), payload label mismatch, or payload unequipped.

Each co ndition can be individually inhibited from contributing to the i nternal AUTO_AISO[1—3] signals. For concat-

enated signals (STS-3c or S TM- 1), all AUTO_A ISO[1—3] sign als should be driv en coincidentally . In STS-3 mode,

each STS-1 signal has a correspondi ng AUTO_ AISO signal.

Table 5 28. Signal Fail or Signal Deg rade Recommended Programming Values

Set

Threshold NsSet LSet MSet BSet Clear

Threshold NsClear LClear MClear BClear

1x10–30x00001 0x5 0x3D 0x003D 1x10–40x00001 0x6 0x03 0x0007

1x10–40x00006 0x8 0x03 0x0007 1x10–50x00006 0x2 0x03 0x0007

1x10–50x00030 0x6 0x03 0x0007 1x10–60x00030 0x2 0x03 0x0007

1x10–60x001E0 0x6 0x03 0x0007 1x10–70x001E0 0x2 0x03 0x0007

1x10–70x01275 0x6 0x04 0x0009 1x10–80x01275 0x2 0x04 0x0009

1x10–80x0B5A4 0x6 0x04 0x0009 1x10–90x0B5A4 0x2 0x03 0x0009

1x10–90x3F7A0 0x4 0x05 0x0013 1x10–10 0x3F7A0 0x2 0x02 0x000F

POH Parity

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

385Agere Systems Inc.

17 TMUX Functional Description (continued)

The following boolean expression is th e cr iteria for AUTO_AI S and send path AIS. The expressions represent com-

binations of s ignal st atus stat es register bits and inhibit state register bits that form the criter ia.

Criteria for AUTO_AISO<n> =

((TMUX_RLAISMON AND TMUX_RLAISMON_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RILOC AND TMUX_RILOC_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSLOS AND TMUX_RHSLOS_ AISINH AND TMUX_RPSMUXSEL ) O R

(TMUX_RHSLOF AND TMUX_RHSLOF_AISINH) OR

(TMUX_RHSOOF AND TMUX _RHSOO F_AISINH) OR

(TMUX_RLOP<n> AND TMUX_RLOP_AISINH) OR

(TMUX_RHSSF AND TMUX_RHSSF_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSSD AND TMUX_RHSSD_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RSFB3<n> AND TMUX_RSFB3_AISINH) OR

(TMUX_RSDB3<n> AND TMUX_RSDB3_AISINH) OR

(TMUX_RPLMP<n> AND TMUX_RHPLMP_AISINH) OR

(TMUX_RUNEQP<n> AND TMUX_RUNEQP_AISINH) OR

(TMUX_RTIMP<n> AND TM UX_RTIMP_AISINH) OR

(TMUX_RPAIS_INS))

In addition to generating the external AUTO_AIS si gnal , the TM UX ca n inse rt path AIS int o th e rec eiv e d si gn al prio r

to driving it onto the low-speed teleco m bus. The conditions for sending path AIS include some of the above condi-

tions. The same inhibit bits are used as above . Note that the above A UT O_AISO[1—3] signal generation is on a per

STS-1 basis, while sendin g path AIS occurs on the compl ete STS-3/ STM- 1 signal (or S T S-1 for STS-1 only m ode).

Criteria for Send Path AIS =

((TMUX_RLAISMON AND TMUX_RLAISMON_AISINH AND TMUX_ RPSMUXSEL) OR

(TMUX_RHSLOS AND TMUX_RHSLOS_ AISINH AND TMUX_RPSMUXSEL ) O R

(TMUX_RHSLOF AND TMUX_RHSLOF_AISINH) OR

(TMUX_RHSOOF AND TMUX _RHSOO F_AISINH) OR

(TMUX_RLOP<n> AND TMUX_RLOP_AISINH) OR

(TMUX_RHSSF AND TMUX_RHSSF_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSSD AND TMUX_RHSSD_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RPAIS_INS))

Receive Side Telecom Bus Interface. The TMUX outputs one parallel clock (RLSCLK, pin V4), t hree sync signals

(RLSSPE, RLSJ0J1V1, and RLSV1; pi n numbers V1, V3, and W4), an 8-bit data bus (RLSDATA[7:0], pins R1, R3,

T4, T2, T3, U4, U2, and U3), and an odd/even (RLSP AR, pin V2) parity signal. T he data bu s carries either three

STS-1/T UG-3 signals, each in their own time slot, or it carri es one STS - 1 s ignal where the para llel clock operates

at 6. 48 MHz instead of 19.44 MHz.

5-9008(F)

Figure 27. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals

A1-1 A1-2 A1-3 A2-1 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3A2-2

A1 A2 J0 J1 V1

3 BYT ES 3 BYTES 3 BYTES 3 BYTES 3 BYTES

RLSSPE

RLSJ0J1V1

RLSV1

RLSDATA[7:0]

RLSCLK

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

386 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

17.6 Transmit D irec tion (Transmit Path to SONET/SDH Line)

All func tions supported by TMUX in the tra nsmit direction are summ arized below:

■Transmit side telecom bus interface

■Path overhead access c hannel (POAC) insert

■Path overhead insertion fu nc tions

■MS P 1 + 1 payload switc h

■Transpor t overhead access channel (TOAC) insert

■Section and line overhead inserti on func ti ons

17.6.1 Transmi t S ide Telecom Bus Interface

The TMUX transmit side drives a parallel clock (TLSCLK, pin AA2) and three sy nc signals ( TLS SPE, TLSJ0J1V1,

and TLS V1; pins A B2, AB4, and AB3) onto th e telecom bus. From these sync signals, the SPE mappers can deter-

mine when to driv e data onto the bu s. The TMUX receives an 8-bit data bus (TLSDATA[7:0], pins W2, W1, W3, Y4,

Y2, Y1, Y3, and AA4), and an odd/even (TLSPAR, pin AA3) parity signal from the telecom bus . The data consists of

the SPE for up to 3 STS- 1 s.

The parallel clock operates at 19.4 4 MH z for STS-3/STM -1 mod es and at 6.48 MHz for STS-1 mo de.

5-9009(F)

Figure 28. Transmit Low-Speed Bus Interface Signals fo r STS-3/STM-1 Signals

17.6.2 Transmit Path and Transport Overhead Insertion Diagram

Th e trans mit blo ck consis ts of two o verhea d insertion sections. The first sectio n i nserts the path over head (POH )

bytes into the payl oad data to create an STS-3/STM-1/STS-1 SPE. After POH insertion, there is an MS P 1 + 1 pr o -

tection switch on the payload. After the switch sel ection is made, the transport overhead bytes are added to the

SPE to generate a complete SONET/SDH frame.

A1-1 A1-2 A1-3 A2-1 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3A2-2

A1 A2 J0 J1 V1

3 BYTES 3 BYTES 3 BYTES 3 BYTES 3 BYTES

TLSSPE

TLSJ0J1V1

TLSV1

TLSDATA[7:0]

TLSCLK

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

387Agere Systems Inc.

17 TMUX Functional Description (continued)

5-9010(F)r.2

Figure 29. Transmit Direction POH and TOH Insertion Diagram

The first section, which is the path overhead s ec t i on , is broken down into the following functional parts:

■J1 path trace insert

■B3 calculation and insert

■C2 signal label insert

■REI-P and RDI-P insert

■Path user byte F2 insert

■H4 mu ltiframe insert

■Path user byte F3 insert

■ K3 insert

■Tandem connection b yte N1 insert

■ AIS-P Insert

SCRAM. INSERT INSERT

AIS

MSOH

INSERT LINE/MSOH

F1 B2

GENERATE K1/K2 RDI-L M0

REI-L SYNC

APS

B2 K1

INSERT

K2 M0 S1

STATUS

B1 F1

SECTION/RSOH

INSERT J0

A1/A2

TRANSMIT PATH TO SONET/SDH LINE (TRANSMIT DIRECTION)

TRANSMIT DATA

TOAC INSER T

D4—D12 AND E2

B1, E1, F1, D1—3 I N SERT

INSERT

J1 INSERT

N1 INSERT

C2 INSERT

REI-P

INSERT

RDI-P

INSERT

APS

INSERT

N1 C2 F3 F2K3 G1 G1J1

INSERT

AIS-P

POAC INSERT

F2, F3, C2, N1, AND J1

INSERT PATH OVERHEAD BYTES

INSERT

TE LECO M B U S

TRANSMIT PROTECTION

MSP 1+1

SWITCH

SWITCH BU S D ATA

[2:0]

GENERATE

INSERT

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

388 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

The second sec tion after the switch, the transport overhead section, is broken down into the fo llowing functional

parts:

■ TOAC insert

■ Sync status byte (S1) ins ert

■ M0/M1—RE I-L Insert

■ K1 and K2 insert

■ AIS-L insert

■ B2 calculation and insert

■ F1 byte ins er t

■ B1 generate and error ins ert

■ Scrambler

■ J0 insert control

■ A2 error inse rt

All insert control functions that are inhibited will insert all zeros or al l ones, depending on the value of microproces-

sor reg ister bit, SM PR_OH_DEFLT (Table 6 7 on pag e68).

17.6.3 POAC Insert

One path overhead access channel (POAC) is provided on-chip to p rovision the path overhead (POH) portion of

the outgoing frame. The TMUX transmits up to three STS-1s. The register bits TMUX_TPOA C_SEL[1:0] (Table 118

on page115 ) designate which STS-1s POH is inserted from the transmit POAC channel.

TMUX_TPOAC_SEL[1:0] = 00 designates no TMUX_TPOAC insertion, TMUX_TPOAC_SEL[1:0] = 01 designates

STS- 1 #1, TMUX_TPOAC_SEL[1:0] = 10 designates STS-1 #2, and TMUX_T POAC_SEL[1:0] = 11 designates

STS-1 # 3.

A POAC ch annel consis t s of the follow ing s ignal s :

■A 576 kHz inverted clock signal sourced by the TMUX (TPOACCLK, pin AE4).

■A 576 kbits/s serial data signal received by the T M UX in the transmit direction (TPOACDATA, pin AD5).

An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the TMU X. The sync signal is normally low.

During the last clock period of each frame, coincident with the least significant bit of the eighth byte, the sync signal

is high.

The data s ig na l i s pa rtitioned in to f ra mes of 9 bytes. The frame rep etition rate is 8 kHz. Each byte consists of 8 bits

that are tr ansmitted/received most signi ficant bit fir st. The MSB of t he first byte of each frame contains an odd/ even

parity bit over the 72 bits of the previous frame. The remaining 7 bits o f this byte are not specified. The B3, G1, and

H4 transmit pat h over head bytes are not provisionable via the POAC channel.

Bytes shown in Table 530 summa rize the access capabilities of the transmi t POAC channel. X indicat es a d on’t

care.

Table 530. P ath Overhead Byte Access—Trans m it Direction

J1 X F3

POH Parity F2 K3

C2 X N1

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
389Agere Systems Inc.  
17 TMUX Functional Description (continued)
An ev ent indication TMUX_TPOA C_PE ( Table 80 on page78 ), interrupt mask bit TMUX_TPOAC_PM ( Table 84 on 
page 87), is provided to indicate parity errors for the POAC channel.  Odd (logic 0)/even (logic 1) parity   is checked 
and is configured wit h TM UX_TPOA C _ OEPMON (Table 117 on page113). 
Table 531 summarizes the insertion options  for the specified overhead bytes for POAC. The TMUX allows a fixed 
default value (all z eros or all ones) to be inserted  on the correspo nding P OAC val ue. All control signals  are activ e-
high.
Tabl e  531 . TPOAC Control  Bits
17.6.4 AIS Path Generation
Path AI S is specified as all ones in the entire STS-1 signal before sc rambling, excludi ng the transport overhead 
(section and line overhead).
Path AIS can be inserted for each ST S -1 in the STS-3  using reg ister bi ts , TMUX_TLS_PAISI NS[3:1] (Tab l e 105 on 
page 102).
17.6.5 J1 Insert Contro l
A 64-byte sequence stored in TMUX_TJ1DINS[1—3][1—64][7:0] (Table 140 on page123 , Table 141, an d 
Table 142), will be inser ted into the outgoing J1 byte if TMUX_THSJ1 INS (Ta ble 108 on page105 ) is set to 1. Oth-
erwise, the associated POAC value  is inserted when   T MUX _TPOAC_J1 (Table 118 o n page 115) is a logic 1, or 
the default  value is inserted when TMUX _TP OAC_J1 is logic 0.
17.6.6 B3 BIP-8 Calculation and Insert
The B3 bytes are allocated for a path overhead error monitoring function. This function will be a bit interl eaved par-
ity 8 code (BIP-8) using  even parity. The BIP-8 is computed before scrambling over all bi ts  of the previous STS-1 
frame except for the first three columns consisting  of the section and line overhead and is placed in byte B3 of the 
current frame, also before scrambling.
A bit error rate can be i nserted on any  B3 byte with TMUX_THSB3ERRINS[1—3] (Table 115 on page112 ) and 
micr oprocess or in terf ace  bloc k  SMPR_BER_I NSRT  (Table 65 on page 66) bi t. When TMUX_THSB3ERRINS[1—3] 
is a sserted, the corresponding B 3 b yte is inve rted each time the SMPR_BER_INSRT bit is   asserted.
17.6.7 C2 Signal Label Byte Insert
When TMUX_THSC2INS[1—3] = 1 (Tabl e 108 on page 105), the value in TMUX_TC2INS[1—3][7:0] (Table 124 on 
page 118) is  inserted into the C2 byte of the outgoing signal. O the rwise, the associat ed POAC value is inserted 
when TMUX_TPOAC_C2 =  1 (Table 118 on page115 ).  If both TM UX_THSC2INS and  TM UX_TPOAC_C2 = 0, 
then the value inserted depends  on the microprocessor interface block, SMPR_OH_DEFLT (Table 67 on page68 ) 
bit value. If S MPR_OH_DEFLT = 0, then all  0s are in sert e d.  If SMPR _O H _DEFLT =  1,  then all ones are   inserted.
Overhead Bytes Register Control Bits Values
0 (Default Value) 1
J1 T M UX_ TPOAC_J1 (Table 118)SMPR_OH_DEFLT
(00000000/11111111) TPOAC
Data
C 2 TMUX_TPOAC_C2 (Table 118)
F2 TMUX_TPOAC_F2 (Table 118)
F3 TMUX_TPOAC_F3 (Table 118)
K3 TMUX_TPOAC_K 3 (Table 118)
N 1 TMUX_TPOAC_N1 (Table 118)

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
390 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
17.6.8 Path RDI (RDI-P) Insert
When TMUX_THSRDIPINS = 1 (Table 1 08 on page 105), then data from TMUX_TRDIPINS[1—3][2:0] (Table 114 
on page110 ) is written into the corresponding three ST S-1 G1  byte output bits (G1[3:1]). For STS-3  mode, each 
STS-1 signal carries   its own G1 value. For S TM-1 mode, only TMUX_TRDIP INS1[2:0 ] is writte n into the first 
STS-1 loc ati on. When TMUX_THSRDIPINS = 0, hardware insert is enabled f or RDI-P insertion. Each defect contri-
bution to the RDI-P outgoing code  can be inhibited. There are two modes supported for path RDI insertion. One 
mode conforms to the earlier one-bit version of the standa r d . T he  ot her mode, enhanced RDI-P mode, uses a 3-bit 
RDI- P cod e  and conforms to the current version of t he standard. When TMUX_TEPRDI_MODE = 0 (Table 110 on 
page 109) , the TM UX sends a 3-bit code that conforms to the earlier 1- bit  version of the s tandards. If 
TMUX_TEPRDI_MODE = 1, the TMUX will send a 3-bit code conforming to the current enhanced path RDI encod-
ing. Note that for non-enhanced RDI-P mode, the relevant defects are AIS-P and LOP-P. For enhanced RDI-P 
mode, the relevant defects are AIS-P, L OP-P, PLM-P, and UNEQ-P. 
When  a failure condition exists that will cause RDI-P to be generated vi a hardware, the generation of RDI-P must 
last for at l eas t 20 frames before cleari ng, even if the original failure cause has cleared in less  than 20 frames.
Table 532 desc r ibes the encoding of the path RDI  defects.
Table 532. RDI-P  Defects f or Enhanced RDI-P Mode
The TMUX pro vi des a protection s wi tch MUX for RDI-P i nsertion.  The MUX is controlled by TMUX_TPREIRDISEL 
(Table 107 on page 103). If TMUX_TPREIRDI SEL = 1, then the RDI-P v alue f or insertion is tak en from the value on 
the protection board rather than from the receive side of the same TMUX. 
17.6.9 REI-P: G1(7:4) Insert
Four bits of the G1 byte G1(7:4) are al l ocated for use as path remote error indication (REI). For STS-1 signals and 
for STM-1 signals , these bits   convey the coun t (in the range of 0 to 8) of interleaved bit blocks that have been 
detected in error by th e BI P-8 ( B3) dete ctor on the received signal. 
The automatic insertion of path REI can be inhibited on an STS-1 basis by programming the corresponding register 
bits TMUX_TPREIIN S[1:3] (Table 115) to 1. For STM-1 mode, o nly TMUX_ TPREIINS[1] is relevant. If the register 
bit(s) TMU X_TPREIINS[1:3] are programmed to 1, then one e rror is inserted into the G1 byte for that particular 
STS-1(s) each time the microproces s or interface block SMPR_BE R _I NSRT (Table 65 on page66 ) bit is asserted.
The TM UX provi des a protection swit ch MUX for REI-P inse rtio n. Th e MU X is controlled b y TMU X_TPREI RDIS EL  
(Table 107 on page 103 ). If TMUX_TPREIRDISEL = 1, then the REI- P value f or  insertion is taken from the value on 
the protection board rather than from the receive side of the same TMUX. 
G1 Triggers
Bit 3Bit 2Bit 1
0 0 0 No defects (nonenhance d RDI-P  mode).
0 0 1 No defects (enhanced RDI-P mode).
0 1 0 LCD-P, PLM-P (LCD-P not supported in Super Mapper).
0 1 1 No defects (nonenhance d RDI-P  mode).
1 0 0 AIS-P, LOP -P (nonenhanc ed RDI-P mode).
1 0 1 AIS-P, LOP-P (enhanced RDI-P mode).
1 1 0 T IM-P,  UNEQ-P  (enhanced RDI-P mode). 
1 1 1 AIS-P, LOP -P (nonenhanc ed RDI-P mode).

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
391Agere Systems Inc.  
17 TMUX Functional Description (continued)
17.6.10 F2 B yte Insert
When TMUX_THSF2INS = 1 (Table 108 on p age 105), the v alue in TMUX_TF2INS[1—3][7:0] (Table 114 on 
page 110) is  inserted into the outgoing signal. Otherwise, the as s ociated PO AC value is inserted when  
TMUX_TPOAC_F2 = 1 (Table 118 on page115 ). If b oth TMUX_THSF2INS and TMUX_TPOAC_F2 = 0,  then the 
value inserted depends on the value of microprocessor interface block  SMPR_OH_DEFLT (Table 67 on pag e68) 
bit. If SMPR_OH_DEFLT  = 0, then all 0s are inserted.  If SMPR_OH _DEFLT = 1, then all ones are inserted.
17.6.11 H4 Insert Control
A 4-byte sequence (0, 1, 2, and 3) will be inserted into the out goi ng H4 by tes. Note that the assertion of pi n TLSV1 
(pin AB3) occurs afte r the J1 byte(s) during the frame where the H4 count equals one.
17.6.12 F3 B yte Insert
When TMUX_THSF3INS = 1 (Table 108), the value in TMUX_TF 3INS[ 1—3][7:0 ] (Table 114 on page110 ) is 
inserted in to the outgoing signal. Otherwise, the associated POAC value is inserted when  T MUX _TPOAC_F3 = 1  
(Table 118 on page 115). If both  TM UX_THSF3INS and TMUX_TPOAC_F3 = 0, then the value inserted depends 
on the value of mi croprocessor interface block SMPR_OH_DEFLT (Table 67 on page68 )  bit.  If SMP R _ O H_ DE F LT 
= 0, then all 0s  are inserted. If SMPR_OH_DEFLT = 1,  then all ones are inserted.
17.6.13 K3 Byte Insert
When TMUX_THSK3INS = 1 (Table 108 on page105 ), the value in TMUX_TK3INS[1—3][7:0]  (Table 114) is 
inserted in to the outgoing signal. Otherwise, the associated POAC value is inserted when  T MUX _TPOAC_K3 =   1  
(Table 118 on page 115).  If both TMUX_T HSK3INS and TM UX_TPOAC_K3 = 0, then the value inserted depends 
on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit. If  S MPR_OH_DEFLT = 0, then all 
0s are inserted. If SMPR_O H_DEFLT = 1, then all ones are inserted.
17.6.14 N1 Byte Insert
When TMUX_THSN1INS = 1 (Table 108 on page 105), the value in  TMUX_ TN1INS[1—3][7:0] (Table 114 on 
page 110)  is inserted into the outgoing signal.  Otherwise, t he associated POAC value is inserte d when  
TMUX_TPOAC_N1 = 1 (Table 118). If both TMUX_THSN1INS and TMUX_TPOAC_N1 = 0, then the v alue inserted 
depends  on the value of microprocessor interface block  SMPR_OH_DEFLT (Table 67 on page68 ) bit. If 
SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
17.6.15 MSP 1 + 1 Payload Switch 
For the working transmit high-speed data output (THSDP/N, pins AF9/AE9), it is possibl e to sele ct the norm al 
transmit path low-speed data by setting TMUX_ TPSMUXSEL2 = 0 (Table 106 on p age 103) or the receive-si de 
protecti on input data by sett ing TMUX_TPSMUXSEL2 = 1.  Note that if the receiv e-side protect ion inpu t is selected, 
then the local clock and frame sync  are generated based on the receive-sid e pr otection inputs as well.
To c reate the transmit high-speed protec tion out p uts (TPSD155P/N and TPSC155P/N; pins  AF13/AE13 and 
AC1 2/AD13),  i t is possible to  select th e normal tran smit path low-speed input data with TMUX_TPSMUX SEL 3 = 0 
(Table 106 on page 103) or the rece ive-side working inputs with  TMUX_TPSMUXSEL3  =  1. 
Note: Clocks and t im ing signals are select ed by T MUX_TPSMUXSEL3 as well as the parallel data.
17.6.16 Transmit Tr ansp ort Overhead  Access Channe l (TTOAC)
The TMUX provides a transmit transport over head access  channel (TTOAC) to provision the TOH portion of the 
outgoing  frame. The TTOAC channel sup ports   three modes  of operati on based on values in 
TMUX_TTO AC_D13MODE and TMUX_TT OAC_D412MODE (Table 117 on page113 ).

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

392 Agere Sy stem s Inc.

17 TMUX Functional Description (continued)

The TTOAC channel cons ists of the following signals:

■A data signal re ceived by the TMUX in the transmit direction (TTOACDATA, pin AE2). The dat a bytes per fr ame

received depend on t he values of TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See Table 533

below.

■A clock signal sourced by the T M UX (TTOACCLK, pin AB6). The clock frequency depends on the values of

TMUX_T TOAC_D13MODE and TMUX _TTOAC_D412M ODE. S ee Table 533 below.

■An 8 kHz synchronization signal (TTOACSYNC, pin AF3) is s ourced by the TMUX. This sync signal is normally

low; during the last clock period o f each frame, coincident with the least significant bit of the last byte, th e sync

signal is high.

Table 533. Transmit TOAC Modes

Transmit TOAC—DCC1 through DCC3 M od e. In this mode, DCC bytes 1 to 3 are received serially on the data

pin. The clock rate is 192 kHz. The data bytes are received MSB first, and the sequence of data bytes is DCC1,

DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes. The frame repetition rat e is 8 kHz.

Transmit TOAC—DCC4 thro ugh DCC12 Mode. In this m ode, DCC by tes 4 to 12 are received serially on the data

output. Th e clock rate is 5 76 kHz. The data bytes are receive d MSB first, and the sequence of data bytes is DCC4,

DCC5, DCC6 , DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. T he data signal is partitioned into frames of

9 bytes. The frame repetition rate is 8 kHz.

Transmit TOAC—Ful l TOH Access Mode. In t his mode, where TMUX_TTOAC_D13M ODE = 0 and

TMUX_TTOAC_D412MODE = 0 (Table 117 on page113 ), the data signal (TTOACDATA, pin A E2) is partitioned

into frames of 81 bytes. The frame repetition rate is 8 kHz. Each b yte consists of 8 bits that are transmitted/receiv ed

most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of

the previous frame. The remaining 7 bits of this byte are not specified.

Bytes shown in Table 534 summarize the access capabilities of the transmit TOAC. This table describes the possi-

ble bytes in the o utgoing frame that can be provisioned from the values on the TOAC c hannel. There are additional

mode bits described in Table 535 that must be programmed to allow inserti on from the TOAC c hann el. Bytes indi-

cated in b old type below are not specified in the standard, but are available for insertion into the outgoing frame via

the register bit, T MUX_TTOA C_AVAIL (Table 117). An X in Table 534 indicates bytes that are don’t care s; the val-

ues of these bytes in the outgoing transmit frame are not related to the values on the TTOAC channel.

Table 534. Transmit Transport Overhead Byte Full Access Mode

TOAC Mode TMU X_ TTOAC_

D13MODE Value TMUX_TTOAC_

D412MODE Value Dat a Bytes per

Frame Cloc k Rate

DCC1—DCC3 1 X 3 192 kHz

DCC4—DCC12 0 1 9 576 kHz

Full TOH mode 0 0 81 5.184 MHz

OH ParityXXXXXXXX

XB1-2 B1-3 E1 E1-2 E1-3 F1 F1-2 F1-3

D1 D1-2 D1-3 D2 D2-2 D2-3 D3 D3-2 D3-3

XXXXXXXXX

XXXXK1-2K1-3XK2-2K2-3

D4 D4-2 D4-3 D5 D5-2 D5-3 D6 D6-2 D6-3

D7 D7-2 D7-3 D8 D8-2 D8-3 D9 D9-2 D9-3

D10 D10-2 D10-3 D11 D11-2 D11-3 D12 D12-2 D12-3

S1 Z1-2 Z1-3 Z2 Z2-2 X E2 E2-2 E2-3

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
393Agere Systems Inc.  
17 TMUX Functional Description (continued)
Table 535 summarizes the insertion options  for the specified overhead bytes f or TOAC in full TOH  access  mode. 
The TMUX  allows a default value (all zeros if m icroprocessor inter face block SMPR_OH_DEFLT = 0 (Table 67 on 
page 68), and all ones  if SMPR_OH_DEFLT = 1 ) to be inserted on the corresponding TOAC va lue. All control sig-
nals are active-high.
Table 535. TTO AC Contr ol Bits in  F ull Access Mode
An event indication must be provided to indicate parity errors for the TOAC channe l. O dd or even pari ty is checked 
depending on TMUX_TTOA C_OEPMON (Table 117 on page 113);  0 selects odd parity and 1 selects even parity. A 
par ity error is reported in s t atu s register bit TMUX _TTOAC_PE (Table 80 on pag e78), and the interrupt  is 
maskable with TMU X_T TOAC_PM (Table 84 on page87 ).
17.6.17 Sync Status  Byte (S1) I nsert
When TMUX_THSS1INS = 1 (Table 107 on page 103), the v alue in TMUX_TS1INS[7:0] (Table 112 on page 110) is 
inserted in to the S 1 byte of the outgoing signal; otherwise, the as sociated TOAC value is in serted when 
TMUX_TTOAC_S1 = 1 (Table 117 on pag e113). If both TMUX_T HSS1INS and TM UX_TTOAC_S1 are a logic 0, 
then the value inserted depends on the value of the mi croprocessor  interface block SMPR_OH_DEFLT (Table 67 
on page68 ) bit. If  S M PR_OH_DEFLT =  0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are 
inserted.
17.6.18 REI-L: M1 Inser t
For S TS- 3/ ST M-1 modes, the M1 by t e is  all oc ated for use as a line remote error indication (R EI). For STS-1, bits 0 
to 3  of the M0 byte are u sed . The M0 or M1 bytes   co nvey  the count of interleaved bi t bl ocks that have been 
detected in error by the line BIP-8 (B2) detec tor on the received signal.
This function can be inhibited by asserting TMUX_THSLR EIINH (Table 107 on page103 ). A  bit error in the M 0/M 1 
byte can be inserted under user con tr ol. When TMUX_TLREIINS  (Table 115 on page112) is asserted the c orre-
sponding M0 o r M1 byte will indic at e one error each time the mic roprocessor interface bl ock SMPR _BER_INSRT 
(Table 65) bi t is  asserted.
T he TMUX provides a p rote ction switch MUX for REI- L insertion , c ontr oll ed by  TMUX_TLREIRDISEL ( Table 107). 
If TMUX_TLREIRDISEL = 1, then the REI-L value for insertion is taken from the value on the protection board 
rather than from the receive side o f the same TMUX.
17.6.19 APS Value an d K2  Insert Co ntrol Parameters
Whe n TMU X_ T H SAPSINS = 1 (Table 107), the K1 byte and the fiv e m ost significant bi ts of the K2 by te are written 
from TMUX_TAPSINS[12:0] (Table 113). When TMUX_THSA PSINS = 0, ei ther all  0s or all ones will be written, 
depending on the val ue of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit. 
Overhead Bytes Register Control Bits Value of the Register Control Bits
0 (Default Value) 1
E1 TMUX_TTOAC_E1 (Table 117)SMPR_OH_DEFLT
(00000000 or 11111111) TOAC Da ta
F1 TMUX_TTOAC_F1 (Table 117)
D1—D3 TMUX_ TTOAC_D1TO3 (Table 117)
D4—D12 TMUX_TTOAC_ D4TO12 (Table 117)
S1 TMUX_TTOAC_S1 (Table 117)
E2 TMUX_TTOAC_E2 (Table 117)
All remaining bytes 
in Table 534 TMUX_TTOAC_AVAIL (Table 117)

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
394 Agere Sy stem s Inc.
 
17 TMUX Functional Description (continued)
An APS babbling test is con t rol led with T M U X_TAPSBABINS  (Table 116 on page113 ).  Se tting 
TMUX_TAPSBABINS = 1 forces the K1[7:0], K2[7:3) to an in consistent state; no three consecutive values are con-
tinuously the same.
When the transmit K2 software insert bit  TMUX_THSK2INS  = 1 (Tab l e 107 on page103 ), data from bits 
TMUX_TK2I NS[2:0]  (Tab l e 113 on page110 ) is written into the K2[2:0] output bits. When TMUX_THSK2INS = 0, 
hardware insertion of  RDI-L is enabled.
17.6.20 Criteria for Insert Line RDI
Hardware inser tion of l ine RDI is generated using the following equation. Each de fect contri bution to line RDI can 
be individually inhibited.
(TMUX_RILOC AND TMUX_TRILOC_LRDIINH) OR
(TMUX_RHSLOS AND TMUX_T RLOS_LRD IINH) O R
(TMUX_RHSLOF AND TMUX_TRLOF_LRDIINH) OR 
(TMUX_RHSOOF AND TMUX_TR O OF_LRDIINH) OR 
(TMUX_RLAISMON AND  T MU X_TRLA I SMON_ LRDIINH) OR 
(TMUX_RHSSF AND TMUX_TRS F_LRDIINH) OR
(TMUX_RHSSD AND TMUX_TRSD_LRDIINH)
When a failure condition exists that will cause RDI-L to be generated, the generation of  RDI-L mu st last for at least 
20 frames before clearing, even if the orig inal failure caus e has cleared  in less than 20  frames.
The TMUX provides a protection switch  MUX for RDI-L insertio n. The MUX is controlled by TMUX_TLREIRDISEL 
(Table 107). If TMUX _TLREIRDISEL = 1,  then the RDI-L value for insertion i s taken from the value on the protec-
tion board rather than from the receive side of the same  TM UX.
17.6.21 Line AIS Generation
Line AIS is sp ec ifi ed as all ones in the entir e STS/STM signal befor e scrambling,  excluding t he s ection overhead. 
Line AIS can be g enera ted by setting TMUX_ T HSLAISINS =  1 (Table 107).
17.6.22 B2 BIP-8 Calculation and Insert
The  B2 byte is allocated for a line overhead er ror monitoring function. This function will be a  bit interleav ed parity-8 
code (BIP-8 )  us ing even pa rity. The BI P -8 is computed before scra mbling, over al l the bits  of  the previous  STS-1 
frame (except for the 9 bytes of s ec ti on overhead) and is placed in byte B2 of the current frame also before  scram-
bling.
A bit  error rate can be inserted  on any B2 byte. When  bit(s) TMUX_THSB2ERRINS[1—3] (Table 115 on page112 ) 
is (ar e)  as ser ted, the corresponding B2 by te is inverted each  time th e mi c roprocesso r interface block  
SMPR _ BER_ I NSR T (Table 65 on page66 ) bit is asserted.
17.6.23 F1 B yte Insert
When TMUX_THSF1INS = 1 (Table 107 on page 103), the v alue in TMUX_TF1INS[7:0] ( Table 112 on page 110) is 
inserted into the F1 byte of the outgoing signal. Otherwise , the ass ociated TOAC value is inserted when 
TMUX_TTOAC_F1 = 1 (Table 117 on page113 ). If b oth TMUX _THSF1INS and TMUX_T TOAC_F1 = 0, then the  
value inserted depends on the value of microprocessor interface block  SMPR_OH_DEFLT (Table 67 on page 68) 
bit. If S MPR_OH_ DEFLT = 0 ,  th en al l 0s are inserted. If SMP R_O H_DEFLT =  1,  then all ones  are inserted.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
395Agere Systems Inc.  
17 TMUX Functional Description (continued)
17.6.24 B1 Generate and Error Ins e rt
The  sec ti on bit interleaved parity c ode (BIP-8)  byte (even parity) is used to check for transmis si on errors over a 
section. Its value is cal culated over all  bits in the previous frame a fter scrambling and placed in the B1 byte of time 
slot 1 before scr amblin g.
A bit error rat e ca n be inserted on th e  B1 byte. When TMUX _THSB1ERRI NS = 1 (Table 115 on pag e 112), the B1 
by te  is inverte d each time the m icroproc es s or interface block SMP R_BER_INSRT (Table 65 on page66 ) bit is 
asserted.
17.6.25 Scrambler
The outgoing frame wil l be scrambled with t he fram e synchronous scrambler of  length 127 and generating polyno-
mial x7 + x6 + 1. The entire STS/ST M sign al will be scrambled except for the first row of overhead. The scrambler 
will be set to 1111111 on the first byte following the last overhead byte in the first row.
For test pu rposes, the scrambler will be disabled whe n  TMUX_TH SSCR = 0 (Table 106 o n page 103).
17.6.26 J0 Insert Control
A 16-byte sequence stored in TMUX_TJ0DINS[1—16][7:0] (Table 133 on page121 ) will be inserted into the outgo-
ing J0 byte if TMUX_THSJ0INS = 1 (Table 107 on pag e103). If TMUX_THSJ0INS = 0, then the value inserted 
depends  on the value of microprocessor interface block  SMPR_OH_DEFLT (Table 67) bit. If SMPR_OH_DEFLT = 
0, t hen all 0s are inserted. If SMPR_OH_ DEFLT = 1, then all ones are inse rted.
17.6.27 Z0-2, Z0 -3 Insert Control
The 2 bytes, Z0-2 and Z0-3, that follow J0 are  not scrambled. If TMUX_THSZ0INS = 1 (Table 107), then the values 
stored in TMUX_TZ02INS[7:0] (Table 111 on pag e110) and TMUX_TZ03 INS[7:0] (Table 111) will be inserted. If 
TMUX_THSZ0INS = 0, then the value inserted depends on the value of  microprocessor interface block 
SMPR_OH_DEFLT bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all 
ones are inserted.
17.6.28 A2 Error Insert
The TMUX allows, under s oftware control, from 1  to 32 cont inuo u s  frames to have an inv erted A2-1 (0x28 to 0xD7) 
pattern in the outgoing frame. The value in TMUX_TA2ERRINS[4:0] (Table 106) specifies t he number of frames to 
insert errors into whil e assertion of microprocessor interface b lock, SMPR_BER_INSRT bit, starts the error inser-
tion process.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
Agere Sy stem s Inc.
 
SPE Mapper Functional Description
Ta ble of Conte nts
Contents Page
SPE Map per Functional Description ................ ... ......................... . ......................... . ........................................ 396
1  In troduction ............................................................................................................................................. 398
2  Features  ................................................................................................................................................. 398
3  SPE Mapper Functional Block Diagrams  ........................ ......... .............. . ................................ . .............. 399
4  TUG-2 to AU-3 /STS-1 SPE Mapping (Used in North American Systems) ............................................. 402
5  TUG - 2 to TUG-3 Mapping (Used  in ITU/ETSI S tandard Based Systems )   .............................. .......... ... .. 40 2
6  DS3 t o AU-3/STS-1 SPE Mapping (Used in 
Telcordia
/
ANSI
 Standards Based Systems) ..................... 403
7  DS3 t o TUG-3 Mapping (Used in ITU/E TS I Standard Based  Systems) .................................. .......... ... .. 40 3
8  SPE  Mapper Basic Configuration  ........................................ .......... ... ...................................................... 403
9  DS3 C onfiguration .................................................................................................................................. 403
9.1 DS3 M13 ...................................................................................................................................... 404
9.2 D S3 Loopback  Channel  .................................................. ....... ....... ....... ........................................ 404
9.3 DS3 Clear  Channel from External Pins ........................................................................................ 404
10  Phase Detector for External DS3 PL L .................................................................................................. 404
11  Serial STS-1 SPE Channel (NSMI)  ... ......................... ....... .................................... ... ............................ 405
12  TMUX  Interface to the SPE Mapper ...... ... ......................... .......... ... ......................... ....... ...................... 406
13  PATH Termination Block ...................................................................................................................... 406
13.1 Pointer Inte rpretation Block ....................................................................................................... 407
14  SP E Mapper Receive Direction Requirement s .................. ..... .............. ..... ... ........................................ 410
14.1 Loss of  Clock and Loss of Sync  Monitors  . .................. . ............. ..... ...................... .................. ... 411
14.2 J1 Monitor .................................................................................................................................. 411
14.3 B3 BIP-8 Check ......................................................................................................................... 412
14.4 Signal Label C2 Byte Monitor ............. .......... ....... ....... ....... ....... ....... .......... ....... ....... ....... ........... 412
14.5 Path User Byte  F2 Monitor ........................................................................................................ 413
14.6 Path User Byte  F3 Monitor ........................................................................................................ 414
14.7 N1 Monitor ................................................................................................................................. 414
14.8 K3 Byte Monitor ......................................................................................................................... 415
14.9 AIS-P and RDI-P Det ec t .................... ..................... ..... . .................. .......................... ................. 415
14.10 REI-P Detect  ........................................................................................................................... 416
14.11 S ignal Degrade B ER Algorithm .......................... ... ......................... . ......................... ..... .......... 416
14.12 Signal Fail BER Algorithm ..................... ............ ............................ ..... ..... ................ ................ 417
14.13 POAC Dro p ............................................................................................................................. 418
14.14 Insertion of AIS-P .................................................................................................................... 419
15  Transmit Direction (to SONET/SDH Line)  ............................................................................................ 420
15.1 PATH Insertion Block ................................................................................................................ 420
15.2 Loss o f Clock and Loss of Sync Detectors .................. . .................. ..................... . .................. ... 421
15.3 J1 Byte Insert  ............................................................................................................................ 421
15.4 B3 BIP-8 Calculation and Insert ................................................................................................ 421
15.5 C2 S ignal Label Byte Insert ............................. ....... ..... ....... ....... . ................................ . .............. 421
15.6 REI-P G1(7:4 ) Insert .................................................................................................................. 421
15.7 Path RDI (RDI-P) Insert  ............................................................................................................. 422
15.8 F2 Byte Insert ............................................................................................................................ 422
15.9 H4 Insert Control ....................................................................................................................... 422
15.10 F3 Byte Insert .......................................................................................................................... 422
15.11 K3 Insert Control Parameters .................................................................................................. 422
15.12 N1 Insert Control Parameters  .................................................................................................. 423
16  POAC Insert  ......................................................................................................................................... 423
17  AIS Path Generation ............................................................................................................................. 424

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
397Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
Table o f Conten ts (continued)
Figures Page
Figure 30. S PE  Mapper Block with Connections to External Pins and Other Blocks in the Device ..................... 399
Figure 31. Basic Functional Flow of the SPE Mapper Transmit Section................................................. ......... .... 400
Figure 32. Basic Functional Flow of the SPE Mapper Recei ve Section...................... ............. . ................ ........... 401
Fig ure 33. STS-1 NSMI Receive Operation ......................................................................................................... 405
Fig ure 34. STS-1 NSMI Transmit Operation ........................................................................................................ 406
Figure 35. Receive Direction Path Terminatio n Block.......................................................................................... 407
Fig ure 36. Pointer Interpretation State Dia gram................................................................................................... 408
Fig ure 37. Transm it Directio n Path Insertion Block.............................................................................................. 420
Tables Page
Table 536. J1 Monitor ..........................................................................................................................................412
Table 537. STS Signal Label Defect Conditions ................ .......... ......... ..... .......................... ............................... 412
Table 5 38. C2MON Processing ........................................................................................................................... 413
Table 539. F2 Monitor ......................................................................................................................................... 414
Table 540. F3 Monitor ......................................................................................................................................... 414
Table 5 41. N1 Monitor ......................................................................................................................................... 414
Table 542. K3 Monitor ......................................................................................................................................... 415
Table 5 43. AIS-P a nd RDI-P D etect .................................................................................................................... 415
Table 544. STS - 1 P-REI  Interpretation ................................................................................................................416
Table 5 45. Signa l Degrade Parameters ........................ .................. . ......................... ..... ... .................................. 417
Table 546. Signal Fail  Parameters ...................................................................................................................... 418
Table 547. P ath Overhead Byte Access .............................. ................... ....... ............ .............. ............................ 419
Table 548.  RDI-P Defects fo r Enhanced  RDI-P M ode  .. ................................ ................. .............. .......................422
Table 549. P ath Overhead Byte Access—Transmit Direction ............................................................................. 423
Table 550. TPOAC Control Bits  .......................................................................................................................... 424

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

398 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

18.1 Introductio n

This section d e scribes the fu n ctions of the SPE mapper block .

The SPE mapper is highly configurable; it can operate in two different modes, as an AU-3/S TS-1 mapper or as a

TUG-3 mappe r. In both mo des, it can map/demap da ta from/to either the VT mapper b lo ck , the M13 MUX/deMUX

block, the DS3 c lear channel, or t he D S3 loopback channel.

The SPE mapper supports numerous autom ati c monitor ing functions. It ca n provide interrupts to the control sy s-

tem, or it c an be operated in a polled mode.

Additionally, this block has a built-in auxiliary channel known as the path overhead acc ess channel (POAC). This

channel is mainly used for path overhead insertion and drop functions.

18.2 Features

■The SPE mapper accepts/delivers T UG-2 data from/to the VT mapper. The TUG-2 data is mapped/demapped

either t o/from an AU-3/STS-1 si gnal fo r t he North Am erican digit al systems or to/from a TUG-3 signal for the

European digital systems.

■Flexibility down to TUG-2 level is provided for choosing which TUG-2s (betwee n 1 and 7) are mapped into which

TUG-3s (between 1 and 3) f or generating STM-1 signals. Similarly, any TUG-2s (up to 7) may be dropped/termi-

nated from the 21 TU G-2s of an STM-1 signal.

■The SPE ma pper a ccep ts/ de liv ers DS3 data fr om/t o the M13 MUX/d eMUX. Th e DS3 dat a is mapped/demapped

either t o/from an AU-3/STS-1 si gnal fo r t he North Am erican digit al systems or to/from a TUG-3 signal for the

European digital systems.

■The SPE mapper accepts/delivers a clear DS3 signal at 44. 736 Mbits/s rate. T he clear DS3 signal is m apped/

demapped essentially the same way as M13 si gnal d e scribed above.

■The SPE mapper has a DS3 loopback circuit placed f or the functions of demapping and remapping a DS3 signal.

It is particularly usef ul in cases where a DS3 signal mapped as an AU-3/ STS-1 si gnal is needed to b e remapped

as a TUG-3 signal or vice versa.

■The SPE mapper supports a path overhead access channel mo re commonly known as the P O AC channel.

Seven path overhead bytes namely J1, C2, F2, H4, F3, K3, an d N 1 may be inserted /dropped through this chan-

nel. This channel works as the master which means that this channel provides a clock in both transmit and

receive directions and POH data may be inserted by the user on the tran smit side or dropped by the block in the

receive side.

■Path overhead byte B3 (BIP error) generation/detection and programmable BIP-2 bit error rate insertion.

■Programmable clear on read/clear on write registers.

■Sign al fail and signal degrade indicators available to report bit error rates above a certain programmable thresh-

old.

■Capable of detecting /inserting alarm indication si gnals (AIS), remote defect indica tion signals (RDI) and remote

error indication signals (RE I ).

■Numerous monitoring functions provided on a ll the TUG-3 path overhead bytes.

■Supports uni directional path switch ring (UPS R ) applications.

■N1 tandem connection support is provided.

■Complies with GR-2 53-CO RE, T1.1 05, ITU-T G.707, ITU-T G.8 3 1 , G.783, E TS 300 417 - 1- 1.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

399Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.3 SPE M app er Fu nc tiona l Block Diagrams

5-9065(F)

Figure 30. SPE Mapper Block with Connections to External Pins and Other Blocks in the Device

MICRO INTERFACE

SPE

MAPPER

DS3DATAINCLK

DS3DATAOUTCLK

DS3NEGDATAIN

PHASEDETUP

PHASEDETDOWN

DS3NEGDATAOUT

AUTO_AIS,

TPOAC

DS3POSDATAOUT

DS3POSDATAIN

REI DS3

AUTO_AIS

DATA, CLK, SYNC

TRANSMIT

RECEIVE

TELECOM

BUS

CLK, DATA

RPOAC

TRANSMIT

RECEIVE

CLK, DATA

TRANSMIT RECEIVE

TRANSMIT

PATH OVERHEAD

INSERT

POAC CHANNEL

TELECOM

BUS

RDI, REI

MAPPER

TRANSMIT

SECTION

MAPPER

RECEIVE

SECTION

M13

MAPPER

TRANSMIT

SECTION

M13

MAPPER

RECEIVE

SECTION

DS3

CLEAR INPUT

TRANSMIT

PINS

DS3

CLEAR INPUT

RECEIVE

PINS

RECEIVE

PATH OVERHEAD

EXTRACT

POAC CHANNEL

TMUX

RECEIVE

SECTION

TMUX

TRANSMIT

SECTION

DATA, CLK, SYNC

DATA, CLK,

CONTROL

DATA, CLK,

CONTROL

LOOPBACKRDI

TRANSMIT

SECTION

SPE

MAPPER

RECEIVE

SECTION

MISC SIGNALS

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

400 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

5-9066(F)

Figure 31. Basic Functional Flow of the SPE Mapper Transmit Section

TELECOM BUS DATA[7:0], CLOCK, PARITY, SYNC (19.44 MHz OR 6.48 MHz)

TO/FROM TMUX TRANSMIT SIDE

DS3 _EXT_CLK

DS3 POS_DATA

51.84 MHz CLOCK FROM TMUX

51.84 MHz CLOCK, CONTROL FROM TMUX

B3ZS

M13

DS3 DATA

DS3 CLK

DS3 CLK_EN

DS3 INPUT CONTROL &

VT/TU

FIFO

DS3

TUG-2

PATH

TUG-2_DATA

SYNC_V1

CLK_6MHz

MUX

TUG-3 MAPPER

AU-3 MAPPER

MUX

TUG-3 OR AU-3

MUX

MICRO-

C-3

TUG-2

MUX

LOOPBACK_CLK

LOOPBACK_DATA

TX_POACDATA

TX_POACSYNC

TX_POACINH

TX_POACCLKO

PATH OVERHEAD

LOOPBACK_CLK_EN

DS3 NEG_DATA

STS3_TIMESLOT

AU3_TUG3

VT_DS3

AU3_TUG3

VT_DS3

TDS3_BIPOLAR

DS3_SRC_TYPE

VT_DS3

84 x 9 bytes

84 x 9

85 x 9 b ytes

87 x 9 bytes

87 x 9 bytes 87 x 9 bytes

TU11_TU12

TUG2_NO[2:0]

TUG3_NO[1:0] AU3_TUG3

VT_DS3

MPUCLKDS3CLK

TELECOM BUS

OUTPU T (87 x 9 bytes)

CONTROL CIRCUITRY

ADD 1 COLUMN

OF FIXED STUFFING &

TU-3 PTR BYTES

ADD 2 COLUMNS

OF FIXED STUFFING

OVERHEAD

INSERTION

INSERT

POAC CHANNEL

MAPPERMAPPER

DECODE

SERIAL-TO-PARALLEL

CONVERSION INPUT

CONTROL

MAPPED AS

CONTAINER C-3

INTERFACE

CLOCK

bytes

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

401Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

5-9067(F)r.1

Figure 32. Basic Functional Flow of the SPE Mapper Receive Section

TELECOM BUS DATA[7:0], CLOCK, PARITY, SYNC (19.44 MHz OR 6.48 MHz)

FROM TMUX RECEIVE SIDE

DS3 _EXT_CLK

DS3 POS_DATA

51.84 MHz CL OCK, CONTROL FROM TMUX

AUTO AIS SI GNAL FROM TMUX

B3ZS

M13

DS3 DATA

DS3 CLK

DS3 CLK_EN

DS3 OUTPUT CONTROL &

VT/TU

FIFO

C-3

TUG-2

PATH

TUG-2_DATA

SYNC_V1

CLK_6MHz

TUG-3 DEMAPPER

AU -3 DEM A PP ER

TUG -3 OR AU-3

MICRO

C-3

TUG-2

RX_POACSYNCO

RX_POACCINH

RX_POACSINH

RX_POACDATAO

PATH OVERHEAD

DS3 NEG_DATA

STS3_TIMESLOT

VT_DS3

AU3_TUG3

VT_DS3

DS3CLK

VT_DS3

84 x 9 b ytes

84 x 9

85 x 9 bytes

87 x 9 bytes 87 x 9 bytes

TU11_TU12

TUG2_NO[2:0]

TUG3_NO[1:0] AU3_TUG3

VT_DS3

TELECOM BUS

INPUT (87 x 9 BYTES)

CONTROL CIRCUIT RY

REMOVE 1 COLUMN

OF FIXED STUFFING &

TU-3 PTR BYTES

REMOVE 2 COLUMNS

OF FIX ED STUFFING

OVERHEAD

EXTRACTION/

EXTRACT

POA C CHANNEL

DEMAPPER

ENCODER

PARALLEL-TO-SERIAL

CONVERSION OUTPUT

CONTROL

DE MAPPED AS

AS DS3

INTERFACE

CLOCK

bytes

DS3

TERMINATION

POINTER

INTERPRETER

MUX

85 x 9 bytes

VT_DS3

RX_POACCLKO

RX_POACDINH

85 x 9 bytes

VC-3

DS3_OUT_TYPE

DS3_BIPOLAR

PHASE_DET_UP

PHASE_DET_DOWN

DS3 _LOOPBACK_DATA

DS3 _LOOPBA CK_CLK

LOOPBACK_CLK_EN

TUG3MPR_DS3_AIS

MPUCLK

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

402 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

The SPE mapper basically interfaces to three other blo cks within the Super Mapper device:

■The VT mapper.

■ The M13 MUX/deMUX.

■ The TMUX.

The interf ace between the SPE mapper and the VT mapper consists of clock, p arallel data, sync, and control type

interfaces and is compl etely intern al to the Super Mapper device.

The interface be tween th e SP E mapper and t he M13 MUX/deMUX c onsists of a serial clock, serial data, and clock

enable type interface and is also completely intern al to the Super Mapper device.

The interf ace between the SPE mapper and the T MUX consists of the telecom b us and every signal that flows

between these two blocks is also brought in/out through external device pins connected to the telec om bus.

As ou tli ned i n the f eatu res , the SPE mapper can map/demap s even TUG-2 or a DS3 to/from AU3/STS-1 or TUG-3.

Each TUG-2 assembled/disassembled by the VT mapper consist of three TU-12 (E1) or four TU-11 (DS1) virtual

tributaries.

The following is a brief de scription of the supported standards based mappings . For greater details, please refer to

the appropriate standard.

18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems)

A TUG-2 payload capacity, which is 9 rows by 12 columns or 108 bytes, may contain four TU-11s or three TU-12s

byt e interleav ingly multiple x ed.

The 27-byte capacity of a TU-11 is equivalent to thre e-column cap acity in an S TS-1 frame of 125 µs. Four TU-11s

are by te interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a struc ture

of 9 rows by 85 c olumns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly

distributed within the payload. Two columns of fixed stuffing ar e then added to the payload to build the complete

STS-1 SPE frame of 9 rows by 87 columns.

The 36-byte capacity of a TU-1 2 i s equivalent to four-column capacity i n a n S TS-1 frame of 125 µs. T h ree TU-12s

are by te interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a struc ture

of 9 rows by 85 c olumns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly

distributed within the payload. Two columns of fixed stuffing ar e then added to the payload to build the complete

STS-1 SPE frame of nine rows by 87 columns.

18.5 TUG-2 to TU G-3 M apping (U sed in ITU/ETSI Sta ndard Based Systems)

A TUG-2 payload capacity, which is nine rows by 12 columns or 108 bytes, may contain four TU-11s or three

TU-12s byte interleavingly multiplexed.

The 27-by te capacity of a TU-11 is equivalent to three-column capacity in a n STM-1 frame of 125 µs. Four TU-11s

are by te interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG- 3. The TUG-3 has a struc-

ture of nine rows by 86 columns: one column of NPI (null pointer indication) plus fixed stuff ing byte s, one column of

fixed stuffing and the other 84 columns are seven TUG-2s evenly distributed within the TUG-3 payl oad.

The 36-byte capacity of a TU -12 is equivalent to four-column capacity in an STM-1 frame of 125 µs. Three TU-1 2s

are byte interleaving multiplexed into a TUG-2 p ayload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

403Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

The TUG-3 has a st ruct ure of 9 rows by 86 columns: one column of null pointer indication (NPI) plus fixed stuffing

by tes, one column o f fixed stuffing, and the other 84 columns a r e seven TUG-2s evenly distrib uted within the

TUG-3 payload.

18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in

Telcordia

ANSI

Standards Based Systems)

DS3 is an asynchronous signal w ith a rat e of 44.736 Mbits/s. This pa yload with other information bits (total

3.648 Mbits/s) is used to form the cont ainer C-3 (48.384 Mbits/s) which occupies 84 columns of an STS-1 frame.

One colum n of path overhead byt es is added to the C-3 container to make a VC-3. Finally, two columns of fixed

stuffing (column numbers 30 and 59) are added to VC-3 to form an STS-1 SPE (87 columns).

Stuffing (S bits) is used to rate adapt the DS3 payload to the SPE. Nine stuffing S bits are included in t h e C-3 con-

tainer. When no stuffing is used, the STS-1 SPE can accommodate a rate of 44.712 Mbits/s. When all nine stuffing

S bits are use d, the STS-1 SPE can accommodate 44.7 84 Mbits/s. Since the DS3 coming from the M13 has a

nominal rate of 44.736 Mbits/s, stuffing is used f or every third row of an STS-1 frame; or in other words, three S bits

per 125 µs are used for stuffing to achieve the DS3 rate.

18.7 DS3 to TUG -3 Mapping (Used in ITU/ETS I S tandard Based Systems)

DS3 is an asynchronous signal w ith a rat e of 44.736 Mbits/s. This pa yload with other information bits (total

3.648 Mbits/s) is used to form the cont ainer C-3 (48.384 Mbits/s) which occupies 84 columns of an STM-1 frame .

One column of path overhead byt es are added to the C-3 container to make a VC- 3 (85 columns). Now a TUG-3

signal consists of 8 6 col umn s by 9 rows, therefore 3 by tes of TU-3 pointer (H1, H2, and H3 b y t es) are placed on

rows 1 through 3 of the newly added column and fixed s tuffing bits ar e placed on the rem a i ni ng rows. Thus, a

TUG-3 frame of 9 row s by 86 columns is formed. Three TUG-3s are byt e i nterleavingl y multiplexed by the TMU X to

form a n STM-1 signal.

Stuffing (S bits) is used to rate adapt the DS3 pa yload to the TUG-3. Nine stuffin g Sbits are incl uded in the C-3

container. When no stuffing is used, the TUG-3 p ayload can accommodate a rate of 4 4.712 Mbits/s. When all nine

stuffing S bit s are used, the TUG-3 payload can accommodate 44.7 84 Mbits/s . Since the DS3 coming fr om the

M13 has a nominal rate of 44.736 Mbits/s, stuffing is used for every t hird row of a T UG-3 frame; or in other words,

three S bits per 125 µs are used for stuffing to achieve the DS3 rate.

18.8 SP E M app er B asic C onfi gur ation

SPE mapper c onfiguration progr amming is provided through r eg i st e rs SPE_MAP_CTL1—SPE_ M AP_CTL3

(Table 153 on page 140).

When mapping to a STS-3/STM-1 rate, the SPE mapper requires configuration to select one of the three time slots

on the telecom bus that inter f aces the TMUX. The register bits for selection are SPE_TSTS3TMSL OT[1:0] and

SPE_RST S3TM SL OT[1:0] (Table 153).

Selection of AU-3/S TS-1 or TUG-3 mapping is provided through bits SPE_T_AU3_TUG3 and SPE_R_ AU3_TUG3

(Table 153).

TUG-2 (virtua l tributary) or DS3 dat a is selected with b its, SPE_T_AU3_TUG3 and SPE_R_ AU3_TU G3.

18.9 DS3 Con figura tion

The SPE mapper is configured to select the source and destination of the DS3 signals. The configuration is deter-

mined with register bits, SPE_ TDS3S RCTYP[1:0] and SPE_RDS3OUTTYP[1:0] (Table 153). DS3 source/destina-

tion may be selected as loopback, external device pins, or M13.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

404 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

18.9.1 DS3 M13

The SPE mapper is conf igured to/from the M13 MUX/deMUX as the source/destination of data by setting b its,

SPE_TDS 3SR CTYP [1:0] = SPE_RDS 3OUT TYP [1:0] = 00 or 01.

18.9.2 DS3 Loopback Channel

The DS3 loopb ack circuit is pla ce d in the SPE mapper to allow demapping a nd remapping of a DS3 sign al.

When SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 10, the SPE mapper extracts the asynchronous DS3

data and clock from the recei ved payload. T he recovered DS3 is looped back to the transmit path and either

mapped as AU-3/STS-1 SPE signal for the No rt h American digit al systems or mapped as TU G-3 for the Eur opean

digital systems. It is particularly useful in cases where a DS3 signal m apped as an AU-3/STS-1 signal is needed to

be remapped as a T UG-3 signal or vice versa.

18.9.3 DS3 Clear Chan nel from Exte rnal P ins

The SPE mapper is configured for a DS3 signal at 44.736 MHz rate from external device pins by setting

SPE_TDS3SRCTYP[1:0] = SPE_ RDS3OUT TYP[1:0] = 11.

The DS3 data can either be unipolar or bipolar. Unipolar data and clock is selected (device pins DS 3POSDATAIN,

DS3DATAINCLK, DS3POSDATAOUT, and DS3DATAO UTCLK (pins M22, J22, R22, and N22, respect ively)) when

bits SPE_TDS3_BIPOLAR and SPE_RDS3_BIPO LAR = 0 (Table 153). Bipolar data and clock is selected (device

pins DS3POSDATAIN, DS3NEGDATAIN, DS3DATAINCLK, DS3POSDATAOUT, DS3NEGDATAOUT, and

DS3DATAOUTCLK (pins M22, K 22, J22, R22, P22, and N22, respectively)) when bits SPE_TD S3_B IPOL AR and

SPE_RDS3_BIPOLAR = 1.

When bipolar data is selected for the transmit path (SPE_TDS3_BIPOLAR = 1), the data received from the external

pins is expected to be B3ZS encoded. A B3ZS decoder is used to recover the DS3 data prior to being mapped into

a container.

The B3ZS dec oder also checks for bipolar coding violations. Th e SPE mapper contains a counter that increments

on ea ch occu rrence of a receiv ed bi polar cod ing viol atio n (BPV) . It als o monit ors the occurre nce of e xcess iv e z eros

(EXZ ), w hich is def ined as any zero string len gth equal to or greater than three. These are part of the per formance

monitoring counters that can be sampled and simultaneously reset. Their last sampled values are av ailable t hr ough

SPE_BIPOL_CNT[23:0] and SPE_EXZ_CNT[23:0] (Table 160).

When bipolar dat a is sele cted for the receive path (SPE_RDS3_BIPOLAR = 1), the data out from the external pins

will be B3ZS encoded. A single bipolar violation may be inserted in the data when SPE_BIPOL_ERR is asserted

(Table 145).

The clock edge for sampling the tr ans mi t path data (device pin DS3DAT A I NCLK (pin J22)) is sel ected with

SPE_TDS3CLK_ED G E (Table 153).

18.10 Phase Detector for External DS3 PLL

The rece ive sec tion of the SPE mapper has a phase detector circ uit built inside the device. This phase detector cir-

cuit generates the necessary up and down signals (device pins PHASEDETUP and PHASEDETDOWN ( pins V22

and U22, respec tively)) for an external phase-lock loop (PLL) circ uit to generate a smooth DS3 clock at

44.736 MHz rate.

The logic sense of the phas e det ector up and dow n outputs may be i nv erted with bits SP E_PHDETUP_INV

(Table 153) and SPE_PHDETDN_INV, respectively.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

405Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.11 Serial STS-1 SPE Channel (NSMI)

The SPE mapper has the capability of accepting a clear serial STS-1 SPE signal at 51.84 MHz rate. The intent is to

map/demap the netwo r k serial mult iplexed interface (NSMI) interface data.

The receive section of the SPE mapper outputs a serial data at 51.84 MHz rate, a clock enable sign al i nhibited dur-

ing overhead insertion times, and a sync signal whose position within the ST S -1 frame is programmable to a cer-

tain extent (is programmable to occupy any STS- 1 c olumn position (numbers 0 —89) within a fixed row (# 8)),

through bits SPE_R_NSMI_BIT[2:0] (Table 153) and SP E_R_NSMI_CO L[6:0] (Table 153).

The transmit section of the SPE mapper input s seria l dat a at 5 1 .84 MH z ra te , outp u ts a cl o c k enable signal inhib-

ited during ov erhead insertion times and a sync signal whose position within the STS-1 frame is programmab le to a

certain ex tent (is programmable to occupy any STS-1 column position (numbers 0—89) within a fixed row (#8)),

through bits, S PE_T_NSMI_BIT[2:0] and SPE_T_N SMI_COL[6:0] (Table 153).

The STS-1 SPE data is then mapped as AU-3 si gnal for the N orth Am erican d igital systems.

0786(F)(F)

Figure 3 3. STS-1 NSMI Receive Operation

UNUSED

VARIABLE

LINE_RXCLK29

RXDATAEN

RXSYNC (OPTIONAL)

LINE_RXDATA29

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

406 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

0785(F)(F)

Figure 34. STS-1 NSMI Transmit Operation

18.12 T M U X Int er face t o the S PE M apper

The SPE mapper sends/receive s data mapped as an AU-3/STS-1 SPE signal or as a TUG-3 signal to/from the

TMUX. The inte rface required f or this exchange of data, clo ck, and control signals is call ed the high-speed tele com

bus. The hig h-speed telecom bus is accessible from ex ternal pins s o that the TMUX can send/receive data to/from

other external Super Mapper devices in the system. T he TM UX can byte interleavingly multipl ex th ree S TS-1s or

three T UG-3 s ignals, receiving through the t elecom bus, to form one STS-3 or STM-1 signal, res pec tively.

The high-speed telecom bus cons ists of a byte-wide data bus running at 19.44 Mbits/s for ST S- 3/ STM-1 mode, or

6.48 Mbits/s for STS-1 stand-alone mode. It also consis ts of a parity bit line, a clock line which is 19.44 MHz or

6.48 MHz depending on STS-3/STM-1 or STS-1 mode, respectively; one sync line and two sync control lines. The

sync l ine out puts the J0, J1, and V1 time slo t si gnals of the STS-3/STM-1 frame and the two sync control signals

distinguishes between the three sync bytes. The sync signals are used to synchronize the byte counters in the SPE

mapper, and the infor mation is also passed along to the VT mapper fo r synchronizing the V1 counters.

The TMUX also provides through the external pins one 51.84 MHz serial clock and one clock cont r ol signal which

synchronizes the 51.84 MHz to the J0 byte o f t he STS-3/STM- 1 frame. This serial clock is re q uired for the M13

MUX/deMUX because of its serial m ode of working.

In the case where the SPE mapper has to drive the telecom bus in the transmit side, there is a 3-state control sig-

nal (acti v e-hi gh) which is an outp ut from the SPE m apper. This si gnal enabl es the 3-state drivers on the high-speed

telecom bus at the time period when the clock is low.

18.13 PATH Term inatio n B lock

The path termination block of the SPE mapper is shown below. The block consists of a pointer interpreter which

monitors the T U-3 pointer bytes H1, H2, and H3, and interprets t he beginning of the path overhead bytes for the

TU G-3 frames. Aft er mo nit orin g and t erminating the path overhead b ytes, the TUG-3 payload is passed on to the

output blocks.

UNUSED

VARIABLE

LINE_TXCLK29

TXDATAEN

TXSYNC (OPTIONAL)

LINE_TXDATA29

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

407Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

5-9068(F)

Figure 35 . Receive D irection Path Termination Block

18.13.1 Pointer Interpretation Block

The TUG-3 pointer int erpreter logic block perfor ms all neces s ary fu nction s t o support TU -3 p oi nter interpretation.

The following features are impl emented:

■ The pointer interpreter consists of the following states:

— LOP-T U3—lo s s of p o inter

— AIS-TU3—TU G-3-AIS (all ones in H1 and H2)

— NDF—NDF enabled (1001, 0001, 1101, 1011, 1000)

— NORM—normal (disabled NDF, normal pointer)

— INC—increment (i nvert ed I bits)

— DEC—decrement (inverted D bits)

The SPE mapper includes ev ent or change of state indicators for pointer interpreter states except the NORM state.

States NDF, DEC, and INC are reported with event st atus bits SPE_RNDFE (Table 146 on page134),

SPE_RDECE (Table 146), and SPE_RINCE (Table 146), respectively. States AI S and LOP are r eported with

change of state (delta) status bits SP E_RAISD (Table 146) and SPE_RLOPD (Table 146), respectively. Interru pts

for each event o r delt a state may be mask ed wit h bits SPE_RNDFM, SPE_RDECM, SPE_RINCM, SP E_ RAISM,

and SPE_RL OPM (all in Ta ble 147 on page 136 ).

INSERT

B3 K3 AIS-P G1

B3 K3 G1 G1N1C2

POAC G1

J1F3

H1, H2, H3 POINTER

PATH

POAC DATA

TUG-3 D ATA VC-3 DATA

TUG-2 DATA

PAYLOAD DATA TO OUTPUT BLOCKS

MUX

MONITOR INTERPRETER

MONITOR F3

MONITOR C2

MONITOR J1

MONITOR N1

MONITOR BIP N

CHECK APS

MONITOR RDI-P

DETECT REI-L

DETECT

AIS-P

TERMINATE

REI

COUNTER

DROP

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

408 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

5-9007(F)

* Thi s st ate di ag r am is ba sed on the E TS 417 -1- 1 poin ter inte rpret a tion sta t e di ag ra m (F ig ure B. 1 ). Tra ns iti on s of eig ht in v al i d pointers from the

INC, DEC, and NDF states into the LOP state have been added.

Figure 3 6. Pointer Interpretation St ate D i agra m

■The pointer inte rpreter transitions into the LOP-TU3 state based on the following conditio ns:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames

(determined by the value program med in bits SPE_CNTDLOPCNT[1:0] (Table 149)), then LOP-TU3 is de-

clared.

— Inv alid pointer valu e s. I f the number of consecutive frames (determi ned by the value programmed in

SPE_CNT DLOPCNT[1 :0] ) are recei ved w ith a poi nter t hat i s not a nor mal va lue, NDF, AIS-TU 3, incremen t, or

decrem ent , then LO P-TU3 is declared.

■ The pointe r interpreter transitions out of the LOP-TU3 state based on the fo llowing conditions:

— Fol lowing thr ee consecutive fram es with all ones in the H1 and H2 bytes the pointer interpreter transitions from

the LOP-TU3 state into the AIS-TU3 s tate.

— Following three new consecutive, consistent, valid pointers the pointer interpret er tran sitions from the

LOP-TU3 state into the NORM state.

— The p ointer interpreter

will not

transition fro m the LO P-TU3 state into the NDF state.

■ The pointer interpreter transitions into the AIS-TU3 state based on the following conditions:

— Following three consecut ive frames with all ones in the H1 and H2 byte s AIS-TU3 is declared.

■ The poi nter interpreter trans itions out of the AIS-TU3 state based on the following c onditions:

— Following three new consecutive, consistent, valid pointers the pointer interpreter transiti ons from the AIS-TU3

state into the NO RM state.

— Fo llowi ng the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]) the pointer interpreter transitions from the AIS-TU3 state into the LOP-TU3 state.

— If NDF is enabled on the incoming H1 an d H2 bytes, the pointer interpreter transitions from the AIS-TU3 state

into the NDF state.

NORM

DECINC

NDF

AISLOP

FROM ALL STATES

8 INVALID POINTERS

FROM ALL STATES

3 NEW POINTERS

INCREMENT DECREMENT

8 NDF ENABLE

NDF ENABLE

NDF

3 ANY 3 ANY

3 NEW POINTERS

3 ANY POINTERS

3 NEW POINTERS

8 INVALID

8 INVALID POINTERS*

INDICATION INDICATION

3 AIS INDICATIONS ENABLE

ENABLE

POINTERS POINTERS

POINTERS ENABLE

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

409Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

■The pointer inte rpreter tran sitions into the NDF state based on the follo wing conditions:

— If NDF is enable d on the incoming H1 and H2 bytes, t he pointer interprete r tr ansition s from the NORM, N D F,

AIS, INC, and D EC states into the NDF state.

■ The pointer interpreter transitions out of the NDF state based on t he following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames

(determined by the value programmed in SPE_CNTDLOPCN T[1:0] (Table 149)), the p ointer interpreter tran-

sitions from the NDF state into the LOP-TU3 state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the NDF

state into the NO RM state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the NDF state into the AIS-TU3 state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the

NDF state into the NORM state .

— Fo llowi ng the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NDF state into the LOP-TU3 state.

■ The pointe r interpreter transitions into the NORM state b ased on t he following con dit ions:

— Following three new consecu tive, consistent, and valid pointers, the pointer interpreter tran sit ions into the

NORM state.

— Fo llowing any three consecutive, consistent, and valid pointers, the pointer interpreter transitions into the

NORM sta te. i.e., t r a n sitioning f rom the INC, DEC, and NDF states.

■ The pointer interpreter transitions out of the NO RM s tate based on the following conditions:

— Fo llowi ng the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NORM stat e into the LOP-TU3 state.

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transiti ons f ro m the NORM state

into the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the NORM state into the AIS- TU3 state.

— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 149)), if 8 of the 10 I and D bits are

correct for a pointer decrement on the incoming H1 and H2 bytes the pointer interpreter transitions f rom the

NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer

decrement on the incoming H1 and H2 bytes, t he pointer interpreter transitions from the NORM state into the

DEC state.

— When operating in the 8 of 10 mode (S P E _8OR MA JORITY = 1), if 8 of the 10 I and D bits are correct for a

pointer in crement on the incoming H1 and H2 bytes, the pointer interpreter tr ansitions from the NORM state

into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are co rrect for a pointer in crement on the

incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the INC state.

■ The pointer inte rpreter transitions into the INC s tate based on the following conditions:

— When operating in the 8 of 10 mode (S P E _8OR MA JORITY = 1), if 8 of the 10 I and D bits are correct for a

pointer increment on the incoming H1 and H2 bytes t h e poi nt e r i nterpreter transitions into the INC state. Oth-

erwi se, if 3 of the 5 I b its and 3 of the 5 D bits are c orrect fo r a poin t er increment on the incoming H1 and H2

bytes, the pointer i nterpreter transitions into the INC state.

■The pointer inte rpreter tran sitions out of the INC state ba sed on the foll owing conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter tr ansitions from the INC state into

the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the INC state into the AIS -TU3 state.

— Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC

state into the NO RM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transit ions from the INC

state into the NO RM state.

— Fo llowi ng the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1 :0 ] ( Table 149)), the pointer interpreter transitions from the INC s tate into the LOP-TU3

state.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
410 Agere Sy stem s Inc.
 
18 SPE Mapper Functional Description (continued)
■The pointer inte rpreter tra nsitions into the DEC state based on the following conditions :
— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 149)), if 8 of the 10 I and D bits are 
correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions into the 
DEC state. Otherwise, if 3  of the 5 I bits and 3 of the 5 D  bits are  correct f or a pointer decrement on the incoming 
H1 and H2 bytes the pointer interpreter tr ansitions into the DEC state.
■The pointer interpreter transitions out of the DEC  state based on the followi ng conditions:
— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into 
the NDF state.
— Following three consecutive frames with all ones  in the H1 and H2 bytes, the pointer interpreter transitions from 
the DEC state into the AI S-TU 3 state.
— Following three new consecu tive, consistent, and valid pointers, the pointer  interpreter trans it ions from the 
DEC state into the NORM  state.
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC 
state into the NO RM state.
— Following the number of consecutive invalid pointers (determined by the value programme d in 
SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the  DEC state into the LOP-TU3 state.
■Pointer  increments and d ecrements will be counted and presented to the microprocesso r as  fol lo ws :
— Pointer increments and de c rements will be monitored and counted internally.
— The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from 
TMUX),  bit SPE_RLOP = 1 (Table 148), or bit SPE_RAIS = 1 (Table 148).
— Latched counts, SPE_ R PT R _ IN C [1 0 :0 ] (Table 161) and SPE_RPTR_DEC[10:0]  (Table 161), wi l l  be updated 
coincident   with the end of a performance monitor interval.
— The internal counters will reset to 0x00 coincident with the end of a performance monitor  interval.
— If SMP R_S A T_RO LLOVER = 1 (Table 67), the internal running cou nts  w ill hold at thei r ma ximum va lue. Oth -
erwis e, t he c ounts will roll over.
— Howev er,  i n cr ement and de crement even t indications  should   be ignored during  LOP state.
■LOP-T U3 (TU-3 path LOP) and AIS-TU3 (TU-3 path AIS) will be detec ted and reported to the microprocessor. 
Both the LOP-TU3 and  AIS-TU3 con ditions will contribute to the AUTO AIS control signal from t he SPE mapper 
to the VT mapper. Any change in state o f SPE_RL OP (Table 148) or SPE_RAIS (Table 148) will be reported to 
the microprocessor via SPE_RLOPD (Table 146) and SPE_RAISD (Table 146). Unless the appropriate mask bit 
is set (SPE_R LOPM/SPE_RAISM (Table 147)),  SPE_RLOPD = 1 or SPE_RAISD = 1 will gener ate an interrupt.
■The current TU-3 pointer v alue is s tored in SPE_STORED_PTR [9: 0] (Table 161).
18.14  SPE Mapper Receive Direction Requirem ents
All monitoring functions supported by the SPE mapper in the receive direction are summarized here:
■Loss of CLOCK and loss of sync monitors
■J1 monitor
■B3 BIP-8 check
■C2 signal label monitor
■F2 monitor
■F3 monitor
■N1 monitor
■K3 mo nitor
■AIS-P and RDI-P detect
■REI-P detect
■Signal degrade BER algorithm
■Signal fail BER algorithm
■Path overhead access c hannel (POAC) drop
■Insertio n of AIS-P

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
411Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
Whenever the continuous N-times detect signals are defined,  they require no t only that the monitored signal  be 
consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status 
can be updated. I f there ar e any e r rors in the framing pattern,  then the consec u t ive N-times d etectio n  counters 
must be r e s e t to 0. N c an range from 1 to 15. Programming a CNTD block with any value less than 1 will set the 
CNTD to 1 time detect.
18.14.1 Loss of Clock  and Loss of Sync M oni tors
The SPE mapper detects and reports los s of  the in put clocks state for RLSCLK (pin V4) (19 MHz clock) in bit 
SPE_ RLSL OC (Table 148 on page 137), RLSC52 (pin A C2)  (52 MHz clock) in bit SPE_RC52LOC (Table 148), and 
DS3DATAINCLK (pin J22) (DS3 external clock) in bit SPE _RDS3LOC (Table 148), as determined by stuck high or  
stuck low fo r t ime T. The detection t ime T  will be greater than 10 µs but les s than 125 µ s . The  function uses the 
micro processor clock as its reference. The device will report changes in the states using b its, SPE_RLSL OCD 
(Table 146 on page 134), SPE_ RC52LO CD (Table 146), and SPE_RDS3LOCD ( Table 146); interrupt mask bits 
SP E_ R L SL OCM ( Table 147), SPE_RC52LOCM (Table 147), and SPE_RDS3LOCM (Table 147 on page136 ), 
respectively.
The SPE mapper will detect loss-of-sync conditions f or the telecom bus sync signals. The states are reported in the 
bits, SPE_ RSY52LOS (Table 148), SPE_RJ0J1V1LOS (Table 148), SPE_RSPELOS (Table 148), a nd 
SPE_RV1LOS (Table 148). T he device w ill report changes in the states in bits SPE_RSY52LOSD (Table 146), 
SPE_RJ0J1V1LOSD (Table 146), SPE_RSPELOSD (Table 146), SPE_RV1LOSD (Table 146); in terrupt  m ask  bi ts 
SPE_RSY52LOSM (Table 147),  SPE_RJ0J1V1LOSM (Table 147), SPE_RSPELO SM (Table 147), and 
SPE_RV1LOSM (Table 147), respectively.
18.14.2 J1 Monitor
J1 (path trace) monitoring has six different monitoring modes controlled by bits SPE_J1MONMODE[2:0] 
(Table 149):
■SPE_J1MONMODE[2:0 ] = 000:  the SPE mapper will latch the value  of the J1 byte every frame for a  total 
64 bytes in SPE_RJ1DMON[1—64][7:0] (Table 162). The SPE mapper compares  the incoming J1 byte with the 
next expected value (the expected value i s obtained by  cycling t hrough the previous stored 64 received bytes in 
round-robin f ashion) and setting the path  trace identifier st ate bit,  SPE_R TIM  (Table 148), if diff erent. Any change 
in state is reported in bit, SPE_RTIMD (Table 146), u si ng in ter rupt  mask bi t SP E_R TI MM ( Table 147). CRC is not 
check ed by the hardware.
■SPE_J1MONMODE[ 2 :0 ] = 001: th is is  the SONE T framing mode. The h ardware looks for 0x0D and then the 
0x0DA  charac ters to indicate that  the n ext byte is  the  fir st byte of  the path trace mes sage. The J1 byte message 
is continuously  written into SPE_RJ1DMON[1—64][7:0] with the first byte residing at the fir st address. If  any 
receiv ed b yte does not match  the previously received byte for its location, then the state  bi t SPE_RTIM is set. 
Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.
■SPE_J 1MONMODE[ 2:0 ] = 010: th is is the SDH fram ing mode . The hardware looks for the byte with the most sig-
nificant bit (MSB) set to one, whi ch indicates   that the nex t byte is the second  byte of the mes sage. The r est of 
operation is the same as in SONET framing mode.
■SPE_J 1MONMODE[2:0] = 011: a  n e w J1  by t e (SPE_RJ1DMON[1][7:0]) wil l be de tected after a number of con-
secutive consistent occurrences (SPE_CNTDJ1[3:0] (Table 150)) of a  new pa ttern in t he J1 overhead byte. Any 
changes to t his  byte is reported in bit S PE_RTIMD, using interrupt  mask bit  SPE_RTIMM. The delta bit in this 
mode indicates a change in state for the J1 byte, and the bit SPE_RT IM is not used.
■SPE_J1MONMODE[ 2 :0 ] = 100: the  use r will p r o g ra m   th e 64  expected values of J1 in reg isters, 
SPE_RJ1DEXP[1—64][7:0] (Table 164), i n SONET framing mode, where the first expected byte,  t he byte f ol lo w-
ing the 0x0A character, is written into the first register  loc ation,  S PE_RJ1DEXP[1][ 7:0] .  T he S P E mapper com-
pares the incoming J1  sequence with the s t ored expected value, setting the S PE_RTIM state  bi t if they are 
different. Any changes in the state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
412 Agere Sy stem s Inc.
 
18 SPE Mapper Functional Description (continued)
■SPE_J1MONMODE[ 2 :0 ] = 101: the  use r will p r o g ra m   th e 16  expected values of J1 in 
SPE_RJ1DEXP[1—16][7:0] in SDH framing mode, where the first byte of the message has t he MSB s et to 1. 
The SPE mapper compares the incomin g J 1 s equence with the stored expected value, setting the st ate bit, 
SPE_RTIM if they’re different. Any change in  state i s reported in bit  SPE_RTIMD, using interrupt mask bit 
SPE_RTIMM.
■SPE_J1MONMODE[1:0] = 11 0 and 111 are currently undefined. 
■Unless bit PAIS_TIMINH (Table 149) is  set, bit SPE_RTIM D co n tributes to the AUTO AIS control signal from th e 
SPE mapper to the VT mapper).
■Unless mask bit SPE _RTIMM is set, bit SPE_RTIM D can generate an interrupt.
Table 536. J1 Monitor
18.14.3 B3 BIP-8 Check
A B3 BIP-8 even parity is computed over all the incoming bits of the T UG-3 frame, after descrambling, and com-
pared to the B3 byte received in the next frame. The total number of B3 BIP-8 bit errors (raw count) or block  erro rs  
is counted (selected through SPE_B3BITBLKCNT (Table 149)). Upon a performanc e monitor (PM) interval, the 
inter nal ru nning count er is pl ac ed into SPE_B3ECNT[15:0] (Table 160) and then cleared . Depending on the value 
of m icroprocessor bit S MPR_SAT_ROLLOVER (Table 67) ,   the internal  counter  will  roll over or sta y at i ts maximu m 
value until cleared.
18.14.4 S ignal Label C2 Byte Moni tor
Table 537. S TS Signal  L abel D efect Conditions
Name Function
SPE_J1MONMODE[2:0] (Table 149)J1 Mo nitoring Type. 
SPE_RJ1DEXP[1—64][7:0] (Table 164)J1 Expected Data Storage (64/1 Byte). 
SPE_RJ1DMON[1—64][7:0] (Table 162)J1 Received Data Storage (64/1 Byte). 
SPE_ C NTDJ1 [3 :0] (Table 150)C ontinuous  Times  Detec t  Value . 
SPE_RTIM (Table 148)J1 Mismatc h State Bit. 
SPE_RTIMD (Table 146)J1 Mismatc h Delta Bit, Active-High. 
SPE_RTIMM (Table 147)J1 Mismatch Mask Bit, Active-High. 
Provisione d ST S PTE 
Functionality, Expected C2 Received Payload Label
(C2 in hex) Defect TMUX_FORCEC2DEF = 1
(Table 97)
Any Equipped Functionality Unequipped (00) TMUX_RUNEQP No Change
Any E quip ped Functionality Equip ped—Nonspec ific (01) None No Change
Equipped—Nonspecific Any   Value (02 to E0, FD  t o FE) N one No Change
Any Payload Specific  C ode The Same Payload Specific 
Code (02 to E0, FD to FE) None No Change
Any Payload S pecific Code A Different Pay loa d Spec ific 
Code (02 to E0, FD to FE) TMUX_RPLMP No Change
Equipped—Nonspecific (01) or 
VT-Structured STS-1 (02) PDI, 1 to 27 VTx Defects 
(E1 to FB) None TMUX_RPLMP
Any Payloa d Spec ific Code 
Except  VT-Stru ctured 
ST S-1 (02)
PDI, 1 to 27 VTx Defects 
(E1 to FB) TMUX_RPLMP No Change
Any Equipped Functionality P DI,  28 VT1.5  Defects or 1 
Non-VT Payload Defect  (F C) None TMUX_RPLMP
Any Equipped Functionality Reserved (FF) None TMUX_RPLMP

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
413Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
The C2 byte i s store d in SPE_C2DMON[7:0] (Table 152 on page140 ). This i s  updated after a number of consecu-
tive  frames (determined by the value programmed in SPE_CNTDC2[3:0] (Table 150 on page139 )) of ident ical C2 
by te s, i.e., the 8-bit pattern must be identical for the number of frames in the programmed SPE_CNTDC2[3:0] p rior 
to updating SPE_C2DMON[7:0].
Whenever the contents of the C2 byte monitor SPE_C2DMON[7:0] chan ges, a d elta bit SPE_C2 DMOND 
(Table 146 on page 134) is set and bit SPE_C2DMONM (Ta ble 147 on page 136 ) is the interrupt m ask  bit.
The SPE mapper maint ains  a program mable ex pected value of the C2 byte in SPE_C2DEXP[ 7:0] (Table 151 on 
page 140) . If the  cu rrent value of the C2 byte (SPE_C2DM ON[7: 0]) does not equal the expected C2 value 
( C2 DEXP[7:0 ]), then a p ay load  label  mismatch (PLM-P) defect is declared and reported in SPE_RPLM 
(Table 148). The change in PLM-P state is reported in SPE_RPLMD (Table 146) with an interru p t mask b it 
SP E_ R PL MM ( Table 147).
Also if the curre n t value  of the C2 byte (SPE_C2DMO N[7:0]) is all 0s, then an unequipped (UNEQ-P) defect is 
declared and re ported in SPE_RUNEQ (Table 148). The change in UNEQ-P state is reported i n SPE_RUNEQD 
(Table 146) with an interr upt mask SPE_RUNEQ M (Table 147).
Table 538. C2MON Processing
18.14.5 Path User Byte F2 Monitor
The SPE mapper monitors the path user channel in the F2 byte. T he c urrent  va lue of the F2 byt e is stored in 
SPE_F2DMON0[7:0] (Table 152) after a number of consecutive frames (determined by   the value programmed in 
SPE_CNTDF2[3:0] (Table 150)) of identical F 2 byte has been received, i.e., the 8-b it patt ern must be i dentical for a 
number of  frames equal to  the value of SPE_CNTDF2[3:0] prior to updating  S P E_F2DMON0[7:0]. 
Whenever the content s of  the F2 byte mon it or (SPE_F2 DM ON 0[ 7:0]) changes, a  del t a  bit  S PE_F 2DMON D 
(Table 146) is set. The  interrupt   mask is S PE_F2D MON M (Table 147).
The SPE mapper maintains  a histor y of  the pr evious valid F2 byte in SPE_F2 DMON1[7:0] (Table 152).
Name Function
SPE_C2DMON[7:0] (Table 152)C2 Current Data Monitor. 
SPE_C2DEXP[7 :0] (Table 151)Expected Value of C2 Byte. 
SPE_CNTDC2[3:0] (Table 150)Co ntinuous Tim es Detect Co un t Value for C2. 
SPE_C2DMOND (Table 146)C2 Data Monitor Event Bit. 
SPE _C2 DMONM (Table 147)C2 Data Monitor Mask Bit. 
SPE_RPLM (Table 148)Payload Label Mismatch St ate. 
SPE_RPLMD (Table 146)Payload Label Mismatch Delt a Bit. 
SPE_RPL MM (Table 147)Pa yload Label Mismatch Mask Bit. 
SPE_RUNEQ (Table 148)Unequipped Path State. 
SPE_RUNEQD (Table 146)Unequi pped Path  Delta Bit. 
SPE_RUNEQD (Table 147)Unequipped Path Mask Bit. 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
414 Agere Sy stem s Inc.
 
18 SPE Mapper Functional Description (continued)
Table 5 39. F 2 Mon ito r
18.14.6 Path User Byte F3 Monitor
The SPE mapper monitors the second path user channel in the F3 byte.  The current value of the F3 byte is stored 
in SPE_F3DMON0[7:0] (Table 152 on page140 ) after a number of consecutive   frames (determined by the value 
programmed in SPE_CNTDF3[3:0] (Table 150)) of identical F3 bytes   has b een rec eived, i.e., the 8-bit pattern m us t  
be identical for a number of frames, determined by SPE_CNTDF3[3:0], prior to updating SPE_F3DMO N0[7 :0] .
Whenever the content s of  the F3 byte mon it or (SPE_F3 DM ON 0[ 7:0]) changes, a  del t a  bit  S PE_F 3DMON D 
(Table 146) is set. The interrupt mask is in reg ister bit SPE_F3DMONM  (Table 147).
The SPE mapper maintains  a histor y of  the pr evious valid F3 byte in SPE_F3 DMON1[7:0] (Table 152).
Table 540. F3 Moni tor
18.14.7 N1 Monitor
Th e SPE mapper st or es the curre nt  val ue of the N1 by te  in SPE_N1 DMON[7:0 ] (Table 152). This is updated after a 
number of  consecutive frames (determined by the value programmed i n bi ts SPE_CNTDN1[3:0] (Table 150)) of 
identical N1 by tes, i.e.,  the 8-bit patt ern must be identical for a number frames de termined by  the val ue in register 
bits SPE_CNTDN1[3:0] prior to updating the N1 register.
Whenever the contents of the N1 byte monitor (SPE_N1DMO N[7:0]) changes, a delta bit SPE_N1DMOND 
(Table 146) is set. The  i nterrupt generated by SPE_N1DMON D can be  maske d  off by SP E _N 1DMONM 
(Table 147).
Table 541. N1 Monitor
Name Function
SPE_F2DMO N0[7:0 ] (Table 152)Fault Location Current Consistent Value. 
SPE_F2DMON1[7:0] (Table 152)Fault Location Previous Consisten t Val ue. 
SPE_C NTDF2[3:0] (Table 150)Continuous N-Times Detect (3—15). 
SPE_F2DMOND (Table 146)F2 Data Monitor Delta Bit.  
SPE_F 2 DMONM (Table 147)F2 Data Monitor Mask Bit. 
Name Function
SPE_F3DMON0[7:0] (Table 152)User Channel Curr ent Consistent Valu e. 
SPE_F3 DMON1[7:0] (Table 152)User Channel Previ ous Consistent Value. 
SPE_CNTDF3[3:0] (Table 150)Continuous N-Times Detect (3—15). 
SPE_F3DMOND (Table 146)F3 Data Monitor Delta Bit. 
SPE_F3DMONM (Table 147)F3 Data Monitor Mask Bit. 
Name Function
SPE_N1DMON[7:0] (Table 152)Fault Location  Current Consistent Value. 
SPE_CNTDN1[3:0] (Table 150)Continuous N-Times Detect (3—15). 
SPE_N1DMOND (Table 146)N1 Data Monitor Delta Bit. 
SPE_N1DMONM (Table 147)N1 Data Mo nitor Mask Bit. 

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
415Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
18.14.8 K3 Byte Monitor
The SPE mapper stores the current value of the K3  by te in SPE_K3DMON[ 7:0] (Table 152 o n pag e140). This is 
updated after a number of consec utive frames ( dete rmined by the value programmed in   bits SPE_CNTDK 3[3:0] 
(Table 150 on page139 )) of identical K3 bytes, i.e., the 8-bit pattern must be identical for a number of frames deter-
mined by the value of SPE_CNTDK3[3:0] prior to updating the K3 register.
Whenever the cont ent s   of the K3 by te monitor ( SPE_K3DMON[7:0])  changes , a  d e lt a bit  SP E _K 3 D M ON D  
(Table 146 on page 134) is set. The interrupt generated by SPE_K3D MON D   can be masked off by the 
SPE_K3DMONM (Table 1 47 on page 136).
Table 542. K3 Monitor
18.14.9 AIS-P and RDI-P  Detect
Th e SPE mapper monitors for path AIS in the H1 and H2 b yt es (all H1 and H2 bits = 1) of the TUG-3 point e r . When 
path AIS is detected, SPE_RAIS (Table 148 on page137 ) will be set to 1 after three co nsecutive occur rences. Any 
changes to SPE_ R AIS wi ll be repor t ed in SPE_RA ISD (Table 146 on page134 )  and the interrupt can be masked, 
using SPE_RAISM (Table 147 on page136 ).
A remote defect indication-path (RDI-P) signal indicates to STS PTE that i ts peer STS PTE has detected a defect 
on the sign al that   it originated. The SPE mapper supports both the single bit RDI-P and the 3-bit enhanced RDI-P; 
the m ode is selec table using bit SPE_RPRDI _MODE (Table 149 on page138 ). When SPE_RPRDI_MODE  = 0, 
1-bit code is  su pported and when SP E_RPRDI_MODE = 1, 3-bit enhanced RDI-P code is supported. Three bits of 
the G1 byte (G1[3:1]) are reserved for the RDI- P signal.
The SPE map per monitors for a 1-bit RDI-P code in G1[3]  bit or a 3-bit enhanced remote defe ct indication (RDI-P) 
condition in the G1[ 3:1] bits and sto res the c urrent value in bits S PE_PRDIDMON[ 2: 0] ( Table 152 on page140 ). 
The current value is updated after a n umb er o f consecu tive frames (dete r mined by the  value of bits 
SPE_CNTDPRDI[3:0]  (Table 150)) of identical G1[3:1], i.e., the 3-bit pattern must be identical for a number of 
frames, determined by the value of SPE_CNTDPRDI[3:0] prior t o updating SP E_ PRDIDMON[2:0].
Whene ver the contents of SPE_PRDIDMON[2:0] changes, a delta bit SPE_PRDIDMOND (Tab le 146 on page 134) 
is set .   The inter ru pt  generated by SPE_PRDIDMOND can be masked off by SPE_PRDIDMONM (Table 147).
Table 543. AIS -P and RDI-P Detect
Name Function
SPE_K3DMON[7:0] (Table 152)Faul t  Location  Curren t  C onsi s t ent Value. 
SPE_CNTDK3[3:0 ] (Table 150)Co ntinuous N-Tim es Detect (3—15). 
SPE_K3DMOND (Table 146)K3 Data Monitor Delta Bit. 
SPE_K3DMONM (Table 147)K3 Data Mo nitor M ask Bit. 
Name Function
SPE_CNTDPRDI[3:0] (Table 150)Contin uous Times Detect Count Value for G1[3:1] Bits (3—15). 
SPE_PRDIDMOND (Table 146)Path RDI  Delta Bit. 
SPE_ PRDIDMONM (Table 147)Path RDI Mask Bit. 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
416 Agere Sy stem s Inc.
 
18 SPE Mapper Functional Description (continued)
18.14.10 RE I-P Detect
Bits 7 through 4 of the G1 byte are allocated for use as a path remote error indication functio n (REI-P).
■F or  STS-1 signals, bits 7 through 4 of the G1 byte are allocated  for REI-P which conveys the error count detected 
by the PT E (using the p ath  BIP-8 code B3) back  to its peer PTE as follows.
Table 544. STS-1 P-REI  Interpretat ion
The SPE mapper pr ovides a counter to accumulate G1-REI errore d bit count in SPE_G1ECNT[15:0] ( Table 160 on 
page 147) from G1[7:4]. This counter will hold at its maximum value or roll over (depending on the v alue of micro-
processor bi t SMPR_SAT_ROLLOVE R ( Table 67 on page 68)) and up date upon the perfor mance monitor ing inter-
val.
18.14.11 Signal Degrade BER Algorithm
A signal deg rade state bit is SPE_SDB3 (Tabl e 148 on page 137) with a c hange of state indication reported in delta 
bi t SPE_SDB 3D (Table 146 on page134 ) and the interrupt mask bit is SPE_SDB3M (Table 147). This bit error rate 
algorithm operates on B 3 errors.
Declaring the signal degrade state requires the definition o f two measurement windows.  A monitoring block con-
sisting o f a number of frames, Ns  (SPE_SDNSSET[18:0]  (Table 158 on page 146)), and a measurement interva l  
consisting of a number of monitoring blocks, B (SPE_SDBSET[11:0] (Table 158)). A block is det ermined bad when 
the number of bit errors equals or exceed s a threshold, L (SPE_SDLS ET[3: 0] (Table 158)).  Signal deg rade is 
declared when a number of bad monitoring blocks equals or exceeds the threshold, M (SPE_SDMSET[7:0] 
(Table 158)), for the measurement interval.
Clear ing the si gnal degrade s tate requ ir es  the de finition of  t wo measurem ent windows. A monitoring  block consist-
ing of a number of frames, Ns (SPE_SDNSCLEAR[18:0] (Table 158)), and a measurem ent in terval consisting of a 
number of monitoring blocks, B (SPE_SDBCLEAR[11:0] (Table 158)). A block is determined good when the num-
ber of bit e rrors is les s than a threshold, L (SPE_SDLCLEAR[3:0] (Table 158)). S ig nal degrad e i s cleared when a 
number of good monitoring block s equals or  exceeds the threshold, M (SPE_SDM C L EAR[7 :0] (Table 158)), for   the 
measurement interval.
The set parameters are used when the signal degrade state is clear, and the  clear p arameters are used when the 
signal degrade state is declared.
The signal degrade s ta te may be forced to the declared state wi th bit SPE_SDSET (Table 145 on page134 ) and 
forced to the cleared state with bit SPE_SDCLEAR (Table 145). The controls are provided to force the BER algo-
rithm into  the failed state or normal state, res pec tively.
The above algor ithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.
G1[7:4] Code Code Interpretation
0000 0 (no errors)
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001—1111 0 (no errors)

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
417Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
Table 545. Signal Degrade Parameters
Note: The threshold written by the control system is one less than the desired number, except for the SPE_SDLSET[3:0]/SDLCLEAR[3:0] 
parameter.
18.14.12 S i gnal Fail BER Algorithm
A signal fail state is  repor ted by   bit  SPE_ SF B3 (Tabl e 148 on pag e137) and change of stat e in bit SPE_SFB3D 
(Table 146) with  the interrupt mask bit SPE_SFB3M (Table 147). This bit error rate algorithm operates on B3 errors.
Declaring the signal fail state requires  the definition of two measure ment window s ,  a  m onitoring block consisting of 
a number of frames, Ns (SPE_ SFNSSET[18:0] (Table 159 on page146 )), and a  measurem ent  i nterval consisting 
of a num ber o f monitoring b locks, B  (SPE_SFBSET[15:0] (Table 159)). A block is determined to be bad when the 
number of bit errors equals or exceeds a threshold, L (SPE_SFLSET [3 :0 ] (v)). Signal  fail is  decl a r e d when the  
number of  bad m onitoring blocks equals or exceeds the threshold, M  (SPE_SFMSET[7:0] (Table 159)), for the 
measurement interval.
Clearing the signal f ail state requires the definition of two measurement windows, a monitoring block consisting of a 
num be r of fr ames,  Ns (SPE_SFNSCLEAR[18:0] (Table 159)), a nd a  measurem ent  i nterval consisting of a number 
of monitor ing blocks, B (SPE_SFBCLE AR[11:0] (v)). A  block is determined to be good when the number of bit 
errors is  less t han a threshold, L (SPE_SFLCL EAR[ 3:0] (Table 159)). Signal fail is cleared when a number of good 
monitoring blocks equals or exceeds the threshold, M (SPE_SFMCLEAR[7:0]  (v)) , fo r the measurement interval.
The  set parameters are used when the signal fail state is clear, and the  clea r parameters are used when the signal 
f ail state is declared.
The signal fail sta te may   be forced to the declared  state with  bit SPE_SFSET ( Table 145 on page134 ) and forced 
to the cleared state with bit SPE _S FCLEAR (Table 145).
The above algor ithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.
Name Function
SPE_SDNSSET[18:0] (Table 158)Signal  Degrade Ns Set. Number of frames in a monitoring block for SD.
SPE_SDLSET[3:0] (Table 158)Signal Degrade L Set. Error thres hold  for deter m inin g if a moni toring 
block is bad.
SPE_SDMSET[7:0] (Table 158)Signal Degrade M Set. Threshol d of the number of bad monitoring blocks 
in an observation interval. If the  number of bad blocks is below this thresh-
old, then SD is cleared .
SPE_SDBSET[15:0] (Table 158)Signal Degrade B Set. Number of monitoring blocks in a measurement 
interval.
SPE_SDNSCLEAR[18:0] (Table 158)Signal Degrade Ns Clear. Number of frames in a monitoring block for SD.
SPE_SDLCLEAR[3:0] (Table 158)Signal Degrade L Clear. Error threshold for determining  if a monitor ing 
block is bad.
SPE_SDMCLEAR[7:0] (Table 158)Signal Degrade M Clear. Threshold of the number of ba d monitoring 
blocks in an observation inte rval.  If the number of bad blocks is below this 
threshold, then SD is cleared.
SPE_SDBCLEAR[15:0] (Table 158)Signal Degrade B Clear. Numb er of monitoring blocks in a measurement 
interval.
SPE_SDSET (Table 145)Signal Degrade  S et. Allows the signal degrade algorithm to be f orced  into 
the failed state (active 0 to 1).
SPE_SDCLEAR (Table 145)Signal Degrade Clear. A llows the signal degrade algorithm to be forced 
into  the normal  state (active 0 to 1).
SPE_SDB3 (Table 148)Signal Degrade BER Algorithm State Bit. 
SPE_SDB3D (Table 146)Sign al Degrade BER Al gorithm Delta Bit. 
SPE_ SDB3M (Table 147)Signal Degrade BER Algorithm Mask Bit. 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
418 Agere Sy stem s Inc.
 
18 SPE Mapper Functional Description (continued)
Table 546. Signal Fail Parameters
Note: The threshold written by the control system is one less than the desired number, except for the SPE_SFLSET[3:0]/SFLCLEAR[3:0] 
parameter.
18.14.13 P OAC Dro p
The  SPE mapper accommodates one path overhead access channel (POAC out put channe l).
The  POAC  ch annel consis t s of the follow ing s ignal s :
■A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3).
■A 576 kb its/s  data signal sourced by the TMUX (RPOACDATA, pin AD4).
■An 8 kHz synchronization signal, sourced by the TMUX (RPOACSYNC, pin AF4). The sync signal is normally 
low; dur ing the last clock period of each frame coincident with the least significant bit  of the last byte, the sync 
signal is high.
The data s ig na l i s pa rtitioned in to  f ra mes of 9 bytes. The frame rep etition rate is 8 kHz. Each byte consists of 8 bits 
that are transmitted/received mos t significant bit first (MSB). The MSB of the second byte of each frame contains 
an odd/even parity bit over the 72 bits of the previous frame. The remaining 7   bits of this byte are n ot  specified.
Bytes shown in Table 547 summarize the a ccess  capabilities  of the receive POAC.
Name Function
SPE_SF NSSET[18:0] (Table 159)Signal Fail Ns Set. Num ber of frames in a monitoring block fo r SF.
SPE_SF L SET [3:0] ( Table 159)Signa l  Fai l L Set. Error thres hold for determining if a monitoring block is 
bad.
SPE_SFMSET[7:0] (Table 159)Signa l Fail M Set. Threshold of the num ber of  ba d monitoring blocks in 
an obse rvation interval. If the number of bad blocks is belo w this thresh-
old, then SF is cleared.
SPE_SF BSET [15:0] (Table 159)Signal Fail B Set. Number of monitoring blocks.
SPE_ SFNSCLEAR[1 8:0] (Table 159)S ignal Fail Ns Clear. Number of frames in a monitoring block for SF.
SPE_SF L CLEAR[3: 0]  ( Table 159)Signal Fail L Clear. E rror threshold for det ermining if a monitoring block 
is bad.
SPE_SFMCLEAR[7:0] (Table 159)Signal Fail  M  Clear. Threshold of the number of bad monitoring blocks in 
an obse rvation interval. If the number of bad blocks is belo w this thresh-
old, then SF is cleared.
SPE_SFBCLEAR [15:0]  (Table 159)Signal Fail B Clear. Number of monitoring blocks.
SPE_SFSET (Table 145)Sig nal Fail Set. Allows the signal degrade algorithm to be forced into the 
failed state (active 0 to 1).
SPE_SFCLEAR (Table 145)S ignal Fail Clear. Allows the signal degrade a lgorithm to be forced into 
the nor mal state (active 0 to 1).
SPE_SFB3 (Table 148)Si gnal Fail  BER Al gor ith m State Bit. 
SPE_SFB3D (Table 146)Si gnal Fail  BER Al gor ith m Delta Bit. 
SPE_SFB3M (Table 147)Signal Fail BER Algorithm Ma sk Bit. 

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

419Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Table 5 47. Path Overhead Byte Access

Even or odd parity can be inserted into the first bit of the second byte of the POAC outgoing frame. Parity is

selected with register b it, SPE_RPOAC_OEPINS (Table 149 on page 138 ).

18.14.14 Ins ertion of AIS-P

The SPE mapper automatically generates AIS path (AIS -P ) when:

■The pointer interpret er declares the receive AIS state (SPE_RAIS in Table 148 on page137 ) or receive l oss of

pointer state (SPE_RLOP (Table 148)) and the appropriate i nhibit signals are in active .

■AIS is requested by signals from the TMUX interface.

■AIS is forced by setting bit SPE_PAISINS (Table 149).

■Any one of the loss-o f-clock or loss-o f -sync bits are active and their co rrespondin g inhibit bits are inactive.

■Any of bits SPE_RU NEQ, SPE_RPLM, and SPE_RTIM (all are in Table 148) are active, and the appropriate

inhibit signals are inactive.

Criteri a for PATH_AIS _GEN ERATE =

((SPE_RLOP AN D (SPE_PAIS_LOPINH)) OR

(S PE_ R AIS AND (SPE_PA IS_ AISINH)) OR

(SPE_R UNEQ AND (SPE_PAIS_UNEQINH)) OR

(S PE_ R PL M AND (SPE_PAIS_PLMINH)) OR

(S PE_ RTIM AND (SPE_PAIS_ TIMINH)) OR

(SPE_SFB3 AND (SPE_PAIS_SFB3INH)) OR

(SPE_SDB3 AND (SPE_PAIS_SDB3INH)) OR

(SPE_RSY52LOS AND (SPE_AIS_LOSSY52INH)) O R

(S PE_RV1LOS AN D (SPE_AIS_ LOSV1INH)) OR

(S PE_ R SPEL O S AN D (SP E_ AIS_LOSSP EINH )) OR

(S PE_RJ0J1V1 LOS AND (SPE_AIS_LOSJ0J1V1 INH)) OR

(SPE_RDS3LOC AND (SPE_AIS_LOCDS3INH)) O R

(SPE_RC52LOC AND (SPE_AIS_LOC 52INH)) O R

(SPE_RLSLOC AND (SPE_AIS_LOCINH)) O R

SPE_ PAISIN S OR

RAUTO_AIS (signal from TM UX))

The SPE mapper starts/stops generating AIS-P within 125 µs of the detection/abse nc e o f a fa il ur e condition.

AIS-P consists of writing all ones into the H1, H2, and H3 bytes and into the entire payload.

POH Pa rit y

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

420 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

18.15 Transmit Direction (to SONET/SDH Line)

The transmit block inserts t he path overhead (POH) bytes t o the pa yload data and o utputs an STS-1 SPE or a

TUG-3 payload as required.

The transmit section is broken down into the following functional parts:

■Loss of clock and loss of sync det ectors

■ N1 insert

■ K3 insert

■ Path user b yte F3 inse rt

■ Path user b yte F2 inse rt

■ AIS-P insert

■ REI-P insert

■ RDI-P insert

■ C2 signal label insert

■ B3 calculation and insert

■ J1 path trace insert

All insert control functions that are inhibited will insert all zeros or all ones into the outgoing bytes depending on the

value of microprocessor register bit SMPR_OH_DEFLT ( Table 67).

18.15.1 PATH Insertio n Block

The path overhead insertion block of th e SPE mapper is shown below. The block computes and inserts the B3 BIP

error bytes and the rest of the path overhead bytes to form a TUG -3 frame.

5-9069(F)

Figure 37. Transm it Dir e ction P a th In sertion Block

INSERT K3

N1 C2 F3 F2K3 G1 G1J1

INSERT

AIS-P

POAC INSERT

INSERT PATH OVERHEAD BYTES

MUX

TO TM UX INTERFACE

BLOCK

VC-3 DATA

TUG-3 DATA

J1 APS

INSERT

RDI-P

INSERT

REI-P

INSERT INSERT

N1 INSERT

C2 INSERT

F3 INSERT

F2 INSERT H4

FIXED VAL

GENERATEINSERT

F2, F3, C2, N1, AND J1

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
421Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
18.15 . 2 Loss of  Clock and  Loss of Sync Detectors
The SPE mapper detects and reports the loss of t he input  clocks for the transmit telecom bus  clock, device pin 
TL SCL K ( AA2 ) , in bi t SPE_ TL SL O C  (Table 148 on page137 ); the 51.84 MHz transmit low-speed clock, device pin 
TLSC52 ( AC3), in bit SPE_TC52LOC (Table 148), and the external DS3 clock , device pin DS3D ATAINCLK (J22), in 
bit SPE_TDS3LOC (Table 148). Loss of  clock is deter mi ned by stuck  high or stuck low for time T.  T he detection 
time T will be greater  than 10 µs but less than 125 µs. The func ti on uses the microproce ssor clock as its reference. 
The device will report a change in the loss of  c lock state for the monitored clocks   using bits SPE_TLSLOCD 
(Table 146 on page 134), SPE_TC52LOCD (Table 146), and SPE_TDS3LOCD (Table 146), respe ctively. The 
microprocessor interrupt may be ma sked using  bits SPE_TLSLOCM (Table 147 on pag e 136), SPE_TC52LOCM 
(Table 147), and SPE_TDS3LOCM (Table 147), respect ively.
The SPE mapper det ects loss-of-sync conditi ons f or the telecom bus sync signals, de vice pins TLSSYNC52 (AD2), 
TLSJ0J1V 1 (AB4), TLSSPE (AB2),  and TLSV1 (AB3). The loss of sync states are reported in bits 
SPE_TSY52LO S (Table 148), SPE_TJ0J 1V1LO S  (Table 148), SPE_TSPEL OS  (Table 148), and SPE_TV1LOS 
(Table 148), res pectively. The device will report a change in the loss of sync  state for the monitored  sync signals in 
bits SP E_ TSY 52LOS D  (Table 146), SPE_TJ0J1V1LO SD (Table 146), SPE_TSPEL OSD (Table 146), and 
SPE_TV1LOSD (Table 146) , res pectively. The mic ropro cessor interru p t may be masked  using bits 
SP E_ TSY52LOSM ( Table 147), SPE_TJ0J1V1LOSM (Table 147), SPE_ TSPELOSM (Table 147), an d 
SP E_ TV1LOSM (Table 147), respectively.
18.15.3 J1 Byte Insert
A 64-byt e sequence stored in SPE_TJ1DINS[1—64][ 7:0] (Tab le 163 on page 148) will be inserted into the outgoing 
J1 by t e when bi t SPE_TJ1INS = 1 (Table 154 on page143 );  o therwise, the  associate d POAC value is i nserted 
when bit SPE_TPOAC_J1 = 1 (Table 154) or t he default value, determined by the value of microprocessor bit 
SMPR _OH_DEFLT (Table 67 on pag e68), is inserted when SP E_T POAC_J1 = 0.
The CRC for the J1 trace has to b e programmed into the J1 bytes by the  user.
18.15.4 B3 BI P-8 Calculation and Insert
The  B3 bytes are allocated for path overhead err or monitoring function. This f unction is a bit interleaved parity 8 
code (BIP-8 ) using even parity.  The BIP-8 is computed before   scra mbling over  all bits of the previous AU -3/TUG-3 
frame, and is placed in byte B 3 of the current frame also bef ore scrambling. When enabled with control bit, 
SPE_TB3ERRINS (Table 156), a single B3 byte can be inverted each time bit SPE_BERR_INS (Table 156) is 
asserted.
18.15.5 C2 S ig nal Label Byte In sert
When bit SPE_TC2INS = 1 (Table 154), the  value in SPE_TC2DINS[7: 0]  (Table 157) is inserted into the o utgo ing 
C2 byte; otherwise, insert the associated POAC value w he n SPE_TPOAC_C2 = 1 (Table 154) or insert the default 
value determined by the microprocessor bit SMPR_OH_D EFLT when bi t  SPE_TP OA C_C2 = 0.
18.15.6 RE I-P G1(7:4) Insert
Four bits of  the G1 b yte G1(7:4) are allocated for use as  a path remote error in dication (REI). For AU-3/TU G-3  sig-
nals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been detected in error by 
the BIP-8 (B3) de tector on the received si gnal.
Thi s function can be inhibited with bit SPE_TREIP_INH (Table 155) and the value in SP E_TG1DINS[7:4] 
(Table 157) i s  inserted in G1(7:4) bits. A  cont inuous error in the G1 byte can be transmitted using cont rol bit 
SPE_TREIERRI NS (Table 156). A value  of 0x03 will be inserted when SPE_TREIERRINS = 1, subject to 
SPE_BERR_INS a n d SMPR_BER_I NSRT bein g en abled.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
422 Agere Sy stem s Inc.
 
18 SPE Mapper Functional Description (continued)
18.15.7 Path RDI (RDI-P) Insert
When transmit RDI software insert cont rol bit SPE_TPRDI INS = 1 (Table 155), data from SPE_TG1D INS[3:1] 
(Table 157) is written into the G1[3:1] output bits. When SPE_TPRDIINS = 0, hardware insert is enabled for RDI-P 
insertion. Each defect  contrib ution to the RDI-P outgoing code  can be inhibited. There are two modes supported f or 
path RDI Insertion.  One mod e  conforms to the earlier 1-bit version of the  standard. The other mode, enhanced 
RDI-P mode, uses a 3-bit R D I -P code and conforms to the current  version of the standard. W hen the mode selec-
tion bit SP E_TPRDI_M ODE = 0 (Table 155),  th e  SPE map per  sends a 3-bit code that  conforms to the earl ier 1-bit 
versi on of th e standar ds. When S PE_T PRDI_M O D E  = 1,  the  SPE  ma pper sends a 3-bit code conforming to the 
current  enhance d path RDI encoding. Note  that for nonenhanced RDI-P mode, the rele vant defects are AIS-P and 
LOP-P.  For enhanc ed RDI-P mode, the relevant defects are AI S -P, LOP-P,  TIM-P, PL M-P, and UNEQ-P, and TIM-P.
When  a failure condition exists that will cause RDI-P to be generated vi a hardware, the generation of RDI-P must 
last for at l eas t 20 frames before cleari ng, even if the original failure cause has cleared in less  than 20 frames.
The  following table describes   the encoding of the  p a th-RDI defects.
Table 548. RDI-P  Defects f or Enhanced RDI-P Mode
18.15.8 F2 B yte Insert
Whe n contr o l bit SPE_TF2INS = 1 (Table 154), inser t the value in SPE_T F2DIN S[7:0] (Table 157) in the outgoing 
F2 byte;  otherwise, insert the  assoc iated POAC  value when bit SPE_TPOAC_F2 = 1 (Table 154) or insert the 
default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 67) when SPE_TPOAC_F2 = 0.
18.15.9 H4 I nser t Control
Whe n control bit SPE_TH 4 INS =  1 (v),  inse rt the value in S PE_TH4DINS[7:0] (Table 157) in the outgoing H4 byte; 
otherwise, i nsert th e associated POAC valu e when bit SPE_TPOAC_H4 = 1 (Table 154) or insert the default value 
determined by the microprocessor bit SMPR_OH_DE FLT when SP E_TPOAC_H4 = 0.
18.15.10 F3 Byte Ins ert
Whe n contr o l bit SPE_TF3INS = 1 (Table 154), insert the value in SPE_T F3DIN S[7:0] (Table 157) in the outgoing 
F3 byte;  otherwise, insert the  assoc iated POAC  value when bit SPE_TPOAC_F3 = 1 (Table 154) or insert the 
default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 67) when SPE_TPOAC_F3 = 0.
18.15.11 K3 Insert  Control Parameters
Whe n contr o l bit SPE_TK3IN S =  1 (Table 154), insert the value in SPE_TK3DIN S[7:0] (Table 157) in the outgoing 
K3 byte; othe rwise, insert t he associated POAC value when bit SPE_TPOAC_K3 = 1 ( Table 154) or insert the 
default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_K3 = 0.
G1 Triggers
Bit 3 Bit 2  Bit 1
0 0 0 No defects (nonenhanced RDI-P mode)
0 0 1 No defects (enhanced RDI-P mode)
0 1 0 LCD-P, PLM-P (LCD-P not supported in Super Mapper)
0 1 1 No defects (nonenhanced RDI-P mode)
1 0 0 AIS-P, LOP-P (nonenhanced RDI-P mode)
1 0 1 AIS-P, LOP -P (enhanced RD I-P mode )
1 1 0 TIM-P, UNEQ-P (enhanced RDI-P mode) 
1 1 1 AIS-P, LOP-P (nonenhanced RDI-P mode)

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
423Agere Systems Inc.  
18 SPE Mapper Functional Description (continued)
18.15.12 N1 Insert Control Parameters
Whe n contr o l bit SPE_TN1 INS = 1 (Table 154), inser t the value in SPE_ TN1DINS[7:0] (Table 157) in th e outgoing 
N1 byte; otherwise, ins ert the associ at ed POAC value when bit SPE_TPOAC_N1 = 1 (Table 154) or insert the 
default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_N1 = 0.
18.16  POAC Inser t
One overhead access channel (POAC) is provided on-chip to provision the path over head portion of the outgoing 
frame. A POAC channel consists of the fol l owi ng signals:
■A 576 kHz inverted clock  s ignal sourced by the SPE mapper (TPOACCL K , pin AE4).
■A 576 kb its/s data signal received by the SPE mapper in the transmit direction (TPOACDATA,  pin AD5).
■An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the SPE mapper. T he sync signal is nor-
mally low; during the first clock period of each frame coincident with the most significant bit of the first byt e, the 
sy nc  sig nal  is high.
The data s ig na l i s  partitioned in to  f ra mes of 9 bytes. The frame repetition rate  is 8  k Hz. Each by te consists of 8  bits 
that are transmitted/received most significant bit first. The MSB of the second by te of each frame contains  an odd/
even parity bit over the 72 bits of the  previous frame. The remaining 7 bits of this byte are not specified. The POAC 
input has full access t o all the   path overhead byt es of the  STS-1 frame. Bytes shown in the table below summarize 
the access capabil ities of the transmit POAC channel.
Table 549. P ath Overhead Byte Access—Trans m it Direction
An event  indication is provided to indicat e parity errors for the POAC channel. Monitoring of odd or even parity  is 
selected with bit S PE_TPOAC_OEPMON (Table 154 on page143 ). Parity errors  are reported with bit 
SPE_TPOAC_PE (Table 146). The interrupt can be masked with bit SP E_TPOAC_PM (Table 147 on page136 ).
Table 550 summarizes the insertion options  for the specified overhead bytes for POAC. The SPE  mapper allows a 
predefined  default value determined by the  value of the   microprocessor   bit SMPR_OH _DEFLT (Table 67) to be 
inserted on the corres ponding POAC value.
J1
POH Pa rit y
C2
G1
F2
H4
F3
K3
N1

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

424 Agere Sy stem s Inc.

18 SPE Mapper Functional Description (continued)

Table 550. T POAC Control Bits

18.17 A IS Path Generation

Path AI S is specified as all ones in the entire STS-1 SPE/TUG -3 frame. Path AIS can be forced by setting bit

SPE_TAISPINS = 1 (Table 154 on page143 ).

Overhead Bytes Control Bits

(Table 154)Values

0 (Default Value) 1

J1 SPE_TPOAC_J1 S M P R_OH_DE FLT TP OAC Data

H4 SPE_TPOAC_H4

F2 SPE_TPOAC_F2

F3 SPE_TPOAC_F3

C2 SPE_TPOAC_C2

K3 SPE_TPOAC_K3

N1 SPE_TPOAC_N1

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
425Agere Systems Inc.  
19 VT/TU Mapper Functional Description
Ta ble of Conte nts
Contents Page
19 VT/TU Mapper Functional Description  . ..... .......................... . .............................. ..................... . ...................... 425
19.1  VT/TU Ma pper Introduc t ion  ............................. ....... . .............................. .............. . .................................. 427
19.2  VT/TU Ma pper Features .. .................... ..... ....... . ......................... ..... ... ......................... . ........................... 427
19.3  VT/TU Ma pper Functional Block Diagram .............................................................................................. 428
19.4  VT/TU Mappings ..................................................................................................................................... 430
19.5  VT/TU Locations ..................................................................................................................................... 431
19.6  VT/TU Ma pper Rec eive Path Description .................... ....... . ....................... ... ....................... .................. 432
19.7  VT Demultiplexer (V TDEMUX) ............................................................................................................... 432
19.8  VT Po inter Interpreter (VTPI) .................................................................................................................. 432
19.9  VT Termination (VTTERM) ..................................................................................................................... 435
19.9.1 V5 Termination ............................................................................................................................. 435
19.9.2 Z6/N2 Termination  ....................................................................................................................... 436
19.9.3 Z7/K4 Terminati on  ....................................................................................................................... 436
19.9.4 Payload Termination .................................................................................................................... 437
19.10  Output Signal Selection (OUTSEL)  ............... .......................... ............................................................. 437
19.11  J2 Byte Monitor and Termination (J 2MON) ...................... ....... ................. ... ......................... ................ 438
19.12  Receive Signaling (RX_VTSIG) ............................................................................................................ 439
19.13  Receive Lower-Order  Path Overhead (RX_LOPOH)  ....... ..... ................... ..................... ..... .................. 440
19.14  VT/TU M apper Trans mit Pat h Requirements ....... . .............................. ....... .............. .......... ... ............... 440
19.14.1 Input Selector (INSEL)  .............................................................................................................. 441
19.14.2 Transmit Elastic Store (TES) ..................................................................................................... 442
19.14.3 Virtual T ributary Generator (VTGEN) ........................................................................................ 442
19.14.4 Pointer Generation .................................................................................................................... 442
19.14.5 VT Multiplexer (VTMUX)  ........................................................................................................... 450
19.14.6 Transmit Signa ling (TX_VTSIG) ................................................................................................ 450
19.14.7 Transmit Lower Path Overhead (TX_LO POH) ........... ............................ . .................................. 450
19.15  VT Mapper System Interf ace Timing  ................................ ....... ................... ....... ................... ................ 451
19.1 5 .1  V T Mapper DS1/E 1 Rece ive Inte rface (to System Inte r face) ..... ............................................... 451
19.15.2 VT Mapper DS1/E1 Transmit Interface (from System Interface) ............................................... 452
19.16  VT Mapper Lower-Order Path  O verh ead Interface Tim ing ........... .......................... .............................. 452
19.16.1 VT Mapper Recei ve  Pat h Overhead Interface Description  . . ......................... . ........................... 452
19.16.2 VT M apper Transmit Path Overhead Interface Description  ...................................................... 453
Figures Page
Fig ure 38. VT Mapper Interface Diagram............................................................................................................. 428
Figure 3 9. VT Mapper Functional B lock   D iagram................................................................................................. 429
Fig ure 40. Pointer Interpretation State Dia gram................................................................................................... 433
Figure 41. DS1 Mode G apped Clock ing Scheme........................... .................................................... .................. 451
Figure 42. E 1 Mode Gapped Clock ing S c heme ................................................................ ....... ............ ................ 451
Fig ure 43. DS1 Interface ...................................................................................................................................... 451
Fig ure 44. E1 Interface......................................................................................................................................... 452
Fig ure 45 . VT Map per  R ece ive Pat h Overhead Ser ial Access Channel .. .... ............... ...... ............. ................... .. . 4 52
Figure 46. VT Mapper Transmit Pat h Ov erhead Ser ial Access Channel .................. ....... ....... ..... ....... ....... ..... ..... 453

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
426 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
Table of Conten ts (continued)
Tables Page
Table 551. VT2/TU-12 Payload Mapping ............................................................................................................ 430
Table 552. V T1. 5/ TU-11 Payload Mapping ............ ....... ...................................... ....... ......................................... 430
Table 553.  VT2/TU-12 Locations ......................................................................................................................... 431
Table 5 54. VT1.5/TU-11 Loca tions ........... ..... ..................... ..... .......................... .......................... ........................ 431
Table 555. Receive VT/TU Demapping Selection ................................. ....... . .............................. ... ..................... 437
Table 5 56.  Rx Signaling B ehavior per Channel .... ..................... ..... .......................... ..................... . ..................... 439
Table 5 57. Data Type Header Definition s  ............................... .......................... ... ............................................... 440
Table 558. Transmit VT/TU Map ping Selection per Channel, VT_TX_MAPTYPE[1—28][3:0] ........................... 441
Table 559. V 5 Overhead Byte Format ................................................................. ................................................ 443
Table 560. BIP-2 Error Insertion Modes . ....................... .......... ... ....................... ... ............................................... 443
Table 561.  RDI-V, RFI-V, and REI-V Automatic Generation ............................. .............. .............. ...................... 444
Table 562. V T Signal  Label Definition .......................................................... ....... ....... ............ ............................. 445
Table 563. J2 Ov erhead Byte Insertion Modes  Per Cha nnel .............................. . .............................. ... .............. 445
Table 564. Z6/N2 Overhead Byte Insertion Modes  Per Channel ............................... . ......................... .......... ..... 445
Table 565. Z 7/K4 Ov erhead Byte Insertion Modes Per Channel ............................... . ......................... ..... .......... 446
Table 566.  O -Bit Insertion Modes Per Channel  ............. ........................ ..................... ........................ ................. 446
Table 567. A s ynchronous VT1. 5 ............................................... ....... ............ ....... ....... ............ ............................. 447
Table 568.  B it S ync hronou s VT1.5  ......................... ............................................. ................................................ 447
Table 569. B y te Sy nc hronous VT1.5 ......................................... ....... ............ ....... ....... ............ ....... ...................... 447
Table 570. A s ynchronous VT2 ............................... ....... ................... ............ ....................................................... 448
Table 571.  B it S ync hronou s VT2 ........................................ . ......................... ....................................................... 448
Table 572. B y te Sy nc hronous VT2 ...... ............ ....... ....... ............ ....... ...................................... ............................. 448
Table 5 73. VC-11 to TU-12 Conversion .............................................................................................................. 449
Table 574. F ra mi ng Byte Generation Per Ch annel ................... ....... . ......................... ................. ... ..................... 450

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

427Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.1 VT/T U Ma pp e r Int rod u ct i on

This section d escribes t he requireme nts of the S ONET/S DH vir tual tributary payload mappi ng block. T his block

supports the following mapping s:

■28 asynchronous, byte synchronous, or bit synchronous DS 1 sig nals into seven vi rtual tributar y groups (VTGs).

■28 asynchronous, byte synchronous, or bit synchronous DS 1 signals into seven tributary unit groups (TUG-2s).

■28 asynchronous, byte synchronous, or bit synchronous J1 signals into seven virtual tri butary groups (VTGs).

■28 asynchronous, byte synchronous, or bit synchronous J1 signals into seven tributary unit groups (TUG-2s).

■21 asynchronous, byte synchronous, or bit synchronous E1 signals into seven tributary unit groups (TUG-2s).

■Any valid DS1/E1 combination resulting in mixed VTGs and TUG-2s .

Additionally, this block has two auxiliary channels: one for DS1/E1 signaling insertion and drop, and another for

low-order pa th overhead (LOP OH) insertion and drop. Control input s and out puts for each internal block ar e s peci-

fied, along with appropriate control r egister bit definitions.

19.2 VT /TU Mappe r Features

■Maps T1/E 1/J1 into VT/TU st ruc t ures :

— T1 into VT1.5/TU-11/TU-12.

— J1 into VT1.5/TU-11/TU-12.

— E1 into VT2/TU-12.

■Supports asynchronous, byte synchronous, and bit synchronous mapping s.

■Supports automat ic ge neration or micro p ro c e ssor overwrite o f one bit RDI and one bit RFI.

■Supports automatic gener ation or mic roprocessor ov erwrite of enhanced RDI.

■Suppo rts A DM ap plications via tributary loopba ck and tributary pointer processing.

■Supports unidirectional pat h switch rin g ( U PSR) applicat ions via lo w-order path overhead access channel.

■Suppor t s five J 2 t race identifier modes.

■Programmable BIP-2 error insertion.

■Monitors BIP-2 bit error rate.

■Programmable clear -on-read/clear-on-write registers.

■Suppo rts aut om at ic A I S generation for dow nstream devices.

■VC-BIP-2, VC-REI one second error co unters.

■Programmable satur ation or rollover of internal counters.

■Complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT-G707, GR-499, ETS 300 417-1-1.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

428 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

19.3 VT/TU Mappe r Functio nal B lock Di agram

The following blo ck diagram shows a high-level view o f the VT/TU mapper bloc k and the interface to the T1/E1

fra mer, cross connect, SPE mapper (SPEMPR), digital jitter a tt enuator (DJA ), and control (microprocess or inte r-

face).

5-9011(F)r.2

Figure 38. VT Mapper Interface Diagram

DATA

RECEIVE

TRANSMIT

RECEIVE VT/TU MAPPER

TRANSMIT VT/TU MAPPER

FRAMER

[28:1]

LOPOHDATAOUT

LOPOHDATAIN

TRIBUTARY

LOPOHCLKIN

CROSS

CONNECT

DJA

CONTROL INTERFACE

DS1XCLK

E1XCLK

LOPOHVALIDOUT

LOPOHVALIDIN

RDI-V

REI-V

RX PATH SIGNALING

TX PATH SIGNALING

SPEMPR RDI, REI

TUG3 RDI, REI

TRANSMIT

RECEIVE

LOOPBACK

TMUX

DATA CLOCK

FSYNC ALA R M

[28:1]

DATA CLOCK

FSYNC ALA R M

RDI, REI PATH, AND LINE ALARMS

RDI, REI PA TH, AND L INE ALARMS

DATA CLOCK

CLOCK CONTROL

ALARM CONTROL SPE

SPEMPR

SPE

SPEMPR

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

429Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

5-9012(F)

Figure 39. VT Mapper Functional Block Diagram

TES

SOFTWARE REGISTERS

LOPOHDATAIN

LOPOHDATAOUT

LOPOHCLKIN

VTRXDATA[7:0]

RX_EN

V1TIME

VTTXDATA[7:0]

DATA[28:1]

CLK[28:1]

FSYNC[28:1]

DATA[28:1]

CLK[28:1]

FSYNC[28:1]

CLK7M_RX

CLK7M_TX

J1TIME

DS1XCLK

E1XCLK

LOPOHVALIDIN

LOPOHVALIDOUT

INSEL

AUTO_AIS[28:1]

VTPI

RX_LOPOH

J2MON

VTTERM

OUTSEL VTDEMUX

RX_VTSIG

VT LOOPBACK (VTLBSEL = 1 )

VTGEN

TX_VTSIG TX_LOPOH

VTMUX

TUG3_REI[3:0]

TUG3_RDI[2:0]

RDI_L

RDI[2:0]

REI_L[4:0]

REI[3:0]

RDI[2:0]

REI[3:0]

RDI_L

RDI_P[2:0]

REI_L[4:0]

REI_P[3:0]

J0TIME

RAI[28:1]

16- BI T MICROPROCESSOR

TX_EN

DEVICE I/O

TRANSMIT PATH

DS1/E1 TO

RECEIVE PATH

DEVICE I/O

SPE M APP ER TMUX

SPE MAPPER

TMUX

DS1/E1 FROM

SIG NAL IN G TO

FRAMERS

x28

SPE M AP PER

CROSS CONNECT

X28

X28X28X28

INTERFACE SIGNALING FROM

FRAMERS

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

430 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

19.4 VT /TU Mapp in g s

Table 551. VT2/TU-12 Payload Mapping

Table 5 52. VT1.5/TU-11 Payload Mapping

Column X 1 2 • • •2

2• • •2

8X2

9• • •4

3• • •5

6X5

7• • •6

4• • •8

J1 V

• • •V

Column X 1 2 • • •2

8X2

0• • •5

6X5

8• • •8

J1 V

• • •v

• • •V

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

431Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.5 VT/T U Locations

Table 553. VT2/TU-12 Locations

* Thi s c ol umn is for th e I/O of the VTMPR . The cross co nn ect can be

pr ovisi on ed to map any ext ern al E1 to any VT 2 .

†See VT2/TU-12 Payload Mapping on page 430.

Table 554. VT1.5/T U - 1 1 Lo cat ion s

* This column is for the I/O of the VTMPR. The cross connect can be

provisioned to map any external DS1 to any VT1.5.

†See VT1.5/TU-11 Payload Mapping on page 430.

VTG VT E1* Columns†

1 1 1 1, 22, 43, 64

2 1 2 2, 23, 44, 65

3 1 3 3, 24, 45, 66

4 1 4 4, 25, 46, 67

5 1 5 5, 26, 47, 68

6 1 6 6, 27, 48, 69

7 1 7 7, 28, 49, 70

1 2 8 8, 29, 50, 71

2 2 9 9, 30, 51, 72

3 2 10 10, 31, 52, 73

4 2 11 11, 32, 53, 74

5 2 12 12, 33, 54, 75

6 2 13 13, 34, 55, 76

7 2 14 14, 35, 56, 77

1 3 15 15, 36, 57, 78

2 3 16 16, 37, 58, 79

3 3 17 17, 38, 59, 80

4 3 18 18, 39, 60, 81

5 3 19 19, 40, 61, 82

6 3 20 20, 41, 62, 83

7 3 21 21, 42, 63, 84

VTG VT DS1* Columns†

1 1 1 1, 29, 57

2 1 2 2, 30, 58

3 1 3 3, 31, 59

4 1 4 4, 32, 60

5 1 5 5, 33, 61

6 1 6 6, 34, 62

7 1 7 7, 35, 63

1 2 8 8, 36, 64

2 2 9 9, 37, 65

3 2 10 10, 38, 66

4 2 11 11, 39, 67

5 2 12 12, 40, 68

6 2 13 13, 41, 69

7 2 14 14, 42, 70

1 3 15 15, 43, 71

2 3 16 16, 44, 72

3 3 17 17, 45, 73

4 3 18 18, 46, 74

5 3 19 19, 47, 75

6 3 20 20, 48, 76

7 3 21 21, 49, 77

1 4 22 22, 50, 78

2 4 23 23, 51, 79

3 4 24 24, 52, 80

4 4 25 25, 53, 81

5 4 26 26, 54, 82

6 4 27 27, 55, 83

7 4 28 28, 56, 84

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
432 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
19.6  VT/TU Mapper Receive Path Description
This section describes all necessary functions of the receive logic (see Figure 39, r ight to left):
■Virtual trib utary demultiplexor (VTDEMUX)
■Virtual tributary pointer interpreter (VTPI)
■Virtual tributary terminator (VTTERM)
■Output selector (OUTSEL)
■J2 16-byte sequence monitor (J2M ON)
■Receive VT/TU sign aling (RX_VT SIG)
■Receive low-order path overhead (RX _LOPOH)
19.7  VT Dem ult i plexe r ( V TDE M UX )
The VTDEMUX logic block (in Figure 39 on page429 ) will perform all necessary   functions to d eco de which virtual 
tributary (VT) is active on the data bus.
This block monitors t he H4 byte and frames  on t he H4 multiframe indicatio n. In frame (VT_H4LOMF = 0 
(Table 176)) wi ll be declared following two consecutive, nonerro re d multiframe indica tions. A multiframe indication 
consists of four consecutive frames containing a (00, 01, 10, 11) pattern in the two LS Bs of the H4 byte. Once 
framed, H4 loss of multiframe (VT_H4LOMF = 1) will be declared following the number of consecutive mismatches 
in the H4 multiframe indication programm ed int o bi ts VT_H4_NTIME[3: 0]  (Table 182). Loss  of H4 m ultiframe align-
ment will generate AIS downstream. A change in H4 multiframe alignment is  indicated by bit VT_H4LOMF_D 
(Table 168) and will generate an interrupt unless the mask is  set (VT_H4LOMF_M = 1  (Table 180)).
Bits VT_RX_GRP_TYPE[6:0] (Table 180) are programmed to determine whether the incoming tribut ary  is  a 
VT1.5/TU-11 or a VT2/TU-12.
See Table 551 through Table 554 on page 430 through page 431 for VT/TU mapping formats.
19.8  VT Pointer Interpreter (VTPI)
The VTPI logic b lock (in  Figure 39 on page429 ) will perform all necessary functions to support VT/TU pointer inter-
pretation. The following features are implemented:
The pointer interpreter consists of the following states:
■Loss of poi nter (LOP-V)
■VT-AIS (AIS- V ) (all o nes in V1  and V2)
■NDF enabl ed (NDF) ( 1001, 0001, 1101, 1011, 1000)
■Normal (NORM) (disab l ed NDF, normal pointer)
■Incr em ent  (INC ) (inverted I bits)
■Decrement  (DE C) (inverted D bits)

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

433Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

5-9007(F)

* Thi s st ate di ag r am is ba se d on th e ETS 4 17- 1- 1 poin t er int e rpreta ti on sta te diag r am (Fig ur e B. 1 ). Tra ns iti on s o f eig ht in val i d p ointers from the

INC, DEC, and NDF sta t es into t h e LO P st at e have b een ad ded .

Figure 4 0. Pointer Interpretation St ate D i agra m

■The pointer inte rpreter will transition into the LOP-V state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive super-

frame s p rogram me d in b its VT_ N DF_ NTIME[3:0] (Table 183) , then LOP -V wi ll be de clared.

— Invalid pointer value s. I f the number of consecutive superframes programmed in register bits

VT_INV_NTIME[3:0] (Table 183) are received with a pointer that is not a normal value, NDF, AIS-V, increment,

or decrement, then LOP-V will b e declar ed. The SS bits contribute to an invalid pointer indi cation.

■The pointer interpreter will transition out of the LOP-V s tate based on the following conditions:

— Following three c onsecutive superframes with all ones in the V1 and V2 bytes the pointer interpreter will tran-

sition from the LOP-V state into the AIS - V state.

— Following three new consecutive, consistent, and valid pointers the pointer interpreter will transiti on fr om the

LOP-V state into t he NORM state.

— The pointer interpreter

does n ot transition from the LOP-V sta te into the NDF state.

■The pointer inte rpreter will transit ion into the AIS-V state based on the following conditions:

— Fo llow ing thr ee consecutive superframes wi th all ones in the V1 and V2 bytes AIS -V will be decl ared.

■The pointe r inte rpreter will transit ion out of the AIS-V state based on the foll owing conditions:

— Following three new consecutive, consistent, and valid pointers the pointer interpreter will transiti on fr om the

AIS-V s tate into t he NORM state.

— Following the number of consecutive invalid pointers programmed in b it s VT_INV_NTIME[3:0], the pointer in-

terpreter will transi tion f r om the AIS-V state into the LOP-V s tate.

— If NDF is enabled on the incoming V1 and V2 bytes, the pointer i n t e r p reter will transition from the AIS-V state

into the NDF state.

NORM

DECINC

NDF

AISLOP

FROM ALL STATES

8 INVALID POINTERS

FROM ALL STATES

3 NEW POINTERS

INCREMENT DECREMENT

8 NDF ENABLE

NDF ENABLE

NDF

3 ANY 3 ANY

3 NEW POINTERS

3 ANY POINTERS

3 NEW POINTERS

8 INVALID

8 INVALID POINTERS*

INDICATION INDICATION

3 AIS INDICATIONS ENABLE

ENABLE

POINTERS POINTERS

POINTERS ENABLE

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

434 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

■The pointe r inte rpreter will transit ion into the NDF state based on the following conditions:

— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM, NDF,

AIS, INC, and DEC states into the NDF state.

■The pointer inte rpreter will transit ion out of the NDF state based on the followin g conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive super-

frame s p rogram me d in b its VT_ N DF_ NTIME[3:0] (Table 183), the pointer interprete r will transition from the

NDF state into the LOP-V state.

— Following any three consecutive, consistent, and val id pointers, the pointer interpreter will transition from the

NDF state into the NORM state .

— Following three consecutive superframes wi th all ones in the V1 and V2 bytes, the pointer interpreter will tran-

sition from the NDF state into the AIS- V state.

— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transiti on from the

NDF state into the NORM state .

— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 183), the

p ointer interpreter w ill t ra n s iti on from the N D F state into the LOP-V state.

■The pointer inte rpreter will transit ion into the NORM s tate based on the following conditions:

— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition into the

NORM state.

— Following any three consecutive, consistent, and val id pointers, the pointer interpreter will transition into the

NORM state. i.e ., transitioning from the INC, DE C, and NDF states.

■The pointer inte rpreter will transit ion out of t he N ORM state based on the foll owing conditions:

— Following the number of consecutive invalid pointers programmed in b it s VT_INV_NTIME[3:0], the pointer in-

terpreter will transition from the NORM state into the LOP-V state.

— If NDF is enabled on t he incoming V1 and V2 bytes, the pointer interpreter will tra ns ition from the NORM state

into the NDF state.

— Following three consecutive superframes wi th all ones in the V1 and V2 bytes, the pointer interpreter will tran-

sition from the NORM state into the AIS-V state.

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 181)), if 8 of the 10 I and D bits are correct

for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM

state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement

on the incoming V1 and V2 bytes, the pointer interprete r will transition from the NORM s tate into the DEC state.

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer

increment on the incoming V1 and V2 bytes, the pointer interpreter will tr ansit ion from the NORM state into the

INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming

V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the INC sta te.

■The pointer inte rpreter will transit ion into the INC state based on the following condit ions:

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer

increment on the incoming V1 and V2 bytes, the pointer interpreter will transition into the INC state. Otherwise,

if 3 of t he 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming V1 and V2 bytes, the

p o in ter inter p rete r will transition in to the IN C sta te.

■The pointer inte rpreter will transition out of the INC sta te based on t h e following conditions:

— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the INC state into

the NDF state.

— Following three consecutive superframes wi th all ones in the V1 and V2 bytes, the pointer interpreter will tran-

sition from the INC s tate into the AIS-V state.

— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transiti on from the

INC state into the NORM state.

— Following any three consecutive, consistent, and val id pointers, the pointer interpreter will transition from the

INC state into the NORM state.

— Following the number of consecutive invalid pointers programmed in b it s VT_INV_NTIME[3:0], the pointer in-

terpreter will transition from the INC state into the LOP-V state.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
435Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
■The pointer inte rpreter will transit ion into the DEC state based on the following  conditions:
— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 181)), if 8 of the 10 I and D bits are correct 
for a p ointer decremen t on the incoming V1 and V2 bytes , the pointer interpreter will transition into the DEC 
state. Otherwise,  if  3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement  on the incoming V1 
and V2 bytes, the poin ter i nterpr eter will transition  into the  DE C state.
■ The pointer interpreter will transition out of the DEC state based on  the following conditions:
— If NDF is enable d on the incoming V1 an d V 2 bytes, the pointe r  i nt e rpret er w ill tr ansiti on f rom the DE C state 
into the NDF state.
— Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will tran-
sition from the DEC state into the A IS-V state.
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transiti on from the 
DEC state into the NORM  state.
— Following any three consecutive, consistent, and val id pointers,  the pointer interpreter will transition from the 
DEC state into the NORM  state.
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 183), the 
p ointe r in terpreter will transiti o n  fr o m the DEC  sta te into  the LOP-V state .
Pointer increments and decrements are monitored and counted internally. The perf ormance monitoring reset signal 
transfers the count to the holding registers for pointer increment  (VT_PTR_INC[1—2 8][3: 0] (Table 208)), and 
pointer decrement (VT_PTR_DEC[1—28 ] [3:0 ] ( Table 208)) for microprocessor read and resets  the running count 
registers to 0. When SMPR_SAT_ROLLOVER = 1 (Table 67), the internal running  counts will hold at their maxi-
mum value. Otherwise, the counts will roll over. The run ning count and holding register counts wi ll be forced to 0, if 
the SPE mapper is requesting AUT O AIS or VT_LOP[1—28] = 1 (loss of pointer) (Table 177) or VT_AIS[1—28] = 1 
(V T AIS) (Table 177) (o r VT_H4 LOM F = 1 (l oss of H4  multiframe alignment) (Table 176)).
LOP-V (VT_LOP) and AIS-V (VT_AIS) will be detected and reported  t o  the microprocessor. Both the LOP-V and 
AIS-V conditions will contrib ute to the VT/TU mapper automatic AIS generation that is driven over a 28-bit internal 
output bus to the cross connect ( XC). Any change in state of V T_LOP or VT_AIS will be reported to the micropro-
cesso r via VT_LOP_ D[1—28] and VT _A IS_D[1 —28] (Table 169). Unles s  the approp riate mask bit is set 
(VT_LOP_M[1—28] or VT_AIS_M[1—28]) (Table 173),  VT _LOP_D[ 1—28] = 1 or VT_AIS_D[1—28] = 1 wil l gener-
ate an interrupt.
A check for VT/TU s i ze m is mat ch e s  is  p er formed by comparing  the expe cted  VT/TU size bits (V T1.5  = 11, 
VT2 = 10) with the actual  received SS bits in the V1 byte. After three consecutive mismatches, size errors will be 
reported with bit VT_SIZERR[1—28] (Table 177). A ny change in s tate of VT_SI ZE RR[1—28] will be reported with 
bit VT_SIZERR_D[1—28] (Table 169). Unless the VT_SIZERR_M[1—28] (Table 173) mask bit is set, 
VT_SIZERR_D[1—28] = 1 will generate a n interrupt.
The accepted pointer is stored and  accessible by the microprocessor.
This block supports tribut ary loopback.
19.9  VT  Ter m i nat i o n (V TTE R M )
The VTTERM logic bloc k (in Figure 39) will perform all necessary  functions to support complete VT/TU  termination.
 
The following features are impl emented.
19.9.1 V5 Termination
The  V5 byte is checked for BIP-2 errors. If  BIP-2 e rrors are detected, R EI -V is  tr ansmitted in the V5 byt e of the cor-
responding trans mit VT, if e nabled by bit VT_REI_EN[1—28] = 1 (Table 198). BIP-2 errors and  recep tion of  REI-V 
in the V5 byte is counted on a per-superfra me  b a sis. B IP -2 error s can counted  on either a bit or block basis 
selected by bit, VT_BIT_BLOCK_CNT (1 = bit, 0 = block) (Table 181).

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
436 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
BIP-2 errors and REI-V recep tion are  m onitored and counted internally.  Th e  performance monitoring reset signal 
transfers the count to the ho lding registers for BIP-2 error count (VT_BIP2ERR_CNT[1—28][11:0]; Table 206), and 
REI-V count (V T_REI_CNT[1 —28][10:0] (Table 207)) for microprocessor read,  and resets the ru nning count   regis-
ters to 0.  When SMPR_SAT_ROLLOVER = 1 (Table 67), the internal r unning counts will hold at their maximum 
value. Otherw is e, the cou nts will roll over. The running count and holding register counts will be forced  to 0, if the 
SPE mapper is requesting AUTO AIS, VT_LOP[1—28] = 1 (loss of pointer), VT_AIS[1—28] = 1 (VT AIS) 
(Table 177) o r VT_H4LOM F = 1 (los s of H4  multiframe alignment) (Table 176).
The  V5 byte will be checked for received  RFI-V via VT_RFI[1—28] bits (Table 177). New val u es will be latch ed  int o  
the register after the n umber of consecutive v alues programmed in bits VT_RDI_NTIME[3 :0] (Table 184) have been 
received. A VT_RFI[1—28] change of state is reported by bit VT_RFI_D[1—28] ( Table 169). When operating in the 
DS1 byte synchronous mode, RFI-V = 1 will f or ce DS1 RAI do wnstream to the framer . Unless the VT_RFI_M mask 
bit (Table 173) is set, VT_RFI_D[1—28] = 1 will generate and cause an interrupt.
When ope rating in normal RDI-V mode (VT_RX_ERDI_EN[1—28] = 1 (Table 204, starting on page168 )),  the V5 
by te  will be checked for received RDI-V and repo r ted v ia  VT_RD I[1—28] bits (Table 177).  New values will be 
latched to this regi s ter after VT_RDI_NTIME[3:0] consecutive values have b een rece ived. A VT_RDI[1—28] 
change of  state i s reported via VT_RDI_D[1—28]  (Table 169). Unless the VT_RDI_M[1—28] (Table 173) mask bi t 
is set, VT_RDI_D[1—28] = 1 will generate and cause an interrupt.
When operating in enhanced RDI-V mode (VT_RX_ERDI_EN[1—28] = 0 (Table 204, starting on page168 )), the 
V5 byte wil l be checked for received RDI-V and reported via VT_RDI[1—28] bit (Table 177). Ne w va lues will be 
latched to this regis ter after VT_ERDI_NTIME[3: 0] (Table 184) consecutive ERDI-V  values (V5 bit 8 and Z7  bits 
5—7)  h a v e  been recei ved. A VT_ERDI[1 —28][2:0] change of state is reported v ia VT_ERDI_D[1—28] (Table 169). 
Unless the VT_ERDI_M[1—28]  mask bit (Table 173)  i s set, V T_ E RDI_D[ 1—28] = 1 will generate and cause an 
interrupt.
The V5 byte VT/TU signal label will be monitored and reported to the microprocessor using bits 
VT_LAB[1—28][2:0] (Table 177). New values  will be lat c hed to the microprocessor after the number of consecutive 
values   programmed in bits VT_LAB_NTIME[3:0] (Table 184) have been received. An all zeros signal label will set 
bit VT_UNEQ[1—28] (Table 177). Any change in state of VT_UNEQ[1—28] wi ll be reporte d t o the micro processor  
via bit VT_UNEQ_D[1—28] (Table 169). Unless the V T_UNE Q_M[1—28] (Table 173) mask bit is set, 
VT_UNEQ_D[1—28] = 1 will generate an interr upt.  VT_UNEQ[1—28] will co ntribute to automatic AIS generation. 
The latched signal label will be compared to the expected signal label. If the ex pected signal label is 001 or if 
VT_UNEQ[1—28] is detected, the detection of PLM-V is disabled. Otherwise,  any mismatch is r eported to the 
micro processor via bit VT_PLM[1—28] (Table 177). Any change in s tate of VT_PLM[1—28 ]  will be rep orted to the 
micro processor via bit VT_PLM_D[1—28] (Table 169). Unless the VT_PLM_M [1 —28]  mask bit is set (Table 173), 
VT_PLM_D[1—2 8] = 1 w ill generate a n interrupt.
19.9. 2 Z 6/ N2 Termi nation
For SONET applications, the Z 6 byte is monitored and presented to the microprocessor using bits 
VT_Z6_BYTE[1—28][7:0] (Table 205)  for growth and m o nitoring purposes only. The Z6 byte is updated to when 
three consec ut ive consistent bytes are received. N2 is def ined for ta ndem connection appli cations per 
ETS 300 417-1-1 and ITU-T G.707/G.783. Low-order tandem connection is not supported. 
19.9. 3 Z 7/ K4 Termi nation
This te rmination will support enh anced RDI when bit VT_RX_ERDI_EN[1—28] = 1(Tab l e 204, starting on 
page 168). The Z7/ K 4[3:1] byte will be monitored and reported to the microprocessor with bits 
VT_ERDI[1—28] [2:0]  (Table 177). New values will be latched to the microprocessor after the number of consecu-
tiv e v alues progr ammed in register  bits VT_ERDI_NTIME[3:0] (Table 184) hav e been receiv ed. A change of state is 
reported using bit VT_ERDI_D[1—28] (Table 169). Unless the VT_ERDI_M[1—28] (Table 173) mask bit is set, 
VT_ERDI_D[1—28] = 1 will generate an interrupt.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
437Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
The Z7/K4[7:4] byte will be monitored and reported to the microprocessor via bits VT_AP S[1—28][3:0]  (Table 178). 
New values will be latched to the microprocessor after the number of consecutive values programmed in bits  
VT_ APS_NTIME[3 :0] (Table 184) have been received. A change of state is reported using bit VT_APS_D[1—28] 
(Table 169). U n less the VT_A PS_ M[1—28] (Table 173) mask b it is set, VT_APS_D[1—28] = 1 will generate an 
interrupt.
19.9.4 Payload Termination
Payload termination will support asynchronous, byte synchronous, and bit synchronous demappings  for SONET 
VT1.5s and VT 2s per 
Bellcore
 GR-253 and ANSI T 1.105.
Payload termination will support asynchronous, byte synchronous, and bit synchronous demappings  for 
SDH T U11s   and TU12s per I TU-T G.707 a nd ET S  300  417 -4-1.
Demappin g modes are selected with bi ts VT _RX_MAPTYPE[1—28][3:0] (Table 204, starting on page168 ), as 
defined in Table 555.
Table 555. R eceive VT/TU Demapping Sele c ti on
The payload termination provides an elastic store for r at e adoption. An elastic store o verflow is indicated in bit 
VT_RX_ESOVFL_D[1—28] (Table 169). Unl e ss th e  VT _ RX_ ESOVFL_M[1—28] mask bit is set (Table 173), 
VT_RX_ESOVFL_D[1—28] = 1 will generate an interrupt.
When an o verflow condition  exists,  the read/write count will b e  forced to the center of the FIFO . The FIFO is 64 bits 
deep.
The payload termination circuitry will generate a gapped D S1/E1 clock  (VT_TERM_CLK). Figure 41 and Fig ure 42 
on page451  descri be the DS1 and E1 gapped clocking schemes, respectiv ely. A frame sync is generated and 
transmitted from the de v ice coincident with the frame bit for DS1 and the MSB of time slot 0 for E 1 when demap-
ping a byte synchronous payload.
19.10  O utput  S ign al S el ection (OU TSE L)
The OU TSE L l ogic block (in Figure 39 on page429 ) will perform all n ec essary functions t o overwrite the outgoing 
DS1/E1 signals with the appropriate AIS clock, data, and frame synchronization.
VT_RX_MAPTYPE[1—28][3:0] (See Table 204.)Description
0 0 0 0 A sy nchronous  VT1. 5/TU-11 (DS1 output)
0 0 0 1 A s y nc hronous VT2/TU-12 (E1 output)
0 0 1 0 Byte synchronous VT1.5/TU-11 (DS1 output)
0 0 1 1 B y te  sync hronous  VT2/TU-12 (E1 output)
0 1 0 0 B it synchronous VT1. 5/ TU-11 (DS1 outp ut)
0 1 0 1 B it synchronous V T2/TU-12 (E1 output)
0110—0111 Und efined,  ge nerates AIS
1 0 0 0 Asynchronous VT2/TU-12 (DS1 outpu t)
1 0 0 1 B y te  sync hronous   VT2/TU-12 (DS1 o utput)
1 0 1 0 Bit synchronous VT2/TU-12 (DS1 output)
1011—1111 Und efined,  ge nerates AIS

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
438 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
VT/TU mapper automat ic  AIS, which is driven over a 2 8-bit internal output bu s to the  c r oss connect (XC), is  gener-
ated according to the following equation:
SPEMPR_AUTO_AIS
or 
VT_LOP[1—28] 
or 
VT_AIS[1—28] 
or 
(VT_H4LOMF and (VT_LOMF_AIS_INH)) 
or 
(VT_UNEQ[1—28] and  (VT_UNEQ_A IS_INH)) 
or 
(VT_PLM[1—28] and (VT _P LM_ AIS_INH)) 
or 
(VT_J2TIM[1—28] and (VT_J 2TIM _AIS _IN H)) 
or 
(VT_LOPS[1—28] and VT_LOPS_AIS_INH))
The  output of the VT/TU mapper receive path will be as shown in Figure 43 on page451  and Figure 44 on 
page 452.
19.11  J2 Byte Monitor a nd Termination (J2MON)
Th e J2M O N lo gic block ( i n   Fig ure 39 on page429 ) will perform all necessary functions to monitor the incoming J2 
trace identifier. The following features are implement ed:
■J2 monitoring will support five different monitor ing modes defined by VT_J2MON_M ODE[1—28][2:0] Table 204 
on pag e168:
— VT_J2MON_MODE[1—28][2:0] = 000: this mode captures an incoming 16-byte sequence and stores it in 
VT_J2BYTE_DET[1—28][1—16][7:0] (Table 209). TIM-V  is disabled for this mode.
— VT_J2MON_MODE[1—28][2:0] = 001: this mode captures an incoming 16-byte sequenc e with SDH framing 
and s tores i t in VT_J2BYTE_DET[1—28][1—16][7:0]. TIM-V is disabled for this m ode.
— VT_J2MON_MODE[1—28][2:0] = 010: this mode captures a constant 1-byte sequence and stores it in 
VT_J2BYTE_DET[1—28][1][7:0] . TI M-V is di s abled for this mod e.
— VT_J2MON_MODE[1—28][2:0] = 011: this mode monitors a  16-byte se quenc e with SDH framing and co m-
pares it to a pr ogrammable expected value. The expected value is programmed by the user using register  bits 
VT_J2BYTE_EXP[1—28][1—16][7:0] (Table 209). The hardware  frames by looking for the b yte   with the MSB 
set to one, which indicates that the next byte is the s e cond byte of the message. CRC is verified based on the 
value pro grammed in VT_J2BYTE_EXP[1—28][1—16 ][7:0]. T IM-V  is enabled for this mode.
— VT_J2MON_MODE[1—28][2:0] = 100: this mode monitors a constant 1-byte sequence and compares it to an 
programmabl e expected value. The expected value is progr amme d  b y  the user using register bits 
VT_J2BYTE_EXP[1—28][1][7:0]. T IM-V is enabled for this mode.
■Trace ident ifier mismatch (T IM-V ) will be d etected following the number of consecutively  errored  sequences
(1-byt e or 16-byte sequences) programmed in  bits, VT_J2_NTIME [3 :0 ] (Table 183),  and reported to the micro-
processor via bit VT_J2TIM[1—28] (Table 177). If TIM-V is detected, the J2  byte monitor will transition into the 
capture mode and star t searching for two consecutive consistent 1-byte or 16-byte sequences. Once  two con-
secutive consistent sequences ar e detected, the J2 byte monitor will t ra nsition into the monito r mode and start 
searchin g for the number of consecutive m ismatc hes   programmed in register bits VT_J2_NTIME[3:0], on a per 
1-byte or 16-byte sequence basis.
 
Once the hardware finds synchron i zation (VT_J2TIM[1—28] = 0), the new 
sequence is latched into VT_J2BYTE_DET[1—28][1—16 ][7:0] (Table 209). The synchronization algorithm used 
will not allow single bit errors to pa ss through to VT_J2BYTE_DET[1—28][1—16][7:0]. 

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
439Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
■Unless bit VT_J2 TIM_AIS_INH (Table 181) is set to a 1, VT_J2TIM[1—28] will co ntr ibute to automatic AI S gen-
eration.
■Any change in state  o f  VT_J2TIM[1—28][1—16][7:0] wil l be reported in bit VT_J2TIM_D[1—28] (Table 169). 
Unless the VT_J2TIM_M[1—28] (Table 173) mask bit is set, VT_J2TIM_D[1—28]  = 1 will generate an interru pt.
19.12  Receive Signal ing (RX_VTSIG)
The RX_VTSIG logic b l ock (in Figure 39 on page429) will perform all necessary functions to extract and transmit 
the received signaling bits when operating in DS1 byte-synchronous mode. The following features  are imple-
mented:
■The signal ing i s sent to the appropriate framer link selected by bits VT_RXSIG_CH_SEL[1—28][4:0] (Table 204). 
VT_RXSIG_CH_SEL[1—28] [4:0] is a necessary duplication of the routing information programmed within the 
cross conne ct (XC) block.
■When VT _SYNC_PBIT[1—28] = 1 (Table 204 on page168 ),  the R X_V TSIG  bloc k wil l sync h ronize to the incom-
ing VT/TU ph ase  indicat ion (P1, P0). Otherwise, VT_LO PS[1—28] (Table 177) and VT_LOPS_D[1—28] 
(Table 169) will be for ced to 0.
■P-bit phase synchronization (VT_LOP S[1—28] = 0) is  declared following two consecutive nonerrored multi-
frames (48 frames). Loss of pha se synchronization (VT_LO P S[1—28]  = 1) is declared following the number of 
consec utive errored multiframes programmed i n bits VT_LOPS_ NTIME[3:0] (Table 182). Any change in 
VT_LOPS[1—28] state will be detected and reported to the m icroprocessor  with bi t V T_ LOPS_D[1—28].
■If the loss of phase synchroniz atio n (VT_LO PS[1—28 ]  = 1)  conditio n exists and VT_LOPS_AI S _I N H =  0,  DS 1 
AIS is transmitted downstream and the signaling bits wi ll be forced to the value in SMPR_OH_DEFLT (Table 67) 
in the MPU block. Otherwise (VT_LOPS[1—2 8 ]  =  0), the  VT_ RX_VT SIG logi c  bloc k will behave as described in 
Table 556 below.
■Unless VT_LOPS_M[1—28] (Table 173) mas k bit is set, VT_LO PS_D[1—28 ] will generate an interrupt.
■See Table 556 below for s ignaling behavior based on the receive   status and control.
Table 5 56. Rx Signaling Behavior per Channel
* If the P1 and P0 bits are not used for phase indication and the F bit is not passed transpare ntly,  the F bit is overwritten with  the appropriate SF 
or ESF framing pa tt e rn ba se d on a rand om  sta rtin g pos itio n. Robb ed - b it si gn al ing  w i ll  not be ac c es sible  un de r  suc h  a co ndit ion.
†When operating in the  ESF mode, the Ft bits will be overwritten with the  ESF frame and the C and M  bits passed transparently.
VT_SYNC_PBIT
[1—28] 
(Table 204)
VT_WR_FBIT
[1—28] 
(Table 204)
VT_SF_ESF
[1—28] 
(Table 204)
VT_LOPS
[1—28] 
(Table 177)
Action
0 0 X X Pa ss F-bi t transparently.
0 1 0* X Overwrite outgoing F bit with ESF pattern.
0 1 1 X Overwrite outgoing F bit with SF pattern.
11
0†0 Overwrit e outgoing F bit with  ESF pattern.
1 1 1 0 Overwrite outgoing F bit with SF pattern.
1 X X 1 Transmit DS1 AIS downstream.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

440 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

19.13 Receive Lower-Order Path Overhead (R X_ LOPOH)

The RX_LOPO H l ogic block (in Figure 39 on page429 ) will perform all necessary functions to store and transmit

the ov erhead associated with each VT/TU , specifically, V5, J2, Z6/N2, Z7/K4, and the O bits. The f ollowing features

will be implemented:

■V5, J2 , Z6/N2, Z7/K4, and the 0 bit s, on a per VT basis, a re stored for one compl et e superframe and tran smitted

during the next superframe . R E I and RDI values received from the SPEMPR and TMUX are stored on a per-

frame basis and transmitted during the next frame. REI and RDI values are latched during the A1 time of the of

the received SONET frame.

■When operating in UPSR mode (bit VT_UPSR = 1 (Table 173)), REI, RDI, and ERDI values in the V5 and Z7

bytes will be modified based on the receive status. See Table 561 on page 444 for automatic generation require-

ments.

■The REI and RDI received from the SPEMPR and TM UX blocks is the first data type transmitted in each frame

as a burst of 34 bits on the rising edge o f the SPE mapper R x clock (6.48 MHz). All other data ty pes a re transmit-

ted as a b urs t of 224 bits on the rising edge of the SPE mapper Rx clock.

Note: The number o f valid bits transmitted i s dependent upon the VT/TU group types. i.e., f ull VT2 equals 168 bits.

■The firs t frame of the f our frame multiframe contains data types 001, 010, 011, and 100, respectivel y. The sec ond

frame of the multiframe contains data types 001, 101, an d 11 0, respectively. The remaining fr ames contai n only

data type 001 . Data type headers will be defined as shown in Table 557 below.

A l l data type s mu st be transmi tte d within 500 µs.

Table 557. Data Type Header Definitions

* A ll overhe ad byt es will be t rans mi t ted fr om MS B to L SB .

†O bits are r eceived in the byte following J2 and the byte following Z6/N2 in asynchronous mode. The O bi t s will be tran smitt ed in th e or d er of

whi ch they are r e ce ive d with in a VT, st arting w ith th e MSB of the ni bble foll owing t he J 2 byte.

Figure 45 o n p a g e452, contains the RX_LOPOH bloc k serial channel format and timing.

19.14 VT/TU Ma pper Transmit Path Re quiremen ts

This section d e scribes all necessary functions of the transmit logic (see Figure 39 on page429, left to right ).

■ Input selector (INSEL)

■ Transmit elastic store (TES)

■ Virtual tributary generator (VTGEN)

■ Virtual tributar y multiplexer (VTMUX)

■ Transmit DS1/E1 signaling (TX_VTSI G)

■ Transmit low- order path overhead (TX_LOPOH)

Header Description

0 0 0 Reserved.

0 0 1 TMUX and SPE mapper RDI/REI.

0 1 0 V 5 byte, 28/21 bytes starting with VT 1*.

0 1 1 J 2 byte, 28/21 bytes starting wit h VT 1.

1 0 0 Z6/N2 byte, 28/21 bytes starting with VT 1.

1 0 1 Z7/K 4 byte, 28/21 bytes starting with VT 1.

110

O bits, 28/21 bytes s tarting with VT 1†.

1 1 1 Reserved. Data will be ignored.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
441Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
19.14.1 I nput Selector (INSEL)
The INSEL logic block (in Figure 39 on page429 ) w ill perform los s  of clock ( L OC) , AIS, and los s of  fr am e  sync 
detection. The following fea tures  will be implemented:
■The incom ing DS 1/E1 signal will be retimed immediately  using the selected DS1/E1 clock edge 
(VT_TX_CLKEDGE[1—28] (Table 198)). If VT_TX_CL KEDG E[ 1 —28] = 1, the rising edge of the i ncoming 
DS1/E 1 CLOCK is used to retime the signal; otherwise,  the falling edge is used.
■The inc oming DS1/E1 signals will be checked for a digital loss of   clock (LOC ) condition and repor t e d  wi th bit 
VT_TX_LOC[1—28] (Table 179). Any change in state of VT_TX_LOC[1—28 ]  will be reported to the microproces-
sor via b it VT_TX_LOC_D[1—28] (Table 171). Unless the VT_TX_LOC_M[1—28] (Table 175) mask bit is set, 
VT_ TX_LOC_D = 1 will generate an interrupt.
■If LOC is detected (VT_TX_LOC[1—28] = 1),  DS1/E1 A IS will be inserted in the app ropriate transmit path VT. 
DS1/ E1 AIS consist s of   a valid VT/TU pointer,  valid VT/T U  overhead, and an all  ones payload.
■In the byte-synchronous   mode, t he incoming DS1/E1 frame sync is monitored for the loss of frame sync condi-
tion (LOFS) and reported in bit VT_L OFS[1—28] (Table 179). I n fr ame sync, (VT_LOFS[1—2 8] = 0) is declared 
following three c onsecutive valid frame sync pulses (375 µs). Loss of frame sync  (VT_LOFS[1—28] = 1) is 
declared follo wing six consecutive frame sync mismatches (750 µs). Any change in state of VT_LOFS[1—28] will 
be reported in b it VT_LOFS_D[1—28]  (Table 171). Un less t he VT_LO FS_M [1—28] (Table 175) m ask bit is set, 
VT_LOFS_D[1—28] = 1 will g enerate an interrupt.
■If LOFS is detect ed (VT_LOFS[1—28] = 1), AIS-V is inserted in the appropriate VT location.  AIS-V consists of 
wr iting an all ones pattern into the entire V T,  including V1~4.
■The incom ing DS 1/E1 signal will be checked for the A IS  co ndit ion and reported in bit VT_TX_AIS[1—28] 
(Table 179). Any  change in stat e of  V T_TX_AIS[1—28]  is reported in bit VT_TX_AIS_D[1—28] (Table 171). 
Unless the VT _TX_AIS_M[1—28] (Table 175) mask bit is set, VT_TX_AIS_D[1 —28] = 1 will generat e an inter-
rupt.
■If the incoming data is DS1, AIS  will be declared if there are less than n ine  ze ro s  ou t  o f 8 192 cl o c k p e ri ods . I f the  
in comin g  data is  E1, AIS will be declared if  there are less than three   zeros in  each of two con secutive 512-bit 
per iods and cleared when  each of two consecutive 512-bit periods  contain more than two zeros. 
Transmit mapping modes are shown in Table 558 below.
Table 558. Transmit VT/TU Mapping Selection per Channel, VT _TX_MAPTYPE[1—28][3:0]
VT_TX_MAPTYPE[1—28][3:0] (See Table 198.) Description
0 0 0 0 As ync hronous VT 1.5/TU -11 (DS1 input).
0 0 0 1 A s y nchronous VT2/TU-12 (E 1 input).
0 0 1 0 Byte synchronous VT1.5/TU-11 (DS1 input).
0 0 1 1 Byte synchronous V T2/TU-12 (E1 input).
0 1 0 0 Bit   synchrono us  VT1.5/TU-11 (DS1 input).
0 1 0 1 B it synchronous VT2/TU-12 (E1 input).
0110—0111 Und efined, generates VT1.5/TU-11 UNEQ-V.
1 0 0 0 Asynchronous VT2/ TU-12 (DS 1 input).
1 0 0 1 Byte synchronous V T2/TU-12 (DS 1 input).
1 0 1 0 Bit   synchrono us  VT2/TU -12 (DS1 input).
1011—1111 Und efined, generates VT2/TU-12 UNEQ-V.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
442 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
19.14.2 Transmit Elastic Store (TES)
The TES logic b l ock (in Fi gure 39 on pag e429) will perform all fun ction s necessary   to synchronize the incoming 
DS1/E1  or  VT1.5/VT2 signals to the local STS-1/STS-3 clock.
■This logic block will support the following modes of operation:
— Async hronous, bit synchronous, and byte synchronous  mapping fro m DS1/E1 input.
— Async hronous, bit synchronous, and byte synchronous mapping from loopback VT1.5/VT2 input.
The TES  logic block has programmable stuffing thresholds. The value programmed in the VT_HIGH_THRES[6:0 ] 
(Table 210) controls positive j ustification. The value programmed in the VT_LO W_THRES[6:0] (Table 210) controls 
negative ju stification. The recommended v alues  for nontributary loopback  (VT_LB_SEL[1—28] = 0 (Table 198)) are 
VT_HIGH_THRES[6:0] = 0x28 and VT_LOW_THRES[6:0] = 0x2 7. Otherwise ( VT_LB_SEL[1—28] = 1), the r ec-
ommen ded values are VT_HIGH_THRES[6:0] = 0x05 and V T_LOW_THRES[6:0]  = 0x04 .
The TES logic blo ck monitors for elastic store overflow co nditions and report s w ith bit  VT_TX_ES OVFL_E[1—28] 
(Table 171). Unless the VT_TX_ESOV FL_M[1—28] (Table 175) mask bi t is set, VT_ TX_ESOVFL_E [1—28] = 1 will 
generate and interrupt.
19.14.3 V irtual Tributary Gen erator (VTGEN )
The VTGEN logic block (in Figure 39 on page429 ) performs all fun ction s necessary to map all possible  DS1/E1  
inputs to the appropriate VT/TU structure. This i nc ludes VT/TU pointer generation, positive/negative stuffing, 
VT/TU overhead  gen eration/insert ion and DS1/E1 dat a insertion. The following features will be implemented:
■This logic block will support the following modes of operation:
— Asynchronous
— Byte sync hronous
— Bit synchronous
19.14.4 Pointer Generation
■The pointer  generat or will support the following features when operating in asynchronous or bi t sy nchronous  
mode:
— If transmit AIS-V is not requested, the follow ing requirements apply:
1. A  fixed pointer value of decimal 78 is   generated for VT1.5/ TU-11 mappings.
2. A  fixed pointer value of dec im al 105 is generated fo r VT2/TU-12 mappings.
3. The VT size field will be set to binary 11 for VT1.5/TU-11 mappings.
4. The VT size field will be set to binary 10 for  VT2/TU- 12 mappings.
5. The new data flag (NDF) set to bina r y 0110 for VT 1.5/VT2 mappings.
6. V 3 and V4 is s et to the selected overhead default (SMPR_OH_DEFLT (Table 67) i n t he micro processor inter-
face block) for all mappings:
— If transmit AIS-V is  requested, V1~V4 will be forced to 0xFF.
— Bit stuffing, using the C and S bits, will be performed based on the fullness of the elastic store.
■The pointer  generatio n will support the following features when operating in byte synchronous  mode:
— If transmit AIS-V is not requested, the follow ing requirements apply:
1. The pointer value is  generated bas ed on the locat ion of the incoming frame sync for VT1.5/VT2 m apping s.
2. The VT size field is set to 11 for VT1.5/TU-11 mappings.
3. The VT size field is set to 10 for VT2/TU-12 mappings. 
4. The new data flag (NDF) i s   set to 0110 for normal VT1.5/VT2 mappings. If a NDF  is requeste d, the NDF will 
be set to 1001 (bin ary).

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
443Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
5. If an in c rement is r equeste d, the pointer bytes, V1 and V2, are programmed with the I-bits inverted. The 
pointer action byte, V3, will be programmed to the selected default (microprocessor bit 
SMPR _FXD_S TFF_DEF LT ( Table 67)), as well as the byte directly following V3. Ho we ver ,  when incrementing 
from 139 to 0 for VT2 mapping, the  pointer generat or sends out NDF-V indication with the correct point er (0) 
instead of the incre ment indication.
6. If a  decrement  is requested, the pointer b ytes,  V1 and V2, will be programmed with the D bits in verted. The 
pointer action byte, V3, wi ll be programmed to actual customer data. However, when decrem enting from 0 to 
139 for VT2  mapping, the pointer generator sends out NDF-V  indi ca tion with the correct pointer (139) instead 
of the decrement indi cation.
7. The V4 byte will be programmed to the selected overhead default (microp ro cessor bit SM PR_OH_DEFLT) for 
all mappings.
— If transmit AIS-V is requested, V1~V4 will  be for ced to 0xFF.
Overhead Byte Generation (V5, J2, Z6/N2, Z7/K4, and O bits). This p o rtion of the VTGEN  logic block will gener -
ate and i nse rt the V5, J2, Z 6/N2, and Z7/K4 overhead bytes  into the appropriate virtual tri butary. O  bits are only 
accessible in the asynchronous and bit synchronous   mode s.
V5 Overhead Byte Format/G eneration. The V5 overhead byte will be mapped as  defi ned in Table 559.
Table 5 59. V5 O verhead Byte Form at
The following features are supported:
■Whe n operating in tributa ry  loopback mode (bit VT_LB_SEL[1—28] = 1 (Table 198)), all bits are simply passed 
through transparen tly.
■When operating in   UPSR mode VT_V5_INS[1—28]  = 1 (Table 199), only a new B IP-2 and  signal label is gener-
ated and inserted while all other bits are programmed fr om t he received LOPOH serial acce ss channel storage. 
BIP-2 will be automatically calculated and inserted. The signal label is determined based on bits 
VT_TX_MAPTYPE[1—28][3:0] (Table 198) and automati c ally inserted.
■AIS-V is f orced by setting b it, VT_AIS_INS[1—28] (Table 198) to a 1. AIS- V consists of overwriting the entire VT, 
inclu din g V1~4 , with al l ones.
■Bits VT_ TX_MAPTYPE[1—28][3:0] may   be programmed to insert an UNEQ-V  signal label. See Tab le 562, VT 
Signal Label Definition on page445 .
■User-controlled bits VT_BIP2ERR_INS[1—28 ][1:0] ( Table 199) will force BI P-2 errors for t roubleshoot ing pur-
poses. See Table 560 below for error i ns ertion modes.
Table 560. BIP-2 Error Insertion M odes
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit  8
BIP-2 REI-V RFI-V SIGNAL LABEL RDI-V
VT_BIP2ERR_INS[1—28][1:0] (See Table 199.) Action
00 No B IP-2 errors inserted.
01 Insert continuous BIP-2 error s.
10 Insert BIP-2 error s based on microprocessor register bit 
SMPR _BER_INSRT (Table 65).
11 No B IP-2 errors inserted.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
444 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
■When operating in   UPSR mode VT_V5_INS[1—28] = 1, REI-V is set to the value in the received LOPOH serial 
access  channel storage when enabled by bit, VT_ REI_EN[1—28] =1 (Table 198). When opera ting in normal 
mode VT_V 5_INS[1—28] = 0, REI-V is set to 1 for any  detected BIP-2 errors in the corresponding received VT 
when enabled by bit,  VT_REI_EN = 1. Otherwise, the REI-V bit is set to  0.
■RF I-V is s upported. Manual control of the RFI-V bit is enabled with bit VT_RFI_EN[1—28] = 1 (Table 198).  T he 
RFI-V bit is programmed with the value of bit VT_RFI_INS[ 1—28] (Table 200). When VT_RFI_EN[1—28] = 0 and 
operating in UPSR m ode VT _V 5_INS[1—28] = 1, RFI-V is set to the value in the received LOPOH  serial access 
channel storage. Otherwise, RFI-V is automatically gener ated and inserted as defined in Table 561 on page 444. 
When operat ing in b yte synchr onous mode, RFI- V is also based on the incoming DS1 RAI from the framer.
■One bit RDI-V is supported when bit  VT_TX_ERDI_EN[1—28] = 0  ( Table 198). Manual control of the RDI-V bit is 
enabled with bit VT_RD I_EN[1—28] =1 (Table 198). The RDI_V bit  is  programed with the value of bit 
VT_RDI_INS[1—28] (Table 200). When VT_RDI_EN[1—28] = 0 and operating in UPSR mode 
VT_V5_INS[1—28]  = 1 (Table 199), RD I-V is set to the value in the received LOP OH serial access channel stor-
age. O therwise, RDI-V is automatically generated and inse rted   as d efined in Table 561 below.
■Enhanced RDI will be supported when bit VT_TX_ERDI_EN[1—28] = 1. Manual control of the ERDI bits 5, 6, 
and 7 of the Z7 byte is enabled with bit VT_ERDI_EN[1—28] = 1  ( Table 198). T he ERDI bits, in bit positions 5, 6, 
and 7 of the Z7 byte are programed with the value of bits VT_ERDI_INS[1—28][2:0] (Table 200),  r e spective ly.  
When VT_ERDI_EN[1—28] = 0 and operating in UPSR mod e VT_V5_INS[1—28] = 1 (Table 199), ERDI-V is set 
to the value in the received LOPOH serial  access channel storag e. Otherw ise, bits 5, 6, and 7 of the Z7 by te are 
automatically generated and inserted a s defined in Table 561 below.
Table 561. RDI-V, RFI-V, and REI-V Au tomatic Generation
Remote Error Indication
REI-V Anomaly/defect.
0 No BIP-2 errors detected.
1 BIP-2  errors detected.One Bit Remo te Failure Indication
RFI-V Anomaly/defect.
0 No alarms.
1 AIS-V, LOP -V, U NEQ -V, PLM- V or automatic AIS detected from S PEM PR .
One Bit Remote Defect Indication
RDI-V Anomaly/defect.
0 No alarms.
1 AIS-V, LOP-V, UNEQ -V, o r TIM-V.
Enhanced Remote Defect Indication  (
Bellcore
 GR-253)
RDI-V
(V5 bit 8) RDI-V
(Z7 bit 5) RDI-V
(Z7 bit 6) RDI-V
(Z7 bit 7) Anomaly/defect
0 0 0 1 No def ects.
0 0 1 0 PLM-V (VT payload mismatch).
1 1 0 1 AIS-V or LOP - V.
1 1 1 0 UNEQUIP-V or TIM-V.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
445Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
■The signal label will be automatically  generated based on  bits VT _TX_MAPTYPE[1—28][3:0] (Table 198). The 
values suppo rted are defined in Table 562.
J2 Overhead Byte Insertion . Three modes of programming the J2 by te as  defined in Table 563 will be supported.
Table 563. J2 Overhead Byte Insertion Modes Per Channel
Z6/N2 Overhead Byte Insertion. The modes of programming t he Z6/N2 byte, de fined in Table 564 are supported.
Table 5 64. Z6/N2 Overhead Byte Insertion Modes Per Channel
Table 562. VT Signal Label Definition
V5(5) V5(6) V5(7) Description
0 0 0 Unequipped
0 0 1 Equipped Nonspecific
0 1 0 Asynchronous  DS1
0 1 0 Asynchronous  E1
0 1 1 Bit s ynchronous DS1
0 1 1 B it sy nchronous E1
1 0 0 Byte synchronous  DS1
1 0 0 Byte synchronous  E1
Others Undefined
VT_J2_INS[1—28][1:0] 
(See Table 199.) Insertion Mode
00 Def ault based on SMPR_OH_DEFLT (Table 67).
01 Microprocessor insert (VT_J2BYTE_INS[1—28][1—16] [7:0 ] (Table 203)).
10 LOPOH serial access channel inse rt.
11 Def ault based on SMPR_OH_DEFLT.
VT_Z6_INS[1—28][1:0] 
(See Table 199.) Insertion Mode
00 Default based on  SMPR_OH_DEFLT.
01 Insert from bits VT_Z6BYTE_INS[1—28][7:0] (Table 201).
10 LOPOH serial access channel insert.
11 Reserved.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
446 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
Z7/K4 Overhead Byte Insertion. Three modes of   programming the Z7/K4 APS bits are supported and controlle d 
by  register bits VT_Z7_INS[1 —28][1:0] (Table 199) as defined in Table 565.
Tabl e  565. Z7/K4 Overhe ad By te Insertion Modes Per Channel
Note: When bits Z7_INS[1—28][1:0] = 01, the AP S bi t s in the Z7/K4 byte (bits  1:4) are based on 
VT_APS_INS[1—28][3:0] (Table 200), while Z7/K4 bits 5:7 are either automa tically inserted  (when 
VT_ERDI_EN[1—28] = 0 (Table 198)and VT_TX_ERDI_EN[1—28] = 1 (Table 198)) or insert ed based on 
VT_ERDI_INS[1—28][2:0] (Table 200) (when VT_ERDI_EN[1—28] = 1). In all other modes,  al l  bits are ov er-
written.
O-bit Insertion (Asynchronous /Bit Sy nc hronous Mode s  Only) .  Three modes of programming the O bits, 
defined in Table 566 will be supported.
Table 566. O-Bit Insertion Modes Per Channel
VT Mappings. Detailed mapping format s are shown in Table 567 through Table 573, where:
I = information bit.
O = overhead bit.
R = fixed stuff bit.
P = phase bit.
S = signaling bit.
F = frame bit.
S1, S2 = stuff bits.
C1, C2 = stuff indication bits.
V 5 = VT overhea d byte.
J2 = VT p at h trace byte.
Z6/N2 = growth/tandem byte.
Z7 /K4  = ERDI/ APS b yte.
V1, V2 = poin te r  bytes .
V3 = pointer action byte.
V4 =  reserved.
VT_Z7_INS[1—28][1:0] 
(See Table 199.) Insertion Mode
00 Def ault based on microprocessor bits SMPR_OH_D EFLT (Table 67).
01 Insert from bits VT_APS_INS[1—28][3:0] (Table 200) and 
VT_ERDI_INS[1—28][2:0] (Table 200).
10 LOPOH serial access channel insert.
11 Def ault based on microprocessor bits SMPR_OH_DEFLT.
VT_O_INS[1—28][1:0] 
(See Table 199.) Insertion Mode
00 Def ault based on microprocessor bits SMPR_OH_DEFLT.
01 Insert from bits VT_OBIT_INS[1—28][7:0] (Table 201).
10 LOPOH serial access channel insert.
11 Def ault based on microprocessor bits SMPR_OH_DEFLT.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

447Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 5 67. Asynchronous VT1.5

*R—val ue based on

SMPR_FXD_STFF_DEFLT (Table 67).

Tabl e 568 . Bit Sync hronous

VT1.5

*R—va lue based on

SMPR_FXD_STFF_DEFLT (Table 67).

Table 569. Byte Synchronous

VT1.5

*R—va lue based on

SMPR_FXD_STFF_DEFLT (Table 67).

RRRRRRIR*

Byte 1

Byte 24

C1C2OOOOIR

Byte 1

Byte 24

Z6/N2

C1C2OOOOIR

Byte 1

Byte 24

Z7/K4

C1C2RRRS1S2R

Byte 1

Byte 24

10RRRRIR*

Byte 1

Byte 24

10OOOOIR

Byte 1

Byte 24

Z6/N2

10OOOOIR

Byte 1

Byte 24

Z7/K4

10RRRRIR

Byte 1

Byte 24

P1P0S1S2S3S4FR*

Byte 1

Byte 24

P1P0S1S2S3S4FR

Byte 1

Byte 24

Z6/N2

P1P0S1S2S3S4FR

Byte 1

Byte 24

Z7/K4

P1P0S1S2S3S4FR

Byte 1

Byte 24

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

448 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

Table 570. Asynchronous VT2

*R—val ue based on

SMPR_FXD_STFF_DEFLT (Table 67).

Tabl e 571 . Bit Sync hronous VT2

*R—va lue based on

SMPR_FXD_STFF_DEFLT (Table 67).

Tabl e 572 . Byt e Synchronou s

VT2

*R—va lue based on

SMPR_FXD_STFF_DEFLT (Table 67).

RRRRRRRR*

Byte 1

Byte 32

RRRRRRRR

C1C2OOOORR

Byte 1

Byte 32

RRRRRRRR

Z6/N2

C1C2OOOORR

Byte 1

Byte 32

RRRRRRRR

Z7/K4

C1C2RRRRRS1

S2 Byte 1[6:0]

Byte 32

RRRRRRRR

10RRRRRR*

Byte 1

Byte 32

RRRRRRRR

10OOOORR

Byte 1

Byte 32

RRRRRRRR

Z6/N2

10OOOORR

Byte 1

Byte 32

RRRRRRRR

Z7/K4

10RRRRRR

Byte 1

Byte 32

RRRRRRRR

P1P0RRRRRR*

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

P1P0RRRRRR

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

Z6/N2

P1P0RRRRRR

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

Z7/K4

P1P0RRRRRR

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

449Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 573. VC-11 to TU-12 Conversion

*R—val ue based on SM PR_F XD_STFF_DEFLT (Table 67).

V1/V2/V3/V4

V5/J2/Z6/Z7

RRRRRRIR/

P1P0S1S2S3S4FR*

Fixed stuff/even parit y

Byte 1

Byte 2

Byte 3

Fixed stuff/even parit y

Byte 4

Byte 5

Byte 6

Fixed stuff/even parit y

Byte 7

Byte 8

Byte 9

Fixed stuff/even parit y

Byte 16

Byte 17

Byte 18

Fixed stuff/even parit y

Byte 19

Byte 20

Byte 21

Fixed stuff/even parit y

Byte 22

Byte 23

Byte 24

Fixed stuff/even parit y

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
450 Agere Sy stem s Inc.
 
19 VT/TU Mapper Functional Description (continued)
19.14.5 VT Multiplexer (VTMUX)
The VTMUX logic block (in Figure 39 on page429 ) performs all f unc tions necessar y  to place  the appropriate V T 
data onto the outgoing mapper transmit path data bus.
Bits VT_T X_GRP_TYPE[6:0] (Table 180) are programmed to determine whether the outgo ing tributary is a 
VT1.5/TU-11 or a VT2/TU-12.
See Table 551 through Table 554 on page 430 through page 431 for VT/TU mapping formats.
19.14.6 Transmit Signaling (TX_VT S IG )
The TX_VTSIG logic bl ock (in Figure 39 on page429 ) will perform all necessary functions to retrie ve the signaling 
phase and data from the framer  and insert it int o the outgoing VT/TU. 
Note: This block is only enabled when operating in the byte synchronous mode.
■The signaling is received from the appropriate framer link selected with the value programmed  in bits 
VT_TXSIG_CH_SEL[1—28][4:0] (Table 202). VT_TXSIG_CH_SEL[1—28][4:0] i s a necessary dupli cation of   the 
routing information programmed within the cross connect (XC) block.
■The TX_V TSIG  block deter mines  whether the phase and signaling bits are to be used in the V T/TU mapping. If 
the phase or signali ng bits are not being used (VT_USE_PBIT [1 —28] = 0, VT_US E_SBI T[1—28] = 0 
(Table 202)), they will be set to  S MPR_F XD_ S TF F_DEFLT (Table 67) in the microprocessor interface block.  
Stomping of the F bit is contro lled by VT_ USE_FBIT[1—28] = 0 (Table 202).  Re fer to Table 574 below for pro-
gramming signa ling inserting.
Table 574. Framing Byte Gen eration Per Channel
*X—value based on SMPR_OH_DEFLT (Table 67), R—val ue based on SM PR_F XD_STFF_D EFL T (Table 67).
19.14.7 Transmit Lower Path Overh ead (TX_LOPOH)
The TX_LOPOH logic block (in Fi gure 39 on page 429) p erforms  al l nec essary functions  t o receive and store the 
low-order pa th overhead as well as the REI and RDI values from the ex t ernal LOPO H s erial access channel. The 
following functions are supported:
■The TX_LOPOH logic  block retimes all inco ming signals on the falling edge of  the e xter nal input pin 
LOP OHCLKI N (AC13).
■The source of the exter na l i nputs LOPOHDATAIN (AC14), L OPOHVALIDIN, and LOPOHCLKIN i s required to 
hold the LOPOHVALIDIN at 0 for a minimum of eight LOPOHCLKIN cycles. The TX_LOPOH logic block  monit ors 
the incom ing LO POHVALIDIN and detects failure cond itions. A failure exist s if there ar e less than eight 
LOP OHCLKIN cycles between a falling edge of LOPOHVALIDI N a nd the next rising edge, or if  the  i nt ernal b it  
counter reaches  its maximum count, for the active data type, and LOPOHVALIDIN does not tran sition to 0.
VT_USE_FBIT[1—28] 
(See Table 202.) VT_USE_PBIT[1—28] 
(See Table 202.) VT_USE_SBIT[1—28] 
(See Table 202.) Action
0 0 0 VT/TU frame byte* = XXXXXXXR
0 0 1 VT/TU frame byte* = XXS1S2S3S4XR
0 1 0 VT/TU frame byte* = P1P0XXXXXR
0 1 1 VT/TU  frame byte* = P1P0S1S2S3S4XR
1 0 0 VT/TU frame byte* = XXXXXXF R
1 0 1 VT/TU frame byte* = XXS1S2S3S4FR
1 1 0 VT/TU frame byte* = P1P0XXXXFR
1 1 1 VT/TU frame byte* = P1P0S1S2S3S4FR

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
451Agere Systems Inc.  
19 VT/TU Mapper Functional Description (continued)
■The first three bits received, following a rising edge of   external input pin LOPOHVALIDIN ( AB14), defines the 
data type on the incoming stream. Data types are defined in Table 557, Data Type Header Definitions on 
page 440.
■LOP OH failure is reporte d in bit VT_LO POH_FAIL_E  (Table 170). If an  LOPOH failu re exists (indi cated by 
VT_LOPOH_FAIL_E = 1), the incoming data will  be ignored .  Unles s the mask bit   VT_LOPOH_FAIL_M 
(Table 174) is set, VT_LOPOH_FAIL_E = 1 will generate an interrupt.
Figure 46  o n p a g e453 conta ins the  T X_LO P OH b lock  serial  c hannel form at and timing.
19.15   V T  Mappe r  Syste m I nte rface   Timing
19.15.1 V T M apper DS1/E1 Receive Interface (to System  Interface)
Figure 41 and Figure 42 sho w the minimum,  typical , and maximum gaps of the clock and data out of the VT  map-
per for DS1 and E1. An asym metric V T/TU m appe r c lock  (VTMPR_RCLK) is derived from an internal 6.48 MHz 
clock. The rising edge of this VT mapper clock is delayed by one 6.48 MHz clock cycle with r espect to the data 
(VTMPR_RDATA) and is one cycle in width.
5-8986(F)r.2
Figure 41 .  D S1 Mo de  Gapped Clocking Scheme
5-8987(F)r.2
Figure 42. E1 Mode Gapped Clocking Schem e
Figure 43 and Figure 44 show a typical frame of VT mapper output. The VT mapper 8 kHz fram e sync output 
(VTMPR_R FSY NC) is coincident with the DS1 frame-bit position and with the MSB of E1 time slot 0. 
Note: The VT mapper 8 kHz frame sync is onl y t ransmitted  for byte synchronous mappings.
5-8988(F)r.1
* Max im um  g ap  be tw ee n r i si ng c lo ck ed ges = 184 8 ns.
Figure 4 3. DS1 Inte rface
VTMPR_RCLK
VTMPR_RDATA
1232 ns 1848 ns
616 ns
154 ns154 ns
VTMPR_RCLK
VTMPR_RDATA
462 ns 924 ns 1386 ns
154 ns 154  ns
VTMPR_RCLK
VTMPR_RDATA
VTMPR_RFSYNC
DS0 #1 DS0 #2
F
DS0 #1 DS0 #2
F
125 µs
154 ns 616 ns 1232 ns*

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

452 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

5-8989(F)r.1

* Max im um g ap be tw ee n r i si ng c lo ck ed ges = 138 6 ns.

Figure 44. E1 Interface

19.15.2 V T M apper DS1/E1 Transmit Interface (from System I nterface)

The VT mapper input clock and data will meet the timing requirements of G.703, 1.544 MHz ± 50 ppm and

2.048 MHz ± 50 p pm. The VT mapper will accommodate up to ± 200 ppm to allow ope ration under maintenance or

trouble conditions. The clock edge to retim e the data is programmable with VT_TX_CLKEDGE[1—28] bit

(Table 198). The receive data is clocked on the rising edge when VT_TX_CLKE DGE[1—28] = 1 and the falling

edge when VT_TX_CLKEDGE[1—28] = 0.

See VT Mapper Timing on page 45 for VT mapper interface and clock timing nu mbers.

19.16 VT Mapper Lower-Order Path Overhead Interface Timing

19.16.1 VT Mapper Receive Path Overhead Interface Description

Figure 45 cont ains the VT mapper receive path overhead serial channel format and timing.

5-8327(F)r.2

Figur e 45. VT Mapper Receive Path Ov erhead Serial Access Channel

VTMPR_RCLK

VTMPR_RDATA

VTMPR_RFSYNC

TS #0 TS #1 TS #1 TS # 1

125 µs

154 ns 462 ns 924 ns*

TMUX/SPEMPR RDI/REI VTMPR VT#1—28 V5(MSB–>LSB) VTMPR VT#1—28 J2(MSB–>LSB) VTMPR VT#1—28 Z6(MSB–>LSB)

FRAME #1 OF MULTIFRAME

125 µs

MINIMUM OF 8 CYCLES 154 ns

LOPOHCLKOUT

LOPOHVALIDOUT

LOPOHDATAOUT 001 010 011 100

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

453Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

The Super Ma pper provides acces s to all necessary func tions associated the receive path overhead for each

VT/TU, sp ecifically V 5, J2 , Z6/ N2, Z 7/K4, and the O bits. T he following features are supported:

■V5, J2, Z6/N2, Z7/K4, and the O bits , on a per VT bas is, will be stored for one complete superframe and transmit-

ted out on external output pin LOPOHDATAOUT (AB17) during the next superframe. REI and RDI values

rece ived fro m the SPE mapper and TMUX w ill be stored on a per-frame basi s and transmi tted during the next

frame. RE I and RDI values will be latched during the A1 time o f the of the received S ONET frame.

■When operating in unidirectional path switch ring (UPSR) mode (VT_UPSR = 1 (Table 181)), REI, RDI and ERDI

values in the V5 and Z7 bytes will be modified based o n the recei ve st atus. See Table 557, Data Type Header

Definitions on pag e440, for automatic generation requirements.

■Each data type out of LOPOHDATAOUT will be transmitted s eria lly as a burst of 227 bits (VT1.5 mode) or

171 bi ts (VT2 mode) on the r ising edge of the clock, LOPOHCLKOUT, which is driven out on external pin AB15.

The REI and RDI received from the SPE mapper and TMUX will be transmi tted serially as a burst of 37 bits on

the ris ing e dged of the clo ck, LOPOHCLKOUT .

■The LOPOHVALIDOUT signal (driving external output pin AB1 8) is set to 1 when vali d data is being transmitted.

■Following transm is sion of any complete data type L OPOHV ALIDOUT is held at 0 for at least eight

LOPOHCLKOUT cycle s.

■The first 3 bits transmitted, following a rising edge of LOPOHVALIDOUT, make up the data type header. Data

type 001 will be the f irs t data type transmitted in each frame. V5, J2, and Z6 are trans mitted respectively in the

first frame of the superframe. Z7 and the O bits are tra nsmitted respectivel y in the second frame of the super-

frame. Note that the LOPOHDATAOUT data types are only transmitted in the first and second frames of the four

frame multiframe.

■All data types must be t ransmitted within 500 µs.

19.16.2 VT Mapper Transmit Path Overhead Interface Description

Figure 46 contains the VT mapper transmit path overhea d s erial channe l format and timi ng.

5-8329(F)r.2

Figure 46 . VT Map per Transmit Path Overhead Serial Acces s Channe l

TMUX/SPEMPR RDI/REI VTMPR VT#1—28 V5(MSB–>LSB) VTMPR VT#1—28 J2(MSB–>LSB) VTMPR VT#1—28 Z6(MSB–>LSB)

FRAME #1 OF MULTIF RAME

125 µs

MINIMUM OF 8 CYCLES 154 ns

LOPOHCLKIN

LOPOHVALIDIN

LOPOHDATAIN

LOPOH BITCNT 0 1 2

012

226

012

226

012

226

001 010 011 100

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

454 Agere Sy stem s Inc.

19 VT/TU Mapper Functional Description (continued)

The VT mapper transmit path overhead will perf orm all necessary functions for the low-order path ov erhead as well

as the REI and RDI values from the internal SPE mapper and TMUX blocks. The following are supported:

■The interface clocks all incoming signals on t he falling edge of external input L O POHCLKIN (pin AC13).

■T h e first 3 bits received , following a risin g e dge of external input pin LOPOHVALIDIN (AB14), will define the data

type on the incom ing strea m. Data types are defined in Tab l e 557, Data Type Header Definitions on page 440.

■The source of the external input LOPOHDATAIN ( AC14), LOPOHVALIDIN, and LOPOHCLKIN signals is required

to hold the L OPOHVALIDIN at 0 for a minimum of eight LOPOHCLKI N cycles. The VT mapper w ill monitor the

inc oming LOPOHVALIDIN and detect failure condition s. A failure exists if there are less than eight LOPOHCLKIN

cycles between a falling edge of LOPOHVALIDIN and the next rising edge, or if the LOPOH bit count

(LOPOH BITCN T) reaches it s maximum count for the active data type and LOPOHVALIDIN does not transition

to 0.

■LOP OH failure is reporte d in bit VT_LO POH_FAIL_E (Table 170). If a fai lure exis ts (VT _LOP OH _FA IL_E = 1),

the incoming data will be ignored and unless the mask bit, VT_LOPOH_FAIL_M (Table 174), i s se t, the LOPOH

failure will ge nerate an interrupt.

■The V T mapper logic block will latch new R EI and RDI values for the TMUX and SPE mapper during the A1 time

of the SONET/ SD H frame.

The timing figures in this section are functional ti ming diagrams. S ee VT Mapper Timing on page 45 for VT mapper

interface and clock timing numbers.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
455Agere Systems Inc.  
M13/M23 MUX/DeMUX Block Functional Description
Ta ble of Conte nts
Contents Page
M13/M23 MU X/DeMUX Block Functional Description .................................................................................... 455
1  M 13 Introduction ..................................................................................................................................... 456
2  Features  ................................................................................................................................................. 456
2.1 M13 Applications .......................................................................................................................... 456
3  Block Diagrams  ...................................................................................................................................... 457
4  M13 Functional Description .................................................................................................................... 460
5  M13 Multiplexing Path ............................................................................................................................ 460
5.1 M12 Multiplexers .......................................................................................................................... 460
5.2 D S1/E1 Interface .......................................................................................................................... 460
5.3 Loopback  Select  ...................................................... ....... ....... ...................................................... 461
5.4 D S1/E1 FIFOs .............................................................................................................................. 461
6  DS2 Frame Generation  ................ ....... ............ ....... ............ ....... ....... ............ ....... ....... ............................ 461
6.1 DS1 Mode .................................................................................................................................... 461
6.2 E1 Mode  ....................................................................................................................................... 462
7  M23 Multiplexer ...................................................................................................................................... 463
7.1 D S2 Interface ............................................................................................................................... 463
7.2 D S2 Select Logic  ......................................................................................................................... 463
7.3 Overhead Bit Generation (GR-499)  .......................................................... ....... ..... ....... ....... . ........ 463
7.4 M23 Mode  ................................................................................................................................... 464
7.5 C -Bit Parity Mode ......................................................................................................................... 464
7.6 FEAC  ........................................................................................................................................... 465
7.7 FEBE ............................................................................................................................................ 466
7.8 Terminal-to-Termina l Path Mai nte nance Data Link  ..................................................... . ............... 466
8  AIS/Idle Insertion .................................................................................................................................... 467
9  B3ZS  Encoder (GR-499) ..... ................ ..... ..... .......................... .......................... ..................................... 467
10  DS3 R-to-T Loopback ........................................................................................................................... 468
1 0 .1  DS 3 Transmit P at h  Interface ..................................................................................................... 468
11  M13/M23 Dem ultipl exer ........................................................................................................................ 468
11.1 DS3 LO C and LOS .................................................................................................................... 468
11.2 DS3  T-to-R Loopba ck  ....... ....................... ..................... . .................. . .................. . ...................... 469
11.3 M23 Dem ultipl exer ..................................................................................................................... 469
11.4 M12 Dem ultipl exers ................................................................................................................... 472
11.5 DS1 Mode .................................................................................................................................. 472
11.6 E1  Mode ..................................................................................................................................... 473
11.7 Output Sele ct Logic .................................................................................................................... 474
Figures Page
Figure 47. M13 Block Diagram............................................................................................................................. 457
Figure 48. M12 Funct ional Block Diagram...........................................................................................................458
Figure 49. M23 Funct ional Block Diagram...........................................................................................................459
Fig ure 50. DS3 NSMI T ransmit Operation............................................................................................................ 462
Fig ure 51. DS3 NSMI Receive Operation............................................................................................................. 462
Tables Page
Tabl e  575. C-Bit Parity Descrip tion and Transmit Value  ..................................................................................... 465

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

456 Agere Sy stem s Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.1 M13 Introduction

The M13 block is a highly configurable multiple xer/demultiplexer. It can ope rate as an M13 in either the C-bit parity

or M23 m ode, a mixed M13/M23, or an M23.

In the C-bit parity mode, the M13 provides a far- end alarm and control (FEAC) code generator and re ceiver, an

HDLC transmitt er and receiver, and automatic far-end block error (FEBE) generation and detection.

Each interna l M12 MUX/deMUX and the M23 MUX/deM UX may be c onfigured to operate as independent MUX/

deMUX.

The M13 supports nu mero us automatic monitoring functio ns. It can provide an interrupt to the control syst em, or it

can be o perated in a polled mode.

20.2 Features

■Configurable mu ltiplexer/d e mu ltiplexer for up to 2 8 DS1 signals, 2 1 E 1 signals, o r 7 DS2 signals t o/from a DS3

signal.

■M23 or C-bit parity mode operation.

■Seven configurable independent M12 multiplexer/demultiplexers for up to 28 DS1 signals or 21 E1 signals

to/from 7 DS2 signals.

■Provisionable time sl ot selection for DS1, E1, and DS2 insertion or drop.

■DS3 multiplexer capable of generating alarm indication si gnal (AIS ), remote alarm indicator (RAI), idle, far-end

alarm and control (F E AC), an d far-end block error (FEBE) signals.

■Automatic DS3 receive monitor that det ec ts loss of signal (LOS), bipolar violation (BPV), excessive zeros (EXZ),

out of frame (OOF), severely errored fram e (SE F), A IS, RA I, FE AC codes, P -bit pari ty errors, C-bit parity e rrors,

and FEBE indications.

■HDLC transmitter with 128-byte data bu ffer and HDLC receiver with 128-byte data FIFO for the C-bit parit y path

maintenance data link.

■DS3, DS 2, DS1, and E1 loopback and loopback reque st generation.

■Complies wi th T1.102, T1. 107, T1.231, T1.403, T1.404, GR-499, G. 747, and G.7 75.

20.2.1 M13 Applications

■M13 and M 2 3 multiplexers.

■M13 multiplexers supporting G .74 7 format.

■Indepe ndent M 12 multiplexers.

■Digita l access cross connects (DACS).

■DS1/E1/DS2 broadcast.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

457Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.3 Block Diagra ms

The following diagram il lu strates th e high-level interface between M13 block an d other function al b locks.

5-9013(F)r.1

Figure 47. M13 Block Diagram

M13 MULTI P LEXER

M13 DEMULTIPLEXER

CROSS

CONNECT

CONTROL INTERFA CE

DS1XCLK

DS2AISCLK

DS1/E1/DS2

LOOPBACK DS3

LOOPBACK

E1XCLK

M1 3 AU TOAI S

SMPR_TDS3CLK

SMPR_TDS3CLK_EN

M13_DS3CLK

M13_DS3NEG

SMPR_RDS3CLK

SMPR_RDS3CLK_EN

SMPR_DS3NEG_BPV

SPEMPR_AUTOAIS

RCBSYNC

RCBCLK

RCBDATA

RDLCLK

RDLDATA TCBSYNC

TCBCLK

TCBDATA

TDLCLK

TDLDATA

SMPR_DS3POS_DAT

M13_DS3POS_DATA

NSMI_RELATED

DNSMI_RELATED

DEVICE I/O

SPE

CROSS

CONNECT

DS3

DS1/E1

DS2

MAPPER

DEVICE I/O

M1 2 DS 1 DATA /

M2 3 DS 2 DATA /

M12 DS2 DATA/CLOCK

CLOCK/STFREQ

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

458 Agere Sy stem s Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

5-9014(F)r.1

Figure 48. M12 Functional Block Diagram

XC_DS1DATA[1—4] M12 MU X

DS1XCLK

M12 MUX

DS1/E1

LOC & AIS

MONITOR

#[1—4]

M13_DS1DATA[1—4]

M13_DS1DATA[25—28]

XC_DS1CLK[25—28]

XC_DS1CLK[1—4]

M13_DS1CLK[1—4]

M13_DS1CLK[25—28]

E1XCLK

XC_DS1STFREQ[25—28]

M13_AUTOAIS[1—4]

M13_AUTOAIS[25—28]

XC_DS1STFREQ[1—4]

M13_DS1M12CLK[1—4]

DS1/E1

LOC & AIS

MONITOR

#[25—28]

DS1/E1

SELECT

#[1—4]

M13_DS1M12CLK[25—28]

XC_DS1DATA[25—28]

OUTPUT

SELECT

#[1—4]

DS1/E1

OUTPUT

SELECT

#[25—28]

DS1/E1

SELECT

#[25—28]

M1 2 DE M U X

XC_DS2DMXCLK[1—7]

XC_DS2M12CLK[1—7]

XC_DS2DMXDATA[1—7]

M13_DS2M12DATA[1—7]

M13_M12DS2DATA[1—7]

DEVICE I/O

DS1/E1 FROM

CROSS CONNECT

DS1/E1 TO

CROSS CONNECT

M12 DEMUX

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

459Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

5-9015(F)

Figure 49. M23 Functional Block Diagram

M13_DS3NEG

SMPR_RDS3NEG_BPV

DS2

SELECT

TCBDATA

TDLDATA

RDLDATA

RCBDATA

DS3

LOOP-

BACK

SELECT

DS3

LOOP-

BACK

SELECT

AIS/

IDLE

INSERT

TCBCLK

TCBSYNC

TDLCLK

RDLCLK

RCBSYNC

RCBCLK

SMPR_RDS3CLK

SMPR_RDS3CLK_EN

SMPR_TDS3CLK

M23

MUX B3ZS

ENCODE

SPEMPR_AUTOAIS

M23

DEMUX B3ZS

DECODE

LOC &

DETECT

LOS

MICROPROCESSOR

INTERFACE AND

M13_M12DS2

DNSMI_RELATED

DS3

LOOP-

BACK

SELECT

M23

DEMUX B3ZS

DECODE

DS2 LOC

& AIS

MONITOR

#[1—7]

XC_DS2M23

XC_DS2ST

DS2AISCLK

M13_DS2

OUTPUT

SELECT

#[1—7]

DS2

M13_DS2M12

M13_DS2M23

SMPR_TDS3CLK_EN

M13_DS3POS_DATA

SMPR_RDS3POS_DATA

DEVICE I/O

DS2

SELECT

DEVICE I/O

NSMI_RELATED

DATA[1—7]

CLK[1—7]

FREQ[1—7]

CLK[1—7]

DATA[1—7]

CLK[1—7]

DS3 FROM/TO

CROSSCONNECT

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

460 Agere Sy stem s Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.4 M13 Fun ctiona l Description

In the descriptions below, some of the re g i ster bits exist for each of the DS1, E1, or DS2 signals. The names of

these register bits hav e a lower case x or a y suffix to show that there are actua lly 28 or 7 of them, respectively.

20.5 M1 3 M ult i plex in g Pa t h

The re are seven M12 multiplexers and one M23 multiplexer on the tran smit side of this M13 block and all of them

can operate independent ly. Twenty-eight DS1 inputs in groups of four, or twenty-one E1 input signa ls in groups of

three can feed into individua l M12 MUXs, while the M23 M U X can take DS2 signals fr om outputs of M12 MUXs, or

direct DS2 inputs, or loopback deMUX ed DS2s.

20.5.1 M12 Multiple xers

M12 m ultiplexers have four operation modes provisionable through M13_M12_MODEy[1:0] (Table 263):

■M13_M12_MODEy[1 :0] = 00: the M 12 operat es as the first stage of M13 multiplexing. It tak es 4 DS1s

(M13_DS1_E 1Ny = 1(Table 263)) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes int o a DS2 signal which will be fed

into the M23 MUX. In this mode, the DS1/E1 clocks are independent inputs to the block. There should be no valid

DS2 input (XC_DS2M23DATAy). This is the d efault mode.

■M13_M12_MODEy[1:0] = 01: the M12 operates as an independent mu ltiplexer. It t ake s 4 DS1s

(M13_DS1_E1Ny = 1) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent directly to

the DS2 output (M13_D S2M12DATAy) of the block and not be passed to M 23 MUX input. In this mode, the

DS1/E1 clocks are independent in put s to t he block and a DS2 input clock (XC_DS2M12CLKy) is required.

■M13_M12_MODEy[1:0] = 1 0: the M12 operates as an independen t multiplexer. It takes 4 DS1s (register bit

M13_DS1_E1Ny = 1) or 3 E1s (register bit M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent

directly to the DS2 outpu t (M13_DS2M12 DAT Ay) of the bloc k and not be passed to M23 MUX input. I n this mode,

t he associated DS 1/E1 clocks are outpu ts from the block and derived from t he DS2 input cloc k

(XC_DS2M12CLKy).

■M13_M12_MODEy[1:0] = 11: the M12 is idl e. The output from this M12 mul tiplexer will be held low.

20.5.2 DS1/E1 Interface

The incoming DS1/E1 clock signals (XC_DS1CLK[ 28—1] ) are first checke d for activity or loss of clock (LOC). This

is rep orted to the microprocessor v ia bits M13_DS1_LOC[28:1] (Table 247). Once LO C is detected, AIS will be

inserted into the associated DS1/ E1 channel using the clock from external pins, DS1XCLK/E1XCLK (AD16/AC17)

(Table 3).

The incoming DS1/E1 data signals are retimed immediately b y the associated clocks . The edge of the clocks that is

used to retime the data is user provisionable to either the rising edge (M13_RDS1_EDGEx = 1 (Table 264)) or fal l-

ing edge (M13_RDS1_EDGEx = 0).

After being ret imed, the incoming data stream is checked for AI S. When the input is DS1, the M13 will declare AI S

if the input data is logic 0 for fewer than 9 out of 8192 clock periods (T1.231). When the input is E1, AIS is decl ar ed

if there are less than 3 zeros in each of two consecutive 512-bit periods and cle ared when each of two consecutive

512-bit per iods contains more than 2 zeros (G. 77 5). If AIS is dete cted on an y of t he DS1/E1 inputs

(XC_DS1DATA[28—1]), the associ ated M 13_DS1_AIS_DE T[28:1] (Table 248) bit is set.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
461Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
20.5.3 Loopback Select
DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 i nputs from the  deMUX  path to be 
loope d back. This loopback can be perfo r med automatically if M13_AUTO_ FLB (Table 259) or M13_AUTO _LB 
(Table 259) bits are set. Regardless of the state of M13_A UT O_FLB and M13_AUTO_LB,  the user can force a DS1 
or E1 loop back by setting M13_SEL_DS1_LBx (Table 264) to 1.
When M13_AUTO_LB = 1, loopback of channel x is activated if M 13_DS1_LB _DE Tx = 1 ( Table 249) (see Sectio n 
20.11.4 M12  Demultiple xers on page 472). In the C-bit pari ty  mode, automatic loopback can also be activated as a 
result of rec ei ving a loopback request through the far-end al arm and control (FEAC) channel. Such a reques t is  
indicated by  status  bit M13_D S1_F EAC_LB_DETx  (Table 251) (see Section 20.7. 6 FEAC on page 465 ). If status 
bit M 13_DS1_ FE AC_LB_DETx = 1 and M13_A UTO_FLB = 1, loopback o f channel x is activated.
20.5.4 DS1/E1 FIFOs
When M13_M12_MODEy[1] = 0 (Table 263), t he 4 selected DS1 or 3 selected E1 signals for each M12 M U X are 
fed into single bit 16-word-deep FIFOs that are used to sync h ronize the selected si gna ls to the DS2 frame genera-
tion  clock. The DS2 /DS3 tra nsmi t clock (XC _DS2 M12CLKy) i s used to derive the clock s ource for DS2 f rame  gen-
eration blocks. In the C-bit parity mode, all DS2 stuff opportunities are used, which produces a nominal 6.306 MHz 
DS2 clock. In th e  M23 mo de, the DS2  stuffing rat io is fixed such th at the DS2 cl oc k i s nominal ly 6.312 MHz.
The  fill level of each FIFO dete rmines the need for bit stuffing its  DS1/E1 input. This block allows the M13 to accept 
DS1/E1 signals with  nominal frequency offsets of ±130 ppm and up to 5 unit  intervals peak jitter.
When operating in M13_M12_MODEy[1:0]  = 10 m ode, the FIFOs are not used.
20.6  DS2 Fram e  Gene ration
Each M12 MUX generates a DS2 frame  either from 4 D S1 signals multiplexed as specified in T1.107 and G R -499-
CORE when M13_DS1_E1Ny = 1 (Table 263), or from 3 E1 signals multiplexed using the for mat specified in ITU-T 
recommendation G.7 47 when M13 _DS1_E1Ny = 0. 
When M13_M12_MODEy[1:0] = 01/10 (Table 263), each M12 MUX is operating independently. In this case, the 
output DS2 signals are re timed by the associated clocks. The edge of the clocks that is used to retime the data is 
user provisionable to either the rising edge  (M 13_DS2M12_EDGEy (Table 275) = 1) or falling edge 
(M13_DS2M12_EDGEy = 0).  The AIS signal can be inserted into any DS2 output by setting 
M13_DS2_FORCE_AISy (Table 271) to 1.
20.6.1 DS1 Mode
In the DS1 m ode, the 4 signals interleaved to generate the yth DS2 signal are the outpu ts  from  DS1/ E1 loopback 
sele cto rs 4y – 3, 4y – 2,   4y – 1, and 4y. Bits multiplexed into the second and fourth channels (fr om se le c to rs 4y  – 2 
and 4y) are inverted before being interleaved (T1.107) when bit M13_MUXCH2_4_INVy = 1 (Table 263).
Loopback requests for a DS1 ch annel are indi cated by inverting the third C bit for that channel (T1.107). This is 
done when bit M13_DS1_LB_REQx  is set to 1 (Table 263).  The 4 M13_DS1_LB_REQx bits that affect the y
th DS2 
are 4y  – 3,  4y – 2, 4y – 1, and 4y.
The X bit is   se t to the inverse of the remote alarm indication (RAI) bit (T1.107) M13_DS2_R AI _SEND y (Table 265).
For testing purp oses, th e M fram e  a li g nm e n t s ignal (normally 011) is generated with the last bit inv erted (010) if 
M13_DS2_M P INVy i s set (Table 267), and the M-subframe alignment s ig nal (01) is generated as (00) if 
M13_DS2_FINVy i s set (Table 268).

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

462 Agere Sy stem s Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.6.2 E1 Mode

In the E1 mode, the 3 signal s interleaved t o generate th e yth DS2 signal are the outputs from DS1/E1 loopback

selectors 4y – 3, 4y – 2, and 4y – 1.

Although it is not part of the G.747 standard, loopback requests for an E1 channel can be indicated as in the DS1

mode by inverting the third C bit for that channel. This is done if the M13_DS1_LB_REQx bit is set. The 3

M13_DS1_LB _RE Qx bits t hat af fect the yth DS2 are 4y – 3, 4y – 2, and 4y – 1.

The remote alarm indication (RAI) bit and the rese rved bit are set to the valu e of M13_DS2_RAI_SENDy and

M13_DS2_RS V_S END y register bits, (Table 266) resp ectively (G.747).

For testing purposes, the frame al ignment signal (normally 111010000 as specified i n G .747) is generated w i th the

last bit inver ted (111010001) if M13_DS2_FINVy is se t, and the pa rity bit is inverted if M13_DS2 _MPINVy is set.

The first parity bit after a 0 to 1 transition of SMPR_BER_INSR T (Table 65) is also in verted if M13_DS2_P_BERy is

set to 1 (Table 269).

0781(F)

Figure 50 . D S3 NSMI Transmit Operation

0782(F)

Figure 51. DS3 NSMI Receive Operation

UNUSED

FRAME BIT

VARIABLE

LINE_TXCLK29

TXDATAEN

TXSYN C (OPTIONAL)

LINE_TXDATA29

DS3POSDATAOUT

UNUSED

FRAME BIT

VARIABLE

LINE_RXCLK29

RXDATAEN

RXSYNC (OPTIONAL)

LINE_RXDATA29

DS3POSDATAOUT

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
463Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
20.7  M23  M u lti p lexe r
The M23 multiple xer generates a transmit DS3 frame and fills the inf ormation bits in the frame with data either from 
the 7 DS2 select bloc ks when M13_NSMI_MODE = 0 ( Table 277) or from the serial pa yload input XC_NSMI_D ATA 
(when M13_NSMI_MODE = 1). It generates t he f rame usin g either  the SMPR_TDS3CLK or the SMPR_RDS3CLK 
input clocks. In the rec eive loop timing mode (M13_LO OP_TIME  =  1 (Table 259)), the received clock, 
SMPR_RDS3CL K, is selected. Otherwise, SMPR_TDS3CLK is used f or DS3 frame generation. SMPR_TDS3CLK 
is monitored for loss of clock, which is reported through bit M13_TDS3_LOC (Table 225).
The s erial data interf ace, when enabled (M 13_NSMI_MODE = 1), generates a clock M13_NSMI_CLK and an 
enable M13_NSMI _EN for accept ing D S3 payload d ata XC_NSMI_DATA. A sync pulse, in reference to and ahead 
of t he first M bit within a DS3  fr ame, is al so generated. The offs et from the sync  pulse to the first M bit   is program-
mable through bits  M13_NSMI_SP_ OFFSE T[7:0] (Table 261).
The M23 MUX can be provisioned to operate in either the M23 mode (M13_M23_CBP =  1 (Table 260)) or the C-bit 
par ity mode (M13_M23_CBP = 0).
An unframed all ones data str eam is generated if M13_TDS3_FORCE_ALL1 is set to 1 (Table 276).
20.7.1 DS2 Interface
The clocks associated with input DS2 signals can be either inputs to the M23 MUX (M13_M23CLK_MODE = 0  
(Table 276)) or output s from the M23 MUX (M13_M 23CLK_MODE = 1).The incoming DS2 clock signals are 
checked for activity or loss of clock (LOC).  T his is repor t ed to the microprocessor via bits M13_ XC_DS2_LOC[7:1] 
(Table 238). In case LOC is detected, AIS will be inserted into the associated DS2 channel using DS2AISCLK 
(pin E10).
The  incoming  D S2 data signals (XC_DS2M23DATA[7—1]) are reti med immediately by the as sociated clock s. The 
edge of the clocks that is used to retime the data is user provisionable to either the   risi ng edge 
(M13_RDS2_E DGE y = 1 (Table 283)) or  falling e d ge (M13_RDS2_ EDGEy  = 0 ).
After being retimed, the incoming data stream is checked for AIS. The M13 will declare AIS  if the  input data is 0 for 
fewer than 5 clock cycles in each of two conse cutive 840 clock periods. The AIS is no t cleared until t here are more 
than 4 zeros in each of two consecutiv e 840-bit per iods (G.775). If AIS is detected on an y of DS2 inputs, the asso-
ciated M13_XC_D S2 _AIS_DET[7:1] bit   is  se t (Table 239).
20.7.2 DS2 Select Logic
The selection  of  DS2  signal s o urce  for each DS2 ti me slot is controlled by M13_AUTO_LB (Table 259), 
M13_DS2_LB _DE Ty (Table 244), M13_SE L_DS 2_LBy  (Table 282), and M13_M12_MODEy (Table 263) bits.
When M13_AUTO_LB = 1 and M13_ DS2_LB_DETy = 1, th e  DS2 signal  fro m time slot y in the received D S 3 signal 
is looped back  into time slot y of  the transmitted DS3 signal (see C-Bit Processing on page 470). The user can also 
force a loopback by setting M13_SEL_DS2_LBy to 1. DS2 loopback should not be done in the C-bit parity mode.
If a loopback is not acti ve, the DS2 signal selector is controlled by bits M13_M 12_MODEy[1:0]. If register bits 
M13_M 12_M ODE y[1 :0] =  00, the output of M12 multiplexer y is chosen for the yth D S2 time slot in the transmitte d 
DS3 signal; otherwise, the input DS2 signal XC_DS2M23DATAy is selected  fo r the yth DS2 time slot  in t he transmit-
ted DS3 signal. 
20.7.3 Overhead Bit Generation (GR-499)
For testing purp oses  th e  F  b its, M bits, and P bits can be generated with errors. The fram e alignment signal  (F-bit 
pattern t hat is normally 1001) is genera ted with the last bit inverted (1000) if M13_DS3_FINV (Table 276) is set. 
The mult ifram e alignment signal (M-bit pattern that i s normally 010) is generated as (011) if M13_DS3_MINV 
(Table 276)  is set. 

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
464 Agere Sy stem s Inc.
 
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
The parity  bi ts (P bits ) are generated   as odd rather than the normal even pa rity if M13_DS3_PINV (Table 276) is 
set. Bot h P bits within the first DS3 frame af ter a 0  to 1 transition of SMPR_BER_INSR T (Table 65) are a lso 
inverted if M13_DS3_P_B ERy (Table 277) is set to 1.
The X b its are set to th e  inverse of the remote alarm indication (RAI) bit (GR-499 ) M13_DS3_RAI_SEND 
(Table 277).
C-bit transmission is a func tion of whether the M13  MUX/deM UX is  in the M23 mode or  t he C-bit parity  mode.
20.7.4 M23 Mode 
Please refer to M13_M23_CBP = 1 in Table 260. The information bits in the DS3 frame are drawn from the 7 DS2 
select blocks .  If  M 13_M23CLK_MODE = 0 (Table 276) and a select block is in the loopback  or direct DS2 input 
state, the selected DS2 mus t be synchronized to the DS3 frame generation clock. To do this, the M 13 conta ins 
7 D S2 F IF Os   each with a depth of 8. The fill level of each FIF O determines the need for bit stuffing it s DS2 input.
When M13_M23CLK_MODE = 0 and DS2 select  b locks are not  in the lo opback or direct DS2 input state, the 
select ed DS2s ar e generated using the DS3 frame generation c lock. In this case, a fixed  stuffing ratio is used for 
the DS2s in order to produce a nominal 6.312 MHz DS2 cl ock rate.
When M13_M23CLK_M ODE = 1, the FIFOs are not used and DS2 stuff request inputs (XC_DS2STF REQ[7—1]) 
will determine when stuff bi ts are needed.
The three C bits in each M-subframe of the DS3 frame are stuff ind ication bits. If the stuff opportunity bit in an M 
su b frame is filled by a DS 2 bit, the fi rst and second C bits in that M-subframe are transmitted as zeros. If the  stuff 
opportunity bit in an  M - subframe is fille d  with a stuff bit,  th e  first and second C bits in that   M-subframe are transmit-
ted as ones.
The third C bit  in each M- su bframe is normally   transmitted with the same value as the first and second C bits. How-
eve r, if M 13_DS2_LB _RE Q y = 1 ( Table 281), the  third C bit i s transmitted as the inver se of the first two  C bits 
(which indicates a loopback request for DS2 channel y).
20.7.5 C-Bit Parity Mode 
Please refer to M13_M23_CBP = 0 in Table 260. The  M23 MUX   ca n operate in the C-bit parity mode under  the  fol-
lowing two circumstanc es:
■When M13_M23CLK_MODE = 0 and 28 DS1 or 21 E1 signals are bei ng MU Xed into the DS 3.
■When M13_M23CLK_MODE = 1 and 7 DS2 signals are being MUXed in to the D S3.
In the C-bit parity mod e, every DS2 stuffing opport unity is filled with a stuff  bit. Because stuffing is not  used for syn-
chronization, the selected DS2s cannot come directly fr om the M13 inputs, and the selected DS2s cannot be 
loope d back from the M23 demultiplexer. The 21 C bits in each DS3 frame are no t requ ired as stuffing indicators. 
Their use is desc r ibed in Table 575 on page 465.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
465Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
Table 575. C-Bit Parity Description and Transmit Valu e
20.7.6 FEA C
The  thir d C  bit of each DS 3 frame provides a far-end alarm  and control (FEAC) signal.  The use of this signal and 
FEAC code words are de fined in T1.107 and  GR-499-CORE.
When the FEAC signal is not active, it is transmitted continuously as  a 1.  The user can provision the M13 to trans-
mit cont inuous ones by setting M13_TFEAC_CTL[1:0] to 00 (Table 278).
Active FE AC signals consist of repeating 16-bit code words of the form 0 x5x4x3x2x1x0 0 11111111, where xi can 
be a 1  or a 0. The code words are transmitted right to left one bit  each DS3 frame for 16 c ons ecutive frames.
Alarm a nd Status Signals. EAC alarm and status si gnals should be transm itted c ontinuously for the du ration of 
the condition being reported, or for a minimum of 10 repetit ions of the code word. FEAC signals are transmitte d 
continuously by se tting M13 _TFEAC_CTL[1:0] to 01, and M13_TFEAC_C O DE[5:0] to x5x4x3x2x1x0 (Table 278), 
where x5x4x3x2x1 x0  is the appropriate value for  the alarm or status  code word.
Control  Signals. EAC control signals are defined for activating or deac tivating a loopback. Code words for loop-
back activation, deactivation, and specifying the type o f loopback can be transmitted using the s ame  metho d as  
described above for alarm and status signals.  Alternatively, the user may provision the M13 to automatically send 
the activate or deactivate commands.
In order t o activate a loopback,  the  user may set M13_TFEAC_CTL[1:0] to 11, and M13_ TFEAC_CODE[5:0] to 
x5x4x3x2x1 x0 , where x5x4x3x2x1x0 is the appropriate value for  the loopback code word. The M13 will then trans-
mit 10 repetitions of the activate code word, 0 000111 0 11111111 followed by 10 repetitions of 
0x5x4x3x2x1x0 0 111 11111. After transmitting this 40 octet s equence, it will  se t M13_T FEAC_DONE to 1 
(Table 217).
In order to deactivate a loopback, the  user ma y set  M13_ TFEAC_CTL[1:0] t o 10, a nd M13_TFEAC_CODE[5:0] to 
x5x4x3x2x1 x0 , where x5x4x3x2x1x0 is the appropriate value for  the loopback code word. The M13 will then trans-
mit 10 repetitions of the deactivate code word,  0 011100 0 11111111, followed by 10 repetitions of 
0x5x4x3x2x1x0 0 111 11111. After transmitting this 40 octet s equence, it will  se t M13_T FEAC_DONE to 1.
C-Bit Number Description Transmit Value
C1 C-Bit Parity Identification 1.
C2 Networ k  Req uirem ent s Bit If M13_CBIT2_ACT = 0 (Table 277), the C2 bit is  set to 1.
If M13_CBIT2_ ACT = 1,  th e  transmit value  o f C2  i s  input 
through pin TCBDATA (E12).
C3 Far-End Alarm and Control (FEAC) See FEAC below.
C4—C6, 
C16—C21 Unused If M13_UNUSED_ACT = 0 (Table 277), a ll are tra ns mitted 
as 1.
If M13_U NUS E D_ACT = 1,  the  transmi t valu es are input 
through pin TCBDATA (E12).
C7—C9 CP Bits (path DS3 parity) S et  to the same value  as the P bits. 
C10—C12 Far-End Block Error (FEBE) Bits See Section 20.7.7  FEBE on  page 466.
C13—C15 Terminal-to-Terminal Data Link See Section 20.7.8 Terminal-to-Terminal Path Maintenance 
Data Link on page 466.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
466 Agere Sy stem s Inc.
 
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
20.7.7 FEBE
C bits 10, 11, and 12 provide a far- end block error (FEBE) in dication.  Each  fra me of  the rec eived DS3 s ignal is 
checked for errors in the F - bit  or M-bit framing sequences and fo r errors in the CP-bit path parity. If no  errors are 
f o und,  t he FEBE bits are set to 111 in the next transmitted DS3 frame. If one or more errors are detected, the FEBE 
bits are transmitted as 000. The user can force t h e transmission of FEBE error indications by setting 
M13_FEBE_ERR to 1 (Table 277). This causes all DS3 frames to be transmitted  wit h  the FEBE bits set to  000, 
regardless of whether or not errors were detected in the received DS3 signal.
20.7.8 Terminal-to-Terminal Path Maintenance Data Link
C bits 13,  14, and 15 can be used as  a 28.2 kbit/s  data link. If  the data  link is not used, the user should set 
M13_TDL_ACT to 0 (Table 279), which causes  all ones to be t r ansmitted. When M13_TDL_ACT = 1 and 
M13_TDL_NTRNL = 0 (Table 279), the data transmitted on this link comes directly from the M13 input pin, pin 
TDLDATA (E8). Otherwise (M13_TDL_ACT = 1 and M 13_TDL_NTRNL = 1), the data link is controlled by  th e inter-
nal HDLC transmitter.
HDLC Transmitter. The internal HDLC transmitter circuitry is composed of two 64-byte data buffers (registers 
M13_TDL_0DATA_R[0—63] (Table 298) and M13_TDL_1DATA_R[0—63] (Table 299)), a CRC-16 frame check 
sequence (FCS) generator , and control circuits. The HDLC transmitter continually outputs flag bytes (01111110) 
with MSB fi rst until the user sets M13_TDL_NTRNL_A CT to 1 (Table 279). Following the completion of the ne xt flag 
byte, the HDLC transmitter begins transmitting the first byte of the first data buffer (register 
M13_TDL_0D ATA_R[0]), which should be filled by the user with the first byte of the address field. (For LAPD mes-
sages, this byte contains the service access point identifier , the command/response bit, and a zero extended 
address bit.)
Bytes from the data buffer are transmitted least significant bit (LS B ) first (GR-499). The HDLC con troller inserts a  0 
after any sequence of fiv e consecutive ones in the data buff er to prevent the occurrence of a flag pattern prior to the 
closing flag.
Buffer Usage. The number of bytes   transmitted from the data buffers before completing the frame is controlled as 
follows.  M 13_TDL_BUF0_END (Table 279) and M13_TDL_BUF1_E ND ( Table 279) are two bits which indicate 
whether or not the final buff er byte to be transmitted is currently in buffer 0 or buffer 1. Whil e bytes f rom  bu ffer 0  are  
being transmitted, t he HDLC c ont ro ller checks the value of M13 _TDL _ B UF0_END bit. If it is 0, all bytes fro m bu ffer 
0 and at least one byte from buffer 1 are transmitted. If it is 1, bytes from buffer 0 are tr ansmitted sequentially up to 
and including byte K, where M13_TDL_B YTE_END[5:0] = K (Table 280).
Similarly, the number of bytes transmitted from buffer 1 i s controlled by the value of M 13_TDL_BUF1_END and 
M13_TDL _BYTE_END[5:0]   bits.   Bytes   are t ransmitted  alternately from  buffer 0 and buf fer 1 until bit 
M13_TDL_BUF[0, 1]_END = 1 for the activ e transmission buff er and the val ue of bits M13_TDL_BYTE_END[5:0] is 
equal to the by te number being transmitt ed.
When the HDLC controller completes transmission of register M13_TDL_0DATA_R[63] (the last byte of buffer 0), 
the interrupt bit M13_TDL_BUF0_INT is set to 1 (Table 217). Similarly, the int errupt bit M13_TDL_BUF1_INT 
(Table 217) is set after the last byte  of buffer 1 is transmitted. T hese bits indicate that the corresponding buffer has 
been emptied and is available for refilling.
The user may abort the transmission of an HDLC   frame by cleari ng M13_TDL_NTRNL_ACT to 0 prior to complet-
ing transmission of the last byte from  the data buffers. If so, the HDLC controller w ill stop transmission from the 
buffers and send an abort byte ( 01111111) transmitted MSB first. The abor t b yt e  w ill then be followed by  flag bytes 
until M13_TDL_NTRN L_ ACT is again set t o  1,  st a rting tran sm ission of a new  f rame.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
467Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
FCS Ge n e rati on.  Once the last buffer byte is transmitted, the HDLC controller either transmits a closing flag byte 
(when M13_TDL_FCS = 0 (Table 279)), or it first appends  the 2-byte ITU-T FCS with the necessary zero stuffing 
before sending the closing flag (when M13_TDL_FCS = 1). In either case, the HDLC controller sets 
M13_TDL _DONE (Table 217) to 1 a fter  the transmission of th e frame is  com plete. F or testing purposes, th e user  
can send corrupted FCS bytes b y clearing M13_TDL_FCS to 0 and filling the last 2 bytes in the buff er with an incor-
rect CRC value.
LAP D  Exam pl e. T1.107 defines three  standard LAPD messages that ma y be transmitted on the path maintenance 
data link. After the opening flag, each of thes e messages contains 79 bytes of a ddress, control, and information. 
These are followed by the 2-byte F CS and the closi n g flag.
To transmit one of these mess ages using the internal HDLC trans mitter, the microprocessor s houl d first set 
M13_TDL_ACT (Table 279) to 1, M13_TDL_NTRNL (Table 279) to 1, and M13_TDL_NTRNL_ACT (Table 279) to 
0. This causes the continuous generation of fl ag bytes.
The  microprocessor may then fill buffer 0 with the f irs t 64 by tes of   the message and fill by tes 0 through 14  of buffer 
1 w ith the last 15 byt es   prior to the FCS of the message. By setting M13 _TDL_BUF0_END (Table 279) to 0, 
M13_TDL_BUF1_E ND (Table 279) to 1, and M1 3_TDL_BYTE_END[5:0] (Table 280) to 001110, the microproces-
sor can indic ate that 79 buffer bytes are to be  tran smitted.
The microprocessor can then set M13_TDL_FCS to 1 and M13_TDL_NTRNL_ACT to 1. This will cause the inter-
nal HDLC transm itter to send the 79 bu ffer byt es, append the  FCS a nd closing  flag, set M1 3_TDL_DONE to 1, and 
resume continuous flag transmission.
If the same LAP D mess age is  to be transmitted later without fir st having transmitted a  different  message, the micro-
processor only needs to t oggle M 13_TDL_NTRNL_ACT to 0 and back  to  1,  as the values of   the other control 
parameters and the buffer bytes are no t mo dified   by the internal HDLC tran smitter.
20.8   AIS/ Id l e Ins ertion
Th e AIS /idle insertion block  can be pro visioned to operate  in the no rmal mo de (M13_DS3_FORCE_AIS = 0 
(Table 276) and M13_DS3_FORCE _IDL E = 0 (Table 276)), generate DS3 AIS (M13_DS3_FORCE_AIS = 1) or 
generate DS3 idle ( M13_DS3_FORCE_AIS = 0 and M13_ DS3_F O RCE_ I DLE = 1).
In the normal mode, data from the M23 multiplexer is passed unchanged to the B3 ZS encoder block.
During AIS ins ertion (M 13_DS3_FORCE _AIS = 1), the generated DS3 frame is altered by overwriting the informa-
tion bits with an alternating 1010 . . . pattern, starting with a 1 after each overhead bit. In addition, the X bits are 
overwritt en with ones, and the C bits are overwritten with all zeros (T1.107 and T1.404).
During idle signal generation (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORC E_IDLE = 1), the information bits 
are overw ritten with  11001100 . . ., starting  with 11 after each overhead bit. T he X bits are overw ritt en w ith ones. In 
the M23 mode (M13_M23_CBP = 1 (Table 260)), the C bit s  are overwritten with all zeros.  In  the C-bit parity mode, 
the C bits  ar e passed unchanged (T1.107 and T1 .404).
20.9  B3ZS Enco der (G R-499)
The transmit DS3 device output  can either  be in the form of unipolar dat a (M13_DS3POS_DATA when 
M13_B IPOLAR = 0 (Table 260)) or po sitive data, and negative data ( M13_DS3POS_DATA, and M13_DS 3NEG 
when M13_B IPOLAR = 1).  If  M13_BIPOLAR = 1, the DS3 da ta is B3Z S encoded wit h M13_DS3POS_DA T A = 1 
indicating a posit ive pulse and M13_DS3NEG = 1 indicating a negative  pulse.
The  B3ZS encoder block accepts dat a output from the M23 multiplexer and when M13_BIP OLAR = 1, performs 
coding as follows: for each inp ut data bit that is a  1, the encoder outputs a 1 (or pulse) on either its  positive or neg-
ative output. The positive or negative output is chosen such that the resulting pulse is opposite in polarity to the last 
nonzero output.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
468 Agere Sy stem s Inc.
 
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
F or each input data bit that is a 0, the encoder outputs zeros on both its positive and negat ive outpu ts, unless doing 
so would c ause three consecutive output perio ds of positive  and negative ze ros. In the latter c ase, the three con-
secutive inp ut zeros   are output as either [00V] or [B0V], where B i s a pulse on either the positive or negative output 
that is opposite in polarity to the last non-zero output, and V is a pulse that   is the sam e  polarit y as the last  nonzero 
output. The choice of [00V] o r [B0V] is made so that the polarity of consecutive  V-pulses alterna tes  (wh ich is   equiv-
alent to forcin g the number of B-pulses between successive V-pulses to b e odd).
When M 13_BIPOLAR = 1, the user can force err ors in the bipolar coding by setting M13_BIPOL_ERR (Table 258) 
to 1. When th is is done, the M 13 transmits the next 1 a s a bipolar vio lation.
20.10   DS3 R-to-T Loopback
The received DS3 signal can be looped directly back to the transmi t DS3 output. If either M13_LOOP_R_ TO_T = 1 
(Table 260), or both M13_AUTO_FLB = 1 (Table 259) and M13_DS 3_FLB_DET = 1 (Table 251) (see Sec tion 
20.7.6 F EAC on p age 465), the loopback is activated. (During  loopback, the SMPR_RDS3POS_DATA and 
SMPR_RDS3NEG_BPV  input signals are lo oped to the M13_DS3POS _DATA and M13_DS3NEG outputs, res pec -
tively.)
20.10.1 DS 3 Transmit Path Interface
When cross c onnected to  th e DS3 devic e pins,  th e DS3 data out DS3POSDATAOUT (p in R22) and 
DS3NEGDATAOUT (pin P22) is clocked out  on the fa lling edge of DS3DATAOUTCLK (pin N22).
If the M13 DS3 interface i s op tioned for loop timi ng (M13_LOOP_TIME = 1), the  DS3 data is clocked out on  the  ris-
ing edge of DS3DAT AINCLK (pin J22).
20.11  M13/M23 Demultiplexer
20.11.1 DS 3 LOC and LO S
SMPR_RDS3CLK is monitored for loss of clock , which is reported through  bit M13_RDS3_LO C (Table 225). The 
user can configure which edge of  SMPR_RD S3CL K retimes the data (M13_RDS3_EDGE = 1 (Table 287) selects 
the risin g edge; M1 3_RDS3_EDGE = 0 selects the falling edge). 
The receive DS3 signal is also checked for loss of   signal ( LO S ), which is reported through bit M13_RDS3_LOS 
(Table 225). An LOS defect, according t o T1.231, is the occurrence of 175 ±75 contiguo us pulse positions with no 
pulses of either positive or negative polari t y at the DS3 input. An LOS def ect is terminated upon detecting an aver-
age pulse density of at least 33% over  a period of 175 ±75 contiguous  pulse positions starting with the receipt  of a 
pulse. An LOS defe ct will not be terminated if, at the end of the pulse-positi on inter val, any subintervals of 100 
pulse po sitions containing  no pulses of either polarity were  obse rve d  ( T1.231).
B3ZS  D ec o der. The receive DS3 device input can either be in the form of  unipolar clock and data 
(SMPR_RDS3CLK  and SMPR_RDS3P OS_DATA when M13_BIP OLA R = 0 (Table 260 on pa g e216)) or unipolar 
clock,  positiv e data, and negativ e  data (SMPR_RDS3CLK, SMPR_RDS3POS_DATA, and SMPR_RDS3NEG_BPV 
when M13_BIPOLAR = 1 and M13_BPV_IN = 0 (Table 259))  or unipolar cloc k, data, and bipolar violation indicati on 
(e xternal input) (SMPR_RDS3 CLK, SMPR_RDS3POS_DATA, and SMPR_RD S3N EG_BPV when 
M13_BIPO LAR  =  0  and M13_BPV_IN = 1). When M13_BIPOLAR = 0, the received DS3 data and clock are 
passed directly to the M23  demultiplexer. When M13_BIPOLAR = 0 and M13_BPV_IN  = 1, the received DS3 data 
and clock are passed  to  the M23 demultipl exer while the bipolar violation indication i s forwarded to the internal BPV 
counter for perfor mance m onitoring (B3ZS decoder is not  us ed) .  When M13_BIPOLAR = 1 and M13_BPV_IN = 0, 
the received SMPR_ RDS3POS_DATA and S MP R_RDS3NEG _BPV data i nputs are first B3Z S decoded.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
469Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
The B3ZS decoder bl ock  perf orms decoding as follo ws.  For each clock period that both SMPR_RDS3POS_DATA 
and SMPR_R D S3NEG_BPV  ar e 0 (no pulse) , the decoder out puts a 0. For each cloc k period that either 
SMPR_RDS3POS_DATA or SMPR_RDS3NEG_BPV is 1 (pulse), the decoder determines whether or not the pulse 
is part of a zero substit ution (ZS) sequence. A Z S sequence is [00V] or [B0V],  w her e B is a pulse on either the  pos-
itive or negative input that is opposite in polarity to the l ast nonzero input, and V  is   a pulse that is the same polarity 
as the last non zero input.
If the received pulse is not part of a ZS sequence, the decoder  ou tp uts a  1. Ot her wise, the decoder outputs three 
consecutive zeros in place of the received ZS sequence.
The B3ZS dec oder also c hecks for bipolar coding viola tions. B ipol ar c oding vi olations  are defined as received 
V- pulses that are not opposite in pola rity to the last V-pulse or are not immediately preceded by a 0, or received 
zeros that   are immediately preceded by two other zeros.
The M13 contains a counter that increments on each occurrence  of a received bipolar co ding violation (BPV). I t 
also monitors the occurrence of excessive zeros (EXZ), which is defined as any zero string length equal to or 
greater than 3 (T1.231) . These are part  of the per formance monitoring coun ters that can be sampl e d  and simulta-
neously reset (see DS3 P erformance Monitors on page 472). Their last  s ampled values  are availabl e in registers 
M13_BPV_CNT_R[1—3] (Table 295) and M13_EXZ_CNT _R[1—3] (Table 296).
20.11.2 DS 3 T-to-R Loopback
The M13 can be conf igured to loopba ck the inte rnal transmit DS 3 from the output of the M23 M UX 
(M13_LOOP_T_TO_R =  1 (Table 259)) o r accept the received DS3 signal after B3ZS decoding 
(M13_LOOP_T_TO_R =  0) and send it into th e M23 deMUX block.
20.11.3 M23 Demultiplexer
The  M23 demultiplexer will take the rece ived DS3 signal and either deM UX it into 7 D S2 data st reams or strip o ff 
the overhead bi t s and send payload out through the NSMI serial interface when M13_NSMI_MODE (Table 277) = 
1. 
The s erial data interf ace, when enabled (M 13_NSMI_MODE = 1), generates a clock M13_DNSMI_CLK and an 
enable M13_DNSMI_EN for outputting DS3 p ayload data M13_DNSMI_DATA. A sync pulse M13_D N SMI_SYNC, 
in referenc e to and ahead of the first M bit within a DS3 frame, is also generated. The offset from the sync pulse to 
the first M bit is programmable through bits M13_D_SP_OFFSET[7:0] (Table 262).
In the case of the received DS 3 signal being deMUXed into 7 DS2s, tho se DS2s can be sent out of   the device, or 
looped back to the transm it   side, or pass ed to M12 demultiplexers for further breakdown into  DS1s/E1s.
DS3 F ramer.  After being B3ZS decoded, the incoming DS3 data stream is checked for the presence of unframed 
all ones. If the input data is 0 f or f ew er than 9 out of 8192 clock periods, bit M13_RDS3_ALL1_DET (Table 225) will 
be set.
The  M23 demultiplexer determines  if the input signal contains valid DS3 framing. This is done in two stages by first 
finding a bit position that matches the frame alignment pattern (F bits), and then  locating the multifr ame alignment 
signal (M bits). After a matching F-bit sequence is found, in-frame is declared (M13_DS3_OOF = 0 (Table 224)) 
when correct M bits  are received for three consecutive M  frames (T1.231). The maximum average reframe tim e is 
0.5 ms in the presence of a bit error  rate of 10–3.
Once the deMUX is i n-frame, the received frame bits are monitored f or out-o f-frame.  Out -of-frame is declared 
( M13_DS3_OOF  = 1) when  too many errors are received  in either  the F b its  (thr ee errors  i n 1 6  bit s when 
M13_DS 3_M ODE = 0  (Table 287), o r at leas t 1 F-bit error in each of four consecutive M-subframes when 
M13_DS3_MODE = 1) or t he M bits (at least 1 error in each of  three consecutive M frames) (T1.231). For testing 
pur poses, the user may also force the framer  out -of-frame by setting M13_DS3_F ORCE_OOF ( Table 258) t o 1.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
470 Agere Sy stem s Inc.
 
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
The  traditio nal algorithm for  dec laring o ut-o f - f rame  (three errors in 16 F  bits) re s ults in false  o u t-of-frame approxi-
mately every  30 s ec onds  when the recei ved bit error  rate i s 1 0–3. By waiting fo r four consecutive M-subf rames with 
F bit errors before declaring out-of-frame (M13_DS3_MODE = 1), the M13 normally stays in frame for over an hour 
when the b it error rate is 10–3.
The M13_DS3_LOF (Table 224) bit is set if bit M13_DS3_OOF is high continuously for 28  frame  periods (approxi-
mately 3 ms). Once set, M13_DS3_LOF is not cleared unti l M13_DS3_OOF is continuously low for 28 frame peri-
ods.
The user can p rovision the M13 to automatically output AIS if  either bit M13_DS3_OOF = 1 (by setting 
M13_ AUTO_AIS_OOF (Table 259) to 1), or M13_DS 3_LOF = 1 (by setting M13_AUTO_AIS_LOF to 1).
The received DS3 frames are also checked for severely errored frames ( SEF). An SEF defect is the occurrence of 
three or more F-bit errors in 16 consecutive F bits and i s  reported through bit M13_RDS3_SEF (Table 225). An 
SEF defect is terminated  when the signal is in-frame and there are less than three F-bit errors in 16 consecutive 
F bits.
AIS, Idl e, and RAI Detection. Each M  frame, the 47 04 inform ation bits are checked  for the presence of the AIS 
(1010) or idle (1100) pattern.   In order t o detect these patterns in the presence of a hig h  erro r rate, AIS 
(M13_DS3_AISPAT_DET = 1 (Table 224)) or idle (M13_DS3_IDLEPAT_DET = 1 (Table 224)) pa ttern d etection is 
declared if fewer t han five pattern errors are received in ea ch of two consecutive fra mes. Once AIS or idle is 
declared, these bits are not cleared  until at least  16 pattern errors are received in each of 2 consecutive frames  
(T1.231).
In addition to the fixed info rmation  bit patterns, A IS and idle  signals are   transmitt ed  with all C bits  set to 0 and both 
X bits set to 1. These conditions are monitored by the M13 and reported in bits M13_DS3_CBZ_DET  (Table 224) 
and M13_DS3_RAI_DET ( Table 224).
If every C bit in three consecutive DS 3 frames is 0, the M13 sets M13_D S3_CBZ_DET to 1. If the three C b its in a 
single M-subfra me are all 1, M13_DS3_CBZ_DET is cle ared. If both X bits in two consecutive frames are received 
as 0, the device sets M13_DS3_RAI_DET to 1. Once  M13_DS3_RAI_DET is s et, it is  not cleared until both X bits 
in two consecutive frames are received  as 1.
The user may wish to declare AIS or idle based on a combination of some or all   of the following bits: 
M13_DS3_CBZ_DET, M13_DS3_RAI_DET, and M13_DS3 _AISPAT_DET or M13_DS3_IDLEPAT_DET.
C-Bit Processi ng. The M13 can be provisioned to operate in either the M23  mode (M13_M23_CBP = 1 
(Table 260)) or the C-bit parity mode (M13_M23_CBP = 0). In t he M23 mode,   the C bits in each M-subfr ame are 
inter preted as st uff indicator bi ts, and they are checked for loopback request s. I f th e third C b it di ffer s fro m t h e  first 
and second C bits   in the yth M-subfra me for 5 successive DS3 frames, M13_DS2_ LB_ DETy (Table 244) is set to 1. 
The M13_DS2_LB_DETy bit is cleared when the third C bit does not diff er  from the first two C bits in subfr ame y for 
five successive DS3 frames.
The first  C bit of  each frame, C1, provi des C-bit  parity identification. I f for eight con se cutive fra mes i t is rec ei ved as 
a 1, the M13 sets M13_DS3_C1_DET (Table 224) to 1. Once M13_DS3_C1_DET bit i s set, three consecutive 
frames with 
C1 = 0 must  be received before it is cleared.
The RCBDATA (pin E15) output provides access to the r eceived C2, C4, C5, C6, and C16 through C21 C bits. The 
received data link bits, C13 through C15, are output as a serial stream on RDLDATA pin (H2 2).
FEAC. In the C-bit parity mode, the third C bit of each DS3 frame,  C3, is mon itored for FEAC s ignals. Active FEAC 
signals consist of repeating 16-bit code words of  the form 0 x5x4x3x2x1x0 0 11111111, where xi can be a 1 or a 0, 
and the b its are receiv ed right-t o-left. The same code word must be rece ived four consecutive times before it i s 
accepted.
When a code word is accepted, the action taken by the M13 depends  on the value of x5x4x3x2x1x0, which may be 
an  alar m indi c at io n , a loopbac k  activ a tion, or a loopback deactiva tion.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
471Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
The  values of M13_DS1_ FEAC_LB _D E Tx and M13_DS3 _FLB _D E T  bits are n ot changed if   an  a ctivate or deacti-
vate control signal is accepted, but the next code word to be accepted is not a channel indication c ontrol signal 
(010011, 011011, or 100001 through 111100).
Alarm, Status, or Unassigned Signals. If a FEAC signal is accepted that is not a loopback activate (000111), 
deactivate (0111 00), or channel indication (010011, 011011,  or 100001 through 111100) signal, the M13 will set 
bits M 13_RFEAC_CODE[5:0] = x5x4x3x2x1x0 and M13_RFEAC_ALM _INT (Table 217) to 1.
Control  Signals. EAC control signals are defined for activating or deactivating a l oopback. I f a loopback a ctivate 
(000111), deactivate (011100), or channel indication (010011, 011011, or 100001 through 111100) is accepted, 
the M13 will set bits M13_RFEAC_CODE[5:0] (Table 252) = x5x4x3x2x1x0 and M13_RFEAC_LB_INT ( Table 217) 
to 1.
If a  loopback activate (000111), followed by   the all-DS1 channels indication ( 010011) is accepted, the de vice set s 
all M13_DS1_FEAC_LB_DETx (Table 251) bits.  All  M13_DS1_FEAC_LB_DETx bits are cleared if a loopbac k 
deactivate (0111 00), followed by the all-DS1 channels indication, is accepted.
If a  loopback ac tivate (000111), followed by the DS3 i ndicat ion (011011) is accepted, the device sets the 
M13_DS3_FLB_DET (Table 251) bit. The M13_DS3_FLB_DET bit is cleared if a loopback deactiv ate (011100), fol-
lowed by the DS 3 indication, is accepted.
Similarly, if  the M13 accepts an activ at e or deactiv at e control signal followed b y a DS1 channel indication (100001 
through 111100), it sets or clears  the M13_DS1_FEAC_LB_DETx bit, where x is equal to the binary value of 
x5x4x3x2x1x0.
Termi nal-to-Terminal Path Maintenance Data Link. C bits 13, 14, and 15 can be used as a 28.2 kbit/s data link. 
These bits are available directly at device output pin RDLDATA (H22). The M13 also contains an internal HDLC 
receiver for process ing the received data link bits.
HDLC Rec eiver . The internal HDLC receiver circuitry is composed of a 128-byte FIF O,  a CRC-16 frame  check 
sequence (FCS) error detector, and control circuits.
The HDLC receiver searches for flag bytes (01111110) and processes the bits received between flag bytes as fol-
lows. T he receiver removes zeros tha t imme diately follow any sequence of five consecutive ones. Sequences of 
8 bi ts a fte r zero destuffing are grouped into bytes and written i nto the FIFO.
As bytes are received, the CRC-16 value, based on the ITU-T polynomial,   is   c alculated. When the closing flag is 
received,  the receiver checks that the received FCS in the final 2 bytes matches the calculated CRC-16. If 
M13_RDL_FCS = 1 (Table 287) and the FCS does  not mat ch, M13_RDL_FCS _ERR ( Table 253) is set. If 
M13_RDL_FCS = 0, M13_RDL_FCS_ERR is held reset at 0. M 13_RDL_FCS bit also determines whe ther or not 
the f i nal 2 bytes o f the frame are written into t he FIFO. They are written into the FIF O only when 
M13_RDL_FCS = 0.
The receiver allows frames to be sent back-to-back with th e   closing flag of one fram e shared as the openi ng f lag of 
the nex t frame. If fewer than three  complete destuffe d  bytes  are received between flag bytes, the receiver i gnores 
the data and writes nothing into the FIFO.
FIFO Usage. The FIFO i s l arge enough to  hold  one full and two  partial standar d DS3 LAPD frames of 79 bytes. In 
case shorter frames  are being transmit ted, the M13 can keep  track of u p to fo ur frames  in the FIFO that have not 
been read.
The receive data-link frame interrupt bit, M13_RDL_FRM_INT (Table 217), is set when a frame closing flag or an 
abort byte is received. The M13_RDL_FIFO_UF (Table 225) bit is set if the buffer underflows, and t he 
M13_RDL_FIFO_AF (Table 225) bit  is set  if  the  buffer reac h es  a  p r ovis ion able fill level . The fill leve l  c a n  b e s et to 
16 byte s (M13_RDL_F ILL[1:0] = 00 (Table 287)), 32 bytes (M13_RDL_FILL[1:0] = 01), 64 bytes 
(M13_RDL_F ILL[1:0]  =  10), o r 96 bytes (M 13_RDL_FILL[1:0] = 1 1).
The user may read bytes from  the FIFO through register M13_RDL_DATA_R (Table 254) . The portion of the earli-
est frame still in the FIFO can be deleted by setting M13_RDL_FRM_CLR ( Table 258) to 1. (This is n or mall y done 
to purge a corrupted or abort ed frame.) The user must reset M1 3_ RDL_ FRM_CLR  before  an ot he r fr a me can  be 
deleted. If  M13_RDL_FRM_CLR is set  before the closing flag of the frame currently being read from the FIFO has 
been received,   all subsequent bytes of the frame will be  discarded without being written into the FIFO.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
472 Agere Sy stem s Inc.
 
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
Frame Status an d Error Reporting. The M13 p rovides i nformation on the earliest frame still in the FIF O through 
status register M 13_RHDLC_STATUS_R (Table 256).
The  status  r egis ter ha s 1 bi t to indicate whether or not the c los ing f lag (or an abort byte) f or the current frame has 
been received, 1 bit to in dicate if the current frame is corrupted, 5 bi ts to indicate t he  size of the cu rrent frame mod-
ulo-32, and 1 bit to indicate wh ethe r or not there are less than  32 bytes of the earliest frame left in the FIFO.
T here are four ways in which the M13 c an identify that  the current frame has  been corrupted.  The frame may have 
been aborted (M13_RDL_ABORT = 1 (Table 253)),  it m ay have fai led the CRC check 
(M13_RDL_F CS _ERR = 1 (Table 253)), the numb er of bits between opening and closi ng flags may not have been 
a multiple of 8 (M13_RDL_NO T_BYTE = 1 (Table 253)), or it may  hav e been overwritten before being read from the 
FIFO (M13_RDL_OVFL = 1 (Table 253)). Also, there is a separate bit M13_RDL_FLAG (Table 253) t o indicate 
whether or not the closing flag (or an abort  b yte) for th e curren t frame has been received.
The size of the current fr ame modulo-128 (including FCS bytes only if M13_RDL_FCS = 0 ( Table 287)) i s indicated 
by  register M13_RDL_FRAME_SI ZE_R (Table 255).
DS3 Performance Monitors. For perfor mance monitoring p urposes, there are a number of error counters in the 
M13. All  of these internal counters are comprised of a running error counter and a hold register that presents stable 
results to the mic ro proc es sor. The counts in all of the r unning counters are latched to the hold registers and the 
running counters cleared with the configured int ernal performance monitor reset signal.
The latched results   are then held to be read by the microprocessor. All of the internal cou nte r s h ave the a b ility to 
store more than the maximum possible c ount in a one second interval for a bit error rate of 10–3. As long as the per-
f ormance monitor reset occurs at least once ev ery second, no count s will be lost. In case this doesn’t happen, all of 
the running counters will either hold their maximum value or roll over to zero, depending on the control  signal  input 
SMPR_SAT_ROLLOVE R (Table 67).
Within the M23 demultiplexer,  there are four performance monitoring counte r s. M 13_DS3_FER R_CNT[11 :0]  
(Table 289) i ncrements each tim e an error is   detected in either an F bit or M bit, and M13_DS3_ PERR_CNT[ 13:0] 
(Table 292) increments if at least one of the P bits disagrees with the parity of the previous frame. In the C-bit par ity 
mode only, M13_DS3_CPE RR_CNT[13:0] (Table 291) counts frames with at least two of  the three C-bit parity bits 
indicating an error , and M13_DS3_FEBE_CNT[13:0] (Table 290) a ccumulates FE BE error in dications (1 error indi-
cation for e a c h D S3 frame with at  le ast one FEBE b it equal to  zero).
20.11.4 M12 Demultiplexers
Each M12 demultiplexer outputs either 4 DS1 si gnals fro m  the DS2 frame as specified in GR-499-CORE (when 
M13_DS1_E1Ny = 1 (Table 263)),  or three E1 signal s from the DS2 format  specified in ITU-T Recom mendation 
G.747 (when M13_DS1_E1Ny = 0 ). In th e D S1 mode, the demultiplexed second and fourth channels are inver ted 
before being sent to the output selector s whe n M13_DEMUXCH2_4_INVy = 1 (Table 272).
Each  M12 DeM U X can be programmed i ndependently t o  r e ceive DS2 signal eith er from M2 3  deMUX (when 
M13_M12DMX_MODEy[1:0] = 00 (Table 272)) or direct DS2 input XC_DS2DMXDATAy (wh en 
M13_M12DMX_MODEy[1:0] = 01). In the latter case, an input DS2 clock XC_DS2DMXCLKy is also required. 
When  M 13_M12DM X_MODEy[1:0]  = 10/11,  the M12 demultiplexer is idle and the outputs  are held lo w.
The DS2 signal is monitored for A IS, which is  de clared (M13_DS2_AIS_DETy = 1 (Table 242)) if the demu ltiplexer 
input is   0 for fewer than five clock cycles in each of two consecutive 840 clo ck periods, and cleared if there are 
more than 4 zeros in each of two consecutive 840-bit periods  (G .775).
20.11.5 DS 1 Mode
Framer. The M 12 demultiplexe rs determine if the input signal contai ns vali d DS2 fr aming. This is done in two 
stages by fi rst finding a bit position that matches the M-subframe alignment pattern (F bits), and then locating the M 
frame alignment signal (M bits). After a matching F-bit sequence is f ound, in-frame is declared (M13_DS2_OOFy = 
0 (Table 240)) when correct M bits are received for three consecutive M frames. The maximum a verage reframe 
time is 2.5 ms  in the presence of a bit error  rate of 10–3.

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
473Agere Systems Inc.  
20 M13/M23 MUX/DeMUX Block Functional Description (continued)
Once the deMUX is  in-frame, the received frame bits are monitored for out-of-frame. Out-of-frame is  declared 
(M13_DS2_OOFy = 1) if too many errors are received in either the F bi ts (two errors i n 4 bits when 
M13_DS 2_M ODE = 0  (Table 274), o r at least one F-bi t error i n four consecutive M-subf rame  pairs when 
M13_DS2_MODE = 1) or the M-bits   (at leas t one error in three consecut ive M frames). For testing purposes, the 
user may also force  the framer out-of-frame by setting M13_DS2_ FOR C E_OOFy (Table 257) to 1.
The traditional algorithm for declaring out-of-frame (two errors in  4 F bits) results in false out-of-frame approxi-
mately every 5 sec onds   when the bit error rate is 10–3. By waiting for four consecutive errored M-subframe  pairs 
(containing 4-F bits) b efore declaring out-of-frame (M13_DS2_MODE =  1), the M13 normally stays in frame for 
over 4four days whe n t he bit error rate is 10–3.
Overhead Processing. The C bi ts for each DS1 channe l are checked for loopback requests. I f the third C bit dif-
fers from the first and second C bits in the zth M-subframe for five successive DS2 frames, M13_DS1_LB_DE Tx 
(Table 249) is set to 1, where x = (4y – 4 + z). M13_DS1_LB_DETx  is cleared w hen the third C bit does  not differ 
from th e first two C bi ts  in the zth M-subf rame for f ive successi ve DS2 frame s.
If the X b it in four consecutive fr ames is rece ived as 0, the M13 sets M 13_DS2_RAI_DETy (Table 243) to 1. Once 
M13_DS 2_RA I_DETy i s set , it is not  c leared until the X bit is  received as 1 in four consecutive frames.
20.11.6 E 1 Mode
Framer. The M 12 demultiplexe rs dete rmine if the input signal c ont a ins a valid frame  fo rmat as  s pecif ied  in ITU-T 
recommendation G.7 47. Frame alig nment is declared (M13_DS2_OOFy =  0 (Table 240)) when a correct frame 
alignment signal is received for three  consec utive frames. The maximum average reframe time is 0. 5 ms  in the 
presence of a bit error rate of 10–3. Out-of-frame is declared (M13_DS2_OOFy = 1) if the frame alignment signal 
contains at least  1-bit error for four consecut ive frames. For testing purposes, the user m ay also force the fr amer 
out-of-frame by   setting M13_D S2_FORCE_OOFy (Table 257) to 1.
Overhead Processing. The C bits f or each E1 channel are check ed f or loopback requests . If th e third Cz bit differs 
from the first and second Cz bits for five successive frames, M13_DS1_LB _DETx (Table 249) is set to 1, where 
x = (4y – 4 + z). M13_DS1_LB_DE Tx  is  cleared when th e third Cz b it does not differ from the first two Cz bits for 
five successi ve fra mes.
If the RAI bit in four consecutive frames is received as 1, the M13 sets M13_DS2_RAI_DETy to 1 ( Table 243). Once 
M13_DS2_RAI_DETy is set, it is not c leared u ntil the RAI bit  is received as 0  in four consecutive fr ames. The 
received reserved bit is  reported through the M 13_DS2_RSV_RCV y   (Table 245), which is updated only when a 
new value is received in four consec utive fram es.
Loss of Frame and Au to matic AIS Insertion. The M 13_DS2_LOFy (Table 241) bit is se t when M13_DS2_OOFy 
is high continuously for 28 DS3 frame period s (approximately 3 ms). Once set, M13_ DS2_LOFy  is not   cleare d until 
M13 _ DS 2 _OOF y is con t i nuously  l ow for 28 DS3 frame periods.
The user can p rovision the M13 to automatically output AIS if either bit M13_DS2_OOFy = 1 (by setti ng 
M13_AUTO_A IS_OOF to 1), or M13_DS2_LOFy = 1 (by setting M13_AUTO_AIS_LOF to 1).
DS2 Performance Monitors. Wit h in each M12 demultiplexer, there are two performance  monitoring counters. 
These counters are cleared and read as described above (see DS3 Perfo rmance Monitors on page 472).
Registers M13_DS 2_ FERR_CNT[7—1]_R (Table 294) count  errors in the frame alignment   signal. In the DS1 
mode, M13_DS2_FERR_CNTy (Table 294) increments  each t im e an error is detected in either an F bit or M bit. In 
the E1 mode, this counter increm en ts either for eac h frame alignment signal bit error (when 
M13_DS2_FERR_MODE = 0 (Table 274)), or once for each  frame alignm ent signal that contains at lea st one bit 
error (when M13_DS2 _FERR_ MOD E =  1).
In the E1 mode only, re gisters M13 _DS2_PERR_CNT[7—1]_R[1—2]  (Table 293) count errors in P bi ts .

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

474 Agere Sy stem s Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.11.7 Output Select Logic

DS2 O utput S el ecti on . The M23 demultiplexer outputs are fed into seven DS2 output selection log ic blocks. This

allows the M13 to output the demul tiplex ed DS2 signals or insert AIS.

Each selector is identified by a number y that range s from one to seven and corre s ponds direc tly t o M13 out puts

M13_DS2DATA[7—1]. The outgoing DS2 signals are retimed by an associated clock, M13_DS2CLK [7 —1]. The

edge of the clocks that is used to retime the da ta is pr ov isionab le t o e ither t h e r i sing edge (M13_TDS2_EDGE = 1

(Table 294)) or falling edge (M13_TDS2_EDGE = 0).

The output from each selection block is controlled by the values of bits M13_DS2_OUT_IDLEy (Table 284) and

M13_DS 2_OUT_AISy (Table 285).

■Output is held low when M13_DS 2_OUT_IDLEy = 1 ; otherwise, the deMU Xed D S2 si gnal is output when

M13_DS2_OUT_AISy = 0 and DS2 AIS is output when M13_DS2_OUT_AISy = 1.

The all ones DS2 AIS signal is also output under all failure conditions at DS3 level which requi re automatic AIS

inse rtion at DS2 level.

DS1/E1 Output Selection. The M12 demultiplexer outputs are fed into 28 DS1/E1 output selection logic blocks.

This allows the M13 to output the demultiplex ed DS1/E1 (M13_D S1_OUT_AISx = 0 (Table 273)), or insert AIS

(M13_DS1_OUT_AISx = 1 ). The all ones AIS signal is also output under all failure condi ti ons at DS 3 or D S2 le v e l

which require automatic AIS insertion at DS1/E1 level.

Each selector is identified by a number x that ranges from 1 to 28 and corresponds directly to a block output

M13_DS1DATA[28—1]. The outgoing DS1 and/or E1 signals are retimed by an associated cl ock,

M13_DS1CLK[28—1]. The edge of the clock that is used to retime the data is provisionable to either the rising

edge (M13_TDS1_EDGE x = 1 (Table 272)) or falling edge (M13_TDS1_EDGEx = 0).

Each o utput selector number, x can be expressed as either 4y – 3, 4y – 2, 4y – 1, or 4y, where y ranges from 1 to

7. For a given y , the 4 sele ctors in the group output DS1 signals when M13_OUT_TYPEy = 1 ( Table 272), o r E1

signals when M 13_OUT_TY PEy = 0. In either of these modes, the four selec tors in the group are con trolled by the

2-bit values OU TSE Lx, where x = 4y – 3, 4y – 2, 4y – 1, and 4y.

When M13_O U T_T Y PEy = 0 , the output of selector 4y is held low .

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
475Agere Systems Inc.  
28-C hannel Framer Block Functional Description
Ta ble of Conte nts
Contents Page
28-Channel Framer Block Functional Description .................... ..................... . ............. . .................. . ............... 475
1  28-Channel Framer Introduction .......... ................... ................... ....... ................... ....... ............................ 479
1.1 D S0/E0 Switching Applications .................................................................................................... 479
2  Transpo rt Applications ............................................................................................................................ 482
3  Framer-to-Line Interface Unit Physical Interface .................................................................................... 485
3.1 Line Interface Re ferences/Stan dards  .......................................................................................... 485
3.2 Frame Formats  ............................................................................................................................ 485
3.3 Transmit Framer Functions .......................................................................................................... 486
3.4 Framing Referenc es /St andards  . ............................................ ................... ....... ................... ......... 486
4  DS1 Transparent Fram ing Format  .......................................................................................................... 486
5  CEPT 2.048 Basic Frame Structure  Transparent Framing Format ........................................................ 487
6  Receive Framer Nonalignment  Mode (DS1/E1) ........................ ....... . ......................... .......... ... ............... 488
6.1 Loss of F rame Alignme nt Criteria  ................................................................................................ 488
7  Frame Alignment Criteria ........................................................................................................................ 489
8  Receive and Transmit Signal ing Processor ................................ ...... ............................... ....................... 489
8.1 Signaling Introduction and Feature Description ........................................................................... 489
8.2 Signaling References/Standards  ................................................................................................. 490
9  Receive S ignaling Per-Link Feature Provisioning  .............. ....... ....... ............ ....... ....... ............ ................ 490
9.1 S ignaling State Mode Sourc e Selection . ............................................ ....... ....... ............................ 491
9.2 S ignaling S tate Mode Select ion . ........................................................ .......................................... 491
9.3 Signaling Source Selection .......................................................................................................... 491
9.4 Signaling Destination Selection  ................................................................................................... 492
10  Optional Receive Signaling Features Provisioned for Eac h Lin k  .... ..................................................... 494
10.1 Su pport of DS1 Robbed-Bit Stomping ..... ... ......................... ................. ... .................................. 494
10.2 Su pport of CEPT Time-Slot 16 Stomping ... ............................................ ................... ................494
10.3 Support of Signaling Debounce ....... ......... ............ ....... ............ .............. ....... ............ ....... .......... 494
10.4 Su pport of Japanese Handling Groups . ................................................. ....... ............ ................ 494
11  Receive Signaling Global Feature Provisioning ..................................................................................... 494
11.1 Link Count Sele ction   ................... . ....................... ... .................. .............. . .................................. 495
12  Other Receive Signaling Global Features ....... ....... ............ ....... ....... ...................................... ................ 495
12.1 Su pport of Automatic Signa ling Free ze  on Framing Bit Errors  ...................... .......... ... ............... 495
12.2 Su pport of Change of Signaling State FIFO .................................................. .......... ... ...............495
13  Receive Signaling Interrupts .................................................................................................................. 496
13.1 Mai ntenance of the Change of Signaling State FIFO Status Bits .............................................. 496
13.2 Mai nte nanc e of Handling Group Related Status Bits ......... ............................................. .......... 496
14  T ra nsmit Signaling Per-Link Feature  Provisioning ....................................... .......................... ................ 497
14.1 Signaling State Mode Source Sel ec tion ................ ....... .......................... .......................... ......... 497
14.2 Signaling Stat e Mode Selection  ............................ ....... ............................................................. 498
14.3 Signaling Sourc e Selection  ....................... .................................................... ............ ................ 498
14.4 Signaling Destination Sel ection .................................... ............................................................. 500
15  Optional Transmit Signaling Features Provisioned for Each Link ......................................... ....... ..........501
15.1 Su pport of Automatic Maintenanc e of the  Time-Sl ot 16 Remote Frame Alarm  . .............. ......... 501
15.2 Su pport of DS1 Robbed-Bit Stomping ..... ... ......................... ................. ... .................................. 501
15.3 Su pport of CEPT Time-Slot 16 Stomping ... ............................................ ................... ................501
15.4 Support of Signaling Debounce ....... ......... ............ ....... ............ .............. ....... ............ ....... .......... 501
15.5 Su pport of Japanese Handling Groups . ................................................. ....... ............ ................ 501
15.6 Su pport of Z ero-Code Suppression ............................ ... ......................... ....... ................. ... ........ 501
16  T ra nsmit Signaling Global Feature Provisio ning .................................................................................... 502
16.1 Link-Count Selection ................................................................................................................. 502
17  Other Transmit Signaling Global Feat ures ...... ....... ...................................... ....... ....... ............ ................ 502
17.1 Su pport of Automatic Signa ling Free ze  on Framing Bit Errors  ...................... .......... ... ............... 502

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
Agere Sy stem s Inc.
 
28-Channel Framer Block Functional Description (continued)
Table of Conten ts (continued)
Contents Page
17.2 Support of Byte Sync SONET Mapping  ................ ............ ....... ....... ............ ....... ....... ............ .... 502
18  T ra nsmit Signaling Status Registers ... ............................................................................. ...................... 502
18.1 Mai nte nanc e of CEPT  Related Status Bits  ............. . ................................... ... ............................502
19  Perfo r mance Monitoring Functional Integration into Superfra mer  ................................... ...................... 503
20  Performance Report Message ............................................................................................................... 506
21  Perfo r mance Monitoring References/Standards .......... ....... .......................... .......................... ............... 508
22  Facility Data  Link ................ .............................. ................. ...................... ............................................... 508
22.1 Facility Data Link Ref erenc es/Standards ......................................... ................... ................... ... 508
22.2 Receive Data Li nk Functional Description ................................................................................. 509
22.3 
SLC
-96 Supe rframe Receive Data Li nk .................................................................................... 509
22.4 DDS Receive Data Link Stack ................................................................................................... 509
22.5 CE PT; CEPT CRC-4 (100 ms); CEP T CRC-4 (400 ms) Multiframe Sa Bits Receive Stack ..... 510
22.6 Receive Data Li nk Stack  Idle Modes ......................................................................................... 511
22.7 Receive Data  Link  Stack Pointer ............................................................................................... 511
2 2.8 Tr a n sm it Facility D a ta Li nk Fun ctional Description ........................ ................. ................. ......... 513
22.9 
SLC
-96 Superframe Transmit Data Link ................................................................................... 513
2 2 .1 0  DDS Transmit Data  Link Stack ........................................ ........................................................ 514
22.11 Transmit ESF Data Link  Bit-Oriented  Mes sages ... ................................................... ............ ... 51 5
22.12 CEPT , CEPT Multiframe Transmit Data Link Sa bits  Stack  .................................................... 515
22.13 Transmit Data Link Stack Idl e  Modes ...................................................................................... 516
22.14 
SLC
-96, DDS, or CEP T ESF Frame Alignment  .............. .......................... ...................... ........ 516
23  HDLC Functional Description ................................................................................................................. 517
24  HDLC Operation  .................................................................................................................................... 517
24.1 Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing) .................... ................ ..................... . ......... 517
24.2 Flags .......................................................................................................................................... 517
24.3 Aborts ........................................................................................................................................ 518
24.4 Receive IDLES .......................................................................................................................... 518
24.5 CRC ........................................................................................................................................... 518
24.6 HDLC Mod e  ............................................................................................................................... 519
24.7 Receive HDLC Transparent Mode ............................................................................................ 519
24.8 Receive HDLC ........................................................................................................................... 519
24.9 Receive HDLC Features  ........................................................................................................... 519
24.10 Transmit HDLC FIFO Features ............................................................................................... 520
25  Framer Phase-Lock Loop (PLL) ............................................................................................................. 522
25.1 Framer Timing Selection ........................................................................................................... 523
26  System Interface .................................................................................................................................... 523
26.1 Syst em Interface Introduct ion ................................. ................... ....... ......................................... 523
26.2 Syst em Interface References/Standards ... .......................................................... ....... . .............. 524
2 6 .3  Tra n s mi t/Receiv e Syst e m Inte r face Features  .................................... ....................................... 524
26.4 Double NOTFAS System Time-Slot (FRM_DNOTFAS ( Table 347)) Mode  ..... ....... .. .......... .. .... 524
26.5 Transparent Mode ..................................................................................................................... 525
26.6 Loopbacks ................................................................................................................................. 525
26.7 System AIS ................................................................................................................................ 525
26.8 Slip Detection ............................................................................................................................ 526
26.9 The Concentration Highway (CHI) Mode  .................... ..... ... .................. ..... ... .................. ..... ... .. 526
26.10 Nominal CHI Timing ................................................................................................................ 526
26.11 CHI T iming with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled  .............. ..... ..... .. .... 528
26.12 CHI Timing with Associated Signaling Mode Enabled  . .............................. ....... . ..................... 529
26.13 ASM 2-Byte Time-Slot Format  ................................................................................................ 529
26.14 CEPT: Time-Slot 16 Signaling ASM 2-Byte Time-Slot Format ....................... ....... .. .......... ...... 530
2 6 .1 5  CHI  O ffset P r ogra mming ....... ....................................................................... ........................... 530

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
477Agere Systems Inc.  
21 28-Channel Framer Block Functional Description (continued)
Table o f Conten ts (continued)
Contents Page
21.26.16 The Parallel Bus System  Int erface M ode ................... ................... .............. ................... .........532
21.26.17 Distributed Stuffing: DS1 ......................................................................................................... 533
21.26.18 Distributed Stuffing: E1 ............................................................................................................ 535
21.26.19 Drive to 3-State and 3-State to Drive   Timing ..................... . ......................... . ....................... . ... 536
21.27  Serial Multiplex Interface ........................................................................................................................ 536
21.27.1 Signals  (6-Pin Mode ) ............................................. . ................................ . .................................. 537
21.27.2 Signals  (8-Pin Mode ) ............................................. . ................................ . .................................. 537
21.27.3 Timing Diagrams ....................................................................................................................... 538
21.27.4 Time-Slot Sequencing ............................................................................................................... 539
21.27.5 Timing Between Transm it and Receive ......................................... ... ................................ ......... 539
21.28  Superf r amer Host  Interface  .......... ....... ...................................... ....... .......................... ............................ 540
21.28.1 Superframer Register Addressing ............................................................................................. 540
21.29  Superframer Register Addres sing ................. ... ....................... ............................ . .................................. 541
21.29.1 Per Link Register Sections in Table 609  . .......................... ............................ ............................ 542
Figures Page
Figure 52. Sw itching Ap plication of the Super Mapper.............. ..................... . ......................... ..... ....................... 479
Figure 5 3. Super Mapper Switc hing Configuration............... . .................. . .................. . .................. . ......................480
Figure 5 4. Super Mapper Switc hing M ode fo r Framer in DS0 Int erface (Parallel or Serial) Configuration 
(The Optional Byte-Sync hronous   VT  Mapping Path Is Shown) ....................... ..... ... ....................... .... 481
Figure 55. Transport Application of the Super Mapper............................ ..... ... ......................... ..... ....... ................ 482
Figure 5 6. Super Mapper T rans port Configuration. . .................. . .................. ..................... . .................. . ............... 483
Figure 5 7. Super Mapper T rans port (with Intrusive Performanc e Monitoring) M ode 
(The Optional Byte-Sync hronous   VT  Mapping Path Is Shown) ....................... ..... ... ....................... .... 484
Fig ure 58. DS1 Transparent Frame Structure......................................................................................................486
Fi gure  59.  CEPT Transpar e n t Fra me Structure .... .............................................................. ................................. 487
Figure 60. HG Alignment Algorithm...................................................................................................................... 497
Figure 61. Rx Data Link  Block Di agram .................................................................................... ........................... 511
Figure 62. Stack Available and Stack Ready Bit Formatting............................................ ....... ................... .......... 512
Fig ure 63. Tx Data Link Block Diagram ................................................................................................................ 516
Fig ure 64. Receive HDLC Block Diagram ............................................................................................................ 519
Fig ure 65. Transm it HDLC FIFO Block Diagram.................................................................................................. 520
Fig ure 66. Framer PLL ......................................................................................................................................... 522
Fig ure 67. Framer Block Transmit Path Timing Selection.................................................................................... 523
Figure 68. System Loopbacks.................................... ......... ............ ....... ............ ............ ......... .............................525
Figure 69. CHI  Mode of the Transmit System Interface....... ................. .......................... ... .................................. 526
Figure 70. Nominal Concentration Highway Interface Timing.............................................................................. 527
Fi gure  71. CHIDTS Mode Concentr a tion Highway Interface Timing.................................................................... 528
Figure 72. Associated Signaling Mode Concent ration Highway  Interface Timing.................... ..... ....... . ............... 529
Figure 73. TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS =  0 (CEX = 3 and CER = 4, 
Respectively)....................................................................................................................................... 531
Figure 74. CHI TCHIDATA and RCHIDATA to CHICK Relationship with  F RM_CMS = 1 
(CEX  = 3  and CER = 6, Respectively) ................................................................................................ 532
Figure 75. Parallel Bus System Interface Mode of the Transmit System  Interface .................. ................. ... ........ 532
Fig ure 76. Parallel Bus System Interface Turnaround T iming.............................................................................. 536
Figure 7 7. Signals (6-Pin Mode)............... ... .................. . .......................... .................. . ......................................... 537
Figure 7 8. Signals (8-Pin Mode)............... ... .................. . .......................... .................. . ......................................... 537
Fig ure 79. Network Serial Multiplexed Interface (Single Octet)............................................................................538
Fig ure 80. Network Serial Multiplexed Interface (Multiple Octets)........................................................................ 539

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
478 Agere Sy stem s Inc.
 
21 28-Channel Framer Block Functional Description (continued)
Table of Conten ts (continued)
Tables Page
Table 5 76. Frame Alignmen t Criteria ................................................................................................................... 489
Table 577. Receive Signaling Link Reg isters 0—31 Bit Description  ................................................................... 491
Table 578. Receive Signaling Link Reg isters 0—31 G-Bit and F-Bit Description .......... ................................. ..... 491
Table 579. Receive Signaling Link Reg isters 0—31 DS1/CEPT/CMI Data ............................ . ............................ 493
Table 580. Receive Signaling Link Reg isters 0—31 Expected Data . ......... ......... ............. ......................... .......... 4 94
Table 581. S ignaling Receive Global Register 3, B it Definition .................................. . ........................................ 495
Table 582.  T ra nsmit Signali ng Link  R egiste rs 0—31 Bit Description .................................................................. 498
Table 583.  T ra nsmit Signali ng Link  R egiste rs 0—31 G-Bit an d F- Bit Description  . .............................................. 498
Table 584.  T ra nsmit Signali ng Link  R egiste rs 0—31 DS1/CEPT/CMI Data ........................................................ 499
Table 585.  T ra nsmit Signali ng Link  R egiste rs 0—31 Expected Data .................................................................. 500
Table 586. Perfo r mance Monitor Funct ional  Descriptions ................ ..... ....... . ......................... . ............................ 503
Table 5 87. Performan ce Repo rt Message Format .............................................................................................. 507
Table 5 88. Performan ce Report Message Field Definition .................................................................................. 507
Table 5 89. Shared Rx Stack F ormat for SLC-96 Frames .................................................................................... 509
Table 5 90. Shared Rx  F DL Stack Format for DDS Frames ................................................................................ 510
Table 5 91. Shared Rx Stack Format for CEPT F rames ...................................................................................... 510
Table 5 92. Shared Tx FDL Stack Format for SLC-96 Frames ............................................................................ 513
Table 5 93. Shared Tx FDL Stack Format for DDS Frames ................................................................................. 514
Table 5 94. Shared Tx S tack  Form at for CEPT Frame  .............. ..... .......................... .......................... ................. 515
Table 5 95. HDLC Frame Format ......................................................................................................................... 517
Table 5 96. Performan ce Repo rt Message Structure ........................................................................................... 521
Table 5 97. Clock Mo de Programming for PLL M ode Device Pins  ............. ... ....................... .......................... ..... 522
Table 5 98. Ass ociated Signaling M ode CHI 2-Byte  Tim e-Slot Format for DS1 Frames . . ......................... ..... ..... 529
Table 599.  A ssociated Signaling Mode CHI  2-Byte Time-Slot Format for Stuffed Channels .............................. 530
Table 6 00.  Associated S ignaling Mode CHI   2-Byte Time-Slot format for CEPT . ..... .......................... .................530
Table 6 01. Programming Values f or FRM_TOFF[2:0]  and F R M_ROFF[2:0 ] when FRM_CMS  = 0 .................... 530
Table 6 02. Program ming Values for FRM_TOFF[2:0] when FRM_CMS = 1 ...................................................... 530
Table 6 03. Program ming Values for FRM_ROFF[2:0] when FRM_C MS = 1 ...................................................... 530
Table 6 04. Parallel System Bus Interface Time-Slot Arrangeme nt for DS1 ........................................................534
Table 605. Parallel System Bus Interface Time-Slot Arrangement for E1 ........................................................... 535
Table 6 06. PSB System I/O Definition ................................................................................................................. 535
Table 607. Serial ID ............................................................................................................................................. 538
Table 608.  Current  Numb er of Globa l and p er Li nk/Cha nnel Registers for Each Block  ... ............. . ................ ..... 540
Table 6 09. Framer Addres s ing Ma p for the Global and Per Link/Channel Registers of the Superframer ........... 541

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

479Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.1 28-Chann el Fram e r Introduc tion

The next two sections describe the switching and transport mode of the superframer. The framer can be configured

into two b asic modes: DS0/E0 switching mode and DS1/E1 transport/monitoring mode.

21.1.1 DS0/E0 Switching Applications

The s witching application of the Super Mapper/superfr amer is shown in Figure 52 and Figure 53. The syst e m in te r-

face is either a parallel interface (e.g., system telecom bus inter face) or a serial system interface (e.g., CHI) that

transmits or receives framed (c hannelized) or unframed (unchannelized ) DS0/E0 time slot s.

In the transmi t line direction (Tx, to the mapper), the framer receives data from the DS0/E0 switch through the sys-

tem interface and sends this data (framed or unframed) to the mapper s ection via the internal DS1 c r os s connect

block. The data co nsis t s of data, clock, and frame sync.

In the receive line direction (Rx), the mapper sends the li ne data and clock (through the internal DS1 cross con-

nect) to the framer block. The framer then takes this data and transmits it to a DS0/E0 switch through the system

interface. Links provisioned for extended s uperframe for mat (E SF) can autom at ically generat e and send perfor-

mance message reports (PRMs) from the Rx path per formance monitor through a Tx path HDLC channel assigned

to the facility data link in the transmit line p ath.

5-8924(F)r.1

Figure 52. Switching Application of the Super Mapper

FRAMER MAPPER

FRAMERMAPPER

SUPER MAPPER #1 SUPER M APPER #1

SUPER MAPPER #2 SUPER M APPER #2

SUPE R MAPPE R #3SUPER MAPPER #3

MAPPER

TELECOM

BUS

STS-3

SYSTEM

INTERFACE SYSTEM

INTERFACE

DS0/E0

SWITCH DS0/E0

SWITCH

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

480 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9017(F)r.1

Figure 53. Super Mapper Switching Configuration

FRAMER

RECEIVE LINE TO TRANSMIT

SYS TEM PATH

(Rx PAT H )

FRAMER RECEIVE SYSTEM

TO TR ANSMIT LINE PATH

(Tx PAT H)

SUPER MAPPER: FRAMER

FDL PRMs

LOOPBACKS

RFS1,

RCLK1,

RDATA28

TFS1,

TCLK1,

TDATA28

SYSTEM IN TERFACE

DS0 I/O

DS2 I/O DS3 I/O SONET/SDH DS 3

MAPPED I/O

DS3 O R T 1/ E1 TO ST S-1

MAPPED OUTPUT

(HIGH-SPEED TELECOM BUS)

M12

MULTIPLEXER D S3 MA PPER

8-bit DATA + 1-bit PARITY

VT/VC

MAPPER VC-4

MULTIPLEXER STM-1

MULTPLEXER

MAPPER

FRAMER

DS1 CROSS

CONNECT

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

481Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Figure 54 show s the fram er block in a switching application. The framer sys tem interface for the transmit path is

labelled re ceive and the receive path is labelled transmit . This may seem an e rr or but is ch osen based on estab-

lished, historical naming conv ention.

5-9018(F)

Figure 54. Super Mapper Switching Mode for Framer in DS0 Interface (Parallel or Serial) Configuration (The

Optional Byte-Synchronous VT Mapping Path Is Shown)

VT MAPPER:

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING RECEIVE DATA

RECE IVE SIG NAL ING DATA

(T O SIGNALING REGISTERS)

VT MAPPER:

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING TRANSMIT DATA

RECEIVE

HDLC RECEIVE

FACILITY

DATA LINK

SUPER MAPPER

VT MAPPER

INTERFACE

Rx LINE

DECODER

RECEIVE

FRAME

ALIGNER

SIGNALING

PROCESSOR

(EXTRACTION)

TRANSMIT

SYSTEM

INTERFACE

TFS1, TCLK 1, TDATA28

SIGNALING

PROCESSOR

(INSERTION)

RECEIVE

SYSTEM

INTERFACE

TRANSMIT

FACILITY DA TA

LINK

TRANSMIT

FRAME

FORMATTER

Tx LINE

ENCODER

SUPER MAPPER

M12

MULTIPLEXER

INTERFACE

Rx PATH

Tx PATH

ESF PRM PAT H

TFS1, TCLK1, TDATA8,

TDATA_PARITYA1

TSIGNALING8,

TSIGNALING_PARITYA1

RFS1, RCLK1, RDATA28

RFS1, RCLK1, RDATA8,

RDATA_PARITYA1

RSIGNALING8,

RSIGNALING_PARITYA1

SYSTEM INTERFACE

PARA LLEL DS0 BUS

SYSTEM INTERFACE

SERIAL DS0 BUS

SUPER MAPPER: FRAMER

TRANSMIT SIGNALING DATA (EXTRACTED

FROM SYSTEM INTERFACES OR

SIGNALING REGISTERS)

PERFORMANCE

MONITOR

TRANSMIT

HDLC

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

482 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

21.2 Tr ans p o r t A pplic at i on s

The transport application of the Super Mapper is depicted in Figure 5 5, Figure 56, and Figure 57. The Super Map-

per in terfaces with LIUs at the DS1/E1 rate in this mode. The data is either framed or unframed DS1s. In the trans-

mit path direction (Tx, to the mapper), the framer receives framed or unframed D S1/E1 data from its line interface

and sends this lin e d ata and clock (via the D S1 cross connect) to the mapper block. The framer can be provi-

sioned to fra me align the data prior to sending it to the mapper section. The framer can be provisioned for perfor-

mance monitoring on the data and in ESF mode transmit PRMs back to its line interface.

In the receiv e path direction (Rx), the mapper sends the line data and clock (through the DS1 cross connect) to the

framer bl ock. This data may be framed or unframed DS1/E1 data. The framer can be provisioned to f ra m e al ign

the data and transmit a frame sync signal in addition to the data and clock. The framer can b e provisioned for per-

for mance monitoring on the data. In ESF m ode, it can automatically generate and send PRMs back to the mapper

interface.

5-8925(F)r.1

Figure 55. Transport App lic ati on of th e Super Mapper

FRAMER MAPPER

FRAMERMAPPER

SUPER MAPPER #1 SUPER M APPER #1

SUPER MAPPER #2 SUPER M APPER #2

SUPE R MAPPE R #3SUPER MAPPER #3

MAPPER

TELECOM

BUS

STS-3

LINE

INTERFACE LINE

INTERFACE

PM PM

PMPM

T1/E1

LINE INTERFACE

UNIT

(T7690 OR T7698)

T1/E1

LINE INTERFACE

UNIT

(T7690 OR T7698)

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

483Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9020(F)r.1

Figure 56. Super Mapper Transport Configuratio n

FRAMER

DS1 RECEIVE LINE PATH

PERFORMANCE MONITORING

(Rx PA TH)

DS1 TRANS MI T LINE PATH

PERFORMANCE MONITORING

(Tx PA TH)

SUPER MAPPER : FRAMER

FDL PRMs

LOOPBACKS

MAPPER-

TO-

FRAMER I/O

CROSS

CONNECT

VT/VC

MAPPER VC-4

MULTIPLEXER STM-1

MULTIPLEXER

8-bit DATA + 1-bit PARITY

DS3

MAPPER

M12

MULTIPLEXER

DS2 I/O DS3 I/O SONET/SDH DS3

MAPPED I /O

RLCK28,

RPD28,TLCK28,

LINE INTERFACE

D S1 I/O

TPD28,

TND28

RND28 DS3 OR T1/E1 TO STS-1

MAPPED OUTPUT

(HIGH-SPEED TELECOM BUS)

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

484 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9021(F)r.2

Figure 57. Super Mapper Trans po r t (with Intru sive P erform an c e Monitori ng ) Mod e (The O ption al Byte-

Synchronous VT Mapping Path Is Shown)

RECEIVE

SIGNALING

PROCESSOR

RX SIGNALING DATA

( T O SIGNAL I N G RE G I STERS)

RECEIVE

HDLC RECEIVE

FACILITY

DATA

LINK

RECEIVE

FRAME

ALIGNER

VT MA PP ER:

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING RECE IVE DATA

VT MA PP ER:

BYTE-SYNCHRONOUS ROBBED-BIT

SIG NAL I NG TRA NSMIT D ATA

SUPER MAPPER

VT MAPP ER

INTERFACE

SUPER MAPPER

M12

MULTIPLEXER

INTERFACE

ESF PRM PATH

PERFORMANCE

MONITOR

TRANSMIT

FRAME

FORMATTER

TRANSMIT

HDLC

TRANSMIT

FRAME

FORMATTER

RECEIVE

FRAME

ALIGNER

TRANSMIT

HDLC

PERFORMANCE

MONITOR

ESF PRM PATH

TX PATH

SIGNALING

PROCESSOR

TRANSMIT

FACILITY

DATA

LINK

TRANSM I T SIG N ALIN G DATA

SUPER MAPPER: FRAMER

RX PATH

TX PATH

TX LINE

ENCODER

RX LINE

DECODER

RLCK28, RPD28, RND28

TLCK28, TPD28, TND28

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

485Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.3 Framer-to-Line Interface Unit Physical Interface

The framer-LIU interface of the Super Mapper framer consists of 28 groups of six connections. The internal DS1

cross connect must be configured to connect the framer-LIU interface through the multifunction system interface to

ex ternal T1/E1 line interface de vices. The six connections for each fr amer are TND, TPD , and TLCK driven from the

transmit framer (receive path) and RPD, RND, and R CLK (transmit path) sourced fro m the ex ternal line interface

devic e. The connections can optionally be from/to the protected switch. See Table 3 on page 15 f or the e xternal pin

names that correspond to the desired six connect ions.

The line i nterface may operate in single-rail or dual-rail mode. The default mode of the line enco der is single-rail

(FRM_LD_MODE[2:0] = 000 (Table 430), FRM_L E_ MO DE [2:0] = 000 (Table 431)). In this mode, the input signals

are passed transparently through the line encoder.

In single rail mode, the link’s framer internal bipolar line encoder/decoder is disabled and monitoring of received

line f ormat violati on is accomplished with the use of the RND input. When RND = 1 o n the risin g edge of RLCK, the

line fo r mat violation FRM_BPV[15:0] (Table 388) counter increme nts by one. The link’s transmit framer transmits

data via the TPD outp ut pin while TND is forced to a 0 state.

In dual rail mode, the internal line encoder/decoder and monitoring are enabled. T he line code may be selected by

provis ioning FRM_LD_MODE[2:0] and FR M_LE_MO D E[2:0]:

1. Alter nate Mark Inversion (AMI ).

2. High-Density Bipolar of Order 3 —G.703, A.1 (HDB3).

3. Binary 8 Zero Code Suppression—G.703, A.2 (B8ZS).

Line format violations due to excessive zeros will be optionally monitored as follows :

1. B8ZS—8 consecutive zeros cause a violation.

2. HDB3—4 consecutive zeros cause a violation.

21.3.1 Lin e Interface References /Standards

1. ITU-T Recom m endat ion G.703, Phy sical/E lectrical Characteristics of Hierarchical Digital Interfaces;1991 .

2. ANSI T 1.403-1995, Network-to-Customer Installation - DS1 Metallic Interface; March 21, 1995.

21.3.2 Frame Formats

The 28 superframers support th e following frame formats:

1. DS1 superframe D4 .

2. DS1 superframe J-D4 with Japanese remote alar m.

3. DS1 superframe DDS.

4. DS1 su perframe

SLC

-96.

5. DS1 extended superf ra me (ESF).

6. Japanese extended superframe J-ESF (J1 standa rd with differen t CRC-6 algorithm).

7. Nonalign DS1 (transparent 193 bits) .

8. CEPT basic frame {ITU G.706}.

9. CEPT CRC-4 multiframe with 100 ms timer {ITU G.706}.

10. CEPT CRC-4 multiframe with 400 ms timer (automatic CRC-4/nonCRC-4 equipment interworking) {ITU G.706

Annex B}.

11. Nonalign E1 (transparent 256 bit s).

12. 2.048 coded mark inversion (CMI) coded interfac e (TT C S tandards JJ-20.11).

13. 6.312 Mbits/s interface (ITU G.704/NTT J2) .

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

486 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

21.3.3 Transmit Framer Functions

1. Transmits alarm indication signal (AIS) to th e line automatically and on demand.

2. Transmits AIS- CI to the line automatically and on demand.

3. Transmits remote alarm indication (RAI) to the line automatic al ly and on demand. Conditions for tran smitting

RAI include; loss of receiv ed frame alignment, CEPT loss of received time slot 0 multiframe alignment, CEPT

CRC-4 timer e xpir ation, CEPT loss of receiv ed time slot 16 signalin g mul tifra me alignment, CEPT received Sa6

equals 8, an d recei ved Sa6 equa ls C .

4. Transmits RAI-CI to the line automatically and on demand.

5. Transmits auxiliar y te s t pattern (AUXP) to the line automaticall y and on demand.

6. Transmits CEPT E bits based received CRC-4 errors.

7. Support the CEPT double not-F AS sys tem mode.

8. Transmits a P R BS test pattern to the line on demand.

9. Transmits line loopback on and off codes to the line on demand (T1.403 s ec tion 9.3. 1).

10. In transport mode, when not in f rame alignment, to optional ly send AIS or transpar ently pass data.

21.3.4 Framing References/Standards

ANSI

T1.403, 1997.

2. ITU-T Recom m endat ion G.703, Phy sical/E lectrical Characteristics of Hierarchical Digital Int erfaces; 1991.

3. ITU-T Recommendation G.704, Synchronous F rame Structures used at 1554, 6312, 2048, 8488 and

44736 kbits/s Hierarchical Levels; July 1995.

4. ITU-T Recommendation G.706, F rame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to

Basic Frame Structures defined in Recomme ndation G.704; 1991.

5. TTC Standard JT-G704, Synchronous F rame Structures used at 1554, 6312, 2048, 8488 and 44736 kbits/s Hier-

archical Le vels; July 1995.

21.4 DS1 Transparent Framing F ormat

The transm it framer can be p rogrammed to transparently transmit 193 bits of CHI system data to the line.

When configured for transparent framing, the transmit framer extracts from the receive CHI system data bit 8 of

time slot 1 and inserts t his bit into the framing bit position of the transmit line data. The other 7 bits of the receive

system time slot 1 are ignored by the transmit framer. The receiv e framer will extract the framing b it (or 193rd bit) of

the receive line data and insert it into bit 8 of time slot 1 of the CHI system data. The other bits of time slot 1 are set

to 0.

Fr ame integrity is maintained in both the trans mi t and receive framer section s.

5-5989(F).ar.1

Fig ure 5 8. DS1 Transparent Frame Structure

TIME-SLOT 1

(STUFF TIME-SLOT)

32 TIM E-SLOT C HI FR A METIME-SLOT 2 TIME-SLOT 3 TIME-SLOT 31 TIME-SLOT 3 2

0000000F BIT

TRAMSMIT FRAMER’S

193-bit FRAME

DS1 = 125 µs

TIME- SLOT 1 TIME-SLOT 2 TIME-SLOT 24F BIT

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
487Agere Systems Inc.  
21 28-Channel Framer Block Functional Description (continued)
In tran sparent framing mode 1, the receive   framer is for c ed not to reframe o n the receive l ine data. Other than bipo-
lar violations and unframed A IS monitoring there is no processing of the receive line d at a. The receive  fr amer will 
insert the 193rd bit of the receive line data  into b it 8 of time slot 1 of the tra nsmit system data.
Bit 8 of time slot 1 o f the  receive  system interface is inser ted  as the 193rd data b it into the transmit line data.
Transparent framing mode 1 is selected b y setting FRM_LNK_TRANSP (Table 421) to 1 and FRM_MODE[3:0] 
(Table 422) to 1000 (nonalign 193rd bit).
In transparent framing mode  2, the receive framer f unctions normally on receive li ne data. Al l nor mal monitoring of 
receive line data is perform ed and data is passed to the transmit  CHI as programmed. The receive fr amer will 
insert the extracted fram ing bit of the receive line data into bit 8 of time slot 1 of the  transmit system data. The 
remaining bits in time slot 1 are set to 0.
Bit 8 of time slot 1 of the receive  system interface is inserted in the tra nsmit l ine f r aming bit position.
Transparent framing mode 2 is selected b y setting FRM_LNK_TRANSP (Table 421) to 1 and selecting t he appro-
priate fr aming mode with FRM_MODE[3:0] (Table 422).
21.5   CEP T  2.04 8 Ba si c F rame S t ruc t ur e Transpar ent Fr amin g  F or mat
The  transm it  framer  can be  programmed to transparently tran smit 256 bits of CHI system data to  the line. The 
transmit framer must be programmed  to transparent framing mode 1.
In trans parent mode, the transmit framer transmits all 256 bit s of the system p ayl oad unmodif ied to the l ine. Time 
slot 1 of the CHI system interface, determined by the system frame sync signal, is inserted into  the FAS/NOTFAS 
time slot of the tra nsmit line interface.
Fr ame integrity is maintained in both the trans mi t and receive framer section s.
5-5988(F)
Figure 59.  C EPT Transparent Frame  S tructure
In transparent framing  mode 1, the receive  framer i s forced not to reframe on the receive line data. Other than bi po-
lar violations and unframed  A I S mo nitoring, there is  no processing of the receive line data. The entire receive line 
payload is transmitted unmodified to the  CHI.
Transparent framing mode 1 is selected b y setting FRM_LNK_TRANSP (Table 421) to 1 and FRM_MODE[3:0] 
(Table 422) to 0000 (non-align 256th bit).
In tr ansparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitoring 
of receive line data is performed and dat a is transmitt ed to the CHI as programmed.
Transparent framing mode 2 is selected b y setting FRM_LNK_TRANSP (Table 421) to 1 and selecting the appro-
priate fr aming mode with FRM_MODE[3:0] (Table 422).
TIME- SLOT 1 32 TI ME - SL OT CHI FR AM ETIME -SLOT 2 TIME-SLOT 3 TIME-SLOT 31 TIME-SLOT 32
TIME- SLOT 1 32 TI ME - SL OT LI NE FRAMETIME-SLOT 2 TIME-SLOT 3 TIME-SLOT 31 TIME-SLOT 32

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

488 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

21.6 Rece iv e F r am e r Nonali g nment Mod e (DS 1/ E 1)

In the non-align framing modes the receiv e frame aligner does not frame to the receive line data. Other than bipolar

violations, AIS, and AU XP monitoring, there is no processing of the receiv e line data. The entire rece ive line frame

is g iven unmodified to the sy s tem int erface.

21.6.1 Loss of Frame Alignment Criteria

There are two criteria for declaring loss of frame: frame bit error s and CRC errors.

Fra me Bit Errors.

1. T1: two frame bit errors out of 4 fr ame bi t s (FT and FS bits checked).

2. T1: two frame bit errors out of 5 fr ame bi t s (FT and FS bits checked).

3. T1: two frame bit errors out of 6 fr ame bi t s (FT and FS bits checked).

4. T1: three frame bit errors o ut of 12 frame bits—DDS o n l y ( FT, FS, and t ime slot 24 F bits).

5. T1: two frame bit errors out of 4 fr ame bi ts (only FT bits checked).

6. T1: two frame bit errors out of 5 fr ame bi ts (only FT bits checked).

7. T1: two frame bit errors out of 6 fr ame bi ts (only FT bits checked).

8. T1: f ou r frame bit e rrors o ut o f 12 f rame bits—DDS only (FT, FS and time slot 24 FAS pattern).

9. E1: three consec utive incorrec t frame alignmen t signals.

10. E1: three consecutive incorrect frame alignment signals or three consecutive incorrect non-FAS frames as indi-

cated by bit 2 in time slot 0 in frames not containing the frame alignment signal.

11. E1: 3 consecutive incorrect FAS or non-FAS fr ames.

12. 2.048 Mbits/s CMI: 2 consecutive missing code rule violations (CRVs).

CRC Errors.

The use of CRC errors to declare loss of frame is optional. CRC errors are monitored in the per formance monitor

block.

In DS1 mode, ESF, and J-ESF formats only, N or more CRC-6 errors in a 1 second inter val results in loss o f frame

alignment. N is provisionable. N defaults to 320 in DS1 mode.

In CEPT mode N, or m ore, CRC-4 errors in a 1 second int erval results in loss of frame alignment. N is provision-

able. N defaults to 915 in CEPT modes.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

489Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.7 Fra m e Ali gn m ent Crite r ia

Table 576 desc r ibes t he frame alignment criter ia for the formats supported by the supe rframer.

Table 576. Frame Alignment Criteria

21.8 Receive and Transmit Signaling Processor

21.8.1 Signaling Introduction and Feature Description

The signaling processor, which is dupl icated in the receive an d transmi t paths, moves signaling data to and from

the foll owi ng interfaces:

■T1/E1/J 1/CMI l ine interface

■System interface

■VT mapper interface

■Host interface

The following frame types are supported when proce ssing signaling to a nd f rom the line interface (no special provi-

sioning is needed for the signaling processor to distinguish between these fr am e types):

■DS1: E SF; J -ES F; D4 ; J-D4 (2-, 4-, o r 16-state mode)

■CEPT Basic Frame; CE PT CRC-4 (100 ms); CEPT CRC-4 (400 ms)

■CMI

Frame Format Alignment Procedure

SF Frame alignmen t i s established when six consecut ive erro r-free superfram es are

received. Only the FT framing b its are checked (36 bits checked).

D4 and J-D4 Frame a lignment is establis hed when six consecutive error-free superframes are

received (72 bits checked in D4, 66 bits checked in J-D4).

DDS Frame alignment i s established when six consecut ive er ror-free frames are

received (42 bits checked: FT, FS, an d time slot 24).

SLC

-96 The FT frame position is estab lished when f our consecutive error-free superframes

are received (24 FT bits check ed). After establ ishing the FT fr ame position,

SLC

-96

superframe alignment is es tablished on the fir st valid FS sequence of

000111000111. All the while the FT f ra me po sition must remain error free.

ESF and J-ESF Frame alignment is established when three consecutive error-free superfr ames are

received (18 bits checked).

CEPT Basic Fram e Uses the strategy out lined in G.706 paragraph 4.1.2.

CEPT CRC-4 100 ms Timer Uses the strategy outlined in G.706 paragraphs 4.1.2 and 4.2.

CEPT CRC-4 400 ms Timer Uses the strategy outlined in G.706 paragraph 4.1.2 and ANNE X B.

2.048 Mbits/s CMI Coded

Interface Frame alignment is established on the f i rst detection of the CRV violation. Multi-

frame alignment is achieved the first time the 01111111 multiframe ali gnment pat-

tern is detected.

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

490 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

The following s ystem bus modes are s upported (no special prov isioning is needed for the signaling proce ssor to

distinguish bet ween these system bus modes):

■Parallel system bus

■CHI bus i n ASM mode

The VT mapper interfac e in the sign aling processor supports VT1.5, VT 2 byte sync mapping, as wel l as V C-11

byte sync mapp ing using handling groups.

The host can read the signaling data extracted from the line, system, or VT mapper interface at an y time. T he

transmit signaling processor can be configured so that the host provides t he signaling data to be forwarded to the

line, system, or VT map per interface.

Other si gnali ng features include:

■Debounce on a ll signaling data extracted from the line interface o r the VT m apper interface.

■Host interrupt upon ch ange of sign aling state in the receive path.

■Sign aling extrac tion inhibit based on frame alignment and fram ing bit errors.

■Stomping of DS1 robbed-bit signaling p o sitions.

■Suppor t of zero-code suppres s ion on the line interface in the transmit path.

■Superf rame s ignaling integrit y. No signaling data tra nsmi tted will be a mix of old and new due to a mid super -

frame update of signaling informat ion.

21.8.2 Signaling References/Standar d s

■ITU Rec. G.704 10/98 CEPT Multiframe Signaling Structure

■ITU Rec. G.775 10/98 CEPT TS16 AIS Detection, Remote Alar m Detection

■ITU Rec. G.732 1998 CEP T T ime-Slot 16 mfa, Time-Slot 16 rfa

■ITU Rec . O.162 10/92 CEPT Time-Slot 16 rfa De tection

■T1.4 03 1995 Robbed-Bit Signaling

■TTC JJ-20.11 CMI Coded Interface

■

ANSI

T1.105 SONET Payload Mapping

■

Telcordia

GF-253-CORE SONET Transport Systems

■ITU Rec G.707 10/ 98 Net work Node Interface for SDH

■TTC JT G.704 Japanese Syn chronous Frame Str uct ures

21.9 Receive Sign al ing Pe r-Link Fe at ure Provisioning

The receive signal ing processor requir es t he provis ioning of f our items for eac h link in order to enable signaling

extraction and delivery:

1. Signaling state mode source (host or Rx CHI interface).

2. Signaling state mode (2-, 4-, and 16-state mode or no-s ignaling).

3. Signaling source (receive line, VT mappe r, o r host i nterface).

4. Signaling destination (trans mit syste m or transmit line interface).

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

491Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.9.1 Signaling State Mode Sou rce Selection

The signaling state mode so urce is selec ted by progra mming FRM_R_FGSRC in Table 374, FRM_RSLR33,

Receive Si gnali ng Lin k Regist er 33 (R/W) on pa ge 269, bit 2. The typical application will select the host for pro-

gramming the sta te mode. If so , the host will have to program the state mode for all of the t im e slots o n each of the

links. The default state mode selected is 16-state signaling.

It is possible for the state mode to be set by the values received on the CHI bus by the receive system interface. In

this mode, the signaling processor will constantly monitor those values and update the state mode for each of the

time slots on each link.

21.9.2 Signaling State Mode Selection

The signa ling state mode for each time slot is se lected by programming bits 5 and 6 of FRM_RSLR0—

FRM_RSLR31, Receive Signali ng Link Registers 0—31 (R/W) in Table 372 on page 268 for eac h link. The bit defi-

nition for each of those 32 registers i s shown below.

Table 577. Receive Signaling Link Registers 0—31 Bit Description

The signaling state mode definitions are shown in the table below.

Table 578. Receive Signaling Link Registers 0—31 G-Bit and F-Bit Description

The signa ling state m ode for DS1 type links sh ould be set to match the fu n ction of each time slot. The signaling

state mode does not apply to CEPT type links and the value must be ke pt in the reset state which is 00. The signal -

ing state mode for CMI type links must be set to 11.

The 16-state mode, which is the sta te mode se lected out of reset, can be used on SF type DS1 links in order to

detect a toggle code. In th is case, signaling will be collected over two superframes and stored as a 4-bit code.

When programming the state mode for each time slot, the host can also program the D, C, B, and A bits in the

same register. Doing this will determine the de fault code forwarded to the t ransmi t system or the transmit line inter-

face before the first valid signaling code has been extracted f rom the recei ve line or VT mapper inter face.

Each o f the links and time slots is completely independent from one another with respect to the signaling s tate

mode s e lection. Any combination i s acceptable.

21.9.3 Signaling Source Selection

The signaling source is selected by programming FRM_R_SIGSRC in Table 374, FRM _RSLR33, Receive Signal -

ing Link Register 33 (R/W) on page 269, bits [1:0]. If the source selected is the receive line interface, the recei ve

signaling processor will start extracting data from the receive line and store v alid signaling cod es into the D, C, B,

and A lo ca tions of FRM _RS LR0—FRM_RS LR31, Rec eive Signaling Lin k Registers 0—31 (R/W), Tabl e 372 on

page 268 for each of the links.

The receive signaling processor will automatic ally deter mine the link t y pe and extract the correct signaling bit posi-

tions from each link. The receive signaling processor can simultaneously service any com bination of CEP T, DS1,

and CMI type links. The rece ive signal ing processo r will extrac t rob bed-bit signaling from DS1 links, common chan-

nel signaling from CEPT links, and time slot 0 signaling from CMI links compli ant with the following standards.

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GF—DCBA

G and F Signaling State Mode Selected

00 16 state (reset state)

01 4 stat e

10 no signaling

11 2 state

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
492 Agere Sy stem s Inc.
 
21 28-Channel Framer Block Functional Description (continued)
■ITU Rec  G.704 10/98 CEPT multiframe signaling structure
■T1.4 03 1995 robbed-bit signaling
■TTC JJ-20.11 CMI coded interfac e
If the VT mapper is  transporting byte sync mapped DS1 links into SONET frames, then the signaling source should 
be set to VT mapper interface. In that case, the receive signaling processor will star t collecting valid signaling 
codes f r om the VT mapper an d s tore them into the D, C, B, and A  locat ions  of FRM_RSLR0—FRM_R SLR31, 
Receive Si gnali ng Lin k Regist ers 0—31 (R/W), Table 372 on page 268 for each of the links.
If the VT m apper is the s ource of s ignal ing, data  will be extracted based on the standards listed below.
■
ANSI
 T1.105SONET payload mapping
■
Bellcore
 GF-253-CORE SONET transport systems
■ITU Rec  G.707 10/98 network node i nterface for SDH
If the VT mapper is transporting byte sync mapped CEPT links into SONET frames, t hen the  signaling source 
should be set to the receive line interface. In that case, the receive signaling processor will extract the entire time 
slot 16 multiframe and st ore that information into F R M_RSLR0—FRM _RSLR31,  receive signaling link regis ters 
0—31 (R/W) for each of the links.
If the signaling source is set to be the  host, the host may write to FRM_RSLR0—FR M_RSLR31, receive signaling 
link registers 0—31 (R/W) and those values will be forwarded to the sel ected de stination. The  host m ode can also 
be used to manually fr eeze signaling.  When the source is switched from receive line to host, for example, the  exist-
ing signaling c odes will be held until  modified by the host or until the signalin g sou rce is switched back to the 
receive line interface. If the host  mo de is used to manual ly freeze signali ng, th en the signaling debounce feature 
must be en abled. To enable signaling debounce set  FRM_R_SIGDEB in Table 374, FRM_RSLR33, Receive Sig-
naling Link Re giste r 33 (R/W) on page 269, bits 5 to 1.
Each o f the links is completely i ndependent  from one another with respect to the signaling source selection.   Any  
combination of  receive li ne, VT mapper, and  host is acceptable.
21.9 .4 Signalin g De st ination Selec tion
There are three destinations for the signaling extracted from the receive line or VT mapper interface:
1. Transm it system  interface.
2. Transm it  line interface.
3. FRM_RSLR0—FRM_RSL R31, receive signaling link registers 0—31 (R/W ), Table 372 on page268 .
The signaling extrac ted from t he re ce ive line or VT mapper interface wil l automatically be delivered to the transmit 
system interf ace when the framer section of the Super Mapper is programmed fo r switch mode. This is done by set-
ting FRM_SW_TRN in FRM_SFGR1, Superframer Global Register 1 (R/W), Table 301 o n pag e243, bits 15 to 1. 
The syste m interface will need to be configured for A SM mode in order for the sig naling to  be transmitted on the 
PSB or CHI buses. A SM mode is controlled by FRM _SYSGR1, System Interface Glob al Register 1 (R/W), 
Table 347 on page257  bit 11.
The  signaling ex tracted from the VT mapper interface can be inserted into the  tra ns mit line interface when the 
framer section of the Super Mapper is programmed for transpo rt  mode. This is done by sett ing FRM_SW_TRN in 
FRM_SFGR1, S uperf ramer Glo bal Register 1 (R/W), Table 301 on page243 , bits 15 to 0, and by setting 
FRM _R _S I GI  in Table 374, FRM _RSLR33, Receive Signaling L ink Register 33 (R/W) on page 269, bit 8 to 1. The 
signaling will be inserted based o n the pr og ramm in g of sta te m odes of each time slot.
The receiv e signaling processor cannot provide data to the transmit system and the tr ansmit line interface  on differ-
ent li nks simultaneously.
Signali ng extracted from the VT mapper or receive line interface will always be available in FRM_RSLR0—
FRM_RSLR31,  Receive Signali ng Link Registers 0—31 (R/W), Table 372 on page268  for each link. The host can 
read these registers regardless of  whether or not the signaling is forwarded to the transmit   system or tr ansmit line 
interf ace. Receive Signaling Link Registers 0—31 DS1/CEPT/CMI Data,  Table 577 on page 491 shows the position 
of t he data in those 32 registers for each  of the receive line formats.

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

493Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table 579. Receive Signaling Link Registers 0—31 DS1/CEPT/CMI Data

For CE PT links, the entire tim e s lot 16 m ultiframe is stored in FRM_R SLR0—FRM_R SLR31, receiv e signaling link

registers 0—31 (R/W), Table 372 on page268 . The spare b its X[2:0] and the time slot 16 remote frame alarm Y bit

are stored in RSLR0. When time slot 16 multiframe alignment is lost, X[2:0] w ill automatically be set to 111 and the

Y bit will be set to 0.

T he format of the data stored in FRM_RSLR0—FRM_RSLR31, Receive Signali ng Link Registers 0—31 (R/W),

Table 372 on page 268 also depends on the signaling state mode selected for each tim e slot as shown inTable 580.

RSLR Address RS L R B it[6:0] ( DS1) RSLR Bit[6:0] (CE PT) RSLR Bit[6:0] (CMI)

0—000 X0 Y X1 X2 —

1 GF0 DCBA (Channel 1) 000 DCBA (Channel 1) 110 DCBA (Channel 1)

2 GF0 DCBA (Channel 2) 000 DCBA (Channel 2) 110 DCBA (Channel 2)

3 GF0 DCBA (Channel 3) 000 DCBA (Channel 3) 110 DCBA (Channel 3)

4 GF0 DCBA (Channel 4) 000 DCBA (Channel 4) 110 DCBA (Channel 4)

5 GF0 DCBA (Channel 5) 000 DCBA (Channel 5) 110 DCBA (Channel 5)

6 GF0 DCBA (Channel 6) 000 DCBA (Channel 6) 110 DCBA (Channel 6)

7 GF0 DCBA (Channel 7) 000 DCBA (Channel 7) 110 DCBA (Channel 7)

8 GF0 DCBA (Channel 8) 000 DCBA (Channel 8) 110 DCBA (Channel 8)

9 GF0 DCBA (Channel 9) 000 DCBA (Channel 9) 110 DCBA (Channel 9)

10 GF0 DCBA (Channel 10) 000 DCBA (Channel 10) 110 DCBA (Channel 10)

11 GF0 DCBA (Channel 11) 000 DCBA (Channel 11) 110 DCBA (Channel 11)

12 GF0 DCBA (Channel 12) 000 DCBA (Channel 12) 110 DCBA (Channel 12)

13 GF0 DCBA (Channel 13) 000 DCBA (Channel 13) 110 DCBA (Channel 13)

14 GF0 DCBA (Channel 14) 000 DCBA (Channel 14) 110 DCBA (Channel 14)

15 GF0 DCBA (Channel 15) 000 DCBA (Channel 15) 110 DCBA (Channel 15)

16 GF0 DCBA (Channel 16) ——

17 GF0 DCBA (Channel 17) 000 DCBA (Channel 17) 110 DCBA (Channel 17)

18 GF0 DCBA (Channel 18) 000 DCBA (Channel 18) 110 DCBA (Channel 18)

19 GF0 DCBA (Channel 19) 000 DCBA (Channel 19) 110 DCBA (Channel 19)

20 GF0 DCBA (Channel 20) 000 DCBA (Channel 20) 110 DCBA (Channel 20)

21 GF0 DCBA (Channel 21) 000 DCBA (Channel 21) 110 DCBA (Channel 21)

22 GF0 DCBA (Channel 22) 000 DCBA (Channel 22) 110 DCBA (Channel 22)

23 GF0 DCBA (Channel 23) 000 DCBA (Channel 23) 110 DCBA (Channel 23)

24 GF0 DCBA (Channel 24) 000 DCBA (Channel 24) 110 DCBA (Channel 24)

25 —000 DCBA (Channel 25) 110 DCB A (Channel 25)

26 —000 DCBA (Channel 26) 110 DCB A (Channel 26)

27 —000 DCBA (Channel 27) 110 DCB A (Channel 27)

28 —000 DCBA (Channel 28) 110 DCB A (Channel 28)

29 —000 DCBA (Channel 29) 110 DCB A (Channel 29)

30 —000 DCBA (Channel 30) 110 DCB A (Channel 30)

31 —000 DCBA (Channel 31) 110 DCB A (Channel 31)

TMXF 28155/51 Super Mapper Prelim inary Data Sheet
155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001
494 Agere Sy stem s Inc.
 
21 28-Channel Framer Block Functional Description (continued)
Table 580. Receive Signaling Link Registers 0—31 Expected Data
If the state mode is 4  state or 2 state, then the unused bits will be set to 0.
21.10   O p t ion a l Rece ive  S ignal in g F eat u r es   Pro visio ne d f o r  E ach  Lin k
21.10.1 Support of DS1 Robbed-Bit Stomping
The DS1 robbed-bit po sitions of voice time sl ot s will be set to 1 in the payload when FRM_R_RXS TOMP in 
FRM_RSLR33,   Rec eive Signaling Lin k Register 33 (R /W) , Table 374 on page 269, bit 7 is set to 1. T he r obbed-bit 
positions in the pay load will be stomped; however,  the signaling will  be transmitted untouched by the system inter-
face.
21.10.2 Suppo rt of  CE P T Time Slot 16 Stomping
Stompin g of time slot 16 for CEPT links is enabled in the system interface block.The Super Mapper c an also be 
configured to transmit AIS on the system  bus in time slot 16 when the si gnali ng block loses time slot 16 alignment. 
The configuration b its related to these two features are located in the FRM_SYSLR2,  System Interface Link Regis-
ter 2 (R/W), Ta ble 419 on page 294. Whe n using these features, the signaling codes forwarded to the transmit sys-
tem bus will continue to reflect the contents of FRM_RSLR0—FRM_RSLR31, Receive Signaling Lin k Registers 
0—31 (R/W), Table 372 on pag e268.
21.10.3 Support of Signaling Debounce
If programmed  to do so, the s ignaling ex tracted from the selec ted source will be debounced. This implies that a 
val id signaling code would ha ve t o be  detected twice bef ore it is updated in FRM_RSLR0—FRM_RSLR31, Receive 
Signaling Link Registers 0—31 (R/W), Table 372 on page268 . This feat ur e is enab led by setting FRM_R_SIGDEB 
in FRM_RSLR33,  Rec eive Signaling Link  Register 33 (R/W), Table 374 on page269 , bit 5.
21.10.4 Suppo rt of  Japanese Hand ling G roups
If the signaling is transporte d by the VT mapper within four handlin g gro ups co mp lian t  to the Japane se standard, 
TTC JT G. 704, then FRM_R_HGEN in FRM_RSLR33, Receiv e  Signaling Link Register 33  ( R/W), Table 374 on 
page 269, bit 4 must   be set to 1. The signal ing state mode must be set to either 2 state or no- signaling when using 
handling groups.
If the signaling transported by the VT mapper uses handling groups, then th e status  of t he handling gr oup align-
ment can be transmitted across the system interface. The transmission of this status is enabled by setting 
FRM_R_T SAISHG in FRM_SGR1, Receive Signaling Global Register 1 (R/W), Table 359 on page 262,  bi ts 15 to 
1. This mode forces the signaling data for  the c hannels contained in each handling group to 1 if HG alignment has 
not been achi eve d  by the  receive signaling processo r. For  example, if HG2 is unaligned then the A bit for time slots 
2, 6, 10, 14, 18, and 22 for warded to the system would be forced to 1.
21.11  Receive Signalin g Global Feature Provisionin g
The receive signaling processor requires the pro visioning of one global item in order to enable signa ling extraction 
and delivery.
■Link count (number of active receive links).
Signaling State Mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
16 state 0 0 0 D C B A
4 state 01000BA
2 state 110000A

Preliminary Data Sheet TMXF28155/51 Super Mapper
May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
495Agere Systems Inc.  
21 28-Channel Framer Block Functional Description (continued)
21.11.1 Link Count Sel ecti on
The link count is specified by prog ramming FRM_R_LINKCNT[4:0] in FRM_SGR1, receiv e signaling global regis ter 
1 (R/W), Table 359 on page262, bits  [14:10]. The reset value is 28, which is appropri ate for a 28 link DS1 applica-
tion. A value of 21 i s appropriate for a  21 link  CEPT application. If the application mixes DS1 and CEPT links or the 
TDM clock supplied to the framer sectio n   is less than 51.84 MHz, this value should match th e  t erm inal count set i n 
FRM_FGR2,   framer global register 2 (R/W), Table 306 on page246 , bits [7:0].
21.12  Other Rece ive Signalin g Global Features
21.12.1 Support of Automatic Signaling Freeze on Framing Bit Errors
By def ault, signaling extracti on from a particular link will halt when the appropriate alignment has been lost. In order 
to guarantee that signaling freeze takes place  as  soon as possibl e, F R M_R_AFZFBE in FRM_SGR1, Receive Sig-
naling Global Register 1 (R/W), Ta ble 359 on pa ge262,  bit 1 must set  to 1. W hen e nabled, FRM_R_AFZ FBE hal ts 
signaling extraction  for 32 frames upon detection o f a frame bit error. This  configuration bit is applicable to DS1, 
CEPT, and CMI type  frames and for si gnali ng ex t racted from the receive line or the VT mapper interface. When  
FRM_R_AFZFBE is   enabled, the receive signaling debounce feature must also be enabled. The FRM_R_SIGDEB 
feature is enabled in FRM_RSLR 33,   Rec eive  Signa ling Link Reg ister 33 (R/W) ,  Table 374 on pag e269, bit 5.
21.12.2 Support of Change of Signaling Sta te FIFO
Signaling can be ter minated in the framer section of the Super Mapper by polling FRM_RSLR 0 —FRM_RSLR31, 
Receive Si gnali ng Lin k Regist ers 0—31 (R/W), Table 372 on page 268 for  each link. An alternative m e thod is  to 
enable the operation of a signaling change of state FIFO. In doing so, the host will be interrupted when there have 
been signaling state changes which need to be processed. In order to enable the ope ration of the signaling change 
of sta te FIFO,   s et   FRM_R_S C OSEN in FRM_S GR2,   Receive Signaling Global Regis ter 2 (R/W), Table 360 on 
page 262, bit 15 to 1.
The  FIFO is loca ted a t signaling receive global register 3. The wor d read by the host  has the following format.
Table 581. Signaling Receive Global Register 3, Bit Definition
The data read by the ho st indicates the link number (L [4:0]), time slot number (TS[4:0]) and the signaling informa-
tion for a ti me slot whose value has changed. The wo r d r ead by the host will also indi cate whether or not the entry 
is valid (V = 1) and whether or not   there are more entries yet to be re ad  (M = 1). A word with V set to 0 indicates  
that the  FIFO is e mpty.  The signalin g code presented wil l  refle ct the associated GF value progra mmed  by the host. 
The  unused signaling bits  will be set to  0.  For  example, if the t ime slot is programmed for 4-stat e s ignaling, the D 
and C bits will be set to 0. The A and B bit will identify the valid signaling code.
This feature can be used in c ombination with any  other feature (i.e.,  debounce).
When the ch ange of state FIFO is enable d , the host will be interrupted when one of two conditions is satisfied. If 
the number of entries in t he FIFO exceed the threshold programmed by  the host or  if there are valid entries to be 
processed and the signaling int er r upt timer has ex pi red, then the host will be interrupted.
The host  s ets the FIFO depth threshold by   programming FRM_R_SCOSDTH[9:0] i n FRM_SGR2, Receive Signal-
ing Global Register 2 (R/W), bi ts [9:0]. The depth of the FIFO is 672, which is suff icient to store an entry for every 
time slot process ed by the 28-link fr amer. The timer interval is  selected by programming FR M _R_SC OSTTH[15:0] 
in FRM_SGR3, Receive Signaling Global Re giste r 3 (R/W),  Table 361 on page 263,  bi ts [15:0]. Th e tim er i ncre-
ments are 125 µs and the maximum interval possible is 8 s. The default setting for t he depth and timer threshold is 
0, which results i n the host being interrupted whenever an entry i s made into the FIFO.
If the FIF O overf lows, the processor  wi ll immediat ely  be inte rru pt ed. The cur rent c ontents of  the FIFO will b e lost  
ho wever, subsequent entries will be stored normally.
The host can poll the change of state FIFO without the use of interrupts.
Bit 15 Bit 14 B it 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
M V L4 L3 L2 L1 L0 TS4 TS3 TS2 TS1 TS0 D C B A

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

496 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

21.13 Receive Signaling Interrupts

There are three interrupts which are maintained in the rece ive signalin g processor, which are located in

FRM_SG R7 , receive signa ling g lobal regi ster 7 (R/W ), Table 365 on page264 . The three interrupt s reflect the sta-

tus of the change of signaling state FIFO. These interrupt bits can be reset based on a cle ar-on-read protocol,

which is p rovisioned in the Super Mapper global registers.

■Thr es hold overflow interrupt. This bit is set to 1 when the programmed threshold for the FIFO capacity h as been

exceeded.

■Inte r r upt ti me r interru pt. This bit is s e t to 1 when the programmed inte rrupt timer has expired and there are valid

entries in the FIFO to be pro cessed.

■FIFO o verflow interrupt. This bit is set to 1 when the FIFO over flows.

There are mask bits associated with each of t he three interrupt statu s bits which are located in FRM_SGR7,

receive signaling global register 7 (R/W).

21.13.1 Maintenance of the Change of Signaling State FIFO Status Bits

There is one bit which reflects the status of the change of signaling stat e FIFO. The location of this status bit is in

FRM_SG R5 , receive signa ling g lobal regi ster 5 (RO), Table 363 on page263 .

■FIFO depth threshold overflow status. Thi s bit is set to 1 when the programmed thresh old for the FIFO capacity

has been exc eeded.

21.13 . 2 Maintenance of Ha ndling Group R elat ed Sta t us Bits

There are three bits which reflect the status of the handling groups extracted fr om the VT mapper interface. There

are four handling groups on each link therefore there will be thre e copies of the following bits for each l ink. The

location of these status bits are in FRM_RSLR33, Receive Signaling Link R egister 33 (R/W), Table 374 on

page 269.

■Loss of HG alignment. Alignment uses the 0101010 . . . framing patter n and follows the alignment algorithm

shown in Figure 60 on page497 .

■AIS detecti on with in each handling group (AIS detection 48 consecutive ones, AIS loss any two zeros).

■RDI detection within each handling group (RDI detection is the presence of three consecutive zeros in the Sp bit

position).

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

497Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9024(F)r.1

Figure 60. HG Alignment Algorithm

21.14 Transmit Signaling Per-Link Feature Provision ing

The transmit signaling processor requires the provisioning of four items for each link to enable signaling extraction

and delivery.

■Signaling State Mode So urce (host or Rx CHI interface)

■Sign aling State Mode (2-, 4-, and 16-state mode or no-signaling)

■Signaling Source (receive line, receive system, or host interface)

■Signaling Destination (V T mapper or transmit line interface)

21.14.1 Signaling State Mode Sou rce Selection

The signaling state mode so urce is selected by progra mming FRM_T_FGSRC in F RM_TSLR32, Transmit Signal-

ing Link Register 32 (R/ W), Table 378 on pag e272, bit 2. The typical application will select the host for program-

ming the state mode. If so, the host will ha ve to program the s tate mod e for all of the time slots on each link.

RESET

n = 1

(n) = 0 AND

(n + 8) = 1 AN D

(n + 16) = 0 AN D

(n + 24) = 1 NO

YES

LOF FOR HG

n = n + 1

n = n + 32

(n) = 0 AND

(n + 8) = 1 AN D

(n + 16) = 0 AN D

(n + 24) = 1

n = n + 25

YES n = n + 16

YES n = n + 32

MF A FOR HG

- INDICATES S bits FROM VT MAPPER (S1, 2, 3, 4)

n - INDICATES THE SEQUE NCE OF EACH S

bit RE CE IV E D

- INDICATES THE HG (HG1 , 2, 3, 4) ASSOCIATED

WITH THE CORRESPONDING S bit (S1, 2, 3, 4)

LOF FOR HG

TMXF 28155/51 Super Mapper Prelim inary Data Sheet

155/51 Mbit s/s SONE T/SD H x28/x21 DS1/E 1 Ma y 2001

498 Agere Sy stem s Inc.

21 28-Channel Framer Block Functional Description (continued)

It is pos s ible for t he s tate mode to be implied by the values received on the C HI or PSB bus b y the receive system

interface. In this mode, the signaling processor will constantly monitor those values and updat e the state mode for

each of the time slots on each link.

21.14.2 Signaling State Mode Selection

The signaling sta te m ode is sel ect ed by programming bits 5 and 6 in FRM_TSLR0—F RM_TSLR31, Transm it Sig-

naling Link Re gisters 0—31 (R/W), Table 372 on pag e268 for each link. The bit de finition for each of those 32 reg-

isters is illustrated below.

Table 582. Transmit S ignal i ng Link Regi sters 0—31 Bit Description

The signaling state mode definitions are illustrated in the table below.

Table 583. Transmit S ignal i ng Link Regi sters 0—31 G-Bit and F-Bit Description

The signa ling state m ode for DS1 type links sh ould be set to match the fu n ction of each time slot. The signaling

state mode does not apply to CEPT type links and the value must be ke pt in the reset state which is 00. The signal -

ing state mode for CMI type links must be set to 11.

The sixteen state mode, which is the st ate mode selected out o f reset, can be use d on SF-type DS1 links in order

to detect a toggle code. In this case, signaling will be collected over t wo superframes and stored as a 4-bit code.

When programm ing the state mode for each time slot, the hos t can al so program the DCBA bits in the same regis-

ter. Doing this wil l determine the default code forwarded to the transmit line or the transmit VT mapper inte rface

before the firs t valid signaling code ha s been extracte d from the receive line or receive system interface.

Each o f the links and time slots is completely independent from one another with respect to the signaling state

mode s e lection. Any combination i s acceptable.

21.14.3 Signaling Source Selection

There are three sourc es for signaling in the transmit path.

■Transmit Sign aling Link Regi s ters 0—31 (host programmed)

■Receive System Interface

■Receive Line Interf ace

The signa ling source is selected b y programming FRM_T_SIGS RC[1:0] in FR M_TSLR32, transmit signaling li nk

register 32 (R/W), Table 373 on page269 , bits [1:0]. If th e source of signali ng i s t he h os t , then the transmit signal-

ing link registers 0—31 must be programmed with valid signaling. Tab l e 584 on pag e499, shows the organization

of s ignaling data in those regi sters for the different types of l inks.

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GF—DCBA

G and F Signaling State Mode Selected

00 16 state (reset state)

01 4 stat e

10 No signali ng

11 2 state

Preliminary Data Sheet TMXF28155/51 Super Mapper

May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

499Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table 584. Transm it Signa ling L in k Registers 0—31 DS1/C EPT/CMI Data

For CEPT links, the entire time slot 16 multiframe is sourced from the transmit signaling link registers

(TSLR) 0—31.

The time slot 16 mult iframe alignment pattern is transmitted from T SLR 16. That location must be wr itten to 0 if the

correct time slot 16 multiframe alignment pattern is to be transmi tted. The reset value of all TSLR locati ons is 0 .

The spare bits (X2, X1, and X0) and the time slot 16 remote fr ame alarm (Y bit) to be transmitted must be written by

the host into TSLR0 . If the s ourc e of signaling is the receive system interface and the X or Y bits mus t be changed,

then switch the signaling sour ce back to host tempora rily, write the new val ues, and then switch the si gnaling

source back to the receive system interface.

If the source of signaling is the host, only the relevant bits need be written in each t ransmit signaling link register.

The format of the data written in each t ra nsm it s ignalin g link register depends on the signaling state mode selected

for each time slot as shown in Table 585.

TSLR Ad dress TSL R Bi t[6:0] ( DS1) TSLR Bit[6:0] (CEPT) TSLR Bit[6:0] (CMI)

0—000 X2 X1 Y X0 —