DGN−8
DDA−8D−8
_
+
RF
CF
λ
−V(Bias)
RL
Photodiode Circuit
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
HIGH-VOLTAGE, HIGH SLEW RATE, WIDEBAND
FET-INPUT OPERATIONAL AMPLIFIER
Check for Samples: THS4631
1FEATURES DESCRIPTION
The THS4631 is a high-speed, FET-input operational
2•High Bandwidth: amplifier designed for applications requiring wideband
–325 MHz in Unity Gain operation, high-input impedance, and high-power
–210 MHz Gain Bandwidth Product supply voltages. By providing a 210-MHz gain
bandwidth product, ±15-V supply operation, and
•High Slew Rate: 100-pA input bias current, the THS4631 is capable of
–900 V/µs (G = 2) simultaneous wideband transimpedance gain and
–1000 V/µs (G = 5) large output signal swing. The fast 1000 V/µs slew
rate allows for fast settling times and good harmonic
•Low Distortion of –76 dB, SFDR at 5 MHz distortion at high frequencies. Low current and
•Maximum Input Bias Current: 100 pA voltage noise allow amplification of extremely
•Input Voltage Noise: 7 nV/√Hz low-level input signals while still maintaining a large
signal-to-noise ratio.
•Maximum Input Offset Voltage: 500 µV at 25°C
•Low Offset Drift: 2.5 µV/°CThe characteristics of the THS4631 make it ideally
suited for use as a wideband photodiode amplifier.
•Input Impedance: 109|| 3.9 pF Photodiode output current is a prime candidate for
•Wide Supply Range: ±5 V to ±15 V transimpedance amplification as shown below. Other
•High Output Current: 95 mA potential applications include test and measurement
systems requiring high-input impedance, ADC and
APPLICATIONS DAC buffering, high-speed integration, and active
filtering.
•Wideband Photodiode Amplifier The THS4631 is offered in an 8-pin SOIC (D), and
•High-Speed Transimpedance Gain Stage the 8-pin SOIC (DDA) and MSOP (DGN) with
•Test and Measurement Systems PowerPAD™package.
•Current-DAC Output Buffer Related FET Input Amplifier Products
•Active Filtering SLEW VOLTAGE
•High-Speed Signal Integrator VSGBWP MINIMUM
DEVICE RATE NOISE
(V) (MHz) GAIN
(V/µS) (nV/√Hz)
•High-Impedance Buffer OPA656 ±5 230 290 7 1
OPA657 ±5 1600 700 4.8 7
OPA627 ±15 16 55 4.5 1
THS4601 ±15 180 100 5.4 1
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2004–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNITS
VSSupply voltage, VS–to VS+ 33 V
VIInput voltage ±VS
IO(2) Output current 150 mA
Continuous power dissipation See Dissipation Rating Table
TJMaximum junction temperature(2) 150°C
TAOperating free-air temperature, continues operation, long-term reliability(2) 125°C
Tstg Storage temperature range –65°C to 150°C
HBM 1000 V
ESD ratings: CDM 1500 V
MM 100 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS POWER RATING(1) (TJ=125°C)
PACKAGE θJC (°C/W) θJA (°C/W) TA≤25°C TA= 85°C
D (8)(2) 38.3 95 1.1 W 0.47 W
DDA (8) 9.2 45.8 2.3 W 0.98 W
DGN (8) 4.7 58.4 2.14 W 1.11 W
(1) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance.
(2) This data was taken using the JEDEC standard High-K test PCB.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN MAX UNITS
Dual Supply ±5±15
VSSupply Voltage V
Single Supply 10 30
TAOperating free-air temperature -40 85 °C
2Copyright ©2004–2011, Texas Instruments Incorporated
1
2
3
4
8
7
6
5
NC
VIN−
VIN+
VS−
NC
VS+
VOUT−
NC
NC = No Internal Connection
TOP VIEW D, DDA, AND DGN
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
PACKAGE / ORDERING INFORMATION
PACKAGE DEVICES(1) PACKAGE TYPE SOIC –8 TRANSPORT MEDIA, QUANTITY
THS4631D Rails, 75
SOIC –8
THS4631DR Tape and Reel, 2500
THS4631DDA Rails, 75
SOIC-PP –8(2)
THS4631DDAR Tape and Reel, 2500
THS4631DGN Rails, 100
MSOP-PP –8(2)
THS4631DGNR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) PowerPad™is electrically isolated from all other pins. Connection of the PowerPAD to the PCB ground plane is recommended because
the ground plane is typically the largest copper area on a PCB. However, connection of the PowerPAD to VS- up to VS+ is allowed if
desired.
PIN ASSIGNMENTS
THS4631
Copyright ©2004–2011, Texas Instruments Incorporated 3
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
VS=±15 V, RF= 499 Ω, RL= 1 kΩ, and G = 2 (unless otherwise noted)TYP OVER TEMPERATURE
PARAMETER TEST CONDITIONS 0°C to –40°C to MIN/
25°C 25°C UNITS
70°C 85°C MAX
AC PERFORMANCE
G = 1, RF= 0 Ω, VO= 200 mVPP 325
G = 2, RF= 499 Ω, VO= 200 mVPP 105
Small signal bandwidth, -3 dB MHz
G = 5, RF= 499 Ω, VO= 200 mVPP 55
G = 10, RF= 499 Ω, VO= 200 mVPP 25
Gain bandwidth product G >20 210 MHz
0.1 dB bandwidth flatness G = 2, RF= 499 Ω, CF= 8.2 pF 38 MHz
Large-signal bandwidth G = 2, RF= 499 Ω, VO= 2 VPP 105 MHz
G = 2, RF= 499 Ω, VO= 2-V step 550
Slew rate G = 2, RF= 499 Ω, VO= 10-V step 900 V/µs
G = 5, RF= 499 Ω, VO= 10-V step 1000
Rise and fall time 2-V step 5 ns
0.1%, G = -1, VO= 2-V step, CF= 4.7 pF 40
Settling time ns
0.01%, G = -1, VO= 2-V step, CF= 4.7 pF 190
HARMONIC DISTORTION
RL= 100 Ω-65
Second harmonic distortion dBc
G = 2, RL= 1 k Ω-76
VO= 2 VPP,RL= 100 Ω-62
f = 5 MHz
Third harmonic distortion dBc
RL= 1 kΩ-94
Input voltage noise f >10 kHz 7 nV/√Hz
Input current noise f >10 kHz 20 fA/√Hz
DC PERFORMANCE
Open-loop gain RL= 1 kΩ80 70 65 65 dB Min
Input offset voltage(1) 260 500 1600 2000 µV Max
VCM = 0 V
Average offset voltage drift(1) 25°C to 85°C±2.5 ±10 ±12 ±12 µV/°C Max
Input bias current 50 100 1500 2000 pA Max
VCM = 0 V
Input offset current 25 100 700 1000 pA Max
INPUT CHARACTERISTICS
-12.5 to
Common-mode input range -13 to 12 -12 to 11 -9 to 11 V Min
11.5
Common-mode rejection ratio VCM = 10 V 95 86 80 80 dB Min
Differential input resistance Ω|| pF
109|| 3.9
Common-mode input resistance Ω|| pF
109|| 3.9
OUTPUT CHARACTERISTICS
RL= 100 Ω ±11 ±10 ±9.5 ±9.5
Output voltage swing V Min
RL= 1 kΩ ±13.5 ±13 ±12.8 ±12.8
Static output current (sourcing) RL= 20 Ω98 90 85 80 mA Min
Static output current (sinking) RL= 20 Ω95 85 80 80 mA Min
Closed loop output impedance G = 1, f = 1 MHz 0.1 Ω
POWER SUPPLY
±15 ±16.5 ±16.5 ±16.5 V Max
Specified operating voltage ±5±4±4±4 V Min
Maximum quiescent current 11.5 13 14 14 mA Max
Minimum quiescent current 11.5 10 9 9 mA Min
Power supply rejection (PSRR +) VS+ = 15.5 V to 14.5 V, VS–= 15 V 95 85 80 80 dB Min
Power supply rejection (PSRR –) VS+ = 15 V, VS–= -15.5 V to -14..5 V 95 85 80 80 dB Min
(1) Input offset voltage is 100% tested at 25°C. It is specified by characterization and simulation over the listed temperature range.
4Copyright ©2004–2011, Texas Instruments Incorporated
_
+
THS4631
49.9 Ω
50 Ω Source
+15 V
953 Ω
499 Ω499 Ω
−15 V
49.9 Ω
Test Data
Mesurement Point
50 Ω Test
Equipment
CF
RF
RG
0
1
2
3
4
5
6
7
8
9
10
100 k 1 M 10 M 100 M 1 G
VO = 200 mVPP
G = 2, RF = 499 Ω,
RG = 499 Ω
105 MHz
f − Frequency − Hz
Signal Gain − dB
CF = 5.6 pF
CF = 0 pF
CF = 8.2 pF
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
100 k 1 M 10 M 100 M
f − Frequency − Hz
Signal Gain − dB
CF = 8.2 pF
38 MHz
−10
0
10
20
30
40
50
100 k 1 M 10 M 100 M 1 G
G = 100, RF = 11.3 kΩ, RG = 115 Ω
VO = 200 mVPP
G = 10, RF = 499 Ω,
RG = 54.9 Ω
G = 5, RF = 499 Ω,
RG = 124 Ω
G = 2, RF = 499 Ω,
RG = 499 Ω
G = 1, RF = 0 Ω
105 MHz
f − Frequency − Hz
Signal Gain − dB
−5
−4
−3
−2
−1
0
1
2
3
4
5
100 k 1 M 10 M 100 M 1 G
G = −1, RF = 499 Ω,
RG = 499 Ω
CF = 2.2 pF
CF = 0 pF
CF = 5.2 pF
VO = 200 mVPP
f − Frequency − Hz
Signal Gain − dB
102 MHz
−10
−8
−6
−4
−2
0
2
4
100 k 1 M 10 M 100 M 1 G
THS4631
+15 V
RL
RISO
−15 V
0 Ω
50 Ω
Source
G = 1,
RF = 0 Ω,
RL = 1 kΩ
RISO = 50 Ω,
CL = 10 pF
RISO = 30 Ω,
CL = 56 pF
f − Frequency − Hz
Signal Gain − dB
RISO = 20 Ω,
CL = 100 pF
CL
0
1
2
3
4
5
6
7
8
100 k 1 M 10 M 100 M 1 G
VO = 0.5 VPP
VO = 2 VPP
f − Frequency − Hz
Signal Gain − dB
VO = 5 VPP
105 MHz
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS (±15 V GRAPHS)
TA= 25°C, G = 2, RF= 499 Ω, RL= 1 kΩ, Unless otherwise noted.
SMALL SIGNAL FREQUENCY SMALL SIGNAL FREQUENCY
RESPONSE RESPONSE 0.1-dB FLATNESS
Figure 1. Figure 2. Figure 3.
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY LARGE SIGNAL FREQUENCY vs
RESPONSE RESPONSE CAPACiTIVE LOAD
Figure 4. Figure 5. Figure 6.
Copyright ©2004–2011, Texas Instruments Incorporated 5
−90
−80
−70
−60
−50
−40
−30
1 M 10 M 100 M
2nd Order Harmonic Distortion − dB
f − Frequency − Hz
Gain = 2
RF = 499 Ω,
CF = 8.2 pF
VO = 2 VPP
RL = 100 Ω
RL = 1 kΩ
-1 10
-100
-90
-80
-70
-60
-50
-40
-30
1M 10M 100M
f-Frequency-Hz
3rdOrderHarmonicDistortion-dB
Gain=2
RF=499 W
CF=8.2pF
VO=2VPP
RL=100 W
RL=1kW
−10
0
10
20
30
40
50
60
70
80
90
1 k 10 k 100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Open−Loop Gain − dB
−200
−175
−150
−125
−100
−75
−50
−25
0
25
50
Phase − 5
0
200
400
600
800
1000
1200
0 2 4 6 8 10 12
VO − Output Voltage − VPP
G = 5,
RF = 499 Ω,
RG = 124 Ω
SR − Slew Rate − V/ µs
72
73
74
75
76
77
78
79
80
81
82
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
TC − Case Temperature − °C
Open-Loop Gain − dB
9
9.5
10
10.5
11
11.5
12
0 2 4 6 8 10 12 14 16
TA = 85°C
TA = 25°C
− Quiescent Current − mA
IQ
VS − Supply Voltage − +V
TA = −40°C
nV/ HzInput Voltage Noise −
1
10
100
10 100 1 k 10 k 100 k
f − Frequency − Hz
0
100
200
300
400
500
600
700
800
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
IIB− Input Bias Current − pA
TA − Free-Air Temperature − °C
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA= 25°C, G = 2, RF= 499 Ω, RL= 1 kΩ, Unless otherwise noted.
SECOND ORDER THIRD ORDER
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
Figure 7. Figure 8. Figure 9.
SLEW RATE OPEN-LOOP GAIN OPEN-LOOP GAIN AND PHASE
vs vs vs
OUTPUT VOLTAGE TEMPERATURE FREQUENCY
Figure 10. Figure 11. Figure 12.
INPUT VOLTAGE QUIESCENT CURRENT INPUT BIAS CURRENT
vs vs vs
FREQUENCY SUPPLY VOLTAGE TEMPERATURE
Figure 13. Figure 14. Figure 15.
6Copyright ©2004–2011, Texas Instruments Incorporated
−300
−200
−100
0
100
200
300
25 35 45 55 65 75 85
Input Offset Voltage −
TA − Free-Air Temperature − °C
mV
D Package
DDA Package
DGN Package
Referred to 25°C
0
25
50
75
100
125
150
175
200
225
250
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
IIO − Input Offset Current − pA
TA − Free-Air Temperature − °C
13.2
13.25
13.3
13.35
13.4
13.45
13.5
13.55
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
− Output Voltage − |V|
VO
TC − Case Temperature − °C
VO+
VO−
− Output Voltage − mVVO
−125
−100
−75
−50
−25
0
25
50
75
100
125
0 10 20 30 40 50 60 70 80
t − Time− ns
Gain = 2,
CF = 8.2 pF,
VI = 100 mVPP,
RL = 1 kΩ
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
0 10 20 30 40 50 60 70 80
Gain = 2,
CF = 8.2 pF,
VI = 1 VPP,
RL = 1 kΩ
t − Time − ns
− Output Voltage − VVO
84
86
88
90
92
94
96
98
100
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Sink
Source
IO− Output Drive Current − |mA|
TC − Case Temperature − °C
-7
-5
-3
-1
1
3
5
7
0 20 40 60 80 100 120 140 180160
Gain=5,
R =499 ,
R =1k
F
L
W
W
10VPP
t-Time-ns
-OutputVoltage-V
VO
-12
-8
-4
0
4
8
12
10
6
2
-2
-6
-10
0 20 40 60 80 100 120 140 180160
t-Time-ns
-OutputVoltage-V
VO
20VPP
Gain=5,
R =499 ,W
R =1kW
F
L
Gain = 2,
CF = 8.2 pF,
VI = 2 VPP,
RL = 1 kΩ
− Output Voltage − VVO
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
0 25 50 75 100 125 150
t − Time− ns
Gain = 2,
CF = 8.2 pF,
VI = 2 VPP,
RL = 1 kΩ
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA= 25°C, G = 2, RF= 499 Ω, RL= 1 kΩ, Unless otherwise noted.
INPUT OFFSET CURRENT INPUT OFFSET VOLTAGE OUTPUT VOLTAGE
vs vs vs
TEMPERATURE TEMPERATURE TEMPERATURE
Figure 16. Figure 17. Figure 18.
STATIC OUTPUT DRIVE CURRENT
vs SMALL SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT
TEMPERATURE RESPONSE RESPONSE
Figure 19. Figure 20. Figure 21.
LARGE SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT LARGE SIGNAL TRANSIENT
RESPONSE RESPONSE RESPONSE
Figure 22. Figure 23. Figure 24.
Copyright ©2004–2011, Texas Instruments Incorporated 7
− Output Voltage − V
VO
t − Time − ns
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
3
0 5 10 15 20 25 30 35 40
Rising
Falling
G = −1,
CF = 4.7 pF
− Output Voltage − V
VO
t − Time − ns
−1.5
−1.25
−1
−0.75
−0.5
−0.25
0
0.25
0.5
0.75
1
1.25
1.5
0 5 10 15 20 25 30 35 40
Rising
Falling
G = −1,
CF = 4.7 pF
−20
−15
−10
−5
0
5
10
15
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−4
−3
−2
−1
0
1
2
3
4
Gain = 5,
RF = 499 Ω,
RG = 124 Ω
t − Time − ms
− Output Voltage − VVO
Input
Output
− Input Voltage − VVI
−20
−15
−10
−5
0
5
10
15
20
−0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
−4
−3
−2
−1
0
1
2
3
4
Gain = 5,
RF = 499 Ω,
RG = 124 Ω
t − Time − ms
− Output Voltage − VVO
Input
Output
− Input Voltage − VVI
0
10
20
30
40
50
60
70
80
90
100
−15 −10 −5 0 5 10 15
VICR − Input Common-Mode Range − V
CMRR − Common-Mode Rejection Ratio − dB
0
10
20
30
40
70
80
90
100
10 k 100 k 1 M 10 M 100 M
f − Frequency − Hz
Rejection Ratio − dB
50
60
CMRR
PSRR+
PSRR−
0.01
0.1
1
10
100
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
− Output Impedance −ZoΩ
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS (±15 V GRAPHS) (continued)
TA= 25°C, G = 2, RF= 499 Ω, RL= 1 kΩ, Unless otherwise noted.
SETTLING TIME SETTLING TIME OVERDRIVE RECOVERY
Figure 25. Figure 26. Figure 27.
COMMON-MODE REJECTION RATIO REJECTION RATIO
vs vs
OVERDRIVE RECOVERY INPUT COMMON-MODE RANGE FREQUENCY
Figure 28. Figure 29. Figure 30.
OUTPUT IMPEDANCE
vs
FREQUENCY
Figure 31.
8Copyright ©2004–2011, Texas Instruments Incorporated
_
+
RF
CF
λ
−V(Bias)
RL
Photodiode Circuit
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
APPLICATION INFORMATION
The large gain-bandwidth product of the THS4631
INTRODUCTION provides the capability for simultaneously achieving
both high-transimpedance gain, wide bandwidth, high
The THS4631 is a high-speed, FET-input operational slw rate, and low noise. In addition, the high-power
amplifier. The combination of: high gain bandwidth supply rails provide the potential for a very wide
product of 210 MHz, high slew rate of 1000 V/µs, and dynamic range at the output, allowing for the use of
trimmed dc precision makes the device an excellent input sources which possess wide dynamic range.
design option for a wide variety of applications, The combination of these characteristics makes the
including test and measurement, optical monitoring, THS4631 a design option for systems that require
transimpedance gain circuits, and high-impedance transimpedance amplification of wideband, low-level
buffers. The applications section of the data sheet input signals. A standard transimpedance circuit is
discusses these particular applications in addition to shown in Figure 32.
general information about the device and its features
TRANSIMPEDANCE FUNDAMENTALS
FET-input amplifiers are often used in
transimpedance applications because of their
extremely high input impedance. A transimpedance
block accepts a current as an input and converts this
current to a voltage at the output. The high-input
impedance associated with FET-input amplifiers
minimizes errors in this process caused by the input
bias currents, IIB, of the amplifier.
DESIGNING THE TRANSIMPEDANCE Figure 32. Wideband Photodiode
CIRCUIT Transimpedance Amplifier
Typically, design of a transimpedance circuit is driven
by the characteristics of the current source that As indicated, the current source typically sets the
provides the input to the gain block. A photodiode is requirements for gain, speed, and dynamic range of
the most common example of a capacitive current the amplifier. For a given amplifier and source
source that interfaces with a transimpedance gain combination, achievable performance is dictated by
block. Continuing with the photodiode example, the the following parameters: the amplifier
system designer traditionally chooses a photodiode gain-bandwidth product, the amplifier input
based on two opposing criteria: speed and sensitivity. capacitance, the source capacitance, the
Faster photodiodes cause a need for faster gain transimpedance gain, the amplifier slew rate, and the
stages, and more sensitive photodiodes require amplifier output swing. From this information, the
higher gains in order to develop appreciable signal optimal performance of a transimpedance circuit
levels at the output of the gain stage. using a given amplifier is determined. Optimal is
These parameters affect the design of the defined here as providing the required
transimpedance circuit in a few ways. First, the speed transimpedance gain with a maximized flat frequency
of the photodiode signal determines the required response.
bandwidth of the gain circuit. Second, the required For the circuit shown in Figure 32, all but one of the
gain, based on the sensitivity of the photodiode, limits design parameters is known; the feedback capacitor
the bandwidth of the circuit. Third, the larger (CF) must be determined. Proper selection of the
capacitance associated with a more sensitive signal feedback capacitor prevents an unstable design,
source also detracts from the achievable speed of the controls pulse response characteristics, provides
gain block. The dynamic range of the input signal maximized flat transimpedance bandwidth, and limits
also places requirements on the amplifier dynamic broadband integrated noise. The maximized flat
range. Knowledge of the source output current levels, frequency response results with CF calculated as
coupled with a desired voltage swing on the output, shown in Equation 1, where CF is the feedback
dictates the value of the feedback resistor, RF. The capacitor, RFis the feedback resistor, CS is the total
transfer function from input to output is VOUT = IINRF.source capacitance (including amplifier input
capacitance and parasitic capacitance at the inverting
node), and GBP is the gain-bandwidth product of the
amplifier in hertz.
Copyright ©2004–2011, Texas Instruments Incorporated 9
CF+
1
pRFGBP )ǒ1
pRFGBPǓ2
)4CS
pRFGBP
Ǹ2
F*3dB +GBP
2pRFǒCS)CFǓ
Ǹ
Gain AOL
20 dB/Decade
Rate-of-Closure
GBP
20 dB/
Decade
Noise Gain
−20 dB/
Decade
f
PoleZero
0
_
+
CI(DIFF)
RF
CF
CP
CD
I(DIODE)
CI(CM)
CS = CI(CM) + CI(DIFF) + CP + CD
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
(1)
Once the optimal feedback capacitor has been
selected, the transimpedance bandwidth can be
calculated with Equation 2.
(2)
Figure 34. Transimpedance Circuit Bode Plot
The performance of the THS4631 has been
measured for a variety of transimpedance gains with
a variety of source capacitances. The achievable
bandwidths of the various circuit configurations are
summarized numerically in Table 1. The frequency
responses are presented in Figure 35,Figure 36, and
Figure 37.
A. The total source capacitance is the sum of Note that the feedback capacitances do not
several distinct capacitances. correspond exactly with the values predicted by the
Figure 33. Transimpedance Analysis Circuit equation. They have been tuned to account for the
parasitic capacitance of the feedback resistor
(typically 0.2 pF for 0805 surface mount devices) as
Where: well as the additional capacitance associated with the
CI(CM) is the common-mode input capacitance. PC board. The equation should be used as a starting
CI(DIFF) is the differential input capacitance. point for the design, with final values for CF optimized
in the laboratory.
CDis the diode capacitance.
CPis the parasitic capacitance at the inverting
node. Table 1. Transimpedance Performance Summary
The feedback capacitor provides a pole in the noise for Various Configurations
gain of the circuit, counteracting the zero in the noise
gain caused by the source capacitance. The pole is SOURCE TRANS- FEEDBACK -3 dB
CAPACITANCE IMPEDANCE CAPACITANCE FREQUENCY
set such that the noise gain achieves a 20-dB per (PF) GAIN (Ω) (PF) (MHZ)
decade rate-of-closure with the open-loop gain 18 10 k 2 15.8
response of the amplifier, resulting in a stable circuit. 18 100 k 0.5 3
As indicated, the formula given provides the feedback 18 1 M 0 1.2
capacitance for maximized flat bandwidth. Reduction
in the value of the feedback capacitor can increase 47 10 k 2.2 8.4
the signal bandwidth, but this occurs at the expense 47 100 k 0.7 2.1
of peaking in the ac response. 47 1 M 0.2 0.52
100 10 k 3 5.5
100 100 k 1 1.4
100 1 M 0.2 0.37
10 Copyright ©2004–2011, Texas Instruments Incorporated
65
70
75
80
85
10 k 100 k 1 M 10 M 1 G
f − Frequency − Hz
Transimpedance Gain − dB
VS = ±15 V
RL = 1 k
RF = 10 k
CS = 100 PF
CF = 3 PF
CS = 18 PF
CF = 2 PF
CS = 47 PF
CF = 2.2 PF
50 W50 W
RS
VS
C1
C2
IO
Network Analizer IO
VS(s) +1
2RSǒ1)C1
C2Ǔ
(Above the Pole Frequency)
IO
VS(s) +
s
2RSǒ1)C1
C2Ǔ
s)1
2 RSǒC1)C2Ǔ
85
90
95
100
105
10 k 100 k 1 M 10 M 1 G
f − Frequency − Hz
Transimpedance Gain − dB
VS = ±15 V
RL = 1 k
RF = 100 k
CS = 47 PF
CF = 0.7 PF
CS = 100 PF
CF = 1 PF
CS = 18 PF
CF = 0.5 PF
1
2 RS(C1 )C2)
1
2 RSǒ1)C1
C2Ǔ
95
100
110
120
10 k 100 k 1 M 10 M
f − Frequency − Hz
Transimpedance Gain − dB
125
VS = ±15 V
RL = 1 k
RF = 1 M
115
105
CS = 18 PF
CF = 0 PF
CS = 47 PF
CF = 0.2 PF
CS = 100 PF
CF = 0.2 PF
ZO(s) +C1 )C2
C1 C2ȧ
ȱ
Ȳ
s)1
2RSǒC1)C2Ǔ
sǒs)1
2 RSC1Ǔȧ
ȳ
ȴ
ZO[1
sC2
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
Table 1. Transimpedance Performance Summary is difficult to measure the frequency response with
for Various Configurations (continued) traditional laboratory equipment because the circuit
requires a current as an input rather than a voltage.
10-kΩTRANSIMPEDANCE RESPONSES Also, the capacitance of the current source has a
direct effect on the frequency response. A simple
interface circuit can be used to emulate a capacitive
current source with a network analyzer. With this
circuit, trans- impedance bandwidth measurements
are simplified, making amplifier evaluation easier and
faster.
Figure 35. A. The interface network creates a capacitive,
100-kΩTRANSIMPEDANCE RESPONSES constant current source from a network
analyzer and properly terminates the
network analyzer at high frequencies.
Figure 38. Emulating a Capacitive Current Source
With a Network Analyzer
The transconductance transfer function of the
interface circuit is:
(3)
The transfer function contains a zero at dc and a pole
Figure 36.
1-MΩTRANSIMPEDANCE RESPONSES at: . The transconductance is constant
at: , above the pole frequency,
providing a controllable ac-current source. This circuit
also properly terminates the network analyzer with 50
Ωat high frequencies. The second requirement for
this current source is to provide the desired output
impedance, emulating the output impedance of a
photodiode or other current source. The output
impedance of this circuit is given by:
Figure 37. (4)
Assuming C1 >> C2, the equation reduces to:
MEASURING TRANSIMPEDANCE
BANDWIDTH , giving the appearance of a capacitive
While there is no substitute for measuring the source at a higher frequency.
performance of a particular circuit under the exact
conditions that are used in the application, the Capacitor values should be chosen to satisfy two
complete system environment often makes requirements. First, C2 represents the anticipated
measurements harder. For transimpedance circuits, it capacitance of the true source. Second C1 is chosen
Copyright ©2004–2011, Texas Instruments Incorporated 11
REQ +RF1 ǒ1)RF2
RF3Ǔ
_
+
RF2
CF
λ
−V(Bias)
RL
RF1
RF3
1
CFEQ +1
CF1 ǒ1)CF3
CF2Ǔ
_
+
RF2
CF
λ
−V(Bias)
RL
RF1
_
+
RF
CF2
λ
−V(Bias)
RL
CF1
CF3
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
such that the corner frequency of the
transconductance network is much less than the
transimpedance bandwidth of the circuit. Choosing (5)
this corner frequency properly leads to more accurate
measurements of the transimpedance bandwidth. If
the interface circuit corner frequency is too close to
the bandwidth of the circuit, determining the power
level in the flatband is difficult. A decade or more of
flat bandwidth provides a good basis for determining
the proper transimpedance bandwidth.
ALTERNATIVE TRANSIMPEDANCE
CONFIGURATIONS
Other transimpedance configurations are possible.
Three possibilities are shown below. A. A resistive T-network enables high
The first configuration is a slight modification of the transimpedance gain with reasonable
basic transimpedance circuit. By splitting the resistor values.
feedback resistor, the feedback capacitor value Figure 40. Alternative Transimpedance
becomes more manageable and easier to control. Configuration 2
This type of compensation scheme is useful when the
feedback capacitor required in the basic configuration The third configuration uses a capacitive T-network to
becomes so small that the parasitic effects of the achieve fine control of the compensation capacitance.
board and components begin to dominate the total The capacitor CF3 can be used to tune the total
feedback capacitance. By reducing the resistance effective feedback capacitance to a fine degree. This
across the capacitor, the capacitor value can be circuit behaves the same as the basic
increased. This mitigates the dominance of the transimpedance configuration, with the effective CF
parasitic effects. given by Equation 6.
(6)
A. Splitting the feedback resistor enables use
of a larger, more manageable feedback
capacitor.
Figure 39. Alternative Transimpedance
Configuration 1
The second configuration uses a resistive T-network A. A capacitive T-network enables fine control
to achieve high transimpedance gains using relatively of the effective feedback capacitance using
small resistor values. This topology can be useful relatively large capacitor values.
when the desired transimpedance gain exceeds the Figure 41. Alternative Transimpedance
value of available resistors. The transimpedance gain Configuration 3
is given by Equation 5.
12 Copyright ©2004–2011, Texas Instruments Incorporated
_
+
Rf
4kT = 1.6E−20J
at 290K
IBN EO
ERF
RS
ERS
IBI
Rg
ENI
4kTRS
4kT
Rg4kTRf
EO+ǒE2
NI )ǒIBNRSǓ2)4kTRSǓNG2)ǒIBIRfǓ2)4kTRfNG
Ǹ
EN+E2
NI )ǒIBNRSǓ2)4kTRS)ǒIBIRf
NGǓ2
)4kTRf
NG
Ǹ
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
SUMMARY OF KEY DECISIONS IN feedback resistors this large or anticipate using an
TRANSIMPEDANCE DESIGN external compensation scheme to stabilize the circuit.
Using a simple capacitor in parallel with the feedback
The following is a simplified process for basic resistor makes the amplifier more stable as shown in
transimpedance circuit design. This process gives a the Typical Characteristics graphs.
start to the design process, though it does ignore
some aspects that may be critical to the circuit. NOISE ANALYSIS
STEP 1: Determine the capacitance of the source. High slew rate, unity gain stable, voltage-feedback
STEP 2: Calculate the total source capacitance, operational amplifiers usually achieve their slew rate
including the amplifier input capacitance, CI(CM) at the expense of a higher input noise voltage. The
and CI(DIFF). 7 nV/√Hz input voltage noise for the THS4631 is,
however, much lower than comparable amplifiers
STEP 3: Determine the magnitude of the possible while achieving high slew rates. The input-referred
current output from the source, including the voltage noise, and the input-referred current noise
minimum signal current anticipated and term, combine to give low output noise under a wide
maximum signal current anticipated. variety of operating conditions. Figure 42 shows the
amplifier noise analysis model with all the noise terms
STEP 4: Choose a feedback resistor value such that included. In this model, all noise terms are taken to
the input current levels create the desired be noise voltage or current density terms in either
output signal voltages, and nV/√Hz or fA/√Hz.
ensure that the output voltages can
accommodate the dynamic range of the input
signal.
STEP 5: Calculate the optimum feedback
capacitance using Equation 1.
STEP 6: Calculate the bandwidth given the
resulting component values.
STEP 7: Evaluate the circuit to determine if all design
goals are satisfied.
SELECTION OF FEEDBACK RESISTORS
Feedback resistor selection can have a significant Figure 42. Noise Analysis Model
effect on the performance of the THS4631 in a given
application, especially in configurations with low
closed-loop gain. If the amplifier is configured for The total output noise voltage can be computed as
unity gain, the output should be directly connected to the square root of all square output noise voltage
the inverting input. Any resistance between these two contributors. Equation 7 shows the general form for
points interacts with the input capacitance of the the output noise voltage using the terms shown in
amplifier and causes an additional pole in the Figure 42.
frequency response. For nonunity gain configurations,
low resistances are desirable for flat frequency
response. However, care must be taken not to load
the amplifier too heavily with the feedback network if (7)
large output signals are expected. In most cases, a Dividing this expression by the noise gain [NG = (1+
trade off is made between the frequency response Rf/Rg)] gives the equivalent input-referred spot noise
characteristics and the loading of the amplifier. For a voltage at the noninverting input, as shown in
gain of 2, a 499-Ωfeedback resistor is a suitable Equation 8:
operating point from both perspectives. If resistor
values are chosen too large, the THS4631 is subject
to oscillation problems. For example, an inverting
amplifier configuration with a 5-kΩ gain resistor and a
5-kΩ feedback resistor develops an oscillation due to (8)
the interaction of the large resistors with the input Using high resistor values can dominate the total
capacitance. In low gain configurations, avoid equivalent input-referred noise. Using a 3-kΩ
source-resistance (RS) value adds a voltage noise
term of approximately 7 nV/√Hz. This is equivalent to
the amplifier voltage noise term. Using higher resistor
Copyright ©2004–2011, Texas Instruments Incorporated 13
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
values dominate the noise of the system. Although performance of the THS4631. Resistors should be
the THS4631 JFET input stage is ideal for a very low reactance type. Surface-mount
high-source impedance because of the low-bias resistors work best and allow a tighter overall
currents, the system noise and bandwidth is limited layout. Again, keep their leads and PC board
by a high-source (RS) impedance. trace length as short as possible. Never use
wirebound type resistors in a high frequency
application. Since the output pin and inverting
SLEW RATE PERFORMANCE WITH VARYING input pins are the most sensitive to parasitic
INPUT STEP AMPLITUDE AND RISE/FALL capacitance, always position the feedback and
TIME series output resistors, if any, as close as possible
Some FET input amplifiers exhibit the peculiar to the inverting input pins and output pins. Other
behavior of having a larger slew rate when presented network components, such as input termination
with smaller input voltage steps and slower edge resistors, should be placed close to the
rates due to a change in bias conditions in the input gain-setting resistors. Even with a low parasitic
stage of the amplifier under these circumstances. capacitance shunting the external resistors,
This phenomena is most commonly seen when FET excessively high resistor values can create
input amplifiers are used as voltage followers. As this significant time constants that can degrade
behavior is typically undesirable, the THS4631 has performance. Good axial metal-film or
been designed to avoid these issues. Larger surface-mount resistors have approximately 0.2
amplitudes lead to higher slew rates, as would be pF in shunt with the resistor. For resistor values >
anticipated, and fast edges do not degrade the slew 2.0 kΩ, this parasitic capacitance can add a pole
rate of the device. The high slew rate of the THS4631 and/or a zero that can effect circuit operation.
allows improved SFDR and THD performance, Keep resistor values as low as possible,
especially noticeable above 5 MHz. consistent with load driving considerations.
•Connections to other wideband devices on the
PRINTED-CIRCUIT BOARD LAYOUT board may be made with short direct traces or
TECHNIQUES FOR OPTIMAL through onboard transmission lines. For short
PERFORMANCE connections, consider the trace and the input to
the next device as a lumped capacitive load.
Achieving optimum performance with high frequency Relatively wide traces (50 mils to 100 mils) should
amplifier-like devices in the THS4631 requires careful be used, preferably with ground and power planes
attention to board layout parasitic and external opened up around them. Estimate the total
component types. capacitive load and determine if isolation resistors
Recommendations that optimize performance include: on the outputs are necessary. Low parasitic
•Minimize parasitic capacitance to any ac ground capacitive loads (<4 pF) may not need an RS
for all of the signal I/O pins. Parasitic capacitance since the THS4631 is nominally compensated to
on the output and input pins can cause instability. operate with a 2-pF parasitic load. Higher parasitic
To reduce unwanted capacitance, a window capacitive loads without an RS are allowed as the
around the signal I/O pins should be opened in all signal gain increases (increasing the unloaded
of the ground and power planes around those phase margin). If a long trace is required, and the
pins. Otherwise, ground and power planes should 6-dB signal loss intrinsic to a doubly-terminated
be unbroken elsewhere on the board. transmission line is acceptable, implement a
matched impedance transmission line using
•Minimize the distance (<0.25”) from the power microstrip or stripline techniques (consult an ECL
supply pins to high frequency 0.1-µF and 100-pF design handbook for microstrip and stripline layout
de-coupling capacitors. At the device pins, the techniques). A
ground and power plane layout should not be in 50-Ωenvironment is not necessary onboard, and
close proximity to the signal I/O pins. Avoid in fact, a higher impedance environment improves
narrow power and ground traces to minimize distortion as shown in the distortion versus load
inductance between the pins and the de-coupling plots. With a characteristic board trace impedance
capacitors. The power supply connections should based on board material and trace dimensions, a
always be de-coupled with these capacitors. matching series resistor into the trace from the
Larger (6.8 µF or more) tantalum de-coupling output of the THS4631 is used as well as a
capacitors, effective at lower frequency, should terminating shunt resistor at the input of the
also be used on the main supply pins. These may destination device. Remember also that the
be placed somewhat farther from the device and terminating impedance is the parallel combination
may be shared among several devices in the of the shunt resistor and the input impedance of
same area of the PC board. the destination device: this total effective
•Careful selection and placement of external impedance should be set to match the trace
components preserve the high frequency
14 Copyright ©2004–2011, Texas Instruments Incorporated
0.060
0.040
0.075 0.025
0.205
0.010
vias
Pin 1
Top View
0.017
0.035
0.094
0.030
0.013
0.140
0.060
0.060
0.010
vias
Top View
0.035 0.080
0.050 0.176
0.030
0.026
0.010
0.035
0.100
0.300
Pin 1
All Units in Inches
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case. This does not preserve signal integrity
or a doubly-terminated line. If the input impedance
of the destination device is low, there is some
signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
•Socketing a high-speed part like the THS4631 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket
creates a troublesome parasitic network which
makes it almost impossible to achieve a smooth,
stable frequency response. Best results are
obtained by soldering the THS4631 part directly
onto the board. Figure 44. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD DESIGN CONSIDERATIONS
The THS4631 is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which
the die is mounted [see Figure 43 (a) and Figure 43
(b)]. This arrangement results in the lead frame being
exposed as a thermal pad on the underside of the
package [see Figure 43 (c)]. Because this thermal
pad has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat Figure 45. DDA PowerPAD PCB Etch and Via
dissipating device. Pattern
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the mechanical methods of PowerPAD PCB LAYOUT CONSIDERATIONS
heatsinking. 1. PCB with a top side etch pattern is shown in
Figure 44 and Figure 45. There should be etch
for the leads and for the thermal pad.
2. Place the recommended number of holes in the
area of the thermal pad. These holes should be
10 mils in diameter. Keep them small so that
solder wicking through the holes is not a problem
during reflow.
3. Additional vias may be placed anywhere along
Figure 43. Views of Thermally Enhanced Package the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
Although there are many ways to properly heatsink the THS4631 IC. These additional vias may be
the PowerPAD package, the following steps illustrate larger than the 10-mil diameter vias directly under
the recommended approach. the thermal pad. They can be larger because
they are not in the thermal pad area to be
Copyright ©2004–2011, Texas Instruments Incorporated 15
PD max +Tmax *TA
qJA
4
3.5
3
2.5
2
1.5
1
0.5
0
−40 −20 0 20 40 60 80 100
− Maximum Power Dissipation − W
PD
TA − Free-Air Temperature − °C
θJA = 58.4°C/W
θJA = 98°C/W
θJA = 158°C/W
TJ = 125°C
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane. (9)
Although the PowerPAD is electrically isolated where:
from all pins and the active circuitry, connection
to the ground plane is recommended. This is due PDmax is the maximum power dissipation in the
to the fact that ground planes on most PCBs are amplifier (W).
typically the targets copper area. Offering the Tmax is the absolute maximum junction
best thermal path heat to flow out of the device. temperature (°C).
5. When connecting these holes to the ground TAis the ambient temperature (°C).
plane, do not use the typical web or spoke via θJA =θJC +θCA
connection methodology. Web connections have θJC is the thermal coefficient from the silicon
a high thermal resistance connection that is junctions to the case (°C/W).
useful for slowing the heat transfer during θCA is the thermal coefficient from the case to
soldering operations. This makes the soldering of ambient air (°C/W).
vias that have plane connections easier. In this
application, however, low thermal resistance is NOTE:
desired for the most efficient heat transfer. For systems where heat dissipation is more
Therefore, the holes under the THS4631 critical, the THS4631 is offered in an 8-pin MSOP
PowerPAD package should make their with PowerPAD package and an 8-pin SOIC with
connection to the internal ground plane with a PowerPAD package with better thermal
complete connection around the entire performance. The thermal coefficient for the
circumference of the plated-through hole. PowerPAD packages are substantially improved
6. The top-side solder mask should leave the over the traditional SOIC. Maximum power
terminals of the package and the thermal pad dissipation levels are depicted in Figure 46 for the
area with its via holes exposed. The bottom-side available packages. The data for the PowerPAD
solder mask should cover the via holes of the packages assume a board layout that follows the
thermal pad area. This prevents solder from PowerPAD layout guidelines referenced above
being pulled away from the thermal pad area and detailed in the PowerPAD application note
during the reflow process. number SLMA002.Figure 46 also illustrates the
7. Apply solder paste to the exposed thermal pad effect of not soldering the PowerPAD to a PCB.
area and all of the IC terminals. The thermal impedance increases substantially
which may cause serious heat and performance
8. With these preparatory steps in place, the IC is issues. Be sure to always solder the PowerPAD
simply placed in position and run through the to the PCB for optimum performance.
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
To maintain maximum output capabilities, the
THS4631 does not incorporate automatic thermal
shutoff protection. The designer must take care to
ensure that the design does not violate the absolute
maximum junction temperature of the device. Failure
may result if the absolute maximum junction
temperature of 150°C is exceeded. For best
performance, design for a maximum junction
temperature of 125°C. Between 125°C and 150°C,
damage does not occur, but the performance of the Figure 46. Maximum Power Dissipation
amplifier begins to degrade. The thermal vs. Ambient Temperature
characteristics of the device are dictated by the
package and the PC board. Maximum power
dissipation for a given package can be calculated
using Equation 9.
16 Copyright ©2004–2011, Texas Instruments Incorporated
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
Results are with no air flow and PCB size = 3" x 3 "
θJA = 58.4°C/W for the 8-pin MSOP with
PowerPAD (DGN).
θJA = 98°C/W for the 8-pin SOIC high-K test PCB
(D).
θJA = 158°C/W for the 8-pin MSOP with
PowerPAD, without solder.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem
DESIGN TOOLS EVALUATION FIXTURE,
SPICE MODELS, AND APPLICATIONS
SUPPORT
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal an evaluation board has
been developed for the THS4631 operational Figure 48. EVM Layers 2 and 3, Ground
amplifier. The board is easy to use, allowing for
straightforward evaluation of the device. The
evaluation board can be ordered through the Texas
Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. The
board layers are provided in Figure 47,Figure 48,
and Figure 49. The bill of materials for the evaluation
board is provided in Table 2.
Figure 49. EVM Bottom Layer
Figure 47. EVM Top Layer
Copyright ©2004–2011, Texas Instruments Incorporated 17
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
BILL OF MATERIALS
Table 2. THS4631DDA EVM
SMD REFERENCE PCB MANUFACTURER'S
ITEM DESCRIPTION SIZE DESIGNATOR QUANTITY PART NUMBER(1)
1 CAP, 2.2 µF, CERAMIC, X5R, 25 V 1206 C3, C6 2 (AVX) 12063D225KAT2A
4 CAP, 0.1µF, CERAMIC, X7R, 50 V 0805 C1, C2 2 (AVX) 08055C104KAT2A
OPEN 0805 R4, Z4, Z6 3
6 RESISTOR, 0 OHM, 1/8 W 0805 Z2 1 (KOA) RK73Z2ATTD
7 RESISTOR, 499 OHM, 1/8 W, 1% 0805 R3, Z5 2 (KOA) RK73H2ATTD4990F
8 OPEN 1206 R8, Z9 2
9 RESISTOR, 0 OHM, 1/4 W 1206 R1 1 (KOA) RK73Z2BLTD
10 RESISTOR, 49.9 OHM, 1/4 W, 1% 1206 R2 1 (KOA) RK73H2BLTD49R9F
11 RESISTOR, 953 OHM, 1/4 W, 1% 1206 Z3 1 (KOA) RK73H2BLTD9530F
13 CONNECTOR, SMA PCB JACK J1, J2, J3 3 (JOHNSON) 142-0701-801
JACK, BANANA RECEPTANCE, 0.25"
14 J4, J5, J6 3 (SPC) 813
DIA. HOLE
15 TEST POINT, BLACK TP1, TP2 2 (KEYSTONE) 5001
TEST POINT, RED TP3 1 (KEYSTONE) 5000
16 STANDOFF, 4-40 HEX, 0.625" LENGTH 4 (KEYSTONE) 1808
17 SCREW, PHILLIPS, 4-40, .250" 4 SHR-0440-016-SN
18 IC, THS4631 U1 1 (TI) THS4631DDA
19 BOARD, PRINTED CIRCUIT 1 (TI) EDGE # 6467873 Rev.A
(1) The manufacturer's part numbers are used for test purposes only.
EVM
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic
capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4631 is
available through either the Texas Instruments web site (www.ti.com). These models help in predicting
small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types
in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the
model file itself.
18 Copyright ©2004–2011, Texas Instruments Incorporated
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
Figure 50. THS4631 EVM Schematic
Copyright ©2004–2011, Texas Instruments Incorporated 19
THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
www.ti.com
ADDITIONAL REFERENCE MATERIAL
•PowerPAD Made Easy, application brief (SLMA004)
•PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
•Noise Analysis of FET Transimpedance Amplifiers, application bulletin, Texas Instruments Literature Number
SBOA060.
•Tame Photodiodes With Op Amp Bootstrap, application bulletin, Texas Instruments Literature Number
SBBA002.
•Designing Photodiode Amplifier Circuits With OPA128, application bulletin, Texas Instruments Literature
Number SBOA061.
•Photodiode Monitoring With Op Amps, application bulletin, Texas Instruments Literature Number SBOA035.
•Comparison of Noise Performance Between a FET Transimpedance Amplifier and a Switched Integrator,
Application Bulletin, Texas Instruments Literature Number SBOA034.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
Input Range, VS+ to VS–10 V to 30 V
Input Range, VI10 V to 30 V NOT TO EXCEED VS+ or VS–
Output Range, VO10 V to 30 V NOT TO EXCEED VS+ or VS–
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Consult the product data sheet or EVM user's guide (if user's guide is available)
prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact
a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
20 Copyright ©2004–2011, Texas Instruments Incorporated
THS4631
www.ti.com
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011
REVISION HISTORY
Changes from Original (December 2004) to Revision A Page
•Changed the Related FET Input Amplifier Products table .................................................................................................... 1
•Changed the Differential input resistance value From: 109|| 6.5 To: 109|| 3.9 ................................................................... 4
•Changed the Common-mode input resistance value From: 109|| 6.5 To: 109|| 3.9 ............................................................ 4
•Changed Figure 8 - From: RL= 499ΩTo RF= 499Ω........................................................................................................... 6
•Changed Figure 9 - From: RL= 499ΩTo RF= 499Ω........................................................................................................... 6
•Added Figure 23 ................................................................................................................................................................... 7
•Added Figure 24 ................................................................................................................................................................... 7
•Added Figure 50 ................................................................................................................................................................. 19
Changes from Revision A (March 2005) to Revision B Page
•Changed the Tstg value in the Absolute Maximum Ratings table From: 65°C to 150°C To: –65°C to 150°C ...................... 2
Copyright ©2004–2011, Texas Instruments Incorporated 21
PACKAGE OPTION ADDENDUM
www.ti.com 2-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4631D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4631DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
THS4631DE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4631DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4631DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4631DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4631DRG4 ACTIVE SOIC D 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 2-Aug-2011
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4631DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4631DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4631DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4631DR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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