5
READ CYCLE
A combination of PE greater than VIH(min), and CE less than
VIL(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
An address access read is initiated by a change in address inputs
while the chip is enabled with OE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
tAVQV is satisfied. Outputs remain active througho ut the ent ire
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
The chip enable-controlled access is initiated by CE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
tELQV is satisfied, the eight-bit word addressed by A(14:0)
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is tGLQV unless tAVQV or tELQV have
not been satisfied.
AC CHARACTERISTICS READ C YCLE (Post-Radiation)*
(VDD = 5.0V
±
10%; -55°C < TC < +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads (Si).
1. Functional test.
2. Three-state is defined as a 200mV change from steady-state output voltage.
SYMBOL PARAMETER 28F256-45
MIN MAX 28F256-40
MIN MAX UNIT
tAVAV1Read cycle time 45 40 ns
tAVQV Read access time 45 40 ns
tAXQX2Output hold time 0 0 ns
tGLQX2OE-controlled output enable time 0 0 ns
tGLQV OE-controlled access time 15 15 ns
tGHQZ OE-controlled output three-state time 15 15 ns
tELQX2 CE-controlled ou tput enable time 0 0 ns
tELQV CE-controlled access time 45 40 ns
tEHQZ CE-controlled output three-state time 15 15 ns