1
®
FN8166.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9251
Single Supply/Low Power/256-Tap/SPI Bus
Quad Digitally-Controlled (XDCP™)
Potentiometer
The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are imple-mented
with a combination of resistor elements and CMOS switches.
The position of the wipers are controlled by the user through
the SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corres ponding WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four potentiometers in one package
• 256 resistor tap s–0.4% resolution
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
• Wiper resistance: 100Ω typical @ VCC = 5V
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current <5µA max
•V
CC: 2.7V to 5.5V Operation
•50kΩ, 100kΩ versions of total resistance
• 100 year da ta retenti o n
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low powe r CMOS
• Pb-free plus anneal available (RoHS compliant)
Functional Diagram
POWER UP,
INTERFACE
CONTROL
AND
VCC
VSS
SPI
RH0
RL0
DCP0
RW0
A1
SO
SI
CS
HOLD
SCK
WP
WCR0
DR00
DR01
DR02
DR03
RH1
RL1
DCP1
RW1
WCR1
DR10
DR11
DR12
DR13
RH2
RL2
DCP2
RW2
WCR2
DR20
DR21
DR22
DR23
RH3
RL3
DCP3
RW3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
STATUS
Data Sheet April 13, 2007
2FN8166.5
April 13, 2007
Ordering Information
PART NUMBER PART
MARKING VCC LIMITS
(V)
POTENTIOMENTER
ORGANIZATION
(kΩ)TEMP RANGE
(°C) PACKAGE PKG.
DWG. #
X9251US24 X9251US 5 ±10% 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251US24Z (Note) X9251US Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251UV24 X9251UV 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24Z (Note) X9251UV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TS24 X9251TS 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251TS24Z (Note) X9251TS Z 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251TS24I X9251TS I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9251TS24IZ (Note) X9251TS ZI -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251TV24I X9251TV I -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9251TV24IZ (Note) X9251TV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251US24I-2.7 X9251US G 2.7 to 5.5 50 -40 to +85 24 Ld SOIC (300 mil) M24.3
X9251US24IZ-2.7 (Note) X9251US ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251UV24-2.7 X9251UV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24Z-2.7 (Note) X9251UV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251UV24I-2.7 X9251UV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9251UV24IZ-2.7 (Note) X9251UV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TS24-2.7 X9251TS F 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251TS24Z-2.7 (Note) X9251TS ZF 0 to +70 24 Ld SOIC (300 mil) (Pb-free) M24.3
X9251TV24-2.7 X9251TV F 0 to +70 24 Ld TSSOP (4.4mm) MDP0044
X9251TV24Z-2.7 (Note) X9251TV ZF 0 to +70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9251TV24I-2.7 X9251TV G -40 to +85 24 Ld TSSOP (4.4mm) MDP0044
X9251TV24IZ-2.7 (Note) X9251TV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9251
3FN8166.5
April 13, 2007
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
Pinout X9251
(24 LD SOIC/TSSOP)
TOP VIEW
Pin Assignments
PIN
(SOIC) SYMBOL FUNCTION
1 SO Serial Data Output for SPI bus
2 A0 Device Address for SPI bus. (See Note 1)
3R
W3 Wiper Terminal of DCP3
4R
H3 High Terminal of DCP3
5R
L3 Low Terminal of DCP3
7V
CC System Supply Voltage
8R
L0 Low Terminal of DCP0
9R
H0 High Terminal of DCP0
10 RW0 Wiper Terminal of DCP0
11 CS SPI bus. Chip Select active low input
12 WP Hardware Write Protect - active low
13 SI Serial Data Input for SPI bus
14 A1 Device Address for SPI bus. (See Note 1)
15 RL1 Low Terminal of DCP1
16 RH1 High Terminal of DCP1
17 RW1 Wiper Terminal of DCP1
18 VSS System Ground
20 RW2 Wiper Terminal of DCP2
21 RH2 High Terminal of DCP2
22 RL2 Low Terminal of DCP2
23 SCK Serial Clock for SPI bus
24 HOLD Device select. Pauses the SPI serial bus.
6, 19 NC No Connect
NOTE:
1. A0 and A1 device address pins must be tied to a logic level.
SO
A0
RW3
NC
VCC
RL0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
X9251
RH3
14
13
11
12
RL3
RH0
RW0
CS A1
SI
WP
X9251
4FN8166.5
April 13, 2007
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the device registers are input on
this pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is brought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
DEVICE ADDRESS (A1 AND A0)
The address inputs are used to set the two least significant
bits of the slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9251. Device pins A1 and
A0 must be tied to a logic level which specifies the internal
address of the device, see Figures 2, 3, 4, 5 and 6.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the SO pin
is at high impedance, and (unless an internal write cycl e is
underway) the device is in the standby state. CS LOW
enables the X9251, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of RH and RL such that
RH0 and RL0 are the terminals of DCP0 and so on.
RW
The wiper pin are equivalent to th e wiper terminal of a
mechanical potentiometer . Since there are 4 potentiometers,
there are 4 sets of RW such that RW0 is the terminals of
DCP0 and so on.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
Principles of Operation
The X9251 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and a serial
interface providing direct commun ication between a host
and the potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin is an
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
X9251
5FN8166.5
April 13, 2007
One of Four Potentiometers
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provid ed that VCC is always more
positive than or equal to VH, VL, and VW (i.e., VCC ≥ VH, VL,
VW). The VCC ramp rate specification is always in effect.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (se rial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)
The wiper counter register is a volatile register; tha t is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).
Status Register (SR)
This 1-bit S t atus Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP = 0, indicates that no high-voltage write cycle is
in progress.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8 8
COUNTER
IF WCR = 00[H] then RW is closet to RL
IF WCR = FF[H] then RW is closet to RH
WIPER
(WCR#)
#: 0, 1, 2, or 3
DR#2
DR#1
DR#3
- - -
DECODE
DCP
CORE RW
RH
RL
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
X9251
6FN8166.5
April 13, 2007
Serial Interface
The X9251 supports the SPI interface hardw are conventions.
The device is accessed via the SI input with dat a clocke d in,
on the rising SCK. CS mu st be LOW and the HOLD and WP
pins must be HIGH during the entire opera tion.
The SO and SI pins can be connected together, since they
have three state output s. This can help to reduce system pin
count.
Identification Byte
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the Identification Byte are a
Device T ype Identifier , ID[3:0]. For the X9251, this is fixed as
0101 (refer to Table 3).
The least significant four bit s of the Ide ntification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0 , A2 is 0,
A1 is the logic value at the input pin A1, and A0 is the logic
value at the input pin A0. Only the device which Slave
Address matches the incoming bits sent by the master
executes the instruction. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
Instruction Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each asso ciated
XDCP. The least two significant bits point to one of four Wipe r
Counter Registers or DCPs.The format is shown below in
Table 4.
TABLE 3. IDENTIFICATION BYTE FORMAT
TABLE 4. INSTRUCTION BYTE FORMAT
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
(MSB) (LSB)
TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE)
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
(MSB) (LSB)
ID3 ID2 ID1 ID0 A3 A2 A1 A0
010100Pin A1
Logic Value Pin A0
Logic Value
(MSB) (LSB)
Device Type
Identifier Slave Address
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
Instruction Register DCP Selection
Opcode Selection (WCR Selection)
Data Register Selection
REGISTER RB RA
DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1
#: 0, 1, 2, or 3
X9251
7FN8166.5
April 13, 2007
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
•Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,
•Write Wiper Counter Register – change current wiper
position of the selected potentiometer,
•Read Data Register – read the contents of the selected
Data Register,
•Write Data Register – write a new value to the selected
Data Register,
•Read Status – this command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register . The
Read Status Register instruction is the only unique format
(See Figure 5).
Four instructions require a two-by te sequence to complete.
These instructions transfer data between the host and the
X9251; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register .
These instructions are:
•XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
•XFR Wip er Co un ter Register to Da ta Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
•Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
•Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
TABLE 5. INSTRUCTION SET
INSTRUCTION
INSTRUCTION SET
OPERATIONI3 I2 I1 I0 RB RA P1 P0
Read Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to
by P1 - P0 and RB - RA
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to
Wiper Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 T ransfer the contents of the Data Register pointed to
by P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 T ransfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed
to by RB - RA
Global XFR Data Registers to
Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed
to by RB - RA of all four pots to their respective
Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Enable Increment/de crement of the Control Latch
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
X9251
8FN8166.5
April 13, 2007
Increment/Decrement Command
The final command is Increment/Decrement (See Figures 6
and 7). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9251 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (tHIGH) while SI is HIGH, the
selected wiper moves one wiper position towards the RH
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position towards
the RL terminal. A detailed illustration of the se quence and
timing for this operation are shown. See Instruction format
for more details.
ID3 ID2 ID1 ID0 0 A1 A0 I3 I2 I1 RB RA P0
SCK
SI
CS
0101
DEVICE ID INTERNAL INSTRUCTION
OPCODE
ADDRESS
REGISTER
0
I0 P1
ADDRESS
DCP/WCR
ADDRESS
0
0
FIGURE 2. TWO-BYTE INSTRUCTION SEQUEN CE
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
DEVICE ID INTERNAL INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
DCP/WCR
ADDRESS
00
P1
DATA FOR WCR[7:0] OR DR[7:0]
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
DEVICE ID INTERNAL INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
DCP/WCR
ADDRESS
00
P1
WCR[7:0]
S0
XXXXX
XXX
DON’T CARE
OR
DATA REGISTER BIT [7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
X9251
9FN8166.5
April 13, 2007
WIP
STATUS
BIT
0 101
A1 A0 I3 I2 I1 I0 RB RA P0
SCK
SI
CS
00
ID3 ID2 ID1 ID0
DEVICE ID INTERNAL INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
POT/WCR
ADDRESS
00
P1
00000
00
1011
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)
0101
A1 A0 I3I2 I1 I0 RB RA P0
SCK
SI
CS
00
ID3 ID2 ID1 ID0
DEVICE ID INTERNAL INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
POT/WCR
ADDRESS
00
P1
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
SCK
SI
R
W
INC/DEC CMD ISSUED
tWRID
VOLTAGE OUT
FIGURE 7. INCREMENT/DECREMENT TIMING SPEC
X9251
10 FN8166.5
April 13, 2007
Instruction Format
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Counter Register
3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Wiper Position
(Sent by X9251 on SO) CS
Rising
Edge
010100A1A010010000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Data Byte
(Sent by Host on SI) CS
Rising
Edge
010100A1A010100000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses Data Byte
(Sent by X9271 on SO) CS
Rising
Edge
010100A1A01011RBRAP1 P0 D
7D
6D
5D
4D
3D
2D
1D
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses Data Byte
(Sent by Host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01100RBRAP1 P0 D
7D
6D
5D
4D
3D
2D
1D
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR
Addresses CS
Rising
Edge
010100A1A00001RBRA00
X9251
11 FN8166.5
April 13, 2007
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Increment/Decrement Wiper Counter Register (WCR)
Read Status Register (SR)
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Counter Register
3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01000RBRA00
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
010100A1A01110RBRA0 0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR and WCR
Addresses CS
Rising
Edge
010100A1A01101RBRA0 0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Increment/Decrement
(Sent by Master on SI) CS
Rising
Edge
0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode WCR
Addresses Data Byte
(Sent by X9251 on SO) CS
Rising
Edge
010100A1A0010100010000000 WIP
X9251
12 FN8166.5
April 13, 2007
Absolute Maximum Ratings Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SCK, CS, SI, SO, WP, HOLD, VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) Limits (Note 4)
X9251. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9251-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Characteristics (Over the recommended operating conditions unless otherwise specified.)
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN TYP MAX UNITS
RTOTAL End to End Resistance T version 100 kΩ
RTOTAL End to End Resistance U version 50 kΩ
End to End Resistance Tolerance ±20 %
RWWiper Resistance IW = @ VCC = 3V 300 Ω
IW = @ VCC = 5V 220 Ω
VTERM Voltage on any RH or RL Pin VSS = 0V VSS VCC V
Noise (Note 6) Ref: 1V -120 dBV/√Hz
Resolution 0.4 %
Absolute Linearity (Note 1) Rw(n)(actual) - Rw(n)(expected) (Note 5) -1 +1 MI (Note 3)
Relative Linearity (Note 2) Rw(n + 1) - [Rw(n) + MI] (Note 5) -0.6 +0.6 MI (Note 3)
Temperature Coefficient of RTOTAL (Note 6) ±300 ppm/°C
Ratiometric Temp. Coefficient (Note 6) ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances See Macro model, (Note 6) 10/10/25 pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/255 or (RH - RL)/255, single pot
4. During power up VCC > VH, VL, and VW.
5. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
V(VCC)
RTOTAL
V(VCC)
RTOTAL
X9251
13 FN8166.5
April 13, 2007
NOTES:
6. This parameter is not 100% tested
7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.)
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN. TYP MAX UNITS
ICC1 VCC supply current
(active) fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS 400 μA
ICC2 VCC supply current
(non-volatile write) fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS 15mA
ISB VCC current (standby) SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V 3μA
ILI Input leakage current VIN = VSS to VCC 10 μA
ILO Output leakage current VOUT = VSS to VCC 10 μA
VIH Input HIGH voltage VCC x 0.7 V
VIL Input LOW voltage VCC x 0.3 V
VOL Output LOW voltage IOL = 3mA 0.4 V
VOH Output HIGH voltage IOH = -1mA, VCC ≥ +3V VCC - 0.8 V
VOH Output HIGH voltage IOH = -0.4mA, VCC ≤ +3V VCC - 0.4 V
Endurance and Data Retention
PARAMETER MIN UNITS
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Capacitance
SYMBOL TEST TEST CONDITIONS TYP UNITS
CIN/OUT (Note 6) Input/Output capacitance (SI) VOUT = 0V 8 pF
COUT (Note 6) Output capacitance (SO) VOUT = 0V 8 pF
CIN (Note 6) Input capacitance (A0, A1, CS, WP, HOLD, and SCK) VIN = 0V 6 pF
Power-Up Timing
SYMBOL PARAMETER MIN MAX UNITS
tr VCC (Note 6) VCC Power-up rate 0.2 V/ms
tPUR (Note 7) Power-up to initiation of read operation 1 ms
tPUW (Note 7) Power-up to initiation of write operation 50 ms
A.C. Test Conditions
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9251
14 FN8166.5
April 13, 2007
Equivalent A.C. Load Circuit
RH
10pF
CLCL
RW
RTOTAL
CW
25pF
10pF
RL
SPICE Macromodel
VCC
2kΩ
10pF
SO pin
2kΩ
AC TIMING
SYMBOL PARAMETER MIN MAX UNITS
fSCK SPI clock frequency 2MHz
tCYC SPI clock cycle rime 500 ns
tWH SPI clock high rime 200 ns
tWL SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 50 ns
tRI SI, SCK, HOLD and CS input rise time 2 μs
tFI SI, SCK, HOLD and CS input fall time 2 μs
tDIS SO output disable time 0 250 ns
tVSO output valid time 200 ns
tHO SO output hold time 0 ns
tRO (Note 6) SO output rise time 100 ns
tFO (Note 6) SO output fall time 100 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in high Z 100 ns
tLZ HOLD high to output in low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
tCS CS deselect time 2 μs
tWPASU WP, A0 setup time 0 ns
tWPAH WP, A0 hold time 0 ns
High-Voltage Write Cycle Timing
SYMBOL PARAMETER TYP MAX UNITS
tWR High-voltage write cycle time (store instructions) 5 10 ms
XDCP Timing
SYMBOL PARAMETER MIN MAX UNITS
tWRPO (Note 6) Wiper response time after the third (last) power supply is stable 5 10 μs
tWRL (Note 6) Wiper response time after instruction issued (all load instructions) 5 10 μs
X9251
15 FN8166.5
April 13, 2007
Symbol Table
Timing Diagrams
Input Timing
Output Timing
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
...
CS
SCK
SI
SO
MSB LSB
HIGH IMPEDANCE
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
X9251
16 FN8166.5
April 13, 2007
Hold Timing
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
...
CS
SCK
SI MSB LSB
VWx
tWRL
...
SO HIGH IMPEDANCE
CS
WP
A0
A1
tWPASU tWPAH
(ANY INSTRUCTION)
X9251
17 FN8166.5
April 13, 2007
Applications information
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal
Potentiometer;
Variable voltage divider Two terminal Variable
Resistor;
Variable current
NON INVERTING AMPLIFIER VOLTAGE REGULATOR
OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9251
18 FN8166.5
April 13, 2007
Application Circuits (continued)
ATTENUATOR FILTER
INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
FUNCTION GENERATOR
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9251
19 FN8166.5
April 13, 2007
X9251
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α0° 8° 0° 8° -
Rev. 1 4/06
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third pa rties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8166.5
April 13, 2007
X9251
Thin Shrink Small Outline Package Family (TSSOP)
N(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.