RHF1201KSO2 - STMicroelectronics

October 2008 Rev 3 1/26

RHF1201

Radiation hardened 12-bit 0.5 to 50 Msps A/D converter

Features

■Wide sampling range: 0.5 Msps to 50 Msps

■OptimwattTM adaptive power:

44 mW at 0.5 Msps, 100 mW at 50 Msps

■Optimized for 2 Vpp differential input

■SFDR up to 75 dB at FS= 50 Msps,

Fin =15MHz

■2.5 V/3.3 V compatible digital I/O

■Built-in reference voltage with external bias

capability

■Hermetic package

■Rad hard: 300 kRad(Si) TID

■Failure immune (SEFI) and latchup immune

(SEL) up to 120 MeV-cm2/mg at 2.7 V and

125° C

■Qml-V qualified, smd 5962-05217

Applications

■Digital communication satellites

■Space data acquisition systems

■Aerospace instrumentation

■Nuclear and high-energy physics

Description

The RHF1201 is a 12-bit 50 MHz maximum

sampling frequency analog-to-digital converter

that uses pure (ELDRS-free) CMOS 0.25 µm

technology combining high performance, radiation

robustness and very low power consumption.

The RHF1201 is based on a pipeline structure

and digital error correction to provide excellent

static linearity and achieve 10.3 effective bits at

FS= 50 Msps, and Fin = 15 MHz.

Specifically designed to optimize power

consumption, the RHF1201 can dissipate as little

as 100 mW at 50 Msps, while maintaining a high

level of performance.

It integrates a proprietary track-and-hold structure

making it ideal for IF-sampling applications up to

150 MHz.

A voltage reference is integrated in the circuit to

simplify the design and minimize external

components. A tri-state capability is available on

the outputs to allow common bus sharing. Output

data can be coded in two different formats.

A Data Ready signal which is raised when the

data is valid on the output can be used for

synchronization purposes.

The RHF1201 is available in a small 48-pin

hermetic SO-48 package for temperatures

ranging between -55° C to +125° C.

Ceramic SO-48 package

www.st.com

Contents RHF1201
2/26   
Contents
Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Equivalent circuits   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings and operating conditions   . . . . . . . . . . . . . 8
Electrical characteristics (unchanged after 300 kRad)  . . . . . . . . . . . . . 9
Application information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1 RHF1201 operating modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11
2 Driving the analog input  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 Reference connection   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
3.1 Internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 External reference  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Clock input  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
5 Power consumption optimization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
6 Layout precautions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
Definitions of specified parameters   . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1 Static parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
2 Dynamic parameters   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
Package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

RHF1201 Block diagram

3/26

1 Block diagram

Figure 1. Block diagram

stage stage stage

2 n

Reference

Timing

circuit

Sequencer-phase shifting

Digital data correction

Buffers

IPOL

VREFM

VREFP

CLK

+2.5V

VIN

VINB

DFSB

OEB

D11

INCM

GND

GNDA

+2.5V/3.3V

SRC

Pin connections RHF1201

4/26

2 Pin connections

Figure 2. Pin connections (top view)

GNDBI

GNDBE

VCCBE

(MSB)D11

D10

(LSB)D0

VCCBE

GNDBE

VCCBI

DGND

CLK

DGND

DVCC

AVCC

AGND

INCM

AGND

VINB

AGND

VIN

AGND

VREFM

VREFP

IPOL

AGND

AVCC

DFSB

OEB

SRC

GNDBI

GNDBE

VCCBE

(MSB)D11

D10

(LSB)D0

VCCBE

GNDBE

VCCBI

DGND

CLK

DGND

DVCC

AVCC

AGND

INCM

AGND

VINB

AGND

VIN

AGND

VREFM

VREFP

IPOL

AGND

AVCC

DFSB

OEB

SRC

GNDBI

GNDBE

VCCBE

(MSB)D11

D10

(LSB)D0

VCCBE

GNDBE

VCCBI

DGND

CLK

DGND

DVCC

AVCC

AGND

INCM

AGND

VINB

AGND

VIN

AGND

VREFM

VREFP

IPOL

AGND

AVCC

DFSB

OEB

SRC

RHF1201 Pin descriptions

5/26

3 Pin descriptions

Table 1. Pin descriptions

Pin Name Description Note Pin Name Description Note

1 GNDBI Digital buffer ground 0 V 25 SRC Slew rate control input 2.5 V/3.3 V CMOS

input

2 GNDBE Digital buffer ground 0 V 26 OEB Output Enable input 2.5 V/3.3 V CMOS

input

3 VCCBE Digital buffer power

supply 2.5 V/3.3 V 27 DFSB Data Format Select input 2.5 V/3.3 V CMOS

input

4 NC Non connected 28 AVCC Analog power supply 2.5 V

5 NC Non connected 29 AVCC Analog power supply 2.5 V

6 OR Out Of Range output CMOS output

(2.5 V/3.3 V) 30 AGND Analog ground 0 V

7 D11(MSB) Most Significant Bit

output

CMOS output

(2.5 V/3.3 V) 31 IPOL Analog bias current input

8 D10 Digital output CMOS output

(2.5 V/3.3 V) 32 VREFP Top voltage reference Can be external

9 D9 Digital output CMOS output

(2.5 V/3.3 V) 33 VREFM Bottom voltage

reference External

10 D8 Digital output CMOS output

(2.5 V/3.3 V) 34 AGND Analog ground 0 V

11 D7 Digital output CMOS output

(2.5 V/3.3 V) 35 VIN Analog input Optimized for 1Vpp

12 D6 Digital output CMOS output

(2.5 V/3.3 V) 36 AGND Analog ground 0 V

13 D5 Digital output CMOS output

(2.5 V/3.3 V) 37 VINB Inverted analog input Optimized for 1Vpp

14 D4 Digital output CMOS output

(2.5 V/3.3 V) 38 AGND Analog ground 0 V

15 D3 Digital output CMOS output

(2.5 V/3.3 V) 39 INCM Input common mode 0.5 V

16 D2 Digital output CMOS output

(2.5 V/3.3 V) 40 AGND Analog ground 0 V

17 D1 Digital output CMOS output

(2.5 V/3.3 V) 41 AVCC Analog power supply 2.5 V

18 D0(LSB) Least Significant Bit

output

CMOS output

(2.5 V/3.3 V) 42 AVCC Analog power supply 2.5 V

19 DR Data Ready output CMOS output

(2.5 V/3.3 V) 43 DVCC Digital power supply 2.5 V

20 NC Non connected 44 DVCC Digital power supply 2.5 V

21 NC Non connected 45 DGND Digital ground 0 V

22 VCCBE Digital Buffer power

supply 2.5 V/3.3 V 46 CLK Clock input 2.5 V compatible

CMOS input

23 GNDBE Digital Buffer ground 0 V 47 DGND Digital ground 0 V

24 VCCBI Digital Buffer power

supply 2.5 V 48 DGND Digital ground 0 V

Equivalent circuits RHF1201

6/26

4 Equivalent circuits

Figure 3. Analog inputs Figure 4. Output buffers

VIN or VINB

7pF

(pad)

AVCC

AGND

D0…D11

7pF

(pad)

AVCC

AGND

OEB

data AVCC

Figure 5. Clock input Figure 6. Data format input

CLK

7pF

(pad)

DVCC

DGND

DFSB

7pF

(pad)

AVCC

AGND

RHF1201 Timing characteristics

7/26

5 Timing characteristics

Figure 7. Timing diagram

Table 2. Timing table

Symbol Parameter Test conditions Min Typ Max Unit

FSSampling frequency 0.5 50 Msps

Tck Sampling clock cycle 20 2000 ns

DC Clock duty cycle(1)

1. For any clock frequency and any duty cycle the high level clock pulse must be longer than 10 ns.

FS = 45 Msps 45 50 65 %

TC1 Clock pulse width (high) 10 1800 ns

TC2 Clock pulse width (low) 8 1800 ns

Tod

Data output delay

(fall of clock to data valid) 10 pF load 4 5 6 ns

Tpd Data pipeline delay 5.5 5.5 5.5 cycles

Tdr

Data ready delay after data

change 0.5 cycles

Ton

Falling edge of OEB to

digital output valid data 13ns

Toff

Rising edge of OEB to

digital output tri-state 13ns

TrD Data rising time 5 pF load, SRC = 0 2.8 ns

5 pF load, SRC = 1 5.7 ns

TfD Data falling time 5 pF load, SRC = 0 2 ns

5 pF load, SRC = 1 4.3 ns

N-3

N-2 N-1

N+4

N+5

N+3

N+1

N+2

N+6

N-3 N-1N-4N-5N-6N-7N-8N-9

CLK

OEB

Tod Ton

Toff

Tpd + Tod

HZ state

DATA

OUT

Tdr

Absolute maximum ratings and operating conditions RHF1201

8/26

6 Absolute maximum ratings and operating conditions

Table 3. Absolute maximum ratings

Symbol Parameter Values Unit

AVCC Analog supply voltage(1)

1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude

of input and output voltages must never exceed -0.3 V or VCC +0.3 V.

0 to 3.3 V

DVCC Digital supply voltage(1) 0 to 3.3 V

VCCBI Digital buffer supply voltage(1) 0 to 3.3 V

VCCBE Digital buffer supply voltage(1) 0 to 3.6 V

IDout Digital output current -100 to 100 mA

Tstg Storage temperature -65 to +150 °C

Rthjc Thermal resistance junction to case 22 °C/W

Rthja Thermal resistance junction to ambient 125 °C/W

ESD HBM (human body model)(2)

2. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a

1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations

while the other pins are floating.

2kV

Table 4. Operating conditions

Symbol Parameter Min Typ Max Unit

AVCC Analog supply voltage 2.3 2.5 2.7 V

DVCC Digital supply voltage 2.3 2.5 2.7 V

VCCBI Digital internal buffer supply 2.3 2.5 2.7 V

VCCBE Digital output buffer supply 2.3 2.5 3.4 V

VREFP Top external reference voltage 0.5 1.8 V

VREFM Bottom external reference voltage 0 0.5 V

VINCM Forced common mode voltage 0 0.5 V

VIN

VIN maximum voltage versus GND 1.6 V

VIN minimum voltage versus GND -0.4 V

VINB

VINB maximum voltage versus GND 1.6 V

VINB minimum voltage versus GND -0.4 V

FIN Input analog frequency band 0 150 MHz

RHF1201 Electrical characteristics (unchanged after 300 kRad)

9/26

7 Electrical characteristics (unchanged after 300 kRad)

Test conditions, unless otherwise specified are: AVCC =DV

CC =V

CCBE =2.5V,

FS= 50 Msps, Fin =2MHz, V

REFP = Internal, VREFM =0V, T

amb = 25° C

Table 5. Analog inputs

Symbol Parameter Test conditions Min Typ Max Unit

VIN-VINB

Full scale input differential voltage(1)

(FS)(2) 2V

p-p

Cin Input capacitance 7.0 pF

ERB Effective resolution bandwidth(1) 95 MHz

1. See Section 9: Definitions of specified parameters on page 20 for more information.

2. Note that the converter is optimized to achieve the best conversion at a differential analog input of 2 Vp-p.

Table 6. Internal reference voltage

Symbol Parameter Test conditions Min Typ Max Unit

VREFP Top internal reference voltage(1) AVCC=2.5 V 0.79 0.95 1.16 V

VINCM Input common mode voltage(1) AVCC=2.5 V 0.40 0.52 0.67 V

Te m p C o Temperature coefficient of VREFP(1) Tmin <T

amb <T

max 0.12 mV/°C

Temperature coefficient of VREFM(1) Tmin <T

amb <T

max 0.12 mV/°C

1. Not fully tested over the temperature range. Guaranteed by sampling.

Table 7. Accuracy

Symbol Parameter Test conditions Min Typ Max Unit

OE Offset error Fin = 2 MHz,

VIN @+1dBFS ±0.3 %

DNL Differential non linearity(1) Fin = 2 MHz,

VIN @+1dBFS ±0.5 LSB

INL Integral non linearity(1) Fin = 2 MHz,

VIN @+1dBFS ±1.7 LSB

- Monotonicity and no missing codes Guaranteed

1. See Section 9: Definitions of specified parameters on page 20 for more information.

Electrical characteristics (unchanged after 300 kRad) RHF1201

10/26

Table 8. Digital inputs and outputs

Symbol Parameter Test conditions Min Typ Max Unit

Clock input

VIL Logic "0" voltage 0 0.8 V

VIH Logic "1" voltage 2.0 2.5 V

Digital inputs

VIL Logic "0" voltage 0 0.25 x

VCCBE

VIH Logic "1" voltage 0.75 x

VCCBE

VCCBE V

Digital outputs

VOL Logic "0" voltage IOL =-1mA 0 0.2 V

VOH Logic "1" voltage IOH =1mA VCCBE

- 0.2 V V

IOZ High impedance leakage current OEB set to VIH -15 15 µA

CLOutput load capacitance 15 pF

Table 9. Dynamic characteristics

Symbol Parameter(1) Test conditions(2) Min Typ Max Unit

SFDR Spurious free dynamic range

Fin =15MHz -75 -63 dBc

Fin =95MHz -70

Fin = 145 MHz -57 dBc

SNR Signal to noise ratio

Fin = 15 MHz 59 63 dB

Fin = 95 MHz 60 dB

Fin = 145 MHz 59

THD Total harmonics distortion

Fin =15MHz -76 -64 dB

Fin =95MHz -72 dB

Fin = 145 MHz -58

SINAD Signal to noise and distortion ratio

Fin = 15 MHz 59 63 dB

Fin =95MHz 60

Fin = 145 MHz 56.5 dB

ENOB Effective number of bits

Fin = 15 MHz 9.7 10.3 bits

Fin = 95 MHz 9.5 bits

Fin = 145 MHz 9.1

1. See Section 9: Definitions of specified parameters on page 20 for more information.

2. VREFP = 1 V with external supply.

RHF1201 Application information

11/26

8 Application information

The RHF1201 is a high-speed analog-to-digital converter based on a pipeline architecture

and a 0.25 µm CMOS process to achieve the best performance in terms of linearity and

power consumption.

The pipeline structure consists of 11 internal conversion stages in which the analog signal is

fed and sequentially converted into digital data. The input signal is sampled on the rising

edge of the clock.

The first 10 stages of the conversion include at each stage:

●an analog-to-digital converter.

●a digital-to-analog converter.

●a track and hold.

●an amplifier with a gain of 2.

A 1.5-bit conversion resolution is also performed at each stage. The final stage is simply a

comparator. Each resulting LSB-MSB couple is then time-shifted to recover from the delay

caused by the conversion. Digital data correction completes the processing by recovering

from the redundancy of the (LSB-MSB) couple at each stage. The corrected data is output

through the digital buffers.

The advantages of such a converter reside in the combination of a pipeline architecture and

the most advanced silicon technologies. The highest dynamic performance is achieved

while consumption remains extremely low.

8.1 RHF1201 operating modes

Extra functionalities are provided to simplify the application board as much as possible. The

operating modes offered by the RHF1201 are described in Ta ble 1 0 .

Table 10. RHF1201 operating modes

Inputs Outputs

Analog input differential

Amplitude DFSB OEB SRC OR DR Most significant bit (MSB)

(VIN-VINB) above maximum range HLXHCLK D11

L L X H CLK D11 complemented

(VIN-VINB) below minimum range HLXHCLK D11

L L X H CLK D11 complemented

(VIN-VINB) within range HLXLCLK D11

L L X L CLK D11 complemented

X X H X HZ HZ HZ(1)

1. High impedance.

X X L H X CLK Low slew rate

X X L L X CLK High slew rate

Application information RHF1201

12/26

Data format select (DFSB): when set to low level (VIL), the digital input DFSB provides a

two’s complement digital output MSB. This can be of interest when performing some further

signal processing. When set to high level (VIH), DFSB provides a standard binary output

coding.

Output enable (OEB): when set to low level (VIL), all digital outputs remain active. When

set to high level (VIH), all digital output buffers are in high impedance state while the

converter goes on sampling. When OEB is set to a low level again, the data arrives on the

output with a very short Ton delay. This feature enables the chip select of the device.

Figure 7 on page 7 summarizes this functionality.

Slew rate control (SRC): when set to high level (VIH), all digital output currents are limited

to a clamp value so that digital noise power is reduced to the minimum. When set to low

level (VIL), the output edges are twice as fast.

Out of range (OR): this function is implemented on the output stage in order to set an "Out

of Range" flag whenever the digital data is over the full-scale range.

Typically, there is a detection of all the data at ’0’ or all the data at ’1’. It sets an output signal

OR which is in low level state (VOL) when the data stays within the range, or in high level

state (VOH) when the data is out of range.

Data ready (DR): the Data Ready output is an image of the clock being synchronized on the

output data (D0 to D11). This is a very helpful signal that simplifies the synchronization of

the measurement equipment or of the controlling DSP.

As all other digital outputs, DR goes into high impedance state when OEB is set to high level

as shown in Figure 7 on page 7.

8.2 Driving the analog input

Figure 8. Equivalent VIN - VINB

INCM (level 0, code 2048)

(level –FS, code 0)

(level +FS, code 4095)

FS (Full Scale), 2Vp-p

VIN

VINB

VIN-VINB

RHF1201 Application information

13/26

Figure 9. Maximum input swing on VIN or VINB

Figure 10. 2 Vp-p single-ended (DC coupling)

+1.6V

0V (ground )

-0.4V

+1.6V

0V (ground )

-0.4V

VIN

VINB

+1.6V

0V (Ground)

-0.4V

External +0.6V

VIN

INCM

Ground

INCM= +0.6V

VIN-VINB(2Vp-p)

VIN

VINB

+1.6V

0V (Ground)

-0.4V

External +0.6V

VIN

INCM

Ground

INCM= +0.6V

VIN-VINB(2Vp-p)

Application information RHF1201

14/26

Figure 11. 2 Vp-p pure differential

The RHF1201 is designed to obtain optimum performance when driven on differential inputs

with a differential amplitude of 2 V peak-to-peak (2Vp-p). This is the result of 1 Vp-p on the

VIN and VINB inputs in phase opposition.

The RHF1201 is specifically designed to meet sampling requirements for IF, intermediate

frequency input signals. In particular, the track-and-hold in the first stage of the pipeline is

designed to minimize the linearity limitations as the analog frequency increases.This is

achieved by making the input impedance independent from the input frequency.

As a result, the RHF1201 can maintain high performance up to an analog frequency of

150 MHz (see Table 4 on page 8).

Figure 12 on page 15 shows a differential input solution. The input signal is fed to the

primary of the transformer, while the secondary drives both ADC inputs. The transformer

must be 50 Ω matched, and it must be loaded with 50 Ω on both the primary and the

secondary. Tracks between the secondary and VIN and VINB pins must be as short as

possible.

The common mode voltage of the ADC (INCM) is connected to the center-tap of the

secondary of the transformer in order to bias the input signal around this common voltage,

internally set to 0.52 V (see Table 6 on page 9).The INCM is decoupled to maintain a low

noise level on this node. Ceramic technology for decoupling provides good stability of the

capacitor across a wide bandwidth.

VIN

VINB

1Vp-p

VIN-VINB(2Vp-p)

INCM

(internal)

1Vp-p

Ground

INCM

VIN

VINB

1Vp-p

VIN-VINB(2Vp-p)

INCM

(internal)

1Vp-p

Ground

INCM

RHF1201 Application information

15/26

Figure 12. Differential implementation using a balun

Some applications may require a single-ended input, which can easily be achieved with the

configuration shown in Figure 13. However, with this type of configuration, a degradation in

the rated performance of the RHF1201 may occur, compared with a differential

configuration. To avoid this, a sufficiently-decoupled DC reference should be used to bias

the RHF1201 inputs. One may also use an AC-coupled analog input and set the DC analog

level with a high value resistor R (10 kΩ to 100 kΩ) connected to a proper DC source. Cin

and R behave like a high-pass filter and are calculated to set a cut-off frequency as low as

possible. An example of VINB decoupling to reduce noise is shown in Figure 13.

The internal references INCM or REFP (refer to Ta b l e 6 ) can be used as proper DC sources.

Using a 1 V DC with a single-ended signal of 2 Vp-p input amplitude improves the SNR

performance.

Figure 13. AC-coupling single-ended input configuration

100nF* ceramic

(as close as possible

to INCM pin)

VIN

VINB

INCM

RHF1201

50Ω

100pF

ADT1-1

1:1

Analog Input Signal

(50Ω output)

50Ω track Short track

470nF* ceramic

(as close as possible

to the transformer)

External INCM

(optional)

*the use of a ceramic technology is

preferable for a large bandwidth

stab ility of the capacitor.

100nF ceramic*

(as close as possible

to INCM pin)

Cin

Analog Input Signal

(50Ω output)

50Ω track Short track

50Ω

External INCM

(optional)

VIN

VINB

INCM RHF1201

Short track

470pF

ceramic*

100nF

ceramic*

*the use of a ceramic technology is

preferab le for a large bandwidth

stability of the capacitor.

Application information RHF1201

16/26

Figure 14. AC-coupling single-ended input configuration for low frequencies

The use of the C capacitor (in the range of 33 pF for example) is dedicated to a low input

frequency range. This capacitor is efficient to reduce the noise in the higher frequencies.

When coupled with the resistors, R and C together behave like a low-pass filter. For

example: R = 10 k and C = 33 pF, the cut-off frequency of this low-pass filter equals

482 kHz.

100nF ceramic*

(as close as possible

to INCM pin)

Cin

Analog Input Signal

(50Ω output)

50Ω track Short track

50Ω

External INCM

(optional)

*ceramic technology for a large

bandwidth stability of the capacitor

VIN

VINB

INCM RHF1201

Short track

RHF1201 Application information

17/26

8.3 Reference connection

8.3.1 Internal reference

In the standard configuration, the ADC is biased with the internal reference voltage. The

VREFM pin is connected to analog ground while VREFP is internally set to a voltage close to

1.0 V. The VREFP should be decoupled so as to minimize low and high frequency noise.

Figure 15 shows the schematics.

Figure 15. Internal reference setting

8.3.2 External reference

An external reference voltage can be used for specific applications requiring even better

linearity or enhanced temperature behavior. In such a case, the amplitude of the external

voltage must be at least equal to the internal reference (see Ta b l e 6 ). An external voltage

reference with the configuration shown in Figure 16 can be used to obtain optimum

performance. Decoupling is achieved by using ceramic capacitors, which provide optimum

linearity versus frequency.

Figure 16. External reference setting

470nF*

100nF*

VIN

VINB

VREFM

VREFP

RHF1201

as close as possible

the ADC pins

*the use of a ceramic technology is

preferable for a large bandwidth

st ability of t he capacito r .

470nF*

100nF*

VIN

VINB

VREFM

VCCA VREFP

External

Reference

1kΩ

as close as possible

the ADC pins

*the use of a ceram ic technology is

preferable for a large bandwidth

stability of the capacitor.

Application information RHF1201

18/26

8.4 Clock input

The quality of the converter very much depends on the accuracy of the clock input in terms

of aperture jitter. The use of a low jitter crystal controlled oscillator is recommended.

The following points should also be considered.

●The input signal must be square-shaped with sharp edges of less than 1 ns.

●At 45 Msps, the duty cycle must be between 45% and 65%; in any case, the high level

clock pulse duration must be longer than 10 ns.

●The clock power supplies must be independent from the ADC output supplies to avoid

digital noise modulation on the output.

●When powered-on, the circuit needs several clock periods to reach its normal operating

conditions.

8.5 Power consumption optimization

The internal architecture of the RHF1201 makes it possible to optimize power consumption

according to the sampling frequency of the application. For this purpose, an external Rpol

resistor is placed between the IPOL pin and the analog ground. Therefore, the total

dissipation can be adjusted across the entire sampling range from 0.5 Msps to 50 Msps to

fulfil the requirements of applications where power saving is critical.

For low sampling frequencies, the resistor value may be adjusted to decrease the analog

current without any deterioration of dynamic performance.

The total power consumption optimization depending on the value of Rpol is as follows.

Figure 17. Analog current consumption according to Rpol resistance

0 102030405060708090

100

Rpol

Icca

Rpol (kΩ) - Icca (mA)

Sampling Frequency, Fs (MHz)

RHF1201 Application information

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8.6 Layout precautions

●Use of dedicated ground planes (analog, digital, internal and external buffer) on the

PCB is recommended for high-speed circuit applications to provide low parasitic

inductance and resistance.

●The separation of the analog signal from the digital output is mandatory to prevent

noise from coupling onto the input signal.

●Power supply bypass capacitors must be placed as close as possible to the IC pins in

order to improve high-frequency bypassing and reduce harmonic distortion.

●All leads must be wide and as short as possible, especially for the analog input, in order

to decrease parasitic capacitance and inductance.

●In order to minimize the transition current when the output changes, it is necessary to

reduce as much as possible the capacitive load at the digital outputs by using the

shortest-possible routing tracks.

●Choose the smallest possible component sizes (SMD).

Definitions of specified parameters RHF1201

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9 Definitions of specified parameters

9.1 Static parameters

Static measurements are performed using the histograms method on a 2 MHz input signal,

sampled at 50 Msps, which is sufficiently high to fully characterize the test frequency

response. The input level is +1 dBFS to saturate the signal.

Differential non-linearity (DNL)

The average deviation of any output code width from the ideal code width of 1 LSB.

Integral non-linearity (INL)

An ideal converter exhibits a transfer function which is a straight line from the starting code

to the ending code. The INL is the deviation from this ideal line for each transition.

9.2 Dynamic parameters

Dynamic measurements are performed by spectral analysis, applied to an input sine wave

of various frequencies and sampled at 50 Msps.

Spurious free dynamic range (SFDR)

The ratio between the power of the worst spurious signal (not always a harmonic) and the

amplitude of the fundamental tone (signal power) over the full Nyquist band. It is expressed

in dBc.

Total harmonic distortion (THD)

The ratio of the rms sum of the first five harmonic distortion components to the rms value of

the fundamental line. It is expressed in dB.

Signal to noise ratio (SNR)

The ratio of the rms value of the fundamental component to the rms sum of all other spectral

components in the Nyquist band (fs/2) excluding DC, fundamental and the first five

harmonics. SNR is reported in dB.

Signal to noise and distortion ratio (SINAD)

Similar ratio as for SNR but including the harmonic distortion components in the noise figure

(not DC signal). It is expressed in dB.

The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula:

SINAD = 6.02 × ENOB + 1.76 dB

When the applied signal is not full scale (FS), but has an amplitude A0, the SINAD

expression becomes:

SINAD = 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS)

The ENOB is expressed in bits.

RHF1201 Definitions of specified parameters

21/26

Effective resolution bandwidth

For a given sampling rate and clock jitter, this is the analog input frequency at which the

SINAD is reduced by 3 dB.

Pipeline delay

Delay between the initial sample of the analog input and the availability of the corresponding

digital data output on the output bus. Also called data latency. It is expressed as a number of

clock cycles.

When powered off to on, there is a delay of several clock cycles before the ADC can achieve

a reliable and stable signal conversion. During this delay, some conversion artefacts may

appear.

Package information RHF1201

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10 Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

RHF1201 Package information

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Figure 18. Ceramic SO-48 package mechanical drawing

Table 11. Ceramic SO-48 package mechanical data

Ref.

Dimensions

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 2.18 2.47 2.72 0.086 0.097 0.107

b 0.20 0.254 0.30 0.008 0.010 0.012

c 0.12 0.15 0.18 0.005 0.006 0.007

D 15.57 15.75 15.92 0.613 0.620 0.627

E 9.52 9.65 9.78 0.375 0.380 0.385

E1 10.90 0.429

E2 6.22 6.35 6.48 0.245 0.250 0.255

E3 1.52 1.65 1.78 0.060 0.065 0.070

e 0.635 0.025

f 0.20 0.008

L 12.28 12.58 12.88 0.483 0.495 0.507

P 1.30 1.45 1.60 0.051 0.057 0.063

Q 0.66 0.79 0.92 0.026 0.031 0.036

S1 0.25 0.43 0.61 0.010 0.017 0.024

Ordering information RHF1201

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11 Ordering information

Table 12. Order codes

Order code Description Temperature

range Package Marking

RHF1201KSO1 Engineering model -55 °C to 125 °C SO-48 RHF1201KSO1

RHF1201KSO2 Engineering model -55 °C to 125 °C SO-48 RHF1201KSO2

RHF1201KSO-01V Flight model -55 °C to 125 °C SO-48 F0521701VXC

RHF1201 Revision history
 25/26
12 Revision history
         
Table 13. Document revision history
Date Revision Changes
01-Sep-2006 1 Initial release in new format.
29-Jun-2007 2
Updated failure immune and latchup immune value to 120 MeV-
cm2/mg.
Updated package mechanical data.
Removed reference to non rad-hard components from Section 8.3.2: 
External reference on page 17.
10-Oct-08 3
Changed cover page graphic.
Changed Figure 2.
Added Chapter 4: Equivalent circuits.
Added Note 2 under Table 3.
Expanded Ta b l e 4  with additional parameters.
Modified "Test conditions" and Vrefp/Vincm in Ta b l e 6 .
Improved readability in Ta b l e 1 0 .
Added Figure 8 to Figure 11.
Modified Figure 12 and Figure 13.
Added Figure 14.
Removed IF sampling section.
Modified Figure 15 and Figure 16. Added Figure 17.
Added ECOPACK information and updated presentation in 
Chapter 10.

RHF1201

26/26

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