XGS Family XGS 12000, XGS 9400 and XGS 8000 Global Shutter CMOS Image Sensors Description The XGS CMOS image sensor family provides high resolution, high performance global shutter image capture. The family comes in different resolutions in a single package; 8.8, 9.4 and 12.6 Megapixels with up to 1-inch optical format. The 21 mm x 20 mm package makes the XGS family particularly suited for integration in 29 mm x 29 mm camera formats. The high speed, 12-bit output maximally leverages interfaces such as USB 3.2, Thunderboltt 2 and 10 GigE. Image data is read out through a column ADC architecture and then transferred over a HiSPi interface. On-chip logic, programmable via the serial interface, generates internal timing for integration and readout control. Up to three register configurations can be programmed and sequentially enabled (frame by frame) using a single command over the control interface. Optical Format Active Pixels Typical Value XGS 12000 1-inch (16.4 mm Diagonal) XGS 9400 1/1.2-inch (13.9 mm Diagonal) XGS 8000 1/1.1-inch (14.8 mm Diagonal) XGS 12000 4096 (H) x 3072 (V) XGS 9400 3072 (H) x 3072 (V) XGS 8000 4096 (H) x 2160 (V) Pixel Size 3.2 m Color Filter Array Monochrome, Bayer Shutter Type Global Shutter Input Clock 32.4 MHz Output Interface HiSPi (24 Lanes - 777.6 Mbps/lane) Frame Rate (12-bit) 24 Lanes (-X1) XGS 12000 90 fps XGS 9400 90 fps XGS 8000 128 fps Features * On-chip 12-bit Column ADCs * Companding Mode for 60 fps (12-lane) and 30 fps (6-lane) at Full Resolution * Data Interface: 24-lane HiSPi (Scalable * * * * Table 1. KEY PERFORMANCE PARAMETERS Parameter www.onsemi.com * * Low-Voltage Signaling) Configurable Number of HiSPi Lanes: 24, 18, 12 or 6 Lanes Two-Wire (I2C) and Four-Wire (SPI) Serial Interface Triggered Integration and Readout Control Programmable Control for up to 8 Regions of Interest (ROI) Context Switching These Devices are Pb-Free, Halogen Free/ BFR Free and are RoHS Compliant Applications * * * * * * Machine Vision Security Intelligent Transportation Systems (ITS) Broadcasting Medical Scientific 12 Lanes (-X2) XGS 9400 56 fps XGS 8000 80 fps 6 Lanes (-X3) XGS 12000 28 fps Read Noise < 4 e- (1x), 1.9 e- (4x) SNRMAX 40 dB Dynamic Range 68 dB Supply Voltages 1.2V, 2.8 V, 3 V (0.4 V, 1.8 V Optional) Power Consumption 1 W (Full Speed, Full Resolution) Operating Temp. -40C to 85C (Junction) Package 163-pin CLGA (Ceramic Land Grid Array) (c) Semiconductor Components Industries, LLC, 2018 July, 2019 - Rev. 1 1 Publication Order Number: XGS12M/D XGS Family ORDERING INFORMATION Table 2. ORDERABLE PART NUMBERS (Note 1, Note 2) Part Number Product Description NOIX1SN012KB-LTI 12.6 Mp Mono NOIX1SE012KB-LTI 12.6 Mp Color NOIX3SN012KB-LTI 12.6 Mp Mono NOIX3SE012KB-LTI 12.6 Mp Color NOIX1SN9400B-LTI 9.4 MP Mono NOIX1SE9400B-LTI 9.4 MP Color NOIX2SN9400B-LTI 9.4 MP Mono NOIX2SE9400B-LTI 9.4 MP Color NOIX1SN8000B-LTI 8.8 Mp Mono NOIX1SE8000B-LTI 8.8 Mp Color NOIX2SN8000B-LTI 8.8 Mp Mono NOIX2SE8000B-LTI 8.8 Mp Color Speed Grade Resolution (H x V) 24 lanes 4096 x 3072 6 lanes 24 lanes 3072 x 3072 12 lanes 24 lanes 4096 x 2160 12 lanes 1. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. 2. All devices listed in Table 2 are equipped with microlenses and optimized for a 0 Chief Ray Angle (zero-shift placement). Table 3. ORDERING INFORMATION EVALUATION KITS Part Number Product Description Additional Information NOIX1SN012KBLFB-GEVB Sensor Headboard (12.6 Mp, Mono, 24-Lane) Demo Kit Headboard (incl. NOIX1SN012KB-LTI) (Note 3) NOIX1SE012KBLFB-GEVB Sensor Headboard (12.6 Mp, Color, 24-Lane) Demo Kit Headboard (incl. NOIX1SE012KB-LTI) (Note 3) AGBAN6CS-GEVK Frame Buffer Demo Board AP21088 including Power Adapter AGB1N0CS-GEVK Demo 3 Board FPGA Base Board including USB Cable and Tripod 3. Sensors are soldered to the headboard. www.onsemi.com 2 XGS Family GENERAL DESCRIPTION The XGS family from ON Semiconductor covers three resolutions: 12.6 Mp, 9.4 Mp and 8.8 Mp and three speed grades (24, 12 or 6 HiSPi lanes). Refer to Table 2 for an overview of the available combinations of resolution and speed. Various operating modes enable flexible sensor operation to meet application specific requirements such as reduced data rate implemented by HiSPi lane multiplexing. all pixels to simultaneously integrate light although the subsequent readout is sequential. Note that integration and readout can occur in parallel; while reading out one frame, integration of the next frame can start (i.e. pipelined operation). The core of the sensor is the 12.6 Mp active pixel array. Figure 1 gives an overview of the major functional blocks of the XGS sensor. FUNCTIONAL OVERVIEW The XGS family features global shutter technology for accurate capture of moving objects. Global shutter requires 1 clock lane 1, 2, 3 or 4 data lanes HiSPi HiSPi HiSPi DIGITAL MUX DIGITAL MUX DIGITAL MUX MONITOR_[2:0] DIGITAL GAIN / DATA PEDESTAL COLUMN ADC (GR and GB) TRIG_INT TRIG_RD SEQUENCER RESET_N ROW DRIVER COLUMN STRUCTURE (GR and GB) PIXEL ARRAY (4096 x 3072) COLUMN STRUCTURE (R and B) BIAS COLUMN ADC (R and B) EXTCLK I2C/SPI DIGITAL GAIN / DATA PEDESTAL PLL I2C/SPI DECODER DIGITAL MUX DIGITAL MUX DIGITAL MUX HiSPi HiSPi HiSPi 1 clock lane 1, 2, 3 or 4 data lanes Figure 1. Functional Block Diagram (XGS 12000) www.onsemi.com 3 XGS Family * Sequencer The on-chip logic, programmable through the Two-Wire (I2C) or Four-Wire (SPI) Serial Interface, generates all internal timing for integration control and frame readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing coarse analog gain) and then through a 12-bit column ADC. The data from the ADCs is first stored in the on-chip column memory bank prior to being processed by the digital data path (which provides additional data processing including digital gain and offset). The digital multiplexer can be configured to reduce the number of active data lanes. The maximum output pixel rate on a single lane is 64.8 Megapixel per second, corresponding to a clock rate of 32.4 MHz. Advanced trigger functions enable synchronization to external events (triggered master and slave mode) but also allow synchronizing image readout with the host (receiver) on a frame or line basis (triggered frame or line readout). The sensor supports configuration of up to eight independent ROIs and up to three register configurations (contexts) can be programmed and sequentially applied (frame by frame) with a single command over the control interface. Refer to Figure 1 for the functional blocks described hereafter. * Two-Wire Serial Interface (I2C) I2C-compatible, two-wire serial interface enables user interaction with sensor. * (Four-Wire) Serial Peripheral Interface (SPI) The Four-Wire serial interface can be used as an alternative to the two-wire interface. The SPI enables faster sensor (re-)configuration compared to the two-wire serial interface. * EXTCLK The nominal input-clock frequency is 32.4 MHz. This clock serves as the base clock for the derived clock domains required by the internal sub-blocks and HiSPi output interface. * Phase-locked Loop (PLL) The on-chip phase-locked loop generates all the internal system clocks, including the HiSPi clock. * Bias Generator The bias generator generates the required reference currents used by the on-chip blocks. * * * * * * * * The sequencer generates the sensor timing and controls the image core which contains all pixels, driving and readout circuits. It controls the ADC circuits and provides the necessary information to the digital data path. The sequencer operating and readout modes (ROI readout, subsampling...) can be configured through the SPI interface. The readout parameters are synchronized to frame boundaries to support dynamic reconfiguration without generating any corrupted images. Row Driver The row drivers generate the reset and select signals used to operate the pixel array. Monitor Pins The sequencer can communicate its internal states through the monitor output pins. Column Structure The column structure contains the analog circuits necessary to ensure a proper transfer of the signal to the column ADC. This structure includes the column amplifiers which can be used to apply analog gain to the signal before these are converted by the ADCs. The sensor supports analog gain of 1x, 2x and 4x. The analog gain is applied globally to all pixels. Column ADC For each column, a 12-bit ADC converts the analog signal into a digital value. Digital Gain A linear, digital gain ranging from 1/32x up to 2x can be configured separately for each color channel in steps of 1/32. Data Pedestal This block adds a user programmable, per color channel digital offset to the pixel values. Digital Mux This block handles the lane multiplexing which can be used to reduce the number of output lanes. HiSPi The 24 HiSPi lanes are laid out in six identical HiSPi blocks. Each block consists of four data lanes and one clock lane. The number of active data lanes (1, 2, 3 or 4) depends on the selected multiplex mode. www.onsemi.com 4 XGS Family PIXEL DATA FORMAT (configurable for each context). The ROI configurations are processed after the black reference lines. The lines accessible through the window configurations are limited to the active area region, including interpolation rows. Note that the windows are configured in logical kernel addresses. A kernel contains four image lines and the kernel with logical address 0 corresponds to the lines with physical addresses: - 15:18 for XGS 12000 and XGS 9400 - 471:474 for XGS 8000 Each window configuration consists of two parameters: a start address and window height. The configured windows are reordered such that the ROI with the smallest start address is read out first. After completion of the readout of the first ROI, the line address pointer will be initialized to the start address of the next ROI. For overlapping windows, the sequencer will just continue the readout. Note that the overlapping part is read out only once. Lines are read out from left to right and each line contains different types of pixels. A line starts with 4 dummy pixels followed by 24 electrical black reference pixels. The regular image pixels are preceded and followed by 4 dummy pixels. Dummy pixels are identical to the regular pixels, but may deviate in performance. Therefore the dummy pixels should be discarded. Each line is ended by another 32 black reference pixels followed by 4 dummy pixels. PIXEL ARRAY STRUCTURE The XGS 12000 active pixel array consists of 4096 columns by 3072 rows of optically active pixels. The active resolution of XGS 8000 and XGS 9600 can be found in Table 1. As shown in Figures 2 through 4, the active array is surrounded by a four-pixel wide collar of interpolation pixels for color interpolation purposes. The entire active array (including interpolation pixels) is isolated from the black reference pixels by a collar of dummy pixels. The purpose of these dummy pixels is to improve the image uniformity within the active area. The complete pixel array, including all dummy, black and interpolation pixels, consists of a total of 4176 columns and 3102 rows (2190 rows for XGS 8000). The sensor's active pixel array is shown with the first pixel in the bottom left corner (refer to Figures 2 through 4). The color version of the sensor has a Bayer Color Filter Array (CFA) placed on top of the pixels. The mapping of the CFA with respect to the active pixel array is shown in Figure 2 through 4. PIXEL ARRAY READOUT The electrical black reference lines are read out at the start of every frame. The number of lines to be read out is configurable through the M lines configuration www.onsemi.com 5 XGS Family Figure 2. XGS 12000 Pixel Array www.onsemi.com 6 XGS Family Figure 3. XGS 9400 Pixel Array www.onsemi.com 7 XGS Family Figure 4. XGS 8000 Pixel Array www.onsemi.com 8 XGS Family Readout Order Frame readout starts by setting the read address to the first row of the configured ROI. Once the row is read, the read address is incremented and the next row is read. This cycle continues until the last row of the ROI has been read. The incremental addressing scheme is depicted in Figure 5. CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC EE CCCCCCCC EE CCCCCCCC = Skip Y = Read X Figure 6. Monochrome Subsampling (Read-1-Skip-1) 2. Read Two Skip Two The Read-Two-Skip-Two subsampling scheme is recommended for color sensors as it preserves the Bayer pattern. When using the Read-Two-Skip-Two scheme, the sensor first reads two rows and then skips two rows. From each row being read, first two adjacent pixels will be read, then two will be skipped. This readout scheme is depicted in Figure 7. Figure 5. Incremental Row Addressing Sequence Subsampled Readout During subsampled readout only a subset of the pixel array is read out, enabling faster read out with the same field of view but at the expense of reduced image resolution. In order to support subsampling on both monochrome and color sensors, XGS supports two different subsampling schemes: 1. Read One Skip One In this mode, one out of four pixels is selected for readout by selecting every other line and column in the image array. The Read-One-Skip-One mode is depicted in Figure 6 below. This subsampling mode does not preserve the Bayer pattern so it is recommended for monochrome devices only. = Skip Y = Read X Figure 7. Color Subsampling (Read-2-Skip-2) Reverse Readout XGS supports reverse readout in the vertical (Y-) direction. If active_config_reg.active_reversed is set to 1, the ROIs will be read top to bottom instead of the default (active_config_reg.active_reversed = 0) bottom to top readout direction. www.onsemi.com 9 XGS Family CONFIGURATION AND PINOUT below. The recommended decoupling capacitors are listed in Table 4. TYPICAL CONFIGURATIONS Configuration Example: Two possible configuration examples are depicted in the figures below. The first example (Figure 8) uses the Four-Wire Serial Interface while the second example (Figure 9) depicts a typical Two-Wire Serial Interface implementation. Pin connections to (and from) the sensor and power supply configurations are shown in the figures * VDD_SLVS = 1.2 V (or 0.4 V); VDD = 1.2 V; VDD_IO * * = 2.8 V (or 1.8 V); VDD_PLL = 2.8 V; VAA = 2.8 V; VAA_PIX = 3.0 V; VAA_RD = 3.0 V; VAA_PIX_BST = 3.0 V 24 data lanes + 2 clock lanes www.onsemi.com 10 HiSPi (1.2 V) Analog (2.8 V) VDD_PLL VDD VDD_SLVS VAA 10k Analog (Pixel) (3.0 V) VAA_PIX_BST Digital Core (1.2 V) VAA_RD PLL (2.8 V) VAA_PIX Digital I/O (2.8 V) VDD_IO XGS Family FWSI_EN 32.4 MHz D_CLK_[2,3]_P EXTCLK 100 D_CLK_[2,3]_N RESET_N DATA_[0:23]_P 100 XGS 12000 XGS 9400 XGS 8000 CS_N SCLK To Receiver From Controller DATA_[0:23]_N SDATAOUT SDATA TRIG_INT MONITOR_0 TRIG_RD MONITOR_1 MONITOR_2 C3 C3 VDD_IO C1 C2 C3 VDD C1 C2 C3 C3 C3 C4 VDD_SLVS C1 C2 C4 C4 C4 C4 VDD_PLL C1 C4 C5 VAA C2 C1 C2 GND VAAPIX_C1 VAAPIX_C0 VAAPIX_B5 VAAPIX_B4 VAAPIX_B3 VAAPIX_B2 VAAPIX_B1 VAAPIX_B0 VAAPIX_A5 VAAPIX_A4 VAAPIX_A3 VAAPIX_A2 VAAPIX_A1 RESERVED VAAPIX_A0 N.C. C5 VAA_PIX C1 C2 VAA_PIX _BST VAA_RD C1 C2 C1 C2 Figure 8. Typical Configuration (Four-Wire Serial Interface) 1. All power supplies must be adequately decoupled (see Table 4) Decoupling. 2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and D_CLK_3 to sample data on the odd data lanes (bottom readout). 3. The active HiSPi lanes need to be terminated using 100 resistors placed as close to the receiver as possible. 4. Unused HiSPi outputs (data and/or clock lanes) must be left floating. 5. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs are not used, they must be left floating. 6. If the TRIGGER inputs are not used, tie them to GND. 7. No distinction is made between analog and digital ground (internally shorted). 8. FWSI_EN must be connected to VDD_IO through a 10 k resistor (enable Four-Wire Serial Interface). 9. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 10. Digital inputs RESET_N and CS_N are both active low. www.onsemi.com 11 Analog (2.8 V) VDD_PLL VDD VDD_SLVS VAA 1.5 K Analog (Pixel) (3.0 V) VAA_PIX_BST HiSPi (1.2 V) VAA_RD Digital Core (1.2 V) VAA_PIX PLL (2.8 V) 1.5 K Digital I/O (2.8 V) VDD_IO XGS Family From Controller SCLK SDATA D_CLK_[2,3]_P 100 D_CLK_[2,3]_N TRIG_INT DATA_[0:23]_P RESET_N To Receiver TRIG_RD 100 DATA_[0:23]_N XGS 12000 XGS 9600 XGS 8000 32.4 MHz EXTCLK MONITOR_0 MONITOR_1 MONITOR_2 N.C. RESERVED FWSI_EN N.C. SDATAOUT C1 C2 VDD C1 C2 C3 C3 C3 C4 VDD_SLVS C1 C2 C4 C4 C4 C4 VDD_PLL C1 C4 C5 VAA C2 C1 C2 GND VAAPIX_C1 VAAPIX_C0 VAAPIX_B5 VAAPIX_B4 VAAPIX_B3 VAAPIX_B2 VAAPIX_B1 VAAPIX_B0 VAAPIX_A5 VAAPIX_A4 VAAPIX_A3 C3 C3 C3 VDD_IO VAAPIX_A2 VAAPIX_A1 VAAPIX_A0 CS_N C5 VAA_PIX C1 C2 VAA_PIX _BST VAA_RD C1 C2 C1 C2 Figure 9. Typical Configuration (Two-Wire Serial Interface) 1. All power supplies must be adequately decoupled (see Table 4) Decoupling. 2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and D_CLK_3 to sample data on the odd data lanes (bottom readout). 3. The active HiSPi lanes need to be terminated using 100 resistors placed as close to the receiver as possible. 4. Unused HiSPi outputs (data and/or clock lanes) must be left floating. 5. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs are not used, they must be left floating. 6. If the TRIGGER inputs are not used, tie them to GND. 7. No distinction is made between analog and digital ground (internally shorted). 8. FWSI_EN and CS_N must be tied to GND when using the Two-Wire Serial Interface. Sdataout can be left floating. 9. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 10. Digital input RESET_N is active low. 11. ON Semiconductor recommends using a 1.5 k pull-up resistor to VDD_IO on both Sclk and Sdata. www.onsemi.com 12 XGS Family Table 4. DECOUPLING RECOMMENDATIONS Capacitor Recommended Capacitor Value (mF) Capacitor Recommended Capacitor Value (mF) C1, C5 0.1 C3 0.1 + 4.7 C2 10 C4 0.1 + 2.2 PINOUT Figure 10. XGS CLGA Package Pinout (Top View; Pads Down) www.onsemi.com 13 XGS Family PIN LIST Table 5. PIN DESCRIPTIONS (163-PIN LGA PACKAGE) Name LGA Pin Name Type Description GND A1, A18, C3, C7, C12, C16, F4, F15, G3, G16, J4, J15, K3, K16, M4, M11, M15, N8, N11, P7, P12, T3, T10, T16, V1, V18, D12, F10, G8, G9, G10, G11, P6, P13 Ground Ground VDD_PLL C10 Power PLL Power Supply VAA C5, C14, M9, M10, N3, N9, N10, N16, R5, R6, R13, R14, T9 Power Analog Supply VAA_RD C6, C13, T5, T14 Power Analog Supply for Row Driver VDD_IO C8, C9, C11, P3, P16 Power I/O Supply FWSI_EN D10 Input SDATA D11 Input/ Output Four-Wire Serial Interface (SPI): SPI Slave In Two-Wire Serial Interface (I2C): Serial Data Input/ Output VAA_PIX D5, D14, P5, P14 Power Pixel Supply VDD D6, D13, E3, E16, F7, F12, H3, H16, J7, J12, L3, L16, M7, M12 Power Digital Supply MONITOR_2 D7 Output Monitor Output 2. If unused, do not connect. MONITOR_1 D8 Output Monitor Output 1. If unused, do not connect. EXTCLK D9 Input SDATAOUT E10 Output TRIG_RD E11 Input Trigger Input for Readout Control. If unused, connect to ground. DATA_0_N E12 HiSPi Differential Data Channel [0], Negative DATA_0_P E13 HiSPi Differential Data Channel [0], Positive DATA_2_N E14 HiSPi Differential Data Channel [2], Negative DATA_2_P E15 HiSPi Differential Data Channel [2], Positive 'HIGH' -> Four-Wire Serial Interface (SPI) 'LOW' -> Two-Wire Serial Interface (I2C) External Clock Input Four-Wire Serial Interface (SPI): SPI Slave Out Two-Wire Serial Interface (I2C): Do not connect DATA_3_P E4 HiSPi Differential Data Channel [3], Positive DATA_3_N E5 HiSPi Differential Data Channel [3], Negative DATA_1_P E6 HiSPi Differential Data Channel [1], Positive DATA_1_N E7 HiSPi Differential Data Channel [1], Negative MONITOR_0 E8 Output Monitor Output 0. If unused do not connect. CS_N E9 Input Four-Wire Serial Interface (SPI): SPI Chip Select (active low) Two-Wire Serial Interface (I2C): Connect to GND TRIG_INT F11 Input Trigger Input for Integration Control. If unused, connect to ground. D_CLK_0_N F13 HiSPi Differential Clock [0], Negative D_CLK_0_P F14 HiSPi Differential Clock [0], Positive VDD_SLVS F3, F16, J3, J16, M3, M16 Power HiSPi Supply D_CLK_1_P F5 HiSPi Differential Clock [1], Positive D_CLK_1_N F6 HiSPi Differential Clock [1], Negative RESET_N F8 Input Asynchronous Hard Reset (Active Low) SCLK F9 Input Serial Interface Clock Input www.onsemi.com 14 XGS Family Table 5. PIN DESCRIPTIONS (163-PIN LGA PACKAGE) Name LGA Pin Name Type Description DATA_4_N G12 HiSPi Differential Data Channel [4], Negative DATA_4_P G13 HiSPi Differential Data Channel [4], Positive DATA_6_N G14 HiSPi Differential Data Channel [6], Negative DATA_6_P G15 HiSPi Differential Data Channel [6], Positive DATA_7_P G4 HiSPi Differential Data Channel [7], Positive DATA_7_N G5 HiSPi Differential Data Channel [7], Negative DATA_5_P G6 HiSPi Differential Data Channel [5], Positive DATA_5_N G7 HiSPi Differential Data Channel [5], Negative DATA_8_N H12 HiSPi Differential Data Channel [8], Negative DATA_8_P H13 HiSPi Differential Data Channel [8], Positive DATA_10_N H14 HiSPi Differential Data Channel [10], Negative DATA_10_P H15 HiSPi Differential Data Channel [10], Positive DATA_11_P H4 HiSPi Differential Data Channel [11], Positive DATA_11_N H5 HiSPi Differential Data Channel [11], Negative DATA_9_P H6 HiSPi Differential Data Channel [9], Positive DATA_9_N H7 HiSPi Differential Data Channel [9], Negative D_CLK_2_N J13 HiSPi Differential Clock [2], Negative D_CLK_2_P J14 HiSPi Differential Clock [2], Positive D_CLK_3_P J5 HiSPi Differential Clock [3], Positive D_CLK_3_N J6 HiSPi Differential Clock [3], Negative DATA_12_N K12 HiSPi Differential Data Channel [12], Negative DATA_12_P K13 HiSPi Differential Data Channel [12], Positive DATA_14_N K14 HiSPi Differential Data Channel [14], Negative DATA_14_P K15 HiSPi Differential Data Channel [14], Positive DATA_15_P K4 HiSPi Differential Data Channel [15], Positive DATA_15_N K5 HiSPi Differential Data Channel [15], Negative DATA_13_P K6 HiSPi Differential Data Channel [13], Positive DATA_13_N K7 HiSPi Differential Data Channel [13], Negative DATA_16_N L12 HiSPi Differential Data Channel [16], Negative DATA_16_P L13 HiSPi Differential Data Channel [16], Positive DATA_18_N L14 HiSPi Differential Data Channel [18], Negative DATA_18_P L15 HiSPi Differential Data Channel [18], Positive DATA_19_P L4 HiSPi Differential Data Channel [19], Positive DATA_19_N L5 HiSPi Differential Data Channel [19], Negative DATA_17_P L6 HiSPi Differential Data Channel [17], Positive DATA_17_N L7 HiSPi Differential Data Channel [17], Negative D_CLK_4_N M13 HiSPi Differential Clock [4], Negative D_CLK_4_P M14 HiSPi Differential Clock [4], Positive D_CLK_5_P M5 HiSPi Differential Clock [5], Positive D_CLK_5_N M6 HiSPi Differential Clock [5], Negative DATA_20_N N12 HiSPi Differential Data Channel [20], Negative DATA_20_P N13 HiSPi Differential Data Channel [20], Positive www.onsemi.com 15 XGS Family Table 5. PIN DESCRIPTIONS (163-PIN LGA PACKAGE) Name LGA Pin Name Type Description DATA_22_N N14 HiSPi Differential Data Channel [22], Negative DATA_22_P N15 HiSPi Differential Data Channel [22], Positive DATA_23_P N4 HiSPi Differential Data Channel [23], Positive DATA_23_N N5 HiSPi Differential Data Channel [23], Negative DATA_21_P N6 HiSPi Differential Data Channel [21], Positive HiSPi Differential Data Channel [21], Negative DATA_21_N N7 VAA_PIX_A0 P10 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND) VAA_PIX_A1 P11 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND) VAA_PIX_A2 R10 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND) VAA_PIX_A3 T11 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND) VAA_PIX_A4 T12 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND) VAA_PIX_A5 T6 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND) VAA_PIX_B0 P8 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND) VAA_PIX_B1 P9 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND) VAA_PIX_B2 R8 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND) VAA_PIX_B3 R9 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND) VAA_PIX_B4 T7 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND) VAA_PIX_B5 T8 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND) VAA_PIX_C0 R11 Decoupling External Noise Decoupling (0.1 F to GND) VAA_PIX_C1 T13 Decoupling External Noise Decoupling (0.1 F to GND) VAA_PIX_BST R7, R12 Power RESERVED P4, P15 N/A Pixel Booster Supply Reserved (do not connect) www.onsemi.com 16 XGS Family SENSOR STATES After Power-Up and while the RESET_N pin is driven low, the image sensor enters a RESET state until the RESET_N signal is de-asserted. Once the RESET_N pin is driven high, the sensor will start loading the default configuration, stored in the on-chip memory, into its configuration registers. As soon as sensor_status_reg (R0x3706) returns value 0xEB, the sensor passed all basic initialization steps and, while waiting for user interaction, enters a SLEEP state. While the sensor is in the SLEEP state, the registers can be programmed using the serial interface. To exit the SLEEP state and enter STANDBY mode, the reset_register_reg (R0x3700) needs to be set to 0x001C. This register upload enables all analog blocks (including the on-chip PLL) and moves the sensor state to STANDBY. When in STANDBY mode and upon user intervention the training patterns or IDLE words can be sent over the video interface allowing receiver locking. Once the host is ready to receive image data, the sensor's sequencer can be enabled. Depending on the configured operation mode, the sensor will either wait for user interaction or start grabbing images autonomously (CAPTURE). Disabling the sequencer moves the sensor state back to STANDBY. When disabling the PLL and analog blocks while in STANDBY state, the state machine will transition back to the SLEEP state. Asserting the RESET_N pin forces the sensor to enter the RESET state, regardless of the current state. The sensor state diagram is shown in Figure 11. RESET_N de-asserted -> internal initialization start R0x3706 = 0xEB?? -> Initialization complete Figure 11. Sensor State Diagram Table 6. TYPICAL TRANSITION TIMES Sensor State Transition Time Description POWER-DOWN 25 ms Time required to transition from POWER-DOWN to CAPTURE state. SLEEP 10 ms Time required to transition from SLEEP to CAPTURE state. STANDBY < 16 line times Time required to transition from STANDBY to CAPTURE state. WAIT_ON_TRIGGER 2 line times + Synchronization Delay (< 50 ns) Time required to transition from WAIT_ON_TRIGGER to CAPTURE (upon trigger action). A minimum delay of one line time will be added. www.onsemi.com 17 XGS Family POWER-UP AND POWER-DOWN SEQUENCE 9. The sensor then loads the default register values from its on-chip memory. As soon as RESET_N is pulled up (released), the sensor starts loading the default register values from it internal memory. When loading is done (sensor_status_reg R0x3706 -> 0xEB), the sensor is ready to accept user uploads. the sensor is ready to accept user uploads (e.g. to configure a special mode). 10. Enable PLL and initialize sensor's internal analog blocks (reset_register_reg = 0x001C). 11. Once the analog blocks are initialized, the sensor transitions to STANDBY state and is ready to start image operations. 12. Enable the sequencer to transition to the CAPTURE state (general_config0_reg[0] = 1). POWER-UP SEQUENCE The recommended Power-Up sequence for the XGS sensor is shown in Figure 12. The available power supplies (VDD_IO, VDD_PLL, VDD, VAA, VAA_PIX, VAA_PIX_BST, VAA_RD and VDD_SLVS) must have the separation specified below. 1. Turn on VDD_IO power supply. 2. After 0-100 s, turn on VDD_PLL power supply. 3. After 0-100 s, turn on VDD power supply. 4. After 0-100 s, turn on VAA power supply. 5. Once VAA is stable, power up VAA_PIX, VAA_PIX_BST and VAA_RD. 6. Once VAA_PIX, VAA_PIX_BST and VAA_RD are stable, power up VDD_SLVS. 7. After VDD_SLVS is stable, enable EXTCLK. 8. After EXTCLK has settled, hold RESET_N low (active) for at least 30 EXTCLK cycles before de-asserting the reset signal. EXTCLK (32.4 MHz) Figure 12. Power-Up Sequence www.onsemi.com 18 XGS Family Table 7. POWER-UP SEQUENCE Symbol Min Typ t0 VDD_IO to VDD_PLL Definition 0 (Note 5) 100 s t1 VDD_PLL to VDD 0 (Note 5) 100 s t2 VDD to VAA 0 (Note 5) 100 s t3 VAA to VAA_PIX/VAA_PIX_BST/VAA_RD 0 (Note 5) 100 s t4 VAA_PIX/VAA_PIX_BST/VAA_RD to VDD_SLVS 0 (Note 5) 100 s tX EXTCLK Settling Time 0.5 30 (Note 4) ms t5 Hard Reset 30 EXTCLK cycles t6 Internal Initialization (ready once R0x3706 reads back 0xEB) 1.5 ms t7 PLL Lock Time 10 t8 Internal Initialization 4. The EXTCLK settling time is component-dependent. 5. The minimum time does not include the settling time of the power supply. www.onsemi.com 19 Max Unit 70 s 6.5 ms XGS Family POWER-DOWN SEQUENCE 3. In STANDBY mode, activate reset by pulling down the RESET_N line for at least 30 EXTCLKs. 4. EXTCLK can be stopped 0.5 ms after RESET_N. 5. Turn off power supplies one by one. Wait at least until the supplies are stable before turning off the next supply. (reverse order of Power-Up Sequence). The recommended Power-Down sequence for the XGS sensor is shown in Figure 13. The available power supplies must have the separation specified below. 1. Disable CAPTURE if output is active by disabling the sequencer (general_config0_reg[0] = 0). 2. Issue a sensor STANDBY request (reset_register_reg[2] = 0). By default, the transition to STANDBY state happens either after completion of current row (or frame) readout or instantly (configurable). EXTCLK (32.4 MHz) Figure 13. Power-Down Sequence Table 8. POWER-DOWN SEQUENCE Symbol Definition Min Typ Max Unit t0 Hard Reset 30 EXTCLK cycles t1 Reset to Disable EXTCLK t2 VAA_RD / VAA_PIX_BST / VAA_PIX to VAA 0.5 ms 0 (Note 6) t3 VDD_SLVS to VAA_RD / VAA_PIX_BST / VAA_PIX 0 (Note 6) s s t4 VAA_RD / VAA_PIX_BST / VAA_PIX to VAA 0 (Note 6) s t5 VAA to VDD 0 (Note 6) s t6 VDD to VDD_PLL 0 (Note 6) s t7 VDD_PLL to VDD_IO 0 (Note 6) s 6. The minimum time does not include the settling time of the power supply. www.onsemi.com 20 XGS Family Line Number INTEGRATION MODES In a global shutter sensor, light integration takes place on all pixels in parallel, although subsequent readout is sequential. Figure 14 shows the integration and readout sequence for the global shutter. All pixels are light sensitive during the same period of time. Common Reset (SFOT) The whole pixel core is reset simultaneously and after the integration time all pixel values are sampled at the same time on the storage node inside each pixel. The pixel core is read out line by line after integration. Note that Figure 14 shows a configuration where integration and readout operations are not pipelined. In a pipelined configuration, integration and readout are performed simultaneously. Pipelined Global Shutter Mode In pipelined shutter mode, the integration and readout are active concurrently. Images are continuously read and integration of frame N is ongoing during readout of the previous frame N-1. The readout of every frame starts with a Frame Overhead time (EFOT), during which the analog value on the pixel diode is transferred to the pixel memory element. After the Frame Overhead Time, the sensor is read out line per line. Image array operations and readout are pipelined. The image array operations are performed in the Row Overhead Time (ROT). During the ROT sequence, an image row is selected for readout. At the start of the integration the sequencer schedules another global operation on the pixel array. This sequence is referred to as Start of integration frame overhead sequence (SFOT). During this SFOT, the readout shall be halted temporarily. Common Sample & Hold (EFOT) Progressive read, line by line (ROT + readout) Time Integration Time Burst Readout Time Figure 14. Global Shutter Operation MASTER MODE (NON-TRIGGERED) Figure 15. Master Mode (non-Triggered) Sequencer schedules the frame operations required to initiate and terminate the light integration. The integration period is started with a Start-of-Integration FOT (SFOT) sequence and is ended with an End-of-Integration FOT (EFOT) sequence. Note that both SFOT and EFOT operations take some time during which the readout will be halted. This will be reflected in an idle period on the sensor's interface. The parameters defining the frame and integration properties are listed in Table 9 below. In this operation mode, the integration time is set through the register interface and the sensor integrates and reads out the images autonomously. The sensor acquires images without any user interaction as shown in Figure 15. On a high level, the frame time consists of a non-integrating time and integration time (during which the pixels are light sensitive and integrating light). The sum of both parameters is the frame time, which is configured in multiple of line periods. Within this total frame time, the www.onsemi.com 21 XGS Family Table 9. INTEGRATION AND FRAME TIMING PARAMETERS Name Description line_time Duration of one line, expressed in logic clock cycles. The minimum line time shall be dictated by the A/D conversion time and readout time (whichever is larger). frame_length Defines the total frame time as frame_length * line_time logic clock periods. This parameter needs to be configured large enough such that both the integration control operations (i.e. SFOT, EFOT and configured integration time) and the readout operations (ROI readout + black lines) can happen. integration_coarse Defines the coarse part of the integration time. Total integration time in logic clock periods is integration_coarse * line_time + integration_fine integration_fine Defines the fine part of the integration time. Total integration time in logic clock periods is integration_coarse * line_time + integration_fine integration_offset_coarse Offset between the Sequencer induced SFOT period and the start of the SFOT, expressed in line periods. The total integration offset time, expressed in logic clock cycles, is defined as (integration_offset_coarse + overhead) * line_time. This parameter allows to increase the latency between a trigger event and the effective start of integration in triggered modes. The frame parameters and their relations are depicted in Figure 16 below. Note that the green area depicts the readout of regular lines (black reference / ROI defined image lines), while the grey area represents the access to dummy lines (no image data). The shaded green part represents the line periods during which the control and datapath pipeline is flushed. Minimum integration time limitations are listed in Table 10. EE EE Figure 16. Frame Timing and Exposure Parameters www.onsemi.com 22 XGS Family MASTER MODE (TRIGGERED) Figure 17. Master Mode (Triggered) edge on the synchronization pin does not have any impact on the readout or integration and subsequent frames are started again for each rising edge. Figure 18 below shows the pipelined operation in triggered master mode (i.e. trigger assertion during frame readout). In Triggered Master Mode, a rising edge on the TRIG_INT pin is used to trigger the start of integration as shown in Figure 17. The integration time is defined by register configuration (integration_coarse, integration_fine). The sensor shall autonomously integrate during this predefined time, after which the EFOT operation starts and the image array is read out sequentially. A falling EE Figure 18. Integration Control in Triggered Master Mode * The response time between a rising edge of TRIG_INT Note that each trigger reads out only one image. The latency between a trigger event and the start of the SFOT operation is constant and predictable. It is defined by the coarse offset configuration + overhead. NOTES: * The trigger is an asynchronous signal which is synchronized in the SCU. As a consequence, synchronization jitter can be observed. * The polarity of the TRIG_INT pin is controlled by trig_int_polarity. The operation described above corresponds to trig_int _polarity = `0'. and the start of integration is fixed, besides the synchronization uncertainty and jitter. The following register is not used in this mode and has no influence (implicitly defined by the trigger): * frame_length Minimum integration time limitations are listed in Table 10. www.onsemi.com 23 XGS Family SLAVE MODE (TRIGGERED) Figure 19. Slave Mode (Triggered) The slave mode depicted in Figure 19 adds more manual control to the sensor. The integration time registers (frame_length and integration) are ignored in this mode and the integration time is rather controlled by an external pin. As soon as the control pin is asserted, the Sequencer schedules the SFOT operations. The integration continues until the external pin is deasserted by the user/system. Now, the image is sampled and the readout is initiated. EE EE Figure 20. Integration Control in Slave Mode (Triggered) * The following registers are not used in this mode and The latency between the trigger events and the SFOT/EFOT operations respectively is fixed and predictable. The latency between a trigger assertion and the SFOT operation is controlled through integration_offset_coarse. NOTES: * The trigger is an asynchronous signal which is synchronized in the Sequencer. As a consequence, synchronization jitter can be observed. * The response time between a TRIG_INT event and the start/end of integration shall be constant, besides the synchronization uncertainty and jitter. do not have any influence (implicitly defined by the trigger): integration_coarse, integration_fine, frame_length Minimum integration time limitations are listed in Table 10 below. www.onsemi.com 24 XGS Family Table 10. MINIMUM INTEGRATION TIME LIMITATIONS (Note 7) Minimum Integration Time (in ms) Number of Output Lanes Non-Triggered Triggered 6 10 60 12 10 30 24 10 20 7. The minimum integration time depends on the configured line time. The values in this table assume the minimum recommended line time is used. 8. Refer to the XGS 12000 Developer Guide for more information on the minimum integration times. www.onsemi.com 25 XGS Family READOUT MODES By default, the readout of the pixel array does not require any user interaction. The sequencer initiates the readout as soon as integration ends and the entire readout is done autonomously. This is the default readout mode. Optionally, the frame readout can be controlled externally. This requires configuring the TRIG_RD input as a frame or line trigger. Table 11 below lists the parameters that control the triggered readout operation. Table 11. TRIGGERED READOUT PARAMETERS Register Name Description frame_trigger_en Start the frame readout upon assertion of TRIG_RD when enabled. This configuration has priority over line_trigger_en. frame_trigger_mode Only valid for frame triggered readout modes. `0': Regular frame triggered mode: The sensor starts the readout of one frame upon a rising trigger edge `1': The sequencer continues frame grabbing as long as the trigger is asserted. line_trigger_en Start the readout of one line upon assertion of TRIG_RD when enabled. Only one line is read out for each trigger assertion. Note that contexts_reg.frames determines how many frames can be read out. This implies that the sequencer will not accept any new trigger once the number of contexts_reg.frames have been read out. If this is not desired, frames should be configured to 0. FRAME TRIGGERED READOUT Frame N Exposure State EFOT Idle Reset Frame N + 1 Integrating EFOT Idle Reset Integrating EFOT TRIG_INT (No effect on falling edge ) TRIG_RD Readout EFOT SFOT EFOT integration length SFOT EFOT integration length = Start of New Line = Readout Figure 21. Frame Triggered Readout Mode XGS 12000 supports two frame triggered readout options, configurable in the frame_trigger_mode register (refer to Table 11). frame_trigger_mode = 1 In this mode, the trigger acts as an external sequencer enable signal. An event (rising or falling depending on the configured polarity) starts the frame readout. After this first frame, the sequencer continues running, cycling through the active contexts, if more than one context is enabled. The end condition depends on the value given in contexts_reg.frames: * contexts_reg.frames > 0: The Sequencer continues running and reads out the given amount of frames, after which it returns to the WAIT_ON_TRIGGER state. After the readout, the sequencer is waiting for another trigger, after which a new sequence is initiated. Note that a new batch of frames shall be read out in case the trigger is asserted at the end of the previous batch. * contexts_reg.frames = 0: The Sequencer continues running as long as the TRIG_RD is asserted. Once the trigger is deasserted, the Sequencer returns to the frame_trigger_mode = 0 In a global shutter mode, the integration is ended by the EFOT. In a non-triggered readout mode, the readout is initiated automatically after the EFOT operations. In frame triggered mode, the Sequencer will not start the readout, but instead it waits until the frame-trigger gets asserted. Once an event (rising of falling depending on the configured polarity) is detected the readout starts and the image is read out line after line. Note that the trigger assertion is latched and served at the first coming internal new line reference (internal time base). As a consequence one may observe a trigger latency up to a line time. Frame triggered readout can be combined with triggered integration modes. www.onsemi.com 26 XGS Family WAIT_ON_TRIGGER state, in which it is ready to accept a new trigger event. Note that this mode is available for both triggered and non-triggered global shutter modes and it can be combined with the use of multiple contexts. When using multiple contexts it is also possible to configure the number of desired frames per context. The sequencer cycles through the active contexts and generates as many frames as configured per context. When retriggered, the sequencer reinitializes the frame properties and starts the readout from a fresh state (i.e. does not continue from where it ended in the previous batch). LINE TRIGGERED READOUT Frame N Exposure State EFOT Idle Frame N+1 Reset Integrating EFOT Idle Reset Integrating EFOT TRIG_INT (No effect on falling edge) TRIG_RD Readout EFOT EFOT SFOT SFOT EFOT integration length = Start of New Line = Readout Figure 22. Line Triggered Readout register or the sequencer can take control. If programmed, the sequencer will cycle through two or three contexts sequentially as depicted in Figures 23 and 24. * Two Context Switching (context_reg.active_contexts = 0x3) context 0 context 1 context 0... The line triggered readout mode is enabled when line_trigger_en is asserted and frame_trigger_en is deasserted. The line triggered readout mode is comparable to frame triggered readout, but in this mode only one line is read out for each trigger. Note that a trigger is latched and interpreted during the following line period if the sensor is retriggered during readout. Line triggered readout is to be used in conjunction with triggered integration modes. Context 0 Features Overview The XGS family has a wide array of features to enhance functionality or to increase versatility. A summary of features follows. Context 1 Figure 23. Two Context Switching RESET The RESET_N input (pin F8) is an active low control input for asynchronous hard reset. During the power-up period, RESET_N must be asserted, then must be deasserted after the power supplies are settled. The minimum RESET_N assert time is 30 EXTCLK cycles. * Three Context Switching (context_reg.active_contexts = 0x7) context 0 context 1 context 2 context 0... Context 0 MONITOR OUTPUTS The XGS sequencer provides three monitor outputs (pins E8, D8 and D7) which can be used to monitor the internal states of the sequencer. The monitor signals can be configured separately for each monitor output. Context 1 CONTEXT SWITCHING XGS supports up to three contexts which allow the user to program a number of configurations and let the sensor cycle through these. Switching from one context to another is done at the start of a frame and cannot corrupt the ongoing readout. The registers that control the switching are grouped in the contexts_reg. The active context switching can be done manually by changing the value in the active_contexts Context 2 Figure 24. Three Context Switching * Multiple Frame Context Switching In addition to defining up to three contexts, the number www.onsemi.com 27 XGS Family of frames per context can be configured for each context separately. In the example configuration depicted in Figure 25, the sensor first generates three frames using context 0 settings followed by a single context 1 frame and two context 2 frames. The sensor loops through this sequence until the sequencer is disabled. The number of frames per context switch is configured in contexts_reg.frames_ctxt0 (for context0). 3 x context 0 context 1 2 x context 2 3 x context 0... in steps of 1/32 (64 steps) and its configuration can be represented by the equation below: Digital gain + Dg_factor2 5 (eq. 1) COMPANDING MODE The companding mode can be used to compress 12-bit pixel data into 10-bit values. The line time remains the time required to convert a 12-bit ADC sample; gain is only achieved when, due to lane multiplexing, the system becomes I/O limited. In that situation, being able to send out 12-bit pixels using only 10 bits, can be useful to boost the frame rate. When companding mode is enabled, the precision of the digital output is 1 Least Significant Bit (LSB) in the low light area, but towards the upper region, the granularity gradually increases to 2, 4, and 8 LSBs as shown in Figure 26. In all cases the ADC quantization steps will be less than the photon shot noise performance of the pixel. Context 0 Context 0 Context 0 ADC Granularity (Bits) Context 1 Context 2 Context 2 Figure 25. Multiple Frame Context Switching 8 4 2 1 0 TEST PATTERN The XGS sensor has the capability of injecting a number of test patterns into the datapath. As the test pattern generator is placed at the beginning of the digital datapath, it can be used to check the functions of the digital blocks or to test the frame grabber or receiver operation. The test patterns can be configured in the test_pattern_mode_reg.test_pattern_mode and only one pattern can be activated at a given point in time. 256 512 1024 2048 4095 Signal (ADU) Figure 26. ADC Granularity - Companding Mode FRAME RATE Assuming the readout of a frame takes longer than the integration, the frame rate can be influenced by changing one or more of the following parameters: * Vertical resolution (number of lines in ROI) * Number of data output lanes (24 / 18 / 12 / 6) or mux mode (4:4 / 4:3 / 4:2 / 4:1) The frame rate scales linearly with the number of lines (vertical direction) but not with the number of columns (horizontal direction) due to the column ADC architecture. Using the sensor with a reduced number of data lanes will lower the frame rate. Alternatively, the frame time can be configured through line_time and frame_time. The line time should be large enough in order to process a full line and the frame time should be configured such that at least all ROIs can be read out and that the maximum integration can be scheduled in. When one of the two conditions are violated the sensor gives either priority to the readout or the integration (int_priority). DATA PEDESTAL The data pedestal is a constant offset that is added to the pixel values at the end of the datapath. The pedestal or offset value can be configured separately for each color channel (GR, GB, R and B) and for each context. The offset is a 12-bit value. GAIN STAGES Analog Gain A column-based analog gain of 1x, 2x or 4x can be applied to the output signal. Digital Gain As opposed to the analog gain stage, the digital gain can be configured to separate levels for each color channel (GR, GB, R and B). The digital gain factor ranges from 1/32 to 2 www.onsemi.com 28 XGS Family * 4:3 multiplexing: four datapath lanes are multiplexed to LANE MULTIPLEXING The lane multiplexing function can be used to reduce the number of output data lanes and thus the output data rate. This can be useful in case the receiver cannot accept all 24 data lanes or the backend is unable to process the sensor's full data rate. The sensor has one multiplexer for each PHY; six in total. Each multiplexer connects 4 datapath outputs to one PHY and can be configured to distribute the data from the 4 datapath inputs over either 1, 2, 3 or 4 outputs; i.e. the sensor supports 4 multiplexing schemes: * 4:4 multiplexing: no multiplexing; each datapath lane is connected to a HiSPi lane (total of 24 lanes). three HiSPi lanes (total of 18 lanes). * 4:2 multiplexing: four datapath lanes are multiplexed to two HiSPi lanes (total of 12 lanes). * 4:1 multiplexing: four datapath lanes are multiplexed to a single HiSPi lane (total of 6 lanes). The four different multiplexing schemes are illustrated in Figures 27 to 30. The pixel readout order for each multiplexing mode is depicted in Figures 31 to 34. time DATAPATH_0 DATA_0 DATAPATH_1 DP0(t0) ... DP 0(t1) DATAPATH_0 DP1(t0) ... DP1(t1) DATA_1 4:3 Multiplexer DP2(t0) ... DP2(t1) DATA_2 DATA_2 DP2(t0) ... DP1(t1) Figure 28. 4:3 Multiplexing (18 Lanes) DATAPATH_0 time DATA_0 DP1(t0) ... DP0(t1) DATAPATH_3 Figure 27. 4:4 Multiplexing (24 Lanes) DATAPATH_0 DATA_1 DATAPATH_2 DP3(t0) ... DP3(t1) DATA_3 DATAPATH_3 DP0(t0) ... DP 3(t0) DATAPATH_1 4:4 Multiplexer DATAPATH_2 time DATA_0 DP0(t0) ... DP 2(t0) DATAPATH_1 time DATAPATH_1 4:2 Multiplexer 4:1 Multiplexer DATAPATH_2 DATA_0 DP0(t0) ... DP 1(t0) ... ...DP2(t0) ... DP 3(t0) DATAPATH_2 DATA_1 DP1(t0) ... DP3(t0) DATAPATH_3 DATAPATH_3 Figure 29. 4:2 Multiplexing (12 Lanes) Figure 30. 4:1 Multiplexing (6 Lanes) Table 14 lists the active data lanes in function of the multiplexing scheme. As depicted in Table 14, HiSPi lane 0 is the lane that is always active, regardless of the selected multiplex scheme. Table 12. ACTIVE DATA LANES IN PHY0 IN FUNCTION OF MUX MODE NOTE: Mux Mode Lane_0 Lane_2 Lane_4 Lane_6 4:4 X X X X 4:3 X X X 4:2 X X 4:1 X Lane usage is illustrated using the first four lanes only (i.e. for a single PHY). www.onsemi.com 29 XGS Family 698 1046 4 1044 2 350 0 348 696 DATA_2 time DATA_4 DATA_6 Figure 31. Column Output with 4:4 Multiplexing ... 352 2 698 1046 1044 2 350 696 696 1044 348 0 348 0 DATA_2 DATA_0 time ... 4 DATA_0 Figure 32. Column Output with 4:3 Multiplexing ... time 1048 1044 DATA_4 DATA_0 700 1046 696 DATA_2 time ... 1048 698 348 ... 700 350 ... 352 352 ... 0 ... 2 ... ... 4 Figures 31 to 34. The numbers in the squares represent the actual column address in the pixel array. DATA_0 The data output on each lane within a single PHY, depending on the multiplexing scheme, is represented in Figure 33. Column Output with 4:2 Multiplexing Figure 35 shows on which output lane columns are sent in case a row with an even address is read and the sensor is configured to have GR and GB pixels sent out on top (even Figure 34. Column Output with 4:1 Multiplexing numbered lanes) and R and B pixels to the bottom (odd numbered lanes). Figure 36 shows the column output in case a row with an odd address is read. www.onsemi.com 30 DATA _0 (GR) SYNC SOF 1, 3, 5... 345, 347 EOL BLANK DATA _1 (R) SYNC SOF 0, 2, 4... 344, 346 EOL BLANK DATA _2 (GR) SYNC SOF 349, 351, 353... 693, 695 EOL BLANK SOF ` 348, 350, 352... 692, 694 EOL BLANK DATA _3 (R) SYNC ... ... ... ... ... ... EVEN ROW XGS Family DATA _22 (GR) SYNC SOF ... 4173, 4175 EOL BLANK DATA _23 (R) SYNC SOF ... 4172, 4174 EOL BLANK DATA _0 (GB) SYNC SOF 0, 2, 4... 344, 346 EOL BLANK DATA _1 (B) SYNC SOF 1, 3, 5... 345, 347 EOL BLANK DATA _2 (GB) SYNC SOF 348, 350, 352... 692, 694 EOL BLANK DATA _3 (B) SYNC SOF ` 349, 351, 353... 693, 695 EOL BLANK ... ... ... ... ... ... ODD ROW Figure 35. Column Output Sequence (Even Row Address) DATA _22 (GB) SYNC SOF ... 4172, 4174 EOL BLANK DATA _23 (B) SYNC SOF ... 4173, 4175 EOL BLANK Figure 36. Column Output Sequence (Odd Row Address) Figure 37. Pixel Readout Order (24 Lanes) www.onsemi.com 31 XGS Family SENSOR CONTROL INTERFACE The sensor's configuration registers are accessible through either the Two-Wire (I2C) or Four-Wire (SPI) Serial Interface. At the cost of speed, the two-wire serial interface can be considered as a simple and cost-efficient alternative to the faster, but more complex, four-wire serial interface. The four-wire serial interface is recommended for applications requiring fast and frequent sensor (re-)configuration. As shown in Figure 38 below, the type of user interface can be selected through the external FWSI_EN pin (`LOW' = two-wire, `HIGH' = four-wire). VDD_IO 1.5 K 10 K 1.5 K VDD_IO N.C. SCLK FWSI_EN SDATA (I/O) CS_N SDATAOUT SCLK CS_N SDATA FWSI_EN SDATAOUT Two-Wire Four-Wire Figure 38. Serial Interface Selection TWO-WIRE SERIAL INTERFACE bus is released with a stop condition. Only the master can generate the start and stop conditions. The two-wire serial interface bus enables read/write access to control and status registers within the sensor. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5 k resistor. Either the slave or master device can drive SDATA LOW - the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the sensor uses SCLK as an input only and therefore never drives it LOW. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a "repeated start" or "restart" condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: * a (repeated) start condition * a slave address/data direction byte * an (a no) acknowledge bit * a message byte * a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A '0' in bit [0] indicates a WRITE, and a '1' indicates a READ. The default slave addresses used by the sensor are 0x20 (write address) and 0x21 (read address). www.onsemi.com 32 XGS Family place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Single READ from Random Location This sequence (Figure 39) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 39 shows how the internal register address maintained by the sensor is loaded and incremented as the sequence proceeds. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a '0' indicates a write and a '1' indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take Previous Reg Address, N S Slave Ad- dress 0A S = Start Condition P = Stop Condition Sr = Restart Condition A = Acknowledge A = No-acknowledge Reg Address[15:8] A Reg Address, M Reg Address[7:0] A Sr Slave Address 1 A M+1 Read Data A P Slave to Master Master to Slave Figure 39. Single READ from Random Location Single READ from Current Location master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. This sequence (Figure 40) performs a read using the current value of the sensor's internal register address. The Previous Reg Address, N S Slave Address 1 A Read Data Reg Address, N+1 A P S Slave Address 1A Figure 40. Single READ from Current Location www.onsemi.com 33 N+2 Read Data A P XGS Family Sequential READ, Start from Random Location has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. This sequence (Figure 41) starts in the same way as the single READ from random location (Figure 39). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data A Reg Address[7:0] M+2 A Read Data Reg Address, M M+3 A Sr Slave Address M+L-2 A 1 A M+1 Read Data M+L-1 Read Data A Read Data A M+L A P Figure 41. Sequential READ, Start from Random Location Sequential READ, Start from Current Location has been transferred, the master generates an acknowledge bit and continues to perform byte READS until `L' bytes have been read. This sequence (Figure 42) starts in the same way as the single READ from current location (Figure 40). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 1 A N+1 Read Data A N+2 Read Data A Read Data N+L-1 A N+L Read Data A P Figure 42. Sequential READ, Start from Current Location Single WRITE to Random Location then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. This sequence (Figure 43) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] Reg Address, M A Reg Address[7:0] A Figure 43. Single WRITE to Random Location www.onsemi.com 34 Write Data M+1 A A P XGS Family Sequential WRITE, Start at Random Location has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until `L' bytes have been written. The WRITE is terminated by the master generating a stop conditions. This sequence (Figure 44) starts in the same way as the single WRITE to random location (Figure 43). Instead of generating a no-acknowledge bit after the first byte of data Previous Reg Address, N S Slave Address 0A M+1 Write Data Reg Address[15:8] A M+2 A Write Data Reg Address, M Reg Address[7:0] A Write Data M+L-2 M+3 A Write Data 35 A M+L-1 A Figure 44. Sequential WRITE, Start at Random Location www.onsemi.com M+1 Write Data M+L A A P XGS Family FOUR-WIRE SERIAL INTERFACE sends a 15-bit register address followed by a single read/write bit. If the read/write bit is set to 1, the slave reads the 16-bit data stored at the specified register address and returns it to the master over the SDATAOUT line. A single SPI read operation is shown in Figure 45. In case the read/write bit is set to `0', the master sends another 16 bits of data for the slave to write to the previously specified register address. A single SPI write transaction is depicted in Figure 46. Both address and register data is sent serially and synchronous to the SCLK. A single SPI transaction consists of 32 bits. In order to speed up the SPI communication, a 32 sequential read and write is possible. The sequential register access is illustrated in Figure 47 and 48. The sensor's configuration registers are accessible through a Four-Wire or Serial Peripheral Interface (SPI). The SPI is a full-duplex, synchronous interface and uses four wires: * CS_N: Chip Select (active low) * SCLK: Serial Input Clock * SDATA: Serial Data Input * SDATAOUT: Serial Data Output The SPI interface uses a master-slave setup in which the sensor is the slave. Every read or write access is initiated by the master by pulling down the CS_N line. The master then Figure 45. Single SPI Read Figure 46. SPI Single Write Figure 47. SPI Sequential Read Figure 48. SPI Sequential Write www.onsemi.com 36 XGS Family ELECTRICAL SPECIFICATIONS Unless stated otherwise, the following specifications apply to the following conditions: VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 1.2 V; EXTCLK = 32.4 MHz; TA = 25C; TWO-WIRE SERIAL REGISTER INTERFACE The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 49 and Table 13. SDATA tLOW tf tSU;DAT tr tf tHD;STA tBUF tr SCLK tHD;STA tHD;DAT S tHIGH tSU;STA tSU;STO Sr P S NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Figure 49. Two-Wire Serial Bus Timing Parameters Table 13. TWO-WIRE SERIAL BUS CHARACTERISTICS Standard Mode Fast-Mode Symbol Min Max Min Max Unit fSCL 0 100 0 400 kHz tHD;STA 4.0 * 0.6 * s LOW Period of the SCLK Clock tLOW 4.7 * 1.3 * s HIGH Period of the SCLK Clock tHIGH 4.0 * 0.6 * s Set-up Time for a Repeated START Condition tSU;STA 4.7 * 0.6 * s Data Hold Time tHD;DAT 0 (Note 12) 3.45 (Note 13) 0 (Note 14) 0.9 (Note 13) s Data Set-up Time tSU;DAT 250 * 100 (Note 14) * ns Rise Time of both SDATA and SCLK Signals tr * 1000 20 + 0.1Cb (Note 15) 300 ns Fall Time of both SDATA and SCLK Signals tf * 300 20 + 0.1Cb (Note 15) 300 ns tSU;STO 4.0 * 0.6 * s tBUF 4.7 * 1.3 * s Cb * 400 * 400 pF CIN_SI * 3.3 * 3.3 pF Parameter SCLK Clock Frequency Hold Time (Repeated) START Condition Set-up Time for STOP Condition Bus Free Time between a STOP and START Condition Capacitive Load for each Bus Line Serial Interface Input Pin Capacitance SDATA Max Load Capacitance SDATA Pull-up Resistor CLOAD_SD * 30 * 30 pF RSD 1.5 4.7 1.5 4.7 k 9. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 10. Two-wire control is I2C-compatible. 11. All values referred to VIHmin = 0.9 VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXTCLK = 32.4 MHz. 12. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 13. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 14. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C-bus specification) before the SCLK line is released. 15. Cb = total capacitance of one bus line in pF. www.onsemi.com 37 XGS Family FOUR-WIRE SERIAL INTERFACE and SDATAOUT) are shown in Figures 50, 51 and 55. The timing parameters are listed in Table 14. The electrical characteristics of the of the Serial Peripheral Interface (SPI) or Four-Wire interface (CS_N, SCLK, SDATA tST CS_N tHD 0.2 x VDD_IO SCLK 0.7 x VDD_IO 0.5 x VDD_IO 1 / fSCLK Figure 50. SPI Timing Diagram - Chip Select SCLK SDATA tDT 0.2 x VDD_IO 0.7 x VDD_IO 0.2 x VDD_IO Figure 51. SPI Timing Diagram - Data Input tST SCLK tHD 0.7 x VDD_IO 0.2 x VDD_IO 0.7 x VDD_IO SDATAOUT 0.2 x VDD_IO Figure 52. SPI Timing Diagram - Data Output www.onsemi.com 38 XGS Family Table 14. SPI TIMING PARAMETERS Parameter Symbol Min Typ Max Unit SPI Read Frequency (PLL disabled / PLL enabled) fSCLK 3.5 / 6.1 MHz SPI Write Frequency (PLL disabled / PLL enabled) fSCLK 12.5 / 25 MHz Setup Time tST (1/fSCLK)*0.1 Hold Time tHD (1/fSCLK)*0.1 Transfer Delay Time tDT ns ns (1/fSCLK)*0.5 ns I/O TIMING External Clock tR tF 80% 50% 20% duty Figure 53. External Clock Timing Table 15. EXTERNAL CLOCK SPECIFICATIONS Parameter Name Min Typ Max Unit EXTCLK 29 (Note 16) 32.4 36 (Note 16) MHz Duty Cycle Duty 45 50 55 % Jitter Clock Frequency Jitter - - 100 ps Rise Time TR - - 5 ns Fall Time TF - - 5 ns 16. Any deviation from the typical EXTCLK frequency needs to be compensated by reconfiguring the internal PLL (guidelines available upon request). Trigger Input tR tF 80% 50% 20% width Figure 54. Trigger Input Pulse Timing Table 16. TRIGGER INPUT PULSE SPECIFICATIONS Parameter Symbol Min Typ Max Unit width 100 - - ns Rise Time TR - - 5 ns Fall Time TF - - 5 ns Pulse Width www.onsemi.com 39 XGS Family DC ELECTRICAL CHARACTERISTICS The DC electrical characteristics of the XGS 12000/8000 sensor are listed in Tables 17 through 28. Table 17. DC ELECTRICAL CHARACTERISTICS Symbol Definition Condition Min Typ Max Unit VDD Core Digital Voltage 1.1 1.2 1.3 V VDD_IO I/O Digital Voltage VAA Analog Voltage 1.7 / 2.7 1.8 / 2.8 1.9 / 2.9 V 2.7 2.8 2.9 V VAA_PIX Pixel Supply Voltage 2.9 3 3.1 V VAA_PIX_BST Pixel Booster Supply 2.9 3 3.1 V VAA_RD Row Driver Supply 2.9 3 3.1 V VDD_SLVS HiSPi Supply Voltage 0.3 / 1.1 0.4 / 1.2 0.5 / 1.3 V VDD_PLL PLL Supply Voltage 2.7 2.8 2.9 V VIH Input HIGH Voltage VDD_IO * 0.7 - VDD_IO + 0.5 V VIL Input LOW Voltage -0.5 - VDD_IO * 0.3 V VOH Output HIGH Voltage VDD_IO - 0.3 - - V VOL Output LOW voltage - - 0.4 V Dedicated Power Supply VDD_IO = 2.8V CAUTION: Stresses greater than those listed in Table 18 below may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 18. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit ABS VDD_SLVS ABS Rating for 0.4 V/1.2 V Supply -0.5 1.5 V ABS VDD ABS Rating for 1.2 V Supply -0.5 1.5 V ABS VDD_IO ABS Rating for 1.8 V/2.8 V Supply -0.5 3.2 V ABS VDD_PLL ABS Rating for 2.8 V Supply -0.5 3.2 V ABS VAA ABS Rating for 2.8 V Supply -0.5 3.2 V ABS VAA_PIX, VAA_RD, VAA_PIX_BST ABS Rating for 3.0 V Supply -0.5 3.6 V TSTG ABS Storage Temperature Range -40 +150 C 85 %RH ABS Storage Humidity Range at 85C Electrostatic Discharge (ESD) (ANSI / ESDA / JEDEC Standard) Human Body Model (HBM): JS-001-2014 2000 Charged Device Model (CDM): JS-002-2014 500 LU Latch-Up: JESD-78 100 V mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 17. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 18. Operating ratings are conditions in which operation of the device is intended to be functional. 19. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625 A. Refer to (AN52561/D). Long term exposure toward the maximum storage temperature will accelerate color filter degradation. 20. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can absorb moisture if the sensor is placed in a high % RH environment. www.onsemi.com 40 XGS Family Table 19. OPERATING CURRENT CONSUMPTION (XGS 12000-X1) (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Symbol IDD IDD_IO IAA IAA_PIX IAA_PIX_BST IAA_RD IDD_SLVS IDD_PLL Parameter Condition Min Typ Max Unit Digital Operating Current 90 fps @ 4096 x 3072 Resolution - 180 240 mA I/O Digital Operating Current 90 fps @ 4096 x 3072 Resolution - 5 10 mA Analog Operating Current 90 fps @ 4096 x 3072 Resolution - 140 180 mA Pixel Supply Current 90 fps @ 4096 x 3072 Resolution - 25 40 mA Pixel Booster Supply Current 90 fps @ 4096 x 3072 Resolution - 15 35 mA Row Driver Supply Current 90 fps @ 4096 x 3072 Resolution - 0 10 mA HiSPi Supply Current 90 fps @ 4096 x 3072 Resolution - VDD_SLVS = 0.4 / 1.2 V - PLL Supply Current 90 fps @ 4096 x 3072 Resolution - 65 / 120 85 / 150 10 20 mA mA Table 20. OPERATING CURRENT CONSUMPTION (XGS 12000-X3) (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Symbol IDD IDD_IO IAA IAA_PIX IAA_PIX_BST IAA_RD IDD_SLVS IDD_PLL Parameter Condition Min Typ Max Unit Digital Operating Current 28 fps @ 4096 x 3072 Resolution - 125 240 mA I/O Digital Operating Current 28 fps @ 4096 x 3072 Resolution - 5 10 mA Analog Operating Current 28 fps @ 4096 x 3072 Resolution - 65 180 mA Pixel Supply Current 28 fps @ 4096 x 3072 Resolution - 10 40 mA Pixel Booster Supply Current 28 fps @ 4096 x 3072 Resolution - 20 35 mA Row Driver Supply Current 28 fps @ 4096 x 3072 Resolution - 0 10 mA HiSPi Supply Current 28 fps @ 4096 x 3072 Resolution - VDD_SLVS = 0.4 / 1.2 V - PLL Supply Current 28 fps @ 4096 x 3072 Resolution - 60 / 115 85 / 150 10 20 mA mA Table 21. OPERATING CURRENT CONSUMPTION (XGS 9400-X1) (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Symbol IDD IDD_IO IAA IAA_PIX IAA_PIX_BST IAA_RD IDD_SLVS IDD_PLL Min Typ Max Unit Digital Operating Current Parameter 90 fps @ 3072 x 3072 Resolution Condition - 180 240 mA I/O Digital Operating Current 90 fps @ 3072 x 3072 Resolution - 5 10 mA Analog Operating Current 90 fps @ 3072 x 3072 Resolution - 140 180 mA Pixel Supply Current 90 fps @ 3072 x 3072 Resolution - 25 40 mA Pixel Booster Supply Current 90 fps @ 3072 x 3072 Resolution - 15 35 mA Row Driver Supply Current 90 fps @ 3072 x 3072 Resolution - 0 10 mA HiSPi Supply Current 90 fps @ 3072 x 3072 Resolution (VDD_SLVS = 0.4 / 1.2 V) - PLL Supply Current 90 fps @ 3072 x 3072 Resolution - www.onsemi.com 41 65 / 120 85 / 150 10 20 mA mA XGS Family Table 22. OPERATING CURRENT CONSUMPTION (XGS 9400-X2) (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Symbol IDD IDD_IO IAA IAA_PIX IAA_PIX_BST IAA_RD IDD_SLVS IDD_PLL Parameter Condition Min Typ Max Unit Digital Operating Current 56 fps @ 3072 x 3072 Resolution - 145 240 mA I/O Digital Operating Current 56 fps @ 3072 x 3072 Resolution - 5 10 mA Analog Operating Current 56 fps @ 3072 x 3072 Resolution - 100 180 mA Pixel Supply Current 56 fps @ 3072 x 3072 Resolution - 20 40 mA Pixel Booster Supply Current 56 fps @ 3072 x 3072 Resolution - 20 35 mA Row Driver Supply Current 56 fps @ 3072 x 3072 Resolution - 0 10 mA HiSPi Supply Current 56 fps @ 3072 x 3072 Resolution (VDD_SLVS = 0.4 / 1.2 V) - PLL Supply Current 56 fps @ 3072 x 3072 Resolution - 60 / 115 85 / 150 10 20 mA mA Table 23. OPERATING CURRENT CONSUMPTION (XGS 8000-X1) (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Symbol IDD IDD_IO IAA IAA_PIX IAA_PIX_BST IAA_RD IDD_SLVS IDD_PLL Min Typ Max Unit Digital Operating Current Parameter 128 fps @ 4096 x 2160 Resolution Condition - 180 240 mA I/O Digital Operating Current 128 fps @ 4096 x 2160 Resolution - 5 10 mA Analog Operating Current 128 fps @ 4096 x 2160 Resolution - 140 180 mA Pixel Supply Current 128 fps @ 4096 x 2160 Resolution - 25 40 mA Pixel Booster Supply Current 128 fps @ 4096 x 2160 Resolution - 20 35 mA Row Driver Supply Current 128 fps @ 4096 x 2160 Resolution - 0 10 mA HiSPi Supply Current 128 fps @ 4096 x 2160 Resolution - VDD_SLVS = 0.4 / 1.2 V - PLL Supply Current 128 fps @ 4096 x 2160 Resolution - 65 / 125 85 / 150 10 20 mA mA Table 24. OPERATING CURRENT CONSUMPTION (XGS 8000-X2) (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Symbol IDD IDD_IO IAA IAA_PIX IAA_PIX_BST IAA_RD IDD_SLVS IDD_PLL Parameter Condition Min Typ Max Unit Digital Operating Current 80 fps @ 4096 x 2160 Resolution - 145 240 mA I/O Digital Operating Current 80 fps @ 4096 x 2160 Resolution - 5 10 mA Analog Operating Current 80 fps @ 4096 x 2160 Resolution - 100 180 mA Pixel Supply Current 80 fps @ 4096 x 2160 Resolution - 20 40 mA Pixel Booster Supply Current 80 fps @ 4096 x 2160 Resolution - 20 35 mA Row Driver Supply Current 80 fps @ 4096 x 2160 Resolution - 0 10 mA HiSPi Supply Current 80 fps @ 4096 x 2160 Resolution - VDD_SLVS = 0.4 / 1.2 V - 60 / 115 85 / 150 mA PLL Supply Current 80 fps @ 4096 x 2160 Resolution - 10 20 mA www.onsemi.com 42 XGS Family Table 25. STANDBY CURRENT CONSUMPTION (VAA_PIX = VAA_PIX_BST = VAA_RD = 3.0 V; VAA = VDD_PLL = 2.8 V; VDD_IO = 1.8 V; VDD = 1.2 V; VDD_SLVS = 0.4 V / 1.2 V; TA = 25C) Condition Min Typ Max Unit VDD_SLVS (0.4 V / 1.2 V) - 75 / 135 - A VDD (1.2 V) - 170 - A VDD_IO (1.8 V) - 5 - A VDD_PLL (2.8 V) - 10 - A VAA (2.8 V) - 130 - A VAA_PIX (3.0 V) - 25 - A VAA_PIX_BST (3.0 V) - 30 - A VAA_RD (3.0 V) - 5 - A VDD_SLVS (0.4 V / 1.2 V) - 75 / 135 - A VDD (1.2 V) - 170 - A VDD_IO (1.8 V) - 5 - A VDD_PLL (2.8 V) - 10 - A VAA (2.8 V) - 20 - A VAA_PIX (3.0 V) - 0 - A VAA_PIX_BST (3.0 V) - 15 - A VAA_RD (3.0 V) - 0 - A VDD_SLVS (0.4 V / 1.2 V) - 55 / 100 - A VDD (1.2 V) - 40 - A VDD_IO (1.8 V) - 5 - A VDD_PLL (2.8 V) - 0 - A VAA (2.8 V) - 0 - A VAA_PIX (3.0 V) - 0 - A VAA_PIX_BST (3.0 V) - 0 - A VAA_RD (3.0 V) - 0 - A VDD_SLVS (0.4 V / 1.2 V) - 55 / 100 - A VDD (1.2 V) - 10 - A VDD_IO (1.8 V) - 5 - A VDD_PLL (2.8 V) - 0 - A VAA (2.8 V) - 0 - A VAA_PIX (3.0 V) - 0 - A VAA_PIX_BST (3.0 V) - 0 - A VAA_RD (3.0 V) - 0 - A Sensor State WAIT_ON_TRIGGER STANDBY SLEEP RESET www.onsemi.com 43 XGS Family HISPI ELECTRICAL SPECIFICATION PHY-to-PHY skew to 2.1 UI. The XGS products adhere to this specification when looking at all HiSPi data and HiSPi clock lanes on the same side of the sensor. The maximum PHY-to-PHY skew between any odd clock lane and any odd data lane is 2.1 UI. The same holds for the skew between any even clock lane and any even data lane. However the maximum PHY-to-PHY skew between any odd clock lane and any even data lane, or between any even clock lane and any odd data lane, can be maximum 4 pixels. The maximum value for this depends on the mux mode that is used. In 4:4 mux mode, the maximum is 1 pixel. In 4:2 mux mode, the maximum is 2 pixels. And in 4:1 mux mode, the maximum is 4 pixels. The XGS sensor from ON Semiconductor supports SLVS mode only. SLVS is typically meant only for short transmission line connections, with the advantage that SLVS drivers consume less power. Refer to the HiSPi Physical Layer Specification v2.00.00 (AND9509/D) for additional electrical definitions, specifications and timing information. Note that the VDD_SLVS supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD_IO is equivalent to VDD_HiSPi as referenced in the specification. Table 4 in the HiSPi Physical Layer specification v2.00.00 (AND9509/D) document sets the maximum D_CLK_p D_CLK_n VCM D_CLK_p / DAT A_p VOD D_CLK_n / DAT A_n Figure 55. HiSPi DC Parameters Table 26. HISPI DC SPECIFICATIONS (VDD_SLVS = 0.4 V) Symbol VDD_SLVS Parameter HiSPi Power Supply Min Typ Max Unit 0.35 0.4 0.45 V VOD Input Differential Voltage (RIN = 100 ) 0.4 * VDD_SLVS 0.5 * VDD_SLVS 0.6 * VDD_SLVS V VCM Input Common Mode Range (RIN = 100 ) 0.45 * VDD_SLVS 0.5 * VDD_SLVS 0.55 * VDD_SLVS V RIN Termination Resistor Output Impedance 100 Output Impedance per Pin 35 50 70 Typ Max Unit Table 27. DIFFERENTIAL DATA OUTPUT DC SPECIFICATIONS (VDD_SLVS = 1.2 V) Symbol VDD_SLVS Parameter Min HiSPi Power Supply 1.1 1.2 1.3 V VOD Input Differential Voltage (RIN = 100 ) 0.3 0.35 0.4 V VCM Input Common Mode Range (RIN = 100 ) 0.3 0.35 0.4 V RIN Termination Resistor Output Impedance 100 Output Impedance per Pin 35 www.onsemi.com 44 50 70 XGS Family tCLK tDiCLK D_CLK _p D CLK = tDiCLK /tCLK D_CLK _n tDiCLK /2 tR tDiCLK /2 tF tDCHSKEW tCLKJITTER DATA _(i)_p 80% 20% DATA _(i)_n tPW tCHSKEW 2PHY DATA _(j)_p DATA _(j)_n 50% tCMPSKEW Figure 56. Differential Data Output AC Parameters Table 28. DIFFERENTIAL DATA OUTPUT AC SPECIFICATIONS (VDD_SLVS = 0.4 V, 1.2 V) Parameter Symbol Min Typ Max Unit 1/tDiCLK - 777.6 - Mbps Clock Period tCLK - 2.57 - ns Data Period tDiCLK - 1.28 - ns Data Rate Data Eye Width tPW 0.6 0.8 - UI Clock Jitter tCLKJITTER - 40 50 ps Rise Time tR - 310 - ps Fall Time tF - 310 - ps DCLK 42 - 58 % Clock to Data Skew within any PHY tDCHSKEW -0.1 - 0.1 UI Skew between any Two PHY Clocks tCHSKEW2PHY -2.3 - 2.3 UI tCMPSKEW -100 - 100 ps Clock Duty Complementary Skew in Differential Pair 21. 1 UI is defined as the normalized mean time between one edge and the following edge of the clock. www.onsemi.com 45 XGS Family IMAGE SENSOR CHARACTERISTICS ELECTRO-OPTICAL SPECIFICATIONS SPECTRAL RESPONSE An overview of the XGS key electro-optical specifications can be found in Table 29. Unless otherwise noted, all measurements were done using the recommended configuration and default operation mode. Quantum efficiency curves are measured using a monochromator with step size of 5 nm. The curves for monochrome and color devices are shown in Figure 57. Table 29. ELECTRO-OPTICAL SPECIFICATIONS Parameter Quantum Efficiency (Note 22) Specification 63% (monochrome) 60% (color) Dark Current 85 e- / s (Tj = 60C) DSNU 1.76 e- (Tj = 60C, Tint = 5 ms) PRNU 0.5% Shutter Efficiency 1/3600 MTF (@ 530nm) 66.5% (vertical) 67.4% (horizontal) 22. Measured on devices with cover glass (typical transmittance cover glass = 91%). 60 Mono Red Blue Green1 Green2 Quantum Efficiency [%] 50 40 30 20 10 0 300 400 500 600 700 Wavelength [nm] Figure 57. Quantum Efficiency www.onsemi.com 46 800 900 1000 XGS Family COVER GLASS 100 90 80 TRANSMISSION (%) 70 60 50 40 30 20 10 0 300 400 500 600 700 800 900 1000 WAVELENGTH (nm) Figure 58. Cover Glass Transmission Curve Table 30. COVER GLASS SPECIFICATIONS Parameter Specification Material D263 T-ECO Refractive Index (@ 550 nm) 1.5255 Luminous Transmittance (@ D65) 91% (0.55 mm Thickness) Density (@ 40C) 2.51 g/cm3 Linear Thermal Coefficient (20C - 300C) 7.2 x 10-6/K www.onsemi.com 47 1100 XGS Family PACKAGING Figure 59. XGS 12000 Shipping Tray - Top View REFERENCES AN52561/D. (n.d.). Image Sensor Handling and Best Practices AND9509/D. (n.d.). High-Speed Serial Pixel (HiSPi) Interface Physical Layer v2.00.00 AND9510/D. (n.d.). High-Speed Serial Pixel (HiSPi) Interface Protocol TND310/D. (n.d.). Device Nomenclature (Naming Convention for Image Sensors) Thunderbolt is a trademark of Intel Corporation or its subsidiaries in the U.S. and/or other countries. www.onsemi.com 48 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS CLGA163 20.88x19.9, 1P CASE 621AB ISSUE A DATE 11 SEP 2018 DOCUMENT NUMBER: DESCRIPTION: 98AON30089G CLGA163 20.88x19.9, 1P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2018 www.onsemi.com CLGA163 20.88x19.9, 1P CASE 621AB ISSUE A DATE 11 SEP 2018 GENERIC MARKING DIAGRAM* XXXX A WL YY WW NN = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Serial Number *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "G", may or may not be present. Some products may not follow the Generic Marking. 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