SST25VF064C-80-4I-S3AE - MICROCHIP TECHNOLOGY

EOL Data Sheet

www.microchip.com

Features

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Serial Interface Architecture

– SPI Compatible: Mode 0 and Mode 3

• Dual Input/Output Support

– Fast-Read Dual-Output Instruction

– Fast-Read Dual I/O Instruction

• High Speed Clock Frequency

– 80 MHz for High-Speed Read (0BH)

– 75 MHz for Fast-Read Dual-Output (3BH)

– 50 MHz for Fast-Read Dual I/O (BBH)

– 33 MHz for Read Instruction (03H)

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 12 mA (typical @ 80 MHz) for sin-

gle-bit read)

– Active Read Current: 14 mA (t ypical @ 75MHz) for dual-

bit read)

– Standby Current: 5 µA (typical)

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 32 KByte overlay blocks

– Uniform 64 KByte overlay blocks

• Fast Erase

– Chip-Erase Time: 35 ms (typical)

– Sector-/Block-Erase Time: 18 ms (typical)

• Page-Program

– 256 Bytes per page

– Single and Dual Input supp ort

– Fast Page-Program time in 1.5 ms (typical)

• End-of-Write Detection

– Software polling the BUSY bit in Status Register

• Write Protection (WP#)

– Enables/Disables the Lock-Down function of the

status register

• Software Write Protection

– Write protection through Block-Protection bits in status

• Security ID

– One-Time Programmable (OTP) 256 bit, Secure ID

- 64 bit Unique , Factory Pre-Programmed identifier

- 192 bit User-Progr a mmab l e

• Temperature Range

– Commercial = 0°C to +70°C

– Industrial: -40°C to +85°C

• Packages Available

– 16-lea d SOI C (300 mil s)

– 8-contact WSON (6mm x 8mm)

– 8-lead SOIC (200 mils)

• All devi ces are RoHS compliant

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

The SST 25 series Serial Flash family features a four-wire, SPI-compatible inter-

face that allows for a low pin-count package which occupies less board sp ace and

ultimately lowers total system costs. SST25VF064C SPI serial flash memory is

manufactured with SST proprietary, high-performance CMOS SuperFlash tech-

nology. The split-gate cell design and thick-oxide tunneling injector attain better

reliability and manufacturability compared with alternate approaches.

Obsolete Device

Please contact Microchip Sales for replacement information.

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Product Description

The SST 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a

low pin-count package which occupies less board space and ultimately lowers total system costs.

SST25VF064C SPI serial flash memory is manufactured with SST proprietary, high-performance

CMOS Super Flash technology. Th e split-gate cell desi gn and thick-oxide tunneling injector attain bet-

ter reliability and manufacturability compared with alternate approaches.

The SST25VF064C significantly improves performance and reliability, while lowering power consump-

tion. The device writes (Program or Erase) with a single power supply of 2.7-3.6V. The total energy

consumed is a function of th e applied v olta ge , current, and time of application. Since for any giv en volt-

age range, the SuperFlash technology uses less current to program and has a shorter erase time, the

total energy consumed during any Erase or Program operation is less than alternative flash memory

technologies.

The SST25VF064C device is offered in 16-lead SOIC (300 mils), 8-contact WSON (6mm x 8mm), and

8-lead SOIC (200 mils) packages. See Figure 2 for pin assignments.

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Block Diagram

Figure 1: Functional Block Diagram

1392 B1.0

Page Buffer,

I/O Buffers

and

Data Latches

SuperFlash

Memory

X - Decoder

Control Logic

Address

Buffers

and

Latches

CE#

Y - Decoder

SCK SI/SIO

SO/SIO

WP# RST#/HOLD#

Serial Interface

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Pin Description

Figure 2: Pin Assignments for 16-Lead SOIC, 8-Contact WSON, and 8-Lead SOIC

Table 1: Pin Descr iption

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface . Commands, addresses, or input

data are latched on the rising edge of the clock input, while output data is

shifted out on the falling edge of the clock input.

SI Serial Data Input To transf er commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO Serial Data Output To transf er data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

SIO[0:1] Serial Data Input/

Output for Dual I/

O Mode

To transfer commands, addresses, or data serially into the device, or data

out of the device. Inputs are latched on the rising edge of the serial clock.

Data is shifted out on the falling edge of the serial clock. These pins are for

Dual I/O mode.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain

low for the duration of any command sequence.

WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status

RST#/HOLD# Reset To reset the operation of the device and the internal logic. The device pow-

ers on with RST# pin functionality as default.

Hold To temporarily stop serial communication with SPI Flash memory while

device is selected. This is selected by an instruction sequence. See “Reset/

Hold Mode” page 5 for details.

VDD Power Supply To provide power supply voltage: 2.7-3.6V

VSS Ground

T1.0 25036

SCK

SI/SIO0

VSS

WP#

RST#/HOLD#

VDD

CE#

SO/SIO1

1392 16-SOIC P1.0

Top View

1392 8-WSON P1.0

CE#

SO/SIO1

WP#

VSS

Top View

VDD

RST#/HOLD#

SCK

SI/SIO0

1392 8-soic S3A P3.1

CE#

SO/SIO1

WP#

VSS

VDD

RST#/HOLD#

SCK

SI/SIO0

Top View

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Memory Organization

The SST25VF064C SuperFlash memory array is organized in unifor m 4 KByte erasable sectors with

32 KByte overlay blocks and 64 KByte overlay erasable blocks.

Device Operation

The SST25VF064C is accessed thro ugh the SPI ( Seria l Per ipheral Inter face) bus compatible protocol.

The SPI bus consists of four control lines; Chip Enable (CE#) is used to select the device, and data is

accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).

The S ST 2 5 V F 0 64 C supports both Mode 0 (0,0) and Mod e 3 (1,1) of SPI b us oper ations . The difference

between the tw o mo des , as shown in Figure 3, is the state of the SCK signal when t he b us ma ster is in

Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is

high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock

signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.

Figure 3: SPI Protocol

Reset/Hold Mode

The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/

HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected

option where an EHLD instruction enables the Hold mode. Once selected as a hold pin (HOLD#), the

RST#/HOLD# pin will be configure d as a HOLD# pin, and goes back to RST# pin only after a po w er-of f

and power-on seq uence.

1392 F04.0

MODE 3

SCK

CE#

MODE 3

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

DON'T CARE

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Reset

If the RST#/HOLD# pin is used as a reset pin, RST# pin provides a hardware method fo r resetting the

device. Driving the RST# pin high puts the device in normal operating mode. The RST# pin must be

driven lo w for a minimum of TRST time to reset the device. The SO pin is in high impedance st at e while

the de vice is in reset. A successful reset will reset the status register to its power-up state (BPL, B U SY

and WEL = 0; BP3, BP2, BP1, and BP0 = 1). See Table 2 for default power-up modes. A device reset

during an active Program or Erase operation aborts the operation and data of the targeted address

range may be corrupted or lost due to the aborted e rase or program operation.

Figure 4: Reset Timing Diagram

Table 2: Reset Timing Parameters

Symbol Parameter Min Max Units

TRST Reset Pulse Width 100 ns

TRHZ Reset to High-Z Output 105 ns

TRECR Reset Recovery from Read 100 ns

TRECP Reset Recover y from Program 10 µs

TRECE Reset Recovery from Erase 1 ms

T2.25036

1292 F28.0

CE#

SCK

RST#

TRECR

TRECP

TRECE

TRST

TRHZ

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Hold Operation

The EHLD instr uction en ables the hold pin fu nctionality of the RS T#/HOLD# pin. Once conver ted to a

hold pin, the RST#/HOLD# pin functions as a hold pin until the device is powered off and on. After the

pow er cycle, the pin functionality r eturns as a reset pin (RST#) after the power on.

The HOLD# pin is used to pause a serial sequence using the SPI flash memory, but without resetting

the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#

mode begi ns when the SCK active low state coincides with th e falling edge of the HOLD# sign al. The

HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.

If the f alling edge of the HOLD# signal does not coincide with the SCK active low state , then the de vice

enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the

HOLD# signal does not coincide with the SCK active low state, then the device exits from Hold mode

when the SCK next reaches the active low state. See Figure 5 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or VIH.

If CE# is driven high during a Hold condition, the device return s to Standby mode. As long as HOLD#

signal is low, the memory remains in the Hold condition. To resume communication with the device,

HOLD# must be driven active high, and CE# must be driven active low. See Figure 5 for Hold timing.

Figure 5: Hold Condition Waveform

Write Protection

SST25VF064C provides software Write protection. The Write Protect pin (WP#) enables or disables

the loc k-do wn function of the statu s register. The Bloc k-Pr otection bits (BP3, BP2, BP1, BP0, and BPL)

in the status register provide Write protection to the memory array and the status register. See Table 5

for the Block-Protection description.

Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.

When WP# is driven low, the execution of the Write-Status-Register ( WRSR) instruction is deter mined by

the value of the BPL bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.

Table 3: Conditions to execute Write-Status-Register (WRSR) Instruction

WP# BPL Execute WRSR Instruction

L 1 Not Allowed

L 0 Allowed

H X Allowed

T3.0 25036

Active Hold Active Hold Active

1392 F05.0

SCK

HOLD#

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Security ID

SST25VF064C offers a 256-bit Security ID (Sec ID) feature. The Security ID space is divided into two

parts – one factory-programmed, 64-bit segment and one user-programmable 192-bit segment. The

factory-programmed segment is programmed at SST with a unique number and cannot be changed.

The user-programma ble segment is left unprogrammed for the customer to prog ram as desired.

Use the Program SID command to program the Security ID using the address shown in Table 7. Once

progr a mmed, the Security ID can be lock e d using th e Lockout SID command. This prevent s an y fut ure

write to the Se curity ID.

The factory-programmed portion of the Security ID can never be programmed, and none of the Secu-

rity ID can be erased.

Status Register

The software status register provides status on whether the flash memory array is available for any

Read or Write operation, whether the device is Write enabled, and the state of the Memory Wr ite pro-

tection. During an internal Erase or Program operation, the status register may be read only to deter-

mine the completion of an operation in progress. Table 4 describes the function of each bit in the

software status register.

Table 4: Status Register

Bit Name Function Default at

Power-up Read/Write

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress 0R

1 WEL 1 = De vice is memory Write enabled

0 = De vice is not memory Write enab led 0R

2 BP0 Indicate current lev el of bloc k write protection (See Table 5) 1 R/W

3 BP1 Indicate current lev el of bloc k write protection (See Table 5) 1 R/W

4 BP2 Indicate current lev el of bloc k write protection (See Table 5) 1 R/W

5 BP3 Indicate current lev el of bloc k write protection (See Table 5) 1 R/W

6 SEC1

1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout SID instruction; other-

wise, the default at power up is ‘0’.

Security ID status

1 = Security ID space lock ed

0 = Security ID space not lock ed

01R

7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits

0 = BP3, BP2, BP1, BP0 are readable/writab le 0R/W

T4.0 25036

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Busy

The Busy bit determines whether there is an inter nal Erase or Program operation in progress. A ‘1’ for

the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is

ready for the next valid operation.

Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the

Write-Enable-Latch bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset ),

it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)

commands. The Write-Enable-Latch bit is automatically reset under the following conditions:

•Power-up

•Write-Disable (WRDI) instruction completion

•Write-Status Register instruction completion

•Page-Program instruction completion

•Dual-Input Page-Program instruction completion

•Sector-Erase instruction completion

•Block-Erase instruction completion

•Chip-Erase instruction completion

•Program SID instruction completion

•Lockout SID instruction completion

Block Protection (BP3,BP2, BP1, BP0)

The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as shown in Table

5, to be softw are protect ed against an y memory Write ( Progr am or Er ase) oper ation. The Write-Status-

high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits

are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to the defaults specified in Table 5.

Block Protection Lock-Down (BPL)

WP# pin dr iven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it pre-

vents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high

(VIH), the BPL bit has no effect and its va lue is “Don’t Care”. After power-up , the BPL bit is reset to 0.

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Security ID Status (SEC)

The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write

command. The SEC is ‘1’ after the host issues a Lockout SID comman d. Once t he ho st issues a Lock-

out SID command, the SEC bit can never be reset to ‘0.’

Table 5: Software Status Register Block Protection FOR SST25VF064C

Prot ectio n Level

Status Register Bit1

1. Default at power-up for BP3, BP2, BP1, and BP0 is ‘1111’. (All Blocks Protected)

Protected Memory Address

BP3 BP2 BP1 BP0 64 Mbit

None 0000 None

Upper 1/128 0 0 0 1 7F0000H-7FFFFFH

Upper 1/64 0 0 1 0 7E0000H-7FFFFF H

Upper 1/32 0 0 1 1 7C0000H-7FFFFFH

Upper 1/16 0 1 0 0 780000H-7FFFFFH

Upper 1/8 0 1 0 1 700000H-7FFFFFH

Upper 1/4 0 1 1 0 600000H-7FFFFFH

Upper 1/2 0 1 1 1 400000H-7FFFFFH

All Blocks 1 0 0 0 000000H-7FFFFFH

All Blocks 1 0 0 1 000000H-7FFFFFH

All Blocks 1 0 1 0 000000H-7FFFFFH

All Blocks 1 0 1 1 000000H-7FFFFFH

All Blocks 1 1 0 0 000000H-7FFFFFH

All Blocks 1 1 0 1 000000H-7FFFFFH

All Blocks 1 1 1 0 000000H-7FFFFFH

All Blocks 1 1 1 1 000000H-7FFFFFH

T5.0 25036

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Instructions

Instructions are used to read, write (Erase and Program), and configure the SST25VF064C. The

instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-

Enable (WREN) instruction must be executed prior any Page-Program, Dual-Input Page-Program,

Sector-Erase, Block-Erase, Write-Status-Register, Chip-Erase, Program SID, or Lockout SID instruc-

tions. The complete list of ins tructions is provided in Table 6.

All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the ris-

ing edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is

entered and must be driven high after the last bit of the instruction has been shifted in (except for

Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before

receiving the last bit of a n instruction bus cycle, will terminate the instruction in progress an d return the

device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the

most significant bit (M SB) first.

Table 6: Device Operation Instructions

Instruction Description Op Code Cycle1

1. One bus cycle is eight clock periods.

Address

Cycle(s)2Dumm y

Cycle(s) Data

Cycle(s)

Read Read Memory 0000 0011b (03H) 3 0 1 to 

F ast-Read Dual I/O Read Memory with Dual Address Input

and Data Output 1011 1011b (BBH) 33131 to 3

F ast-Read Dual-Out-

put Read Memory with Dual Output 0011 1011b (3BH) 3 1 1 to 3

High-Speed Read Read Memory at Higher Speed 0000 1011b (0BH) 3 1 1 to 

Sector-Erase4Erase 4 KByte of memory array 0010 0000b (20H) 3 0 0

32 KByte Block-Erase5Erase 32KByte b lock of memory arra y 0101 0010b (52H) 3 0 0

64 KByte Block-Erase6Erase 64 KByte block of memory arra y 1101 1000b (D8H) 3 0 0

Chip-Erase Erase Full Memory Array 0110 0000b (60H) or

1100 0111b (C7H) 000

P age-Program To Program 1 to 256 Data Bytes 0000 0010b (02H) 3 0 1 to 256

Dual-Input P age-

Program To Program 1 to 256 Data Bytes 1010 0010b (A2H) 3 0 1 to 1283

RDSR7Read-Status-Register 0000 0101b (05H) 0 0 1 to 

EWSR Enable-Write-Status-Register 0101 0000b (50H) 0 0 0

WRSR Write-Status-Register 0000 0001b (01H) 0 0 1

WREN Write-Enable 0000 0110b (06H) 0 0 0

WRDI Write-Disable 0000 0100b (04H) 0 0 0

RDID8Read-ID 1001 0000b (90H) or

1010 1011b (ABH) 301 to 

JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 0 0 3 to 

EHLD Enable HOLD# pin functionality of the

RST#/HOLD# pin 1010 1010b (AAH) 0 0 0

Read SID Read Secur ity ID 1000 1000b (88H) 1 1 1 to 32

Program SID9Program User Security ID area 1010 0101b (A5H) 1 0 1 to 24

Lockout SID9Lockout Security ID Programming 1000 0101b (85H) 0 0 0

T6.0 25036

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Read (33 MHz)

The Read instruction, 03H, supports up to 33 MHz Read. The de vice out puts the dat a startin g from the

specified address location. The data output stream is continuous through all addresses until termi-

nated by a lo w to high transition on CE#. The internal address pointer will automatically increment until

the highest memory address is reached. Once the highest memory address is reached, the address

pointer will automatically increment to the beginning (wrap-around) of the address space. F or e xample ,

once the data from address location 7FFFFFH has been read, the next output will be from address

location 000000H.

The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits A23-A0.

CE# must remain active low for the duration of the Read cycle. See Figure 6 for the Read sequence.

Figure 6: Read Sequence

2. Address bits above the most significant bit can be either VIL or VIH.

3. One bus cycle is four clock periods (dual operation)

4. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.

5. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.

6. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

8. Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H. The Manufac-

turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.

9. Requires a prior WREN command.

1392 F06.0

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 7047 48 55 56 63 64

N+2 N+3 N+4N N+1

DOUT

MSB MSB

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

High-Speed Read (80 MHz)

The High-Speed Read instruction supporti ng up to 80 MHz Read is in itiated b y exe cuting an 8-bit com-

mand, 0BH, followed by address bits A23-A0 and a dummy byte. CE# must remain active low for the

duration of the High-Speed Read cycle. See Figure 7 for the High-Speed Read sequence.

F ollowing a dummy cycle, the High-Speed Read instruction outputs the data starting from the specified

address locati on. T he dat a ou tp ut str ea m is continuous th rough all add resse s until t erminated b y a low

to high transition on CE#. The internal address pointer will automatically increment until the highest

memory address is reached. Once the highest memory address is reached, the address pointer will

automatically increment to the beginning (wrap-around) of the address space. For example, once the

data from address location 7FFFFFH is read, the next output is from add ress location 000000H.

Figure 7: High-Speed Read Sequence

1392 F07.0

CE#

SCK

ADD.

012345678

ADD. ADD.0B

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63 64

N+2 N+3 N+4

NN+1

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

71 72

DOUT

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Fast-Read Dual-Output (75 MHz)

The Fast-Read Dual-Output (3BH) instruction outputs data up to 75 MHz from the SIO0 and SIO1 pins.

To initiate the instruction, execute an 8-bit command (3BH) followed by address bits A23-A0 and a

dummy byte on SI/SIO0. Following a dummy cycle, the Fast-Read Dual-Output instruction outputs the

data star ting from the specified address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock

sequence, odd data bits D7, D5, D3, and D1; and SIO0 outputs even data bits D6, D4, D2, and D0.

CE# must remain active low for the duration of the Fast-Read Dual-Output instruction cycle. See Fig-

ure 8 for the Fast-Read Dual-Output sequence.

The data output stream is continuous through all addresses until terminated by a low- to-high tr ansition

on CE#. The internal address pointer will automatically increment until the highest memory address is

reached. Once the highest memor y address is reached, the address pointer automatically increments

to the beginning (wraparound) of the address space. for 64 Mbit density, once the data from address

location 7FFFFFH has been read the next output will be from address location 000000H.

Figure 8: Fast-Read Dual Output Sequence

1392 F08.1

CE#

SIO1

SIO0

SCK

012345678 28 29 30 31

MSB

MODE 3

MODE 0

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

6420642064206420

7531 7531 7531 7531

24-Bit Address Dummy Cycle

DOUT

MSB

DOUT

MSB

DOUT

MSB

DOUT

N N+1 N+2 N+3

IO, Switches from Input to Output

ADD. ADD. ADD.

15 16

HIGH IMPEDANCE

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Fast-Read Dual I/O (50 MHz)

The Fast-Read Dual I/O (BBH) instruction reduces the total num ber of inpu t cloc k cycles, which results

in faster data access. The device is firs t selected by driving Chip Enable CE# low. Fast-Read Dual I/O

is initiated by executing an 8-bit command (BBH) on SI/SIO0, thereafter, the device accepts address

bits A23-A0 and a dummy byte on SI/SIO0 and SO/SIO1. It offers the capability to input address bits

A23-A0 at a rate of two bits per clock. Odd address bits A23 through A1 are input on SIO1 and even

address bit s A2 2 thr ou gh A0 a re inpu t on SIO 0, alternately For example the most significant bit is input

first followed by A23/22, A21/A20, and so on. Each bit is latched at the same rising edge of the Serial

Clock (SCK). The input data during the dummy clocks is “don’t care”. However, the SIO0 and SIO1 pin

must be in high-impedance prior to the falling edge of the first data output clock.

Following a dummy cycle, the Fast-Read Dual I/O instruction outputs the data star ting from the speci-

fied address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock sequence, odd data bits D7,

D5, D3, and D1; and SIO0 ou tputs e v en data bits D6, D4, D2, and D0 per cloc k edge . CE# m ust remain

active low for the duration of the Fast-Read Dual I/O instruction cycle. The data output stream is con-

tinuous t hrough all addresses until terminated by a low-to-high transition on CE#.

The internal address pointer will automatically increment until the highest memory address is reached.

Once the highest memory address is reached, the address pointer automatically increments to the

beginning (wraparound) of the address space. For example, once the data from address location

7FFFFFH is read, the next output is from address location 000000H. See Figure 9 for the Fast-Read

Dual I/o sequence.

Figure 9: Fast-Read Dual I/O Sequence

1392 F29.0

CE#

SIO1

SIO0

SCK

01234567891011121314

MODE 3

MODE 0

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

642064206420

753175317531

MSB

6420642064206420

7531753175317531

MSB MSB MSB

A23-16 A15-8 A7-0

DOUT DOUT DOUT DOUT

N N+1 N+2 N+3

IO, Switches from Input to Output

Dummy

Cycle

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Page-Program

The page-Program instruction programs up to 256 bytes of data in the memory. The selected page

address must be in the erased state (FFH) before initiating the Page-Program operation. A Page-Pro-

gram applied to a protected memory area will be ignored.

Prior to the program operation, the Write-Enabled (WREN) instruction must be executed. CE# must

remain active low for the duration of the Page-Program instruction. The Page-Program instruction is

initiated b y executing an 8-bit command, 02H, followed b y address bits A23-A0 . Following the address ,

at least one byte is needed for the data input. CE# must be driven high before the instruction is exe-

cuted. The user may poll the Busy bit in the software status register or wait TPP for the completion of

the internal self-timed Page-Program operat ion. See Figure 10 for the Page-Program sequence.

For Page-Program, the memory range for SST25VF064C is set in 256 byte page boundaries. The

device handles shifting of more than 256 bytes of data by keeping the last 256 bytes of data shifted as

the correct data to be programmed. If the target address for the Page-Program instruction is not the

beginning of t he page boun dary (A7-A0 are not all z ero) an d the n umber of data input exceeds or over-

laps the end of the address of the page boundar y, the excess data inputs will wrap around and will be

programmed at the start of that target page.

Figure 10: Page-Program Sequence

1392 F30.0

CE#

SCK

ADD.

012345678

ADD. ADD. Data Byte 1

HIGH IMPEDANCE

15 16 23 24 31 32 39

MODE 0

MODE 3

MSBMSB

MSB LSB

CE#

SCK 40 41 42 43 44 45 46 47 48

Data Byte 2

HIGH IMPEDANCE

MSBMSB

MSB LSB

50 51 52 53 54 55

2072

Data Byte 3

2073

2074

2075

2076

2077

2078

2079

Data Byte 256

LSBLSB

LSB LSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Dual-Input Page-Program (50 MHz)

Dual-Input Page-Program instruction A2H, doubles the data input transfer of normal Page-Program

instruction and supports up to 50MHz. Data to be progr a mmed is ente red using two I/O pins , SI O1 and

SIO0. Prior to the program operation the Write-Enable (WREN) instruction must be executed. The

Dual-Input Page-Program instruction is entered by driving CE# low, followed by the instruction code,

A2H, three address bytes, and at least one data byte on serial data inputs SIO1 and SIO0 pins. CE#

must be driven low for the entire duration of the sequence. The Dual-Input Page-Program instruction

programs up to 256 bytes of data in the memory. The selected page address must be in the erased

state (FFH) before initiating the Page-Progr am oper ation. A Dual-I nput Page-Progr am applied to a pr o-

tected memory area will be ignored.

CE# must be driven high after the seventh and eight bit of the last data byte has been latched; other-

wise, the dual input prog r am instruction is not e x e cuted. Once CE# is driven high the instruction is e xe-

cuted and the user may poll the WEL and Busy bit of the software status register or wait TPP for the

completion of the internal self-timed Page-Program operation. See Figure 10 for the Dual-Input-Page-

Program sequence.

For Dual-Input Page-Program, the memory range for the SST25VF064C is set in 256 byte page

boundaries. The device handles shifting of more than 256 bytes of data by keeping the last 256 bytes

of data shifted as the correct data to be programmed. If the target address for the Page-Program

instruction is not the beginning of the page boundary (A7-A0 are not all zero) and the number of data

input exceeds or overlaps the end of the address of the page boundary, the excess data inputs will

wrap around and will be programmed at the start of that target page.

Figure 11: Dual-Input Page-Program

1392 F31.0

CE#

SIO1

SIO0

SCK

012345678910

MODE 3

MODE 0

28 29 30 31 32 33 34 35 36 37 28 39 40 41 42 43 44 45 46

64206420

75317531

MSB

64206420

75317531

MSB MSB

6420

7531

3210

23 22 21

24-bit Address (1)

MSB MSB

Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 256

High Impedance

1052

1053

1054

1055

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Sector-Erase

The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase

instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-

Enable (WREN) instruction must be e x ecuted. CE# must remain active lo w f or the duration of any com-

mand sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol-

lowed by address bits A23-A0. Address bits AMS-A12 (AMS = Most Significant address) are used to

determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high

before the instruction is executed. Poll the Busy bit in the software status register or wait TSE fo r the

completion of the internal self-timed Sector-Erase cycle. See Figure 12 f or th e Sector-Era se sequence .

Figure 12: Sector-Erase Sequence

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1392 F13.0

MSBMSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

32-KByte and 64-KByte Block-Erase

The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-

Erase instruction applied to a protected memor y area will be ignored. The 64-KByte Block-Erase instruc-

tion clears all bits in the selected 64 KByte b l oc k t o FFH. A Bloc k-Er ase instruction applied to a protected mem-

or y area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.

CE# must remain active low for the duration of any command sequence. The 32-KByte Block-Erase

instruction is initiated by executing an 8-bit command, 52H, followed by address bits A23-A0. Address

bits AMS-A15 (AMS = Most Significant Address) are used to determine bloc k address (BAX), remaining

address bi ts can be VIL or VIH. CE# must be driven high bef ore the instruction is e xecuted. The 64- KByte Block-

Erase instruction is initiated by executing an 8-bit co mmand D8H, followed by address bits A23-A0. Address bits

AMS-A15 are used to determine block address (BAX), remaining address bits can be VIL or VIH. CE# must be

driven high before the instruction is executed. Poll the Busy bit in the software status register or wait TBE fo r

the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase cycles. See

Figure 13 for the 32-KByte Block-Erase sequence and Figure 14 for the 64-KByte Block-Erase

sequence.

Figure 13: 32-KByte Block-Erase Sequence

Figure 14: 64-KByte Block-Erase Sequence

CE#

SCK

ADDR

012345678

ADDR ADDR

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1392 F32.0

MSB MSB

CE#

SCK

ADDR

012345678

ADDR ADDR

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1327 F33.0

MSB MSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Chip-Erase

The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored

if any of t he me mor y area is pr otected . Prior to any Write operation, the Write-Enable (WREN) instruction

must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.

Initiate the Chip-Er a se instruction by executing an 8-bit command, 60 H or C7H. CE# mu st be driven high

bef ore the instruction is ex ecuted. P oll the Busy bit in the software status register or wait TCE for the comple-

tion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase sequence.

Figure 15: Chip-Erase Sequence

Read Security ID

To execute a Read SID op eratio n, the host drive s CE# lo w, send s the Read SID comm and cycle (88 H),

one address cycle, and then one dummy cycle. Each cycle is eight bits long, most significant bit first.

After the dummy cycle, the device outputs data on the falling edge of the SCK signal, starting from the

specified address locati on. The data outpu t stream is contin uous through all SID addr esses until termi-

nated by a low-to-high transition on CE#. The internal address pointer automatically increments until

the last SID address is reached, then outputs wrap around until CE# goes high.

Lockout Security ID

The Lockout SID instruction prevents any future changes to the Security ID. Prior to the Lockout SID

operation, the Write-Enable (WREN) instruction must be executed. To execute a Lockout SID, the host

drives CE# low, sends the Lockout SID command cycle (85H), then drives CE# high. A cycle is 8 bits

long, most significant bit first. The user may poll the BUSY bit in the software status register or waits

TPSID for the completion of the Lockout SID operation.

CE#

SCK 01234567

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

1392 F16.0

MSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Program Security ID

The Program SID instr uction programs one to 24 bytes of data in the use r-programmable, Security ID

space. The device ignores a Program SID instruction pointing to an invalid or protected address, see

Table 7. Prior to the program operation, execute WREN.

To execute a Program SID oper ation, the host drive s CE# lo w, sends th e Prog r am SID comma nd cycle

(A5H), one address cycle, the data to be programmed, then drives CE# high. The programmed data

must be betw een 1 to 2 4 Bytes and in whol e Byte increments . To determine the completion o f the inter-

nal, self-timed Program SID operation, poll the BUSY bit in the software status register, or wait TPSID

for the completion of the internal self-timed Program SID operation.

Read-Status-Register (RDSR)

The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register

may be read at any time even during a Write (Program/Era se) operation. When a Write operation is in

progress, the Busy bit may be checked before sending any new commands to assure that the new

commands are prope rly receiv ed b y the de vice . CE# mu st be driven low before the RDSR instruction is

entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing

clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR

instruction sequence.

Figure 16: Read-Status-Register (RDSR) Sequence

Table 7: Program Security ID

Program Security ID Address Range

Pre-Programmed at factory 00H – 07H

User Programmable 08H – 1FH

T7.0 25036

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

1392 F17.0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

Status

MSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to ‘1’

allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Pro-

gram/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Sta-

tus-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be

cleared upon th e rising edge CE# of the WRSR instruction. CE# must be driv en high bef o re the WREN

instruction is executed.

Figure 17: Wr ite Enable (WREN) Sequence

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit to ‘0,’ thereby, preventing any

new Write operations . The WRDI in struction will not terminate any program or erase oper ation in prog-

ress. Any program or erase operation in progress will continue after executing the WRDI instruction.

CE# must be driven high before the WRDI instruction is executed.

Figure 18: Wr ite Disable (WRDI) Sequence

CE#

SCK 01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1392 F18.0

MSB

CE#

SCK 01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1392 F19.0

MSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Write-Status-Register instruction must be

executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-

step instruction sequence of the EWSR instruction followed by the WRSR instruction works like soft-

ware data protection (SDP) command structure which prevents any accidental alteration of the status

high before the EWSR instruction is executed.

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of

the status register. CE# must be driven low before the command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN

and WRSR instruction sequences.

Executing the Write-Status-Register instr uction will be ignored when WP# is low and BPL bit is set to

‘1’. When the WP# is lo w, the BPL bit can only be set fr om ‘0’ to ‘1’ to lock-down the status regist er, b ut

cannot be reset f rom ‘1’ to ‘0’. Wh en WP# is high, t he lock-down function of t he BPL bit is d isabled and

the BPL, BP0, BP1, BP2, and BP3 bits in the status register can all be changed. As long as BPL bit is

set to ‘0’ or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of

the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this

case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as

alter ing the BP0, BP1, BP2 , and BP3 bits at the same time. See Table 3 for a summar y de scr iption of

WP# and BPL functio ns.

Figure 19: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Sta-

tus-Register (WRSR) Sequence

1392 F20.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

76543210

MSBMSBMSB 01

MODE 3

SCK

CE#

MODE 0

50 or 06

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Enable-Hold (EHLD)

The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/

HOLD# pin. CE# must rem ain activ e lo w for the duration of the Enab le-Hol d instruction sequence. CE#

must be driven high before the instruction is executed. See Figure 20 for the Enable-Hold instruction

sequence.

Figure 20: Enable-Hold Sequence

Read-ID (RDID)

The Read-ID instruction (RDID) identifies the device as SST25VF064C and manufacturer as SST. The

device information can be read from executing an 8-bit command, 90H or ABH, followed by address

bits A23-A0. Following the Re ad-ID in st ruction, the ma nufacturer’s ID is located in address 000 00H a nd

the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s

and device ID output data toggles between address 00000H and 00001H until terminated by a low to

high transit ion on CE#. After CE# is driven high, the device is put into standby mode.

Refer to Tab les 8 and 9 for device identification data.

Figure 21: Read-ID Sequence

CE#

SCK 01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1203 F21.0

MSB

1392 F21.0

CE#

SCK

012345678

00 ADD

90 or AB

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63

BF Device ID BF Device ID

Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.

1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.

HIGH

IMPEDANCE

MODE 3

MODE 0

MSB MSB

MSB

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Table 8: Product Identification

Address Data

Manufacturer’s ID 00000H BFH

Device ID

SST25VF064C 00001H 4BH

T8.0 25036

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

JEDEC Read-ID

The JEDEC Read-ID instruction identifies the device as SST25VF064C and the manufacturer as SST.

The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC

Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 24-bit

device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H,

identifies the memory type as SPI Serial Flash. Byte 3, 4BH, identifies the device as SST25VF064C.

The instruction sequence is sho wn in Figure 22. The JEDEC Read ID instruction is terminated by a lo w

to high tra nsition on CE# at any time during data output.

Figure 22: JEDEC Read-ID Sequence

Table 9: JEDEC Read-ID Data

Manufacturer’s ID Device ID

Memory Type Memory Capacity

Byte1 Byte 2 B yte 3

BFH 25H 4BH

T9.0 25036

25 4B

1392 F22.0

CE#

SCK 012345678

HIGH IMPEDANCE

15 1614 28 29 30 31

MODE 3

MODE 0

MSBMSB

9 10111213 1718

19 20 21 22 23 24 25 26 27

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Electrical Specifications

Absolute Maximum Stress Ratings Applied conditions greater than those listed under “Absolute

Maximum Stress Rat ings” ma y cause permanent damage to the de vice . This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sectio ns of this data sheet is not implied. Exposu re to absolute maxim um stress rating con-

ditions may affect device reliability.

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Output shorted for no more than one second. No more than one output shorted at a time.

Table 10: Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

T10.1 25036

Table 11: AC Conditions of Test1

1. See Figure 28

Input Rise/Fall Time Output Load

5ns CL = 30 pF

T11.1 25036

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Table 12: DC Operating Characteristics (VDD = 2.7-3.6V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDDR Read Current 12 mA C E # = 0 . 1 V DD/0.9 VDD@33 MHz, SO = open

IDDR2 High-Speed Read Current 25 mA C E # = 0 . 1 V DD/0.9 VDD@80 MHz, SO = open

IDDR3 Fast-Read Dual-Output/Dual I/

O Current 25 mA CE# = 0.1 VDD/0.9 VDD@75/50 MHz

IDDW Program and Erase Current 25 mA CE# = VDD

ISB1 Standby Current 20 µA CE# = VDD, VIN = VDD or VSS

ILI Input Leakage Current 1 µA VIN = GND to VDD, VDD = VDD Max

ILO Output Leakage Current 1 µA VOUT = G ND to VDD, VDD = VDD Max

VIL Input Low Voltage 0.8 V VDD = VDD Min

VIH Input High Voltage 0.7 VDD VV

DD = VDD Max

VOL Output Low Voltage 0.2 V IOL = 100 µA, VDD = VDD Min

VOH Output High Voltage VDD-0.2 V IOH = -100 µA, VDD = VDD Min

T12.0 25036

Table 13: Capacitance (TA = 25°C, f = 1 Mhz, other pins open)

P arameter Description Test Condition Maximum

COUT1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Output Pin Capacitance VOUT = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T13.0 25036

Table 14: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Endurance 10,000 Cycles JEDEC Standard A11 7

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T14.0 25036

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Table 15: AC Operating Characteristics

Symbol Parameter

33 MHz 50 MHz 75/80 MHz

UnitsMin Max Min Max Min Max

FCLK1Serial Cloc k F re quency High-Speed Read 33 50 75/80 MHz

TSCKH Serial Clock High Time 13 9 6 ns

TSCKL Serial Clock Low Time 13 9 6 ns

TSCKR2Serial Clock Rise Time (Sle w Rate) 0.1 0.1 0.1 V/ns

TSCKF Serial Clock Fall Time (Slew Rate) 0.1 0.1 0.1 V/ns

TCES3CE# Active Setup Time 5 5 5 n s

TCEH3CE# Activ e Hold Time 5 5 5 ns

TCHS3CE# Not Active Setup Time 5 5 5 ns

TCHH3CE# Not Acti ve Hold Time 5 5 5 ns

TCPH CE# High Time 50 50 50 ns

TCHZ4CE# High to High-Z Output 7 7 7 ns

TCLZ SCK Low to Low-Z Output 0 0 0 ns

TDS Data In Setup Time 3 3 2 ns

TDH Data In Hold Time 5 5 4 ns

THLS HOLD# Low Setup Time 5 5 5 ns

THHS HOLD# High Setup Time 5 5 5 ns

THLH HOLD# Low Hold Time 5 5 5 ns

THHH HOLD# High Hold Time 5 5 5 ns

THZ4HOLD# Low to High-Z Output 7 7 7 ns

TLZ4HOLD# High to Low-Z Output 7 7 7 ns

TOH Output Hold from SCK Change 0 0 0 ns

TVOutput Valid from SCK 15 10 6 ns

TSE Sector-Erase 25 25 25 ms

TBE Block-Erase 25 25 25 ms

TSCE Chip-Erase 50 50 50 ms

TPP Page-Program 2.5 2.5 2.5 ms

TPSID Progra m Security ID 1.0 1.0 1.0 ms

T15.1 25036

1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz

Maximum clock frequency Fast-Read Dual-Output (3BH) is 75 MHz

Maximum clock frequency Fast-Read Dual I/O (BBH) is 50 MHz

Maximum clock frequency for High-Speed Read, OBH, is 80 MHz

Maximum clock frequency for Dual-Input Page-Program, A2H, is 50 Mhz

2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements

3. Relative to SCK.

4. Not 100% tested in production.

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Figure 23: Ser ial Input Timing Diagram

Figure 24: Ser ial Output Timing Diagram

Figure 25: Hold Timing Diagram

HIGH-Z HIGH-Z

CE#

SCK

MSB LSB

TDS TDH

TCHH TCES TCEH TCHS

TSCKR TSCKF

TCPH

1392 F23.0

1392 F24.0

CE#

SCK

MSB

TCLZ

TSCKH

TCHZ

TOH

TSCKL

LSB

THZ TLZ

THHH THLS THHS

1392 F25.0

HOLD#

CE#

SCK

THLH

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Power-Up Specifications

All functionalities and DC specifications are specified for a VDD ramp rate of grea ter than 1V per 10 0

ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is

required. The recommended VDD power-up to RESET# high time should be greater than 100 µs to

ensure a proper reset. See Table 16 and Figures 26 and 27 for more information.

Figure 26: Power-Up Reset Diagram

Figure 27: Power-up Timing Diagram

Table 16: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only f or initial qualification and after a design or process change that could affect this parameter.

VDD Min to Read Operation 100 µs

TPU-WRITE1VDD Min to Write Operation 100 µs

T16.0 25036

1292 F36.0

VDD

RESET#

CE#

TPU-READ

VDD min

VIH

TRECR

Note: See Table 2

Time

VDD Min

VDD Max

VDD

Device fully accessible

TPU-READ

TPU-WRITE

Chip selection is not allowed.

All commands are rejected by the device.

1392 F26.0

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Figure 28: AC Input/Output Reference Waveforms

1392 F37.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”.

Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD).

Input rise and fall times (10%  90%) are <5 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Product Ordering Information

Valid combinations for SST25VF064C

SST25VF064C-80-4I-SCE

SST25VF064C-80-4I-S3AE

SST25VF064C-80-4I-Q2AE SST25VF064C-80-4C-Q2AE

Note:Valid combinations are thos e products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of v alid combinations and to determine av ailability of new combi-

nations.

SST 25 VF 064C - 80 - 4I - SAE

XX XX XXXX -XX-XX-XXX

Environmental Attribute

E1 = non-Pb

Package Modifier

C = 16 leads

A = 8 contacts

Package Type

S = SOIC (300 mil body width)

Q2 = WSON (6mm x 8mm)

S3 = SOIC (200 mil body width)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Operating Frequenc y

80 = 80 MHz

Version

C = Page-Program

Device Density

064 = 64 Mbit

Voltage

V = 2.7-3.6V

Product Series

25 = Serial Peripheral Interface

flash mem ory

1. En vironmental suffix “E” denotes non-Pb sol-

der. SST non-Pb solder devices are “RoHS

Compliant”.

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Packaging Diagrams

Figure 29: 16-Lead Plastic Small Outline Integrated Circuit (SOIC)

SST Package Code SC

16.soic-SC-ILL.3

Note: 1. Complies with JEDEC publication 95 MS-013 AA dimensions (except as noted), although some dimensions may be more stringent.

† = JEDEC min is 10.10; SST min (10.08) is less stringent

‡ = JEDEC min is 0.40; SST min (0.38) is less stringent

2. All linear dimensions are in metric (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

.33

.51

10.08 †

10.50

1.27 BSC .10

.30

2.35

2.65

.23

.32 .38 ‡

1.27

.020x45° 7°

4 places

7°

4 places

10.00

10.65

7.40

7.60

Pin #1

Identifier

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Figure 30: 8-Contact Very-ver y-thin Small Outline No-lead (WSON)

SST Package Code: Q2A

Note:

1. All linear dimensions are in millimeters (max/min).

2. Untoleranced dimensions are nominal target dimensions.

3. The external paddle is electrically connected to die back-side and VSS.

This paddle can be soldered to the PC board;

SST suggests connecting this paddle to VSS of the unit.

Connection of this paddle to any other voltage potential will

result in shorts and/or electrical malfunction of the device.

8-wson-6x8-Q2A-2.0

4.8

1.27

BSC

0.45

0.35

6.0

6.00

±0.10

8.00

±0.10

0.55

0.45

TOP VIEWBOTTOM VIEW

CROSS SECTION

SIDE VIEW

1mm

0.076

Detail

A-A

0.80

0.70

0.2

0.05

Max

0.80

0.70

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Figure 31: 8-Lead Small Outline Integrated Circuit (SOIC)

SST Package Code S3A

8-soic-5x8-S3A-1.0

Note: 1. All linear dimensions are in millimeters (max/min).

2. Coplanarity: 0.1 mm

3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.

T OP VIEW SIDE VIEW

END VIEW

7.34

7.08

8.10

7.70

5.38

5.18

Pin #1

Identifier 0.48

0.35

0.25

0.19

0.80

0.50

10°

4 places

1mm

0°

8°

1.27 BSC

0.25

0.05

2.16

1.75

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Table 17: Revision History

Number Description Date

00 •Initial release of data sheet Sep 2008

01 •Added 8-contact WSON Q2 A package

•Added Security ID information throughout

•Updated Table 6 on page 11

•Revised “Fast-Read Dual- Ou tp ut (75 MHz) ” on pa ge 14 and “Fast-Read

Dual I/O (50 MHz)” on page 15.

•Modified Figure 8 on page 14.

•Updated Table 15 on page 29

•Added Commercial temperature range in Features, page 1; Operating

Range, page 23; and Product Ordering Information, page 28

Apr 2009

02 •Added 8-lead SOIC S3A package Sep 2009

03 •Changed Max Value of IDDR2 and IDDW to 25mA in Table 12 on page 28 Dec 200 9

04 •Revised Table 6 on page 11

•Updated address information on page 31. Apr 2010

A•Applied new document format.

•Released document under letter revision system.

•Updated Spec number from S71392 to DS25036

Jun 2011

B•Correct pin description for 8-lead SOIC on page 4 Aug 2012

C•EOL of all SST25VF064C devices.

•Document marked obsolete. Apr 2015

SST, Silicon Storage Technology, the SST logo, SuperFlash, and MTP are registered trademarks of Microchip Technology, Inc.

MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Microchip Technology, Inc. All other trademarks and registered trade-

marks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Ref er to www .microchip .com for the most recent documentation. F or the most current

package dra wings, please see the Pac kaging Specification located at http://www . microchip .com/pac kaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

Microchip makes no warranty f or the use of its products other than those e xpressly contained in the Standard Terms and Conditions

of Sale.

For sales office locations and information, please see www.microchip.com.

www.microchip.com

ISBN:978-1-63277-310-4