LM2685MTC/NOPB - NATIONAL SEMICONDUCTOR

LM2685

LM2685 Dual Output Regulated Switched Capacitor Voltage Converter

Literature Number: SNVS055B

LM2685

OBSOLETE

September 22, 2011

Dual Output Regulated Switched Capacitor Voltage

Converter

General Description

The LM2685 CMOS charge-pump voltage converter operates

as an input voltage doubler, +5V regulator and inverter for an

input voltage in the range of +2.85V to +6.5V. Five low cost

capacitors are used in this circuit to provide up to 50mA of

output current at +5V (± 5%), and 15mA at −5V. The LM2685

operates at a 130 kHz switching frequency to reduce output

resistance and voltage ripple. With an operating current of

only 800µA (operating efficiency greater than 80% with most

loads) and 6µA typical shutdown current, the LM2685 is ideal

for use in battery powered systems. The device is in a small

14-pin TSSOP package.

Features

■+5V regulated output

■Inverts V05(+5V) to VNEG(−5V)

■Doubles input supply voltage

■TSSOP-14 package

■80% typical conversion efficiency at 25mA

■Input voltage range of 2.85V to 6.5V

■Independent shutdown control pins

Applications

■Cellular phones

■Pagers

■PDAs

■Handheld instrumentation

■3.3V to 5V voltage conversion applications

Typical Application and Connection Diagram

10110001

10110002

14-Pin TSSOP

Ordering Information

Order Number Package Type NSC Package

Drawing Supplied As

LM2685MTC TSSOP-14 MTC14 94 Units, Rail

LM2685MTCX TSSOP-14 MTC14 2.5k Units, Tape and Reel

101100 Version 7 Revision 3 Print Date/Time: 2011/09/22 14:26:35

LM2685 Dual Output Regulated Switched Capacitor Voltage Converter

Pin Descriptions

Pin No. Name Function

1 VIN Power supply input voltage.

2 GND Power supply ground.

3 VNEG Negative output voltage created by inverting V05.

4 VNSW VNEG output connected through a series switch, NSW.

5 CE Chip enable input. This pin is high for normal operation and low for shutdown. (See Shutdown and

Load Disconnect section in the Detailed Device Description division).

6 SDP Positive side shutdown input. This pin is low for normal operation and high for positive side shutdown

and VPSW load disconnect. (See Shutdown and Load Disconnect section in the Detailed Device

Description division).

7 SDN Negative side shutdown input. This pin is low for normal operation and high for negative side shutdown

and VNSW load disconnect. (See Shutdown and Load Disconnect section in the Detailed Device

Description division).

8 C2−The negative terminal of inverting charge-pump capacitor, C2.

9 C2+The positive terminal of inverting charge-pump capacitor, C2.

10 V05 Regulated +5V output.

11 VPSW V05 output connected through a series switch, PSW.

12 VDBL Voltage Doubler Output. (2.85V ≤ VIN ≤ 5.4V. See Voltage Doubler section).

13 C1+The positive terminal of doubling charge-pump capacitor, C1.

14 C1−The negative terminal of doubling charge-pump capacitor, C1.

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LM2685

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VIN to GND or GND to

VNEG)6.8V

SDN, SDP, CE (GND − 0.3V) to

(VIN + 0.3V)

V05 Continuous Output Current 80mA

V05 Short-Circuit Duration to GND

(Note 2) Indefinite

Continuous Power Dissipation (TA =

25°C) (Note 3) 600mW

TJMAX (Note 3)150°C

θJA (Note 3)140°C/W

Operating Ambient Temp. Range −40°C to 85°C

Operating Junction Temp. Range −40°C to 125°C

Storage Temp. Range −65°C to 150°C

Lead Temp. (Soldering, 10 sec.) 300°C

ESD Rating (Note 4) 2kV

Electrical Characteristics

Limits with standard typeface apply for TJ = 25°C, and limits in boldface type apply over the full temperature range. Unless

otherwise specified VIN = 3.6V, C1 = C2 = C3 = C5 = 2.2µF. C4 = 4.7µF (Note 5)

Symbol Parameter Conditions Min Typ Max Units

V+Supply Voltage 2.85 6.5 V

IQSupply Current No Load 800 1600 µA

No Load, VIN = 6.5V 300 600

ISD Shutdown Supply Current VIN = 6.5V 6 30 µA

VSD Shutdown Pin Input Voltage for CE,

SDP, SDN

Logic Input High @ 6.5V 2.4 V

Logic Input Low @ 6.5V 0.8

IL (+5V) Output Current at V05 2.85V < VIN < 6.5V 50 mA

RO (−5V) Output Resistance at VNEG IL = 15mA (Note 6) 20 40 Ω

FSW Switch Frequency 85 130 180 kHz

PEFF Average Power Efficiency at V05 2.85V ≤ VIN ≤ 6.5V

IL = 25mA to GND

82 %

V05 Output Regulation 1mA < IL < 50mA, VIN = 6.5V (Note

4.848 5.05 5.252

1mA < IL < 50mA, VIN = 6.5V (Note

4.797 5.05 5.303

GLINE Line Regulation 2.85V < VIN < 3.6V 0.25 %/V

3.6V < VIN < 6.5V 0.05

GLOAD Load Regulation 1mA < IL < 50mA, VIN = 6.5V 0.3 1.0 %

RSW Series Switch Resistance VNEG to

VNSW

VIN > 2.85V 1.5 Ω

V05 to VPSW 5.0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: V05 may be shorted to GND without damage. However, shorting VNEG to V05 may damage the device and must be avoided. Also, for temperature above

85°C, V05 must not be shorted to GND or device may be damaged.

Note 3: The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX — TA)/θJA, where TJMAX is the maximum junction temperature, TA is

the ambient temperature and θJA is the junction-to-ambient thermal resistance of the specified package.

Note 4: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 5: In the typical operating circuit, capacitors C1 and C2 are 2.2µF, 0.3Ω maximum ESR capacitors. Capacitors with higher ESR will increase output resistance,

reduce output voltage and efficiency.

Note 6: Specified output resistance includes internal switch resistance and ESR of capacitors. See the Detailed Device Description section.

Note 7: The 50 mA maximum current assumes no current is drawn from VDBL pin. See Voltage Doubler section in the Detailed Device Description.

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101100 Version 7 Revision 3 Print Date/Time: 2011/09/22 14:26:35

LM2685

Typical Performance Characteristics Unless otherwise specified, TA = 25°C, VIN = 3.6V.

Supply Current vs Input Voltage

10110006

Supply Current vs Temperature

10110007

Efficiency vs Load Current

10110008

Output Voltage (V05) vs.

Load Current

10110009

V05 Voltage vs.

Input Voltage

10110021

Output Resistance (VNEG) vs. Temperature

10110010

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LM2685

Output Resistance (VDBL) vs.

Input Voltage

10110011

Output Resistance (VDBL) vs. Temperature

10110012

Switch Frequency vs. Temperature

10110013

Line Transient Response (with 5mA Load)

10110014

A: INPUT VOLTAGE: VIN = 3.2V to 6.0V, 5V/div

B: OUTPUT VOLTAGE: VPSW: 100mV/div

C: OUTPUT VOLTAGE: VNSW: 100mV/div

V05 Load Transient Response

10110015

A: LOAD CURRENT: ILOAD = 5mA to 39.6mA, 10mA/div

B: OUTPUT VOLTAGE: V05: 10mV/div

VNSW Load Transient Response

10110016

A: LOAD CURRENT: ILOAD = 4.4mA to −9.4mA, 10mA/div

B: OUTPUT VOLTAGE: VNSW: 50mV/div

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LM2685

VPSW and VNSW Response to CE

(with 5mA Load)

10110017

A: CE INPUT: 5V/div

B: OUTPUT VOLTAGE: VPSW: 5V/div

C: OUTPUT VOLTAGE: VNSW: 5V/div

V05 Response to SDP (with 5mA Load)

10110018

A: SDP INPUT: 5V/div

B: OUTPUT VOLTAGE: 5V/div

VNSW Response to SDP (with 5mA Load)

10110019

A: SDP INPUT: 5V/div

B: OUTPUT VOLTAGE (VNSW): 5V/div

VNSW Response to SDN

(with 5mA Load)

10110020

A: SDN INPUT: 5V/div

B: OUTPUT VOLTAGE (VNSW): 5V/div

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LM2685

Detailed Device Description

10110003

FIGURE 1. Functional Block Diagram

The LM2685 CMOS charge pump voltage converter operates

as an input voltage doubler, +5V regulator and inverter for an

input voltage in the range of +2.85V to +6.5V. It delivers max-

imum load currents of 50mA and 15mA for the regulated +5V

and the inverted output voltages respectively, with an oper-

ating current of only 800µA. It also has a typical shutdown

current of 6µA. All these performance qualities make the

LM2685 an ideal device for battery powered systems.

The LM2685 has three main functional blocks: a voltage dou-

bler, a low dropout (LDO) regulator, and a voltage inverter.

Figure 1 shows the LM2685 functional block diagram.

VOLTAGE DOUBLER

The voltage doubler stage doubles the input voltage VIN, with-

in the range of +2.85V to +5.4V. For VIN above 5.4V, the

doubler shuts off and the input voltage is passed directly to

VDBL via an internal power switch.

The doubler contains four large CMOS switches which are

switched in a sequence to double the input supply voltage.

Figure 2 illustrates the voltage conversion scheme. When S2

and S4 are closed, C1 charges to the supply voltage VIN.

During this time interval, switches S1 and S3 are open. In the

next time interval, S2 and S4 are opened at the same time,

S1 and S3 are closed, the sum of the input voltage VIN and

the voltage across C1 gives the 2VIn and the voltage across

C2 gives the 2VIN at VDBL output. VDBL supplies the LDO reg-

ulator. It is recommended not to load VDBL when V05 has a

load of 50mA. For proper operation, the sum of VDBL and

V05 loads must not be more than 50mA.

The Schottky diode D1 is only needed for start-up. The inter-

nal oscillator circuit uses the VDBL and GND pins. The voltage

across them must be larger than 1.8V to ensure the operation

of the oscillator. During start-up, D1 is used to charge up the

voltage at VDBL pin to start the oscillator; it also protects the

device from turning on its own parasitic diode and potentially

latching up. The diode should have enough current carrying

capability to change capacitor C3 at start-up, as well as a low

forward voltage to prevent the internal parasitic diode from

turning on. A Schottky diode like 1N5817 can be used for most

applications. If the input ramp is less than 10V/ms, a smaller

schottky diode like MBR0520LT1 can be used to reduce the

circuit size.

10110004

FIGURE 2. Voltage Doubler Principle

+5 LDO REGULATOR

VDBL is the input to an LDO regulator that regulates it to a +5

output voltage at V05. VPSW is tied to V05 through a series

switch PSW. The LDO output capacitor (4.7µF Tantalum)

may be tied to either V05 or VPSW.

INVERTER

From the V05 output, a −5V output is created at VNEG by

means of an inverting charge pump. This negative output is

unregulated, meaning that it's output will droop as the load

current at VNEG increases. The inverter contains four large

CMOS switches which are in a sequence to invert the input

supply voltage. Figure 3 illustrates the voltage conversion

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101100 Version 7 Revision 3 Print Date/Time: 2011/09/22 14:26:35

LM2685

scheme. When S1 and S3 are closed, C1 charges to the sup-

ply voltage V05. During this time interval, switches S2 and S4

are open. In the second time interval, S1 and S3 are open;at

the same time, S2 and S4 are closed, C1 is charging C2. After

a number of cycles, the voltage cross C2 will be pumped to

V05. Since the anode of C2 is connected to ground, the output

at the cathode of C2 equals −(V05) when there is no load cur-

rent. The output voltage drop when a load is added is deter-

mined by the parasitic resistance (Rds(on) of the MOSFET

switches and the ESR of the capacitors) and the charge trans-

fer loss between capacitors.

10110005

FIGURE 3. Voltage Inverter Principle

SHUTDOWN AND LOAD DISCONNECT

In addition to the nominal charge pump and regulator func-

tions, the LM2685 features shutdown and load disconnect

circuitry. CE (chip enable) and SDP (shutdown positive) per-

form the same task with opposite input polarities. When CE

is low or SDP is high, all circuit blocks are disabled and V05

falls to ground potential. This is the same result as when the

die temperature exceeds 150°C (typical), and the device's in-

ternal thermal shutdown is triggered.

Forcing SDN (shutdown negative) high disables only the in-

verting charge pump. The doubling charge pump and the LDO

regulator continue to operate, so the V05 and the VPSW remain

at 5V.

The LM2685 incorporates two low impedance switches tied

to the V05 and VNEG outputs, because some special applica-

tions require load disconnect and this is achievable via the

switches. Switch PSW connects V05 to VPSW, and switch NSW

connects VNEG to VNSW. In normal operation, these switches

are closed, allowing 5V loads to be tied to either V05 or

VPSW and −5V loads to be tied to either VNEG or VNSW. Driving

SDN high opens switch NSW only, while forcing CE low or

SDP high, opens both the PSW and NSW.

Application Information

CAPACITOR SELECTION

The output resistance and ripple voltage are dependent on

the capacitance and ESR values of the external capacitors.

VOLTAGE DOUBLER EXTERNAL CAPACITORS

The selection of capacitors are based on the specifications of

the dropout voltage (which equals IOUT ROUT), the output volt-

age ripple, and the converter efficiency.

where RSW is the sum of the ON resistance of the internal

MOSFET switches as shown in Figure 2.

The peak-to-peak output voltage ripple is determined by the

oscillator frequency, the capacitance and ESR of the capac-

itor C3.

High capacitance (2.2µF to higher), low ESR capacitors can

reduce the output resistance and the voltage ripple.

where IQ(V+) is the quiescent power loss of the IC device, and

I2LR is the conversion loss associated with the switch on-re-

sistance, the two external capacitors and their ESRs.

Low ESR capacitors (table to be referenced) are recommend-

ed to maximize efficiency, reduce the output voltage drop and

voltage ripple.

+5 LDO REGULATOR EXTERNAL CAPACITORS

The voltage doubler output capacitor, C3, serves as the input

capacitor of the +5 LDO regulator. The output capacitor C4,

must meet the requirement for minimum amount of capaci-

tance and appropriate ESR (Equivalent Serving Resistance)

for proper operation. The ESR value must remain within the

regions of stability as shown in Figure 4, Figure 5 and Figure

6 to ensure output's stability. A minimum capacitance of 1µF

is required at the output. This can be increased without limit,

but a 4.7µF tantalum capacitor is recommended for loads

ranging upto the maximum specification. With lighter loads of

less or equal to 10mA, ceramic capacitor of at least 1µF and

ESR in the milliohms can be used. This has to be connected

to VPSW pin instead of the V05 pin.

Any output capacitor used should have a good tolerance over

temperature for capacitance and ESR values. The larger the

capacitor, with ESR within the stable region, the better the

stability and noise performance.

10110025

FIGURE 4. ESR Curve for COUT = 2.2µF

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LM2685

10110026

FIGURE 5. ESR Curve for COUT = 4.7µF

10110027

FIGURE 6. ESR Curve for COUT =10µF

INVERTER EXTERNAL CAPACITORS

As discussed in the +5 LDO Regulator External Capacitors

section, the output resistance and ripple voltage are depen-

dent on the capacitance and ESR values of the external

capacitors. A minimum of 1µF capacitor with good tolerance

over temperature for capacitance and ESR values. The ca-

pacitance value can be increased without limit while still main-

tain high low ESR value. 2.2µF capacitors are recommended

for the two external capacitors, C2 and C5 of the inverter.

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LM2685

Physical Dimensions inches (millimeters) unless otherwise noted

TSSOP-14 Package

14-Lead Thin Shrink Small-Outline Package

For Ordering, Refer to Ordering Information Table

NS Package Number MTC14

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LM2685

Notes

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101100 Version 7 Revision 3 Print Date/Time: 2011/09/22 14:26:35

LM2685

Notes

LM2685 Dual Output Regulated Switched Capacitor Voltage Converter

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