EXHIBIT 69 EXHIBIT 69 Data Sheet September 2007 t_s| 232"" TruePHYTMET1011C Gigabit Ethernet Transceiver Features Introduction n lOBa.se-T, l()OBase-'l`X, and lO00Base-T The LS1 ETl0l 1C is a Gigabit Ethemet transceiver fabri cated on a single CMOS chip. Packaged in either an 128 pin TQFP, an 84-pin MLCC, or a 68-pin MLCC, the ETl()l 1C is built on 0.13 um technol ogy for low power consumption and application in sen/er and desktop NIC cards. it features single power supply operation using on-chip regulator controllers. The 10/100/ l00()Base-T device is fully compliant with lEEE(R) 802.3, 8()2.3u, and 802.3ab standards. gigabit Ethemet transceiver: A 0.13 pm process - 128-pin TQFP and 84-pin MLCC: ORGMII, GMII, Mll, RTBI, and TBI interfaces to MAC or switch -- 68-pin MLCC: 0 RGMII and RTBI interfaces to MAC or switch ll Low power consumption: -- Typical power less than 750 mW in 1000Basc-T mode ---- Advanced power management - ACPI compliant wake-on-LANsupport II Ovcrsarnpling architecture to improve signal integrity and SNR .. Optimized, extended performance echo and NEXT fil ters 11All-digital baseline wander correction ll Digital PGA control n On-chip diagnostic support I1 Automatic speed negotiation n Automatic speed downshilt n Single supply 3.3 V or 2.5 V operation: -- On-chip regulator controllers # 3.3 V or 2.5 V digital I/O ---- 3.3 V tolerant l/O pins (MDC, MDIO, COMA, RESET_N, and JTAG pins) -- l .0 V or 1.1 V core power supplies 4 1.8 V or 2.5 V for transformer center tap It JTAG n ETIO IlC is a pin-compatible replacement for the ETl0l1 device n Commercial- and industrial--temperatureversions avail able The F.Tl()11C uses an oversampling architecture to gather more signal energy from the communication channel than possible with traditional architectures. The additional sig nal energy or analog complexity transfers into the digital domain. The result is an analog front end that delivers robust operation, reduced cost, and lower power consump tion than traditional architectures. Using oversampling has allowed for the implementation ot a fractionally spaced equalizer. which provides better equalization and has greater immunity to timing j itter. resulting in better signal-to-noise ratio (SNR) and thus improved BER. In addition. advanced timing algorithms are used to enable operation over a wider range of cabling plants. Tr:ueP{-IY ETl01lC I Data sheet Gigabit Ethernet Transceiver September 2007 Table of Contents Contents Page Features.........i...........,. Introduction Functional Description Oversampling Architecttue.......... Automatic Speed Downsbift........ Transmit Functions Receive Functions........................... Autonegotiation Carrier Sense (128-Pin TQFP and Timing ResetTiming .6 ............7 84-Pin MLCC Only) Digital Loopback Analog L0opback........ Low-Power Modes................ Pinlnfonnation .... Pin Diagram, 128-Pin TQFP Pin Diagram. 84-Pin MLCC Pin Diagram. 68'Pin MLCC Pin Descriptions, 128-Pin TQF1'. 84-Pin MLCC, and 68-Pin MLCC ..................................................... MAC lnterface ....... Management Interface Configuration interface l,EDs Interface .......... Media-Dependent Interface: Transformer lnterface Clocking and Reset .. 15 22 27 29 31 32 33 34 34 35 Regulator Control Power,Ground,andNo Connect Cable Diagnostics............................... 36 Register Address Map.............. Register Functions/Settings Electrical Specifications ...... Absolute Maximum Ratings .......... 37 37 38 62 62 62 Register Description RecommendedOperatingConditions 63 .......................... .. 67 (128-Pin TQ1-"Pand 84-1-`inMLCC Only) ................. .. 67 GMll l()()0Base-T Receive Timing (128-Pin TQFP and 84-Pin MLCC Only) ................. .. 68 69 RG3/lll 1()O0Basc-TTransmit 'l`iming.......... RGMH1000Basc-TReceiveTiming M111()0Base-TX Transmit Timing........ Mll l0OBase-TX Receive Timing M11 l0Base-T Transmit Timing 2 Clock JTAG Package Diagram, 128-Pin TQFP Package Diagram, 84--PinMLCC Package Diagram, 68-Pin MLCC ()rdering1nfo1-mation ............... Table Regulator Control Resetting the 1~1'l`101 1C......... Loopbaek Mode Timing Specification .................. GM11 1000Base-T Transmit Timing Page M11 1OBase-T Receive Timing ...... Serial Management Interface Timing......... Link Monitor..................... DeviceElectricalCharacteristics Contents 71 73 74 .......76 .......77 .......78 .......79 .......8O .......8l .......82 .......83 .......84 Page Table 1. ETIOI 1C Device Signals by Interface, 128-Pin TQFP, 84-Pin 15 and 68-Pin MLCC ....................... .....2O Table 2. Multiplexed Signals on the ETl011C Table 3. GMII Signal Description (10l)()Base-T Mode) (128-pin TQFP and 84-pin MLCC only) ................................. .......22 `Table 4. RGM11Signal Description (l0l)()Base-T Mode) ................................. ..23 Table 5. Mll Interface (1OOBase-TX and 1()Base-'1`)(l28~Pin TQFP and 84-Pin MLCC Only).............. .................. ..4<4'I24 Table 6. Ten-Bit Interface (1000Base-T) (128-Pin TQFP and 84-Pin MLCC Only).. .....25 Table 7. RTBI Signal Description .....26 (1000Base--TMode) ........ 27 Table 8. Management FrameStructure .....28 Table 9. Management 1nterfaee............... .....29 Table 10 . Configuration Signals............., Table 11 31 32 Table 12 . Transformer lnterfaceSignals 33 Table 13 . Clocking and Reset ............. 34 Table 14 ..1'1`AGTest Interface ......... I{.--'34 Table 15 . Regulator Control 1nterfaee..t...... 35 Table 16 . Supply Voltage Combinations........ .....35 Table 17 . Power. Ground, and No Connect........ .....36 Table 18. CableDiagnostic Functions .....37 Table 19. Register Address Map.............. . I4QI37 Table 20 . Register Type Definition Table 21 . Control Register--Address (1 .38 39 Table 22 . Status Register`/Xddress 1........... ......4(1 Table 23 . PHY identifier Register 1--Address 2 ......4O Table 24 . PHY Identifier Register 2---Address 3 Table 25 . Autonegotiation Advertisement Rcgister-- Address 4 ................................. ........4l Table 26 . Autonegotiatlon Link Partner Ability Register----Address5 ................................ .. 42 Table 27 . Autonegotiation Expansion Register --Address 6 ..............................................,.....43 75 LS1 Corporation Data Sheet September 2007 TruePH YET10l1C Gigabit Ethernet Transceiver Table of Contents (continued) Table Page Table 28 . Autonegotiation Next Page Transmit Register--Address 7...................................... ..43 Table 29. Link PartnerNext Page Register Acldress 8 ....................................................... ..44 Table 30 1000 Base-T Control Register---- Address 9 .................... .......................... ..45 Table 31 lOO()Base-T Status Register ---- 46 Address l0 ....................................... 47 Table 32 Reserved Registers--Addresses ll--l4 47 Table 33 Extended Status Rcgister---Address l5 47 Table 34 Reserved Registers--Acldresses 16-17 48 Table 35 Pl lY Control Register 2----Addrcss 4`) Table 36. MDI/MDl-X Configuration 49 Table 37. MDI/MDI-X Pin 50 Table 38 Loopback Control Register--Address Table 39. Loopback Bit (0.14) and Cable Diagnostic Mode Bit (23.13) Settings for SO Loopback Mode ...... ................... Sl Table 40. RX Error Counter Register-Address 20 Table 41 Management Interface (MI) Control 51 Register--~Address 2l ......................... 52 Table 42. PIIY Configuration Rcgister---Address 53 Table 43 PHY Control Register--/Xddress Table 44. lnterrupt Mask Register--Address 24 55 Table 45 Interrupt Status Register--~Address 25 56 Table 46. PllYStatus Register---Address 26 57 Table 47. LED Control Register l---Address 58 Table 48. LEDControl Register 2*/\ddress28 58 Table 49. LEDControl Register 3--Address 29 Table 50 . Diagnostics Control Register (TDR Mode}--Address 30 ............................ ..59 Table 51 Diagnostics Status Register (TDR Mode)--Address 31 ............................ ..60 Table 52 Diagnostics Control Register 6] (Link Analysis M0de)--Addrcss 30 Table 53 . MD]/MDT-X Configuration for l00OBase-T with C and D Swappcd/Not Swapped .............61 Table 54. Absolute Maximum Ratings ............................. ..62 Table 55 . ETIOI lC Recommended 62 Operating Conditions................. Table 56 . Device Charactei'lstios--3.3 V Digital l/(J Supply (DVDDIO) ...................... ..63 l,Sl Corporation Table Table 57 Device Characteristies-----2.5V Digital l/O Supply (DVDDIO) Table 58 ET] 01lC Current Consumption l000Base-T ..................................... Table 59 ETl0l lC Current Consumption l0OBase~TX .................................. .. Table 60 ET] Ol 1C Current Consumption l0Base-T ......... Table 6l ETlOl 1C Current Consumption l0Base-T idle .................................. Table (>2 ET1Ol lC Current Consumption Hardware Powerdown ................... .. Table 63 ETl0l 1C Current Consumption Low Power Energy Detect (LPIIZD) Table 64 ET 101 1C Current Consumption Standby Powerdown ..................... .. Table 65 lETlO11C Current Consumption Software Powerdown Table 66. GMll l0tl(lBase-T Transmit Timing .. Table 67 GMll l000Base-T Receive Tirning.... Table 68 RGMll l0O0l3ase-T Transmit Timing Table 69. RGMII l0()0Base-T Transmit Timing Table 70. RGMII lO00Base-T Receive Timing. Table 71 RGMII lO0()Base-T Receive Timing. Table 72 l\/ill l00Base-TX Transmit Timing Table 73 Mll l0()Base-TX Receive Timing...... Table 74 Mll l0Base-T Transmit Timing Table 75 Mll l0Base-T Receive Timing........... Table 76 Serial Management Interface Timing. Table 77 Reset Timing .................................... .. Table 78 Clock Timing............. Table 79 JTAG Timing................ Table 80 Ordering Information Page TruePH YET101lC Gigabit Ethernet Transceiver Data Sheet Septem ber 2007 Table of Contents Figure Page Figure l. E'l`1011C Block Diagram........ Figure 2. Leopbaek Functionality Figure 3. Digital Loophack ......................................... Figure 4. Replica and Line Driver Analog Loopback Figure 5. External Cable Loopbaek ........... Figure 6. Pin Diagram for E'l`l0l TC in 128-Pin TQFP Package (Top View) ............ .. 12 Figure 7. Pin Diagram for ETIOI lC in 84-PinMLCCPackage(TopView) 13 Figure 8. Pin Diagram for ETlOl1C in 68--PinMLCC Package (Top View) Figure 9. ET1()l l C Gigabit Ethernet Card l4 BlockDiagram.......... Figure10.GMIIMAC-PHYSignals Zl 22 Figure Figure Figure Figure Figure Figure 4 . 23 ll. RGMll MAC-PHY Signals......... 24 I2. Mll Signals ....... 25 13. Ten-Bit Interface 26 14. Reduced Ten-Bit Interface 15. GMT] l()0()Base-T Transmit Timing................. 67 16. GMII l00OBase-T Receive Timing ................ .. 68 (continued) Figure Page Figure l7 RGMII l00OBase-T Transmit Timing-- Trace Delay ......................... ...... Figure 18 RGMII lOO0Base-T Transmit 'l"iming~- Internal Delay .............................................. ..7O Figure l9. RGMTI l()0OBase-T Receive Timing-- Trace Delay .................................................7l RGMII l00OBase-T Receive Timing-- Figure 20. Internal Delay ....................... .. Figure 21 MII lO0Base-TX Transmit Timing....................73 Figure 22 .Mll l00Base-TX Receive Timing........ Figure 23 MII 1OBase-TTransmit Timing Figure 24 MII 10Base-T Receive Timing. Figure Figure Figure Figure Management interface Timing 25 Serial 26 ResetTiming............................. 27 Clock ....... ..80 28 JTAG Timing......... LS1 Corporation Data Sheet September 2007 TruePH YETl011C Gigabit Ethernet Transceiver Functional Description The LS1 ETl01lC is a Gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four UTP pairs of category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using five-level pulse-amplitude modulation (PAM). Figurc l is a block diagram of its basic configuration. it if GTX_CLK TX_CLK TXD[7:0] TX_ER TX_EN u ,,,/` / , ma .. GM" H PMAA NEXT Cancellers M PCS RX_C LK RXD|_7:0] Echo Canceller 6 RX ER _ RX_DV COL CRS LEDS LEDSI Confls MDIO MDlNT_N DAG I I ADC BLW Gain Correction Control PGA @ Trellis Timing Clock Decoder Control Generator I lmemlce JTAGI Test Negafiaflon 1OBA$E-T : Management I TRD[0--3]t Hybrld : Config PHYAD[4 :0] MDC Transmit Shaping MlRegisters RSET TCK TRST_N TMS rm TDO SYS_CLK XTAL_1 XTAL__2 RESET_N Figure 1. ETl011C Block Diagram Oversampling Architecture Automatic Speed Downshift The ETl0l 1C architecture uses oversampling techniques to sample at two times the symbol rate. A fractionally spaced feed forward equalizer (FFE) adapts to remove intersymbol interference (lSl) and to shape the spectrum of the received signal to maximize the (SNR) at the trellis decoder input. The l~`Fliequalizes the channel to a fixed target response. Oversampling enables the use ofa fractionally spaced equal izer (FSE) structure for the FFE, resulting in symbol rate clocking for both the FFE and the rcst of the receiver. This provides robust operation and substantial power savings. Automatic speed downshift is an enhanced feature ol`autone gotiation that allows the BT10] 1C to: n Fallback in speed, based on cabling conditions or link partner abilities. l'\ Operate over CAT-3 cabling (in lOBase-T mode). n Operate over two--pairCAT-5 cabling (in l00Base-TX mode). For speed fallback, the ETl0l1C first tries to autonegotiate by advertising l()()0Base--Tcapability. After a number of failed attempts to bring up the link, the ETl0l1C falls back to advertising l00Base--TXand restarts the autonegotiation process. This process continues through all speeds down to l0Base--T.At this point, there are no lower speeds to try and so the host enables all technologies and starts again. PHY configuration register. address 22, bits ll and |() enable automatic speed downshift and specifies if fallback to lOBase-T is allowed. PHY control register. address 23. bits ll and l2 specify the number of failed attempts before downshift (programmable to 1, 2, 3, or 4 attempts). LSI Corporation 5 Data Sheet September 2007 TruePHYETl0l1C Gigabit Ethernet Transceiver Functional Description (continued) Hybrid Transmit Functions l000Base-T Encoder The hybrid subtracts the transmitted signal from the input signal allowing full-duplex operation on each of the twisted pair cables. ln l000Base-T mode, the E'[`l0llC translates 8-bit data Programmable Gain Amplifier (PGA) from the MAC interfaces into 21code group offour quinary symbols that are then transmitted by the PMA as 4D five levcl PAM signals over the four pairs ol`CAT-5 cable. l00Base-TX Encoder ln lO0Base-TX mode, 4-bit data from the media independent interface (Mil) is 4B/SB encoded to output 5-bit serial data at 125 MHZ. The bit stream is sent to a scrambler, and then encoded to a three-level MLT3 sequence that is then transmitted by the PMA. 10Base-T Encoder in l0Base-T mode, the ETl0l 1Ctransmits and receives Manchester-encoded data. The PGA operates on the received signal in the analog domain prior to the analog-to-digital converter (ADC). The gain control module monitors the signal at the output ofthc ADC in the digital domain to control the PGA. lt implements a gain that maximizes the signal at the ADC while ensuring that no hard clipping occurs. Clock Generator A clock generator circuit uses the 25 Mllz input clock signal and a phase-locked loop (Pl,l.) circuit to generate all the required internal analog and digital clocks. A 125 Ml-lz sys tem clock is also generated and is available as an output clock. Analog-to-Digital Converter Receive Functions The ADC operates at 250 MHz oversampling at twice the symbol rate in l0OOBase--Tand lO0Basc-TX. This enables Decoder 100llBase-T In l0O(lBase-Tmode, the PMA recovers the 4D PAM signals alter compensating for the cabling conditions. The resulting code group is decoded to 8-bit data. Data stream delimiters arc translated appropriately, and the data is output to the receive data pins of the MAC interfaces. The GMll receive error signal is asserted when invalid code groups are detected in the data stream. Decoder l00Base-T X In lOOBase--TXmode, the PMA recovers the three-level MLT3 sequence that is descrarnhled and 5B/4B decoded to 4-bit data. This is output to the Mll receive data pins after data stream delimiters have been translated appropriately. The Mil receive error signal is asserted when invalid code groups are detected in the data stream. Decoder 10Base-T innovative timing recovery and fractional skew correction and has allowed transfer of analog complexity to the digital domain. Timing Recovery/Generation The liming recovery and generator block creates transmit and receive clocks for all modes of operation. In transmit mode, the 1OBase-Tand lO0Base-TX modes use the 25 Ml-lz clock input. While in receive mode, the input clock is locked to the rcccivc data stream. l000Base--Tis imple mented using a master-slave timing scheme, where the mas ter transmit and receive are locked to the 25 MHZ clock input, and the slave acquires timing information from the receive data stream. Timing recovery is accomplished by first acquiring lock on one channel and then making use of the constant phase relationship between channels to lock on the other pairs, resulting in a simplified PLL architecture. Timing shifts due to changing environmental conditions are tracked by the ETl0l lC. ln 1OBase-'l`mode. the ET10 l IC decodes the Manchester encoded received signal. 6 LSI Corporation TruePHYET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Functional Description (continued) Autonegotiation Adaptive Fractionally Spaced Equalizer Autonegotiation is implemented in accordance with IEEE 802.3. Thc device supports 10Base-T, l00Base-'1'X, and l00OBase-T and can autonegotiate between them in either halil or full-duplex mode. it can also parallel detect l0Base T or l00Base-TX. lfautonegotiation is disabled, a l0Base-T or lO0Base-TX link can be manually selected via the IEEE The ET101 lC's unique oversampling architecture employs an FSE in place of the traditional FFE structure. This results in robust equalization ofthc communications channel, which translates to superior bit error rate (BER) performance over the widest variety of worst-case cabling scenarios. The all digital equalizer automatically adapts to changing condi Lions. Echo and Crosstalk Cancellers Since the four twisted pairs arc bundled together and not insulated from each other in Gigabit Ethernet, each of the transmitted signals is coupled onto the three other cables and is seen at the receiver as near-cnd crosstalk (NEXT). A hybrid circuit is used to transmit and receive simultaneously on each pair. if the transmitter is not perfectly matched to the line. a signal component will be reflected back as an ccho. Reflections can also occur at other connectors or cable imperfections. The ETIOI 1C cancels echo and NEXT by subtracting an estimate ofthese signals from the equalizer output. Baseline Wander Correction A known issue for 10()0Base-T and l00Base~TX is that the transformer attenuates at low flequencies. As a result, when a large number of symbols of the same sign are transmitted consecutively, the signal at the receiver gradually dies away. This effect is called baseline wander. By employing a circuit that continuously monitors and compensates for this effect, the probability of encountering a receive symbol cn'or is reduced. M11registers. Pair Skew Correction ln Gigabit Ethernet, pair skew (timing differences between pairs ofcable) can result from differences in length or manu facturing variations between the four individual twisted-pair cables. The ETIOI 1C automatically corrects for both integer and fractional symbol timing differences between pairs. Automatic MDI Crossover During autonegotiation, the lZTl0l IC automatically detects and sets the required MD1 configuration so that the remote transmitter is connected to the local receiver and vice vcrsa. This eliminates the need for crossover cables or crosswircd (M1)IX)poi1s. Ifthe remote device also implements auto matic MDI crossover, and/or the crossover is implemented in the cable. the crossover algorithm ensures that only one ele ment implements the required crossover. Polarity Inversion Correction In addition to automatic M1)! crossover that is necessary for autonegotiation, 10Base-T, and 100Base-TX operation, the ET 1011C automatically corrects crossover of the additional two pairs used in 1000Basc-T. Polarity inversion on all pairs is also corrected. Both of these effects may arise if the cabling has been incorrectly wired. Carrier Sense (128-PinTQFP and 84-Pin MLCC Only) The carrier sense signal (CRS) of the MAC interface is asserted by the 1~lT101lCwhenever the receive medium is nonidle. In hall`-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the Pl1Y configuration register, address 22, hit 15. LS1 Corporation 7 Data Sheet Septem ber 2007 TruePHYET10l1C Gigabit Ethernet Transceiver Functional Description (continued) LEDS Link Monitor l000Base-T Once l()00Base-T is autonegotiated and the link is estab lished. both link partners continuously monitor their local receiver status. If the master device determines a problem with its receiver, it signals the slave and both devices cease transmitting data but transmit IDLE. If the master retrains its receiver within 750 ms, then normal operation recom mences. Otherwise, both devices restart autonegotiation. If the slave device determines a problem with its receiver, it ceases transmitting and expects the master to transmit the IDLE sequence. ll'the slave retrains its receiver within 350 ms, normal operation recommcnces when the master signals that its receiver is ready. Il`either receiver fails to reacquire, then autonegotiation is restarted. 100Base-TX In l0OBase-TX mode, the ETl0l 1C monitors the link and determines the link quality based on signal energy. mean square error and scrambler lock. ll'the link quality is deemed insufficient, transmit and receive data are disabled. lf the link had been autonegotiated, then control is handed back to autonegotiation. If the link had been manually set, the l()()Base~'l`Xreceiver is retrained, and the transmitter is set to transmit idle. Once the link quality has been recovered, data transmit and receive are enabled. l0Base--T In lOBase-'l` mode, the l;`T|(ll lC monitors the link and determines the link quality based either on the presence of valid link pulses or valid l(lBase-T packets. If the link is deemed to have failed and the link had been autonegotiated, then control is handed back to autoncgotiation. If the link had been manually set, the ETI 011C continues to try to rees tablish the link. 8 Four status LEDs are provided. These can be used to indicate speed ofopcration, duplex mode, link status, etc. There is a very high degree of programrnability allowed. Hence. the LEDs can be programmed to difi"erentstatus functions from their default value, or they can be controlled directly from the r\/lll register interface. The LED signal pins can also be used for general-purpose I/() if not needed for LED indica tion. Regulator Control The ET l0llC has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or 2.5 V.The on-chip regulator control circuits provide output control voltages that can be used to control two exter nal transistors and thus provide regulated 1.0 V and 2.5 V supplies. Resetting the ET1011C The ETl0l1C provides the ability to reset the device by hardware (pin RESET_N) or via sollware through the man agcment interface. A hardware reset is accomplished by driving the active-low pin RESET_N to Ovolts for a mini mum of20 ps. The configuration pins and the physical address configuration are read during a hardware reset. A hardware reset is required alter powerup in order to ensure proper operation. A software reset is accomplished by setting bit l5 of the con trol register (Mll register address 0. bit 15). The configura tion pins and the physical address configuration are not read during software reset. LS1 Corporation Data Sheet September 2007 TruePHYET10l1C Gigabit Ethernet Transceiver Functional Description (continued) Loopback Mode Enabling loopback mode allows in-circuit testing of the ETlOl lC's digital and analog data path. The ETIOI IC provides several options for loopbaek that test and verify various functional blocks within the PHY. These are digital loopbaek and analog loopbaek. Figure 2 is a block diagram that shows the PHY loopbaek functionality. All Digital Loopback Replica Loopback l l l MAC I Switch PHY Digital PHY AFE T Remote PHY Y RMllLoopback kl Line DriverLoopback Figure 2. Loopback Functionality The loopback mode is selected by setting the respective bit in the PHY loopback control register, Mll register address l9. The default loopbaek mode is digital Mll loopback. Loopback is enabled by writing to the PHY control register, address O,bit l4. Digital Loopback Digital loopback provides the ability to loop the transmitted data back to the receiver via the digital circuitry. The point at which the signal is looped back is selected using the loopback control register with the following options being provided: Mll and all digital. Selecting the Mil option gives a simple loopbaek with minimal latency where the data is looped back directly at the media-independent interface. This loopback is currently set as the default, but it should be noted that it only exercises a small percentage ofthe Pl-lY circuitry. When the all-digital option is selected, the transmitted data is looped back at the inter face between the digital and the analog circuitry, thereby exercising a high percentage of the digital logic. Figure 3 shows a block diagram of digital loopback. MAC! Switch l PHY Digital PHY AFE Figure 3. Digital Loopbaek LS1 Corporation 9 TruePH YET1011C Gigabit Ethernet Transceiver Data sheet September 2007 Functional Description (continued) Analog Loopback Analog loopback provides the ability to loop the transmitted signal back to the receiver within the AFE. The point at which the signal is looped back is selected using the loopback control register with the following options being provided: replica and line driver. Selecting the replica option causes the transmitted signal to be looped back through the replica generation circuitry of the on chip hybrid, thereby allowing most ofthc digital and analog circuitry to be exercised. This loopback mode may be used even when the device is connected to a network because nothing is transmitted to or received from the l\/[Diin this case. Line driver loopback transmits data to and receives data from the MDI. llowever, in general, this loopback may not be used when the device is connected to a network because it could cause an unanticipated response from the link partner. Line driver loopbaek requires 100 Q terminations to be present on the line side of the transformer for each wire pair. For example, for wire pair A, connect a 100 Q resistor between the leads (pins l and 2) ofa short cable plugged into the RJ45. This should also be done for wire pairs B, C, and D. Another way to accomplish this is to connect to a link partner with a short cable and power down the link partner. Figure 4 shows a block diagram of both replica and line driver loopbacks. REPLICA LOOPBAC K MACI Switch PHY Digital PHY AFE R145 Figure 4. Replica and Line Driver Analog Loopback External Cable Loopback External cable loopback loops GMIITx to GM|l Rx via complete digital and analog path and via an external cable. The external cable should have pair A (pins 1 and 2) looped to pair B (pins 3 and 6), and pair C (pins 4 and 5) looped to pair D (pins 7 and 8). This willtest all the digital data paths and all the analog circuits. Figure 5 shows a block diagram of external cable loopback MAC/ PHY PHY 2 Figure 5. External Cable Loopback I0 LS1 Corporation Data Sheet September 2007 Functional Description (continued) Low-Power Modes Hardware Powerdown Mode In Hardware Powerdown, all Pl-IY functions (analog and digital) are disabled. During Hardware Powerdown, SYSgCLK is not available and the Mll registers are not accessible. This is the lowest power mode for the ETl011C. llardware Powerdown is entered when the LPED_EN_N and SYS__CLK__EN__N pins are high (dcassertcd). and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). Low-Power Energy-Detect (LPED) Mode TruePHY ET1011C Gigabit Ethernet Transceiver This powerdown mode is a combination of Standby Power down mode and LPEI) mode. The PLL is running and the PIIY monitors the cable (MDI interface) for energy. If energy is detected. the Ml)lN'l`_N pin is asserted. During this mode, SYS_CLK is available and the Mll registers are not accessible. The host system monitors the MI)INT_N pin and then places the PHY into a regular operating mode in response to the interrupt. This mode is entered when the LPED"EN_N pin is low (asserted), SYS___CLK_EN_Npin is low (asserted), and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). At exit from Standby Powerdown or Standby Powerdown with LPED, the ETIOI lC docs the following: .1 Initializes all analog circuits excluding the PLL. .. Initializes all digital logic and state machines. n Reads and latches the PHY address pins. In LPED mode, the PHY is in a low power state but still monitors the cable (MDI interface) for energy. If energy is detected. the MDINT_N pin is asserted. During LPED mode, SYS_CLK is not available and the Mll registers are not accessible. The host system monitors the MDINT_N pin and then places the PHY into a regular operating mode in response to the interrupt. LPED mode is entered when the I.PED_EN_N pin is low (asserted). SYS__CLK_I5N_Npin is high (deasserted). and either the COMA signal is high (asserted) or the RESET__Nsignal is driven low (asserted). At exit from Hardware Powerdown or LPED modes, the ET l 0 l I C does the following: n Initializes all analog circuits including the PLL. l1 Initializes all Mil registers to their default values (l-l/W configuration pins are reread). Software Powerdown Mode Soflware powerdown is entered when bit I1 of the control register (MII register address 0, bit ll) is set. In software powerdown, all PHY functions except the serial manage ment interface and clock circuitry are disabled. The Mil reg isters can be read or written. If the system clock output is enabled (MII register address 22. bit 4), the 125 Ml-lz system clock will still be available tor use by the MAC on pin SYS_CLK. n Initializes all Mil registers to their default values (H/W configuration pins are reread). At exit from software powerdown, the BT10] l C initializes all digital logic and state machines only. NOTE: The H/W configuration pins and the PHY address pins are not re-read and the Mil registers are not reset to their default values. These operations are only done during reset or recov eiy ii-om hardware powerdown. Standby Powerdown Mode Wake-On-LAN Powerdown Mode In Standby Powerdown, most PIIY functions (analog and digital) are disabled but the PLL is still running. During Standby Powerdown, SYS_CLK is available and the Mil registers are not accessible. Standby Powerdown mode is entered when the LPED_ll\I_N pin is high (deasscrted). SYS_Cl.K_F.N_N pin is low (asserted), and either the COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). ACPI power consumption compliant Wake-On-LAN mode is implemented on the ET] OllC by using the IEEE standard Mll registers to put the PIIY into lOBase-T or l()0Base-TX modes. Clearing the advertisement of l()0OBase-T (M11reg ister address 9, bits 8, 9) and setting the desired l()Base-T and lO0Base--'I`Xadvertisement (MII register address 4, bits 5--8) activates this feature. This must be followed by an autonegotiation restart via the control register (Mil register address 0, bit 9). n Initializes all digital logic and state machines. n Reads and latches the PHY address pins. Standby Powerdown with Low-Power Energy--Detect (LPED) Mode LSI Corporation ll TruePH YETI 011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information Pin Diagram, 128-Pin TQFP >< E 5 Q U7 >< 1:55 _Z vu 0 uvss nxnp] 1 102 Z 101 TXD[3] 3 100 TXDI-1| 4 90 RXms] TXD|5| TXD[6| TxD17| 5 93 97 RXme] RXD[7] NC uvss nvss nvnmo TCK vou nvss nvss 6 X `J6 l]< 9 9-4 XI! 93 H <12 H 91 7 13 90 TRST__N 14 TMS1SYS_ (`LK_l-IN_N 15 89 xx TD!/LPED EN N TDO MAr_n'q_sEl.|u| M/\(` 1+"sum] AVDDL AVSS AVDDH PRES NC LEl)__l.Nwr muss x4 83 NC NC LED_\ 000/SPEED_lm1< VDD LS1 1`) ETIOI 1C $2 I 31 an nvss 24 79 25 78 CTRI._1V0 CTRI._2V5 26 27 23 29 30 77 vun__|usn 7:; DVSS NC NC 75 7-: (`l.K_lN/XTAl.__1 X'l`AL_2 N(` RI3SET_N 31 73 72 32 11 33 70 34 N(" 35 (-9 ms we 36 37 38 NC NC uvumo 115 Zl Z2 nvss v 01> MIX` MDIO M 01 NT_N 35 20 NC COMA VDD nvss as AUTO_>MD|_EN nvss nv & SYS_(`LK 17 M.\(T_II-`_SELI'l] VDD s7 lb ovumo u: ."`m5` L ,. NC PHYAD[I1|fLED_'l'XRX PI-iYAD[1|./|.Eu_|ou Pl lYAD[2] PHYA[)[3] (>7 m-mmg-:1 (>6 NC Nv as -.. --.v;` we _. , Figure 6. Pin Diagram for ET101lC in 128-Pin TQFP Package (Top View) 12 I SI Corpm anon Data Sheet September 2007 TruePHYET10l1C Gigabit Ethernet Transcelver Pill IIlf0l"l113fi0Il (continued) Pin Diagram, 84-Pin MLCC TXD[5]Q 1 63Q vnn TXD[6]Q 2 TXD[7]Q 3 DVDDIDQ 4 TCKQ 5 62 Q 61 Q 60 Q 59 Q vooQ 5 NCQ 7 LS1 NCQ s NCQ 9 ETl0llC RXD[4] RXD[5] RXD[6] RXDU] 58 Q Dvomo 57 Q sv$_cu< 5s Q VDD 55 Q MDC 54 Q M010 NCQ NCQ TRST_NI 10 11 12 TMSlSYS_CLK_EN_NQ 15 51 Q PRES TDI/LPED_EN_NQ 14 50 Q LED_LNKIPAUSE TDOQ 15 49 Q LED_1OGO/SPEED_1000 MAC_|F_SEL[0]Q 1s as Q VDD MAC_|F_SEL[1)Q 17 47 Q CTRL_1V0 MAC_|F_SEL{2]Q 1s VDDQ AVDDLQ 19 20 4a Q 45 Q CTRL_2V5 VDD_REG AVDDHQ 21 53 Q MD\NT__N 52Q nvomo EXPOSED PAD (DVSS AND AVSS) 44 Q Pl-lYAI)[0].'l.ED_TXRX 43 Q PI--l'YAD[l 1.-'1.ED>lou Figure 7. Pin Diagram for ETHNIC in 84-Pin MLCC Package (Top View) LS1 Corporation TruePH YET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Diagram, 68-Pin MLCC E __ _ 51C 50C DVDDIO 1 -:' TCK2 i) VDD I 4 : 5 ; TMS/SYS_CLK__EN_N- e 1 TD|fLPED_EN_N 4sC 47C 46C 45C 44C 7 : TDO- a 1 MAC_1F_SEL[0] 9 : MAC_|F_SEL[1]- LS! ET1011C 43$ ` COMA 121 von 1:1; XTAL_2117 MDIO MDlNT__N uvomo PRES LED_LNK/PAUSE 41C voo 40 C] CTRL_1V0 39C CTRL_2\/5 37C PHYAD[O]ILED_T>(RX sac VDD_REG AVDDL 14; AVDDH " 15' CLK IN/XTAL1 15 MDC 42CZl LED_10U0fSPEED_1000 10 1 VDD 11 SYS_CLK 49; vno 3 DVSS_ TR$T_N_ ovnmo ' I_ EXPOSFD PAD (DVSS AND N N AVSS) 36C! PHYAD[1]/LED_1D0 35(I PHYAD[2] Figure 8. Pin Diagram for ETIOHC in 68-Pin MLCC Package (Top View) 14 LS1 Corporation Data Sheet September 2007 Pin Information TruePHYET101lC Gigabit Ethernet Transceiver (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68--PinMLCC Table 1. ET10l1C Device Signals by Interface, 128-Pin TQFP, 84~Pin and 68--PinMLCC Name Description Pad Type Internal Pull-Up/ Pull-Down 3Analog State Pin # I28-Pin TQFP Pin # 84-Pin MLCC MAC: GMIl----GigahitMedia-Independent Interface (128-Pin TQFP and 84-Pin MLCC Only) --- 121 77 GMII transmit clock 0"rx_cu< --124 78 Transmit error TX_ER 79 A 125 Transmit enable TX_EN 3. 2,1, 84. Pull-dovm Transmit data bits ---- 7, 6,5,4,3 128, 'rxn[7;0] -- 10.9 83, 82, 81, 80 72 70 69 --- 97, 98, 99, 100, 105, 106, 107, 59, 60. 61, 62, 65, 66, 67. 68 Z --~ 116 74 Z ---- 115 73 127, 126 --- 113 -- 110 RX_CLK RX_ER RX_DV RXD[7:0] Receive clock Receive error Receive data valid Receive data bits CRS COL Carrier sense Collision detect TXC MAC: RGMII-Reduced Gigabit Media-IndependentInterface 77 --121 RGMII transmit clock I 83, 82. 81, 80 3, 128, Pull-down Transmit data bits 1 Pin # 68-Pin MLCC ---- -- 108 TXD [3 :01 O O 79 72 67, 66 65 64 60 65, 66, 67, 68 55.56 127, 126 'I`X_CTL RXC RXD[3 =0] Transmit control Receive clock Receive data bits 1 Z Z O O -- 125 --- 113 ---- 105.106, 107, 108 RX~CTL TX_CLK TX_ER TX_EN TXD[3 :0] RX_CLK RX_11R RX__DV RXD[3:0_] Receive eontrol Z O -- 109 63 69 57 58 MAC: 1VIIl--1VIedia-IndependentInterface (128-Pin TQFP and 84-Pin ML CC Only) 75 -- 118 Z O M11transmit clock 78 -- I24 I Transmit error Transmit enable Transmit data bits Pull-down Receive clock Receive error Receive data valid Receive data bits -- 125 79 --- 3, 128, 127, 126 83, 82, 81, 80 ----- 113 -- 110 72 70 ----- 109 69 i 105,106, 65. 66, 67, 68 107. 108 CRS COL LS1 Corporation Carrier sense Collision detect O Z W 116 74 O Z ------ 115 73 15 TruePHYET101lC Gigabit Ethernet Transceiver Data Sheet September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type Internal 3--State Analog Pnll-Up/ Pull-Down Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLC C 77 MAC: TBl--Ten-Bit Interface (128-Pin TQFP and 84-Pin NILCC Only) PM/\_ TX_CLK T131transmit clock I __ _- i 121 TXD[9:O] Transmit data bits 1 Pull-down -- 7 124,125, 7, 6, 78, 79, 3, 2, U11 5,4,3,128, 1,84, '1`xn[710] 127,126 83,82,141, -- 80, PMA_RX__CLK[()] TB1 receive clock Receive data bits RXD[9:()] O -- Z 113 72 O --- Z 110, 109, 97, 70, 69, 59, O O PMA_RX_ c1.1<[1] T131receive clock Valid comma detect COMMA -- __ Z __ 98, 99,100, 60, 61. 62, 105, 106, 107, 108 65, 66, 67, 68, 115 73 116 74 MAC. RTBl----Reduced Ten-Bit I nterface TXC TXD13 :0] 'r><,c"r1, RXC RXD[3:0] RTB1transmit clock Transmit data bits Transmit control RTBI receive clock Receive data bits I _ _ 121 77 63 3, 128, 127, 126 68, 67, 66, 65 64 60 I ._ __ 125 8 3, 82, 81, 80, 79 O -- Z 113 72 0 ,~- Z 105. 106,10 7. 54, 55, 56. 57 109 65, 66, 67 68 69 39 25 19 41 26 45 28 20 22 47 29 34 35 37 38 32 1 Pull-down ~--~ 108 RX_CTL Receive control O ------ Z 58 MD1:Transformer Interface `I'RD[0]+ 'l`RD[O]-- TRD[1j+ TRD[1 1 TRD [2]+ TRD[2] TRD[3]+ TRD[3]-- RSET 16 Transmit and receiv (3 differemial pair Transmit and receive ciifferential pair Transmit and receiv 6 differential pair Transmit and receiv 6 differential pair Analog reference resis tor l/O ---- A 1/O -- -- A 1/o - A 54 56 1/O -- -- A 60 62 1/O ----- -- A 52 23 28 29 31 32 26 LS1 Corporation Data Sheet September 2007 Pin Information TruePH YET1011C Gigabit Ethernet Transceiver (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 1. ET10l1C Device Signals by Interface, 128-Pin TQF P, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type Internal Pull-Up/ Pull-Down 3-State Analog Pin # 128-Pin Pin # 84-Pin MLCC Pin # 68-Pin MLC C 69, 7l_ 70 40, 41, 42, 43, 44 34, 35, 36, 37 TQFP Manage ment Interfa CB Pl-lYAD[4:O] Pl--lYaddress 4--l l, l. L Pull~d0wn -- --~ l./O PHY address 0 67, 68, Pl-IYAD l/O Pull-up I Pul l-down 91 55 I/0 Pull~up 90 54 48 47 89 53 46 Pull-up Pull-down 82 49 50 42 Pull-up Pull-down Pull-down Pull-down 21 18 l6 9 19 17 10 20 18 Pull-up Pull-up 15 13 6 l6 l4 7 87 5l 44 [310] MDC MDlO MDlN'l`_N Management interface clock Management data I/O Management interface inter rupt O Con figuration` s P EED_l0()0 PAUSE AU'l`O_MDl EN M/\CHlF_SEL[O] MAC_IF_SE L [1] MAC_lF_SEL[2] SYS CLK EN N I`PED_EN_N PRES l00()Base-T speed select Pause mode Auto-MDI detection enable MAC interface select 0 MAC interface select 1 MAC interface select 2 System clock enable Low power energy detection enable Precision resistor l 85 A 43 ll Configuration signal s are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configura tion and later to sel ect the polarity to drive the LEDS. LS1 Corporation l7 TruePHYET101lC Gigabit Ethernet Transceiver Pin Information Data Sheet September 2007 (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 1. ET|0l1C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68--PinMLCC (continued) Name Description Pad Type Internal 3-State Pull-Up/ Pull-Down Analog Pin # I28-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC 42 LED Interface 1.2111000 LED_1.NK LED_TXRX LED_l00 1000Base-T LED Link established LED O Pull-up -- O Pull~d0wn --~ General-purpose LED General-purpose LED l/() Pull-up 49 50 44 l/O Pull-down 4 43 43 37 36 JTAG TCK TR S'1`_N TMS TD I TDO Test clock Test reset Test mode select Test data input Test data output Pull-up A 5 Pull-down 12 Pull-up Pull-up -- -- 13 Pull-up -- 15 l4 Clocking and Reset CLKWIN XTAL_l XTAL_2 SYS_CLK RESE'l`_N COMA Reference eloek input Reference crystal input Reference crystal System clock Reset l/O l/O l/O () Hardware powerdown l A A A l Pull-down 22 22 l6 l6 23 l7 57 50 24 l8 12 -- Regulator Control CTRL__lvo CTR L_2V5 Regulator control 1.0 V Regulator control 2.5 V O A 47 O A 46 40 39 1 Configuration signals are 1nultiplexed with the LED controls During a reset, the status of the configuration pins are latched and used to set the configura uon and later to select the polarity to drive the LEDs. 18 LS1 Corporation Data Sheet September 2007 TruePH YET101l C Gigabit Ethernet Transceiver Pin Information (continued) Pin Descriptions, 84-Pin MLCC and 68-Pin MCCC (continued) Table 1. ETl01lC Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description Pad Type lnternal 3-State Analog Pull-Up/ Pull-Down TQFP Pin # 84- Pin M LCC Pin # 68-Pin MLCC 45 38 Pin# 128-Pin Power, Ground, and No Conn ect VDD_REG DVDDIO V DD Regulator 2.5 V or 3.3 V supply Digital l/O 2.5 V or 3.3 V supply VDD 77 Vnn 9, 88, 96,111, Digital core 1.0 V sup VDD 119 92,102 Ply nvssl Digital ground ll, 22, 26, 81, 4, 52, 58, 1,413.51 64, 71, 76 53,59. 62 6, 19, 48, 56, 63 3,11,13 41,49, 52 Vss 4 2, 8,12,13,23, 27, 76. 80,93, 95,101,103, 112.117, 123 AVDDH AVDDL Analog power 2.5 V Analog power 1.0 V AVSS2 Analog ground NC Reserved--do not con nect Von Von Vss 30,51 28, 43, 49. 53, 58, 64 21,31 20, 27,30. 33, 36, 39 15, 25 14, 21. 24, 27, 30, 33 29, 40, 42, 46, 48, 50, 55, 57, 61, 63 1,24-,33.35.36, 7,8,9, 37, 38, 44, 59. 65, 66, 72, 73, 10.11 74,75. 104,114, 120, 122 1 Configuranon signals are multiplexed with the LED controls. During a reset, the status of the configuraiion pins are latched and used to set the configura tion and laler to select the polarity to drive the Ll3Ds. 2. All AVSS and DVSS pins share a common ground pin (pad) in the center of the device. l,Sl Corporation 19 TruePH YET1011C Gigabit Ethernet Transceiver Pin Information Data Sheet September 2007 (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC (continued) Table 2. Multiplexed Signals on the ETIOHC Default Pin # I28-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Alternate COL 115 73 com CRS 116 74 PM/\_RX_CLK[1]7 cRs`~ COMMA2 G'l"X_CLK 121 77 I..ED_1.NK 85 50 63 43 l1El)_11)0O 82 49 42 LED TXRX 71 44 37 LED_100 70 43 36 <1rx_cu<' PM/\_Tx_cu<" TXC3' 4 LED_LNK PAUSE; LED 1000 sPEE1_1000-` LElJ_TXRX PH Y/>.n[0]5 LED_100 PHYAD[_ 115 113 RX_CLK Rx_cu< 1-" 72 PM/\_RX_CLK[0]Z 60 RX_ER 1 10 70 RX_DV 109 69 RXC3' 4 __i___2_i_ Rx_ER'-- " RX[)[9] RX_DV1- " RXD[8 12 TDI 16 14 58 7 TMS 15 13 6 TX_ER 124 78 1X_Eli`<5M 'l'X_}:IN 125 79 'I`X__1-1N1` RX_C'l`L.m 'l`Dl LPED_ENwN5 TMS SYS CLK EN N` 'rxr>[911' TXD[8 )2 31 XTALA1 22 64 Tx_c`r1?- 4 16 XTAL 1 CLK_IN 1 _GMH $1g|1a|, 2. TB] signal, 3 . RGMl1 signal. 20 4, RTBI signal. 5. Reset/configuration signai. 6. Mll signal. LS1 Corporation Data Sheet September 2007 TruePH YET1011C Gigabit Ethernet Transceiver Hardware Interfaces The following hardware interfaces are included on the ETl ()1IC G1gabit Ethernet transceiver: .1 MAC interfaces: -- -- -- -- -~ n Configuration interface GMII (l28--pinTQFP/84-pin MLCC only) RGMII MII (128-pin TQFP/84-pin MLCC only) 'l`Bl (128-pin TQFP/84-pin MLCC only) RTBI ll LED interface i. Clock and reset signals n J"l`AGinterfaec n Regulator control fl Media-dependent interface n Power and ground signals n Management interface Several of the pins of the MAC interface are multiplexed, but they are designed to be interchangeable so that the device can change the MAC interface once the transmission capabilities (1000Base-T, l0OBasc-TX, and lOBase-T) are established. The following diagram shows the various interfaces on each ET101lC and how they connect to the MAC and other support devices in a typical application. ETl0llC Gigabit Ethernet PHY <srx_cu< u:1)_io0 Q; TX_CLK LE Defxkp Y "rxr>[7=0] LED_1 000 TX_ER TX_EN LED_LNK RX___CLK RXD[7:0] RX_ER RX_DV COL Q cRs ET1011C MAC__|F_SEL[2:0] PHYAD[4:U] MDC MDIO MD|NT_N TCK TR$T__N ms TDI rno TRD[O]+l TRD[1]+I TRD[2]+I TRD[3]+I RSET VDD_REG -Q CTRL__2V5 CTRL_1V0 COMA RESET__N h - XTAL_1 XTAL_2 Figure 9. ETIOHC Gigabit Ethernet Card Block Diagram LSI Corporation `I I 2.5V Power Plane I :3 efler Plane Data Sheet September 2007 TruePHY ET1011C Gigabit Ethernet Transceiver new Hardware Interfaces (continued) GTX_cLK MAC Interface TXD{7 01 The ET10l1C supports RGMII, GM11.M11,RTBI. and TB1 interfaces to the MAC. The MAC intcrfacc mode is selected via the hardware configuration pins, MAC_1F_SEL[2:()]. Gigabit Media-Independent Interface (GMII) (128-Pin TQFP and 84-Pin MLCC Only) TX_EN Rx_<:|. MAC RX_ER PHY RX_DV axon oi The GMII is fully compliant with IEEE 802.3 clause 35. The GM11interface mode is selected by setting the hardware con CRS CO figuration pins lVIAC_1F_SELl>2:l)]= 000. Figure I0. GMII MAC-Pl-IY Signals Table 3. GMII Signal Description (10lJOBase-TMode) (128-Pin TQFP and 84-Pin MLCC only) Pin Name Pin # I28-Pin TQFP Pin # 84-Pin MLCC Pin Description Functional Description Transmit clock The MAC drives this 125 MI-lz clock signal that is held low during autonegotiation or when operating in modes other than l000Base-T. Transmit error The MAC drives this signal high to indicate a transmit coding error. 124 78 Transmit 125 79 The MAC drives this signal high to indicate that data is available on the transmit data bus. enable 7, 6, 5, 4, 3, 2,1. 84, Transmit data The MAC transmits data synchronized with GTXMCLKto the bits 740 ET101 1C for transmission on the media--dependent(transformer) 3, 128, 83. 82, 81 interface. 127, 126 80 Receive clock The ETIOIIC generates a 125 MHZ clock to synchronize receive 113 72 data. Receive error The ET10 11C drives RX_[-IRto indicate that an error was detected 110 70 in the frame that was received and is being transmitted to the MAC. Receive data The E'l`1011C drives RX_DV to indicate that it is sending recov 109 69 ered and decoded data to the MAC. valid Receive data The ET1011C transmits data that is synchronized with RX_CLK to 97, 98, `)9, 59, 60, 61, the MAC. 100.105. 62. 65, 66, 121 77 67, 68 CRS 106. 107, 108 116 74 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the ETl011C whenever the receive medium is nonidle. In hall' duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit CO1. 115 73 Collision In 1(lBase-T, 1OOBase-TX, and 1000Basc-T halt`-duplex modes, COL is asserted when both transmit and receive media are nonidle. GTX_CLK TXNER 'l`X_l~l1\l 'rxo[7=0] RX_C | .14 Rx_ER RX_DV RXD[7:0] 15. detect 22 LS1 Corporation Data Sheet September 2007 TruePH YET10l1C Gigabit Ethernet Transceiver Hardware Interfaces (continued) . .J><__C_M. Reduced Gigabit Media-Independent interface (RGMII) T2Ql.Fll. . The RGMII interface is fully compliant with the RGMII Rev. 1.3 specification. The RGMll interface mode is selected by setting the hardware configuration pins MAC_lF~SEL[2:0] = l()t) or 110. (See Table it) on page 30 for further informa tion on MAC_lF__SEL pin operation.) "rxcrt l MAC PHY ...._Rl.-.._.. ;_ t__.___ _ RXDa;o __R)<_.Tt-_. Figure ll. RGMII MAC~PHYSignals Table 4. RGMI! Signal Description (1000Base-T Mode) Pin Name TQFP Pin # 84-Pin MLCC 121 77 Pin # 128-Pin TXC rxn[s :0] 3,128, I27, TX_C'l"l, 83, 82, 126 2 1, so 125 79 Pin # 68-Pin MLCC Functional Description Pin Description The MAC drives this 125 MI-I7.clock signal that is held low during autonegotiation. To obtain the 1 Gbit transmission rate, the MAC uses both the positive and negative clock transitions. 68, 67, 66, Transmit data bits The MAC transmits data synchronized with TXC to the ETl0llC for transmission on the l'1'lCCli21-Cipl1 as dent (transformer) interface. The MAC transmits bits 3:0 on a positive transition QFTXC and bits 7:4 on a 63 Transmit clock 64 Transmit control negative transition of TXC. The MAC transmits control signals across this line ('1`X__ERand TX_ EN). The MAC transmits 'l"X__EN` l l3 RXC RXD[3 =0] 105, I06, RX_CTL 72 60 65, 66, 67, 54, 55, 56, 107, 108 68 57 109 69 58 Receive clock Receive data Receive control on a positive transition ol'TXC and TXv_ENand 'l`X__ER1on the negative transition of TXC. The ETl0l ICTgenerates a 125 MHZ clock to syn chronize receive data. T0 obtain the l gigabit trans mission ratc, the ET101 l C uses both the positive and negative clock transitions. The l:ITl0llC transmits data that is synchronized with RX_CLl< to the MAC. The ETlO1lC transmits bits 3:0 on a positive transition of RXC and bits 7:4 on the negative transition of RXC. The El l0llC transmits oontrol signals across this line (RX_ER and RX_l'N).The ETl0l 1C transmits RX_D\/1 on a positive transition of RXC and RX_El\" and RX__ER`on the negative transition of TXC . l. Reference the GMII interface for description of the following parameters: TX_EN, T X_ER, RX__DV,RX__EN, and RX_ER. LSI Corporation 23 TruePHYET10llC Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) 25 MHZ at the GTX_CLK pin. The ET101lC then uses a FIFO to resynchronize data presented synchronously with this reference clock. Media~lndependent Interface (128-Pin TQFP and 84-Pin MLCC Only) TX_CLK The Mll is fully compliant with IEEE 802.3 clause 22. The M11interface mode is selected by setting the hardware con figuration pins MAC_lF_SEL[2:0] = 000. TX_EN TXD(3 0| In l()0Base-TX and 10Base-T mode. the RXD[7:4] pins are driven low by the ETlO1lC and the TXI)[7:4] pins are ignored. They should not be left floating but should be set either high or low. In the M11interface mode, the GTX__CLK pin may be held low. An alternative to the standard M11is provided when operat ing in l0Base-T or l00Base-TX mode by setting hardware configuration pins MAC_lF_SEL[2:0] = 010. in this alternative interface. the MAC provides a reference clock at 2.5 MHZ or RX_CLK MAC EUR PHY Figure 12. M11 Signals Table 5. Ml] Interface (l00Base-TX and l0Base-T) (128-Pin TQFP and 84-Pin MLCC Only) Pin # 128-Pin Pin # Pin 84--Pin Description TQFP MLCC rx_c 1.14 118 75 GTX_CLK 121 77 Pin Name Functional Description Transmit clock In l00Base-TX mode, the ET10l IC generates 25 M1-12reference clocks and in 1OBase-Tmode provides 2.5 MHz reference clocks. MAC_1F_SEL[2:()] = 000-vthis is default behavior. Alternate 1n 10OBase-TX mode, the MAC generates the 25 M112reference clock and transmit clock in 10Base-'1"mode provides a 2.5 MHZreference clock. M/\C_lF_SEL[2:0] I 010. TX_ER TX_1--lN TXD[3:0] RX_CLK RX_ER RX_DV r<xo[310] CRS COL 24 Transmit error Thc MAC drives this signal high to indicate a transmit coding error. Transmit The MAC drives this signal high to indicate that data is available on the transmit data bus. enable Transmit data The MAC transmits data synchronized with TX_C1..Kto the ET1011C for 3, 128, 8 3,82,81, bits 80 transmission on the media-dependent (transformer) interface. 127,126 Receive clock In 100Base-TX mode, the 1?/F10l lC generates 25 MHZ reierence clocks 72 113 and in 10Base-T mode provides 2.5 Ml-lz reference clocks. Receive error The ET1()l 1C drives RX_ER to indicate that an error was detected in the 70 110 frame that was received and is being transmitted to the MAC. Receive data The E'l`lOl1C drives RX_DV to indicate that it is sending recovered and 69 109 valid decoded data to the MAC. 105,106, (>5,66,67, Receivedata The ETlO`l1C transmits data synchronized with RX_CI.K to the MAC. 68 bits 107, 108 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the 116 74 ET 1011C whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register. address 22, bit 15. H5 73 Collision In 10I3ase-T, 1()013ase-TX: and lO00Base-'I`ha1'l`-duplex modes, COL is asserted when both transmit and receive media are nonidle. detect 124 125 78 79 LS1 Corporation Data Sheet September 2007 Hardware TruePHYET1011C Gigabit Ethernet Transceiver Il1tl`f&1S(continued) Ten-Bit Interface (rm) (128-Pin TQFP and 84-Pin MLCC Only) PMA-T`-"`GM" TXD{9] YX__ER ` The 'l`Bl is full) ' compliant with IEEIL 802 . 3 clause 36 . It may be used as an alternative to the GMI I in l000Base-T , mode. The FBI mode is selected by setting the hardware con figuration pins MAC_IF_SEL[2:0] = 001. TXD[8l WEN TXD[7:O] V rxnlm] PMA_RX__CLK MAC RX__CLKPHY rotors] RX_ER nxorsg Rx_ov axon 0] RXD[7:U] MA_RX_CLK[1] COMMA cot CR5 Figure 13. Ten-Bit lnterface Table 6. Ten-Bit interface (1000Base-T) (128-Pin TQFP and 84-Pin MLCC Only) Pin Name Pin # I28-Pin TQFP Pin # Pin Description Functional Description MLCC PMA_TX_cu< l2l 77 TBI transmit clock The MAC drives this 125 MHz clock signal and should be held low during autonegotiation or when operating in modes other than l000Base-T. TXD[9:0] 124, 125, 7, 6, 5, 4, 3, 128. 127, 78, 79, 3, 2, l, 84, 83, 82. Transmit data bits The MAC transmits data synchronized with PM/-\_TX_CLK to the ETlOllC for transmission on the media-dependent (transformer) interface. 84~Pin 81,80 126 ll3 72 RXD[9:O] l l0. 109. 97, 98. 99. I00, lO5, 106, 107, 108 70, 69 59, 60, 61 62, 65, 66, 67. 68 PMA_RX_cu<[1] 115 73 Receive clock COMMA H6 74 Comma signal PM/\_RX_CLK[`()] LS1 Corporation Receive clock The F.Tl()llC generates a 62,5 MHZ clock to synchro nize receive data for the odd oode group. This signal is 180 degrees out of phase from PMA_RX_CLK[l]. Receive data bits The ET1Ol1C transmits data that is synchronized with PMA_ RX_CLK[()] to the MAC. The ETl()l 1C generates a 62.5 MHZ clock to synchro nize receive data for the even code group. This signal is 180 degrees out of phase from PMA_RX__CLl<'.[O]. This signal indicates that COMMA has been detected. 25 TruePH YET1.01lC Gigabit Ethernet Transceiver Hardware Interfaces Data sheet Septgmbef 2007 (continued) ---~-~ p Tm Reduced Ten Bit Interface (RTBI) i T...i><Rta21 The RTBI is fully compliant with RGMII rev 1.3 specifica tion. The RTBI mode is selected by setting the hardware configuration pins MAC_lF_SEL[2:0] = 101 or Ill. (See Table 10 on page 30 for further information MAC_ll*`_S[ZL ------~--~ on n<_cn, t MAC 1 pin operation.) PHY i `__M___5g<_o___ H R><D@.21-... RX _c`r|. * ___ Figure 14. Reduced Ten-Bit Interface Table 7. RTBI Signal Description (1000Base-T Mode) Pin Name TXC Pin Description MLCC Pin # 68-Pin MLCC 121 77 63 Transmit clock Pin # I28-Pin TQFP Pin # 84-Pin Functional Description The MAC drives this I25 Mllz clock signal that is held low during autonegotiation. Transmit data bits The MAC transmits data synchronized with TXC to the ETIO l 1C for transmission on the media-dependent (transformer) interface. The MAC transmits bits 3:0 on a positive transition of TXC and bits 8:5 on a nega tive transition of TXC. 3,128, 83,82,8l 127,126 80 68, 67, 66, 65 'l`X_CTl. I25 79 64 RXC I13 72 60 RXD[_3:0] I05, 106, I07, 108 65, 66, 67, 68 54, 55, 56. 57 Receive data The ETIOI l C transmits data that is synchronized with RXC to the MAC. The ETIOI IC transmits bits 3:0 on a positive transition ofRXC and hits 8:5 on the nega tive transition of RXC. RX_cT1. 1O9 69 58 Receive control The ETl011C transmits bit 5 and bit 10 synchronized with RXC to the MAC. The ETIOIIC transmits bit 5 on a positive transition of RXC and hit I0 on the nega tive transition of RXC. TXD[3:0] 26 Transmit control The MAC transmits bit 5 and bit I0 synchronized with TXC to the ETl0l I C for transmission on the mediat dependent (transformer) interface. The MAC trans mits bit 5 on a positive transition ofTXC and bit I0 on the negative transition of TXC. Receive clock The ETIOIIC generates a 125 MHz clock to synchro nize receive data. LSI Corporation Data Sheet September 2007 TruePH YET1011C Gigabit Ethernet Transceiver Hardware Interfaces (continued) Management Interface Serial Management Interface The Mil management interface (Ml) provides a simple, two-wire serial interface between the MAC and the PHY to allow access to control and status infonnation in the internal registers of the ETl01lC. The interface is compliant with IEEE 802.3 clause 22 and is compatible with the clause 45.3, enabling the two systems to co-exist on the same MDIO bus. Management Frame Structure Frames transmitted on the Ml have the following structure. Table 8. Management Frame Structure I PRE` Read Write 1. . . 1 |I l ...l sr l 01> P PHYAD REGADl 01 10 aaaaa rrrrr |I 01 I 101 I |aaaaa rrrrr TA 10 | in DATA d IDLE |4 n PRE (preamble): At the beginning ofeach transaction. the MAC may send a sequence of32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the Pl-lY with a pattern that it can use to establish synchronization. The l2TlOl 1C supports MF preamble suppression and thus the MAC may initiate management frames with the ST (start of frame) pattern. ll ST (start of Frame):The start of frame is indicated by a <0l> pattern. This pattern ensures transitions from the default logic one line state to zero and back to one. When a clause 45 start of frame <O0>is received, the frame is ignored. -1 OP (operation code): The operation code for a read transaction is <lO>. while the operation code for a write transaction is <Ol>. n Pl-WAD (Pl-TYaddress): The PHY address is 5 bits. The first PHY address bit transmitted and received is the MSB oi`the address. Only the PHY that is addressed will respond to the Ml Operation. '1 REGAD (register address): The register address is 5 bits. The first register address bit transmitted and received is the MSB of the address. ll TA (turnaround): The turnaround time is a 2-bit time spacing between the register address field and the data held ofa man agement flame to avoid contention during a read transaction. For a read transaction. the PHY remains in a high-impedance state for the first bit time of the turnaround and drives a zero bit during the second bit time of the turnaround. During a write transaction, the PHY expects a one for the first bit time of the tumaround and a zero for the second bit time of the tum around. " DATA (data): The data field is 16 bits. The first data bit transmitted and received is the MSB ofthc register being addressed. n IDLE (idle condition): The IDLE condition on MDIO is a high-impedance state, and the ETl0l 1C internal pull-up resistor will pull the MDIO line to logic one. LS1 Corporation 27 TruePH YETl011C Gigabit Ethernet Transceiver Data sheet Septemher 2007 Hardware Interfaces (continued) Table 9. Management Interface Pin Name PHYAD Pin # I28-Pin TQFP Pin # 84-Pin MLCC 67, 68, 69, 40. 4|, 4-2, [410] 70, 71 43. 44 Ml)C 9l 55 MD10 90 54 MDlNT_N 89 53 Pin # 68-Pin MLC Pin Description Functional Description The physical address of the l5Tl(ll lC is configured at reset by the current state of the PHYAl')[4:0] pins. Once these pins have been latched in at reset, the ETl0llC is accessible via (PHYAD the management interface at the configured address. The [$101) default address is set to l by internal pull-up/downs. These may be overridden by extemal pull-up/downs. The valid range is Oto 31`. 48 Management The management data clock (MDC) is a reference for the interface Clock data signal and is generated by the MAC. It can be turned ofl when the Ml is not being used. This pin has an internal pull down resistor. MDC is nominally 2.5 MHZ, and can work up to a maximum of 12.5 MHZ. 47 Management The management data input/output (MDIO) is a bidirectional Data 1/O data signal between the MAC and one or more Pl~lYs.;\/[D10 is a 3-state pin that allows either the MAC or the selected PHY to drive this signal. This pin has an internal pull-up resistor. An external pull-up resistor should also be used. the exact value depending on the number of Pl-[Y5sharing the MDIO signal. Data signals written by the MAC are sampled by the PHY synchronously with respect to the MDC. Data signals written by the PHY are generated synchronously with respect to the Ml)C. 34, 35, PHY Address 36, 37 46 Management lnterface Interrupt This pin requires an external pull-up (1 kQ to ll) kQ). This pin is active-low and indicates an unmasked manage ment interrupt. This pin requires an external pull-up resistor (1 kt! to 4.7 kQ). Pin is open drain. l. Pl-lYAD description applies to the 84-MLCC only. For the 68-MLCC. the valid range will be 0---15. ManagementInterrupt The ETl01lC is capable of generating hardware interrupts on pin MD1NT_N in response to a variety of user-selectable condi tions. MDINT_N is an open-drain, active-low signal that can be wire--()Redwith several other ETl()l lC devices. A single 2.2 kQ pull-up resistor is recommended for this wire-OR configuration. When an interrupt occurs, the system can poll the status of the interrupt status register on each device to determine the origin of the interrupt. There are nine conditions that can be selected to generate an interrupt: .1 Autoncgotiation status change n Link status change ll Autonegotiation page received fl FIFO overflow/underllow ll CRC errors ll Full error counter 7| Local/remote l'Xstatus change ll Automatic speed downshilt occurred I1 Ml)lO synchronization lost The ETl0l l C is configured to generate an interrupt based on any of these conditions by use ofthe interrupt mask register (Mll register 24). By setting the corresponding bit in the intenupt mask register for the desired condition, the E'I`lOl 1C will gener ate the desired interrupt. The E'l`l011C can be polled on the status ofan activated interrupt condition by accessing Mll register interrupt status register (Mil register 25). If this condition has occurred, the corresponding bit in the interrupt status register will be set. The interrupt status register is self-clearing on a read operation. 28 LS1 Corporation Data Sheet September 2007 TruePHYET1011C Gigabit Ethernet Transceiver Hardware Interfaces (continued) Configuration Interface The hardware configuration pins listed in Table 10 initialize the BT10] 1C at power-on and reset. The configuration is latched during initialization and stored. These pins set the default value of their corresponding Mll register bits. Some configuration inputs are shared with LED pins. The hardware configuration and LED pins are read on initial powerup of the ETlOl 1C, during a hardware reset and during recovery irom hardware powerdown. The logic value at the pin is sensed and latched. After RESET_N has been deasscrted (raised high), the shared configuration pins become outputs that are used to drive L.EDs.(For details on sharing LED and configuration pins, refer to the application note, TruePHY[;'T10I1 Gigabit Ethernet PH)' Design and Layout Guide.) Table 10. Configuration Signals Pin # 68-Pin MLCC Pin Description Functional Description TQFP Pin # 84-Pin MLCC SPEED_l 000 82 49 42 Speed 1,000 The SPEED_l O00conilguration pin sets the default advertised speed. The deassertion of SPEED_l 000 disables advertisement of the 1000Base-T to the remote end. The default is to advertise all three speeds. PAUSE 85 50 43 Pause SYS__CLK_EN_N 15 13 6 SYS_Cl.K Enable This input sets the pause mode. lf PAUSE is asserted, full-duplex pause and asymmetric pause operation are advertised. 0 = Don't adver tise pause (default).l = Advertise full-duplex pause and asymmetric pause. Enables the system clock. Pin Name Pin # 128-Pin If SYS_CLK_EN_T\l is asserted when RESETvN is low, SYS_CLK will be enabled and will con tinue to be generated while RESET__Nis low. If SYS_Cl.K_EN_N is not asserted when RESET_N is low, then SYS_CLK is disabled. () = SYS__CLl( enabled. 1 = SYS_CLK disabled (default). See Low Power Modes on page 11 for additional information. l..PED_EN_N l6 14 7 L.ow Power Energy Detection Enable LPED4EN_N enables the low-power energy deteet (LPED) mode when COMA is asserted. See Low Power Modes on page ll Foradditional information. When the PHY is in LPED mode, it can wake the MAC/controller (instead of Magic Pucker) by asserting the MDINT_N pin to indicate the pres ence of cable energy. 0 = Low-power energy-detect mode enable. PRES LS1 Corporation 87 5l 44 Precision Resistor l = Low--poWerenergy-detect mode disabled (default). Connect a 1.0 kQ precision resistor to ground to set termination for all digital I/Os. 29 TruePHY _ ET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Hardware Interfaces (continued) Table 10. Configuration Signals (continued) Pin Name M/\C_IF_ SELILZZO] Pin # Pin # Pin # Pin 128-Pin 84-Pin 68--Pin Description TQFP MLCC MLCC 20 18 ~ MAC Inter- 1; face Mock (MAC H.- Functional Description This input selects the desired MAC interface mode. Configure the MAC during reset as follows ooo = GMII/Mll (84-Pin MLCC default). SEL[l:0]' (See 001 = TBI. 010 = GMII/Mil (clocked by GTX__CLKinstead of Note 1.) TX_.CLK) 011 = Reserved. 100 = RGMH/RMII (RXC DLL delay; 68-MLCC defauIt)1 101 = RTBI (RXC DLL de|ay)1. 110 RGMIIIRMH(RXC and rxc DLLdelay)1. _t11 = RTBI (RXC and TXC DLL delay)1. l. ln the 68-MLCC, MAC_lF_SEl. 2 (1 l) will be set internally. Also, for all package types: ---MAC >IF _SEI_pins I00 will set MAC interface mode select bits in register 222:0 = l10; ziltcmative RGMII TXC DLL Delay bit 23.6 = ~~~MAC_|F__SELpins = l0l will sut MAC interface mode select hits in register 222:0 = ll]: alternative RGMll TXC DLL Delay bit 23.6 = ~- M/\C__'IF_SEL pins = l 10 will set MAC interface mode select bits in register 22.2:0 --=' 110; alternative RGMII TXC DLL Delay bit 23,6 T ---- MAC_ll`-'__SELpins = lll will set MAL` interface mode select hits in register 22.210 '* 11l; alternative RGMII TXC DLL Delay bit 23.6 30 LSI Corporation Data Sheet TruePH YET1 011C September 2007 Gigabit Ethernet Transceiver Hardware Interfaces (continued) LEDs Interface The ET10 l lC is capable ofsinking or sourcing current to drive LF.Ds. These LEDs are used to provide link status infomiation to the user. The ET10l 1C is capable of automatically sensing the polarity of the LEDs. The device determines the active sense of the LED based upon the input that is latched during configuration. Thus, if logic 1 is read, the device will drive the pin to ground to activate the LED; otherwise, it will drive the pin to supply to activate the LED. The LEDs can be programmed to stretch out events to either 28, 60, or IUOms. This makes very short events more visible to the user. All LEDs can be programmed to be on, off, or blink instead of the default status function. This is useful for alterna tive function indication under host processor control: for example, a system error during power-on self-check. All LEDs can be programmed to indicate une ofthirtccn different status functions instead of the default status function: n 1()OOBase-T fl Transmit or receive activity fl l0()Base-T X It Full duplex II lOBase-T .1 Collision KI l0O0Base-T (on) and l0()B-ase-TX( blink) l'\ Link established (on) and activity (blink) n Link established I1 Link established (on) and receive activity (blink) n Transmit activity Ii Full duplex (on) and collision (blink) -1 Receive activity The LED drivers can be configured by use of LED control register 1, LED control register 2. and LED control register 3 (Mll registers27429). Table ll. LED Pin Name Pin # 128-Pin TQFP Pin # 84-Pin MLCC Pin # 68-Pin MLCC Pin Description Functional Description LED_l000 42 l00()Base-T LED This LED indicates that the device is operating in lO0()Base-T mode. Setting can be overridden. LED_LNK 43 Link Established LED This LED indicates that the link is established. Setting can be overridden. 44 37 36 General-Purpose LEIJS Set to be ofl`by default. 43 LED_'I`XRX | LED_10(l t LS] Corporation 71 70 31 True.PHYETl0llC Gigabit Ethernet Transceiver Data sheet September 1007 Hardware Interfaces (continued) Media-Dependent Interface: Transformer Interface Table 12. Transformer Interface Signals Pin Name Pin # 84-Pin MLCC '|`Rl)[O]+ Pin # 128-Pin TQFP 39 25 19 TRD[0] 41 26 20 Pin # 68-Pin MLCC Pin Description Functional Description Transmit and Connect this signal pair through a transformer to the Receive Differen media-dependent interface. tial Pair () In lO00Base-T mode, transmit and receive occur simul taneously at 'l`RD{O]fl:. In l()Base-'1` and lO()Base-TX modes, 'l`RD[()]:t are used to transmit when operating in the MDI configura tion and to receive when operating in the MDI-X con figuration. 'l"Rl)[1 1+ TRD[1]-- 45 47 28 29 22 23 The PHY automatically determines the appropriate MDI/MDI-X configuration. 'l`ransmit/Receive Connect this signal pair through a transformer to the Differential Pair l media-dependent interface. In l0()()Base-T mode, transmit and receive occurs simultaneously at TRD[l]d:. ln l0Base--Tand lO0Base-TX modes, TRD[l]i are used to receive when operating in the MDI configura tion and to transmit when operating in the MDI-X con figuration. TRD[2]+ TRD[2]~ 54 56 34 35 28 29 The PHY automatically determines the appropriate MDI/MDI-X configuration. Transmit/Receive Connect this signal pair through a transformer to the Differential Pair 2 media-dependent interface. In l0O0Base-T mode, transmit and receive occurs simultaneously at 'l'RD[2]:k. In 1()Base-T and l(l0Base-TX modes, TRD[2]i are unused. TRD[3]+ 'l`RD[3]-- 60 62 37 38 31 32 Transmit/Receive Connect this signal pair through a transfomqer to the Ditfcrential Pair 3 media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[3]i. RSET 52 32 26 ln l0Base-'1` and l00Base-TX modes. 'l`RD[3]:l:are unused. Analog Reference RSF.T sets an absolute value reference current for the transmitter. Resistor Connect this signal to analog ground through a preci sion 6.34 l<Z1% resistor. 32 LS1 Corporation Data Sheet TruePH YET.l 011C September 2007 Gigabit Ethernet Transceiver Hardware Interfaces (continued) Clocking and Reset Table 13. Clocking and Reset Pin Name CI..K_[N Pin # 128-Pin Pin # 84-Pin Pin # 68-Pin TQFP MLCC MLCC 31 22 16 Reference Clo ck Input XTAL__l 3l 22 16 XTALA2 32 23 17 Functional Description Pin Description Reference Crystal Input Reference Crystal Input Connect this signal to a 25 MHZ clock input (CLK_lN will only accept a 2.5V signal) or a 25 MHZ i 50 ppm tolerance crystal (X'l`AL__l). Connect this signal to a 25 MHz -i 50 ppm tolerance crystal. Float this signal ifan external clock is used (Cl ,l<_l"N). SYS_CLK 94 S7 50 System Clock Use this signal to supply a 125 MHZ clock to the MAC. By default, the SYS_CI..K output is disabled. The SYS_Cl,,K output can be enabled by asserting the SYS_CLK_EN_N pin or via the management inter face. RESET_N 34 24 18 Reset Drive l{ESET_N low for 20 us to initiate a hardware reset. The ET1011C completes all reset operations within S ms of this signal returning to a high state. The configuration pins and the physical address con figuration are read during a hardware reset. See Low Power Modes on page l l for additional information. COMA 25 ----- l2 Hardware Powerdown Drive COMA high to initiate a hardware power down. The ET1011C completes all resct operations within 5 ms of this signal returning to a low state. All hardware functions are disabled during a hard ware powerdown. The configuration pins and the physical address con figuration zireread during a hardware powerdown. See Low Power Modes on page l 1 tor additional information` LS1 Corporation 33 TruePH'YET 1011C Data Sheet Gigabit Ethernet Transceiver September 2007 Hardware Interfaces (continued) J TAG The ET1()11C has a standard [EEE 1149.1 JTAG test interface. The interface provides extensive test and diagnostics capabil ity. lt contains internal circuitry that allows the device to be controlled through the JTAG port to provide on-chip, in-circuit emulation. The JTAG interface is a bidirectional serial interface with its own reset strobe (TRST_N). The reset strobe can be used inde pendently to reset the JTAG state machine but must be used during atpower-on reset (see Reset Timing on page 78). Table 14. JTAG Test Interface Pin Name Pin # 128-Pin TQF P Pin # 84-Pin ML CC Pin # 68-Pin MLCC TDI 16 14 7 Test Data Input TDO 17 '15 8 Test Data Output TCK 1O 5 2 Test Clock TMS 15 13 6 TRST_N 14 12 5 Test Mode Select Test Reset Pin Description (JTAG Reset) Functional Description This signal is the JTAG serial input. All instructions and scanned data are input using this pin. This pin has an internal pull-up resistor. This signal is the JTAG serial output. Scanned data and status bits are output using this pin. This pin has an inter nal pull-up resistor. This signal is the JTAG serial shifi clock. It clocks all ot` the data that passes through the port on TDI and TDO. This pin has an internal pull-up resistor. This signal is the JTAG test mode control. This pin has an internal pull-up resistor. This signal is active-low and causes the JTAG TAP con troller to enter the reset state. This pin has an internal pull-down resistor. Regulator Control The F,Tl()11C has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or 2.5 V.The on-chip regulator control circuits provide output control voltages that can be used to control two external transistors and thus provide regulated 1.0 V and 2.5 V supplies. Table 15. Regulator Control Interface Pin # 128-Pin TQFP Pin Name Pin # 84-Pin MLCC Pin # 68-Pin MLCC 1 19 M 47 1.0 V Regulator Control for This is the regulator output control voltage for the 2.5 V supply. It is used to control an external transis 2.5 V tor and thus provide 21regulated 2.5 V supply. 40 crnugvs 78 g 46 39 Functional Description `Thisis the regulator output control voltage for the 1.0 V supply. it is used to control an cxtemal transis tor and thus provide a regulated 1.0 V supply. Regulator Control for CTRL__1 V0 34 Pin Description LS1 Corporation Data Sheet September 2007 TruePHYET101lC Gigabit Ethernet Transceiver Hardware Interfaces (continued) Regulator Control (continued) The ETl01 1C digital and analog core operates at 1.0 V. The analog 1/0 operates at 2.5 V The digital l/O can operate at either 3.3 V or 2.5 V. The GK/111 interface operates at 3.3 V and the RGMII intertace operates at 2.5 V. The on-chip regulator control allows the device to be operated from a wide variety of extemal supply combinations. When more than one external supply is available, one or both of the regulator control circuits may be left unused. Table 16 lists example combinations of available external supplies and shows how the on-chip regulator control may be used to provide the required supplies. Table 16. Supply Voltage Combinations Available External Supplies Av DDL D VD D AVDDH VDD_REG 1 Description 3 .3 V only 1.0 1.0 2.5 3.3 Digital l/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 1.0 V and 2.5 V. 2.5 V only l.() 1.0 2.5 2.5 Digital l/O is 2.5 V. Regulator control is used to provide 1.0 V. 3.3 V and 1.0V 1.0 1.0 2.5 3.3 Digital 1/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 2.5 V. 2.5Vandl.0V 1.0 1.0 2.5 2.5 Digital 1/O is 2.5 V. 3.3 Regulator controls are not connected. 3.3 V and 2.5 V 1.0 1.0 2.5 3.3 V, 2.5 V, 1.0 1.0 2.5 Digital 1/() can be either 3.3 V or 2.5 V. Regulator control is used to provide 1.0 V. r 2.5 and 1.0 V Digital l/O can be either 3.3 V or 2.5 V. Regulator controls are not connected. 1 Even ifthe regulator controls are not connected, VDD__REGmust be powered. Power, Ground, and No Connect Table 17. Power, Ground, and No Connect Pin Name Pin Description VDD_REG DVDDIO Von Regulator 2.5 V or 3.3 V supply. Von Digital l/O 3.3 V or 2.5 V supply. DVDD VDD DVSS Vss | Digital ground`. AVDD1-I Von l Analog power 2.5 V. AVDDL Von l Analog power 1.0 V. AVSS Vss | Analog groundl. lit No Connect Functional Description I Digital core 1.0 V supply. l Reserved----clonot connect. l, For 84-pin MLCC and 68-pin MLCC, all AVSS and DVSS pins share a common ground pin (exposed pad) in the center of the device. LS1 Corporation 35 TruePHYET10l1C Gigabit Ethernet Transceiver Data Sheet September 2007 Cable Diagnostics The ET10l1C has on-chip cable diagnostics. The cable analysis uses two distinct methods for evaluating the cable: link analy sis arid time domain reflectometry (TDR) analysis. This analysis can be used to detect cable impairments that may be prevent ing a gigabit link or affecting perfonnance. When there is a link active, the link analysis can detect cable length, link quality, pair skew, pair swaps (MDIIMDI-X configu ration). and polarity reversal. When there is no link, TDR can detect cable faults (open circuit, short circuit), distance to the fault, pair fault is on, cable length, pair skew, and excessive crosstalk. Table l8 summarizes the specifications of the cable diagnostic function s. Table 18. Cable Diagnostic Functions Feature Detection oi`Cable Fault on Any Pair Description 10 I00 1 Cable open Cable short Indicate distance to fault Pair swaps Detect Polarity Reversal Good Cable with Link Good Cable Without Link Pair Skew with Link 000 Indicate length Term Unterm Analysis / / Line Probing / J i=2 m =l:2 m /l -/ ~/ \/ *2 / :klOlT1 3; 10m Indicate length Detect excessive. >50 / Link Analysis Link Analysis Link Analysis i5 m3 :2 m Linc Probing Link Analysis 1'15 Pair Skew Without Link Detect excessive, >50 ./3 / Line Probing if \/ Line Probing HS Excessive Crosstalk Cable quality or split pairs 1. Pair swaps on C and D as well as pairs A and B are reported. 2. Polarity reversal in l0OBase-TX is not detected because Ml.T-3 signaling is polarity insensitive. 3. If the magnitude of the peak reflection is greater than 15% ofan open circuit. 36 LS1 Corporation TruePHYFT1lll1C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description Register Address Map Table 19. Register Address Map Address l0 ll----l4 15 16---l7 18 l9 20 21 22 23 24 25 26 27 28 29 30 31 Description Control register. Status register. PHY identifier register 1. PHY identifier register 2. Autonegotiation advertisement register. Autonegotiation link partner ability register. Autonegotiation expansion register. Autonegotiation next page transmit register. Link partner next page register. 1000Basc-T control register. l00Ol3ase-T status register. Reserved. Extended status register. Reserved. PHY control register 2. Loopback control register. RX error counter register. Management interface (Mi) control register. PHY configuration register. PHY control register. Interrupt mask register". Interrupt status register. PHY status register. LED control register 1. LED control register 2. LED control register 3. Diagnostics control register. Diagnostics status register (TDR mode). Table 20. Register Type Definition Type Description LL Latching low. Latching high. Read write. Register can be read or written. Read only. Register is read only. Writes to register are ignored. Self-clearing. Register is self-clearing; if a one is written, the register will automatically clear to zero afier the function is completed. LH WW RO SC l,Sl Corporation TruePH YET10llC Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings Table 21. Control Register--Address 0 Control Register Bit l5 Name Reset l4 Loopback 13 Speed Selection (L SB) Description = PHY reset. = Normal operation. = Enable loopback. 0 = Disable loopback. Bit 6,13. ll = Reserved. l0 = 1000 Mbits/s. Oi = 100 Mbits/s. Type R/W Default Notes l SC 2 R/W R/W Sl'EED__l 000 3 O0 = 10 Mbits/s. lZ Autonegotiati on ll Enable Powerdown l0 isolate 9 Restart Autoneg tion 8 Duplex Mode 7 Collision Test 6 Speed Selection (MSB) 5:0 Reserved = Enable autonegotiation process. = Disable autonegotiation process. = Powerdown. = Normal operation. = lsolatc PHY from Mll. = Nomtal operation. = Restart autonegotizition process. Normal operation. = Full duplex. = llalf duplex. = Enable collision to-st. O= Disable collision test. K/W R/W O 7 See bit 13. R/W Sec bit l3. 3 R0 0 -- ~ 4 RIW R/W 5 R/W SC R/W 6 The reset bit is automatically cleared upon completion of the reset sequence. This bit is set to 1 during reset. This is the master enable for digital and analog loopback as defined by the standard. The exact type of loopback is determined by the loophack control register (address l9). The speed selection address 0 bits 13 and 6 may be used to configure the linkmanually. Setting these bits has no effect unless address Obit 12 is clear. When this bit is cleared, the link configuration is determined manually. Setting this bit isolates the PHY from the Mil, GMll, or RGMll interfaces. This bit may be used to configure the link manually. Setting this bit has no effect unless address O bit 12 is clear. Enables IEEE 22.2.4.1.9 collision test. LS1 Corporation Data Sheet TruePH YET l 011C September 2007 Gigabit Ethernet Transceiver RglStI` DBSCl'ipfi0l1 (continued) Register Functions/Settings (continued) Table 22. Status Registcr--Address 1 Status Regster Name Bit Description Type Default Notes l l5 I00Base-T4 0 = Not lO0Base-T4 capable. RO O 14 l00Basc-X Full Duplex I I l00Base-X full-duplex capable. 0 = Not l00l3ase-X full-duplex capable. R(_) l 13 l()0l3ase-X Half Duplex l I l0()Base-X half-duplex capable. O= Not l0OBase-X half-duplex capable. R0 1 I2 l0Base-T Full Duplex l = l0Base-T fullsduplex capable. 0 = Not l0Base-T full-duplex capable. RO l ll lOl3ase-Tl-IalfDuplcx 1 = 1OBasc-T half-duplex capable. 0 = Not lOBase--Thall'-duplex capable. RO 1 10 l00Base-T2 Full Duplex 0 = Not l00Base-T2 full-duplex capable. RO O 9 0 = Not l0OBase-T2 half-duplex capable. R0 0 8 ll)OBase-T2 Half Duplex Extended Status l I Extended status information in register 0l~'h. R0 1 7 Reserved RO -- 6 MI' Preamble Suppression l = Preamble suppressed management frames accepted. RO l 5 Autonegotiation Complete RO 0 2 4 Remote Fault 1 = Autonegotiation process complete. O= Autonegotiation process not complete. l = Remote fault detected. O= No remote fault detected. RO O 3 l = Autonegotiation capable. 0 = Not autonegotiation capable. RO 1 O 3 Autonegotiation Ability 2 Link Status l O Jabber Detect Extended Capability I_.H 1: Link is up. RO 0 = Link is dc"-11. Ll. 1 = Jabber condition detected. 0 = No jabber condition detected. RO l = Extended register capabilities. RO 4 0 l..H l 5 1. The ET101lC does not support 10OBase-T4 or 10OBase-T2; therefore, these register bits willalways be set to zero. 2. Upon completion of autonegotiation, this bit becomes set. 3. This bit indicates that a remote fault has been detected. Once set, it remains set until it is cleared by reading registert via the management interface or by PHY reset. 4. This bit indicates that a valid link has been established. Once cleared due to link failure, this bit willremain cleared until register 1 is read via the management interface. 5. Indicates that the PHY provides an extended set of capabilities that may be accessed through the extended register set. For a PHY that incorporates a GMII/RGMII,the extended register set consists of all management registers except registers 0, 1, and 15. LS! Corporation 39 TruePH YET.l.01lC Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 23. PHY Identifier Register 1----Address2 PI-IYIdentifier Register 1 15:0 PHY Identifier Bits Bit iI 3 :1 8 Name Organizationaily unique identifier (OUI), bits 3:18. I\ Description ` Type " |I Default i Notes 0><02s2 ` Default I Notes 1 Table 24. PHY Identifier Register 2--Address 3 PHY Identifier Register 2 Bit | Name | Description 111100 19:24 Identifier Bits 15:10 \ PHY 320 9:4 Revision Number i Model Number }Organizationaliy unique identifier (OUI), bits 19:24. number | Revision Model number I l.= 4. 000001 0100 1 ---- 1. The LS1 OUI is 00-05-3D. 40 I.Sl Corporation Data Sheet September 2007 TruePHYET10l1C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 25. Autonegotiation Advertisement Register--Address 4 Autonegotiation Advertisement Register 1 Bit Name l5 Next Page 14 Reserved Description l = Advertise next page ability supported. OI Advertise next page ability not supported. --- l = Advertise remote fault detectedr 0 = Advertise no remote fault detected. TYPE Default R/W 0 RO O R/W O RO 0 Notes 13 Remote Fault 12 Reserved ll Asymmetric Pause 1 = Advertise asymmetric pause ability. 0 = Advertise no asymmetric pause ability. R/W PAUSE l 10 Pause Capable l = Capable offull-duplex pause operation. O= Not capable of pause operation. RI W PAUSE 1 9 lO0Base-T4 Capabil- 1 = l00Base-T4 capable. ity 0 = Not l00Base-T4 capable. R/W 0 2 8 l00Base-TX FullDuplex Capable l00Base-TX Half~ Duplex Capable 1 = l0OBase-TX full-duplex capable. 0 = Not l00Base-TX full-duplex capable. 1 = l00Base-TX half-duplex capable. O= Not l00Base--'l`Xhalf-duplex capable. R/W l R/W 1 lOBase-T FullDuplex Capable l0Base-T Haltl Duplex Capable Selector Field l = l0Base-T full-duplex capable. 0 = Not 1OBase-T full-duplex capable. l = l0Base-T halt`-duplexcapable. 0 = Not l0Base-T half-duplex capable. 0000i = IEEE 802.3 CSMA/CD. R/W 1 R/W l R/W 00001 7 6 5 4:0 i 1. Value read from PAUSE on reset. 2. The ET1011C does not support 1OOBase-T4,so the default value of this register bit is zero. Note: Any write to this register prior to the completion of autonegotiati on is followed by a restart ofautonegonationi Also note that this register is not updated following autonegotiution. LS1 Corporation 4] TruePH YET101] C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 26. Autoncgotiation Link Partner Ability Register--Address 5 Autonegotiation Link Partner Ability Register Bit 15 Next page 14 Acknowledge 13 Remote Fault l2 Reserved ll Asymmetric Pause ll) Pause Capable 9 l00Basc-T 4 Capa 8 bility l0OBase-TX Full Duplex Capable Description = Link partner = Link partner = Link partner = Link partner = Link partner = Link partner has next page ability. does not have next page ability. has received link code word. has not received link code word. has detected remote fault. has not detected remote fault. l00Base-TX Half Duplex Capable l = Link partner is l00Base-TX half-duplex capable. 0 = Link partner is not lO0Base-TX halt`-duplex capa blc. 6 l0Base-T Full Duplex Capable l0Base-T l-lalf Duplcx Capable Protocol Selector Field mlI Link partner is 1OBase-T full-duplex capable. 0 = Link partner is not 10Basc-T full-duplex capable. l = Link partner is 10Base-T half-duplex capable. 0 = Link partner is not 10Basc-T half-duplex capable. Link partner protocol selector field. 4-:0 Type Default Notes R0 O -- = Link partner desired asymmetric pause. = Link partner does not desire asymmetric pause. Link partner capable of full-duplex pause opera tion. ()= Link partner is not capable of pause operation. 1 I Link partner is l00Basc-T4 capable. O= Link partner is not l00Base-T4 capable. l = Link partner is 1(]0Base-TX full-duplex capable. 0 = Link partner is not 100Base-TX full-duplex capa blc. 7 5 42 Name LS] Corporation Data Sheet September 2007 TruePHYETl0l1C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 27. Autonegotiation Expansion Register--~Address6 Autouegotiation Expansion Register Bit 15:5 4 3 2 Name Reserved Parallel Detection Fault Link Partner Next Page Ability Next Page Capabil ity l Page Received 0 Link Partner Auto negotiation Ability Description = Parallel link fault detected. = Parallel link fault not detected. Type Default RO RO O Notes Ll cl = Link partner has next page capability. = Link partner does not have next page capability. = Local device has next page capability. I Local device does not have next page capability. RO O R0 1 I New page has been received from link partner. = New page has not been received. = Link partner has autonegotiation capability. I Link partner does not have autonegotiation capa RO LH RO 0 Type R/W Default RO R/W 0 LH O bility. Table 28. Autonegotiatiun NX t Page Transmit Rcgister--Address 7 Autonegotiation Next Page Transmit Register Bit Name 15 Next Page 14 Reserved .l3 Message Page 12 Acknowledge 2 11 Toggle 10:0 Message/ Unformatted Code Field LS1 Corporation Description l = Additional next pages follow. 0 = Sending last next page. = Formatted page. = Unformattcd page. R'W = Complies with message. = Cannot comply with message. l = Previous value of transmitted link code word Wfinfi RO logic zero. 0 = Previous value of transmitted link code word was logic one. R/\V Next page message code or unformatted data. Notes 0 1 K) 0 l 43 Data Sheet September 2007 TruePHYET10l1C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 29. Link Partner Next Page Register--Address 8 Link Partner Next Page Register Name Bil l5 Next Page l4 Acknowledge 13 Message Page l2 Acknowledge 2 ll Toggle 10:0 44 Messagel Unfonnattcd Code Field Description = Additional next pages follow. = Sending last next page. Z Acknowledge. = N0 acknowledge. = Formatted page. = Unformatted page. Complies with message. = Cannot comply with message. = Previous value of transmitted link code word was logic zero. 0 Previous value oftransmitted link code word was logic one. Next page message code or unfomtatted data. Type RO Default Notes () __ RO U T R/W 0 _._ R/W O 1 RO Q _ R/W 0 4.. LS1 Corpomtion Data Sheet September 2007 TruePH YET1011C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 30. 1000 Base-T Control Register---Address 9 1000Base-T Control Register Bit 15:13 Type R/W Default Notes O00 -- l = Enable master/slave configuration. 0 = Automatic master/slave configuration` R/W Q __ 1 I Configure PHY as master. O= Configure PHY as slave. Rl W () 1 = Prefer multipoit device (master). = Prefer single-port device (slave). = Advertise lO0OBase-T Full-duplex capability. ll = Advertise no l()00Base-T fiill-duplex capability. R/ W Q __ R/W SP EED_l 000 2 R/W SP EED_1000 2 Name Test Mode Description 000 = Normal mode. O01 = Test mode l--transmit waveform test. 0] 0 = 'l`estmode 2 master transmitjitter test. 011 = Test mode 3--s1ave transmitjitter test (slave mode). 100 = Test mode 4---transmit distortion test. 101,110,111: Reserved. 12 ll Master/ Slave Configuration Enable Master/Slave Configuration Value l0 Port Type 9 Advertise l000Basc-"I" Full 8 7:0 l duplex Capability Advertise 1 = Advertise 'l000Base-'l' half-duplex capability. l00()Base-T Half 0 = Advertise no 1000Base-T half-duplex capability. duplex Capability Reserved RO Setting this bit has no effect unless address 9. bit 12 is set. 2. Value read from SPEED_1000 pin at reset. Note; Logically, bits 12:8 can be regarded as an extension of the technology ability field of register 4. LSI Corporation 45 TruePHY ET] 011C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 31. l000Base-T Status Reg"ister--Address 10 l000Base-T Status Register Bit l5 l4 l3 l2 ll Name Master/ Slave Configura tion Fault Master/ Slave Configuration Resolution Local Receiver Status Remote Receiver Status Link Partner l000l3asc-T Full duplex lIapabil Description l = Master/slave configuration fault detected. 0 = No master/slave configuration fault detected. 1 = Local PHY resolved to master. 0 = Local PHY resolved to slave. Type Default Notes RO, LH, SC RO O l () 2 l = Local receiver okay. O= Local receiver not okay. I Remote receiver okay. = Remote receiver not okay. = Link partner is capable of lO00Base-T full duplex. = Link partner not l0OOBasc-T full-duplex capable. RO 0 _ R0 0 _ RO 0 3 l = Link partner is l000Base-T half-duplex capable. 0 = Link partner not lO(l()Base-'1"half-duplex capable. R0 O 3 RO RO () 4 ity 10 9:8 7:0 Link Partner l0()0Base-T Half-duplex Capability Reserved Idle Error Count MSB of idle error count. 1. Once set, this bit remains set until cleared by the following actions: |`lRead of register l0 via the rnanagement interface. n Reset. IiCompletion of autonegotiation. rtEnable of autoncgotiation. 2. This bit is not valid when bit 15 is set. 3. Note that logically, bits 11:10 may be regarded as an extension of the technology ability field of register 5. 4. These bits contain a cumulative count of the errors detected when the receiver is receiving idles and both local and remote receiver status are OK. The count is held at 255 in the event of overflow and is reset to zero by reading register 10 via the management interface or by reset. 46 LSI Corporation Data Sheet September 2007 TruePH YET10l1C Gigabit Ethernet Transceiver Register Description Register Functions/Settings (continued) Table 32. Reserved Registers---~Addresses 11----14 Reserved Registers Bit | Name 15:0 |Rescrvcd ` l Description --- I Type | -- Default -- Notes Type R0 Default 0 Nates --- R0 0 -- RO 1 R0 l -- 0 --' Table 33. Extended Status Register--Address 15 Extended Status Register Bit 15 Name I Description l000Base-X Pull0 = Not l00OBase-X full-duplex capable. duplex l000Base-X Ha1f- 0 = Not l000Base-X half-duplex capable. duplex l000Base-T Full= l000Base-T full-duplex capable. duplex I Not l()()()Base-T full-duplex capable. l00()Base-T Halli I l00()Base-'1"half-duplex capable. duplex = Not 1000Base-T half-duplex capable. 14 13 l2 ll :0 | Reserved | ---- | I. Value is a result of (SPEED__l000) pin at reset. Table 34. Reserved Registers--Addresses 16-17 Reserved Registers Bit | 15:0 | Reserved LS1 Corporation Name | Description Type | --- -- Default ---- | Notes I -- 47 TruePHYET101lC Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Fnnctions/Settings.(continued) Table35. PHYControl Register 2--Address 18 PHY Control Register 2 Bit Name Description 15 Resolved 14 Count False Car rier Events -- 1 I Rx error counter counts false carrier events. 0 I Rx error counter does not count false car rier events. 13 Count Symbol Errors Reserved Automatic M[)l/M.DI-X 1 = Rx error counter counts symbol errors. O= Rx cnor counter counts CRC errors. -- I Enable automatic MDl/MDI-X detection. = Disable automatic MDI/MDI-X detection. 12:11 10 9 8:3 2 MDI/MDI-X Configuration Reserved Enable Diagnostics 1 :0 = Manual MD]-X configuration. = Manual MI)l configuration. -- l = Enable diagnostics, 0 1 Disable diagnostics. Reserved ~-- Type Default Notes IUW 0 1 R/W O 1 R!W 1 R/W 0 See Table 36. R/W 0 2 -- ----- --- 1. Count symbol errors (18.13) and count false carrier events (18.14) control the type of errors that the Rx error counter (20. 15.0) counts (settings are shown below). The default is to count CRC errors. Count False Carrier Events Count Symbol Errors 1 0 Rx Error Counter Cotmts symbol errors and false carrier events. Counts CRC errors and false carrier events I Counts symbol errors. 0 I Counts CRC errors. 2. This bit enables Pl-IYdiagnostics. which include IP phone detection and TDR cable diagnostics. it is not recommended to enable this bit in normal opera tion (when thc link is active}. This bit does not need to be set for link analysis cable diagnostics. 48 LS1 Corporation TruePH YET101l C Data Sheet September 2007 Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Bit 9. PH`! Control Register 2, manually sets the MDI/MDI-X configuration ifautcmatic MDIX is disabled, as indicated below. Table 36. MDI/MDI-X Configuration Automatic MD!/MDI-X MDI/MDI-X Configuration MD!/MDI-X Mode i Automatic MDI/MDI-X detection. i MDI configuration (NlC/DTE). I MDI-X configuration (switch). 0 l The mapping of the transmitter and receiver to pins for MDI and MDI-X configuration for lOBase-T, iO()Base-TX. and l0()0Base-T is shown below. Note that even in manual MDI/MD]-X configuration, the PHY automatically detects and cor rects for C and D pair swaps. Table 37. MD!/MD]-X Pin Mapping Pin MDI Pin Mapping 10Base-T MD!-X Pin Mapping 100Base-TX i 1000Base-T l0Base-T 100Base--TX i l000Base-T TRD[l)]+/~ Transmit +/-- Transmit +/~ Transmit A+/-- Receive +l* Receive B+/~ Receive +/- Transmit B+/A Receive A+/~ 'I`RD[1]+/~- Receive +/-- Transmit B+/~ Transmit +l-- Receive A+I-- Transmit +/- Transmit A+/-- Receive B+/A Receive +/7- TRD[2]+/- - -- Transmit 0+/e Receive D+/- -- -- Transmit D+/ Receive C+/ TRD[3]+/- - - TransmitD+I- -- -~ TransmitC+/ Receive C+/- LSI Corpuration Receive D+/ 49 Data Sheet September 2007 TruePHY ET1011C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 38. Loopback Control Register--Address 19 Loopback Control Register Type Default Notes l = Mil loopback selected. O= Mil loopback not selected. R/W 1 .... _ Name Bit l5 Mil I4: I 3 Description Reserved 12 All Digital l = All digital loopback selected. 0 = All digital loopback not selected. R/W [) ll Replica 1 Replica loopback selected. 0 = Replica loopback not selected. R/W 0 l 10 Line Driver l = Line driver loopback selected. 0 = Line driver loopback not selected. R/W Q __. l = External cable loopback enabled. 0 = External cable loopback disabled. R/W () __ 1 = Force link status okay in Mli loopback. 2 = Force link status not okay in Mil loopback. R/W 0 2 9:8 7 6:1 0 Reserved External Cable Reserved Force Link Status 1. Replica loopback is not available in l0Base-T. 2. This bit can be used to force link status okay during Mil loopback. ln Mil loopback, the link status bit will not he set unless force link status is used. in all other loopback modes, the link status hit will be set when the link comes up. Loophack "ode Settings The following table shows how the loopback bit (0.14) and the cable diagnosticmode bit (23.13) should be set for each loopback mode. It also indicates whether the loopback mode sets the link status bit and when the PHY is ready to receive data. Table 39. Loopback Bit (0.14) and Cable Diagnostic Mode Bit (23.13) Settings for Loopback Mode Bit 0.14 Loopback Bit 23.13 = I Cable Diagnostic Mode Required Required Mil Yes All Digital Yes Loopback Replica Linc Driver l 50 Ext Cable Bit 26.6 Link Status Set PHY Ready for Data N0 19.0 Alter atfew ms Yes Yes Link Status Yes YS Yes Link Status Yes Yes Yes Link Status | No Yes Yes Link Status l l i.,Sl Corporation Data Sheet September 2007 TruePH YETI 011C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 40. RX Error Counter Register----Address20 RX Error Counter Register Bit 1 15:0 Name l Rx Error Counter Description IType 16-bit Rx error counter. R0, Defaultl Notes O Reference Reg ister 18 (bits I3 and l4) for error type descrip lions SC Table 41. Management Interface (Ml) Control Register-Address 21 Management Interface (Ml) Control Register Bit 15:3 2 1 0 i Name Reserved Ignore 10G Frames |Reserved Preamble Suppression Enable LS1 Corporation | | Description ---- R Type I l = Management frames with ST = <00> are ignored. 0 = Management frames with ST <0()> are treated as wrong frames ~~ 1 = Ml preamble is ignored. 0 = Ml preamble is required. 4 R/W 1 Default I -- R/W __ ` Notes \ T iii 51 TruePH YETl0l1 C Gigabit Ethernet Transceiver Data Sheet Septembet 2007 Register Description (continued) Register Functions/Settings (continued) Table 42. PHY Configuration Register--Arldress 22 PHY Configuration Register Bit l5 CRS Trzinsmil Enable 14 Reserved 13:12 Description Name Transmit FIFO depth (10()0Base-T) I = Enable CRS on transmit in half-duplex mode. (J= Disable CRS on transmit. 00 = i8. Type R/W Default R/W Ol R/W ll 0 Ol=il6. 10=i24. ll =i32. Automatic Speed Downshift Mode O0= Disable automatic speed downshilt. 9 TBI Detect Select R/W 0 8 T131Rate Select R/W 0 7 Alternate Next~Page R/W 0 6 R/ W () 5 Group MDlO Mode Enable Transmit Clock Enabl G R/W 0 4 System Clock Enable l = CRS pin outputs comma detect. (J= CRS pin outputs link status detect l = Output l25 Mllz clock on RX_CLK while COL is held low (full rate). 0 ==Output even/odd clocks on RX_CLK/COL l = Enables manual control of lOO0Base-T next pages only. 0 = Normal operation of lO0OBase-T next page exchange 1 = Enable group MDIO mode. 0 I Disable Group MDIO mode. l I Enable output of l()00Base-'l` transmit clock ('l`X_CLK pin). 0 = Disable output. 1 = Enable output of` 125 MHZ reference clock (SYS_CLK pin). 0 = Disable output of 125 MHz reference clock. 3 2:0 Reserved MAC Interface Mode Select O00 = GMII/MIL 001 = TBI. 010 = GMII/MI] clocked by GTX_C LK instead of 'l`X_CLK. O11 = Reserved. 100 = RGMII (trace delay). 101 = RTBI (trace delay). 110 = RGMl1(DLL delay). R/W 11:10 Notes 1 10= 100Base-TX downshift enabled. xl = 100Base-TX and 10Base-T enabled. R/W 2 sYs_cu<_i=.N_N See bit 23.6 (next page) and Note 1, Table 10, page 30. ' 3 lll = RTBI (DLL delay). I. lf automatic speed downshift is enabled and the l-`HYfails to autonegotiate at l0OOBase-'1`,the PHY will fall hack to attempt connection at 100Base-TX and, subsequently, l0Base-To This cycle will repeat lfthe link is broken at any speed, the PHY Wlll restart this process by reatteiiipting, connection at the highest possible speed (e.g.. l00OBase~T). 2. Value is read from inversion ofSYS__Cl,K_ EN N at reset 3. For the 63-pin MLCC, only RGMIl and RTBI inodes;'options are supported. Register Description (continued) 52 LSl Corporation Data Sheet September 2007 TruePHYET101lC Gigabit Ethernet Transceiver Register Functions/Settings (continued) Table 43. Pl-lY Control Register--Address Z3 PI-IYControl Register Name Bit Description 15 [P Phone Detected 14 IP Phone Detect Enable 13 Cable Diagnostic Mode 12:11 = IP phone detected. 1 IP phone not detected. = Enable automatic ll" phone detect. = Disable automatic 1Pphone detect. = Link analysis mode. = TDR mode. Type RO R/W. SC R/W R/W Automatic Speed 00 = 1 Downshifi/\t`ternpts 01 = 2 Before Downshift 10 = Default Notes O 1 0 2 1 3 ll See Note 1, Table l0. 4 ll= Reserved -- Alternative RGM11 1 1 TXC DLl.. delay in RGMII mode is opposite ofRXC. 10:7 6 TXC DLL Delay RfW O= TXC DLL delay in RGMI1 mode is same as RXC. page 30. 3 Jabber ( l0Base-T) SQE (10Base-T) TP_LOOPBACK 2 (10Base-'1`) Preamble Genera- l tion Enable Reserved 0 Force Interrupt 5 4 = Disable jabber. = Normal operation. = Enable heartbeat. = Disable heartbeat. =Disabl e TPl oop back ' during half-dup lex. = Normal operation. = Fonebl e preamble ge ` nera ti 0n F0 r 10Base-'1`. R/ W Q _ R/W O -- R/W 1 _.. R/W 1 __. R/W Q ___ = Disable preamble generation for 10Base-'1'. -- 1 = Assert l\/ll)lN'1`_N pin. 0 = Deassett MD1NT_N pin. This bit is only valid when the PHY is in PHY standby mode (26.15 e 1) and after the IP phone detect enable bit (23.14) has been set and has seltleleared to indicate that the ll` phone detection algorithm has completed. 2. Setting this bit enables the automatic 1P phone detection algoriflim and clears the IP phone detected bit (23. 15). Diagnostics must be enabled ( 18.2 = 1), cable diagnostic TDR mode must be selected (23.13 I 0), and the Pl-lY must be in PHY standby mode (26.15 = llto do 11`phone detection. IP phone detect enable self-clears when the [P phone detection algorithm is complete, the result is then indicated in IP phone detected 3 This bit sets the cable diagnostics mode. The default is link analysis mode wherein the PHY brings up atlink with a remote partner. For analysis of cable faults, the Pl-lY can be put in TDR mode. ln TDR mode, the P1lY will not respond to link pulses from a remote link partner and will not bring up a link. 4 This bit allows independent control over TXC and RXC DLL delay. Settings are shown below: 1 RGMII Mode Delay Description RXC Ons 22.220 TX C 10x Ons llx Zns 2 ns 10x 2ns Ons llx Ons Zns LS1 Corporation I RGM11 (trace delay). | not/111 (txc and RXC 01.1. delay). | RGMII (rxc DLL delay). l RGMl1(RXC mt delay). 53 TI`llePHYETIIJIIC Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Ful1Cfi0IlS/Settings(eontinued) Table 44. Interrupt Mask Register---~Address24 Interrupt Mask Register Bit 15:1I Name Description Type Default Notes Reserved 10 TDRIIP Phone = Interrupt enabled. = Interrupt disabled. R/W Q _. 9 MDIO Sync Lost R/W 0 _ 8 R/W I) -- 7 Autunegotiation Status Change CRC Errors = Interrupt enabled. = Interrupt disabled. = Interrupt enabled. R/W () __ 6 Next Page Received R/W [) 5 En-or Counter Full R/W Q ___ 4 FIFO OverIl0w/ Underflow Receive Status Change Link Status Change R/ W O i R/W 0 ._._ R/W 0 __ R/W 0 ._ R/W O ___ 3 2 I Automatic Speed Downshift 0 l\/IDINT_N Enable I IIIILCITUPI disabled. = Interrupt enabled. = Interrupt disabled. = Interrupt enabled. I Interrupt disabled. Z Interrupt enabled. = Interrupt disabled. = Interrupt enabled. = Interrupt disabled. = Interrupt enabled. = Interrupt disabled. = Interrupt enabled. = Interrupt disabled. = Interrupt enabled. = Interrupt disabled. = Ml)IN'l`_N'enab1ed`. = MDlNT_N disabled. _ .._. I. MDINT _Nis asserted (zvelive-low) if Mll interrupt pending 1 I. 54 LSI Corporation Data Sheet September 2007 TruePHYET101lC Gigahit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 45. Interrupt Status Register---Address25 Interrupt Status Register Bit 15:11 10 1`/re Default Notes = Event has completed. = Event has not completed. RO, 0 . R0, 0 l 0 -- [) _..._ Q .__ Q .._ () __ I) ~-- 0 __ O -- R0, 0 2 Description Name Reserved TDR/IP Phone 1 Automatic Speed Downshift = Event has occurred. = Event has not occurred. = Event has occurred. = Event has not occurred. = Event has occurred. = Hvent has not occurred. : Event has occurred. = Event has not occurred. = Event has occurred. = Event has not occurred. = Event has occurred. Event has not occurred. : Event has occurred. = Event has not occurred. = Event has occurred. Event has not occurred. I Event has occurred. = Event has not occurred. 0 Mll Interrupt Pend ing = lntcmtpt pending. = No interrupt pending. 9 MDIO Sync Lost 8 7 Autonegotiation Status Change CRC Errors 6 Next Page Received 5 Error Counter Full 4 FIFO Overtlow/ Underfl ow Receive Status Change Link Status Chang 6 3 2 LH LH R0, LH R0, LH R0, LH RO, LH RO. LH R0, LH R0, LH R0, LH LH l. lf the management frame preamble 1Ssuppressed (MF preamble suppression, register O,bit 6), it is possible for the PHY to lose synchronization if there is a glitch at the interface. The PHY can recover ifa single frame with apreanible is sent to the PHY. The MDIO sync lost interrupt can he used to detect loss of s'nchronization and, thus, enable recovery. 2. An event has occurred and the corresponding interrupt mask bit is enabled (set = 1). l.Sl Corporation 55 TTUQPHYETIQIIC Data Sheet Gigabit Ethernet Transceiver September 2007 Register Description (continued) Register Functions/Settings (continued) Table 46. PHY Status Register--Address 26 PHY Status Register Bit Name Description ll Autonegotiation Status MDI-X Status 10 Polarity Status 1 = PHY in standby mode. 0 = PHY not in standby mode. l0 = Master/slave autonegotiation fault. 01 = Parallel detect autonegoliation fault. 00 = N0 autonegotiation fault. 1 = Autoncgotiation is complete. O = Autonegotiation not complete. l = MDI-X configuration. I) = MDI configuration. 1 = Polarity is normal ( l0Base-T only). Speed Status O = Polarity is inverted (1 0Base-'1"only). ll -'=Undetermined. 15 'l4:l3 l2 9:8 PHY in Standby Mode Autonegotiation Fault Status Type Default Notes O 1 10 : 'l0()0Base--T. 01 l00Base-TX. 00 = l()Base--T. 7 Duplex Status 6 Link Status 5 Transmit Status 4 Receive Status 3 Collision Status 2 Autonegotiation Enabled PAUSE Enabled = Full duplex. : I-lalfduplex. l 0 Asymmetric Direc tion = Link is up. = Link is down. = Pl lY is transmitting a packet. () = PHY is not transmitting a packet. = PHY is receiving atpacket. I PHY is not receiving a packet. = Collision is occurring. = Collision not occurring. = Both partners have autonegotiation enabled. I Both partners do not have autonegotiation enabled. = Link partner advertised PAUSE mode enabled. = Link partner advertised PAUSE mode disabled. = Link partner advertised direction is symmetric. = Link partner advertised that direction is asymmetric. 1. This bit indicates that the Pi lY is in standby mode and is ready to perform IP phone detection or 'l"DR cable diagnostics. The PHY enters standby mode when cable diagnostic TDR mode is selected (23. I3 = 0) and the link is dropped. A software reset (0.15) or software power down (0. I l) can be used to force the link to drop. 56 LS1 Corporation Data Sheet September 2007 TruePHYET10llC Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 47. LED Control Register l-Address 27 LED Control Register l Bit 15 14 13 l2 l1 l0 9:8 7:4 3:2 Description Name = Two-color mode for LF.l)_i0O0 and LED_100. = Normal mode for LED_l 000 and l,ED_l O0. LED_1o0o/LEo_100 = Two-color mode for LED_LINK and LED_TXRX. Two-Color Mode LED_LlNK/LED_TXRX = Normal mode for l.ED_LINK and LED_TXRX. = Extended modes for LED_TXRX. LED__TXRX Extended = Standard modes for LEl)_TXRX. Modes I Extended modes for LED_I.lNK. LED_l,lNK Extended 0 = Standard modes for LED_LINK. Modes = Extended modes for LED_l00. l,ED__lO0 Extended I Standard modes for LED_l()0. Modes = Extended modes for LED_I 000. LED_1000 Extended = Standard modes for LED_1()00. Modes Reserved LED Blink Pattern Pause LED blink pattem pause cycles. 00 = Stretch LED events to 28 ms. LED Pulse 01 = Stretch LED events to 60 ms. Duration Two-Color Mode Default Notes O l R/W U 1 R/W 0 2 R/W 0 2 R/W 0 2 R/W 0 Z R/W R/W OX0 R/W l Type R/W 00 10 '= Stretch LED events to 100 ms. ll = Reserved. I Reserved O Pulse Stretch 0 l = Enable pulse stretching of LEI) functions: transmit activity, receive activity. and collision O= Disable pulse stretching of LED functions: transmit activity, receive activity, and collision. l. iftwo-color mode 1Senabled for pair LED_l_lNl\' and LED _"l"XRX,the signal output for LED_LlNK is equal to (l.ED_LlNK and Li.iD_TXRX). For the cuss where LED_LlNK and LED_TXRX are not mutually exclusive (e g , duplex and oollisionl this mode can simplify the extemal circuitry because it ensures either LED_LINK or LED_TXRX is on, and not both at the some time. The same rule applies to pair LED_l000 and l.ED_l00. 2. The LED function is programmed using this bit and register 28. LS1 Corporation 57 Data Sheet September 2007 TruePHY ET1011C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settin gs (continued) Table 48. LED Control Register 2--Address 28 LED Control Register 2 Bit 15:12 LED_'1'XRX 11:8 Type Default Notes As per 11:8. RW 1111 --~ Standard modes R/W 01()O -- Name LED_l..1N1( Description 0000 = l000Base-'1`. 0001 = l00Base-TX. 0010 = 1OBase-T. 0011 = 100013356-Ton, 100Base-TX blink. 0100 = Link established. 0101 = Transmit. 0110 = Receive. 0111 = Transmit or receive activity. 1000 = Full duplex. 1001 = Collision. 1010 = Link established (on) and activity (blink). 1011 = Link established (on) and receive (blink). 1100 = Full duplex (on) and collision (blink). 1101 = Blink. 1110 = On. 1111 = Off. Extended modes 0000 = 10Base--Tor 100Base-TX. 0001 = Resewed. 0010 1 Reserved. 0011 = Reserved. 01.00 I 10001-Ease-`1" (on) and activity (blink). 0101 = 10Base-T or 100Base-TX (on) and activity (blink). 011x = Reserved. 7:4 1.1-,'1)_100 As per 11:8. 3.0 1.1;-)D_1000 As per 11:8. RW R/W 1111 --- 0000 -- Table 49. LED Control Register 3-Address 29 LED Control Register 3 Bit 1 Name 15:14 LED Blink Pattern Address 13:8 LED Blink Pattcm Frequency 7:0 I LED Blink Pattern Description 1 Type i Default | Notes Select LED blink pattern register set. O0I Select register set for 1.ED_1.1NK. 01 = Select register set for 1.ED_TXRX. 10 = Select register set 1'0:-1.El)_l000. 11 = Select register set for LED_100. LED blink pattern clock frequency divide ratio. R/W 00 --- R/W ilxlf l LED blink pattern. R/w} 0x2: 1 I 1. The default pattem is a 512 ms blink 58 LS1 Corporation Data Sheet September 2007 TruePHYETl0ll C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 50. Diagnostics Control Register (TDR Mode)--Adtlress 30 Diagnostics Control Register (TDR Mode) Bit Name Description Type Default Notes 15: I4 TDR Request ll = Automatic TDR analysis in progress. 10 = Single-pair TDR analysis in progress. 01 = TDR analysis complete, results valid. O0= TDR analysis complete, results invalid. R/W 00 1 13:12 TDR Tx Dim Transmit dimension for single-pair TDR analysis. O0= TDR transmit on pair A. Oi = TDR transmit on pair B. 10 = TDR transmit on pair C. ll = TDR transmit on pair D. R/W ()0 2 ll:lO TDR Rx Dim Receive dimension for single-pair TDR analysis. O0 = TDR rcccivc on pair A. ()1 = TDR receive on pair B. 10 = TDR receive on pair C. R/W 00 2 R/W 0 3.4 I I = TDR receive on pair D. 9:2 Distance to Fault l :0 Reserved Distance to open or short fault. 1 Automatic TDR analysis is enabled by setting TDR request to (ll ). All 10 combinations of pairs are analyzed in sequence, and the results are available in registers 30 and 31. TDR analysis for a single-pair combination can be enabled by setting TDR request to {I0} Diagnostics must be enabled (1 8.2 = I), cable diagnostic TDR must be mode selected (23.13 = O),and the PHY must be in Pl-lY standby mode (26.15 '--l) to perform TDR operations. Bit l5 sch" clears when the TDR operation is complete. When TDR is complete, bit 14 indicates whether the results are valid. 2. TDR transmit and receive dimensions are only valid for single-pair TDR analysis. They are ignored for automatic TDR analysis when all l0 pair combina tions arc analyzed. 3. This is the distance to an open, short, or strong impedance mismatch fault on the chosen pair for single~pair TDR analysis. For automatic TDR analysis, this returns the distance to the last open, short, or strong impedance mismatch fault found. The automatic algorithm searches for faults in the order of short between C and D. B and D. B and C, A and D, A and C, A and B; and faults on pair D. pair C, pair B. and pair A. Iflhere is no fault, the result will be Oxff and should he ignored. 4. The 8-bit integer value can be linearly converted to distance in meters. The value 0x08 (or less) corresponds to a distance of 0 m, and the value Oxte corre~ sponds to a distance of 200 m (180 ni for Cat-3 cable). The following equation can be used to convert the integer value to meters: distance (m) i l.l79 X(x- 8) XNVP Where, NVP I normalized velocity ofpropagation (typically 0.69 for CATS, C/\'l'5e. and CAT6; 0.62 for CAT3). For CATS/Sc/'6cable. a simple approximation (accurate to 0.1%) is (x '--8) x 13/16. LS1 Corporation 59 TruePHYETlD11C Gigabit Ethernet Transceiver Data Sheet September 2007 Register Description (continued) Register Functions/Settings (continued) Table 51. Diagnostics Status Register (TDR Mode)--Address 31 Diagnostics Status Register (TDR Mode) Bit Name Description Type Default Notes 15:14 TDR Fault Type Pair A (or fault type for single pair combi nation) 11 = 10 = 01 = O0= Short found on pair A. Open found on pair A. Strong impedance mismatch found on pair A. Good termination found on pair A. R/W ()0 l 13:12 TDR Fault Type 11 = Short found on pair B. 10 I Open "foundon pair B. 01 = Strong impedance mismatch found on pair B R/W 00 -- Pair B 00 I Good termination found on pair B. 11:10 TDR Fault Type Pair C 1I = Short found on pair C. 10 = Open found on pair C. Ol = Strong impedance mismatch found on pair C O0= Good termination found on pair C. R/W 00 9:8 TDR Fault Type Pair D ll = Short found on pair D. I0 = Open found on pair D. O1= Strong impedance mismatch found on pair I). ()0= Good termination found on pair D. R/W 00 7 Short Between R/W O _._ Pairs A and B I = Short between pairs A and B. O= No short between pairs A and B. 6 Short Between Pairs A and (I l = Short between pairs A and C. 0 = N0 short between pairs A and C. RIW 0 _ 5 Short Between Pairs A and l) 1 1 Short between pairs A and D. O= N0 short between pairs A and 1). R/W 0 _. 4 Short Between Pairs B and C 1 = Short between pairs B and C. 0 = No short between pairs Band C. R/W () __ 3 Short Between Pairs B and D 1 = Short between pairs B and D. 0 = N0 short between pairs B and D. R/W O _. 2 Short Between Pairs C and D 1 = Short between pairs C and D. 0 = No short between pairs C and D. R/W 0 _ 7 1 :0 Reserved 1. For automatic TDR analysis. this returns the fault type on pair A. For single-pair TDR analysis, this returns the fault type on the pair combination under test, i.c., as specified in the TDR Tx Dim and Rx Dim (30. 13:12 and 30.11110, respectively). 60 LS1 Corporation Data Sheet September 2007 TruePHYETl0ll C Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 52. Diagnostics Control Register (Link Analysis Mode)--Address 30 Diagnostics Control Register (Link Analysis Mode) Type Default Notes Pair Swap on Pairs C 1 = Pairs C and D are swapped (l00OBase-T only). and D 0 = Pairs C and D are not swapped (l 000i-Base-Tonly). R/W 0 See Table 53. Cable Length Cable length when link is active. R/W O 1 4 Polarity on Pair D l I Polarity on pair D is normal (l000Basc-T only). 0 = Polarity on pair D is inverted (l0O0Base-T only). R/W 0 3 Polarity on Pair C l = Polarity on pair C is normal (1000Base-'l` only). O= Polarity on pair C is inverted (l000l3asc-T only). R/W 0 2 Polarity on Pair B 1 = Polarity on pair B is normal (l000Base-'l" only). 0 = Polarity on pair B is inverted (lO00Base-T only). R/W 0 l Polarity on Pair A l = Polarity on pair A is normal (1000Base-'1` only). 0 = Polarity on pair A is inverted (l0()0Base-T only`). R/W O O Excessive Pair Skew 1 = Excessive pair skew (lOO0Base-T only). 0 = Not excessive pair skew (l0O0Base-T only). R/W 0 Bit l5:l2 l1 l0:5 Name Description Reserved 2 1. This is the cable length estimate when the link is active (maximum of I55 rn). The values of 0x00 to Oxifcorrespond to 0 m--l $5 m in S m increments. The values of 0x20 to 0x3e are reserved for future use, e.g., cable lengths of 160 m--315 m. The result may be invalid for a l0Base-T lllll\'. if the result is invalid, a value of0x3f is returned. 2. lalxcessivepair skew is detected by determining that the scrambler has not acquired. ll is possible for other scrambler acquisition errors to be mistaken for excessive pair skew. The following table shows the mapping ofthe transmitter and receiver for MDI and MD]-X configuration for 100()Basc-T when pairs C and D are not swapped and are swapped. Table 53. MDI/MD]-X Configuration for 1000Base-T with C and D Swapped/Not Swappcd Pin Pair C and D Are Not Swapped MDI-X Pair C and D Are Swapped MDI Configuration MDI-X lVlDlConfiguration Configuration TRD_[0:7]_|i0'|+/-- Transmit A+/-Receive B+/-- Transmit B+/-- Receive /\+/~ Transmit A+/-- Receive B+/~ Transmit B+/-- Receive A+/--- TRD_[0:7]_[l ]+/-- Transmit B+/-Receive Transmit A+/~ 'l`Rl)_[0:7]_[2']+/ '1*no__[0=7]_[3]+/ LSI Corporation Configuration A+/-- Receive 13+/~ Transmit B+/-- Receive A+/A Transmit A+/~ Receive B+/' Tiansmit C+/-- Rcceive D+/-- Transmit D+/ Transmit C+/- Transmit D+/ Receive C+/-- Receive C+/A Receive D+/-- Transmit D+/-- Receive C+/Y Transmit C+/~ Transmit D+/-- Transmit C+/-- Receive D+/-- Receive D+/~ Receive C+/4 61 TruePHYET10llC Gigabit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress rat ings only. Functional opcration of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 54. Absolute Maximum Ratings Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V/2.5 V digital) Max Min Symbol AVDDH 4.2 AVDDL 1.2 D\/DDlO 4.2 Von Vest: l.2 2000 | Unit I Supply Voltage (1.0 V digital) ESD Protection -40 TSTORE Storage Temperature l 25 C Recommended Operating Conditions Table 55. ETl0l1C Recommended Operating Conditions Parameter Symbol Min Tyv Max 2.62 Unit AVDDH 2.38 2.5 /\\/poi. l.0orl.l l.l5 3.3 2.5 3.46 2.62 Von 0.95 3.14 2.38 0.95 l.O0rl.l 1.15 TA 0 70 C Ambient Operating Temperature------lndustrial TA -40 85 C Maximum Junction Temperature Thermal Characteristics. 128 TQFP (JDEC 3 in. x 4.5 in. 4-layer PCB): TJ 0 l25 Supply Voltage (2.5 V analog) Supply Voltage (l .0 V analog)` Supply Voltage (3.3 V digital)2 Supply Voltage (2.5 V digital? Supply Voltage (1.0 v digital)` Ambient Operating Temperatu re---Commercial DVoD|o DV Doio TJB 29 TJC 33 \|I.lT 0 m/s airflow l m/s airflow 2.5 m/s airflow Thermal Characteristics, 84-pin MLCC and 68-pin MLCC (IDEC 3 in. x 4.5 in. 4-layer PCB): 0 m/s Airflow l m/s Airflow 2.5 m/s Airflow "C "C/W l Tm 37 32 30 TJB 10 Ti <1 3 TJA TJA C./W um l TJA 24 Tm Tm 23 21 l. For the l28-pin TQFP package operating over the industrial temperature range. the maximum voltage is reduced from l.l5 V to 1.05. V.The center tap voltage range is changed to l.8V only. 2. The part can operate at either 3.3 V (typically for an GMII interface) or 2.5 V (typically for an RGMII interface). 62 LS1 Corporation Data Sheet September 2007 TruePHYET101lC Gigabit Ethernet Transceiver Electrical Specifications (continued) Device Electrical Characteristics Device electrical characteristics refer to the behavior of the device under specified conditions imposed on the user for proper operation of the device. Unless otherwise noted, the parameters below are valid for the conditions described in the previous section, Recommended Operating Conditions. Table 56. Device Characteristics--3.3 V Digital I/O Supply (DVDDIO) Max Unit -l0 I0 u/\ lILcak -lO0 100 uA Input Low Voltage Vn. v0.3 0.8 V Input High Voltage Vin 2.0 3.6 V 0.4 V Symbol Min Input Leakagel (digital pins without pull-up or pull-down) llLeak Input Leakage (digital pins with pull-up or pull-down) Parameter TYP Output Low Voltagez Vot Output High Voltagc3 Von 2.4 Differential Output Voltage (analog MDI pins l000Base-'1`) V 0131H-` 0.67 0.75 0.82 V Differential Output Voltage (analog MDI pins IO0Basc-TX) VODII-"F 0.95 1.0 1.05 V Differential Output Voltage (analog MDI pins 10Base-T) VODII-`F 2.2 2.5 2.8 V Symbol Min WP Max Unit Input Leakage (digital pins without pull--upor pull-down) In. -10 10 uA Input Leakage (digital pins with pull-up or pull-down) lu. -100 100 uA -0.3 l.7 0.7 V 2.8 V 0.4 V V Table 57. Device Characteristics--2.5 V Digital l/O Supply (DVDDIO) Parameter Input Low Voltage V 11.. Input High Voltage VII-I Output Low Voltage; VOL V Von 2.0 I)it'ferential Output Voltage (analog MD] pins lO0OBase-T) VODIFF 0.67 0.75 0.32 V Differential Output Voltage (analog MDI pins lO0Base-TX) VODII-`F 0.95 1.0 1.05 V I)iflerentia1 Output Voltage (analog MDI pins lOBase--T) VODIFF 2.2 2.5 2.8 V Output High Voltage3 I RESET N pin IILeak max=1mA when DVVDIO is more than 0.8V above the AVDDII supply. 2. All pinsitested with IOL=4mA except for the following pins: RXD[3:0]==3mAin Mll mode only; MDlNT__Nand MDlO=9mA, 'I`DO1l4mA. 3. All pins tested iwth IOH==3mAexcept for the following pins; RXD[3:0]=2mA in MII mode; MDINT__Nand MDIO=6mA with VOlImin'--].9S\/, TDO:8m/\ with VOI-lmin=l.95V. PHYADOand PI-IYADI =5rna with VOHmin=l.95V. LSI Corporation TruePHYET10l1C Gigahit Ethernet Transceiver Data Sheet September 2007 Electrical Specifications (continued) Device Electrical Characteristics (continued) Table 58. ETl011C Current Consumption 1000Base-T Min Max Unit Symbol Condition Supply Voltage (2.5 V analog) lavoon Tx/Rx random data 62 in/\ Supply Voltage (1.0 V analog) lAVDDL Tx/Rx random data 205 mA Supply Voltage (3.3 V digital - GMII mode) or (2.5 V digital - RGMll mode) lovooio Tx/Rx random data 30 20 mA mA Supply Voltage (1.0 V digital) l\/on 131 mA Center Tap Voltage (1.8 V or 2.5 V analog) ICTAP 183 mA Parameter TX/Rx TYP random data Tx/Rx random data Table 59. ET1011C Current Consumption 1l]0Base-TX Max Unit Symbol Condition Supply Voltage (2.5 V analog) lavoon Tx/Rx random data 20 mA Supply Voltage (1.0 V analog) lA\/DDL Tx/Rx random data 55 m/\ Supply Voltage (3.3 V digital - Mll mode) or (2.5 V digital - RGMII mode) lovnmo 22 14 mA mA Supply Voltage (1.0 V digital) lvoo Tx/Rx random data 23 mA TX/Rx 40 mA Parameter Min TX/RX random data lCTAP Center Tap Voltage (1.8 V or 2.5 V analog) Tyn random data Table 60. ET101lC Current Consumption 10Base-T Min Max Unit Symbol Condition Supply Voltage (2.5 V analog) lAVDl)H Tx/Rx random data 20 mA Supply Voltage (1.0 V analog) IAVDDL TX/Rx 55 mA Supply Voltage (3.3 V digital - Mll mode) or (2.5 V digital - RGMII mode) 1ox-131510 20 14 mA mA Parameter Typ random data TX/Rx random data Supply Voltage (1.0 V digital) lwm Tx/Rx random data ll mA Center Tap Voltage (1.8 V or 2.5 V analog) Iornr Tx/Rx random data 60 mA 64 LS1 Corporation Data Sheet September 2007 TruePHYET] 011C Gigabit Ethernet Transceiver Electrical Specifications (continued) Device Electrical Characteristics (continued) Table 61. ET1l)11C Current Consumption 10Base-T Idle Min Max Unit Symbol Condition Supply Voltage (2.5 V analog) lAVDDl-l ldle 20 mA Supply Voltage (1.0 V analog) lAVl')DL Idle 55 mA Supply Voltage (3.3 V digital - Mil mode) or (2.5V digital - RGMII mode) lI)\'DDlO ldle 16 l0 mA mA Parameter Supply Voltage (l .0 V digital) Center Tap Voltage (1.8 V or 2.5 V analog) Typ l\/on Idle ll mA lCTAP Idle l mA Table 62. ETl01lC Current Consumption Hardware Powerdown Min Max Unit Symbol Condition Supply Voltage (2.5 V analog) lAVDDH Hardware Powerdown 2 mA Supply Voltage (1.0 V analog) lA\'Dl)l. Hardware Powe rdown 6 mA Supply Voltage (3.3 V or 2.5 V digital) lDVl')DlO Hardware Powerdown 7 m/\ lvon Hardware Powerdown 3 mA Hardware Powerdown 0 mA Parameter Supply Voltage (1.0 V digital) Center Tap Voltage (1.8 V or 2.5 V analog) lC'I'AP TYP Table 63. ETl01lC Current Consumption Low Power Energy Detect (LPED) Min Max Unit Symbol Condition Supply Voltage (25 V analog) lAvonH LPED 4 mA Supply Voltage (1.0 V analog) lAVDDL LPED 6 mA Supply Voltage (3.3 V or 2.5 V digital) l.DVD]')lO LPED 7 mA lvoo LPED 3 mA ICTAP LPED 0 m/-\ Parameter Supply Voltage (1.0 V digital) Center Tap Voltage (1.8 V or 2.5 V analog) LS1 Corporation Ty! 6: TruePHYET10llC Gigabit Ethernet Transceiver Ei6Cfl'iC3i Specifications Data Sheet September 2007 (continued) Device Electrical Characteristics (continued) Table 64. ETl0llC Current Consumption Standby Powerdown and Standby Powerdown with LPED Parameter Symbol Condition Min Typ Max Unit ~-- mA Supply Voltage (2.5 V analog) IAVDDH Standby Powerdown Mode with LPED A 5 Supply Voltage (1.0 V analog) iAVDDL Standby Powerdown Mode with LPED -- 20 - mA Supply Voltage (3.3 V or 2.5 V digital) iDVl)l)l0 Standby Powerdown Mode with LPED ~ 12 -- mA Supply Voltage (1.0 V digital) Ivpo Standby Powerdown Mode with LPED ~-- 13 ---- mA Center Tap Voltage (l 48V or 2.5 V analog) ICTAP Standby Powcrdown Mode with LPED -~ O 4 mA Table 65. ETl0llC Current Consumption Software Powerdown Symbol Condition Min Typ Max Unit Supply Voltage (2.5 V analog) l AVunn Software Powerdown -- 20 -- mA Supply Voltage (l.O V analog) IAVDDL Software Powerdown ~ 59 ----- mA Supply Voltage (3.3V or 2.5 V digital) iDVDDlO Software Powerdown --~ ll --- rnA Supply Voltage (1.0 V digital) lvnn Soliware Powerdown -- ll -- mA Center Tap Voltage (1.8 V or 2.5 V anal Q2) l ("mp Sofiware Powerclown ~ 0 -- mA Parameter 66 LS1 Corporation Data Sheet September 2007 TruePHYETl01lC Gigabit Ethernet Transceiver Timing Specification GMII l000Base-T Transmit Timing (128-Pin TQFP and 84-Pin MLCC Only) 5 I GTX_C LKc\/ms ( i GTX_CLKmm| K 5 > GTX_CLNfiW >< Z __. __. -. -______-_____- ;__.-._-____-___. I , --_____-__..__ I GTX_CLK GTX_CLKF*~'=*-->1 I<-- o<o[7;o] TX EN TX ER -*'-GTX_CLKmsa . ______ ____ . . ___. . . ___. . . . ____. ___. . _. _ _. _ ,-j I __. . . _-;_;-__-____---_---__---- GTX CLMww GTX_C LKSU E4-:4 <---------m E Figure I5. GMII l000Base-T Transmit Timing Table 66. GMII l000Base-T Transmit Timing Parameter Symbol Min T p Max Unit 8.5 HS GTX_CLKcYcu-: GTX_CLl< Cycle Time 7.5 GTX_CLKi~noH G'l`X_CLK High Time 2.5 US GTX_CLKLOw GTX__CLKLow Time 2.5 US GTX_CLKR1sE GTX_CLK Rise Time GTX_CLKmu. (iTX_CLKsu GTX_CLK Fall Time I GMII Input Signal Setup Time to GTX_CLK GMII Input Signal Hold Time to GTX_CLK i (1`TX_CLKn01.o LSI Corporation 1.0 HS 1.0 HS 2.0 HS 0.() US TruePi`IYET101lC Glgablt Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) GMII 1000Base-T Receive Timing (128-Pin TQFP and 84-Pin MLCC Only) . RX_C LKCYCLE . K E >5 RX__cLKH\GH , K RX_CLKw~ E )( 2 . . . ____-.:. ______-_______ .j..1__<____.._._--__-...-.-__-____--`_ _--....____ K RX_CLK . . RX_Cl_KFALk----------); (-- ;<-----RX'cL|,(R|sE _. . . . . _. _. . _. ___, . . . . _____. . __________ ___. . . _. _..---__,_-.____-..-_____. _.. RXD[7:0] RX_ EN RX ER . _ ; 1 Z `.. . . _. . - - _ RX__ CLKSU F~"i--> ' . .._v__. RX_CLK.HOLD L Figure 16. GM]! 1l]00Base-T Receive Timing Table 67. GMII l0l]0Base-T Receive Timing Symbol RX_Cl.KcYcLE RX_CLKmsn Parameter RX__CLKLOw | RX_cu< Cycle Time | RX_CLK High Time | RX_CLK Low Time R'l`X~CLl<.1usE I RXMCLK Rise Time RX_CI.KFA1.1. I R.X_Cl.K Fall Time RX_CLKsU RX_CLKu0u> 68 l GMII Output Signal Setup Time to RX_CLK I GMII Output Signal Hold Time to RX_CLK Min Typ Max Unit 7.5 8.0 -- HS 2.5 --- HS 2.5 --- ns HS HS 2.5 -- T13 0.5 -- HS LS1 Corporation Data Sheet September 2007 TruePHY ET1011C Gigabit Ethernet Transceiver Timing Specifications (continued) RGMII 1000Base-T Transmit Timing Trace Delay rxc AT TRANSMHTER 1 TskewT TXD[B:5l[3:0] rxn(r;4][s;o1 TX_EN qrx_crt_) >< rxen TXERR TXD[4] ><rxo[e] ;; ; ---~>j I >< >< iiiiiiii TskewR TXC AT RECEIVER Figure 17. RGMII 10l]0Base~TTransmit Timing-~Trace Delay Table 68. RGMII l0UUBase-TTransmit Timing Symbol 'l'sl<ewT TskewR i Parameter l Data to Clock Output Skew (at tran smit'ter)--Trace Delay` Data to Clock Input Skew (at receiver)-Trace Delay` Tcyc Clock Cycle Durationz Duty_G i Duty Cycle for Gigabit3 Duty_T 'l`r/Tt' l Duty Cycle for l0Base-T/1O0Basc-TX3 [ Rise/Fall Time (20%-20%) Min i Max Unit Typ 500 -- 0 500 PS l 1.8 2.6 l'lS 7.2 8 8.8 l'lS 45 50 55 % 50 60 % 40 | 0.75 l'lS l. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see M11register 22 bits 2:0. 2. For l()Base-T and l00Basc-TX, Tcyc scales to 400 ns 4-40 ns and 40 ns Q 4 ns, respectively. 3_Duty cycle may be shrunk/slretclied during Speed changes or while transitioning to a received packefs clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the l0\\/est speed transitioned between LSI Corporation 69 TDMEPHYETl 011C ` Data Sheet Glgablt Ethernet Transcelver September 2007 Timing Specifications (continued) Internal Delay """""'\ / TXC AT TRANSMITTER '-`- "\ \ / ' \ / . INTERNAL =\. 1 ._._..J Q, rxc WITH '~i .' I r I \: -` VI __ -_/ DELAY ._l_._I rx0[a;5][s;o1 rxo[1;41[a;o3 rxn{s;o1>egE,fi} T$etupT ----v TholdT TX_EN (rx_cr|.) X TXEN TXERR 5 TXDH] ><TXD[9]>< >< TXC E4--- Thbld AT RECEWER TsewpR i<-- Figure 18. RGMII l000Base-T Transmit Timing---Internal Delay Table 69. RGMII l000Base-T Transmit Timing Min Tyv Max Unit Data to Clock Output Setup (at transmitter--integi~ated delay) 1.2 2.0 -- ns Thold'l' Clock to Data Output Hold (at transmltter--integrated delay)` 1.2 2.0 --- ns TserupR Data to Clock Input Setup (at receiver----integrateddelay)` 1.0 2.0 i ns TholdR Data to Clock Input Hold (at receiver--integrated delay)1 1.0 2.0 -- ns Tcyc Clock Cycle Durationz 7.2 8 8.8 ns Duty_G Duty Cycle for Gigabit3 45 50 55 % Duty__T Duty Cycle for l()Basc-T/l0()l3asc-TX3 40 50 60 % 0.75 ns Symhnl Tsetupl` Parameter 1 Tr/Tl' l Rise/Fall Time (2()%--8O%) The FHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2 O ns 2. For l0Basc-T and lO0Basc-TX, Tcyc scales to 400 ns 1-40 ns and 40 ns +_4 ns. respectively J Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packefs clock domain as long as minimum duty cycle ISnot violated and stretching occurs for no more than three Tcyc ofthe lowest speed transitioned between. 70 LSI Corporation Data Sheet September 2007 TruePH YET 10ll C Gigabit Ethernet Transceiver Timing Specifications (continued) RGMII 1000Base-T Receive Timing Trace Delay RXC AT TRANSMITTER -->1 TskewT RXD[8:5][3:0] RXD|_'I:4][3:0] RX_EN (RX_CTL) >< RX_DV >< RXERR -E -->j RXC ' >< 5 ' TskewR = AT RECEIVER Figure 19. RGMII 1000Base-T Receive Timing---Trace Delay Table 70. RGMII l000Base-T Receive Timing Symbol Tskew'l' Tskewk Tcyc Dut:y__G Duty_T 'l`r/Tf T Parameter I Data to Clock Output Skew (at transmittcr)~---Trace Delay` Data to Clock lnpul Skew (at ' receiver)---Frace Clock Cycle Durationz I Duty Cycle for Gigabit3 Duty Cycle for l0Base- I`/100Base-TX3 Rise/TallTime (20%-80%) Max Unit 500 PS 1 2.6 HS 7.2 8.8 l1S 45 55 % 40 60 Min Delay] -- Typ 0.75 l'lS 1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will he added to the associated clock signal. Tn enable imemal delay, sce MII register 22 bits 2:0. 2. For l0Base-T and l0OBase-'l`X, Tcyc scales lo 400 ns i 40 ns and 40 ns 1:4 ns, respecnvely 3` Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received pu/skefs clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. LS1 Corporation 7l TYMQPHYETIUIIC Data Sheet Gigabit Ethernet Transceiver September 2007 Timing Specifications (continued) Internal Delay '--""'\ 4 RXC .1 AT TRANSMFITER `W""\ \ 1 ./ \ . ._._.J RXD[8:5][3:O] RXD[7:4-][3:0] ' \ 1 I ._._.J RXD[3:0] ' ` ' I 1 `-- INTERNAL \ >< <- TholdT XWXWX X X RX_DV RXERR I RXC AT RECEIVER DELAY _/ ._._..J >< TsetupT -->1 RX_EN (RX_CTL) RXC WITH _/ \ X 1 14* Thold : Tsetu pR Figure 20. RGMII 1000Base-T Receive Timing--lnternal Delay Table 71. RGMII l00llBase-T Receive Timing Parameter Symbol TsetupT TholdT 'l'setupR TholdR | Tcyc l)uty_G l Duty__'l` l Tr/l'f Data to Clock delay)` Clock to Data delay)` Data to Clock Data to Clock Min Output Setup (at transrnitter--iritegrated 1.2 Tyv 2.0 Output Hold (zittransmitter---integraled 1.2 2.0 Input Setup (at receiver---lntegrated delay)` Input Hold (at receiver--integ1'ated dela}/)1 LO 2.0 2.0 I Clock Cycle Duration` l Duty Cycle for Gigabit-" | Duty Cycle for l0l3ase-T/lO()Basc-TX" | RisefFall Time (20%--80%) Max Unit ----- |'lS ---- HS - ns ~ ns 8 8.8 ns 45 50 55 % 40 50 60 0.75 % ns l.() 7.2 l. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2_Ons 2. For l0Base-'l" and l00Base-TX, `l"cycscales to 400 ns 5:40 ns and 40 ns 1 4 ns, respectively. 3 Duty cycle may he Shl"l.ll'll{/Sll'5tCl1d during speed changes or while transitioning to a received packefs clocl-;domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Toys of the lowest speed transitioned between. 72 LS1 Corporation TruePHYET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) MII l00Base-TX Transmit Timing . TX__C L KCVCLE K I K TX_CLK<\sn _. . . ____4 __________--. I TX___CLK 3 TX_,C1-KI-OW >4 H 4,. _ __ _ __ . _ . _ ___-` _ ___ . ,1 ,4 . ___. __ , _____. . . . _. . ---i-A ..-_-__-__-._-_ ,.-__. I Tx~CLKF'\"Li :"""_ :"""'TX CLKRisE TXD[3ZO] TX_EN TX_ER1 -- -- -- ---- ----- ----------------------- --- , ,I - - - - ---.--a-- TX TX_CLKsu CLKHOLD E<------->` <-----i------------>' E 1. 'I`X_ER is not available on the 68-pin MLCC. Figure 21. MII 100Base-TX Transmit Timing Table 72. MII l00Base-TX Transmit Timing Parameter Symbol TX__CLKcvcuz '1"X__CLKn1<;n TX_C l 4KLQW TX__CI , KRISE T X__CLKl-`ALL TX_Cl.Ksu TX_CLKHOLD LSI Corporation TX_CLK TX_CLK TX_CLK TX_CLK TX_CLK Min | MII Input Signal Hold Time to TX_Cl,K Max 40 20 20 Cycle Time Iiigh Time Low Time Rise Time Fall Time i Ml] Input Signal Setup Time to TX_CI,K TYP Unit l'iS HS HS 5 HS 5 I15 15 l'lS 0 HS Data Sheet September 2007 TruePHYET1011C Gigabit Ethernet Transceiver Timing Specifications (continued) MII 100Base-TX Receive Timing 1 K RX_C LKcvc LE )1 4 i )( RX_CLK111s+< ' 1 RX__CLKuJw >i 111 _. . . . . ____. ___ LJ_______._-.___. . 1 1 '1 RX_C LK __. _. _. ___. _. . . . _______L'__-_------____'_J-_-_~ RX_CLK1=111k_>i j<_ 5 CLKRISE 1 1 1 RXD[3:0] """"""""""""""""""""""""""""""" 1 __ RX_EN RX --ER .1, _. ____ . ___ _. ______ _. _. . . ___. . ____. . _. _ _. . . _. __._.F_r_______-._...--.__'-__ 1 _ RX_CLKsu;<--i>'g - 3 . RX__CLK11o1.0 . Figure 22. MII l00Base-TX Receive Timing Table 73. Mll l00Base-TX Receive Timing Symbol ` Parameter Min R)(_CI..KcYc1.E 1RX_CLK Cycle Time RX_CLKH1011 | RX_CLK High Time RX_CI..K1.0W | RX_CI,K Low Time RTX_CLKR1sF. | RX_Cl,K Rise Time RX_CLKFAL1_ RX_CLK Fail Time RX_CLKsu Mil Output Signal Setup Time to R.X_CLK RX__CLKH01_n MII Output Signal Hold Time to RX_CLK 74 Typ 40 20 20 1 1 Max Unit HS HS HS HS HS ]() HS 10 HS LS1 Corporation TruePH YET101l C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Specifications (continued) M1110Base-T Transmit Timing | '4 ' TX_CLKCYCLE >' TX_CLK>-new 3 TX_C|-KLOW X K >:< -.1 . _______.; ____. . . . . . . .__ ;.1.____._._____.Ll | . > _`..____.... , TX_C LK | I v . .v_ _ _ __ __ . _ . . . . ..'._-_ TX--CLkALL% T" _ . . . . . . __ . _. `iTX__CLKR1sE -\._----___ TXD[3I0] TX_EN TX_ER 1_ , TX_CLKsu J 5 . :<i------> TX_CLK)iQLD . 1 Figure 23. MII l0Base-T Transmit Timing Table 74. Ml] 1llBase-T Transmit Timing Min Q Symlwl Parameter TX_CLKcYCi_E TX__CLK Cycle Time TX_CLKi11GH TX_C LK High Time TX_CLK1.,0w TX__CLK Low Time TX_CLKRisF. TX_ (ILK Rise Time TX_CLKFALL TX_CLKsu TX i CLKHQLD LSI Corporation Max Unit 400 200 I'lS ZOO HS 1 HS 1 | TX_CLK Fall Time | Mli Input Signal Setup Time to TX_CLK | MII Input Signal Hold Timc to TX_(ZLK TYP ns I15 15 1'15 0 l'1S 75 Data Sheet September 2007 TruePHYET10llC Gigabit Ethernet Transceiver Timing Specifications (continued) MI] 10Base-T Receive Timing . RX___Ci_KCYCLE K 1 K >I RX_CLK>~usH )(: RX_C LKLOW X . . ______4 __-___._______ ;J.____________ _.; -_ 1|! RX_CLK RX_CLKF\LL----* <------ <--Rx_c|_KR.sE RXD[3:0] __________________________________________ - RX_EN RX_ER _ RX_CLKsu - 1 l RX__CLKHOl_D ; 2<----------->'1 Figure 24. Mll 10Base-T Receive Timing Table 75. Mll l0Base-T Receive Timing Symbol Parameter RX_CLKc\/cu: l RX_CLl<Cycle Time Min RX_CLKH1GH RX_CLK High Time RX_CLKLow RX_CLK Low Time ` RTX_CLKR1s1=.' RX__CLK Rise T irnc -- RX_CLK]-`ALL i RX_CLK Fall Time -- 76 Max Unit HS HS HS 1 HS l HS HS RX_CL Ksu ,K RX__CLKi-[OLD ` Mil Mll Output Output Signal Signal Hold Setup Time TimetotoRX_CI RX_CLK Typ 400 200 200 10 10 HS LS1 Corporation Data Sheet September 2007 TruePHY ETl01l C Gigabit Ethernet Transceiver Timing Specifications (continued) Serial Management Interface Timing MDCcYc|_E i MDCHIGH : . MDCLQW Z 4- ................... --..--.. .;_.;.................. .........;..;. MDC <--|\/lDCR\sE MDIO (INPUT) .......................................................................... -.............;.;..i MDCHOLD MDCsu ................................................................. .. ; ................4.......... MDC |v|0|o (OUTPUT) ...... A4 -...,.. ....... ....,___...... MDCDE LAY Figure 25. Serial Management Interface Timing Table 76. Serial Management Interface Timing Symbol I\/IDCCYCLE MDC!-non MI)C|.0w IVIDCRISE MDC;-1\LL MDCsU lVlDCH0l.D M DC DELAY LSI Corporation i Parameter l MDC Cycle Time I MDC High Time MDC Low Time ' MDC Rise Time l MDC Fall Time MDIO Signal Setup Time to MDC MDIO Signal Hold Time to MDC MDIO Delay Time from MDC I Min TYP Max 100 Unit HS 40 40 1'15 HS 5 HS 5 HS 10 HS 10 HS 80 l'lS TruePH YET1011C Gigabit Ethernet Transceiver Data Sheet September 2007 Timing Sp6CifiCflti0IlS (continued) Reset Timing K RESETPL|LSE_LEN j _ RESETCFGJREAD RESET N RESETHSE LED_xx LED pins are Inputs I LED pins are Outputs SYS_CLK I K COMA COMAPULSE LEN _ Y 1 CoMAc1=a ' READ ~f "*cOMAALL LED_xx LEDpins are Inputs LED pins are Outputs SYS CLK 1<_COMAw_sYs_cu:c :<-i--i*I COMA |_svs_cu<_v|m Figure 26. Reset Timing Table 77. Reset Timing Symbol t 1 RESETPULSEWLEN [ RESET_N Pulse Length 1 RI1-ISE'l`R1si=. | RESET_N Rise Time RFSET( rm READ COMAPuL;5_|.E1~.' CON]/\FAI.L COMA'ro sx/s,c1.|< Min Parameter REl"T_N DdS5TliO1'1 to Configuration 20 1.0 78 Max Unit _ pg -- | COMA Pulse Length 1COMA Fall Time 1COMA Deassertion to SYS_CLK {COMA Deasscflion to Configuration Read HS ITIS Read COMA'r0__sYs_cLK_w.1.iDI COMA Dctassertion to SYS_CI,K Valid COMAcFG_READ Typ 20 __ H3 1.0 ---- [IS 1.0 _ "S ITIS IIIS LSI Corporation Data Sheet TruePH YET1 011C September 2007 Gigabit Ethernet Transceiver Timing Specifications (continued) Clock Timing I XTAL__1 cvctz 7. .< : XTAL__1w@| E XTAL_1t@w >1 2` . . __. ___-__|___...-__-..._----.. _...._--......._.__..___._\. ____..._ | I 1 1 - XTA L_1 | 1 vl --. t XTA|__1FAu. XTAL_'lR\sE Figure Z7. Clock Timing Table 78. Clock Timing Symbol X'l`AL_lcYc|_E Parameter XTAL_1 Cycle Time XT./\L_iHlGH XTAL_1 High Time XTAI,._Ii.0\v XT/\L_l Low Time XTAL_l RISE Min TYP 39.998 I5 40 20 20 15 XTAL_1 Rise Time XTAL 1i=Ai.1. IXTAL ]Fa1lTime Q i | XTAL:] Input Clock mm (RMS) -- | XTAL_1 Input Clock Frequency -- \ X'l`AL_1 Input Clock Accuracy LS1 Corporation Max Unit 40.002 l'lS 25 HS 25 I15 3 HS 3 HS 20 pS MHZ 25 SO PP1" TTHEPHYETIOIIC Data Sheet Gigabit Ethernet Transceiver septem ber 2007 Timing Specifications (continued) JTAG Timing TCKc~rcLE . E . . TCKHHGH g TC Kww t .. . . . _._. .-....._____-_ TCK . ______ . __. . . _. . . . . _.-.'.t \._-_.________. ,_. TCKFAU-_-)E :g-TCKRISE TDI TMS -"H 5' TKs~ II:IIIllIX TDO E? TCKHOLD 2 iiiiiiiiiiiiiiiiii iiiii TC KDELAV Figure 2s. JTAG Timing Table 79. JTAG Timing Symbol TCKCYCLE 'l`Cl<;n1csn TC K|_0w TCKR|s12 TCKFALL TCl~'.sL' TCKHOLD TCKDELAY 80 i Parameter I TCK Cycle Time "rc1< High Time TCK Low Time TCK Rise Time 1TCK Fall Time TD], TMS Setup Time no TCK TDI, TMS Hold Time to TCK TDO Delay Time from TCK Min Typ Max Unit 20 X15 10 T15 10 HS l HS 1 HS 2.7 0.8 I13 TIS 8.1 l'lS LS1 Corporation TruePHY ET.1011C Data Sheet September 2007 PBCk2lg Diagram, Gigabit Ethernet Transceiver 128-Pin TQFP (Dimensionsare inmillimeters.) Note: Package outlines are unofficial and for reference only. 16.00 i 0.20 14.00 1' 0.20 PlN #1 1DEN'1'lFlER ZONE 128 103 1 -1 102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -111 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 38-1 20.00 i 0.20 22.00 iO.20 \-___._______-_-Z/ 65 1 -_______._.Y_ 39 1.40 i 0.05 [ DETAIL./\ 1 /-- DETAILB I ' --T - 1.6+;MAX I\ IllI|||l|l|||||ll|||||||||||||||l!|lll|l|||||l||||IIII / ' ' ' ' ' ' ' ' ' ' ' ' ' ' - _' ' ' ' - - - - _Ti` xT' ' -->ll<---5 TY? l 1 swmc. PLANE 0.05/0.15 E 1.00 REF 0.25 GAGE PLANE SEATINGPLANE L [(1.106/'0.'ZOO 0.45/O. 75 0.19/0'27 _'| 1 DETAIL A LS1 Corporation 81 Data Sheet TruePHY ET1011C September 2007 Gigabit Ethernet Transceiver Package Diagram, 84-Pin MLCC (Dimensions are in millimeters.) Note: Package outlines are unofficial and for reference only. mango z3amfiu:> uzfi.Ew L. Tl >ma:m> J >m :>; . y-......---_-_....-..-_-......-_-_-......;" K .. <58.. S"ZE m_nFzmo_ 82 nN.o _:|Q _.o.o "zaTf.iuom mzn8\._a>Eu Two.gig/_fit uaBm\._zsE~ C.JCZHSM 98 mm: LS1 Corporation Data Sheet n Cr. M TSw m m e W September 2007 Package Diagram, 68--Pin MLCC (Dimensions are in millimeters.) Note: Package outlines are unofiicial and for reference only. uzt<fi.ma Iz>Em.:eawHp Fu._9ilIGEdwuzae_-gb/4|._IJ18om6TEz~ euSBl3<\> mad . ,.---..-....----......-----....-----.. -`s E +2 Lu 9 LS1 Corporation #.i4| TruePHYETl0l1C Gigabit Ethernet Transceiver Data Sheet September 2007 Ordering Information Table 80. Ordering Information Device/Package Part Number` Description Comcode ET 101 1C Commercial GbE Transceiver, Lead-Free L-ET1011C2-C-D 711017464 84-pi n MLCC Commercial GbE Transceiver, Lead-Free L-ET1011C2-C-DT 711017465 Industrial GbE Transceiver, Lead-Free L-ET1011C2-C1-D 711017462 Industrial GbE Transceiver. Lead-Free L-ET1011C2-Cl-DT 711017463 Commercial GbE Transceiver, Lead-Free I.-ETl011C2-M-D 711017468 Commercial GbE Transceiver, Lead-Free L-ET1011C2-M~D'l` 711017469 Industrial GbE `lransceiver. Lead-Free I.-ETl01lC2-MI-D 711017466 Industrial GbE Transceiver, Lead-Free L-ETl 0 l1C2-Ml-DT 711017467 Commercial GbE Transceiver, Lead-Free L-ET10l1N1C-T-DB 711010940 BT10! 1C 68-pin MLCC E'l'1 01 1C 128~pin TQFP2 lead-free, -DT I Tape and Reel. 5 is revision 3, "C" silicon (not revismn 4, "C2" Hind is not recommended for new designs. 84 LS1Corporation TruePHYET101lC Gigabit Ethernet Transceiver Data Sheet September 2007 IEEE is a regisiered trademark of the Institute of Electrical and Electronics Engineers, lnc. Magic Packer 1Sa registered trademark of Advanced Micro Devices, Inc. For additional informaiiun. contact your LSI Account Manager or the following: INTERNET: Home: http:IIwww.lsi.com E-MAIL: docmaster@agere.com N. AMERICA: LSI Corporation, Coporate Headquarters` 1621 Barber Lane, Mipilas, CA. 95035 1-800-372-2447, FAX610-712-4106 (In CANADA:1-800-553-2448, FAX610-712-4106) ASIA: CHINA:(as) 21-54614688 (Shanghai), (ss)1ss-2ssa1122 EUROPE: JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAlWAN;(885) 2-2725-5858 (Taipei) Tel. (44) 1344 865 900 (Shenzhen), (as) 10-ssaswee (Beijing) LSI Corporation resewes the right to make changes to the productis) or inlormalion ooniained herein wiihoui notice No iiabiliiyis assumed as a result of their use or EipP||C3iiGl'I LSI and ma LSI Iago are trademarks of LSI Corporation. Allother brand and prnduct names may be rrademarks of iheir respective companies. TruePHY is a irademark of Agere Systems inc Copyrighi(c) 2007 LSI Corporation Ail Rights Reserved September 2007 DSD6-161GPHY-4(Replaces D806-161PHY-3. D506-i61GPHY-2, DS06-161GPHY-1 and DSO5OSSGPHY) H 4 1 Q3 Q