LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 LM95010 Digital Temperature Sensor with SensorPathTM Bus Check for Samples: LM95010 FEATURES 1 * 23 * * SensorPath Bus - 4 Hardware Programmable Addresses Temperature Sensing - 0.25 C Resolution - 127.75 C Maximum Temperature Reading 8-Lead VSSOP Package APPLICATIONS * * Microprocessor Based Equipment - (Motherboards, Base-stations, Routers, ATMs, Point of Sale, ...) Power Supplies KEY SPECIFICATIONS * * * Temperature Sensor Accuracy 2C (max) Temperature Range -20 to +125C Power Supply Voltage +3.0 to +3.6 V * * Power Supply Current 0.5 mA (typ) Conversion Time 14 to 1456 ms DESCRIPTION The LM95010 is a digital output temperature sensor that has single-wire interface compatible with the SensorPath interface. It uses a Vbe analog temperature sensing technique that generates a differential voltage that is proportional to temperature. This voltage is digitized using a Sigma-Delta analogto-digital converter. The LM95010 is part of a hardware monitor system, comprised of two parts: the PC System Health Controller (Master), such as a Super I/O, and up to seven slaves of which four can be LM95010s. Using SensorPath, the LM95010 will be controlled by the master and report to the master its own die temperature. SensorPath data is pulse width encoded, thereby allowing the LM95010 to be easily connected to many general purpose microcontrollers. Block Diagram LM95010 ADDRESS POINTER REGISTER SensorPath BUS SWD MANUFACTURER ID REGISTER DEVICE NUMBER ADD0 ADD1 V+ (Power) REVISION AND DEVICE ID REGISTER +3.3V_SBY DEVICE CONTROL REGISTER GND CAPABILITIES FIXED REGISTER DEVICE STATUS REGISTER TEMPERATURE CONTROL REGISTER TEMPERATURE CAPABILITIES REGISTER TEMPERATURE DATA READOUT REGISTER THERMAL DIODE SIGNAL CONDITIONING 6' ADC CONVERSION RATE REGISTER BANDGAP REFERENCE 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SensorPath is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2013, Texas Instruments Incorporated LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 www.ti.com Connection Diagram V+/ 3.3V_SBY 1 NC 2 8 SWD 7 ADD1 LM95010 NC 3 6 ADD0 NC 4 5 GND Figure 1. 8-Lead VSSOP See DGK Package PIN DESCRIPTION Pin Number Pin Name Type Description Typical Connection 1 V+/3.3V SB Power Positive power supply pin +3.3V pin. Should be powered by +3.3V Standby power. This pin should be bypassed with a 0.1 F capacitor. A bulk capacitance of approximately 10 F needs to be in the near vicinity of the LM95010. Ground System ground 2-4 NC 5 GND Power Must be grounded. 6 ADD0 Input Address select input that assigns the serial bus device number 10k resistor to V+ or GND; must never be left floating 7 ADD1 Input Address select input that assigns the serial bus device number 10k resistor to V+ or GND; must never be left floating 8 SWD Input/ Output Single-wire Data, SensorPath serial interface line; Open-drain output Super I/O with 1.25k pull-up to 3.3V Typical Application +3.3V Standby R1** C1* 100 pF C2 0.1 PF 1 V+ 2 NC 3 NC 4 NC 8 SWD 7 ADD1 6 ADD0 5 GND SWD Super I/O LM95010 * Note, place close to LM30 pins. **Note, R1 may be required for lower power dissipation and depends on bus capacitance. Figure 2. LM95010 connection to SensorPath master such as a Super I/O. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) Supply Voltage (V+) -0.5 V to 6.0 V -0.3 V to (V+ + 0.3 V) Voltage on Pin 2 -0.5 V to 6.0 V Voltage on all other Pins Input Current per Pin (3) Package Input Current 5 mA (3) 30 mA (4) Package Power Dissipation Output Sink Current 10 mA -65 C to +150 C Storage Temperature ESD Susceptibility (5) Human Body Model 2000 V Machine Model 200 V Soldering Information, Lead Temperature VSSOP Package (1) (2) (3) (4) (5) (6) (6) Vapor Phase (60 seconds) 215 C Infrared (15 seconds) 220 C All voltages are measured with respect to GND, unless otherwise noted. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > V+), the current at that pin should be limited to 5 mA. Parasitic components and/or ESD protection circuitry are shown below for the LM95010's pins. The nominal breakdown voltage of D3 is 6.5 V. SNP stands for snap-back device. Devices that are connected to a particular pin are marked with a "" in Table 1. Thermal resistance junction-to-ambient when attached to a printed circuit board with 2 oz. foil is 210 C/W. Human body model, 100 pF discharged through a 1.5 k resistor. Machine model, 200 pF discharged directly into each pin. See Figure 3 for the ESD Protection Input Structure. See the URL "http://www.ti.com/packaging/" for other recommendations and methods of soldering surface mount devices. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 3 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 Operating Ratings www.ti.com (1) (2) TMIN TA TMAX Temperature Range for Electrical Characteristics -20 C TA +125 C LM95010CIMM -20 C TA +125 C Operating Temperature Range Supply Voltage Range (V+) (1) (2) +3.0 V to +3.6 V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND, unless otherwise noted. DC Electrical Characteristics The following specifications apply for V+ = 3.0 VDC to 3.6 VDC, unless otherwise specified in the conditions. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = +25 C. POWER SUPPLY CHARACTERISTICS Symbol V+ I+AVG I+Peak Parameter Conditions Typical Power Supply Voltage Average Power Supply Current Peak Power Supply Current (1) Limits (2) Units (Limit) 3.3 3.0 3.6 V (min) V (max) 750 A (max) 1.6 V (min) 2.8 V (max) 3 C (max) 2 C (max) SensorPath Bus Inactive (3) 500 SensorPath Bus Inactive (3) 1.6 Power-On Reset Threshold Voltage mA TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS TA = -20 C and +125 C Temperature Error +25 C TA +60 C (4) 1 (4) Temperature Resolution 10 Bits 0.25 C SWD and ADD DIGITAL INPUT CHARACTERISTICS VIH SWD Logical High Input Voltage VIL SWD Logical Low Input Voltage TA = 0 C to +85 C 2.1 V (min) V+ + 0.5 V (max) 0.8 V (max) -0.5 V (min) -0.3 V (min) VIH ADD Logical High Input Voltage 90% x V+ V (min) VIL ADD Logical Low Input Voltage 10% x V+ V (max) 10 A (max) VHYST IL CIN SWD Input Hysteresis 300 mV SWD and ADD Input Leakage Current GND VIN V+ 0.005 SWD Input Leakage Current with V+ Open or Grounded GND VIN 3.6 V, and V+ Open or GND 0.005 A 10 pF Digital Input Capacitance SWD DIGITAL OUTPUT CHARACTERISTICS VOL Open-drain Output Logic "Low" Voltage IOH Open-drain Output Off Current IOL = 4 mA 0.4 IOL = 50 A COUT (1) (2) (3) (4) 4 0.005 Digital Output Capacitance 10 V (max) 0.2 V (max) 10 A (max) pF "Typicals" are at TA = 25 C and represent most likely parametric norm. They are to be used as general reference values not for critical design calculations. Limits are specified to TI's AOQL (Average Outgoing Quality Level). The supply current will not increase substantially with SensorPath transactions. Temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power dissipation of the LM95010 and the thermal resistance. See Note 4 in Absolute Maximum Ratings table for thermal resistance to be used in the self-heating calculation. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 AC Electrical Characteristics The following specification apply for V+ = +3.0VDC to +3.6VDC, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25 C. The SensorPath Characteristics conform to the SensorPath specification. Please refer to that specification for further details. HARDWARE MONITOR CHARACTERISTICS Symbol Parameter tCONV Conditions Total Monitoring Cycle Time (3) Typical Default (1) 182 (2) Limits Units (Limits) 163.8 ms (min) 200.2 ms (max) Rpull-up= 1.25 k 30%, CL= 400 pF 300 ns (max) Rpull-up= 1.25 k30%, CL= 400 pF SensorPath Bus CHARACTERISTICS tf SWD fall time tr SWD rise time 1000 ns (max) Minimum inactive time (bus at high level) ensured by the LM95010 before an Attention Request 11 s (min) tMtr0 Master drive for Data Bit 0 write and for Data Bit 0-1 read 11.8 s (min) 17.0 s (max) Master drive for Data Bit 1 write 35.4 s (min) 48.9 s (max) tSFEdet Time allowed for LM95010 activity detection 9.6 s (max) tSLout1 LM95010 drive for Data Bit 1 read by master 28.3 s (min) 38.3 s (max) tMtrS Master drive for Start Bit tSLoutA tRST tRST_MAX (2) (3) (4) (5) (5) tINACT tMtr1 (1) (4) 80 s (min) 109 s (max) LM95010 drive for Attention Request 165 s (min) 228 s (max) Master or LM95010 drive for Reset 354 s (min) Maximum drive of SWD by an LM95010, after the power supply is raised above 3V 500 ms (max) "Typicals" are at TA = 25 C and represent most likely parametric norm. They are to be used as general reference values not for critical design calculations. Limits are specified to TI's AOQL (Average Outgoing Quality Level). This specification is provided only to indicate how often temperature data is updated once enabled. The output fall time is measured from VIH min to VIL max. The output fall time is ensured by design. The output rise time is measured from VIL max to VIH min. The output rise time is ensured by design. Table 1. Pin Name PIN # D1 D2 D3 D4 D5 R1 SNP ESD CLAMP V+/3.3V SB 1 NC 2 NC 3 NC 4 ADD0 6 ADD1 7 SWD 8 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 5 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 www.ti.com V+ D1 D3 D4 R1 I/O D2 SNP ESD Clamp D5 GND Devices that are connected to a particular pin are marked with a "" in the table above. Figure 3. ESD Protection Input Structure 0 Ps 50 Ps 100 Ps tINACT tMtr0 Master Write 0 **SlvDetectData1 tINACT tMtr1 Master Write 1 tINACT tMtr0 Mout_Mrd_0 **SlvDetect_st Sout_Mrd_0 tSFEdet Master Read 0 tINACT tMtr0 Mout_Mrd_1 **SlvDetect_st Sout_Mrd_1 tSFEdet **MstDetect_1 Master Read 1 DetctStart DetctStart tINACT DetctStart tMtrS Master Write Start See SensorPath BIT SIGNALING for further details. Figure 4. Timing for Data Bits 0, 1 and Start Bit 6 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 0 Ps 50 Ps 100 Ps 200 Ps 300 Ps 400 Ps Master Write 0 Master Write 1 Master Read 0 Master Read 1 tINACT tMtrS Master Write Start tINACT tMtr0 Mout_ Attention tINACT tSLoutA Sout_ Attention Attention Detect tINACT Attention tRST Mout_ Reset tRST Sout_R eset tRST Reset Detect Reset See SensorPath BIT SIGNALING for further details. Figure 5. Timing for Attention Request and Reset Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 7 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Conversion Rate Effect on Power Supply Current 2.00 POWER SUPPLY CURRENT (mA) 1.75 Peak Current 1.50 1.25 1.00 0.75 Average Current 0.50 0.25 0 10 ms 100 ms 1s 10s CONVERSION TIME Figure 6. FUNCTIONAL DESCRIPTION The LM95010 is based on a Vbe temperature sensing method. A differential voltage, representing temperature, is digitized using a Sigma-Delta analog to digital converter. The digital temperature data can be retrieved over a simple single-wire interface called SensorPath. SensorPath is optimized for hardware monitoring. TI offers a royalty-free license in connection with its intellectual property rights in the SensorPath bus. The LM95010 has 2 address pins that allow up to 4 LM95010s to be connected to one SensorPath bus. The physical interface of SensorPath's SWD signal is identical to the familiar industry standard SMBus SMBDAT signal. The digital information is encoded in the pulse width of the signal being transmitted. Every bit can be synchronized by the master simplifying the implementation of the master when implemented with a microcontroller. For microcontroller's with greater functionality an asynchronous attention signal can be transmitted by the LM95010 to interrupt the microcontroller and notify it that temperature data has been updated in the readout register. To optimize the LM95010's power consumption to the system requirements, the LM95010 has a shutdown mode as well as it supports multiple conversion rates. SensorPath BUS SWD SWD is the Single Wire Data line used for communication. SensorPath uses 3.3V single-ended signaling, with a pull-up resistor and open-drain low-side drive (see Figure 7). For timing purposes SensorPath is designed for capacitive loads (CL) of up to 400pF. Note that in many cases a 3.3V standby rail of the PC will be used as a power supply for both the sensor and the master. Logic high and low voltage levels for SWD are TTL compatible. The master may provide an internal pull-up resistor. In this case the external resistor is not needed. The minimum value of the pull-up resistor must take into account the maximum allowable output load current of 4mA. V+ RI 1.25k Option SWD V+ RE >1.25k Option LM95010 SWD CL <400pF Master Figure 7. SensorPath SWD simplified schematic SensorPath BIT SIGNALING Signals are transmitted over SensorPath using pulse-width encoding. There are five types of "bit signals": 8 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com * * * * * SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 Data Bit 0 Data Bit 1 Start Bit Attention Request Reset All the "bit signals" involve driving the bus to a low level. The duration of the low level differentiates between the different "bit-signals". Each "bit signal" has a fixed pulse width. SensorPath supports a Bus Reset Operation and Clock Training sequence that allows the slave device to synchronize its internal clock rate to the master. Since the LM95010 meets the 15% timing requirements of SensorPath, the LM95010 does not require the Clock Training sequence and does support this feature. This section defines the "bit signal" behavior in all the modes. Please refer to the timing diagrams in Electrical Characteristics (Figure 4 and Figure 5) while going through this section. Note that the timing diagrams for the different types of "bit signals" are shown together to better highlight the timing relationships between them. However, the different types of "bit signals" appear on SWD at different points in time. These timing diagrams show the signals as driven by the master and the LM95010 slave as well as the signal as seen when probing SWD. Signals labels that begin with the label Mout_ depict a drive by the master. Signals labels that begin with the label Slv_ depict the drive by the LM95010. All other signals show what would be seen when probing SWD for a particular function (e.g. "Master Wr 0" is the Master transmitting a Data Bit with the value of 0). Bus Inactive The bus is inactive when the SWD signal is high for a period of at least tINACT. The bus is inactive between each "bit signal". Data Bit 0 and 1 All Data Bit signal transfers are started by the master. A Data Bit 0 is indicated by a "short" pulse; a Data Bit 1 is indicated by a longer pulse. The direction of the bit is relative to the master, as follows: * Data Write - a Data Bit transferred from the master to the LM95010. * Data Read - a Data Bit transferred from the LM95010 to the master. A master must monitor the bus as inactive before starting a Data Bit (read or Write). A master initiates a data write by driving the bus active (low level) for the period that matches the data value (tMtr0 or tMtr1 for a write of "0" or "1", respectively). The LM95010 will detect that the SWD becomes active within a period of tSFEdet, and will start measuring the duration of that the SWD is active in order to detect the data value. A master initiates a data read by driving the bus for a period of tMtr0. The LM95010 will detect that the SWD have become active within a period of tSFEdet. For a data read of "0", the LM95010 will not drive the SWD. For a data read of "1" the LM95010 will start within tSFEdet to drive the SWD low for a period of tSLout1. Both master and LM95010 must monitor the time at which the bus becomes inactive to identify a data read of "0" or "1". During each Data Bit, both the master and all the LM95010s must monitor the bus (the master for Attention Request and Reset; at the LM95010s for Start Bit, Attention Request and Reset) by measuring the time SWD is active (low). If a Start Bit, Attention Requests or Reset "bit signal" is detected, the current "bit signal" is not treated as a Data Bit. Note that the bit rate of the protocol varies depending on the data transferred. Thus, the LM95010 has a value of "0" in reserved or unused register bits for bus bandwidth efficiency. Start Bit A master must monitor the bus as inactive before beginning a Start Bit. The master uses a Start Bit to indicate the beginning of a transfer. LM95010s will monitor for Start Bits all the time, to allow synchronization of transactions with the master. If a Start Bit occurs in the middle of a transaction, the LM95010 being addressed will abort the current transaction. In this case the transaction is not "completed" by the LM95010 (see SensorPath BUS TRANSACTIONS). During each Start Bit, both the master and all the LM95010s must monitor the bus for Attention Request and Reset, by measuring the time SWD is active (low). If an Attention Request or Reset condition is detected, the current "bit signal" is not treated as a Start Bit. The master may attempt to send the Start Bit at a later time. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 9 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 www.ti.com Attention Request The LM95010 may initiate an Attention Request when the SensorPath bus is inactive. Note that a Data Bit, or Start Bit, from the master may start simultaneously with an Attention Request from the LM95010. In addition, two LM95010s may start an Attention Request simultaneously. Due to its length, the Attention Request has priority over any other "bit signal", except Reset. Conflict with Data Bits and Start Bits are detected by all the devices, to allow the bits to be ignored and re-issued by their originator. The LM95010 will either check to see that the bus is inactive before starting an Attention Request, or start the Attention Request with the tSFEdet time interval after SWD becomes active. The LM95010 will drive the signal low for tSLoutA time. After this, both the master and the LM95010 must monitor the bus for a Reset Condition. If a Reset condition is detected, the current "bit signal" is not treated as an Attention Request. After Reset, an Attention Request can not be sent before the master has sent 14 Data Bits on the bus. See Attention Request Transaction for further details on Attention Request generation. Bus Reset The LM95010 issues a Reset at power up. The master must also generate a Bus Reset at power-up for at least the minimum reset time, it must not rely on the LM95010. SensorPath puts no limitation on the maximum reset time of the master. Following a Bus Reset, the LM95010 may generate an Attention Request only after the master has sent 14 Data Bits on the bus. See Attention Request Transaction for further details on Attention Request generation. SensorPath BUS TRANSACTIONS SensorPath is designed to work with a single master and up to seven slave devices. Each slave has a unique address. The LM95010's supports up to 4 device addresses that are selected by the state of the address pins ADD0 and ADD1. The Register Set of the LM95010 is defined in Register Set. Bus Reset Operation A Bus Reset Operation is global on the bus and affects only the communication interface of all the devices connected to it. The Bus Reset operation does not affect either the contents of the device registers, or device operation, to the extent defined in LM95010 Register Set, see Register Set. The Bus Reset operation is performed by generating a Reset signal on the bus. The master must apply Reset after power-up, and before it starts operation. The Reset signal end will be monitored by all the LM95010s on the bus. After the Reset Signal SensorPath BIT SIGNALING requires that the master send a sequence of 8 Data Bits with a value of "0", without a preceding Start Bit. This is required to enable slaves that "train" their clocks to the bit timing. The LM95010 does not require nor does it support clock training. Reset Signal 0 0 0 0 0 0 0 0 = Bit Controlled by Master = Bit Controlled by Slave Figure 8. Bus Reset Transaction 10 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 Read Transaction During a read transaction, the master reads data from a register at a specified address within a slave. A read transaction begins with a Start Bit and ends with an ACK bit, as shown in Figure 9. * Device Number This is the address of the LM95010 device accessed. Address "000" is a broadcast address and can be responded to by all the slave devices. The LM95010 ignores the broadcast address during a read transaction. * Internal Address The address of a register within the LM95010 that is read. * Read/Write (R/W) A "1" indicates a read transaction. * Data Bits During a read transaction the data bits are driven by the LM95010. Data is transferred serially with the most significant bit first. This allows throughput optimization based on the information that needs to be read. - The LM95010 supports 8-bit or 16-bit data fields, as described in Register Set. * Even Parity (EP) This bit is based on all preceding bits (device number, internal address, read/write and data bits) and the parity bit itself. The parity -number of 1's - of all the preceding bits and the parity bit must be even - i.e., the result must be 0. During a read transaction, the EP bit is sent by the LM95010 to the master to allow the master to check the received data before using it. * Acknowledge (ACK) During a read transaction the ACK bit is sent by the master indicating that the EP bit was received and was found to be correct, when compared to the data preceding it, and that no conflict was detected on the bus (excluding Attention Request - Attention Request Transaction). A read transfer is considered "complete" only when the ACK bit is received. A transaction that was not positively acknowledged is not considered "complete" by the LM95010 and following are performed: - The BER bit in the LM95010 Device Status register is set - The LM95010 generates an Attention Request before, or together with the Start Bit of the next transaction A transaction that was not positively acknowledged is also not considered "complete" by the master (i.e. internal operations related to the transaction are not performed). The transaction may be repeated by the master, after detecting the source of the Attention Request (the LM95010 that has a set BER bit in the Device Status register). Note that the SensorPath protocol neither forces, nor automates re-execution of the transaction by the master.The values of the ACK bit are: - 1: Data was received correctly - 0: An error was detected (no-acknowledge). MSB S Device # Internal Address R/W S=Start signal R/W= Read or Write bit EP = Parity bit ACK=Acknowledge bit LSB n Data Bits EP ACK = Bit Controlled by Master = Bit Controlled by Slave Figure 9. Read Transaction, master reads data from LM95010 Write Transaction In a write transaction, the master writes data to a register at a specified address in the LM95010. A write transaction begins with a Start Bit and ends with an ACK Data Bit, as show in Figure 10. * Device Number This is the address of the slave device accessed. Address "000" is a broadcast address and is responded to by all the slave devices. The LM95010 responds to broadcast messages to the Device Control Register. * Internal Address This is the register address in the LM95010 that will be written. * Read/Write (R/W) A "0" data bit directs a write transaction. * Data Bits This is the data written to the LM95010 register, are driven by the master. Data is transferred serially with the most significant bit first. The number of data bits may vary from one address to another, based on the size of the register in the LM95010. This allows throughput optimization based on the information that needs to be written. - The LM95010 supports 8-bit or 16-bit data fields, as described in Register Set. * Even Parity (EP) This data bit is based on all preceding bits (Device Number, Internal Address, Read/Write and Data bits) and the Even Parity bit itself. The parity (number of 1's) of all the preceding bits and the parity Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 11 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 * www.ti.com bit must be even - i.e. the result must be 0. During a write transaction, the EP bit is sent by the master to the LM95010 to allow the LM95010 to check the received data before using it. Acknowledge (ACK) During the write transaction the ACK bit is sent by the LM95010 indicating to the master that the EP was received and was found correct, and that no conflict was detected on the bus (excluding Attention Request - see Attention Request Transaction). A write transfer is considered "completed" only when the ACK bit is generated. A transaction that was not positively acknowledged is not considered complete by the LM95010 (i.e. internal operation related to the transaction are not performed) and the following are performed: - The BER bit in the LM95010 Device Status register is set; - The LM95010 generates an Attention Request before, or together with the Start Bit of the next transaction A transaction that was not positively acknowledged is also not considered "complete" by the master (i.e. internal operations related to the transaction are not performed). The transaction may be repeated by the master, after detecting the source of the Attention Request (the LM95010 that has a set BER bit in the Device Status register). Note that the SensorPath protocol neither forces, nor automates re-execution of the transaction by the master.The values of the ACK bit are: - 1: Data was received correctly; - 0: An error was detected (no-acknowledge). MSB S Device # Internal Address R/W S=Start signal R/W= Read or Write bit EP = Parity bit ACK=Acknowledge bit LSB EP n Data Bits ACK = Bit Controlled by Master = Bit Controlled by Slave Figure 10. Write Transaction, master write data to LM95010 Read and Write Transaction Exceptions This section describes master and LM95010 handling of special bus conditions, encountered during either Read or Write transactions. If an LM95010 receives a Start Bit in the middle of a transaction, it aborts the current transaction (the LM95010 does not "complete" the current transaction) and begins a new transaction. Although not recommend for SensorPath normal operation, this situation is legitimate, therefore it is not flagged as an error by the LM95010 and Attention Request is not generated in response to it. The master generating the Start Bit, is responsible for handling the not "complete" transaction at a "higher level". If LM95010 receives more than the expected number of data bits (defined by the size of the accessed register), it ignores the unnecessary bits. In this case, if both master and LM95010 identify correct EP and ACK bits they "complete" the transaction. However, in most cases, the additional data bits differ from the correct EP and ACK bits. In this case, both the master and the LM95010 do not "complete" the transaction. In addition, the LM95010 performs the following: * the BER bit in the LM95010 Device Status register is set * the LM95010 generates an Attention Request If the LM95010 receives less than the expected number of data bits (defined by the size of the accessed register), it waits indefinitely for the missing bits to be sent by the master. If then the master sends the missing bits, together with the correct EP/ACK bits, both master and LM95010 "complete" the transaction. However, if the master starts a new transaction generating a Start Bit, the LM95010 aborts the current transaction (the LM95010 does not "complete" the current transaction) and begins the new transaction. The master is not notified by the LM95010 of the incomplete transaction. Attention Request Transaction Attention Request is generated by the LM95010 when it needs the attention of the master. The master and all LM95010s must monitor the Attention Request to allow bit re-sending in case of simultaneous start with a Data Bit or Start Bit transfer. Refer to Attention Request of the data sheet. 12 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 The LM95010 will generate an Attention Request using the following rules: 1. A Function event that sets the Status Flag has occurred and Attention Request is enabled and 2. The "physical" condition for an Attention Request is met (i.e., the bus is inactive), and 3. At the first time 2 is met after 1 occurred, there has not been an Attention request on the bus since a read of the Device Status register, or since a Bus Reset. OR 1. A bus error event occurred, and 2. the "physical" condition for an Attention Request is met (i.e., the bus is inactive), and 3. At the first time 2. is met after 1 occurred, there has not been a Bus Reset. All devices (master or slave) must monitor the bus for an Attention Request signal. The following notes clarify the intended system operation that uses the Attention Request Indication. * Masters are expected to use the attention request as a trigger to read results from the LM95010. This is done in a sequence that covers all LM95010s. This sequence is referred to as "master sensor read sequence". * After an Attention Request is sent by an LM95010 until after the next read from the Device Status register the LM95010 does not send Attention Requests for a function event since it is ensured that the master will read the Status register as part of the master sensor read sequence. Note that the LM95010 will send an attention for BER, regardless of the Status register read, to help the master with any error recovery operations and prevent deadlocks. * A master must record the Attention Request event. It must then scan all slave devices in the system by reading their Device Status register and must handle any pending event in them before it may assume that there are no more events to handle. NOTE There is no indication of which slave has sent the request. The requirement that multiple requests are not sent allows the master to know within one scan of register reads that there are no more pending events. Fixed Number Setting The LM95010 device number is defined by strapping of the ADD0 and ADD1 pins. The LM95010 will wake (after Device Reset) with the Device Number field of the Device Number register set to the address as designated in DEVICE NUMBER (Addr 00o). It is the responsibility of the system designer to avoid having two devices with the same Device Number on the bus. Devices should be detected by the master by a read operation of the Device Number register. The read returns "000" if there is no device at that address on the bus (the EP bit must be ignored). Register Set REGISTER SET SUMMARY Reg Add Register Name R/ W P O R Val 000 000 Device Number R * 000 001 Manufacture r ID R 100B h 000 010 Device ID R 21h 000 011 Capabilities Fixed R 1h 000 100 Device Status R Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Not Available 0 0 0 1 0 Reserved 0 0 0 0 0 0 See Table 2 0 0 0 0 0 0 0 0 0 1 0 0 RevID 0 0h 0 0 1 1 0 0 1 Device ID 0 0 0 0 0 0 0 1 Reserved 0 Bit 0 LSb 0 0 0 0 Function 1 0 Not Available 0 0 0 0 0 0 0 1 BER 0 0 ERF 1 0 0 0 SF1 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 13 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 Reg Add Register Name R/ W 000 101 Device Control R/ W 001 000 Temperature R Capabilities 001 001 Temperature R Data Readout 001 010 Temperature R/ Control W 001 011 011 111 Reserved R 100 000 Conversion Rate R/ W 100 001 111 111 Undefined Registers R P O R Val www.ti.com Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 0 0 0 0 0 0h Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reserved 014A h 0 0 Reserved 0 0 0 0 Int Rout Sign Sen Size s 0 0 0 0 0 0 0 1 0 1 MSb Sign 64 C 32 C 16 C 8C 4C 2C 1C 0.5 C LSb 0.25 C 0 0 0 0 0 0 0h EnF 1 Res 0 Low Shut Pwr dow n 10Bits 0 0 0 0 Res et 0.25C Resolution 1 0 1 0 0 0 EN0 ATE Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0 Bit 0 LSb Undefined 2h Not Available 0 Conversion Rate Undefined * Depends on state of ADD pins see Table 2. Device Reset Operation A Device Reset operation is performed in the following conditions: * At device power-up. * When the Reset bit in the Device Control register is set to 1 (see DEVICE CONTROL (Addr 05o)). The Device Reset operation performs the following: * Aborts any device operation in progress and restarts device operation. * Sets all device registers to their "Reset" (default) value. DEVICE NUMBER (Addr 00o) This register is used to specify a unique address for each device on the bus. Reg Add Register Name R/ W 000 000 Device Number R P O R Val 4h-1h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Reserved 0 0 0 0 Bit 2 Bit 1 Bit 0 LSb AS2 AS1 AS0 0 The value of AS2:AS0 is determined by the setting of the ADD0 and ADD1 input pins: Table 2. Device Number Assignment 14 [ADD1:ADD0] [AS2:AS0] 00 001 01 010 10 011 11 100 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 The value of AS2:AS0 will directly change and follow the value determined by ADD1:ADD0. Since this is a read only register the value of the address cannot be changed by software. MANUFACTURER ID (Addr 01o) Reg Add Register Name R/ W 000 001 Manufacture r ID R P O R Val Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 0 0 0 1 0 0 100B h Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 0 0 1 0 Bit 0 LSb 1 1 The manufacturer ID matches that assigned by the PCI SIG. This register may be used to identify the manufacturer of the device in order to perform manufacturer specific operations. DEVICE ID (Addr 02o) Reg Add Register Name R/ W P O R Val 000 010 Device ID R 21h Bit 15 MSb Bit 14 0 0 Bit 13 Bit 12 Bit 11 Bit 10 0 0 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RevID 0 Bit 0 LSb DeviceID 0 0 0 0 1 0 0 0 0 1 The device ID is defined by the manufacturer of the device and is unique for each device produced by a manufacturer. Bits 15-11 identify the revision number of die and will be incremented upon revision of the device. Bit Type 10-0 RO Description DeviceID (Device ID Value) A fixed value that identifies the device. 15-11 RO RevID (Revision ID Value) A fixed value that identifies the device revision. CAPABILITIES FIXED (Addr 03o) Reg Add Register Name R/ W P O R Val 000 011 Capabilities Fixed R 1h Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 0 0 0 0 0 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reserved 0 0 Bit 0 LSb FuncDescriptor1 0 0 0 0 0 0 0 0 1 The value of this register defines the capabilities of the LM95010. The LM95010 supports only one function, that of Temperature Measurement type. Please refer to SensorPath BIT SIGNALING for further details on other FuncDescriptor values. DEVICE STATUS (Addr 04o) This register is set to the reset value by a Device Reset. Reg Add Register Name R/ W P O R Val Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb 000 100 Device Status R 0h BER 0 0 ERF1 0 0 0 SF1 Bit Type Description 0 RO SF1 (Status Function 1). This bit is set by a Function Event within Function 1. Event details are function dependent and are described within the function. SF1 is cleared by Device Reset or by handling the event within the function (seeTEMPERATURE MEASUREMENT FUNCTION (TYPE - 0001) for further details). 0: Status flag for Function 1 is inactive (no event). 1: Status flag for Function 1 is active indicating that a Function Event has occurred. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 15 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 www.ti.com Bit Type 3-1 RO Not supported. Will always read "0". Description 4 RO ERF1 (Error Function 1) This bit is set in response to an error indication within Function 1. ERF1 is cleared by Device Reset or by handling the error condition within the function (see TEMPERATURE MEASUREMENT FUNCTION (TYPE - 0001) for further details). 0: No error occurred in Function 1. 1: Error occurred in Function 1. 6-5 RO Not supported. Will always read "0". 7 RO BER (Bus Error). This bit is set when the device either generates, or receives an error indication in the ACK bit of the transaction (i.e., no-acknowledge). BER is cleared by Device Reset or by reading the Device Status register. 0: No transaction error occurred. 1: An ACK bit error (no-acknowledge) occurred during the last transaction. DEVICE CONTROL (Addr 05o) This register responds to a broadcast write command (DeviceNumber 000). Write using broadcast address is ignored by bits 15-2. This register is set to the reset value by a Device Reset. P O R Val Bit 15 MSb Reg Add Register Name R/ W 000 101 Device Control R/ W Bit Type 0 R/W Reset (Device Reset). When set to "1" this bit initiates a Device Reset operation ( See Device Reset Operation). This bit self-clears after the Device Reset operation is completed. 0: Normal device operation. (default) 1: Device Reset The LM95010 does not require a Device Reset command after power. 1 R/W Shutdown (Shutdown Mode). When set to "1" this bit stops the operation of all functions and places the device in the lowest power consumption mode. 0: Device in Active Mode. (default) 1: Device in Shutdown Mode. 2 R/W LowPwr (Low-Power Mode). When set to "1" this bit slows the operation of all functions and places the device in a low power consumption mode. In Low-Power Mode, the conversion rate of the LM95010 is effected see CONVERSION RATE (Addr 40o) for further details. 0: Device in Active Mode. (default) 1: Device in Low-Power Mode. 3 RO Not supported. Will always read "0". 4 R/W EnF1 (Enable Function 1). When bit is set to "1" this bit Function 1 is enabled for operation. A function may require setup before this bit is set. The function registers can be accessed even when the function is disabled. 0: Function 1 is disabled. (default) 1: Function is enabled. 15-5 RO Not supported. Will always read "0". 16 Bit 14 Bit 13 Bit 12 Bit 11 0h Bit 10 Bit9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reserved 0 0 0 0 0 0 0 0 0 0 0 EnF 1 Res Bit 0 LSb Low Shut Pwr dow n Re set Description Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 TEMPERATURE MEASUREMENT FUNCTION (TYPE - 0001) This section defines the register structure and operation of a Temperature Measurement function as it applies to the LM95010. The FuncDescriptor value of this function is `0001'. Operation The Temperature Measurement function as implemented in the LM95010 supports one temperature zone, the LM95010's internal temperature (LM95010's junction temperature). Since the LM95010 only supports one temperature measurement the Sensor Scan function as defined in SensorPath BIT SIGNALING only applies to one temperature sensor. A temperature scan is enabled by the SensorEnable bit (EN0). The minimum scan rate is recommended to be 4Hz (i.e. the measurement data is updated at least once in 250 ms), see CONVERSION RATE (Addr 40o) for further details. In Low-Power Mode, the scan rate is four time lower than the scan rate in Active Mode. The scan rate effects the bus bandwidth required to read the results. The sampling rate of the temperature measurements can also be controlled via the Conversion Rate register, see CONVERSION RATE (Addr 40o) for further details. Data Readout When a new result is stored in the Readout register a Function Event is generated. Reading the Readout register clears the Status Function 1 flag (SF1). The result is available in the Readout register waiting for the master to read it during the master sensor read sequence. If a new result is ready before the previous result has been read, the new result overwrites the previous result and the Error Function 1 flag (ERF1) is set (indicating an overrun event). Reading the Readout register clears also the Error Function 1 flag (ERF1). The Readout register contains the temperature data, and the sensor number. Since the LM95010 only supports one temperature zone the sensor number field will always report zero. Other fields in the Readout register as defined by the SensorPath BIT SIGNALING are not supported. Readout Resolution The resolution of the readout is defined in the Temperature Capabilities register. The resolution of the LM95010 is fixed and cannot be modified by software. Function Event The Temperature Measurement function generates a Function Event whenever a temperature conversion cycle is completed and new data is stored in the Readout Register. When the new data is stored into the Readout register the SF1 bit in the device Status register is set to "1" and remains set, until it is cleared by reading the Readout register. An Attention Request is generated on the bus, only if it is enabled by the Attention Enable bit (ATE) in the Temperature Control register. Setup Before Enabling enabled. No setup is required for the Temperature Measurement function before the function is Temperature Capabilities (Addr 10o) Reg Add Register Name R/ W 001 000 Temperature R Capabilities P O R Val Bit 15 MSb Bit 14 Bit 13 014A h Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reserved 0 0 0 0 Int Rout Sign Sen Size s 0 0 0 1 0 1 10Bits 0 0 Bit 0 LSb 0.25C Resolution 1 0 1 0 This register defines the format of the temperature data in the readout register. The LM95010 only supports one format as defined by the values of this register. Bit Type Description 2-0 R Resolution. This field defines the value of 1 LSb of the Temperature Readout field in the Readout Register. The SensorPath specification defines many different weights for the temperature LSb. The LM95010 supports a resolution of 0.25 C and thus a value of 010 for this field. For a full definition of this field please refer to the SensorPath specification. 5-3 R Number of Bits. This field defines the total number of significant bits of the Temperature Readout field in the Readout register. The total number of osignificant bits includes the number of bits representing the interger part of the temperature data and the fractional part of it, as defined by the Resolution field. The LM95010 supports 10 bits and thus a value of 001 for this field. For a full definition of this field please refer to the SensorPath specification. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 17 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 www.ti.com Bit Type 6 R Sign (Signed Data). Defines the type of data in the Temperature Readout field of the Readout register. 0: Unsigned, positive fixed point value. 1: Signed, 2's complement fixed point value. (value for the LM95010) Description 7 R RoutSize (Readout Register size). Defines the total size of the Readout register. 0: 16 bits. (LM95010 default) 1: 24 bits. 8 R/W IntSens (Internal Sensor Support). Indicates if the device supports internal temperature measurements, as the LM95010 does. 0: No internal temperature measurement 1: Internal temperature sensor implemented. (value for the LM95010) 15-9 RO Reserved. Will always read "0". Temperature Data Readout (Addr 11o) Reg Add Register Name R/ W 001 001 Temperature R Data Readout P O R Val Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 MSb Sign 64 C 32 C 16 C 8C 4C 2C 1C 0.5 C LSb 0.25 C Bit 0 LSb Reserved 0 0 0 0 0 0 The LM95010's temperature data format is two's complement and has 10-bits of resolution with the LSb having a weight of 0.25 C. The LM95010 can resolve temperature between +127.75 C and -128 C, inclusive. It can measure temperatures between +127.75 C and -20 C with an accuracy of 3.0 C. Table 3. Temperature Data Format Decimal Binary Hex +127.75 C 01 1111 1111 1FFh +100.00 C 01 1001 0000 190h +1.00 C 00 0000 0100 004h +0.25 C 00 0000 0001 001h 0 C 00 0000 0000 000h -0.25 C 11 1111 1111 3FFh -1.00 C 11 1111 1100 3FCh -20.00 C 11 1011 0000 3 B0h -39.75 C 11 0110 0001 361h -40.00 C 11 0110 0000 360h -128.00 C 10 0000 0000 200h Temperature Control (Addr 12o) This register is set to the reset value by a Device Reset. Reg Add 001 010 18 Register Name R/ W Temperature R/ Control W P O R Val Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 0h 0 0 0 0 0 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reserved 0 EN0 0 Submit Documentation Feedback 0 0 0 0 0 Bit 0 LSb ATE 0 Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 Bit Type 0 R ATE (Attention Enable). When set, this bit enables an Attention Request signal to generated by the LM95010, if the EN0 bit is set. 0: Attention Request disabled (from enabled Temperature Sensor- default) 1: Attention Request enabled Description 1 R EN0 (Enable Sensor). When this bit is set, the Temperature Sensor is enabled for temperature measurements. 0: Temperature Sensor disabled (default) 1: Temperature Sensor enabled 15-2 R Reserved. Will allways read "0". CONVERSION RATE (Addr 40o) Reg Add Register Name 100 000 Conversion Rate R/ W R/ W P O R Val Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 2h 0 0 0 0 0 0 Bit 1 Bit 0 LSb Conversion Rate LowPwr Conversion Rate[1:0] Typical Conversion Rate (ms) 0 00 14 1 00 91 0 01 91 1 01 364 0 10 182 (default) 1 10 728 0 11 364 1 11 1456 The temperature conversion rate is controlled by this register as well as the Low Power Bit of Device Control Register. This register is not defined by the SensorPath specification. Therefore, it must be accessed during BIOS run time. The conversion rate is dependent on system physical requirements and limitations. The thermal response time of the VSSOP package is one such requirement. Applications Information MOUNTING CONSIDERATIONS The LM95010 can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued or cemented to a surface. The temperature that the LM95010 is reading will typically be within +0.2 C of the surface temperature to which the LM95010's leads are attached to. This presumes that the ambient air temperature is almost the same as the surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature measured would be at an intermediate temperature between the surface temperature and the air temperature. Alternatively, the LM95010 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LM95010 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often used to ensure that moisture cannot corrode the LM95010 or its connections. The thermal resistance junction to ambient (JA) is the parameter used to calculate the rise of a device junction temperature due to its power dissipation. For the LM95010 the equation used to calculate the rise in the die temperature is as follows: TJ = TA + JA x [(V+ x IQ) + (VOL x IOL)] where * IQ is the quiescent current (500 A typ.) Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 19 LM95010 SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 * * www.ti.com VOL is the logic "Low" output level of SWD IOL is the load current on SWD (1) Since the LM95010's junction temperature is the actual temperature being measured care should be taken to minimize the load current that the LM95010 is require to drive. When mounted to a PCB, with 2 oz. copper foil, the LM95010's thermal resistance is typically 210 C/W. 20 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 LM95010 www.ti.com SNIS133D - SEPTEMBER 2003 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM95010 21 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) LM95010CIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -20 to 125 T19C LM95010CIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 125 T19C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM95010CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM95010CIMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM95010CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM95010CIMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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