AmC010CFLKA150 - Advanced Micro Devices

FINAL

Publication# 18723 Rev: CAmendment/+1

Issue Date: May 1998

AmC0XXCFLKA

1, 2, 4, or 10 Megabyte 5.0 V-only Flash Memory PC Card

DISTINCTIVE CHARACTERISTICS

■High performance

— 150 ns maximum access time

■Single supply operation

— Write and eras e voltage, 5.0 V ±5%

— Read voltage, 5.0 V ±5%

■CMOS low po wer consumption

— 45 mA maximum active read current (x8 mode)

— 65 mA maximum active erase/write current

(x8 mode)

■High write endurance

— Minimum 100,000 erase/write cycles

■PCMCIA/JEIDA 68-pin standard

— Selectable byte- or word-wide configuration

■Write prot ect switch

— Prevents accidental data loss

■Zero data retention power

— Batteries not required for data storage

■Separate attribute memory

— 512 byte EEPROM

■Au tomated write and erase operations increase

system write performance

— 64K byte memory sectors for faster automated

erase speed

— Typically 1.5 seconds per single memory sector

erase

— Random address writes to previously erased

bytes (16 µs typical per byte)

■Total system integration solution

— Support from independent software and

hardware vendors

■Low insertion and removal force

— State-of-the-art connector allows for minimum

card insertion and removal eff ort

■Sector erase suspend/resume

— Suspend the erase operation to allow a read

operation in another sector within the same

device

GENERAL DESCRIPTION

AMD’s 5.0 V-only Flash Memory PC Card provides the

highest system lev el perf ormance for data and file stor-

age solutions to the portable PC market segment. Man-

ufactured with AM D’s Negative Gat e Erase, 5.0 V-only

technology, the AMD 5.0 V-only Flash Memor y Cards

are the most cost-effective and reliable approach to

single-supply Flash memor y cards. Data files and ap-

plication programs can be stored on the “C” series

cards. This allows OEM manufacturers of portable sys-

tems to eli minate the weight, high power co nsumption

and rel iabil ity issue s ass oci ated w ith el ectro mec hanic al

disk-based systems. The “C” series cards also allow to-

day’s bulky and heavy batter y packs to be reduced in

weight and size. Typically only two “AA” alkaline batter-

ies are required for total system operation. AMD’s

Flash Memory PC Cards provide the most efficient

method to transfer useful work between different hard-

ware platforms. The enabling technology of the “C” se-

ries cards enhances the productivity of mobile workers.

Widespread acceptance of the “C” series cards is as-

sured due to their compatibility with the 68-pin PCM-

CIA/JEIDA international standard. AMD’s Flash

Memory Cards can be read in either a byte-wide or

word-wide mode which allows for flexible integration

into various system platforms. Compatibility is assured

at the hardware interface and software interchange

specification. The Card Information Structure (CIS) or

Metaformat, can be written by the OEM at the memory

card’s attribute memory address space beginning at

address 00000H by using a for m at utility. The CIS ap-

pears a t the beginning of the Card’s att ribute memor y

space and defines the low-le vel organization of data on

the PC Card. The “C” series cards contains a separate

512 byte EEPROM memory for the cards’ attribute

memor y space. This allows all of the Flash memory to

be used for the common memory space.

Third party software solutions such as Microsoft’s

Flash File System (FFS), M-System’s True FFS, and

SCM’s SCM-FFS, enable AMD’s Flash Memory PC

Card to replicate the function of traditional disk-based

memory systems.

2 AmC0XXCFLKA 5/4/98

BLOCK DIAGRAM

Notes:

R = 20 K(min)/140 K

Ω

(max)

*1 Mbyte card = S0 + S1, *2 Mbyte card = S0…S3, *4 Mbyte card = S0…S7, *10 Mbyte card = S0…S19

Address

Buffers

and

Decoders

I/O

Transceivers

and

Buffers WP

(Note 1)

A0–A8 D0–D7

Attribute Memo ry

Write Protect

Switch

VCC

A0–A18

CEH0–

CEH9

CEL0–

CEL9

D0–D15

D8–D15

D0–D7

A1–A23*

CE2

CE1

A1–A9

CE2

CE1

REG

CD1

CD2

Card Detect

BVD1

BVD2

VCC

Battery Voltage

Detect

GND

VCC

10K

VCC

Decoder

VCC

Am29F040

A0–A18 D0–D7

VSS VCC

S0*

Am29F040

A0–A18 D8–D15

VSS VCC

S1*

A0–A18 D0–D7

VSS VCC

S2*

A0–A18 D8–D15

VSS VCC

S3*

A0–A18 D0–D7

VSS VCC

S18*

A0–A18 D8–D15

VSS VCC

S19*

18723C-1

5/4/98 AmC0XXCFLKA 3

PC CARD PIN ASSIGNMENTS

Notes:

I = Input to card, O = Output from card

I/O = Bidirectional

NC = No connect

In systems which switch V

individually to cards, no signal should be directly connected between cards other than ground.

1. V

not required for P rogramming or Reading operations.

2. BVD = Internally pulled-up.

3. Signal must not be connected between cards.

4. Highest address bit for 1 Mbyte car d.

5. Highest address bit for 2 Mbyte car d.

6. Highest address bit for 4 Mbyte car d.

7. Highest addre s s bit for 10 Mbyte card.

Pin# 3 3 Function Pin# Signal I/O Function

1 GND Ground 35 GND Ground

2 D3 I/O Data Bit 3 36 CD1 O Card Detect 1 (Note 3)

3 D4 I/O Data Bit 4 37 D11 I/O Data Bit 11

4 D5 I/O Data Bit 5 38 D12 I/O Data Bit 12

5 D6 I/O Data Bit 6 39 D13 I/O Data Bit 13

6 D7 I/O Data Bit 7 40 D14 I/O Data Bit 14

7CE

1 I Card Enable 1 (Note 3) 41 D15 I/O Data Bit 15

8 A10 I Addre ss Bit 10 42 CE2 I Card Enable 2 (Note 3)

9OEI Output Enable 43 NC No Connect

10 A11 I Address Bit 11 44 NC No Connect

11 A9 I Address Bit 9 45 NC No Connect

12 A8 I Address Bit 8 46 A17 I Address Bit 17

13 A13 I Address Bit 13 47 A18 I Address Bit 18

14 A14 I Address Bit 14 48 A19 I Address Bit 19 (Note 4)

15 WE I Write Enable 49 A20 I Address Bit 20 (Note 5)

16 NC No Connect 50 A21 I Add ress Bit 21 (N ote 6)

17 VCC1 Power Supply 51 VCC2 Power Supply

18 NC No Connect (Note 1) 52 NC No Connect (Note 1)

19 A16 I Address Bit 16 53 A22 I Address Bit 22

20 A15 I Address Bit 15 54 A23 I Address Bit 23 (Note 7)

21 A12 I Address Bit 12 55 NC No Connect

22 A7 I Address Bit 7 56 NC No Connect

23 A6 I Address Bit 6 57 NC No Connect

24 A5 I Address Bit 5 58 NC No Connect

25 A4 I Address Bit 4 59 NC No Connect

26 A3 I Address Bit 3 60 NC No Connect

27 A2 I Address Bit 2 61 REG I Register Select

28 A1 I Address Bit 1 62 BVD2 O Battery Voltage Dete ct 2 (Note 2)

29 A0 I Address Bit 0 63 BVD1 O Battery Voltage Dete ct 1 (Note 2)

30 D0 I/O Data Bit 0 64 D8 I/O Data Bit 8

31 D1 I/O Data Bit 1 65 D9 I/O Data Bit 9

32 D2 I/O Data Bit 2 66 D10 I/O Data Bit 10

33 WP O Write Protect (Note 3) 67 CD2 O Card Detect 2 (Note 3)

34 GND Ground 68 GND Ground

4 AmC0XXCFLKA 5/4/98

ORDERING INFORMATION

Standard Products

AMD stan dard products are av ailab le in s ev eral pac kages a nd operati ng ranges . The orde r number (Valid Combinatio n) is f ormed

by a combination of:

SPEED OPTION

-150 ns

OUTPUT CONFIGURATION:

(x16/x8)

FLASH TECHNOLOGY

PC MEMORY CARD

MEMORY CARD DENSITY

001 = One Megabyte

002 = Two Megabyte

004 = Four Megabyte

010 = Ten Megabyte

AMD

REVISION LEVEL

SERIES

AM C 0XX C FL KAxxx

5/4/98 AmC0XXCFLKA 5

PIN DESCRIPTION

A0–A23

Address Inputs

These inputs are internally latched during write cycles.

BVD1, BVD2

Battery Voltage Detect

Internally pulled-up.

CD1, CD2

Card Detect

When card detect 1 and 2 = ground the system detects

the card.

CE1, CE2

Card Enable

This input is active low . The memory card is deselected

and power consumption is reduced to standby levels

when CE is high. CE activates the internal memory

card circuitry that controls the high and low byte control

logic of the card, input buffers segment decoders, and

associated memory devices.

D0–D15

Data Input/Output

Data inputs are internally latched on write cycles. Data

outputs during read cycles. Data pins are active high.

When the memory card is deselected or the outputs

are disabled the outputs float to tristate.

GND

Ground

No Connect

Corr espondi ng pi n is not conn ecte d int ernally to t he d ie .

Output Enable

This input is active low and enables the data buffers

through the card outputs during read cycles.

REG

Attribute Memory Select

This input is active low and enables reading the CIS

from the EEPROM.

VCC

PC Card Power Supply

For de vice operation (5.0 V ± 5%) .

Write Enable

This input is active low and controls the write function

of the command register to the memory array. The

target address is latched on the falling edge of the WE

pulse and the appropr i ate data is latch ed on the r isin g

edge of the pulse.

Write Protect

This output is active high and disables all card write

operations.

MEMORY CARD OPERATIONS

The “C” ser ies Flash Memory Card is organized as an

array of individual devices. Each device is 5 12K by tes

in size with eight 64K byte sectors. Although the ad-

dress space is continuous each physical device defines

a logical address segment size.

Byte-wide erase operations could be performed in

four ways:

■In increments of the segment size

■In increments of the sectors in individual segments

■All eight sectors in parallel within individual

segments

■Selected sectors of the eight sectors in parallel

within individual segments

Multiple segments may be erased concurrently when

additional ICC current is supplied to the device. Once a

memor y se ctor or mem or y segm ent i s erased any ad-

dress loc ation may be programmed. Flash technology

allows any logical “1” data bit to be programmed to a

logical “0”. The only way to r eset b its to a l ogica l “1” is

to erase the entire memory sector of 64K bytes or

memory segment of 512K bytes.

Erase ope ra tions are th e only ope rations that wo rk on

entire m emory secto rs or m emor y s egmen ts. All ot her

operations such as word-wide programming are not af-

fected by the physical memory segments.

The common memory space data contents are altered

in a similar manner as writing to individual Flash mem-

ory devices. On-card address and data buffers activate

the appropriate Flash device in the memory array. Each

device internally latches address and data during write

cycles. Ref er to Table 1.

Attr ibute memory i s a separately ac c es sed car d m em-

or y space. The register memor y space is active when

the REG pin is driven low. The Card Information Struc-

ture (CIS) describes the capabilities and specification

of a card. The CIS is stored in the attribute memory

space beginning at address 00000H. The “C” series

cards contain a separate 512 byte EEPROM memor y

for the Card Information Structure. D0–D7 are active

duri ng attr ibute memory access es. D8–D15 s hould b e

ignored. Odd order bytes present invalid data. Refer to

Table 2.

6 AmC0XXCFLKA 5/4/98

Word-Wide Operations

The “C” series cards provide the flexibility to operate on

data in a byte-wide or word-wide format . In wor d-wide

operations the Low-bytes are controlled with CE1 when

A0 = 0. The High-bytes are controlled with CE2 with

A0 = don’t care.

Table 1. Common Memory Bus Operations

Legend:

X = Do n’t Care, where D on’ t Care i s eith er at V

or V

lev el. See DC Characteristics for voltage levels of normal TTL or CMOS

input levels.

Notes:

1. V

pins are not connected in the 5.0 V -Only Flash Memo ry Card.

2. Manu fac turer and device codes ma y be acces sed via a c ommand regi ster write s equence . (Ref er to A uto select C ommand in

Tables 3 and 4.)

3. Standby current is I

CCS

4. Refer to Tables 3 and 4 for valid D

during a byte write operation.

5. Refer to Table 5 for valid D

during a word write operation.

6. Byte access—Even. In this x8 mode, A0 = V

outputs or inputs the “even” byte (low byte) of the x16 word on D0–D7.

7. Byte acc ess—O dd . In thi s x8 mo de, A0 = V

outputs or inputs the “odd” byte (high byte) of the x16 word on D0–D7. This is

acco mplishe d internal to the card by transposing D8–D15 to D0–D7.

8. Odd byte only access. In this x8 mode, A0 = X outputs or inputs the “odd” byte (high byte) of the x16 word on D8–D15.

9. x16 word accesses present both “even” (low) and “odd” (high) bytes. A0 = X.

Pins/Operation REG CE2CE1OEWE A0 D8–D15 D0–D7

READ-ONLY

Read (x8) (Note 6) VIH VIH VIL VIL VIH VIL High-Z Data Out-Even

Read (x8) (Note 7) VIH VIH VIL VIL VIH VIH High-Z Data Out-Odd

Read (x8) (Note 8) VIH VIL VIH VIL VIH X Data Out-Odd High-Z

Read (x16) (Note 9) VIH VIL VIL VIL VIH X Data Out-Odd Data Out-Even

Output Disable VIH XXV

IH VIH X High-Z High-Z

Standby (Note 3) X VIH VIH X X X High-Z High-Z

READ/WRITE

Read (x8) (Notes 2, 6) VIH VIH VIL VIL VIH VIL High-Z Data Out-Even

Read (x8) (Notes 2, 7) VIH VIH VIL VIL VIH VIH High-Z Data Out-Odd

Read (x8) (Notes 2, 8) VIH VIL VIH VIL VIH X Data Out-Odd High-Z

Read (x16) (Notes 2, 9) VIH VIL VIL VIL VIH X Data Out-Odd Data Out-Even

Write (x8) (Notes 4, 6) VIH VIH VIL VIH VIL VIL High-Z Data In-Even

Write (x8) (Notes 4, 7) VIH VIH VIL VIH VIL VIH High-Z Data In-Odd

Write (x8) (Notes 4, 8) VIH VIL VIH VIH VIL X Data In-Odd High-Z

Write (x16) (Notes 5, 9) VIH VIL VIL VIH VIL X Data In-Odd Data In-Even

Output Disable VIH XXV

IH VIL X High-Z High-Z

Standby (Note 3) X VIH VIH X X X High-Z High-Z

Volt-only?

5/4/98 AmC0XXCFLKA 7

Table 2. Attribute Memory Bus Operations

Legend:

X = Don’t Care, where Don’t Care is either V

or V

levels. See DC Characteristics for voltage levels of normal TTL or CMOS

input levels.

Notes:

1. V

pins are not connected in the 5.0 V -Only Flash Memo ry Card.

2. In this x8 mode, A0 = V

outputs or inputs the “even” byte (low byte) of the x16 word on D0–D7.

3. Only even-byte data is valid during Attribute Memory Read function.

4. During Attribute Memory Read function, REG and OE must be active for the entire cycle.

5. During Attribute Memory Wr ite function, REG and WE must be act ive f or the ent ire cy c le , OE must be inactive for the entire

cycle.

6. Standby current is I

CCS

Pins/Operation REG CE2CE1OEWE A0 D8–D15 D0–D7

READ-ONLY

Read (x8) (Notes 2, 4) VIL VIH VIL VIL VIH VIL High-Z Data Out-Even

Read (x8) (Notes 3, 4) VIL VIH VIL VIL VIH VIH High-Z Not Valid

Read (x8) (Note 3) VIL VIL VIH VIL VIH X Not Valid High-Z

Read (x16) (Notes 3, 4, 5) VIL VIL VIL VIL VIH X Not Valid Data Out-Even

Output Disable VIL XXV

IH VIH X High-Z High-Z

Standby (Note 6) X VIH VIH X X X High-Z High-Z

READ/WRITE

Read (x8) (Notes 2, 4) VIL VIH VIL VIL VIH VIL High-Z Data Out-Even

Read (x8) (Notes 3, 4) VIL VIH VIL VIL VIH VIH High-Z Not Valid

Read (x8) (Note 4) VIL VIL VIH VIL VIH X Not Valid High-Z

Read (x16) (Note 4) VIL VIL VIL VIL VIH X Not Valid Data Out-Even

Write (x8) (Notes 2, 5) VIL VIH VIL VIH VIL VIL High-Z Data In-Even

Write (x8) (Note 5) VIL VIH VIL VIH VIL VIH High-Z High-Z

Write (x8) (Notes 4, 5) VIL VIL VIH VIH VIL X High-Z High-Z

Write (x16) (Note 5) VIL VIL VIL VIH VIL X High-Z Data In-Even

Output Disable VIL XXV

IH VIL X High-Z High-Z

Standby (Note 6) X VIH VIH X X X High-Z High-Z

Volt-only?

8 AmC0XXCFLKA 5/4/98

Byte-Wide Operations

Byte-wide data is available on D0–D7 for read and write

operations (CE1 = low, CE2 = high). Even and odd

bytes are stored in separate memory segments (i.e.,

S0 and S1) and are accessed when A0 is low and high

respectively. The even byte is the low order byte and

the odd byte is the high order byte of a 16-bit word.

Erase operat ions in the byte-wide mod e must account

f or data m ultiple xing on D0–D7 b y changing the state of

A0. Each memory sector or memory segment pair

must be addressed separately for erase operations.

Card Detection

Each CD (output) pin s hould be read by t he host sys-

tem to determine if the memory card is adequately

seated i n the socket. CD1 and CD2 are internally tied

to ground. If both bits are not detected, the system

should indicate that the card must be reinserted.

Write Protection

The AMD Flash me mor y card has three types of wr ite

protection. The PCMCIA/JEIDA socket itself provides

the first type of write protection. P ower supply and con-

trol pins have specific pin lengths in order to protect the

card with prope r power supply seque ncing in the c ase

of hot insertion and removal.

A mechanical write protect switch provides a second

type of wr ite protectio n. When this switch is activated,

WE is inter nally forced high. The Fla sh memory com-

mand register is disabled from accepting any write

commands.

The third type of write protection is achiev ed with VCC1

and VCC2 belo w V LKO. Each Flash memory device that

comprises a Flash memory segment will reset the com-

mand register to the read-only mode when VCC is

below VLKO. VLKO is the voltage below whic h wr ite op-

erations to individual command registers are disabled.

MEMORY CARD BUS OPERATIONS

Read En able

Two Card Enable (CE) p ins are available on th e mem-

ory card. Both CE pins must be active low for

word-wide read a cc ess es. O nly on e CE i s requir ed for

byte-wide accesses. The CE pins c ontrol th e s el ection

and gates power to the high and low memory seg-

ments. The Output Enable (OE) controls gating ac-

cessed data from the memory segment outputs.

The device will automatically power-up in the read/

reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read

cycles will retrieve array data. This default value en-

sures that no spurious alteration of the memory content

occurs during the power transition. Refer to the AC

Read Characteristics and Waveforms for the specific

timing parameters.

Output Disable

Data outputs from the card are disabled when OE is at

a logic-high level. Under this condition, outputs are in

the high-impedance state.

Stand by Operations

Byte-wide re ad acc esses o nly r equire ha lf of the read /

write output buffer (x16) to be active. I n addition, only

one memory segment is active within either the high

order or low order bank. Activation of the appropriate

half of the output buffer is controlled by the combination

of both CE pins. The CE pins also control power to the

high and low-order banks of memor y. Outputs of the

memor y bank not selected are placed in the high im-

pedance state. The individual memory segment is acti-

vated by the address decoders. The other memory

segments operate in standby. An active memory seg-

ment continues to draw power until completion of a

write or erase operation if the card is deselected in the

process of one of these operations.

Auto Select Operation

A host system or external card reader/writer can deter-

mine the on- card manufac turer and devi ce I.D. codes.

Codes ar e available after wr iti ng the 90H co mmand t o

the command register of a memory segment per

Tables 3 and 4. Reading from address location 00000H

in any segment provides the manufacturer I.D. while

address location 00002H provides the device I.D.

To ter m in ate th e Auto Sele ct o pera tio n, i t is ne ces s ary

to write the Read/Reset command sequence into the

Write Operations

Write and erase operations are valid only when VCC1

and VCC2 are above 4.75 V. This activates the state

machine of an addressed memory segment. The com-

mand register is a latch which saves address, com-

mands, and data information used by the state

machine and memory array.

When Writ e En able (WE) and appropriate CE(s) ar e at

a logic-level low, and Output Enable (OE) is at a

logic-high, the command register is enabled for write

operations. The falling edge of WE latches address in-

formation and the rising edge latches data/command

information.

Write or erase operations are performed by writing ap-

propriate data patterns to the command register of ac-

cessed Flash memory sectors or memory segments.

The byte-wide and word-wide commands are defined

in Tables 3, 4, and 5, respectively.

5/4/98 AmC0XXCFLKA 9

Table 3. Even Byte Command Definitions (Note 5)

*Address for Me mory Segment 0 (S0) only. Address f or the higher e v en memory segments (S2– S18) = (Addr) + (N/2)* 100000H

where N = Memory Segment number (0) for 1 Mbyte, N = (0, 2) for 2 Mbyte, N = (0, 2, 4, 6) for 4 Mbyte, N = (0…18) for 10 Mb yte.

Notes:

1. Address bit A16 = X = Don’t Care for all address commands e xcept for Program Address (PA), Read Address (RA) and Sector

Address (SA).

2. Bus operations are defined in Table 1.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment.

To select the memory segment:1 and 2 Mbyte: Use CE1 and A20

4 Mbyte: Use CE1 and A20, A21

10 Mbyte: Use CE1 and A20–A23.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE pulse.

5. A0 = 0 and CE1 = 0

Embedd ed

Command

Sequence

Bus

Write

Cyc l es

Req’d

First Bus

Write Cycle Second Bus

Write Cycle Third Bus

Write Cycle Fourth Bus

Read/Write Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data

Reset/Read 4 AAAAH AAH 5554H 55H AAAAH F0H RA RD

Autoselect 4 AAAAH AAH 5554H 55H AAAAH 90H 00H/02H 01H/A4H

Byte Write 4 AAAAH AAH 5554H 55H AAAAH A0H PA PD

Segment Er ase 6 AAAAH AAH 5554H 55H AAAAH 80H AAAAH AAH 5554H 55H AAAAH 10H

Sector Erase 6 AAAAH AAH 5554H 55H AAAAH 80H AAAAH AAH 5554H 55H SA 30H

Sector Erase Suspend Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)

Sector Erase Resume Erase can be resumed after suspend with Addr (don’t care), Data (30H)

10 AmC0XXCFLKA 5/4/98

Table 4. Odd Byte Command Definitions (Note 5)

*Address for Memory Segment 1 (S1) only. Address for the higher odd memory segments (S3–S19) = (Addr) + ((N–1)/2)*

100000H + 80000H where N = Memory Segment number (1) for 1 Mbyte, N = (1, 3) for 2 Mbyte, N = (1, 3, 5, 7) for 4 Mbyte,

N = (1…19) for 10 Mbyte.

Notes:

1. Address bit A16 = X = Don’t Care for all address commands e xcept for Program Address (PA), Read Address (RA) and Sector

Address (SA).

2. Bus operations are defined in Table 1.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment.

To select the memory segment:1 and 2 Mbyte: Use CE2 and A20

4 Mbyte: Use CE2 and A20, A21

10 Mbyte: Use CE2 and A20–A23.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE pulse.

5. A0 = 1 and CE1 = 0 or A0 = X and CE2 = 0.

Embedded

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle Second Bus

Write Cycle Third Bus

Write Cycle Fourth Bus

Read/Write Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data

Reset/Read 4 AAABH AAH 5555H 55H AAABH F0H RA RD

Autoselect 4 AAABH AAH 5555H 55H AAABH 90H 00H/02H 01H/A4H

Byte Write 4 AAABH AAH 5555H 55H AAABH A0H PA PD

Segment Er ase 6 AAABH AAH 5555H 55H AAABH 80H AAABH AAH 5555H 55H AAABH 10H

Sector Erase 6 AAABH AAH 5555H 55H AAABH 80H AAABH AAH 5555H 55H SA 30H

Sector Erase Suspend Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)

Sector Erase Resume Erase can be resumed after suspend with Addr (don’t care), Data (30H)

5/4/98 AmC0XXCFLKA 11

Table 5. Word Command Definitions (Note 7)

Notes:

1. Address bit A16 = X = Don’t Care for all address commands except for Program Address (PA) and Sector Address (SA).

2. Bus operations are defined in Table 1.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment.

To select the memory segment:1 and 2 Mbyte: Use CE1, CE2, A20

4 Mbyte: Use CE1, CE2, A20, A21

0 Mbyte: Use CE1, CE2, A20–A23.

4. RW = Data r ead from location RA during read operation. (Word Mode).

PW = Data to be programmed at location PA. Data is latched on the rising edge of WE. (Word Mode).

5. Address for Memory Segment Pair 0 (S0 and S1) only. Address for the higher Memory Segment Pairs (S2, S3 = Pair 1, S4,

S5 = Pair 2, S6, S7 = Pair 3…) is equal to (Addr) + M* (80000H) where M = Memory Segment Pair number.

6. Word = 2 bytes = odd byte and even byte.

7. CE1 = 0 and CE2 = 0.

Table 6. Memory Sector Address Table

for Memory Segment S0 FLASH MEMORY WRITE/ERASE

OPERATIONS

Details of AMD’s Embedded Write and

Erase Operations

Embedded Erase™ Algorithm

The automatic memory sector or memory segment

erase does not require the device to be entirely prepro-

gramming prior to executing the Embedded Erase

command. Upon executing the Embedded Erase com-

mand sequence, the addressed memory sector or

memory segment will automatically write and verify the

entire memory segment or memory sector for an all

“zero” data patter n. The s ystem is not requ ired to pro-

vide any controls or timing during these operations.

When the memory sector or memory segment is auto-

matically verified to contain an all “zero” pattern, a

self-timed chip erase-and-verify begins. The erase and

verify operations are complete when the data on D7 of

the memory sector or memory segment is “1” (see

“Write Operation Status” section) at which time the

Embedded

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle Second Bus

Write Cycle Third Bus

Write Cycle Fourth Bus

Read/Write Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data Addr* Data

Reset/Read 4 AAAAH AAAA 5554H 5555 AAAAH F0F0 RA RW

Autoselect 4 AAAAH AAAA 5554H 5555 AAAAH 9090 00H/02H 0101/

A4A4

Byte Write 4 AAAAH AAAA 5554H 5555 AAAAH A0A0 PA PW

Segment Er ase 6 AAAAH AAAA 5554H 5555 AAAAH 8080 AAAAH AAAA 5554H 5555 AAAAH 1010

Sector Erase 6 AAAAH AAAA 5554H 5555 AAAAH 8080 AAAAH AAAA 5554H 5555 SA 3030

Sector Erase Suspend Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)

Sector Erase Resume Erase can be resumed after suspend with Addr (don’t care), Data (30H)

Sector A19 A18 A17 Address Range

0 0 0 0 00000h-0FFFFh

1 0 0 1 10000h-1FFFFh

2 0 1 0 20000h-2FFFFh

3 0 1 1 30000h-3FFFFh

4 1 0 0 40000h-4FFFFh

5 1 0 1 50000h-5FFFFh

6 1 1 0 60000h-6FFFFh

7 1 1 1 70000h-7FFFFh

Note: A0 is not mapped inter nally.

12 AmC0XXCFLKA 5/4/98

device returns to the Read mode (D15 on the odd

byte). The system is not required to provide any control

or timing during these operations. A Reset command

after the device has begun execution will sto p the de-

vice but the data in the operated segment will be unde-

fined. In that case, restart the erase on that sector and

allow it to complete.

When using the Embedded Erase algorithm, the erase

automatically terminates when adequate erase margin

has been achiev ed for the memory array (no erase ver-

ify co mmand i s requ ired). The margin voltages are in-

ternally generated in the same manner as when the

standard erase verify command is used.

The Embedded Erase command sequence is a com-

mand only operation that stages the memory sector or

memory segment for automatic electrical erasure of all

bytes in the array. The automatic e rase begins on the

rising edge of the WE and terminates when the data on

D7 of the memory sector or memory segment is “1”

(see “Write Operation Status” section) at which time

the device returns to the R ead mo de. Please note that

f or the memory segment or memory sector erase oper-

ation, Data P olling may be performed at any address in

that segment or sector.

Figure 1 and Table 7 illustrate the Embedded Erase Al-

gorith m, a ty pical command st rin g and bus oper a ti on s .

As descr ibe d earlier, o nce the memor y sector in a de-

vice or memory segment completes the Embedded

Erase operation it returns to the Read mode and ad-

dresses are no longer latched. Therefore, the device

requires that a valid address input to the device is sup-

plied by the system at this particular instant of time.

Otherwise, the system will never read a “1” on D7. A

system designer has two choices to implement the Em-

bedded Erase algorithm:

1. The system (CPU) keeps the sector address (within

any of the sectors being erased) valid during the en-

tire Embedded Erase operation, or

2. Once the system executes the Embedded Erase

command sequence, the CPU takes away the ad-

dress from the device and becomes free to do other

tasks. In this case, the CPU is required to keep track

of the valid sector addr ess by loading it into a tem-

porary register. When the CPU comes back for per-

forming Data Polling, it should reassert the same

address.

Since the Embedded Erase operation takes a signifi-

cant amount of time (1.5–30 s), option 2 makes more

sense. However, the choice of these two options has

been left to the system designer.

Sector Erase

Sector erase is a six bus cycle operation. There are two

“unlock” write cycles. These are follow ed by writing the

“set-up” command. Two more “unlock” write cycles are

then followed by the sector erase command. The sector

address (any address location within the desired sec-

tor) is latched on the falling edge of WE, while the com-

mand (data) is latched on the rising edge of WE. A

time-out of 100 µs from the rising edge of the last sec-

tor erase command will initiate the sector erase

command(s).

Multiple sectors may be erased concurrently by writing

the six bus c ycle operation s as descr ibed above. This

sequence is followed with writes of the sector erase

command 30H to addresses in other sectors desired to

be concurr ently erased. A time-out of 100 µs from the

rising edge of the WE pulse for the last sector erase

command will initiate the sector erase. If another sector

erase command is written within the 100 µs time-out

window the timer is reset. Any command other than

sector erase within the time-out window will reset the

device to the read mode, ignoring the previous com-

mand string (refer to “Write Operation Status” section

for Sector Erase Timer operation ). Loading the sector

erase buffer may be done in any sequence and with

anysector number.

Sector erase does no t requi re the user to pr ogram the

device prior to erase. The device automatically pro-

grams all memory locations in the sector(s) to be

erased prior to electrical erase. When erasing a sector

Table 7. Embedded Erase Algorithm

Bus Opera tion Command Comments

Standby Wait for VCC ramp

Write Embedded Erase

command sequence 6 bus cycle

operation

Read Data Polling to

verify er asure

18723C-2

Figure 1. Embedded Erase Algorithm

Write Embedded Erase

Command Sequence

(Table 3 and 4)

Data Po ll from Device

(Figure 3)

Start

Erasure Complete

5/4/98 AmC0XXCFLKA 13

or sectors the remaining unselected sectors are not af-

fe cted. Th e system is no t required to provide any con-

trols or timings during these operations. A Reset

command after the device has begun execution will

stop the device but the data in the operated segment

will be undefined. In that case, restart the erase on that

sector and allow it to complete.

The automatic sector erase begins after the 100 µs

time out from the rising edge of the WE pulse for the

last sector erase command pulse and terminates when

the data on D7 is “1” (see “Write Operation Status” sec-

tion) at which time the device returns to read mode.

Data Polling must be performed at an address within

any of the sectors being erased.

Figure 1 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

Embedded Program™ Algorithm

The Embedd ed Pr ogram Setup is a four bus cycle op-

eration that stages the addressed memor y sector or

memory segment for automatic programming.

Once th e Embedded Pro gram Setup operation i s per-

f ormed, the next WE pulse causes a transition to an ac-

tive programming operation. Addresses are internally

latched on the falling edge of the WE pulse. Data is in-

ternally latched on the rising edge of the WE pulse . The

rising edge of WE also begins the programming opera-

tion. The system is not required to provide further con-

trol or timi ng. The device will automati cally provide an

adequate internally generated write pulse and verify

margin. The automatic programming operation is com-

pleted whe n th e da ta o n D7 of the a ddr es sed memory

sector or memory segment is equivalent to data written

to this bit (see Write Operation Status section) at which

time the device returns to the Read mode (no write ver-

ify command is required).

Addresses are latched on the falling edge of WE during

the Embedded Program command execution and

hence the system is not required to keep the addresses

stable dur ing the entire Programmin g operation. How-

ever, once the device completes the Embedded Pro-

gram operation, it returns to the Read mode and

addresses are no longer latched. Therefore, the device

requires that a valid address input to the device is sup-

plied by the system at this par ticular instant of time.

Otherwise, the system will never read a valid data on

D7. A system designer has two choices to implement

the Embedded Programming algorithm:

1. The system (CPU) keeps the address valid during

the entire Embedded Programming operation, or

2. Once the system ex ecutes the Embedded Program-

ming command sequence, the CPU takes away the

address from the device and becomes free to do

other tasks. In this case, the CPU is required to

keep track of the valid address by loading it into a

temporar y reg ister. When t he CPU come s back for

performing Data P olling, it should reassert the same

address.

Howe ver, since the Embedded Programming operation

takes only 16 µs typically, it may be easier f or the CPU

to keep the address stable during the entire Embedded

Programming operation instead of reasserting the valid

address during Data P oll ing. An yw ay, this has been lef t

to the sy stem desi gner’s choice to g o for either opera-

tion. Any commands written to the segment during this

period will be ignored.

Figure 2 and Table 8 illustrate the Embedded Program

Algorit hm, a typica l command string , and bus o perat ion.

Reset Command

The Reset command initializes the sector or segment

to the read mode. Please ref er to Tables 3 and 4, “Byte

Command Def initions,” and Table 5, “Word Comman d

Definitions” for the Reset command operation. The

sector or segment rema ins enabled for reads unti l the

command register contents are altered. There is a 6 µs

Write Recovery Time before Read for the first read

after a write.

The Reset command will safely reset the segment

memor y to the Read mode. Memor y contents are not

altered. F ollowing any other command, write the Reset

command once to the segment. This will safely abort

any operation and reset the device to the Read mode.

The Reset is needed to terminate the auto select oper-

ation. It can be used to terminate an Erase or Sector

Erase op eration, but the d ata in the s ec tor or seg men t

being erased would then be undefined.

Write Opera tion Stat us

Data Polling—D7 (D15 on Odd Byte)

The Flash Memory PC Card features Data Polling as a

method to indicate to the host system that the Embed-

ded algorithms are either in progress or completed.

While t he Embedd ed Programming algor ithm is i n op-

eration, an attemp t to r ead th e device will prod uce th e

complement of expected valid data on D7 of the ad-

dressed memory sector or memory segment. Upon

Table 8. Embedded Program Algorithm

Bus Operation Command Comments

Standby Wait for VCC ramp

Write Embedded Program

comma nd sequence 3 bus cycle

operation

Write Program

Address/Data 1 bus cycle

operation

Read Data Polling to

verify program

14 AmC0XXCFLKA 5/4/98

completion of the Embedded Program algorithm an at-

tempt to read the device will produce valid data on D7.

The Data P olling feature is valid after the rising edge of

the fourth WE pulse of the four write pulse sequence.

While the Embedded Erase algorithm is in operation,

D7 will rea d “ 0” un til the erase operatio n i s completed .

Upon completion of the erase operation, the data on D7

will re ad “1”.

The Data Po lling feature is only active during the Em-

bedded Programming or Erase algorithms. Please note

that the AmC0XXCFLKA data pin (D7) may change

asynch ronously while Ou tput Enable (OE) is asser ted

low. Thi s means that the device is dr iving st atus infor -

mation on D7 at one instant of time and then the byte’s

valid data at the next instant of time. Depending on

when the system samples the D7 output, it may read ei-

ther the status or valid data. Even if the device has

completed the Embedded operation and D7 has a valid

data, the data outputs on D0–D6 may be still invalid

since the switching time for data bits (D0–D7) will not

be the same. This happens since the internal delay

paths for data bits (D0–D7) within the device are differ-

ent. The valid data wi ll be provid ed on ly afte r a ce rtain

time delay (<tOE). Please refer to Figure 4a for detailed

timing diagrams.

See Figures 3 and 5 for the Data Polling timing

specifications and diagrams.

Toggle Bit—D6 (D14 on Odd Byte)

The Flash Memory PC Card also features a “Toggle Bit”

as a method to indicate to the host system that the Em-

bedded algorithms are either in progress or have been

completed.

While t he E mbedd ed Pr ogram o r Eras e al gor i thm is i n

progress, successive attempts to read data from the

device will result in D6 toggling between one and zero.

Once the Embedded Program or Erase algorithm is

completed, D6 will stop toggling and valid data on

D0–D7 will be read on the next successive read at-

tempt. The Toggle bit is also used for entering Erase

Suspend mode. Please refer to the section entitled

“Sector Erase Suspend.”

Please n ote th at even if the device compl etes the Em-

bedded algorithm operation and D6 stops toggling,

data bits D0–D7 (including D6) may not be valid during

the current bus cycle. This may happen since the inter-

nal circ uitr y may be sw itchin g fro m statu s mode t o the

Read mode. There i s a tim e del ay associa ted wi th th is

mode switching. Since this time delay is always less

than tOE (OE access time), the ne xt successive read at-

tempt (OE going low) will provide the valid data on D0-

D7. Also note that once the D6 bit has stopped toggling

and the outpu t enable OE is held low thereafter (with-

out toggling) the data bits (D0–D7) will be valid after

tOEtime delay.

See Figur es 4 and 6 for the Data Po lling diagram an d

timing specifications.

18723C-3

Figure 2. Embedded Programming Algorithm in Byte-Wide Mode

Write Embedded Write Command

Sequence per Table 3 or 4

Verify Byte No

Yes

Data Poll Device

Yes

Increment Address No

Start

Completed

Last

Address

5/4/98 AmC0XXCFLKA 15

Sector Erase Suspend

Sector Erase Suspend command allows the user to in-

terrup t the chip and then do data re ads (not program)

from a non-busy sector while it is in the middle of a

Sector Erase operation (which may take up to several

seconds). This command is applicable ONLY during

the Sector Erase operation and will be ignored if written

during the chip Erase or Programming operation. The

Erase Suspend command (B0H) will be allowed only

duri ng the Sec to r Erase O pe ration th at wi ll i nc lude th e

sector erase time-out period after the Sector Erase

commands (30H). Writing this command during the

time-out will result in immediate termination of the

time-out period. Any subsequent writes of the Sector

Erase command will be ignored as such, but instead

will be taken as the Erase Resume command. Note

that any other commands during the time out will reset

the device to read mode. The addresses are

don’t-cares in writing the Erase Suspend or Erase

Resume commands.

When the Sector Erase Suspend command is written

duri ng a Sector Erase o peration, the chi p will take be-

tween 0.1 µs to 10 µs to suspe nd the erase operat ion

and go into erase suspended read mode (pseudo-read

mode), during which the user can read from a sector

that is NOT being erased. A read from a sector being

erased may result in inv alid data. The user must moni-

tor the toggle bit (D6) to deter mine if the chip has en-

tered th e pseudo -read mod e, at which time the toggle

bit stops toggling. Note that the user must keep track of

what state the chip is in since there is no external indi-

cation of whether the chip is in pseudo-read mode or

actual read mode. After the user writes the Sector

Erase Suspend command and waits until the toggle bit

stops toggling, data reads from the device may then be

performed. Any further writes of the Sector Erase Sus-

pend command at this time will be ignored.

Every time a Sector Erase Suspend command followed

by an Erase Resume com mand is wr itten, the in ter nal

(pulse) counters are reset. These counters are used to

count the number of high voltage pulses the memory

cell requ ir es to program o r eras e. If the count exceeds

a certain limit, then the D5 bit will be set (Exceeded

Time Limit flag). This resetting of the counters is nec-

essary since the Erase Suspend command can poten-

tially interrupt or disrupt the high v oltage pulses.

To resu me the op eration of S ec tor E rase, the Res um e

command (30H) should be written. Any further writes of

the Resum e command at this poi nt will be ignore. An-

other Se ctor Erase Suspend com mand can be wr itten

after the chip has resumed.

16 AmC0XXCFLKA 5/4/98

Write Operation Status

Table 9. Hardware Sequence Flags

Note: D0, D1, and D2 are reserve pins for future use. D4 is for AMD internal use only.

Status D7D6D5D3 D2–D0

In Progress

Auto-Programming D7 Toggle 0 0

Programming in Auto-Erase 0 Toggle 0 1 (D)

Erasing in Auto-Erase 0 Toggle 0 1

Exceeded

Time Limits

Auto-Programming D7 Toggle 1 0

Programming in Auto-Erase 0 Toggle 1 1 (D)

Erasing in Auto-Erase 0 Toggle 1 1

Start

Fail

D7 = Data?

No Pass

Yes

D7 = Data?

D5 = 1?

Yes

Read Byte

(D0–D7)

Addr = VA

Read Byte

(D0–D7)

Addr = VA

18723C-4

Note: D7 is rechecked even if D5 = 1 because D7 may change simultaneously with D5.

Figure 3. Data Polling Algorithm

VA = Valid Address

VA = Byte addr for Write

operation

VA = Any segment (sector)

address during segment

(sector) erase operation

5/4/98 AmC0XXCFLKA 17

Start

Fail

Yes

D6 = Toggle?

Yes Pass

Yes

D6 = Toggle?

D5 = 1?

Read Byte

(D0–D7)

Addr = VA

Read Byte

(D0–D7)

Addr = VA

18723C-5

Note: D6 is rechecked even if D5 = 1 because D6 may stop toggling at the same time as D5 changes to “1”.

Figure 4. Toggle Bit Algorithm

VA = Valid Address

VA = Byte addr for Write

operation

VA = Any segment (sector)

address during segment

(sector) erase operation

18 AmC0XXCFLKA 5/4/98

18723C-6

* D7 = Valid Data (The device has completed the Embedded operation.)

Figure 5. AC W aveforms for Data Polling During Embedded Algorithm Operations

D0–D6

Valid Data

tOE

D7 =

Valid D ata

High-Z

D7 D7

D0–D6 D0–D6 = Invalid

tOEH

tCE

tCH

tDF

tOH

tWHWH 3 or 4

18723C-7

* D6 stops toggling (The device has completed the Embedded operation.)

Figure 6. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

tOEH

D6 =

Stop Toggling D0–D7

Valid

D6 = Toggle

Data

(D0–D7)

tOE

5/4/98 AmC0XXCFLKA 19

EMBEDDED ALGORITHMS

18723C-8

Figure 7. Byte-Wide Programming and Erasure Overview

Software polling from

memory segment

Write Embedded

Programming or Erase

command sequence to

memory segments

Completed

The Emb edded Algorithm opera tions comple tely automate

the programming and erase procedure by internally exe-

cuting the algori thmic com mand seq uence of original AMD

devices. The devices automatically provide Write Opera-

tion Status information with standard read operations.

See Table 3 or 4 for Program Command Sequence.

Start

20 AmC0XXCFLKA 5/4/98

EMBEDDED ALGORITHMS

18723C-9

Figure 8. Byte-Wide Programming Flow Chart

Activity

Initialize Program ming Variables:

EF = Error Flag

PGM =Embedded Byte Write Command

Sequence Cycle #1–3 (Table 3 or 4)

ADRS = Appropriate address for memory segment

PD = Program Data

VDAT = Valid Data

FMD = Flash Memory Data

EF = 0 = No Programming error

EF = 1 = Programming error

Program Complete

Initialization:

EF = 0

Wait 16 µs

Read ADRS/FMD

Program Error

Begin

Programming

Write PGM

Get ADRS/PD

VDAT = PD

Write ADRS/PGM

Write ADRS/VDAT

Yes

FMD = VDAT

More Data

Begin software

polling subroutine

(Figure 9)

5/4/98 AmC0XXCFLKA 21

EMBEDDED ALGORITHMS

D5 = 1?

18723C-10

Note: D7 is checked even if D5 = 1 because D7 may have changed simultaneously with D5 or immediately after D5.

Figure 9. Byte-Wide Software Polling for Programming Subroutine

VA = Byte Address for Prog r am ming

D5 = 1

No = P rogram time not exce eded limit

Yes = Program t ime exceed limit, device failed

EF = Error Flag

Start

Subroutine

Yes

D7 = Data?

D7 = Data

Subroutine

Return

Recommend 16 µs

time out from previous

data polling

Device failed

to program

EF = 1

Device Passed

Read Byte

(D0–D7)

Addr = VA

Read Byte

(D0–D7)

Addr = VA

22 AmC0XXCFLKA 5/4/98

EMBEDDED ALGORITHMS

18723C-11

Figure 10. Byte-Wide Erasure Flow Chart

Activity

EF = Error Flag = 0

SEG ADRS = Segment Address = 0

ERS =Erase Command Sequence

(Even byte per Table 3, Odd byte per Table 4)

3 sec onds wa it = 2 sec onds memory segment

preprogram time +1 second

memory segme nt er as e time

FMD = Flash Memory Data

FFH = Erased Flash Memory Data

Eras e Comp lete

Wait 3 seco nds

Erase Error

Begin

Erase

Yes

FMD = FFH

Las t Segment

Address

Initialization:

EF = 0

SEG ADRS = 0

Write ERS cycle

#1–5

Write SEGADRS/ERS

cycle #6

Read SEG

ADRS/FMD

Begin software

polling subroutine

(Figure 11)

Increment SEG ADRS

5/4/98 AmC0XXCFLKA 23

EMBEDDED ALGORITHMS

D5 = 1?

18723C-12

Figure 11. Byte-Wide Software Polling Erase Subroutine

X = Don’t Care

D7 = 1

Yes = Erase Complete

No = Erase not Complete

D5 = 1

Yes = Erase time exceeded limit, device failed

No = Erase time has not exceeded limit

Start

Subroutine

Yes

D7 = 1?

D7 = 1

Subroutine

Return

Device failed

to program

EF = 1

Device Passed

Read Byte

(D0–D7)

Addr = X

Read Byte

(D0–D7)

Addr = X

24 AmC0XXCFLKA 5/4/98

WORD-WIDE PROGRAMMING AND

ERASING

Word-Wide Programming

The Word-Wide Programming sequence will be as

usual per Table 5. The Program word command is

A0A0H. Each byte is independently programmed. For

example, if the high byte of the word indicates the suc-

cessful com pletio n of programmin g via one o f its wr ite

status bits such as D15, software polling should con-

tinue to monitor the low byte for write completion and

data verification, or vice versa. During the Embedded

Programming operations the device ex ecutes program-

ming pulses in 16 µs increments. Status reads provide

information on the progress of the byte programming

relative to the last complete write pulse. Status informa-

tion is autom atica lly update d u pon c omple tion o f e ach

internal write pulse. Status information does not

change within the 16 µs write pulse width.

Word-W ide Erasing

The Word-Wide Erasing of a memor y segment pair is

similar to word-wide programming. The erase word

command is a 6 bus cycle command sequence per

Table 5. Each byte is independently erased and veri-

fied. Word-wide erasure reduces total erase time when

compar ed to byte erasure. Each Flash memory device

in the card may erase at different rates. Therefore each

device (byte) must be verified separately.

18723C-13

Figure 12. Embedded Algorithm Word-Wide Programming and Erasure Overview

Software polling from

memory segments

Write Embedded

Programming or Erase

command sequence to

memory segments

Completed

The Emb edded Algorithm opera tions comple tely automate

the parallel programming and erase procedures by inter-

nally executing the algorithmic command sequences of

AMD’s Flashrite and Flasherase algorithms. The devices

automatically provide Write Operation Status information

with standard read operations.

See Table 5 for Program Command Sequence.

Start

5/4/98 AmC0XXCFLKA 25

EMBEDDED ALGORITHMS

18723C-14

Figure 13. Word-Wide Programming Flow Chart

Activity

Initialize Program ming Variables:

EF = Error Flag

EF = 0 = No failure

EF = 1 = Low byte program error

EF = 2 = High byte program error

EF = 3 = Word-wide prog r a m error

VWDAT = Valid Word Data

PGM =Embedded Word Write Command

Sequence Cycle #1–3 (Table 5)

ADRS = Appropriate address for Memory Segment

(Cyc le #4)

PDW = Program Data Word

FMD = Flash Memory Data

Program Complete

Initialization:

EF = 0

Program Error

Begin

Programming

Yes

FMD = VWDAT

More Data

Get ADRS/PDW

VWDAT = PDW

Write PGM

Write ADRS/PDW

Wait 16 µs

Read ADRS/FMD

Begin software

polling subroutine

(Figure 14)

26 AmC0XXCFLKA 5/4/98

EMBEDDED ALGORITHMS

18723C-15

Figure 14. Word-Wide Software P ollin g Program Subro utine

VA = Word Address for Programming

data

= Valid data

D5/13 = 1?

Yes = Erase time has exceeded limit, device failed

No = Erase time has not exceeded limit

Start

Subroutine

Yes

D7 = Vdata?

Yes

D15 = Vdata?

Subroutin e

Return

Low byte pr ogram

time ex ceeded limit,

EF = 1

Read Byte

(D0–D7)

Addr = VA

Read Byte

(D8–D15)

Addr = VA

D5 = 1?

Read Byte

(D0–D7)

Addr = VA

Yes

D7 = Vdata?

No No

D13 = 1?

Read Byte

(D8–D15)

Addr = VA No

D15 = Vdata?

Yes

High byte program

time ex ceeded limit,

EF = 2 + EF

Yes

5/4/98 AmC0XXCFLKA 27

EMBEDDED ALGORITHMS

18723C-16

Figure 15. Word-Wide Erasure Flow Chart

Activity

EF = Error Flag

EF = 0 = No failure

EF = 1 = Low byte erase error

EF = 2 = High byte erase error

EF = 3 = Word-wi de er as e error

SEG ADRS = Segment Address

ERS = Se gment Er ase Comm and Sequenc e (Table 5)

FMD = Flash Memory Data

Eras e Comp lete

Wait 3 seco nds

Erase Error

Begin

Erase

Yes

FMD = FFFFH

Las t Segment

Address

Read SEG

ADRS/FMD

Begin software

polling subroutine

(Figure 16)

Increment SEG ADRS

Write ERS

cycle #6:

SEG ADRS

Initialization:

EF = 0

SEG ADRS = 0

Write ERS

cycle #1– 5

28 AmC0XXCFLKA 5/4/98

EMBEDDED ALGORITHMS

18723C-17

Figure 16. Word-Wide Software Polling Erase Subroutine

D7/15 = 1

Yes = Erase complete

No = Erase not complete

D5/13 = 1

Yes = Erase time has exceeded limit, device failed

No = Erase time has not exceeded limit

Start

Subroutine

Yes

D7 = 1?

Yes

D15 = 1?

Subroutine

Return

Low byte pr ogram

time ex ceeded limit,

EF = 1

Read Byte

(D0–D7)

Read Byte

(D8–D15)

D5 = 1?

Read Byte

(D0–D7)

Yes

D7 = 1?

No No

D13 = 1?

D15 = 1?

Yes

High byte program

time exceeded limit,

EF = 2 + EF

Yes

Read Byte

(D8–D15)

Yes

5/4/98 AmC0XXCFLKA 29

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . . –30°C to +70°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . –10°C to +70°C

Voltage at All Pins (Note 1) . . . . . . . .–2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . . .–0.5 V to 6.0 V

Output Short Circuit Current (Note 2) . . . . . . . 40 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, inputs may overshoot V

to –2.0 V

f or periods o f up to 2 0 ns . Maxim um DC v oltage on outp ut

and I/O pins is V

+ 0.5 V. During voltage transitions,

outputs may overshoot to V

+ 2.0 V for periods up to

20ns.

2. No more than one output shorted at a time. Durations of

the short circuit should not be greater than one second.

Conditions equal V

OUT

= 0.5 V or 5.0 V, V

= V

max.

These values are chosen to avoid test problems caused

by tester ground degradation. This parameter is sampled

and not 100% t ested, b ut guar anteed b y c haracteri zation.

3. V

PP1

and V

PP2

are not connected.

Stresses above those listed under “Absolute Maximum

Rating s” ma y cause permanent d amage to the de vice . This is

a stress rating only; functional operation of the device at

these o r any ot her condi tions abo ve th ose indica ted in the o p-

erational sections of this specification is not implied. Expo-

sure of the device to absolute maximum rating conditions for

extended periods may affect device reliabili ty.

OPERATING RANGES

Commercial (C) Devices

Case Temperature (TC). . . . . . . . . . . . . .0°C to +60°C

VCC Supply Voltages. . . . . . . . . . . . +4.75 V to 5.25 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

30 AmC0XXCFLKA 5/4/98

DC CHARACTERISTICS

Byte-Wide Operation

Notes:

1. For TTL input voltage l evels (V

or V

), the minimum limit should be increased by: 1 mA for 1 Mbyte

3 mA for 2 Mbyte

7 mA for 4 Mbyte

19 mA for 10 Mbyte.

2. One Flash device acti ve, al l the others in standby.

Parameter

Symbol Parameter Description Test Description Min Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS

For all cards:

(CE, REG, WE, OE = –300 µA Min)

1 MB –300 + 20

µA

2 MB –300 + 20

4 MB –300 + 20

10 MB –300 + 20

ILO Output Leakage Current VCC = VCC Max,

VOUT = VCC or VSS

1 MB ± 20

µA

2 MB ± 20

4 MB ± 20

10 MB ± 20

ICCS VCC Standby Current (Note 1) VCC = VCC Max

CE = VCC ± 0.2 V

VIN = VCC or GND

1 MB 0.7

2 MB 0.9

4 MB 1.3

10 MB 2.5

ICC1 VCC Active Read Current

(Notes 1, 2) VCC = VCC Max, CE = VIL,

OE = VIH, IOUT = 0 mA, at 3.3 MHz 45 mA

ICC2 VCC Write/Erase Current

(Notes 1, 2) CE = VIL

Programming in Progress 65 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.4 VCC + 0.3 V

VOL Output Low Voltage IOL = 3.2 mA, VCC = VCC Min 0.40 V

VOH Output High Voltage IOH = 2.0 mA, VCC = VCC Min 3.8 VCC V

VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

5/4/98 AmC0XXCFLKA 31

Word-Wide Operation

Notes:

1. For TTL input voltage l evels (V

or V

), the minimum limit should be increased by: 2 mA for 2 Mbyte

6 mA for 4 Mbyte

18 mA for 10 Mbyte.

2. Two Flash devices active, all the others in standby

Parameter

Symbol Parameter Description Test Description Min Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS

(CE, REG, WE, OE = –300 µA Min)

1 MB –300 + 20

µA

2 MB –300 + 20

4 MB –300 + 20

10 MB –300 + 20

ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS

1 MB ± 20

µA

2 MB ± 20

4 MB ± 20

10 MB ± 20

ICCS VCC Standby Current (Note 1) VCC = VCC Max

CE = VCC ± 0.2 V

VIN = VCC or GND

1 MB 0.7

2 MB 0.9

4 MB 1.3

10 MB 2.5

ICC1 VCC Active Read Current

(Notes 1, 2) VCC = VCC Max, CE = VIL,

OE = VIH, IOUT = 0 mA, at 3.3 MHz 90 mA

ICC2 VCC Programming Current

(Notes 1, 2) CE = VIL

Programming in Progress 130 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.4 VCC + 0.3 V

VOL Output Low Voltage IOL = 3.2 mA, VCC = VCC Min 0.40 V

VOH Output High Voltage IOH = 2.0 mA, VCC = VCC Min 3.8 VCC V

VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

32 AmC0XXCFLKA 5/4/98

PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz.

SWITCHING A C CHARACTERISTICS

Read Only Operation (Note 1)

Note:

1. Input Rise and Fall Times (10% to 90%): ð 10 ns, Input Pulse levels:

and V

, Timing Measurement Reference Level: Inputs—V

and V

Outputs—V

and V

Parameter Symbol Parameter Description Test Conditions Max Unit

CIN1 All except A1–A9 VIN = 0 V 31 pF

COUT Output Ca pa cit anc e V OUT = 0 V 31 pF

CIN2 A1–A9 VIN = 0 V 45 pF

CI/O I/O Capacitance D0–D15 VI/O = 0 V 31 pF

Card Speed

Parameter Symbol

Parameter Description

-150 ns

UnitJEDEC Standard Min Max

tAVAV tRC Read Cycle Time 150 ns

tELQV tCE Chip Enable Access Time 150 ns

tAVQV tACC Address Access Time 150 ns

tGLQV tOE Output Enable Access Time 75 ns

tELQX tLZ Chip Enable to Output in Low-Z 5 ns

tEHQZ tDF Chip Disable to Output in High-Z 75 ns

tGLQX tOLZ Output Enable to Output in Low-Z 5 ns

tGHQZ tDF Output Disable to Output in High-Z 75 ns

tAXQX tOH Output Hold from First of Address, CE, or OE Change 5 ns

tWHGL Write Recovery Time Before Read 6 µs

5/4/98 AmC0XXCFLKA 33

AC CHARACTERISTICS

Write/Erase/Program Operations

Notes:

1. Rise/Fall ð 10 ns.

2. Maximum specification not needed due to the devices internal stop timer that will stop any erase or write operation that exceed

the device specific ation.

3. Embedded Program Operation of 16

s consist of 10

s program pulse and 6

s write recovery before read. This is the

minimum time for one pass through the programming algorithm. D5 = “1” only after a byte takes longer than 48 ms to Write.

Card Speed

Parameter Symbol

Parame ter Description

-150 ns

UnitJEDEC Standard Min Typ Max

tAVAV tWC Write Cycle Time 150 ns

tAVWL tAS Address Setup Time 20 ns

tWLAX tAH Address Hold Time 55 ns

tDVWH tDS Data Setup Time 50 ns

tWHDX tDH Da ta Ho ld Time 20 ns

tOEH Output Enable Hold Time for Embedded Algorithm 20 ns

tWHGL tWR Write Recovery Time before Read 6 µs

tGHWL Read Recovery Time before Write 0 µs

tWLOZ Output in High-Z from Write Enable 5 ns

tWHOZ Output in Low-Z from Write Enable 60 ns

tELWL tCS CE Setup Time 0 ns

tWHEH tCH CE Hold Time 20 ns

tWLWH tWP Write Pulse Widt h 45 ns

tWHWL tWPH Write Pulse Widt h HIG H 50 ns

tWHWH3 Embedded Programming Operation (Notes 1, 2, 3) 16 µs

48 ms

tWHWH4 Embedded Erase Operation for each 64K Byte

Memory Sector (Notes 1, 2) 1.5 s

tVCS VCC Setup Time to CE LOW 50 µs

34 AmC0XXCFLKA 5/4/98

KEY TO SWITCHING WAVEFORMS

SWITCHING WAVEFORMS

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010-PAL

18723C-18

Note: CE refers to CE1 and CE2.

Figure 17. AC Waveforms for Read Operations

Addresses

Outputs

Addresses Stable

High-Z High-Z

(tDF)

(tOH)

Output Valid

tACC

tOE

(tCE)

tRC

5/4/98 AmC0XXCFLKA 35

SWITCHING WAVEFORMS

18723C-19

Note: SA is the sector address for Sector Erase per Table 6.

Figure 18. AC Waveforms Segment/Sector Byte Erase Operations

tAS

tWP

tCS tDH

AAAAH 5554H SA

Data

VCC

AAH 55H

Addresses 5554H

tVCS

tDS

AAAAH AAAAH

tWPH

tGHWL

tAH

AAH 55H80H 10H/30H

36 AmC0XXCFLKA 5/4/98

SWITCHING WAVEFORMS

VCC tVCS

18723C-20

Notes:

1. Figure indicates last two bus cycles of four bus cycle sequence.

2. PA is address of the memory location to be programmed.

3. PD is data to be programmed at byte address.

4. D7 is the output of the complement of the data written to the device.

5. D

OUT

is the output of the data written to the device.

Figure 19. AC Waveforms f or Byte Write Operations

DOUT

tAH

Data Polling

tDF

tOH

tOE

tDS

tCS tWPH

tDH

tWP

tGHWL

Addresses

Data D7

AAAAH PA

A0H

tWC tRC

tAS

tWHWH3

tCE

5/4/98 AmC0XXCFLKA 37

AC CHARACTERISTICS—ALTERNATE CE CONTROLLED WRITES

Write/Erase/Program Operations

Notes:

1. Rise/Fall ð10 ns.

2. Maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the

device specification.

3. Card Enable Controlled Programming:

Flash Prog ramming is control led by the v alid combin ation of the Card Enable (CE 1, CE2) and Write Enab le (WE) signals. For

systems that us e th e Ca rd Ena ble signal(s) to de fin e the w rite pul se width , all Se tup, Hold, an d ina cti ve Write Enab le ti mi ng

should be measured relative to the Card Enable signal(s).

4. Embedded Program Operation of 16

s consis t of 1 0

s program pulse and 6

s write recovery before read. This is the min-

imum time for one pass through the programming algorithm. D5 = “1” only after a byte takes longer than 48 ms to Write.

Card Speed

Parameter Symbol

Parameter Description

-150 ns

UnitJEDEC Standard Min Max

tAVAV tWC Write Cycle Time 150 ns

tAVEL tAS Address Setup Time 20 ns

tELAX tAH Address Hold Time 55 ns

tDVEH tDS Data Setup Time 50 ns

tEHDX tDH Data Hold Time 20 ns

tGLDV tOE Output Enable Hold Time for Embedded Algorithm 20 ns

tGHEL Read Recovery Time before Write 0 µs

tWLEL tWS WE Setup Time before CE 0ns

EHWH tWH WE Hold Time 0 ns

tELEH tCP CE Pulse Width 65 ns

tEHEL tCPH CE Pulse Width HIGH (Note 3) 50 ns

tEHEH3 Embedded Programming Operation (Notes 3, 4) 16 µs

48 ms

tEHEH4 Embedded Erase Operation for each 64K byte Memory Sector

(Notes 1, 2) 1.5 s

tVCS VCC Setup Time to Write Enable LOW 50 ms

38 AmC0XXCFLKA 5/4/98

SWITCHING WAVEFORMS

18723C-21

Notes:

1. Figure indicates last two bus cycles of four bus cycle sequence.

2. PA is address of the memory location to be programmed.

3. PD is data to be programmed at byte address.

4. D7 is the output of the complement of the data written to the device.

5. D

OUT

is the output of the data written to the device.

Figu re 2 0. Al tern a t e CE Controlled Byte Write Operation Timings

DOUT

tAH

Data Polling

tDS

tWS tCPH

tDH

tCP

tGHEL

Addresses

Data

VCC

AAAAH PA

A0H

tWC tAS

tWHWH3 or 4

tWH

tVCS

5/4/98 AmC0XXCFLKA 39

CARD INFORMATION STRUCTURE

The “C” series card contains a separate 512 byte

EEPROM memory for the Card Information Structure

(CIS).

All or part of the 51 2 byte cou ld be used for the c ard’s

attribute memory space. This allows all of the Flash

memory to be used for the common memory space.

P art of the common memory space could also be used

to store the CIS if more than 512 bytes of CIS are

needed.

The EEPROM used in the “C” series card is a NEC

µPD28C05G X- 20 -EJA designe d to op erate fro m a 5 V

single power supply. The µPD28C05 provides a Data

Polling function that provides the End of Write Cycle

and Auto Erase and Programming functions.

Table 10 shows the CIS information stored in the AMD

Flash memory card.

SYSTEM DESIGN AND INTERFACE

INFORMATION

Power Up and Power Down Protection

AMD’s Flas h memor y devi ces are desi gned to protec t

against a ccidenta l programming or erasur e caused by

spur ious system s ignals that might ex ist durin g power

transitions. The AMD PC Card will power-up into a

READ mode when VCC is greater than VLKO of 3.2 V.

Erasing of memor y sectors or memor y segments can

be accomplished only by writing the proper Erase com-

mand to the card along with the proper Chip Enable,

Output Enable and Write Enable control signals. Hot in-

sertion of PC cards is not permitted by the PCMCIA

standard.

Note: Hot inse rt ion is defined as the so cket conditio n

where the card is inserted or removed with any or

all of the following conditions present: V

= V

CCH

PPH

, address and/or data lines are active).

System Power Supply Decoupling

The AMD Flash memory card has a 0.1 µF decoupling

capacitor between the VCC and the GND pins. It is rec-

ommended the sy s tem si de als o have a 4.7 µF capac-

itor between the VCC and the GND pins.

40 AmC0XXCFLKA 5/4/98

Table 10. AMD’s CIS for “C” Series Card

Tuple

Address 2 Mbyte Card

Tuple Value Tuples and Rema rks

00h 01h CISTPL_DEVICE [Common Memory]

02h 03h TPL_LINK

04h 53h Flash Device, Card Speed: 53h = 150 ns

06h 0Dh/06h/FCh/9Dh Card Size: 0Dh = 1 MB, 06h = 2 MB, FCh = 4 MB, 9Dh = 10 MB

08h FFh End of Tuple

0Ah 18h CISTPL_JEDEC [Common Memory]

0Ch 02h TPL_LINK

0Eh 01h AMD MFG ID Code

10h A4h Device ID Code: A4h = 4 Mbit Device

12h 1Eh CISTPL_DEVICEGEO

14h 06h TPL_LINK no FFh terminator

16h 02h DGTPL_BUS: Bus Width

18h 11h DGTPL_EBS: 11h = 64K Byte Erase Block size

1Ah 01h DGTPL_RBS: Read Byte Size

1Ch 01h DGTPL_WBS: Write Byte Size

1Eh 01h DGTPL_PART: Number of partition

20h 01h FL DEVICE INTERLEAVE: No interleave

22h 15h CISTPL_VERS1

24h 03h TPL_LINK

26h 04h Major version number 1

28h 01h Minor version for PCMCIA Std. 2.0

2Ah FFh End of Tuple

2Ch 17h CISTPL_DEVICE_A [Attribute Memory]

2Eh 04h TPL_LINK

30h 47h EEPROM with extended sp eed

32h 3Ah Extended speed = 250 ns

34h 00h Device Size = 1 unit of 512 byte

36h FFh End of Tuple

38h 80h Vendor-Spec ific Tuple

3Ah 0Ah TPL_LINK

3Ch 41h “A”

3Eh 4Dh “M”

40h 44h “D”

42h 26h “&”

44h 42h “B”

46h 45h “E”

48h 52h “R”

4Ah 47h “G”

4Ch 00h END TEXT

4Eh FFh End of Tuple

50h 81h Vendor Spec ific Tuples: 81h

: xxh ASCII Characters

: xxh :

6Ah xxh ASCII Characters

6Ch FFh CISTPL_END

5/4/98 AmC0XXCFLKA 41

PHYSICAL DIMENSIONS*

Type 1 PC Card

Trademarks

AMD and the AMD logo are registered tradema r ks of Advanced Micro Devices, Inc.

Embedded Erase and Embedded Program are trademarks of Advanced Micro Devices, Inc.

Product names used in this public ation are for identification purposes only and may be trademarks of their respective companies.

10.0 Min (mm)

85.6 ± 0.2 mm

54.0 ± 0.1 mm

3.3 ± 0.1 mm

34 1

3568

Front Side

Back Side

42 AmC0XXCFLKA 5/4/98

DATA SHEET SUMMARY FOR AMC0XXCFLKA

PIN DESCRIPTION

Added description for REG pin.

Table 3. Even Byte Command Definitions

Each density card now has a list of paired segment

numbers. The address increment for Even bytes should

be (N/2) * 100000H.

Added Note 5 for clarification. Note 3 requires use of

CE1, not CE2, and A21. Note 2 was clarified.

Table 4. Odd Byte Command Definitions

Each density card now has a list of paired segment

numbers. The address increment for Even bytes should

be (N-1/2) * 100000H + 8000 0H.

Added Note 5 for clarification. Note 3 requires use of

CE2, not CE1, and A21. Note 2 was clarified.

Autoselect operation data is A4h.

Table 5. Word Command Definitions

Added Note 7 for clarification. Note 3 requires use of

CE1 and CE2 an d A21 . No te 5 was mo dif ied to r efl ect

that the address should be (Addr) + M * (100000H).

Note 2 was clarified.

A utoselect operation data is 0101/A4A4h.

Sector Erase

Clarified that any sector number can be loaded into the

sector erase buffer.

Toggle Bit—D6

Added cl arificati on that D6 is us ed for enter ing Sector

Erase Suspe nd mod e.

Sector Erase Suspend

Repeated sentence was deleted.

Write Operation Status Table

D3 in ‘Exceeded Time Limit’ mode is 0.

Figure 5. A C Waveforms for Data Polling During

Embedded Algorithm Operations

Corrected tWHWH3 or 4. Removed erroneous tOE

reference.

Figure 6. A C Waveforms for Toggle Bit During

Embedded Algorithm Operations

Clarified diagram.

Embedded Algorithm Flow Charts

Figures 6, 7, 11 references to 14 µs time outs were cor-

rected to 16 µs.

DC Characteristics—Byte-Wide Operation

Note 1 has been modified to show standby current is in-

creased by: 19 mA for 10 Mb, 7 mA fo r 4 Mb, 3 mA for

2Mb and 1 mA for 1 Mb card in TTL modes.

DC Characteristics—Word-Wide Operation

For CE, REG, WE, OE, IIL minimum is –300 µA. Note 1

has been modified to show standby current is in-

creased by: 18 mA for 10 Mb , 6 mA f or 4 Mb, and 2 mA

for 2 Mb card in TTL modes.

AC Characteristics—Write/Erase/Program

Operations

tWHWH4 applies to 64K Byte sectors. Note 1 was modi-

fied to exclude the statement regarding preprogram-

ming time.

Figure 19. AC W aveforms for Byte Write Operations

tWHWH1 is now tWHWH3. The Unlock address was

changed to AAAAh according to the Byte Write se-

quence. Added t.

AC Characteristics—Alternate CE Controlled

Writes—Write/Erase/Program Operations

tWHWH4 applies to 64K Byte sectors. Note 1 was modi-

fied to exclude the statement regarding preprogram-

ming time.

Figure 20. Alternate CE Controlled Byte Write

Operation Timings

Added tVCS and tEHEH3 or 4 to Figure 18.

Table 10. AMD’s CIS for AmC0XXCFLKA

Removed bracketed reference for Tuple Address 04h.

Tuple Addres s 32h now refle cts CIS memory speed of

250 ns (3Ah).

Revision B+1

Sector Erase Suspend

Removed the statement requiring the address of a sec-

tor not being erased for valid D6 status.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademark s of Advanced Micro Devices, Inc.

Product names used in this public ation are for identification purposes only and may be trademarks of their respective companies.