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FEATURES APPLICATIONS
DESCRIPTION
DIR9001
SLES198 – DECEMBER 2006
96-kHz, 24-Bit Digital Audio Interface Receiver
•AV/DVD Receiver, AV Amplifier•One-Chip Digital Audio Interface Receiver(DIR) Including Low-Jitter Clock-Recovery
•Car or Mobile Audio SystemSystem
•Digital Television•Compliant With Digital Audio Interface
•Musical InstrumentsStandards: IEC60958 (former IEC958), JEITA
•Recording SystemsCPR-1205 (former EIAJ CP-1201, CP-340),
•High-End Audio/Sound Card for PCAES3, EBU tech3250
•Replacement of DIR1703•Clock Recovery and Data Decode From
•Other Applications Requiring S/PDIF ReceiverBiphase Input Signal, Generally Called S/PDIF,EIAJ CP-1201, IEC60958, AES/EBU•Biphase Input Signal Sampling Frequency (f
S
)
The DIR9001 is a digital audio interface receiver thatRange: 28 kHz to 108 kHz
can receive a 28-kHz to 108-kHz sampling-•Low-Jitter Recovered System Clock: 50 ps
frequency, 24-bit-data-word, biphase-encoded signal.The DIR9001 complies with IEC60958-3, JEITA•Jitter Tolerance Compliant With IEC60958-3
CPR-1205 (Revised version of EIAJ CP-1201),•Selectable Recovered System Clock: 128 f
S
,
AES3, EBUtech3250, and it can be used in various256 f
S
, 384 f
S
, 512 f
S
applications that require a digital audio interface.•Serial Audio Data Output Formats: 24-Bit I
2
S;
The DIR9001 supports many output system clockMSB-First, 24-Bit Left-Justified; MSB-First 16-,
and output data formats and can be used flexibly in24-Bit Right-Justified
many application systems. As the all functions which•User Data, Channel-Status Data Outputs
the DIR9001 provides can be controlled directlySynchronized With Decoded Serial Audio Data
through control pins, it can be used easily in anapplication system that does not have a•No External Clock Required for Decode
microcontroller. Also, as dedicated pins are provided•Includes Actual Sampling Frequency
for the channel-status bit and user-data bit,Calculator (Needs External 24.576-MHz Clock)
processing of their information can be easily•Function Control: Parallel (Hardware)
accomplished by connecting with a microcontroller,DSP, etc.•Functions Similar and Pin AssignmentsEquivalent to Those of DIR1703
The DIR9001 does not require an external clocksource or resonator for decode operation if the•Single Power Supply: 3.3 V (2.7 V to 3.6 V)
internal actual-sampling-frequency calculator is not•Wide Operating Temperature Range: –40 °C to
used. Therefore, it is possible to reduce the cost of a85 °C
system.•5 V-Tolerant Digital Inputs
The operating temperature range of the DIR9001 is•Package: 28-pin TSSOP, Pin Pitch: 0,65 mm
specified as –40 °C to 85 °C, which makes it suitablefor automotive applications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SpAct is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
DIR9001
SLES198 – DECEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage –0.3 to 4 VV
DD
V
CC
to V
DD
Supply voltage differences ±0.1 VAGND to DGND Ground voltage differences ±0.1 VDigital input –0.3 to 6.5Digital input voltage VDigital output –0.3 to (V
DD
+ 0.3) < 4XTI, XTO –0.3 to (V
CC
+ 0.3) < 4Analog input voltage VFILT –0.3 to (V
CC
+ 0.3) < 4Input current (any pins except supplies) ±10 mAAmbient temperature under bias –40 to 125 °CStorage temperature –55 to 150 °CJunction temperature 150 °CLead temperature (soldering) 260 °C, 5 sPackage temperature (reflow, peak) 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Analog supply voltage 2.7 3.3 3.6 VDCV
DD
Digital supply voltage 2.7 3.3 3.6 VDCXTI is connected to clock source 24.576 MHzDigital input clock frequency
XTI is connected to DGND Not required MHzDigital output load capacitance, except SCKO 20 pFDigital output load capacitance (SCKO) 10 pFT
A
Operating free-air temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS
DIR9001
SLES198 – DECEMBER 2006
All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT/OUTPUT CHARACTERISTICS
V
IH
0.7 V
DD
V
DDInput logic level
(1)
VDCV
IL
0.3 V
DD
V
IH
2 5.5Input logic level
(2)
VDCV
IL
0.8V
OH
I
O
= 4 mA 0.85 V
DDOutput logic level
(3)
VDCV
OL
I
O
= –4 mA 0.15 V
DD
I
IH
V
IN
= V
DD
65 100Input leakage current
(4)
µAI
IL
V
IN
= 0 V –10 10I
IH
V
IN
= V
DD
–10 10Input leakage current
(5)
µAI
IL
V
IN
= 0 V –100 –65I
IH
V
IN
= V
DD
–10 10Input leakage current
(6)
µAI
IL
V
IN
= 0 V –10 10
BIPHASE SIGNAL INPUT AND PLL
Input sampling frequency range 28 108 kHzJitter tolerance — (IEC60958-3) IEC60958-3 (2003-01) CompliantFrom biphase signal detection to error-outPLL lock-up time 100 msrelease (ERROR = L)
RECOVERED CLOCK AND DATA
Serial audio data width 16 24 Bit128 f
S
3.584 13.824256 f
S
7.168 27.648SCKO frequency MHz384 f
S
10.752 41.472512 f
S
14.336 55.296BCKO frequency 64 f
S
1.792 6.912 MHzLRCKO frequency f
S
28 108 kHzf
S
= 48 kHz, SCKO = 256 f
S
, measuredSCKO jitter 50 100 ps rmsperiodicSCKO duty cycle 45% 55%
XTI SOURCE CLOCK
XTI is connected to clock source 24.576XTI source clock frequency MHzNotXTI is connected to DGND
requiredFrequency accuracy XTI is connected to clock source –100 100 ppmXTI input-clock duty cycle XTI is connected to clock source 45% 55%
POWER SUPPLY AND SUPPLY CURRENT
V
CC
2.7 3.3 3.6Operation voltage range VDCV
DD
2.7 3.3 3.6
(1) CMOS compatible input: XTI (not 5-V tolerant)(2) 5-V tolerant TTL inputs: RXIN, FMT0, FMT1, PSCK0, PSCK1, CKSEL, RST, RSV(3) CMOS outputs: XTO, SCKO, BCKO, LRCKO, DOUT, UOUT, COUT, BFRAME, ERROR, CLKST, AUDIO, EMPH, FSOUT0, FSOUT1(4) Internal pulldowns: FMT0, FMT1, PSCK0, PSCK1, CKSEL, RSV(5) Internal pullup: RST(6) No internal pullup and pulldown: RXIN, XTI
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PIN ASSIGNMENTS
8
7
6
5
4
3
2
1AUDIO
FSOUT0
FSOUT1
SCKO
VDD
DGND
XTO
XTI
CLKST
LRCKO
BCKO
DOUT
PSCK0
PSCK1
21
22
23
24
25
26
27
28
CKSEL
ERROR
FMT1
FMT0
VCC
AGND
FILT
RST
RXIN
RSV
BFRAME
EMPH
UOUT
COUT
14
13
12
11
10
9
15
16
17
18
19
20
DIR9001
(TOP VIEW)
DIR9001
SLES198 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
S
= 96 kHz, PLL locked, XTI connected 6 8.3 mAto DGNDI
CC
Supply current
(7)
f
S
= 96 kHz, PLL locked, XTI connected 6 8.3 mAto 24.576-MHz resonatorRXIN = H or L, XTI = L, RST = L 130 µAf
S
= 96 kHz, PLL locked, XTI connected 6 8.3 mAto DGNDI
DD
Supply current
(7)
f
S
= 96 kHz, PLL locked, XTI connected 9 12.4 mAto 24.576-MHz resonatorRXIN = H or L, XTI = L, RST = L 72 µAf
S
= 96 kHz, PLL locked, XTI connected 40 55 mWto DGNDP
D
Power dissipation
(7)
f
S
= 96 kHz, PLL locked, XTI connected 50 68 mWto 24.576-MHz resonatorRXIN = H or L, XTI = L, RST = L 0.67 mW
TEMPERATURE RANGE
T
A
Operation temperature range –40 85 °Cθ
JA
Thermal resistance 28-pin T-SSOP 105 °C/W
(7) No load connected to SCKO, BCKO, LRCKO, DOUT, COUT, VOUT, BFRAME, FSOUT0, FSOUT1, CLKST, ERROR, EMPH, AUDIO
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DIR9001
SLES198 – DECEMBER 2006
TERMINAL FUNCTIONS
TERMINAL
PULLI/O REMARKS DESCRIPTIONUP/DOWNNAME NO.
AGND 23 – Analog groundAUDIO 1 OUT CMOS Channel-status data information of non-audio sample word, active-lowBCKO 11 OUT CMOS Audio data bit clock outputBFRAME 18 OUT CMOS Indication of top block of biphase input signalCKSEL 28 IN Pulldown 5-V tolerant TTL Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock
(1)
CLKST 9 OUT CMOS Clock change/transition signal outputCOUT 15 OUT CMOS Channel-status data serial output synchronized with LRCKODGND 6 – Digital groundDOUT 12 OUT CMOS 16-bit/24-bit decoded serial digital audio data outputEMPH 17 OUT CMOS Channel-status data information of pre-emphasis (50 µs/15 µs)ERROR 27 OUT CMOS Indication of internal PLL or data parity errorFILT 22 – External filter connection terminal; must connect recommended filter.FMT0 25 IN Pulldown 5-V tolerant TTL Decoded serial digital audio data output format selection 0
(1)
FMT1 26 IN Pulldown 5-V tolerant TTL Decoded serial digital audio data output format selection 1
(1)
FSOUT0 2 OUT CMOS Actual sampling frequency calculated result output 0FSOUT1 3 OUT CMOS Actual sampling frequency calculated result output 1LRCKO 10 OUT CMOS Audio data latch enable outputPSCK0 13 IN Pulldown 5-V tolerant TTL PLL source SCKO output frequency selection 0
(1)
PSCK1 14 IN Pulldown 5-V tolerant TTL PLL source SCKO output frequency selection 1
(1)
RST 21 IN Pullup 5-V tolerant TTL Reset control input, active-low
(2)
RSV 19 IN Pulldown Reserved, must be connected to DGND
(1)
RXIN 20 IN 5-V tolerant TTL Biphase digital data input
(3)
SCKO 4 OUT CMOS System clock outputUOUT 16 OUT CMOS User data serial output synchronized with LRCKOV
CC
24 – Analog power supply, 3.3-VV
DD
5 – Digital power supply, 3.3-VCMOSXTI 8 IN Oscillation amplifier input, or external XTI source clock inputSchmitt-triggerXTO 7 OUT CMOS Oscillation amplifier output
(1) TTL Schmitt-trigger input with internal pulldown (51 k Ωtypical), 5-V tolerant(2) TTL Schmitt-trigger input with internal pullup (51 k Ωtypical), 5-V tolerant(3) TTL Schmitt-trigger input, 5-V tolerant.
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BLOCK DIAGRAM
Clock and Data Recovery
SCKO
BCKO
LRCKO
DOUT
RXIN
Divider
FILT XTOXTI
FSOUT0
FSOUT1
RST
OSC
RESET
CLKST
EMPH
UOUT
COUT
BFRAME
VCO
CKSEL
DGND
ERROR
AUDIO
Power Supply
VDD DGND AGND
VCC
PSCK0
PSCK1
FMT0
RSV
PLL
Divider
Decoder
FMT1
Preamble
Detector
Charge
Pump
Sampling
Frequency
Calculator
Clock
Decoder
Biphase
Data Decoder
Serial
AudioData
Formatter
ERROR
Detector
Function
Control
AudioData
MUTE Control
Channel Status
and
UserData
Output
DIR9001
SLES198 – DECEMBER 2006
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TYPICAL PERFORMANCE CHARACTERISTICS
POWER SUPPLY CURRENT
fS − Sampling Frequency − kHz
6
8
10
12
14
16
18
20
30 40 50 60 70 80 90 100
ICC + IDD − Supply Current − mA
G001
–40°C
25°C–25°C
0°C
50°C
85°C
VCC = VDD = 3.3 V
SCKO = 256 fS
fS − Sampling Frequency − kHz
6
8
10
12
14
16
18
20
30 40 50 60 70 80 90 100
ICC + IDD − Supply Current − mA
G002
3 V
3.6 V 3.3 V
2.7 V
TA = 255C
SCKO = 256 fS
RECOVERED SYSTEM CLOCK (SCKO) JITTER
fS − Sampling Frequency − kHz
20
40
60
80
100
120
140
160
180
200
30 40 50 60 70 80 90 100
Periodic Jitter − ps rms
G003
128 fS
384 fS
256 fS
512 fS
VCC = VDD = 3.3 V
TA = 255C
DIR9001
SLES198 – DECEMBER 2006
Oscillation amplifier operating with crystal; 1-kHz, 0-dB, sine-wave data; no load
SUPPLY CURRENT SUPPLY CURRENTvs vsLOCKED SAMPLING FREQUENCY LOCKED SAMPLING FREQUENCY
Figure 1. Figure 2.
SCKO JITTER
vsLOCKED SAMPLING FREQUENCY
Figure 3.
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DEVICE INFORMATION
ACCEPTABLE BIPHASE INPUT SIGNAL AND BIPHASE INPUT PIN (RXIN)
DIR9001
SLES198 – DECEMBER 2006
The DIR9001 can decode the biphase signal format which is specified in one of the following standards.Generally, these following standards may be called Sony/Philips digital interface format (S/PDIF) or AES/EBU.•IEC60958 (revised edition of former IEC958)•JEITA CPR-1205 (revised edition of former EIAJ CP-1201, CP-340)•AES3
•EBU tech3250
The sampling frequency range and data word length which DIR9001 can decode is as follows:•Sampling frequency range is 28 kHz to 108 kHz.•Maximum audio sample word length is 24-bit.
Note of others about the biphase input signal.•The capture ratio of the built-in PLL complies with level III of sampling frequency accuracy (±12.5%), which isspecified in IEC60958-3.•The jitter tolerance of the DIR9001 complies with IEC60958-3.•The PLL may also lock in outside of the specified sampling-frequency range, but extended range is notassured.
Notice about the signal level and transmission line of the biphase input signal.•The signal level and the transmission line (optical, differential, single-ended) are different in each standard.•The biphase input signal is connected to the RXIN pin of the DIR9001.•The RXIN pin has a 5-V tolerant TTL-level input.•An optical receiver module (optical to electric converter) such as TOSLINK, which is generally used inconsumer applications, is connected directly to the RXIN pin without added external components.•The output waveform of the optical receiver module varies depending on the characteristics of each producttype, so a dumping resistor or buffer amplifier might be required between the optical receiver module outputand the DIR9001 input. Careful handling is required if the optical receiver module and the DIR9001 areseparated by a long distance.•The DIR9001 needs an external amplifier if it is connected to a coaxial transmission line.•The DIR9001 needs an external differential to single-ended converter, attenuator, etc., for general consumerapplications if non-optical transmission line is used.
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SYSTEM RESET
VDD
2.7 V
Min. 100 ns
Reset
RST
Operation
Unknown
DIR9001
Status
DIR9001
SLES198 – DECEMBER 2006
DEVICE INFORMATION (continued)
The DIR9001 reset function is controlled by and external reset pin, RST.
The reset operation must be performed during the power-up sequence as shown in Figure 4 . Specifically, theDIR9001 requires reset operation with a 100-ns period after the supply voltage rises above 2.7 V.
Figure 4. Required System Reset Timing
The state of each output pins during reset is shown in Table 1 .
Table 1. Output-Pin States During Reset Period
CLASSIFICATION PIN NAME WHILE RST = L
BCKO LClock LRCKO LSCKO LData DOUT LAUDIO LBFRAME LCLKST LCOUT LFlag and status EMPH LERROR HFSOUT0 LFSOUT1 LUOUT LOscillation amplifier XTO Output
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OPERATION MODE AND CLOCK TRANSITION SIGNAL OUT
Operation Mode
DIR9001
SLES198 – DECEMBER 2006
The DIR9001 has the following three operation modes.
These modes are selected by the connection of the CKSEL pin.•PLL MODE: For demodulating a biphase input signal; always outputs PLL source clock•XTI MODE: For clock generator; always outputs XTI source clock•AUTO MODE: Automatic clock source selection; output source depends on ERROR pin.
Notes about operation mode selection:•Normally, the PLL mode: CKSEL = L is selected to decode a biphase input signal.•The XTI mode is a mode that supplies the XTI source clock to peripheral devices (A/D converters, etc);therefore, recovered clock and decoded data is not output.•When the XTI source is not used, an XTI source is not required. In this case, clocks are not output in the XTImode.
•At the time of XTI mode selection, biphase decode function continues to operate. Therefore, the biphaseinput status (ERROR) and the result of the sampling frequency calculator (a required XTI source foroperation), are always monitored. That is, the following output pins: ERROR, BFRAME, FSOUT[1:0], CLKST,AUDIO and EMPH are always enabled.
The details of these three modes are given in Table 2 .
Table 2. Operation Mode and Clock Source
OPERATION CKSEL PIN ERROR DOUT DATA AUDIO FSOUT BFRAME COUTSCKO, BCKO, LRCKOMODE SETTING PIN EMPH [1:0] UOUTCLOCK SOURCESTATUS
H PLL (VCO) free-running MUTE (Low) LOW HL LOW LOWclock
(1)PLL L
L PLL recovered clock Decoded data OUT OUT OUT OUTH XTI clock MUTE (Low) LOW HL LOW LOWXTI H
L XTI clock MUTE (Low) OUT OUT OUT LOWH XTI clock MUTE (Low) LOW HL LOW LOWConnected toAUTO
ERROR pin
L PLL recovered clock Decoded data OUT OUT OUT OUT
(1) The VCO free-running frequency is not a constant frequency, because the VCO oscillation frequency is dependent on supply voltage,temperature, and process variations.
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Clock and Data Recovery
SCKO
BCKO
LRCKO
DOUT
RXIN
Divider
FILT XTO
XTI
FSOUT0
FSOUT1
OSC
CLKST
VCO
CKSEL
DGND
ERROR
PLL
Divider
Decoder
Preamble
Detector
Charge
Pump
Clock
Decoder
Biphase
Data Decoder
Serial
AudioData
Formatter
ERROR
Detector
AudioData
MUTE Control
Sampling
Frequency
Calculator
Clock Transition Signal Out
DIR9001
SLES198 – DECEMBER 2006
Figure 5. Clock Source, Source Selector, and Data Path
The DIR9001 provides an output pulse that is synchronized with the PLL’s LOCK/UNLOCK status change.
The CLKST pin outputs the PLL status change between LOCK and UNLOCK. The CLKST output pulse dependsonly on the status change of the PLL.
This clock change/transition signal is output through CLKST.
As this signal indicates a clock transition period due to a PLL status change, it can be used for muting or otherappropriate functions in an application.
A clock source selection caused by the CLKSEL pin does not affect the output of CLKST.
CLKST does change due to PLL status change even if CKSEL = H in the XTI source mode.
When DIR9001 is reset in the state where it is locked to the biphase input signal, the pulse signal of CLKST isnot output. That is, the priority of reset is higher than CLKST.
The relation among the lock-in/unlock process, the CLKST and ERROR outputs, the output clocks (SCKO,BCKO, LRCKO), and data (DOUT) is shown in Figure 6 .
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DIR9001
SLES198 – DECEMBER 2006
PARAMETERS MIN TYP MAX UNIT
t
CLKST
CLKST pulse duration, high 4 20 µs
Figure 6. Lock-In and Unlock Process
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CLOCK DESCRIPTION
System Clock Source
DIR9001
SLES198 – DECEMBER 2006
DIR9001 has the following two clock sources for the system clock.•PLL source (128 f
S
, 256 f
S
, 384 f
S
, 512 f
S
are available, recovered by built-in PLL)•XTI source (One 24.576-MHz resonator or external clock source is required.)
Two clock sources are used for the following purpose.•PLL source: Recovered system clock from the biphase input signal•XTI source: Clock source for peripheral devices (for example, A/D converter, microcontroller, etc.)Measurement reference clock for the internal actual-sampling-frequency calculator
Description of PLL clock source•The PLL clock source is the output clock of built-in PLL (including VCO).•The PLL clock source frequency is selectable from 128 f
S
, 256 f
S
, 384 f
S
, 512 f
S
by PSCK[1:0].•When the PLL is in the locked condition, the PLL clock source is the clock recovered from the biphase inputsignal.
•When PLL is in the unlocked condition, the PLL clock source is the built-in free-running clock of the VCO.•The frequency of the PLL clock source in the unlocked condition is not constant.(The VCO free-running frequency is dependent on supply voltage, temperature, and variations in the die’swafer.)
Description of XTI clock source•The XTI clock source is not used to recover the clock and decode data from the biphase input signal.•Therefore, if the DIR9001 is used only for recovering the clock and decoding data from the biphase inputsignal, an XTI clock source is not required. In this case, the XTI pin must be connected to the DGND pin.(The DIR9001 does not have a selection pin for using an XTI clock source or not using one.)
The selection method of clock source•The output clock is selected from two clock sources by the level of the CKSEL pin.•The selection of the system clock source depends only on the input level of CKSEL pin.•CKSEL = L setting is required for recovering the clock and decoding data from biphase input.•CKSEL = H setting is required for XTI clock source output.•The continuity of clock during the clock source transition between the XTI source and the PLL source is notassured.
Method of automatic clock source selection (CLOCK SOURCE MODE: AUTO)•This method enables selection of the clock source automatically, using the DIR9001 ERROR status. The PLLsource clock is output when ERROR = L; the XTI source is output when ERROR = H.•To enable automatic clock source selection, the CKSEL pin must be connected to the ERROR pin.•If XTI clock source is needed during the ERROR period, this method is recommended.•Because the clock source during ERROR status is XTI, if an XTI clock source is not provided to the XTI pin,then SCKO, BCKO, and LRCKO are not output during the ERROR period.
The relationship between the clock/data source and the combination of CKSEL pin and PLL status inputs isshown in Table 2 .
The clock tree system is shown in Figure 7 .
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SCKO (O)
BCKO (O)
LRCKO (O)
XTI (I)
XTO (O)
VCO
RXIN Built-in PLL
Clock Recovery 1/N
1/N
PLL Clock Source
1/N
1/4
1/64
XTI Clock Source
CKSEL (I)
Oscillation Amplifier ClockSource
Selector
[PSCK1]
[PSCK0]
PLL Clock Source (Built-In PLL and VCO) Description
DIR9001
SLES198 – DECEMBER 2006
Figure 7. Clock Tree Diagram
The DIR9001 has on-chip PLL (including VCO) for recovering the clock from the biphase input signal.
The clock that is output from the built-in VCO is defined as the PLL clock source.
In the locked state, the built-in PLL generates a system clock that synchronizes with the biphase input signal.
In the unlocked state, the built-in PLL (VCO) generates a free-running clock. (The frequency is not constant.)
The PLL can support a system clock of 128 f
S
, 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the sampling frequency ofthe biphase input signal.
The system clock frequency of the PLL is selected by PSCK[1:0].
The DIR9001 can decode a biphase input signal through its 28 sampling-frequency range of kHz to 108 kHz,independent of the setting of PSCK[1:0].
Therefore, the DIR9001 can decode a biphase input signal with a sampling frequency from 28 kHz to 108 kHz atall settings of PSCK[1:0]
The relationship between the PSCK[1:0] selection and the output clock (SCKO, BCKO, LRCKO) from the PLLsource is shown in Table 3 .
Table 3. SCKO, BCKO, and LRCKO Frequencies Set by PSCK[1:0]
PSCK[1:0] SETTING OUTPUT CLOCK FROM PLL SOURCE
PSCK1 PSCK0 SCKO BCKO LRCKO
L L 128 f
S
64 f
S
f
S
L H 256 f
S
64 f
S
f
S
H L 384 f
S
64 f
S
f
S
H H 512 f
S
64 f
S
f
S
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Required PLL Loop Filter Description
DIR9001
PLL Section
Charge
Pump VCO
FILT AGND DGND
C2
R1 C1
DIR9001
SLES198 – DECEMBER 2006
In PLL mode (CKSEL = L), output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock.
The relationship between frequencies of LRCKO, BCKO, and SCKO at different sampling frequencies f
S
of thebiphase input signal are shown in Table 4 .
Table 4. Output Clock Frequency in PLL Locked State (CKSEL = L)
LRCKO BCKO SCKO (Depending on PSCK[1:0] Setting)
f
S
64 f
S
128 f
S
256 f
S
384 f
S
512 f
S
32 kHz 2.048 MHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz44.1 kHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz48 kHz 3.072 MHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz88.2 kHz 5.6448 MHz 11.2896 MHz 22.5792 MHz 33.8688 MHz 45.1584 MHz96 kHz 6.144 MHz 12.288 MHz 24.576 MHz 36.864 MHz 49.152 MHz
The DIR9001 incorporates a PLL for generating a clock synchronized with the biphase input signal.
The built-in PLL requires an external loop filter, which is specified as follows.
Operation and performance is assured for recommended filter components R1, C1, and C2.
Notes about Loop Filter Components and Layout•The resistor and capacitors which comprise the filter should be located and routed as close as possible to theDIR9001.
•A carbon film resistor or metal film resistor, with tolerance less than 5%, is recommended.•Film capacitors, with tolerance is less than 5%, is recommended.•If ceramic capacitors are used for C1 and C2, parts with a low voltage coefficient and low temperaturecoefficient, such as CH or C0G, are recommended.•The external loop filter must be placed on FILT pins.•The GND node of the external loop filter must be directly connected with the AGND pin of the DIR9001; itmust be not combined with other signals.
The configuration of external loop filter and the connection with the DIR9001 is shown in Figure 8 .
Figure 8. Loop Filter Connection
The recommended values of loop filter components is shown in Table 5 .
Table 5. Recommended Value of Loop Filter Components
REF. NO. RECOMMENDED VALUE PARTS TYPE TOLERANCE
R1 680 ΩMetal film or carbon ≤5%C1 0.068 µF Film or ceramic (CH or C0G) ≤5%C2 0.0047 µF Film or ceramic (CH or C0G) ≤5%
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XTI Clock Source and Oscillation Amplifier Description
Resonator
XTI
Crystal
OSC
Circuit
24.576MHz
InternalClock
DIR9001
ResonatorConnection
XTO
CL1
CL2
Rd
External
Clock
MustBe
Open
XTI
XTO
Crystal
OSC
Circuit
24.576MHz
InternalClock
DIR9001
ExternalClockInputConnection
DIR9001
SLES198 – DECEMBER 2006
This clock, driven by the built-in oscillation amplifier or input into the XTI pin from an external clock, is defined asthe XTI source. A 24.576-MHz fundamental resonator or external 24.576-MHz clock is used as the XTI source.
The DIR9001 requires an XTI source for following purposes:•The measurement reference clock of actual-sampling-frequency calculator•The clock source for the XTI source mode (CKSEL = H setting)(That is, the DIR9001 does not require an XTI source if it is only decoding the biphase input signal.)
The XTI clock source is supplied in one of the following two ways; the details are described in Figure 9 .•Setting up an oscillation circuit by connecting a resonator with the built-in amplifier•Applying a clock from an external oscillator circuit or oscillator module
To set up an oscillation circuit by connecting a resonator with the built-in amplifier:•Connect a 24.576-MHz resonator between the XTI pin and XTO pin.•The resonator should be a fundamental-mode type.•A crystal resonator or ceramic resonator can be used.•The load capacitor C
L1
, C
L2
, and the current-limiting resistor R
d
depend on the characteristics of theresonator.
•No external feedback resistor between the XTI pin and XTO pin is required, as an appropriate resistor isincorporated in the device.•No load other than the resonator is allowed on the XTO pin.
To connect an external oscillator circuit or oscillator module:•Provide a 24.576-MHz clock on the XTI pin•Note that the XTI pin is not 5-V tolerant; it is simple CMOS input.•The XTO pin must be open.
Figure 9. XTI and XTO Connection Diagram
Description of oscillation amplifier operation:•The built-in oscillation amplifier is always working.•If the XTI source clock is not used, then the XTI pin must be connected to DGND.•For reducing power dissipation, it is recommended to not use the XTI source clock.
In XTI mode (CKSEL = H), output clocks (SCKO, BCKO, LRCKO) are generated from XTI source clock.
The relation between output clock frequency (SCKO, BCKO, LRCKO) and the XSCK pin setting in XTI sourcemode is shown in Table 6 .
Table 6. SCKO, BCKO, LRCKO Output Frequency at XTI Mode
XTI FREQUENCY OUTPUT CLOCK FREQUENCY IN XTI SOURCE MODE (CKSEL = H)
SCKO BCKO LRCKO
24.576 MHz 24.576 MHz 6.144 MHz 96 kHz
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DATA DESCRIPTION
Decoded Serial Audio Data Output and Interface Format
BiphaseSignal(IN)
tLATE
BFRAME(OUT)
LRCKO(OUT)
(I S)
2
LRCKO(OUT)
(ExceptI S)
2
DOUT (OUT)
BW M W
0L 0R 1L 1R
0L 0R 1L 1R
17BCK
DIR9001
SLES198 – DECEMBER 2006
The DIR9001 supports following 4-data formats for the decoded data.•16-bit, MSB-first, right-justified•24-bit, MSB-first, right-justified•24-bit, MSB-first, left-justified•24-bit, MSB-first, I
2
S
Decoded data is MSB first and 2s-complement in all formats.
The decoded data is provided through the DOUT pin.
The format of the decoded data is selected by the FMT[1:0] pins.
The data formats for each FMT[1:0] pin setting are shown in Table 7 .
Table 7. Serial Audio Data Output Format Set by FMT[1:0]
FMT[1:0] SETTINGS
DOUT SERIAL AUDIO DATA OUTPUT FORMATFMT1 FMT0
L L 16-bit, MSB-first, right-justifiedL H 24-bit, MSB-first, right-justifiedH L 24-bit MSB-first, left-justifiedH H 24-bit, MSB-first, I
2
S
PARAMETERS MIN TYP MAX UNIT
t
LATE
LRCKO/DOUT latency 3/f
S
s
Figure 10. Latency Time Between Biphase Input and LRCKO/DOUT
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Right Justified (MSB First, 24-bit, 16-bit)
22 23 24
DOUT
DOUT
LRCKO
BCKO
14 15 16
R-channel
L-channel
1/fS
MSB
2
1
LSB
15 16
MSB
21
LSB
23 24
MSB
21
LSB
15 16
MSB
21
LSB
23 24
Left Justified (MSB First)
DOUT
LRCKO
BCKO
R-channel
L-channel
1/fS
MSB
21
LSB
23 24
MSB
21
LSB
23 24
DOUT
LRCKO
BCKO
R-channelL-channel
1/fS
1
MSB LSB
21 23 24
MSB
21
LSB
23 24
DataLength:16-bit
DataLength:24-bit
DataLength:24-bit
DataLength:24-bit
I SFormat(MSBFirst)
2
DIR9001
SLES198 – DECEMBER 2006
The relationships among BCKO, LRCKO, and DOUT for each format are shown in Figure 11 .
Figure 11. Decoded Serial Audio Data Output Formats
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tBCH tBCL
tBCDO
tBCY
BCKO
(OUT)
LRCKO
(OUT)
DOUT
(OUT)
SCKO
(OUT) V /2
DD
tCKLR
tSCBC tSCY
V /2
DD
V /2
DD
V /2
DD
DIR9001
SLES198 – DECEMBER 2006
PARAMETERS MIN TYP MAX UNIT
t
SCY
System clock pulse cycle time 18 nst
SCBC
Delay time of SCK rising edge to BCK rising edge 4 8 15 nst
CKLR
Delay time of BCKO falling edge to LRCKO valid –5 0.5 0.5 nst
BCY
BCKO pulse cycle time 1/64f
S
st
BCH
BCKO pulse duration, HIGH 60 nst
BCL
BCKO pulse duration, LOW 60 nst
BCDO
Delay time of BCKO falling edge to DOUT valid –5 1 5 nst
r
Rising time of all signals 10 nst
f
Falling time of all signals 10 ns
NOTE: Load capacitance of the LRCKO, BCKO, and DOUT pins is 20 pF. DOUT, LRCKO, and BCKO are synchronized withSCKO.
Figure 12. Decoded Audio Data Output Timing
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Channel-Status Data and User Data Serial Outputs
UOUT
COUT
BFRAME
Recovered
LRCKO
(I S)
2
Recovered
LRCKO
(ExceptI S)
2
U0L U0RU191R U1L U1R U2L U2R
C0L C0RC191R C1L C1R C2L C2R
DOUT 0L 0R191R 1L 1R 2L 2R 3L
17BCK
Channel-Status Data Information Output Terminal
DIR9001
SLES198 – DECEMBER 2006
The DIR9001 can output channel-status data and user data synchronized with audio data from the biphase inputsignal.
Each output data has its own dedicated output pin.•Channel-status data (C, hereinafter) is output through COUT pin.•User data (U, hereinafter) is output through UOUT pin.
The C and U outputs are synchronized with LRCKO recovered from the biphase input signal.
The polarity of LRCKO recovered from the biphase input signal depends on FMT[1:0] setting.
For detecting the top of the block of channel-status data or user data, the BFRAME pin is provided.
The BFRAME pin outputs a high level for an 8-LRCK period if the preamble Bis detected in the receivedbiphase signal.
In processing these data by a microcontroller or register circuit, LRCKO is used as the data input clock, and theoutput pulse on the BFRAME pin is used as the top-of-block signal.
The relationship among LRCKO, BFRAME, DOUT, COUT, and UOUT is shown in Figure 13 .
When in the XTI mode and the PLL-locked state, COUT and UOUT output L.
NOTE: The numbers 0 through 191 of DOUT, COUT, and UOUT indicate frame numbers of the biphase input.
Figure 13. LRCKO, DOUT, BFRAME, COUT, UOUT Output Timing
The DIR9001 can output part of the channel-status information (bit 1, bit 3) through two dedicated pins, AUDIOand EMPH.
The channel-status information which can be output from dedicated pins is limited to information from theL-channel.
If channel-status information other than AUDIO or EMPH is required, or information from the R-channel, then thechannel-status data on the COUT pin, which is synchronized with biphase input signal, can be used.
These outputs are synchronized with the top of block.
The information that can be output through the dedicated pins is shown as follows.
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AUDIO Pin
EMPH Pin
LRCKO
(ExceptI S)
2
AUDIO
LRCKO
(I S)
2
DOUT 0L
Bit1ofPreviousBlock
191R 1L 1R 2L 2R 3L
EMPH Bit 3ofPreviousBlock
0R
DIR9001
SLES198 – DECEMBER 2006
This is the output pin for the audio sample word information of the channel-status data bit 1.
Table 8. Audio Sample Word Information
AUDIO DESCRIPTION
L Audio sample word represents linear PCM samples.H Audio sample word is used for other purposes.
This is the output pin for the emphasis information of the channel-status data bit 3.
Table 9. Pre-Emphasis Information
EMPH DESCRIPTION
L Two audio channels without pre-emphasisH Two audio channels with 50 µs / 15 µs pre-emphasis
NOTE: The numbers 0 through 191 of DOUT indicate frame numbers of the biphase input.
Figure 14. AUDIO and EMPH Output Timing
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ERRORS AND ERROR PROCESSING
Error Output Description
ERROR Output
DIR9001
DetectedParityError
DataError
Parity Error Processing
DIR9001
SLES198 – DECEMBER 2006
Error detection and data error processing for PLL errors•PLL responds with unlock for data in which the rule of biphase encoding is lost (biphase error andframe-length error).•PLL responds with unlock for data in which the preamble B, M, W can not be detected.
Error processing function and error output pins•The DIR9001 has a data error detect function and an error output pin, ERROR.•The ERROR pin is defined as the logical OR of data error and parity error detection.•The ERROR rising edge is synchronized with CLKST.•The ERROR falling edge is synchronized with LRCK.
The relationship between data error and detected parity error is shown in Figure 15 .
Figure 15. ERROR Output
The state of the ERROR pin and the details of error are shown in Table 10 .
Table 10. State of ERROR Output Pin
ERROR DESCRIPTION
L Lock state of PLL and nondetection of parity errorH Unlock state of PLL or detection of parity error
Error detection and error processing for parity errors•For PCM data, interpolation processing by previous data is performed.•For non-PCM data, interpolation is not performed and data is directly output with no processing. (Non-PCMdata is data with channel-status data bit 1 = 1.)
The processing for parity error occurrence is shown in Figure 16 .
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AUDIO
InternalLOCK
Ln
LRCKO(I2S)
MUTE(Low)
ERROR
DOUT
ParityError
InterpolationProcessing
byPreviousData
AUDIO
InternalLOCK
LRCKO(I2S)
ERROR
DOUT
ParityError
[ =L]AUDIO
[ =H]AUDIO
RnLn+1 Rn+1 Ln+1 Rn+2 Rn+3
Ln+3
Ln
MUTE(Low) RnLn+1 Rn+1 Ln+2 Rn+2 Rn+3
Ln+3
Other Error
DIR9001
SLES198 – DECEMBER 2006
Figure 16. Processing for Parity Error Occurrence
Error for sampling frequency change: A rapid continuous change or a discontinuous change of the inputsampling frequency causes the PLL to lose lock.
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CALCULATION OF ACTUAL SAMPLING FREQUENCY
DIR9001
SLES198 – DECEMBER 2006
The DIR9001 calculates the actual sampling frequency of the biphase input signal and outputs its result throughdedicated pins.
To use this function, a 24.576-MHz clock source must be supplied to the XTI pin. The 24.576-MHz clock is usedas a measurement reference clock to calculate the actual sampling frequency.
If the XTI pin is connected to DGND, calculation of the actual sampling frequency is not performed.
If there is an error in the XTI clock frequency, the calculation result and range are shifted correspondingly.
This output is the result of calculating the sampling frequency, it is not the sampling frequency information of thechannel-status data (bit 24–bit 27).
The sampling frequency information of the channel-status data (bit 24–bit 27) is not output through these pins.
The calculation result is decoded into 2-bit data, which is output on the FSOUT[1:0] pins.
If the PLL is locked but the sampling frequency is out-of-range, or if the PLL is unlocked, FSOUT[1:0] = HL isoutput to indicate an abnormality.
When the XTI source clock is not supplied before power on, FSOUT [1:0] always outputs LL.
When the XTI source clock is stopped, the f
S
calculator holds the last value of the f
S
calculator result.
If XTI source clock is supplied, the f
S
calculator resumes operation.
The calculated value is held until reset.
The relationship between the FSOUT[1:0] outputs and the range of sampling frequencies is shown in Table 11 .
Table 11. Calculated Sampling Frequency Output
NOMINAL f
S
ACTUAL SAMPLING FREQUENCY CALCULATED SAMPLING FREQUENCY OUTPUTRANGE
FSOUT1 FSOUT0
Out of range Out of range or PLL unlocked H L32 kHz 31.2 kHz–32.8 kHz H H44.1 kHz 43 kHz–45.2 kHz L L48 kHz 46.8 kHz–49.2 kHz L H
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TYPICAL CIRCUIT CONNECTION
R2
AUDIO
Receiver Circuit
C5
3.3-V VDD +C7
+C8
C6
For Automatic Clock Source Selection
Reset (active LOW)
11
12
10
9
8
7
6
5
4
3
2
COUT
DOUT
UOUT
EMPH
BFRAME
RST
RSV
RXIN
CKSEL
FILT
DGND
PSCK1
PSCK0
FSOUT0
BCKO
LRCKO
CLKST
SCKO
FSOUT1
ERROR
1
15
16
17
18
19
20
21
22
23
24
13
14
XTI
XTO
AGND
FMT1
FMT0 25
26
27
28
To Microcontroller
R1
C4
Actual Sampling
Frequency Output
X1
C3
System Clock
FrequencySetting
384, 512f
(128, 256,
S)
Audio Data
Processor
DecodedData Format
Setting
3.3-V VCC
C1
C2
VDD VCC
DIR9001
SLES198 – DECEMBER 2006
Figure 17 illustrates typical circuit connection.
NOTES: R
1
: Loop filter resistor, 680 ΩR
2
: Current-limiting resistor; generally, a 100 Ω–500 Ωresistor is used, but it depends on the crystal resonator.C
1
: Loop filter capacitor, 0.068 µF.C
2
: Loop filter capacitor, 0.0047 µF.C
3
, C
4
: OSC load capacitor; generally, a 10-pF–30-pF capacitor is used, but it depends on the crystal resonator andPCB layout.
C
5
, C
8
: 10- µF electrolytic capacitor typical, depending on power-supply quality and PCB layout.C
6
, C
7
: 0.1- µF ceramic capacitor typical, depending on power-supply quality and PCB layout.X
1
: Crystal resonator, use a 24.576-MHz fundamental resonator when XTI clock source is needed.
Figure 17. Typical Circuit Connection Diagram
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APPLICATION INFORMATION
Differences for DIR1703
DIR9001
SLES198 – DECEMBER 2006
The DIR9001 has many improved functions compared to the DIR1703.
The DIR9001 functions are similar to those of the DIR1703.
The DIR9001 pin assignment is equivalent to that of the DIR1703.
The DIR9001 biphase input signal decoding function is almost equivalent to that of the DIR1703.
The differences between the DIR9001 and DIR1703 are shown in Table 12 .
Table 12. Main Differences Between DIR1703 and DIR9001
DIFFERENCE DIR1703 DIR9001
Operational supply-voltage range 3 V to 3.6 V 2.7 V to 3.6 VOperation temperature range –25 °C to 85 °C –40 °C to 85 °CPackage SSOP-28P, pin pitch: 0.65 mm TSSOP-28P, pin pitch: 0.65 mmClock recovery architecture SpAct™ feature Conventional PLLIEC60958-3 jitter tolerance Not compliant CompliantIEC60958 sampling frequency accuracy Level II ( ±1000 ppm) Level III ( ±12.5%)Acceptable sampling frequency 32/44.1/48/88.2/96 kHz, ±1500 ppm 28 kHz to 108 kHz continuousBiphase input signal level CMOS level 5-V tolerant TTL levelConnection of loop filter Between FILT pin and VCC Between FILT pin and AGNDXTI source clock frequency One of the following clock sources or Optional 24.576-MHz (24.576-MHz clock isresonators must be connected to the XTI pin: only required to use the internal4.069/5.6448/6.144/ 8.192/11.2896/12.288/ actual-sampling-frequency calculator or use16.384/16.9344/18.432/ 22.5792/24.576-MHz the DIR9001 as a 24.576-MHz clockgenerator.)BFRAME H period 32/f
S
8/f
S
Channel status and user data Synchronous with LRCK transition 17-BCK delay from LRCK transitionLatest tracked frequency hold Available Not availablePLL mode clock at error Latest tracked frequency VCO free-running frequencyClock transition signal out CKTRNS pin, active H CLKST pin, active-highOscillation amplifier External feedback resistor (typ. 1 M Ω) Internal feedback resistor
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DIR9001
SLES198 – DECEMBER 2006
The differences between the DIR1703 and DIR9001 I/O pins are shown in Table 13 .
Table 13. The Differences Between DIR1703 and DIR9001 in All I/O Pin
PIN NO. DIR1703 DIR9001 DIFFERENCES DESCRIPTIONS OF DIR9001
1 ADFLG AUDIO Pin name only Channel-status data information of non-audio sample word, active-low2 BRATE0 FSOUT0 Pin name only Actual-sampling-frequency calculated result output 03 BRATE1 FSOUT1 Pin name only Actual-sampling-frequency calculated result output 14 SCKO SCKO Same function System clock output5 V
DD
V
DD
Same function Digital power supply, 3.3-V6 DGND DGND Same function Digital ground7 XTO XTO Same function Oscillation amplifier output8 XTI XTI Same function Oscillation amplifier input, or external XTI source clock input9 CKTRNS CLKST CLKST is active-high Clock change/transition signal output10 LRCKO LRCKO Same function Audio data latch enable output11 BCKO BCKO Same function Audio data bit clock output12 DOUT DOUT Same function 16 bit–24 bit decoded serial digital audio data output13 SCF0 PSCK0 Pin name only SCKO output frequency selection 014 SCF1 PSCK1 Pin name only SCKO output frequency selection 115 CSBIT COUT Pin name only Channel-status data serial output synchronized with LRCKO16 URBIT UOUT Pin name only User data serial output synchronized with LRCKO17 EMFLG EMPH Pin name only Channel-status data Information of pre-emphasis (50 µs/15 µs)18 BFRAME BFRAME Same function Indication of top block of biphase input signal19 BRSEL RSV Reserved Reserved, must be connected to DGND20 DIN RXIN Pin name only Biphase digital data input21 RST RST Same function Reset control input, active-low22 FILT FILT Same function External filter connection terminal. Recommended filter must beconnected.23 AGND AGND Same function Analog ground24 V
CC
V
CC
Same function Analog power supply, 3.3-V25 FMT0 FMT0 Same function Decoded serial digital audio data output format selection 026 FMT1 FMT1 Same function Decoded serial digital audio data output format selection 127 UNLOCK ERROR Pin name only Indication of internal PLL or data parity error28 CKSEL CKSEL Same function Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DIR9001PW ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DIR9001PWG4 ACTIVE TSSOP PW 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DIR9001PWR ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DIR9001PWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DIR9001 :
•Automotive: DIR9001-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 3-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DIR9001PWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DIR9001PWR TSSOP PW 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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