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ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FDB0260N1007L N-Channel PowerTrench(R) MOSFET 100 V, 200 A, 2.6 m Features General Description This N-Channel MOSFET is produced using Fairchild Semiconductor's advance PowerTrench(R) process that has been especially tailored to minimize the on-state resistance while maintaining superior ruggedness and switching performance for industrial applications. Max rDS(on) = 2.6 m at VGS = 10 V, ID = 27 A Fast Switching Speed Low Gate Charge High Performance Trench Technology for Extremely Low RDS(on) Applications High Power and Current Handling Capability Industrial Motor Drive RoHS Compliant Industrial Power Supply Industrial Automation Battery Operated tools Battery Protection Solar Inverters UPS and Energy Inverters Energy Storage Load Switch D(Pin4, tab) 4 12 3 56 7 1. Gate 2. Source/Kelvin Sense 3. Source/Kelvin Sense 4. Drain 5. Source 6. Source 7. Source G (Pin1) D2-PAK (TO263) S(Pin2,3,5,6,7) MOSFET Maximum Ratings TC = 25 C unless otherwise noted. Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous -Continuous ID PD TJ, TSTG Units V 20 V TC = 25C (Note 5) TC = 100C (Note 5) 140 (Note 4) 1100 -Pulsed EAS Ratings 100 Single Pulse Avalanche Energy (Note 3) Power Dissipation TC = 25C Power Dissipation TA = 25C 200 912 250 (Note 1a) Operating and Storage Junction Temperature Range 3.8 -55 to +175 A mJ W C Thermal Characteristics RJC Thermal Resistance, Junction to Case RJA Thermal Resistance, Junction to Ambient (Note 1) 0.6 (Note 1a) 40 C/W Package Marking and Ordering Information Device Marking FDB0260N1007L Device FDB0260N1007L (c)2015 Fairchild Semiconductor Corporation FDB0260N1007L Rev.C3 Package D2-PAK-7L 1 Reel Size 330 mm Tape Width 24 mm Quantity 800 units www.fairchildsemi.com FDB0260N1007L N-Channel PowerTrench(R) MOSFET March 2016 Symbol Parameter Test Conditions Min. Typ. Max. Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 A, VGS = 0 V BVDSS TJ Breakdown Voltage Temperature Coefficient ID = 250 A, referenced to 25 C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 A IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 4 V 100 V 53 mV/C On Characteristics (Note 2) VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 A VGS(th) TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 A, referenced to 25 C rDS(on) Static Drain to Source On Resistance gFS Forward Transconductance 2 2.8 -13 mV/C VGS = 10 V, ID = 27 A 2.3 2.6 VGS = 10 V, ID = 27 A, TJ= 150C 4.5 6.6 VDS = 10 V, ID = 27 A 59 m S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 50 V, VGS = 0 V, f = 1 MHz 6101 8545 pF 1343 1885 pF 46 65 pF 2.7 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain "Miller" Charge VDD = 50 V, ID = 27 A, VGS = 10 V, RGEN = 6 VDD = 50 V, ID = 27 A, VGS = 10 V 30 48 ns 29 46 ns 51 81 ns 19 34 ns 84 118 nC 25 nC 17 nC Drain-Source Diode Characteristics IS Maximum Continuous Drain to Source Diode Forward Current 200 A ISM Maximum Pulsed Drain to Source Diode Forward Current 1100 A VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 27 A (Note 2) IF = 27 A, di/dt = 100 A/s 0.8 1.2 V 75 120 ns 97 155 nC Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. a) 40 C/W when mounted on a 1 in2 pad of 2 oz copper. b) 62.5 C/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0 %. 3. EAS of 912 is based on starting TJ = 25 C, L = 0.3 mH, IAS = 78 A, VDD = 10 V, VGS = 90 V. 100% test at L = 0.1 mH, IAS = 113 A. 4. Pulsed Id please refer to Figure "Forward Bias Safe Operating Area" for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. (c)2015 Fairchild Semiconductor Corporation FDB0260N1007L Rev.C3 2 www.fairchildsemi.com FDB0260N1007L N-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25 C unless otherwise noted. 3 VGS = 10 V VGS = 8 V VGS = 7 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 300 200 VGS = 6.5 V VGS = 6 V 100 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 0 0.0 0.5 1.0 1.5 2.0 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX VGS = 6 V 2 VGS = 6.5 V 1 0 2.5 0 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 200 300 Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 20 ID = 27 A VGS = 10 V rDS(on), DRAIN TO 2.0 1.8 1.6 1.4 1.2 1.0 0.8 SOURCE ON-RESISTANCE (m) 2.4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics 2.2 VGS = 8 V VGS = 7 V PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 15 ID = 27 A 10 TJ = 150 oC 5 TJ = 25 oC 0.6 -75 -50 -25 0 25 50 75 100 125 150 175 TJ, JUNCTION TEMPERATURE (oC) 0 Figure 3. Normalized On Resistance vs. Junction Temperature Figure 4. On-Resistance vs. Gate to Source Voltage IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VDS = 5 V 200 TJ = 175 oC 100 TJ = 25 oC TJ = -55 oC 2 3 4 5 6 300 100 6 7 8 9 10 VGS = 0 V 10 TJ = 175 oC 1 0.1 TJ = 25 oC 0.01 TJ = -55 oC 0.001 0.0 7 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics (c)2015 Fairchild Semiconductor Corporation FDB0260N1007L Rev.C3 5 VGS, GATE TO SOURCE VOLTAGE (V) 300 0 4 Figure 6. Source to Drain Diode Forward Voltage vs. Source Current 3 www.fairchildsemi.com FDB0260N1007L N-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted. 50000 VGS, GATE TO SOURCE VOLTAGE (V) 10 ID = 27 A VDD = 25 V CAPACITANCE (pF) VDD = 50 V 6 VDD = 75 V 4 2 0 Ciss 10000 8 0 20 40 60 80 Coss 1000 Crss 100 f = 1 MHz VGS = 0 V 10 0.1 100 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs. Drain to Source Voltage 2000 1000 ID, DRAIN CURRENT (A) 1000 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 100 TJ = 25 oC TJ = 150 oC 10 10 s 100 10 1 THIS AREA IS LIMITED BY rDS(on) 100 s SINGLE PULSE TJ = MAX RATED 1 ms o 1 0.001 0.01 0.1 1 10 100 0.1 0.1 1000 10000 10 ms 100 ms/DC RJC = 0.6 C/W TC = 25 oC CURVE BENT TO MEASURED DATA 1 tAV, TIME IN AVALANCHE (ms) 10 100 1000 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 10. Forward Bias Safe Operating Area Figure 9. Unclamped Inductive Switching Capability 5 P(PK), PEAK TRANSIENT POWER (W) 10 SINGLE PULSE o RJC = 0.6 C/W o TC = 25 C 4 10 3 10 2 10 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, PULSE WIDTH (sec) Figure 11. Single Pulse Maximum Power Dissipation (c)2015 Fairchild Semiconductor Corporation FDB0260N1007L Rev.C3 4 www.fairchildsemi.com FDB0260N1007L N-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 -1 10 PDM t1 t2 -2 NOTES: 10 ZJC(t) = r(t) x RJC RJC = 0.6 oC/W Peak TJ = PDM x ZJC(t) + TC Duty Cycle, D = t1 / t2 SINGLE PULSE -3 10 -5 -4 10 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Case Transient Thermal Response Curve (c)2015 Fairchild Semiconductor Corporation FDB0260N1007L Rev.C3 5 www.fairchildsemi.com FDB0260N1007L N-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted. 10.20 9.70 A 1.40 1.00 10.50 8.40 9.40 9.00 10.20 1.40 MAX C 3.45 0.73 1 7 0.95 0.90 0.70 (1.27) 6X 1.27 6X 7.62 0.70 C 0.50 LAND PATTERN RECOMMENDATION 0.25 A M 7.62 B 8.78 8.38 1.40 1.20 4.70 4.30 7.70 MIN 8 C 1 7 0.60 0.40 0.254 0.20 MAX GAGE PLANE NOTES: C OUT OF JEDEC STANDARD VALUE. D. DIMENSION AND TOLERANCE AS PER ASME Y14.5-1994. E. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS. F. LAND PATTERN RECOMMENDATION PER IPC. TO127P1524X465-8N. G. DRAWING FILE NAME: TO263A07REV5. 5.20 4.80 R0.50 2.84 2.44 A A. PACKAGE CONFORMS TO JEDEC TO-263 VARIATION CB EXCEPT WHERE NOTED. B. ALL DIMENSIONS ARE IN MILLIMETERS. SEATING PLANE C 15.70 15.10 0.20 B 0 - 8 DETAIL A SCALE 2:1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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