Product Folder Order Now Technical Documents Support & Community Tools & Software LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 LMH6574 4:1 High Speed Video Multiplexer 1 Features * * * * * * * * 1 * * 3 Description 500 MHz, 500 mV -3 dB Bandwidth, AV = 2 400 MHz, 2 VPP -3 dB Bandwidth, AV = 2 8 ns Channel Switching Time 70 dB Channel to Channel Isolation at 10 MHz 0.02%, 0.05 Diff. Gain, Phase 0.1 dB Gain Flatness to 150 MHz 2200 V/s Slew Rate Wide Supply Voltage Range: 6 V (3 V) to 12 V (6 V) -68 dB HD2 at 5 MHz -84 dB HD3 at 5 MHz 2 Applications * * * * * * Video Router Multi Input Video Monitor Instrumentation / Test Equipment Receiver IF Diversity Switch Multi Channel A/D Driver Picture in Picture Video Switch The LMH6574 is a high-performance analog multiplexer optimized for professional grade video and other high fidelity high bandwidth analog applications. The output amplifier selects any one of four buffered input signals based on the state of the two address bits. The LMH6574 provides a 400-MHz bandwidth at 2 VPP output signal levels. Multimedia and high definition television (HDTV) applications can benefit from the LMH6574 0.1 dB bandwidth of 150 MHz and its 2200 V/s slew rate. The LMH6574 supports composite video applications with its 0.02% and 0.05 differential gain and phase errors for NTSC and PAL video signals while driving a single, back terminated 75- load. An 80-mA linear output current is available for driving multiple video load applications. The LMH6574 gain is set by external feedback and gain set resistors for maximum flexibility. The LMH6574 is available in the 14-pin SOIC package. Device Information(1) PART NUMBER PACKAGE LMH6574 SOIC (14) BODY SIZE (NOM) 8.65 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Frequency Response vs Gain Frequency Response vs VOUT 1 1 0 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) -1 -1 VOUT = 0.5 VPP -2 VOUT = 1 VPP -3 -4 VOUT = 2 VPP -5 -6 VOUT = 4 VPP -7 -8 -4 AV = 6, RF = 300: -5 AV = 10, RF = 180: -6 -7 VS = 5V VOUT = 2 VPP -9 AV = 2V/V 10 -9 10 AV = 2, RF = 575: -3 -8 VS = 5V AV = 1, RF = 1.5 k: -2 100 1000 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics 5 V ................................. Electrical Characteristics 3.3 V .............................. Typical Characteristics .............................................. Detailed Description ............................................ 13 7.1 Functional Block Diagram ....................................... 13 7.2 Feature Description................................................. 13 7.3 Device Functional Modes........................................ 16 8 Application and Implementation ........................ 17 9 Power Supply Recommendations...................... 21 8.1 Application Information............................................ 17 9.1 Power Dissipation ................................................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (December 2014) to Revision E Page * Changed IBN parameter maximum specifications from 5 A to 5.2 A and from 5.6 A to 5.8 A .............................. 5 * Changed PSRR parameter minimum specifications from 47 dB to 43 dB and from 45 dB to 41 dB .................................... 5 * Changed Supply Current Disabled parameter maximum specifications from 5.8 mA to 6.2 mA and from 5.9 mA to 6.3 mA .................................................................................................................................................................................... 6 * Changed IiL parameter minimum specifications from -2.9 A to -3.3 A and from -8.5 A to -9 A ................................. 6 * Added Feature Description and Device Functional Modes sections .................................................................................... 13 Changes from Revision C (November 2012) to Revision D Page * Added, updated, or revised the following sections: Pin Configuration and Functions, Specifications, Application and Implementation, Power Supply Recommendations , Layout , Device and Documentation Support , and Mechanical, Packaging, and Orderable Information................................................................................................................................... 1 * Revised text in Application and Implementation section, formerly titled "Application Notes"............................................... 17 * Revised text in Multiplexer Expansion section. Added Figure 31, Figure 32, and Figure 33 .............................................. 17 2 Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 5 Pin Configuration and Functions 14-Pin SOIC Package D (Top View) 14 V+ 13 OUT 3 12 FB GND 4 11 SD IN2 5 10 EN V- 6 9 A1 IN3 7 8 A0 IN0 1 GND 2 IN1 + - Pin Functions PIN NO. NAME I/O DESCRIPTION 1 IN0 I 2 GND -- Input Channel 0 3 IN1 I 4 GND -- 5 IN2 I Input Channel 2 6 V- I V- Supply 7 IN3 I Input Channel 3 8 A0 I Select Pin A0 9 A1 I Select Pin A1 10 EN I Enable 11 SD I Shutdown 12 FB I Feedback 13 OUT O Output 14 V+ I V+ Supply Ground Input Channel 1 Ground Truth Table A1 A0 EN SD OUT 1 1 0 0 CH 3 1 0 0 0 CH2 0 1 0 0 CH1 0 0 0 0 CH 0 X X 1 0 Disable X X X 1 Shutdown Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 3 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MIN MAX UNIT Supply Voltage (V+ - V-) 13.2 V IOUT (3) 130 mA (VS+0.6) V Signal & Logic Input Pin Current 20 mA Maximum Junction Temperature +150 C +150 C Signal & Logic Input Pin Voltage -65 Storage Temperature (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics 5 V tables If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be allowed to exceed 150C). See the Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less. 6.2 ESD Ratings VALUE Electrostatic discharge (1) V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) 2000 Machine model (MM) 200 UNIT V Human Body model, 1.5 k in series with 100 pF. Machine model, 0 In series with 200 pF. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as 200 V may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN Operating Temperature Supply Voltage (1) NOM MAX UNIT -40 85 C 6 12 V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics 5 V tables 6.4 Thermal Information THERMAL METRIC (1) D 14 PINS UNIT RJA Junction-to-ambient thermal resistance 130 C/W RJC(top) Junction-to-case (top) thermal resistance 40 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 6.5 Electrical Characteristics 5 V VS = 5 V, RL = 100 , AV = 2 V/V, RF = 575 , TJ = 25 C, unless otherwise specified. TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT FREQUENCY DOMAIN PERFORMANCE SSBW -3 dB Bandwidth VOUT = 0.5 VPP 500 MHz LSBW -3 dB Bandwidth VOUT = 2 VPP 400 MHz .1 dBBW 0. 1 dB Bandwidth VOUT = 0.25 VPP 150 MHz DG Differential Gain RL = 150 , f = 4.43 MHz 0.02% DP Differential Phase RL = 150 , f = 4.43 MHz 0.05 deg XTLK Channel to Channel Crosstalk All Hostile, 5 MHz -85 dB 8 ns TIME DOMAIN RESPONSE Channel to Channel Switching Time Logic Transition to 90% Output Enable and Disable Times Logic Transition to 90% or 10% Output 10 ns TRL Rise and Fall Time 4-V Step 2.4 ns TSS Settling Time to 0.05% 2-V Step 17 ns OS Overshoot 2-V Step 5% SR Slew Rate 4-V Step 2200 V/s TRS DISTORTION HD2 2nd Harmonic Distortion 2 VPP , 5 MHz -68 dBc HD3 3rd Harmonic Distortion 2 VPP , 5 MHz -84 dBc IMD 3rd Order Intermodulation Products 10 MHz, Two Tones 2 VPP at Output -80 dBc EQUIVALENT INPUT NOISE VN Voltage >1 MHz, Input Referred 5 nVHz ICN Current >1 MHz, Input Referred 5 pA/Hz STATIC, DC PERFORMANCE CHGM Channel to Channel Gain Difference VIO Input Offset Voltage (2) DVIO Offset Voltage Drift Input Bias Current (2) (3) IBN DIBN (1) (2) (3) 0.005% -40C TJ 85C VIN = 0 V 0.032% 0.035% 1 -40C TJ 85C 20 30 -3 VIN = 0 V -40C TJ 85C V/C 5.2 Power Supply Rejection DC, Input Referred Ratio (2) -7 -40C TJ 85C nA/C 10 13 43 -40C TJ 85C A 5.8 11 Pin 12, Feedback Point, VIN = 0 V mV 25 Bias Current Drift Inverting Input Bias Current PSRR DC, Difference in Gain Between Channels 54 41 dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application and Implementation for information on temperature de-rating of this device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted. Parameters guaranteed by electrical testing at 25C. Positive Value is current into device. Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 5 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Electrical Characteristics 5 V (continued) VS = 5 V, RL = 100 , AV = 2 V/V, RF = 575 , TJ = 25 C, unless otherwise specified. TEST CONDITIONS (1) PARAMETER ICC Supply Current (2) No Load Supply Current Disabled (2) ENABLE > 2 V Supply Current Shutdown SHUTDOWN > 2 V TYP MAX 13 16 -40C TJ 85C 18 4.7 -40C TJ 85C 1.8 Logic High Threshold (2) Select & Enable Pins (SD & EN) VIL (2) Select & Enable Pins (SD & EN) Logic Pin Input Current Low (3) Logic Input = 0 V Select & Enable Pins (SD & EN) -40C TJ 85C IiH Logic Pin Input Current High (3) Logic Input = 2.0 V, Select & Enable Pins (SD & EN) -40C TJ 85C 2.5 2.6 2.0 UNIT mA mA mA V 0.8 -3.3 IiL 6.2 6.3 -40C TJ 85C VIH Logic Low Threshold MIN -1 A -9 47 V 68 72.5 A MISCELLANEOUS PERFORMANCE RIN+ Input Resistance CIN Input Capacitance 5 k 0.8 ROUT Output Resistance pF Output Active, (EN and SD < 0.8 V) 0.04 ROUT Output Resistance Output Disabled, (EN or SD > 2 V) 3000 COUT Output Capacitance Output Disabled, (EN or SD > 2 V) 3.1 pF VO No Load Output Voltage Range RL = 100 VOL CMIR Input Voltage Range IO Linear Output Current (2) (3) 3.54 -40C TJ 85C 3.53 3.18 -40C TJ 85C 3.7 3.5 3.17 2.5 V V 2.6 V 80 mA 230 mA +60 ISC (4) 6 Short Circuit Current VIN = 0 V (4) -70 -40C TJ 85C +50 -40C TJ 85C -60 VIN = 2 V, Output Shorted to Ground The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be allowed to exceed 150C). See the Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less. Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 6.6 Electrical Characteristics 3.3 V VS = 3.3 V, RL = 100 , AV = 2 V/V, RF = 575 ; unless otherwise specified. PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT FREQUENCY DOMAIN PERFORMANCE SSBW -3 dB Bandwidth VOUT = 0.5 VPP 475 MHz LSBW -3 dB Bandwidth VOUT = 2.0 VPP 375 MHz 0.1 dBBW 0.1 dB Bandwidth VOUT = 0.5 VPP 100 MHz GFP Peaking DC to 200 MHz XTLK Channel to Channel Crosstalk All Hostile, f = 5 MHz 0.4 dB -85 dBc TIME DOMAIN RESPONSE TRL Rise and Fall Time 2-V Step 2 ns TSS Settling Time to 0.05% 2-V Step 20 ns OS Overshoot 2-V Step 5% SR Slew Rate 2-V Step 1400 V/s DISTORTION HD2 2nd Harmonic Distortion 2 VPP, 10 MHz -67 dBc HD3 3rd Harmonic Distortion 2 VPP, 10 MHz -87 dBc STATIC, DC PERFORMANCE VIO Input Offset Voltage VIN = 0 V -5 mV IBN Input Bias Current (2) VIN = 0 V -3 A PSRR Power Supply Rejection Ratio DC, Input Referred 49 dB ICC Supply Current No Load 12 mA VIH Logic High Threshold Select & Enable Pins (SD & EN) VIL Logic Low Threshold Select & Enable Pins (SD & EN) 1.3 V 0.4 V MISCELLANEOUS PERFORMANCE RIN+ Input Resistance CIN Input Capacitance ROUT Output Resistance VO VOL Output Voltage Range No Load RL = 100 CMIR Input Voltage Range IO Linear Output Current VIN = 0 V ISC Short Circuit Current VIN = 1 V, Output Shorted to Ground (1) (2) 5 k 0.8 pF 0.06 2 V 1.8 V 1.2 V 60 mA 150 mA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Application and Implementation for information on temperature de-rating of this device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted. Positive Value is current into device. Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 7 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com 6.7 Typical Characteristics VS = 5 V, RL = 100 , AV = 2, RF = RG = 575 , unless otherwise specified. 1 1 0 0 -1 VOUT = 0.5 VPP NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) -1 -2 VOUT = 1 VPP -3 -4 VOUT = 2 VPP -5 -6 VOUT = 4 VPP -7 VS = 5V -8 AV = 1, RF = 1.5 k: -2 AV = 2, RF = 575: -3 -4 AV = 6, RF = 300: -5 AV = 10, RF = 180: -6 -7 VS = 5V -8 AV = 2V/V -9 VOUT = 2 VPP -9 10 100 10 1000 100 FREQUENCY (MHz) Figure 1. Frequency Response vs VOUT Figure 2. Frequency Response vs Gain 90 2 CL = 8.6 pF, ROUT = 63: VS = 5V 80 LOAD = 1 k: || CL SUGGESTED ROUT (:) NORMALIZED GAIN (dB) 0 CL = 18 pF, ROUT = 48: -2 CL = 56 pF, ROUT = 24: -4 CL = 100 pF, ROUT = 19: -6 V OUT = 1 VPP CL || 1 k: -8 V = 5V S AV = 2 (V/V) -10 1 10 70 60 50 40 30 20 10 0 1 FREQUENCY (MHz) 10 100 CAPACTIVE LOAD (pF) Figure 3. Frequency Response vs Capacitive Load Figure 4. Suggested ROUT vs Capacitive Load 100 1000 2 1400 1.5 1200 1 OUTPUT (V) SUGGESTED VALUE OF RF (:) 1000 2.5 1600 1000 800 600 0.5 0 -0.5 -1 400 -1.5 200 VS = 5V -2 0 -2.5 1 8 1000 FREQUENCY (MHz) 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 GAIN (V/V) TIME (ns) Figure 5. Suggested Value of RF vs Gain Figure 6. Pulse Response 4VPP Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 Typical Characteristics (continued) VS = 5 V, RL = 100 , AV = 2, RF = RG = 575 , unless otherwise specified. 1.5 1.5 VS = 5V VS = 3.3V 0.5 0.5 VOUT (V) 1 VOUT (V) 1 0 0 -0.5 -0.5 -1 -1 -1.5 -1.5 5 0 10 15 20 25 30 5 0 10 TIME (ns) 15 20 25 30 TIME (ns) Figure 7. Pulse Response 2VPP Figure 8. Pulse Response 2VPP 10000 10000 DISABLED VS = 5V 100 |Z| (:) |Z| (:) DISABLED 1000 1000 VIN = 0V AV = 2V/V 100 VIN = 0V 10 10 1 0.1 AV = 1V/V 1 ENABLED 0.1 0.01 VS = 5V 1 10 100 ENABLED 0.1 0.01 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Closed Loop Output Impedance Figure 10. Closed Loop Output Impedance 0.75 60 PSRR + CHANNEL 1 0.25 PSRR - OUTPUT (V) PSRR (dB) 40 30 20 0 -0.25 CHANNEL 0 -0.5 3 2 10 ADDRESS LINE 0 (V) 0.5 50 1 ADDRESS LINE 0 0 0.1 0 1 10 100 1000 FREQUENCY (MHz) 0 10 20 30 40 50 60 70 80 TIME (ns) Figure 11. PSRR vs Frequency Figure 12. Channel Switching Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 9 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Typical Characteristics (continued) VS = 5 V, RL = 100 , AV = 2, RF = RG = 575 , unless otherwise specified. 0.5 0.25 0.25 VOUT AV = 2 -0.5 3 VOUT -0.25 OUTPUT (V) -0.25 SHUTDOWN (V) 0 0 VOUT (V) VIN = 0V -0.5 -0.75 6 2 4 SHUTDOWN 1 2 0 0 SHUTDOWN VOLTAGE (V) 0.5 SHUTDOWN 10 0 20 30 40 50 60 70 80 20 0 40 TIME (ns) 80 100 120 140 160 TIME (ns) Figure 13. SHUTDOWN Switching Figure 14. Shutdown Glitch 0.5 0.5 VIN = 0V 0.25 0.25 VOUT AV = 2 0 0 -0.5 3 -0.25 ENABLE (V) -0.25 OUTPUT (V) VOUT ENABLE (V) VOUT (V) 60 -0.5 6 2 4 ENABLE 1 2 0 0 ENABLE 10 0 20 30 40 50 60 70 80 20 0 TIME (ns) Figure 15. ENABLE Switching 80 100 120 140 160 Figure 16. Disable Glitch -40 VOUT = 2 VPP VOUT = 2 VPP CH3 -50 DISTORTION (dBc) -50 DISTORTION (dBc) 60 TIME (ns) -40 -60 CH2 -70 CH0 -80 CH1 -60 -70 HD3 ALL CHANNELS -80 -90 -90 -100 -100 1 10 40 10 100 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. HD2 vs Frequency Figure 18. HD3 vs Frequency Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 Typical Characteristics (continued) VS = 5 V, RL = 100 , AV = 2, RF = RG = 575 , unless otherwise specified. -60 -60 CH2 f = 5 MHz -65 -70 -70 DISTORTION (dBc) DISTORTION (dBc) CH3 -65 -75 -80 -85 CH1 CH0 -90 VOUT = 2 VPP -75 CH3 -80 -85 CH1 -90 CH2 f = 5 MHz VOUT = 2 VPP -95 -95 CH0 -100 -100 5 6 7 8 9 11 10 12 5 6 SUPPLY VOLTAGE (V) 7 8 9 11 10 12 SUPPLY VOLTAGE (V) Figure 19. HD2 vs VS Figure 20. HD3 vs VS -40 -30 f = 5 MHz f = 5 MHz -40 -50 DISTORTION (dBc) DISTORTION (dBc) CH3 CH2 -60 -70 -80 -50 -60 -70 -80 CH0 CH1 -90 -90 -100 -100 0 1 6 2 4 5 3 OUTPUT VOLTAGE (VPP) 7 8 0 Figure 21. HD2 vs VOUT 6 2 4 5 3 OUTPUT VOLTAGE (VPP) 7 8 Figure 22. HD3 vs VOUT 4 MAXIMUM OUTPUT VOLTAGE (V) -2.4 MINIMUM OUTPUT VOLTAGE (V) 1 -2.6 -2.8 -3 -3.2 -3.4 -3.6 -3.8 20 40 60 80 3.6 3.4 3.2 3 2.8 -100 -4 0 3.8 100 -80 -60 -40 -20 0 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Positive Value is current into device Positive Value is current into device Figure 23. Minimum VOUT vs IOUT Figure 24. Maximum VOUT vs IOUT Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 11 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Typical Characteristics (continued) VS = 5 V, RL = 100 , AV = 2, RF = RG = 575 , unless otherwise specified. -30 -30 SELECTED INPUT TO OUTPUT UNSELECTED INPUT TO -40 OUTPUT, VS = 5V -50 -60 -70 -80 -60 DISABLE -70 -80 -90 -90 -100 -100 -110 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) -110 0.01 SHUTDOWN 0.1 1 10 100 FREQUENCY (MHz) Figure 25. Crosstalk vs Frequency 12 VIN = 2 VPP -50 ISOLATION (dB) CROSSTALK (dBc) -40 Submit Documentation Feedback Figure 26. Off Isolation Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 7 Detailed Description 7.1 Functional Block Diagram + V A0 14 RT 8 IN 0 1 A1 RIN0 IN 1 9 3 + - RIN1 RT VOUT 13 IN 2 ROUT RF 12 5 RG IN 3 SD 11 RIN2 7 RT 10 RIN3 EN 2, 4 6 RT - V 7.2 Feature Description 7.2.1 Video Performance The LMH6574 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with backterminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. The Functional Block Diagram shows a typical configuration for driving a 75 cable. The output buffer is configured for a gain of 2, so using back terminated loads will give a net gain of 1. 7.2.2 Feedback Resistor Selection 1600 SUGGESTED VALUE OF RF (:) 1400 1200 1000 800 600 400 200 0 1 2 3 4 5 6 7 8 9 10 GAIN (V/V) Figure 27. Suggested RF vs Gain Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 13 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Feature Description (continued) The LMH6574 has a current feedback output buffer with gain determined by external feedback (RF) and gain set (RG) resistors. With current feedback amplifiers, the closed loop frequency response is a function of RF. For a gain of 2 V/V, the recommended value of RF is 575. For other gains see Figure 27. Generally, lowering RF from the recommended value will peak the frequency response and extend the bandwidth while increasing the value of RF will cause the frequency response to roll off faster. Reducing the value of RF too far below the recommended value will cause overshoot, ringing and, eventually, oscillation. Since all applications are slightly different it is worth some experimentation to find the optimal RF for a given circuit. For more information see Current Feedback Loop Gain Analysis and Performance Enhancement, Application Note OA-13 (SNOA366), which describes the relationship between RF and closed-loop frequency response for current feedback operational amplifiers. The impedance looking into pin 12 is approximately 20. This allows for good bandwidth at gains up to 10 V/V. When used with gains over 10 V/V, the LMH6574 will exhibit a "gain bandwidth product" similar to a typical voltage feedback amplifier. For gains of over 10 V/V consider selecting a high performance video amplifier like the LMH6720 (SNOSA39) to provide additional gain. 7.2.3 Other Applications The LMH6574 could support a multi antenna receiver with up to four separate antennas. Monitoring the signal strength of all 4 antennas and connecting the strongest signal to the final IF stage would provide effective spacial diversity. For direction finding, the LMH6574 could be used to provide high speed sampling of four separate antennas to a single DSP which would use the information to calculate the direction of the received signal. 14 Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 Feature Description (continued) 7.2.4 Driving Capacitive Loads Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 28 shows the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Figure 29 provides a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values. ROUT 45: LMH6574 CL 10 pF VOUT RL 1 k: Figure 28. Decoupling Capacitive Loads 90 2 80 LOAD = 1 k: || CL 0 70 NORMALIZED GAIN (dB) SUGGESTED ROUT (:) CL = 8.6 pF, ROUT = 63: VS = 5V 60 50 40 30 20 10 CL = 18 pF, ROUT = 48: -2 CL = 56 pF, ROUT = 24: -4 CL = 100 pF, ROUT = 19: -6 V OUT = 1 VPP CL || 1 k: -8 V = 5V S AV = 2 (V/V) 0 -10 1 10 100 CAPACTIVE LOAD (pF) 1000 1 10 100 1000 FREQUENCY (MHz) Figure 29. Suggested ROUT vs Capacitive Load Figure 30. Frequency Response vs Capacitive Load 7.2.5 ESD Protection The LMH6574 is protected against electrostatic discharge (ESD) on all pins. The LMH6574 will survive 2000-V Human Body model and 200-V Machine model events. Under normal operation the ESD diodes have no effect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6574 is driven by a large signal while the device is powered down the ESD diodes will conduct . The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation. Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 15 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com 7.3 Device Functional Modes 7.3.1 SD vs EN The LMH6574 has both shutdown and disable capability. The shutdown feature affects the entire chip, whereas the disable function only affects the output buffer. When in shutdown mode, minimal power is consumed. The shutdown function is very fast, but causes a very brief spike of about 400 mV to appear on the output. When in shutdown mode the LMH6574 consumes only 1.8 mA of supply current. For maximum input to output isolation use the shutdown function. The EN pin only disables the output buffer which results in a substantially reduced output glitch of only 50 mV. While disabled the chip consumes 4.7 mA, considerably more than when shutdown. This is because the input buffers are still active. For minimal output glitch use the EN pin. Also, care should be taken to ensure that, while in the disabled state, the voltage differential between the active input buffer (the one selected by pins A0 and A1) and the output pin stays less than 2V. As the voltage differential increases, input to output isolation decreases. Normally this is not an issue. See Multiplexer Expansion for further details. To reduce the output glitch when using the SD pin, switch the EN pin at least 10 ns before switching the SD pin. This can be accomplished by using an RC delay circuit between the two pins if only one control signal is available. Logic inputs "SD" and "EN" will revert to the "High", while "A0" and "A1" will revert to the "Low" state when left floating. 16 Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMH6574 is a high-speed 4:1 analog multiplexer, optimized for very high speed and low distortion. With selectable gain and excellent AC performance, the LMH6574 is ideally suited for switching high resolution, presentation grade video signals. The LMH6574 has no internal ground reference. Single or split supply configurations are both possible. The LMH6574 features very high speed channel switching and disable times. When disabled the LMH6574 output is high impedance making MUX expansion possible by combining multiple devices. See Multiplexer Expansion. 8.1.1 Multiplexer Expansion It is possible to use multiple LMH6574 devices to expand the number of inputs that can be selected for output. Figure 31 shows an 8:1 MUX using two LMH6574 devices. Figure 31. 8:1 MUX Using Two LMH6574 Devices Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 17 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Application Information (continued) In such an application, the output settling may be longer than the LMH6574 switching specifications (~20ns), while switching between two separate LMH6574 devices. The switching time limiting factor occurs when one LMH6574 is turned off and another one is turned on, using the SD (shutdown) pin. The output settling time consists of the time needed for the first LMH6574 to enter high impedance state plus the time required for the second LMH6574 output to dissipate the left-over output charge of the first device (limited by the output current capability of the second device) and the time needed to settle to the final voltage value. While Figure 31 MUX expansion benefits from more isolation, originating from the parasitic loading of the unselected channels on the selected channel, afforded by individual ROUT on each multiplexer output, this configuration does not produce the fastest transition between individual LMH6574 devices. For the fastest transition, the configuration of Figure 32 can be used where the LMH6574 output pins are all shorted together. Figure 32. Alternate 8:1 MUX Expansion Schematic (for Faster SD Switching) 18 Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 Application Information (continued) Figure 33 shows typical transition waveforms and shows that SD pin switching settles in less than 145 ns. 4.5 1.5 145 ns 4 1 3.5 3 0.5 SD_MUX1 2.5 OUT 2 0 Vout (V) SD Pin (V) SD_MUX2 1.5 -0.5 1 Settled final value 0.5 -1 0 -0.5 -1E-07 -5E-08 0 5E-08 0.0000001 1.5E-07 0.0000002 -1.5 2.5E-07 Time (50 ns/div) Figure 33. SD Pin Switching Waveform and Output Settling If it is important in the end application to make sure that no two inputs are presented to the output at the same time, an optional delay block can be added, to drive the SHUTDOWN pin of each device. Figure 34 shows one possible approach to this delay circuit. The delay circuit shown will delay SHUTDOWN's H to L transitions (R1 and C1 decay) but will not delay its L to H transition. R2 should be kept small compared to R1 in order to not reduce the SHUTDOWN voltage and to produce little or no delay to SHUTDOWN. R2 D1 C1 TO SD R1 Figure 34. Delay Circuit Implementation Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 19 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com Application Information (continued) With the SHUTDOWN pin putting the output stage into a high impedance state, several LMH6574's can be tied together to form a larger input MUX. However, there is a loading effect on the active output caused by the unselected devices. The circuit in Figure 35 shows how to compensate for this effect. For the 16:1 MUX function shown in Figure 35, the gain error would be about -0.8 dB, or about 9%. In the circuit in Figure 35, resistor ratios have been adjusted to compensate for this gain error. By adjusting the gain of each multiplexer circuit the error can be reduced to the tolerance of the resistors used (1% in this example). Figure 35. Multiplexer Gain Compensation NOTE Disabling of the LMH6574 using the EN pin is not recommended for use when doing multiplexer expansion. While disabled, If the voltage between the selected input and the chip output exceeds approximately 2V the device will begin to enter a soft breakdown state. This will show up as reduced input to output isolation. The signal on the noninverting input of the output driver amplifier will leak through to the inverting input, and then to the output through the feedback resistor. The worst case is a gain of 1 configuration where the non inverting input follows the active input buffer and (through the feedback resistor) the inverting input follows the voltage driving the output stage. The solution for this is to use shutdown mode for multiplexer expansion. 20 Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 LMH6574 www.ti.com SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 9 Power Supply Recommendations 9.1 Power Dissipation The LMH6574 is optimized for maximum speed and performance in the small form factor of the standard SOIC package. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation. Follow these steps to determine the Maximum power dissipation for the LMH6574: 1. Calculate the quiescent (no-load) power. PAMP = ICC* (VS) where * VS = V+ - V- (1) 2. Calculate the RMS power dissipated in the output stage: PD (rms) = rms ((VS - VOUT) * IOUT) where * * * VOUT is the voltage across the external load IOUT is the current through the external load VS is the total supply voltage (2) 3. Calculate the total RMS power: PT = PAMP + PD. The maximum power that the LMH6574 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150 - TAMB)/RJA where * * TAMB = Ambient temperature (C) RJA = Thermal resistance, from junction to ambient, for a given package (C/W) (3) For the SOIC package RJA is 130 C/W. 10 Layout 10.1 Layout Guidelines Whenever questions about layout arise, use the evaluation board LMH730276 as a guide. To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. In the Functional Block Diagram, the capacitor between V+ and V- is optional, but is recommended for best second harmonic distortion. Another way to enhance performance is to use pairs of 0.01 F and 0.1 F ceramic capacitors for each supply bypass. Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 21 LMH6574 SNCS103E - NOVEMBER 2004 - REVISED AUGUST 2018 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For additional information, see the following: * Current Feedback Loop Gain Analysis and Performance Enhancement Application Note OA-13 * IC Package Thermal Metrics Application Report * LMH730276 4:1 Multiplexer Evaluation Board 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright (c) 2004-2018, Texas Instruments Incorporated Product Folder Links: LMH6574 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMH6574MA NRND SOIC D 14 55 Non-RoHS & Green Call TI Call TI -40 to 85 LMH65 74MA LMH6574MA/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65 74MA LMH6574MAX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65 74MA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMH6574MAX/NOPB Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.35 2.3 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6574MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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