Low Cost, 300 MHz
Rail-to-Rail Amplifiers
Data Sheet
AD8061/AD8062/AD8063
Rev. J Document Feedback
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FEATURES
Low cost
Single (AD8061), dual (AD8062)
Single with disable (AD8063)
Rail-to-rail output swing
Low offset voltage: 6 mV
High speed
300 MHz, −3 dB bandwidth (G = 1)
650 V/µs slew rate
8.5 nV/√Hz at 5 V
35 ns settling time to 0.1% with 1 V step
Operates on 2.7 V to 8 V supplies
Input voltage range = −0.2 V to +3.2 V with VS = 5 V
Excellent video specifications (RL = 150 Ω, G = 2)
Gain flatness: 0.1 dB to 30 MHz
0.01% differential gain error
0.04° differential phase error
35 ns overload recovery
Low power
6.8 mA/amplifier typical supply current
AD8063 400 µA when disabled
APPLICATIONS
Imaging
Photodiode preamps
Professional video and cameras
Handsets
DVDs/CDs
Base stations
Filters
ADC drivers
Clock buffers
CONNECTION DIAGRAMS
8
7
6
5
1
2
3
4
NC
–IN
+IN
(AD8063 ONLY)
+VS
VOUT
NC–VS
AD8061/
AD8063
NC = NO CONNECT
(Not t o Scale)
01065-001
DISABLE
V
OUT1
–
IN1
+IN1
–
V
S
+V
S
V
OUT2
–
IN2
+IN2
1
2
3
4
8
7
6
5
(Not t o Scale)
AD8062
01065-003
Figure 1. 8-Lead SOIC (R) Figure 2. 8-Lead SOIC (R)/MSOP (RM)
+IN
+V
S
–
V
S
1
2
34
–
IN
V
OUT 5
AD8061
(Not t o Scale)
01065-004
Figure 3. 6-Lead SOT-23 (RJ) Figure 4. 5-Lead SOT-23 (RJ)
R
F
= 0Ω
FREQUENCY (MHz)
3
–1211k
NORM ALIZED G AIN (dB)
–6
10010
0
–3
–9
V
O
= 0.2V p-p
R
L
= 1kΩ
V
BIAS
= 1V
R
F
OUT
IN
V
BIAS
50Ω R
L
R
F
= 50Ω
01065-005
Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω
GENERAL DESCRIPTION
The AD8061/AD8062/AD8063 are rail-to-rail output voltage
feedback amplifiers offering ease of use and low cost. They have
a bandwidth and slew rate typically found in current feedback
amplifiers. All have a wide input common-mode voltage range
and output voltage swing, making them easy to use on single
supplies as low as 2.7 V.
Despite being low cost, the AD8061/AD8062/AD8063 provide
excellent overall performance. For video applications, their
differential gain and phase errors are 0.01% and 0.04° into a
150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi-
tionally, they offer wide bandwidth to 300 MHz along with
650 V/µs slew rate.
The AD8061/AD8062/AD8063 offer a typical low power of
6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 µA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Maximum Power Dissipation ..................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
Circuit Description ......................................................................... 14
Headroom Considerations ........................................................ 14
Overload Behavior and Recovery ............................................ 15
Capacitive Load Drive ............................................................... 16
Disable Operation ...................................................................... 16
Board Layout Considerations ................................................... 16
Applications Information .............................................................. 17
Single-Supply Sync Stripper ...................................................... 17
RGB Amplifier ............................................................................ 17
Multiplexer .................................................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
5/13—Rev. I to Rev. J
Added Output Voltage Swing Parameters; Table 1 ...................... 3
Added Output Voltage Swing Parameters; Table 2 ...................... 4
Added Output Voltage Swing Parameters; Table 3 ...................... 5
Changes to Ordering Guide .......................................................... 20
5/13—Rev. H to Rev. I
Changes to Figure 15 ........................................................................ 8
Changes to Ordering Guide .......................................................... 20
1/13—Rev. G to Rev. H
Changes to Figure 12 ........................................................................ 7
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
2/10—Rev. F to Rev. G
Changes to Table 4 ............................................................................ 6
11/09—Rev. E to Rev. F
Changed Input Common-Mode Voltage Range Parameter........ 4
Updated Outline Dimensions ....................................................... 19
10/07—Rev. D to Rev. E
Changes to Applications .................................................................. 1
Updated Outline Dimensions ....................................................... 19
12/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Change to Features and General Description ............................... 1
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
5/01—Rev. B to Rev. C
Replaced TPC 9 with new graph .................................................... 7
11/00—Rev. A to Rev. B
2/00—Rev. 0 to Rev. A
11/99—Revision 0: Initial Version
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 3 of 20
SPECIFICATIONS
TA = 25°C, VS = 5 V, R L = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 320 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
−3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 280 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz
Slew Rate G = 1, VO = 2 V step, RL = 2 kΩ 500 650 V/µs
G = 2, V
O
= 2 V step, R
L
= 2 kΩ
300
500
V/µs
Settling Time to 0.1% G = 2, VO = 2 V step 35 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −77 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ −50 dBc
Crosstalk, Output to Output f = 5 MHz, G = 2, AD8062 −90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
Differential Gain Error (NTSC) G = 2, RL = 150 Ω 0.01 %
Differential Phase Error (NTSC)
G = 2, R
L
= 150 Ω
0.04
Degrees
Third-Order Intercept f = 10 MHz 28 dBc
SFDR f = 5 MHz 62 dB
DC PERFORMANCE
Input Offset Voltage 1 6 mV
TMIN to TMAX 2 6 mV
Input Offset Voltage Drift 3.5 µV/°C
Input Bias Current 3.5 9 µA
TMIN to TMAX 4 9 µA
Input Offset Current
±0.3
±4.5
µA
Open-Loop Gain VO = 0.5 V to 4.5 V, RL = 150 Ω 68 70 dB
VO = 0.5 V to 4.5 V, RL = 2 kΩ 74 90 dB
INPUT CHARACTERISTICS
Input Resistance
13
MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range −0.2 to +3.2 V
Common-Mode Rejection Ratio VCM = –0.2 V to +3.2 V 62 80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Low RL = 150 Ω 0.3 0.1 V
RL = 2 kΩ 0.25 0.1 V
Output Voltage Swing High RL = 150 Ω 4.75 4.86 V
RL = 2 kΩ 4.85 4.9 V
Output Current
V
O
= 0.5 V to 4.5 V
25
50
mA
Capacitive Load Drive, VOUT = 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE
Turn-On Time
40
ns
Turn-Off Time 300 ns
DISABLE Voltage (Off) 2.8 V
DISABLE Voltage (On) 3.2 V
POWER SUPPLY
Operating Range 2.7 5 8 V
Quiescent Current per Amplifier 6.8 9.5 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio ∆VS = 2.7 V to 5 V 72 80 dB
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 4 of 20
TA = 25°C, VS = 3 V, R L = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
–3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 250 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz
Slew Rate
G = 1, V
O
= 1 V step, R
L
= 2 kΩ
190
280
V/µs
G = 2, VO = 1.5 V step, RL = 2 kΩ 180 230 V/µs
Settling Time to 0.1% G = 2, VO = 1 V step 40 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −60 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ −44 dBc
Crosstalk, Output to Output f = 5 MHz, G = 2 −90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 1 6 mV
TMIN to TMAX 2 6 mV
Input Offset Voltage Drift 3.5 µV/°C
Input Bias Current 3.5 8.5 µA
TMIN to TMAX 4 8.5 µA
Input Offset Current ±0.3 ±4.5 µA
Open-Loop Gain VO = 0.5 V to 2.5 V, RL = 150 Ω 66 70 dB
VO = 0.5 V to 2.5 V, RL = 2 kΩ 74 90 dB
INPUT CHARACTERISTICS
Input Resistance 13 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range −0.2 to +1.2 V
Common-Mode Rejection Ratio
V
CM
= –0.2 V to +1.2 V
80
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Low RL = 150 Ω 0.3 0.1 V
RL = 2 kΩ 0.3 0.1 V
Output Voltage Swing High
R
L
= 150 Ω
2.85
2.87
V
RL = 2 kΩ 2.9 2.9 V
Output Current VO = 0.5 V to 2.5 V 25 mA
Capacitive Load Drive, VOUT = 0.8 V 30% overshoot, G = 1, RS = 0 Ω 25 pF
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE
Turn-On Time 40 ns
Turn-Off Time 300 ns
DISABLE Voltage—Off 0.8 V
DISABLE Voltage—On 1.2 V
POWER SUPPLY
Operating Range 2.7 3 V
Quiescent Current per Amplifier 6.8 9 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio 72 80 dB
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 5 of 20
TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz
G = –1, +2, VO = 0.2 V p-p 60 115 MHz
G = 1, VO = 1 V p-p 230 MHz
Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p, VO dc = 1 V 30 MHz
Slew Rate
G = 1, V
O
= 0.7 V step, R
L
= 2 kΩ
110
150
V/µs
G = 2, VO = 1.5 V step, RL = 2 kΩ 95 130 V/µs
Settling Time to 0.1% G = 2, VO = 1 V step 40 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ –60 dBc
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ –44 dBc
Crosstalk, Output to Output f = 5 MHz, G = 2 –90 dBc
Input Voltage Noise f = 100 kHz 8.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 1 6 mV
TMIN to TMAX 2 6 mV
Input Offset Voltage Drift 3.5 µV/°C
Input Bias Current 3.5 µA
TMIN to TMAX 4 8.5 µA
Input Offset Current ±0.3 ±4.5 µA
Open-Loop Gain VO = 0.5 V to 2.2 V, RL = 150 Ω 63 70 dB
VO = 0.5 V to 2.2 V, RL = 2 kΩ 74 90 dB
INPUT CHARACTERISTICS
Input Resistance 13 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage Range –0.2 to +0.9 V
Common-Mode Rejection Ratio
V
CM
= –0.2 V to +0.9 V
0.8
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Low RL = 150 Ω 0.3 0.1 V
RL = 2 kΩ 0.25 0.1 V
Output Voltage Swing High
R
L
= 150 Ω
2.55
2.55
V
RL = 2 kΩ 2.6 2.6 V
Output Current VO = 0.5 V to 2.2 V 25 mA
Capacitive Load Drive, VOUT = 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF
G = 2, RS = 4.7 Ω 300 pF
POWER-DOWN DISABLE
Turn-On Time 40 ns
Turn-Off Time 300 ns
DISABLE Voltage (Off) 0.5 V
DISABLE Voltage (On) 0.9 V
POWER SUPPLY
Operating Range 2.7 8 V
Quiescent Current per Amplifier 6.8 8.5 mA
Supply Current when Disabled (AD8063 Only) 0.4 mA
Power Supply Rejection Ratio
80
dB
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 8 V
Internal Power Dissipation1
8-lead SOIC (R) 0.8 W
5-lead SOT-23 (RJ) 0.5 W
6-lead SOT-23 (RJ) 0.5 W
8-lead MSOP (RM) 0.6 W
Input Voltage (Common-Mode) (−VS − 0.2 V) to (+VS + 0.2 V)
Differential Input Voltage
±V
S
Output Short-Circuit Duration Observe power derating curves
Storage Temperature Range
R-8, RM-8, SOT-23-5, SOT-23-6
−65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering,
10 sec)
300°C
1 Specification is for device in free air.
8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W.
5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W.
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8061/AD8062/AD8063 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure. While the
AD8061/AD8062/AD8063 is internally short-circuit protected,
this may not be sufficient to guarantee that the maximum
junction temperature (150°C) is not exceeded under all
conditions.
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
AMBIENT TEMPERATURE
(°C)
2.0
1.0
0
–50 –40
MAXIMUM POWER DISSIPATION (W)
–30 70 80 90
1.5
0.5
605040300–10–20 2010
T
J
= 150° C
MSOP
SOT-23-5, S O T-23-6
8-L E AD S OIC
PACKAGE
01065-006
Figure 6. Maximum Power Dissipation vs. Temperature for
AD8061/AD8062/AD8063
ESD CAUTION
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD CURRENT ( mA)
0010
VOLTAGE DIFFERENTIAL FROM V
S (Unit)
0.2
+VOUT @ +85° C
+VOUT @ +25° C
+VOUT @ –40°C
–VOUT @ +85° C
–VOUT @ +25° C
0.4
0.6
0.8
1.0
1.2
20 30 40 50 60 70 80 90
01065-007
–VOUT @ –40°C
Figure 7. Output Saturation Voltage vs. Load Current
SINGLE PO W ER SUPPLY (V)
18
8
0
POWER SUPPLY CURRENT (mA)
16
14
12
10
6
4
2
AD8062
AD8061
01065-008
28
7
5
463
Figure 8. ISUPPLY vs. VSUPPLY
RF = 0Ω
FREQUENCY (MHz)
3
–1211k
NORM ALIZED G AIN (dB)
–6
10010
0
–3
–9
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
RF
OUT
IN
VBIAS
50Ω RL
RF = 50Ω
01065-009
Figure 9. Small Signal Response, RF = 0 Ω, 50 Ω
FREQUENCY (MHz)
3
–1211k
NORMALIZED GAIN(dB)
–6
100
10
0
–3
–9
G = +1
G = +2
G = +5
V
O
= 0.2V p-p
R
L
= 1kΩ
V
BIAS
= 1V
01065-010
Figure 10. Small Signal Frequency Response
FREQUENCY (MHz)
3
–1211k
NORMALIZED GAIN(dB)
–6
10010
0
–3
–9
G = +2
G = +5
G = +1
VO = 1.0V p-p
RL = 1kΩ
VBIAS = 1V
01065-011
Figure 11. Large Signal Frequency Response
G = –1
FREQUENCY (MHz)
3
–1211k
NORM ALIZED G AIN (dB)
–6
10010
0
–3
–9
G = –2
G = –5
V
S
= 5V
V
O
= 0.2V p-p
R
L
= 1kΩ
V
BIAS
= 1V
01065-012
Figure 12. Small Signal Frequency Response
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 8 of 20
FREQUENCY(MHz)
3
–1211k
NORM ALIZED G AIN (dB)
–6
100
10
0
–3
–9
G = –1
G = –2
G = –5
V
S
= 5V
V
O
= 1V p-p
R
L
= 1kΩ
V
BIAS
= 1V
01065-013
Figure 13. Large Signal Frequency Response
FREQUENCY (MHz)
0.1
–0.511k
NORM ALIZED G AIN (dB)
–0.2
10010
0
–0.1
–0.3
–0.4
V
S
= 5V
V
S
= 3V
V
S
= 2.7V V
O
= 0.2V p-p
R
L
= 1kΩ
V
BIAS
= 1V
G = +1
01065-014
Figure 14. 0.1 dB Flatness
0.01 0.1 1 10 100 1k
80
60
40
20
0
–20
–40
200
150
100
50
0
–50
–100
–150
–200
–250
–300
OPEN-LOOP GAIN (dB)
PHASE ( Degrees)
FREQUENCY (MHz)
GAIN
PHASE
01065-015
Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency,
VS = 5 V, RL = 1 kΩ
INPUT SIGNAL DC BIAS (V)
0
–50
–1000.5
HARMO NIC DISTORTION (dBc)
1.0 3.0 3.5
–10
–20
–30
–40
–60
–70
–80
–90
2.52.0
1.5
3RD @ 1MHz
3RD @ 10MHz
2ND @ 1MHz
2ND @ 10MHz
VS = 5V
RL = 1kΩ
G = +1
01065-016
Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias
FREQUENCY (MHz, START = 10kHz , S TOP = 30MHz)
–70
0.01
DISTORTION (dB)
–40
–50
–60
–80
–90
–100
–110 0.1
3RD H
2ND H
1.25V
dc
50Ω
604Ω
1kΩ
52.3Ω
0.1µF
10µF
5V
+
+
–
0.1µF
1kΩ
(R
LOAD
)
1MΩ INPUT
01065-017
110 50
Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.
Input Signal DC Bias
OUTPUT SIGNAL DC BIAS (V)
–50
–120 0
DISTORTION (dB)
1
–30
–40
–60
–70
–80
–90
432
–110
–100
V
S
= 5V
R
L
= 1kΩ
G = +5
V
O
= 1V p-p
3RD
2ND 10MHz
5MHz
2ND
3RD
1MHz
3RD
2ND
5
01065-018
Figure 18. Harmonic Distortion vs. Output Signal DC Bias
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 9 of 20
RTO OUTPUT (V p-p)
–100
DISTORTION (dB)
1.0 3.0 3.5
–40
–50
–60
–70
2.52.01.5
3RD @ 2MHz
2ND @ 2MHz
2ND @ 10MHz
–90
–80
4.0 4.5
VS = 5V
RF = RL = 1kΩ
G = +2
–110
3RD @ 500kHz
+
1kΩ
5V 10µF
0.1µF
1kΩ
50Ω
1kΩ
50Ω
1MΩ
INPUT
TO
3589A
2ND @ 500kHz
01065-019
Figure 19. Harmonic Distortion vs. Output Signal Amplitude
FREQUENCY (MHz, START = 10kHz , STOP = 30MHz)
DISTORTION (dB)
0.01 0.1 110
–30
–40
–50
–60
–70
–80
–90
–100
V
S
= 5V
R
I
= R
L
= 1kΩ
V
O
= 2V p-p
G = 2
S1 2ND HARMONIC/
DUAL ±2.5V SUP PLY
S1 3RD HARMONIC/
SINGLE +5V SUPPLY
S1 2ND HARMONIC/
SINGLE +5V SUPPLY
S1 3RD HARMONIC/
DUAL ±2.5V SUP PLY
–110
01065-020
Figure 20. Harmonic Distortion vs. Frequency
TIME (µs)
0.7
0
OUTPUT VOLTAGE (V)
0.2
1.0
0.9
0.8
0.6
0.5
0.4
0.3
0.10
0.1
0.2
0.3 0.4 0.5
V
S
= 5V
R
L
= 1kΩ
G = +1
01065-021
Figure 21. 400 mV Pulse Response
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
DIFFERENTIAL PHASE
(Degrees)
0.02
0
–0.02
–0.04
–0.06
DIFFERENTIAL GAIN
(%)
0.01
0
–0.01
–0.02
–0.04
–0.06
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
01065-022
Figure 22. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 1 kΩ, VS = 5 V
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
0.04
0.03
0.02
0.01
0
0.010
0.005
0
–0.005
–0.010
–0.01
–0.02
DIFFERENTIAL PHASE
(Degrees) DIFFERENTIAL GAIN
(%)
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
01065-023
Figure 23. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 150 Ω, VS = 5 V
OUTPUT STEPAMPLITUDE (V)
1000
500
SLEW RATE (V/µ s)
700
1.0
900
800
600
1.5 2.0 2.5 3.0
400
FALLING EDGE
RISING EDGE
100
300
200
0
VS = 5V
RL = 1kΩ
G = +1
01065-024
Figure 24. Slew Rate vs. Output Step Amplitude
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 10 of 20
OUTPUT STEP (V)
1400
04.0
SLEW RATE (V/µ s)
2.0 2.5
1200
1000
800
600
400
200
00.5 3.0 3.5
FALLING EDGE
VS = +5V
FALLING EDGE
VS = ±4V
RISING EDGE
VS = ±4V
RISING EDGE
VS = +5V
1.0 1.5
01065-025
Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 kΩ, VS = 5 V
VOLTAGE NOISE (nV/ Hz)
V
S
= 5V
R
L
= 1kΩ
FREQUENCY (Hz)
1k
10 10M100 1k 100k 1M
100
10
110k
01065-026
Figure 26. Voltage Noise vs. Frequency
FREQUENCY (Hz)
100
10 10M
CURRENT NOIS E (p A/ Hz)
100 1k 100k 1M
10
010k
1
VS = 5V
RL = 1kΩ
01065-027
Figure 27. Current Noise vs. Frequency
500mV/DIV
0 20 40 60 80100 120 140 160 180 200
2.5V
VOLTS
TIME (ns)
0V
VIN
VOUT
VS = ±2.5V
G = +1
RL = 1k
Ω
01065-028
Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V
500mV/DIV
V
S
= ±2. 5V
G = +5
R
L
= 1k
Ω
0 20 40 60 80 100 120 140 160 180 200
2.5V
VOLTS
TIME (ns)
1.0V
0V
VIN
VOUT
01065-029
Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V
FREQUENCY(MHz)
0.01 500
CMRR (dB)
0.1 10 100
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1
SIDE 1
SIDE 2
V
CM
= 0.2V p-p
R
L
= 100
Ω
V
S
=
±2.5V
154
Ω
154
Ω
57.6
Ω
50
Ω
V
IN
200mV p - p
604
Ω
604
Ω
01065-030
Figure 30. CMRR vs. Frequency
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 11 of 20
PSRR ( dB)
FREQUENCY (MHz)
500
0.1 10 100
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1
–PSRR
+PSRR
ΔV
S
= 0.2V p-p
R
L
= 1kΩ
V
S
= 5V
0.01
01065-031
Figure 31. ±PSRR vs. Frequency Delta
FREQUENCY (MHz)
0.01 500
OUTPUT TO OUTPUT CROSSTAL K ( dB)
0.1 10 100
–120
–110
–100
–80
–70
–60
–50
–40
–30
–20
1
INP UT = SIDE 2 INPUT = S IDE 1
V
S
= 5V
V
IN
= 400mV rms
R
L
= 1kΩ
G = +2
–90
IN
1kΩ
1kΩ
50Ω
+2.5V
1kΩ
OUT
–2.5V
01065-032
Figure 32. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V
FREQUENCY (MHz)
0
11k
DIS ABLED I S OLATION (dB)
–20
10010
–10
–30
–50
–40
–60
–70
–80
–90
V
S
= 5V
V
O
= 0.2V p-p
R
L
= 1kΩ
V
BIAS
= 1V
01065-033
Figure 33. AD8063 Disabled Output Isolation Frequency Response
DIS ABLE VO LTAGE
7
1.0 5.0
ISUPPLY ( mA)
1.5 2.0 2.5
6
5
4
3
1
03.0
2
3.5 4.0 4.5
VS = 5V
01065-034
Figure 34. AD8063 DISABLE Voltage vs. Supply Current
V
DISABLE
TIME (µs)
6
02.0
OUTPUT VOLTAGE (V)
0.4
5
4
3
2
0
–1 0.8
1
1.2 1.6
V
OUT
V
S
= 5V
G = +2
f
IN
= 10MHz
@ 1.3V
BIAS
R
L
= 100Ω
01065-035
Figure 35. AD8063 DISABLE Function, Voltage = 0 V to 5 V
FREQUENCY (MHz)
1k
0.1 1k
IMPEDANCE (Ω)
10
110 100
100
1
0.1
0.01
V
S
= 5V
V
O
= 0.2V p-p
R
L
= 1kΩ
V
BIAS
= 1V
01065-036
Figure 36. Output Impedance vs. Frequency,
VOUT = 0.2 V p-p, RL = 1 kΩ, VS = 5 V
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 12 of 20
20ns/DIV
+0.1%
SETTLING TIMETO 0.1%
–0.1%
VS = 5V
RL = 1kΩ
t = 0
1kΩ
50Ω
1kΩ
RL = 1kΩ
01065-037
Figure 37. Output Settling Time to 0.1%
OUTPUT VOLTAGE STEP
50
0.5
SETTLING TIME (ns)
1.0 1.5 2.0
45
40
35
30
25
20
15
10
5
02.5
FALLING EDGE
RISING EDGE
V
S
= 5V
R
L
= 1kΩ
G = +1
01065-038
Figure 38. Settling Time vs. VOUT
2µs
VS = 5V
G = –1
RF = 1kΩ
RL = 1kΩ
4.86V
2.43V
0V
1V
01065-039
VOLTS
Figure 39. Output Swing
500mV/DIV
V
S
= 5V
G = +2
R
L
= 1kΩ
VIN = 1V p-p
010 20 80 90 100
3.5V
TIME (n s)
2.5V
1.5V
70
60504030
01065-040
VOLTS
Figure 40. 1 V Step Response
20mV/DIV
VS = 5V
G = +2
RL = 1kΩ
VIN = 100mV
010 20 80 90 100
2.6V
TIME (n s)
2.5V
2.4V
7060504030
01065-041
VOLTS
Figure 41. 100 mV Step Response
2µs/DIV
0V
1V/DIV
V
S
= 5V
G = +2
R
F
= R
L
= 1kΩ
V
IN
= 4V p-p
01065-042
VOLTS
Figure 42. Output Rail-to-Rail Swing
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 13 of 20
50mV/DIV
VS = 5V
G = +1
RL = 1kΩ
0 5 10 40 45 50
2.6V
TIME (n s)
2.5V
2.4V
35
30252015
01065-043
VOLTS
Figure 43. 200 mV Step Response
1V/DIV
V
S
= 5V
G = +2
R
L
= R
F
= 1kΩ
V
IN
= 2V p-p
0 5 10 40 45 50
TIME (n s)
3530252015
4.5V
2.5V
0.5V
01065-044
VOLTS
Figure 44. 2 V Step Response
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 14 of 20
CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family is comprised of high
speed voltage feedback op amps. The high slew rate input stage
is a true, single-supply topology, capable of sensing signals at or
below the minus supply rail. The rail-to-rail output stage can
pull within 30 mV of either supply rail when driving light loads
and within 0.3 V when driving 150 Ω. High speed perform-
ance is maintained at supply voltages as low as 2.7 V.
HEADROOM CONSIDERATIONS
These amplifiers are designed for use in low voltage systems.
To obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.
The AD8061/AD8062/AD8063 input common-mode voltage
range extends from the negative supply voltage (actually 200 mV
below this), or ground for single-supply operation, to within
1.8 V of the positive supply voltage. Thus, at a gain of 2, the
AD8061/AD8062/AD8063 can provide full rail-to-rail output
swing for supply voltage as low as 3.6 V, assuming the input
signal swings from −VS (or ground) to +VS/2. At a gain of 3,
the AD8061/AD8062/AD8063 can provide a rail-to-rail output
range down to 2.7 V total supply voltage.
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier’s positive input lies within the amplifier’s input
common-mode range.
The input stage is the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 45 shows a typical offset voltage vs. input
common-mode voltage for the AD8061/AD8062/AD8063
amplifier on a 5 V supply. Accurate dc performance is main-
tained from approximately 200 mV below the minus supply
to within 1.8 V of the positive supply. For high speed signals,
however, there are other considerations. Figure 46 shows −3 dB
bandwidth vs. dc input voltage for a unity-gain follower. As
the common-mode voltage approaches the positive supply,
the amplifier holds together well, but the bandwidth begins to
drop at 1.9 V within +VS.
This manifests itself in increased distortion or settling time.
Figure 16 plots the distortion of a 1 V p-p signal with the
AD8061/AD8062/AD8063 amplifier used as a follower on
a 5 V supply vs. signal common-mode voltage. Distortion
performance is maintained until the input signal center voltage
gets beyond 2.5 V, as the peak of the input sine wave begins to
run into the upper common-mode voltage limit.
VCM (V)
VOS (mV)
–4.0
–3.6
–3.2
–2.8
–2.4
–2.0
–1.6
–1.2
–0.8
–0.4
–0.5 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
01065-045
Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V
FREQUENCY (MHz)
2
–80.1
GAIN (d B)
–4
0
–2
–6
110 100 1k 10k
01065-046
V
CM
= 3.0
V
CM
= 3.1
V
CM
= 3.2
V
CM
= 3.3
V
CM
= 3.4
Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V
Higher frequency signals require more headroom than lower
frequencies to maintain distortion performance. Figure 47
illustrates how the rising edge settling time for the amplifier
configured as a unity-gain follower stretches out as the top of
a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
For signals approaching the minus supply and inverting gain
and high positive gain configurations, the headroom limit is
the output stage. The AD8061/AD8062/AD8063 amplifiers use
a common emitter style output stage. This output stage
maximizes the available output range, limited by the saturation
voltage of the output transistors. The saturation voltage
increases with the drive current the output transistor is required
to supply, due to the output transistors’ collector resistance. The
saturation voltage is estimated using the equation
VSAT = 25 mV + IO × 8 Ω
where:
IO is the output current.
8 Ω is a typical value for the output transistors’ collector
resistance.
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 15 of 20
TIME (n s)
2.0
0
OUTPUT VOLTAGE (V)
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
4812 16 20 24 28 32
2V TO 3V STEP
2.1V TO 3.1V STEP
2.2V TO 3.2V STEP
2.3V TO 3.3V STEP
2.4V TO 3.4V STEP
01065-047
Figure 47. Output Rising Edge for 1 V Step at
Input Headroom Limits, G = 1, VS = 5 V, 0 V
As the saturation point of the output stage is approached, the
output signal shows increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than lower frequency
signals. Figure 16, Figure 17, and Figure 18 illustrate this point,
plotting typical distortion vs. output amplitude and bias for
gains of 2 and 5.
OVERLOAD BEHAVIOR AND RECOVERY
Input
The specified input common-mode voltage of the AD8061/
AD8062/AD8063 is −200 mV below the negative supply to
within 1.8 V of the positive supply. Exceeding the top limit
results in lower bandwidth and increased settling time as seen
in Figure 46 and Figure 47. Pushing the input voltage of a unity-
gain follower beyond 1.6 V within the positive supply leads to
the behavior shown in Figure 48—an increasing amount of
output error and much increased settling time. Recovery time
from input voltages 1.6 V or closer to the positive supply is
approximately 35 ns, which is limited by the settling artifacts
caused by transistors in the input stage coming out of saturation.
The AD8061/AD8062/AD8063 family does not exhibit phase
reversal, even for input voltages beyond the voltage supply rails.
Going more than 0.6 V beyond the power supplies turns on
protection diodes at the input stage, which greatly increases the
current draw of the device.
TIME (n s)
2.1 0
OUTPUT VOLTAGE (V)
2.3
100
VOLTAGE STEP
FROM 2. 4V TO 3. 4V
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VOLTAGE STEP
FROM 2. 4V TO 3. 6V
VOLTAGE STEP
FROM 2. 4V TO 3.8V,
4V AND 5V
200 300 400 500 600
01065-048
Figure 48. Pulse Response for G = 1 Follower,
Input Step Overloading the Input Stage
Output
Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure 49
shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
TIME (n s)
–0.2
INPUT AND OUT P UT VOLTAGE (V)
OUTPUT VOLTAGE
5V TO 2.5V
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
10 20 30 40 50 60 70
OUTPUT VOLTAGE
0V TO 2.5V
INP UT VOLTAGE
EDGES R
5V
V
O
2.5V
R
V
IN
––
0
01065-049
Figure 49. Overload Recovery, G = −1, VS = 5 V
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 16 of 20
CAPACITIVE LOAD DRIVE
The AD8061/AD8062/AD8063 family is optimized for
bandwidth and speed, not for driving capacitive loads. Output
capacitance creates a pole in the amplifier’s feedback path,
leading to excessive peaking and potential oscillation. If dealing
with load capacitance is a requirement of the application, the
two strategies to consider are as follows:
Use a small resistor in series with the amplifier’s output and the
load capacitance.
Reduce the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
AD8061
V
O
R
SERIES
C
LOAD
V
IN
01065-050
Figure 50. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in the AD8061/AD8062/
AD8063 family are able to drive more capacitive load without
excessive peaking when used in higher gain configurations
because the increased noise gain reduces the bandwidth of the
overall feedback loop. Figure 51 plots the capacitance that
produces 30% overshoot vs. noise gain for a typical amplifier.
CLOSED-LOOP GAIN
10k
1k
101 52
CAPACITIVE LOAD (pF)
100
3 4
RS = 0
RS = 4.7
01065-051
Figure 51. Capacitive Load vs. Closed-Loop Gain
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown
in Figure 52. When the DISABLE node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 µA, and the AD8063 output
enters a high impedance state. If the DISABLE node is not
connected and allowed to float, the AD8063 stays biased at
full power.
VCC
DISABLE
TOAMPLIFIER
BIAS
VEE
2V
01065-052
Figure 52. Disable Circuit of the AD8063
Figure 34 shows the AD8063 supply current vs. DISABLE
voltage. Figure 35 plots the output seen when the AD8063 input
is driven with a 10 MHz sine wave, and DISABLE is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD8061/AD8062/
AD8063 family requires the use of high speed board layout
techniques and low parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
Proper bypassing is critical. Use a ceramic 0.1 µF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 µF to
10 µF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 17 of 20
APPLICATIONS INFORMATION
SINGLE-SUPPLY SYNC STRIPPER
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of analog-to-digital conversion,
the sync pulses consume some of the dynamic range, so
removing them increases the converter’s available dynamic
range for the video information.
Figure 53 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the negative
supply is at ground potential, the lowest potential to which the
output can go is ground. This feature is exploited to create a
waveform whose lowest amplitude is the black level of the video
and does not include the sync level.
75Ω VIDEO OUT
75Ω
RG
1kΩ
75Ω
RF
1kΩ
10µF
3V
AD8061
0.1µF
3
24
6
7
VIDEO IN
PI N NUM BE RS ARE
FOR 8-L E AD PACKAGE
01065-053
Figure 53. Single 3 V Sync Stripper Using AD8061
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Because the sync level is
below the black level, it does not show up at the output. However,
all of the active video portion of the waveform is amplified by a
gain of 2 and then normalized to unity gain by the back-
terminated transmission line. Figure 54 is an oscilloscope plot
of the input and output waveforms.
01065-054
500mV
INPUT
OUTPUT
1
2
10µs
Figure 54. Input and Output Waveforms for a Single-Supply
Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single-supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not
at ground but at a positive voltage.
The circuit can be modified to provide the sync stripping
function for such a waveform. Instead of connecting RG to
ground, connect it to a dc voltage that is two times the black
level of the input signal. The gain from the noninverting input
to the output is 2, which means the black level is amplified by 2
to the output. However, the gain through RG is −1 to the output.
It takes a dc level of twice the input black level to shift the black
level to ground at the output. When this occurs, the sync is
stripped, and the active video is passed as in the ground-
referenced case.
75Ω
10µF
0.1µF
3V
3
2
4
6
7
75Ω
MONITOR
#1
75Ω
75Ω
75Ω
1kΩ
1kΩ
1kΩ
1kΩ
3V
1kΩ
3
2
5
6
7
8
1
4
MONITOR
#2
GREEN
DAC
RED
GREEN
BLUE
RED
DAC
BLUE
DAC
75Ω
75Ω
75Ω
75Ω
AD8061 75Ω
10µF
0.1µF
1kΩ
AD8062 75Ω
AD8062
75Ω
01065-055
Figure 55. RGB Cable Driver Using AD8061 and AD8062
RGB AMPLIFIER
Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
is also zero. Before the availability of high speed rail-to-rail op
amps, it was essential that an amplifier have a negative supply
to amplify such a signal. Such an amplifier is necessary if one
wants to drive a second monitor from the same DAC outputs.
However, high speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 accept ground-level input signals and
output ground-level signals. They are used as RGB signal
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system. Figure 55 shows a circuit that performs this function.
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 18 of 20
MULTIPLEXER
The AD8063 has a disable pin used to power down the ampli-
fier to save power or to create a mux circuit. If two (or more)
AD8063 outputs are connected together, and only one is enabled,
then only the signal of the enabled amplifier will appear at the
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
different gain stages, or differently tuned filters, to make a gain-
step amplifier or a selectable frequency amplifier.
Figure 56 shows a schematic of two AD8063 devices used to
create a mux that selects between two inputs. One of these is a
1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave.
49.9Ω
1kΩ
+4V
1
–4V
49.9Ω
TIME
BASE
OUT
TIME
BASE
IN
1V p-p
3MHz
2V p-p
1MHz
VOUT
49.9Ω
SELECT
HCO4
1kΩ
10µF
0.1µF
10µF
0.1µF
AD8063
49.9Ω
1kΩ
+4V
1
–4V
1kΩ
10µF
0.1µF
10µF
0.1µF
AD8063
01065-056
Figure 56. Two-to-One Multiplexer Using Two AD8063s
The select signal and the output waveforms for this circuit are
shown in Figure 57. For synchronization clarity, two different
frequency synthesizers, whose time bases are locked to each
other, generate the signals.
1V 2V
2µs
SELECT
OUTPUT
01065-057
Figure 57. AD8063 Mux Output
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-01-2010-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-178-AB
10°
4°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
65
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.30 MIN
0.55
0.45
0.35
PIN 1
INDICATOR
12-16-2008-A
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 60. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Figure 61. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 20 of 20
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Branding
AD8061AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8061ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8061ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8061ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8061ART-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 HGA
AD8061ART-REEL7 −40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 HGA
AD8061ARTZ-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 H0D2
AD8061ARTZ-REEL −40°C to +85°C 5-Lead SOT-23, 13-Inch Tape and Reel RJ-5 H0D2
AD8061ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 H0D2
AD8061AR-EBZ Evaluation Board for 8-Lead SOIC_N
AD8061ART-EBZ Evaluation Board for 5-Lead SOT-23
AD8062AR −40°C to +85°C 8-Lead SOIC_N R-8
AD8062ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD8062ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8062ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8
AD8062ARM −40°C to +85°C 8-Lead MSOP RM-8 HCA
AD8062ARMZ −40°C to +85°C 8-Lead MSOP RM-8 #HCA
AD8062ARMZ-RL −40°C to +85°C 8-Lead MSOP, 13-Inch Tape and Reel RM-8 #HCA
AD8062ARMZ-R7 –40°C to +85°C 8-Lead MSOP, 7-Inch Tape and Reel RM-8 #HCA
AD8062AR-EBZ Evaluation Board for 8-Lead SOIC_N
AD8062ARM-EBZ Evaluation Board for 8-Lead MSOP
AD8063ARZ –40°C to +85°C 8-Lead SOIC_N R-8
AD8063ARZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8
AD8063ARZ-REEL7
–40°C to +85°C
8-Lead SOIC_N, 7-Inch Tape and Reel
R-8
AD8063ART-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 HHA
AD8063ART-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 HHA
AD8063ARTZ-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 H0E3
AD8063ARTZ-REEL –40°C to +85°C 6-Lead SOT-23, 13-Inch Tape and Reel RJ-6 H0E3
AD8063ARTZ-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 H0E3
AD8063AR-EBZ Evaluation Board for 8-Lead SOIC_N
AD8063ART-EBZ Evaluation Board for 6-Lead SOT-23
1 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
2 New branding after data code 0542, previously branded HGA.
3 New branding after data code 0542, previously branded HHA.
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D01065-0-5/13(J)
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