Not For New Design
This is information on a product still in production but not recommended for new designs.
June 2009 Rev 5 1/55
1
NAND512R3A2C
NAND512R4A2C NAND512W3A2C
512-Mbit, 528-byte/264-word page,
1.8 V/3 V, SLC NAND flash memories
Features
●High density NAND flash memories
– 512-Mbit memory array
– Cost effective solutions for mass storage
applications
●NAND interface
– x8 or x16 bus width
– Multiplexed address/ data
●Supply voltage: 1.8 V, 3 V
●Page size
– x8 device: (512 + 16 spare) bytes
– x16 device: (256 + 8 spar e) words
●Block size
– x8 device: (16K + 512 spare) bytes
– x16 device: (8K + 256 spare) words
●Page read/program
– Random access:
12 µs (3 V)/15 µs (1.8 V) (max)
– Sequential access:
30 ns (3 V)/50 ns (1.8 V) (min)
– Page program time: 200 µs (typ)
●Copy back program mode
●Fast block erase: 2 ms (typ)
●Status registe r
●Electronic signature
●Chip Enable ‘don’t care’
●Secur ity features
–OTP area
– Serial number (unique ID) option
●Hardware data protection
– Program/erase locked during power
transitions
●Data integrity
– 100,000 program/erase cycles (with ECC)
– 10 years data retention
●RoHS compliant packages
●Development tools
– Error correction code models
– Bad blo c ks managemen t and wear lev e ling
algorithms
– Hardware simulation models
FBGA
TSOP48 12 x 20 mm (N)
VFBGA55 8 x 10 x 1.05 mm (ZD)
VFBGA63 9 x 11 x 1.05 mm (ZA)
Table 1. Device summary
Reference Root part number
NAND512-A2C
NAND512R3A2C
NAND512R4A2C
NAND512W3A2C
www.numonyx.com
Contents NAND512-A2C
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.1 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.2 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2.3 Sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
NAND512-A2C Contents
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6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7.2 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7.3 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . 28
6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 34
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 46
10.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
List of tables NAND512-A2C
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List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Address insertion, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. NAND flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Program, erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. DC characteristics, 1.8 V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. DC characteristics, 3 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. TSOP48 - 48 lead plastic thin sm all ou tlin e, 12 x 2 0 mm, mecha nic al da ta. . . . . . . . . . . . 49
Table 23. VFBGA55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, mechanical data . 51
Table 24. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15 active ball array, 0. 8 mm pitch, mechanical data 52
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
NAND512-A2C List of figures
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List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. VFBGA55 connections - x8 devices (top view through package). . . . . . . . . . . . . . . . . . . . 10
Figure 5. VFBGA63 connections - x8 devices (top view through package). . . . . . . . . . . . . . . . . . . . 11
Figure 6. Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Copy back operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0
Figure 23. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. Read status register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 25. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Page read A/read B operation AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. Read C operation, one page AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 28. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 29. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 30. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 31. Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32. Program/erase disable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 33. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 34. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 35. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 48
Figure 36. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 37. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 49
Figure 38. VFBGA55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, package outline. . 50
Figure 39. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.8 mm pitch, package outline . . . . . . . . . . . . . . 52
Description NAND512-A2C
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1 Description
The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND technology. It is referred to as the small page family.
The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of
512 Mbits and operate with ei ther a 1. 8 V or 3 V voltag e supp ly. The size of a page is eit her
528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device
has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pi n count and makes it possible to migrate
to other densities without changing the footprint.
To extend the lifetime of NAND flash devices it is strongly recommended to implement an
error correction code (ECC). The use of ECC co rrection allows to achie ve up to 100,000
program/erase cycles for each block. A write protect pin is available to give a hardware
protection against program and erase operations.
The devices feature an open-drain Ready/B usy output that can be used to identify if the
program/erase/read (P/E/R) controller is currently active. The use of an open-drain output
allows the ready/busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back comman d is available to optimize the management of defective b locks. When
a page prog ram oper ation f ails, the data can be prog rammed in anot her page without ha ving
to resend the data to be programmed.
The devices are available in the TSOP48 (12 x 20 mm), VFBGA55 (8 x 10 x 1.05 mm) and
VFBGA63 (9 x 11 x 1.05 mm) packages and in two different versions:
●No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allows to download up to all the pages in a block with one read command and
addressing only the first page to read
●With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are sim ultaneou sly active as Chip Enable tr ansiti ons during
latency do not stop read oper a t ions. Program and erase operations are not inter rupted
by Chip Enable transitions.
They also come with the following security features:
●OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about
this feature are subject to an NDA (non disclosure agreement)
●Serial number (unique identifier) option, which enables each device to be uniquely
identified. It is subject to an NDA and is, therefore, not described in the datasheet.
For more details about these security features, contact your nearest Numonyx sales office.
For information on how to order these devices refer to Table 25: Ordering information
scheme. Devices are shipped from the factory with block 0 always v alid and the memory
content bits, in valid blocks, erased to ’1’.
See Table 2: Product description, for all the devices available in the fa mily.
NAND512-A2C Description
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Figure 1. Logic diagram
Table 2. Product description
Reference Part number Density Bus
width Page
size Block
size Memory
array Operating
voltage
Timings
Package
Random
access
Max
Sequential
access
Min
Page
program
Typ
Block
erase
Typ
NAND512-A2C
NAND512R3A2C
512
Mbits
x8 512+16
bytes 16K+512
bytes 32 pages x
4096 blocks
1.7 to 1.95 V 15 µs 50 ns
200 µs 2 ms TSOP48
VFBGA55
VFBGA63
NAND512W3A 2C 2.7 to 3.6 V 12 µs 30 ns
NAND512R4A2C x16 256+8
words 8K+256
words 1.7 to 1.95 V 15 µs 50 ns
AI07557C
W
I/O8-I/O15, x16
VDD
NAND flash
E
VSS
WP
AL
CL
RB
R
I/O0-I/O7, x8/x16
8
Description NAND512-A2C
8/55
Figure 2. Logic block diagram
Table 3. Signal names
Signal Function Direction
I/O8-15 Data input/ou tputs for x16 devices I/O
I/O0-7 Data input/outputs, address inputs, or command inputs for x8 and
x16 devices I/O
AL Address Latch Enable Input
CL Command Latch Enab le Input
EChip Enable Input
RRead Enable Input
RB Ready/Busy (open-drain output) Output
WWrite Enable Input
WP Write Protect Input
VDD Supply voltage Power supply
VSS Ground Ground
NC Not connected internally –
DU Do not use –
Address
register/counter
Command
interface
logic
P/E/R controller,
high voltage
generator
WP
I/O buffers & latches
I/O8-I/O15, x16
E
W
AI07561c
R
Y decoder
Page buffer
NAND flash
memory array
X decoder
I/O0-I/O7, x8/x16
Command register
CL
AL
RB
NAND512-A2C Description
9/55
Figure 3. TSOP48 connections - x8 devices
I/O3
I/O2
I/O6
R
RB
NC
I/O4
I/O7
AI07585C
NAND flash
(x8)
12
1
13
24 25
36
37
48
E
I/O1
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O5
NC
NC
NC
I/O0
NC
NC
NC
NC
NC
VDD
NC
NC
NC
VSS
NC
NC
NC
NC
Description NAND512-A2C
10/55
Figure 4. VFBGA55 connections - x8 devices (top view through package)
AI09366b
I/O7
WP
I/O4I/O3
NC VDD
I/O5VDD
NC
H
VSS
I/O6
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O0
AL
NC NC
NC
NCNC NC NCNC
NCNC
VSS
NCNC
NC NC
RB
I/O2
NC
DU
I/O1
R
NC
NC
NC
VSS
DU
DU
DUDU
DU
M
L
K
J
NAND512-A2C Description
11/55
Figure 5. VFBGA63 connections - x8 devices (top view through package)
AI07586B
I/O7
WP
I/O4I/O3
NC VDD
I/O5VDD
NC
H
VSS
I/O6
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O0
AL
DU
NC NC
NC
NCNC NC NCNC
NCNC
VSS
NCNC
NC NC
RB
I/O2
DU
NC
DU
I/O1
109
R
NC
NC
NC
VSS
DU
DU DU
DU
DU DU
DU
DU
DU DU
DU
M
L
K
J
Memory array organization NAND512-A2C
12/55
2 Memory array organization
The memory array is made up of NAND structu re s wh er e 16 cells are co nn ected in ser ie s.
The memory array is organized in blocks where each block contains 32 pag es. The array is
split into tw o area s , t he main area an d the spa re ar ea. The main a rea of the array is used to
store data wher eas the spare ar ea is typically used to stor e error correctio n codes , softw are
flags or bad block identification.
In x8 devices the pag es are sp lit into a ma in area with tw o half page s of 25 6 b ytes ea ch and
a spare area of 16 bytes. In the x16 devices the pages are split into a 256-word main area
and an 8-word spare area. Refer to Figure 6: Mem ory array organization.
Bad blocks
The NAND flash 528-byte/ 264-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 7.1: Bad block
management for more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both th e bad b lo c ks that are present when t he device is shipped and the Bad Bloc ks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4. Valid blocks
Density of device Min Max
512 Mbits 4016 4096
NAND512-A2C Memory arr ay organization
13/55
Figure 6. Memory array organization
AI07587
Block = 32 pages
Page = 528 bytes (512+16)
512 bytes
512 Bytes
Spare area
2nd half page
(256 bytes)
16
bytes
Block
8 bits
16
bytes 8 bits
Page
Page buffer, 512 bytes
1st half page
(256 bytes)
Block = 32 pages
Page = 264 words (256+8)
256 words
256 words
Spare area
Main area
8
words
16 bits
8
words 16 bits
Page buffer, 264 words
Block
Page
x8 DEVICES x16 DEVICES
Signal descriptions NAND512-A2C
14/55
3 Signal descriptions
See Figure 1: Logic diagram, and Table 3: Signal nam es , for a brief overview of the signals
connected to this device.
3.1 Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the se lected address, output the data during a read
operation or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I /O7 are left floating when the device is deselected or
the outputs are disabled.
3.2 Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a read operation or input data during a write operation. Command and address
inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3 Address Latc h Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.4 Command Latch Enab le (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.5 Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and read
circuitry. When Chip Enable is Low, VIL, the device is selected.
If Chip Enable goes High (VIH) while the device is busy programming or erasing, the device
remains selected and does not go into standby mode.
While the device is busy reading:
●the Chip Enable input should be held Low during the whole busy time (tBLBH1) for
de vices that do not feature the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes into standby mode.
●for devices that feature the Chip Enable don’t care option, the Chip Enable going High
during the b usy time (tBLBH1) will not interrupt the read operation and the de vice will not
go into standby mode.
NAND512-A2C Signal descriptions
15/55
3.6 Read Enable (R)
The Read Enable, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
3.7 Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input ad dress and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a co mmand. It is r ecommended t o k eep Write Enab le
High during the recovery time.
3.8 Write Protect (WP)
The Write Protect pin is an inpu t that giv es a hardware protecti on against unwanted program
or erase operations. When Write Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to k e ep the Write Prot ect pin L ow, VIL, during po w er-up an d po we r-do wn.
3.9 Ready/Busy (RB)
The Ready/Busy output , RB, is an op en-drain out put that can b e used to identi fy if the P/E/R
controller is currently active.
When Ready/Busy is Low, VOL, a read, program or erase oper ation is in progr ess. When the
operat ion completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interf ace is ready to accept a co mmand. During the reco very time the RB signal is
Low, VOL.
Refer to the Section 10.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resis tor.
3.10 VDD supply voltage
VDD provides the power supply to the internal core of the memory device . It is the main
power supply for all operations (read, program and erase).
An internal voltage det ector disables all functio ns whenev er VDD is belo w the VLKO thre shold
(see Figure 36: Data protection) to protect the device from any in voluntary program/erase
operations during power-transitions.
Each device in a system should ha ve VDD decoupled with a 0.1 µF capacitor . The PCB tr ack
widths should be sufficient to carry the required program and erase currents
Signal descriptions NAND512-A2C
16/55
3.11 VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
NAND512-A2C Bus operations
17/55
4 Bus operations
There are six standard bus op erations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.
4.1 Command input
Command Input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 20 and Table 20 for details of the tim ings requirements.
4.2 Address input
Address input bus operations are used t o input the memory address. Thre e bus cycles are
required to input the addresses for the 128-Mbit and 256-Mbit devices and four bus cycles
are require d to input the addresse s for the 512-Mbit an d 1-Gbit d e vices (re f er to Table 6 and
Table 7, Address Inse rtion).
The addresses a re accepted when Chip Enable is Low, Address Latch Enab le is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresse s.
See Figure 21 and Table 20 for details of the tim ings requirements.
4.3 Data input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The dat a is latched on the rising edge of th e
Write Enable signal. The d ata is input sequentially using the Write Enable signal.
See Figure 22, Table 20, and Table 21 for details of the timings requiremen ts.
4.4 Data output
Data Output bus operations are used to read: the data in the memory array, the stat us
register, the electronic signature and the serial number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 23 and Table 21 for details of the tim ings requirements.
Bus operations NAND512-A2C
18/55
4.5 Write protect
Write protect bus operations are used to protect the memory against program or erase
operations . When the Write Protect signal is Low the de vice will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6 Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5. Bus operations
Bus operation E AL CL R WWP I/O0 - I/O7 I/O8 - I/O15(1)
1. Only for x16 devices.
Command input VIL VIL VIH VIH Rising X(2)
2. WP must be VIH when issuing a program or erase command.
Command X
Address input VIL VIH VIL VIH Rising X Address X
Data input VIL VIL VIL VIH Rising X Data input Data input
Data output VIL VIL VIL Falling VIH X Data output Data output
Write protect X X X X X VIL XX
Standby VIH XX X XX X X
Table 6. Address inse rtion, x8 devices(1)(2)
1. A8 is set Low or High by the 00h or 01h command, see Section 6.1: Pointer operations.
2. Any additional address input cycles is ignored.
Bus
cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st A7 A6 A5 A4 A3 A2 A1 A0
2nd A16 A15 A14 A13 A12 A11 A10 A9
3rd A24 A23 A22 A21 A20 A19 A18 A17
4th VIL VIL VIL VIL VIL VIL VIL A25
Table 7. Address inse rtion, x16 devices(1)(2)
1. A8 is don’t care in x16 devices.
2. Any additional address input cycle is ignored.
Bus
cycle I/O8-
I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st XA7 A6 A5 A4 A3 A2 A1 A0
2nd XA16 A15 A14 A13 A12 A11 A10 A9
3rd XA24 A23 A22 A21 A20 A19 A18 A17
4th(4) X VIL VIL VIL VIL VIL VIL VIL A25
NAND512-A2C Bus operations
19/55
Table 8. Address definition
Address Definition
A0 - A7 Column address
A9 - A25 Page address
A9 - A13 Address in block
A14 - A25 Block address
A8 A8 is set Low or High b y the 00h or 01h command,
and is don’t care in x16 devices
Command set NAND512-A2C
20/55
5 Command set
All bus write operations to the device are interpreted by the comman d interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 9.
Table 9. Commands
Command Bus write operation s (1)(2)
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence is ignored by the device.
Command
accepted during
busy
1st cycle 2nd cycle 3rd cycle
Read A 00h – –
Read B(3)
3. The Read B command (code 01h) is not used in x16 devices.
01h – –
Read C 50h – –
Read Electronic Signature 90h – –
Read Status Register 70h – – Yes
Page Program 80h 10h –
Copy Back Program 00h 8Ah (10h)(4)
4. The Program Confirm command (code 10h) is no more necessary for NAND512-A2C devices. It is optional
and has been maintained f or backward compatibility.
Block Erase 60h D0h –
Reset FFh – – Yes
NAND512-A2C Device operations
21/55
6 Device operations
6.1 Pointer operations
As the NAND flash memories contain two different areas f or x16 devices and three different
areas for x8 devices (see Figure 7) the read com m an d code s (0 0h , 01 h, 50h) are used to
act as pointers to the different areas of the memory arra y (they select the most significant
column address).
The Read A and Read B commands a ct as pointers to the main memory area. Their use
depends on the bus width of the device.
●In x16 devices the Read A command (00h) sets the pointer to area A (the whole of t he
main area) that is words 0 to 255.
●In x8 de vices the Read A command (00h) sets the poin ter to area A (the first ha lf of the
main area) that is bytes 0 to 255, and the Read B command (01 h) sets the pointer to
area B (the second half of the main area) that is bytes 256 to 511.
In both the x8 a nd x1 6 devices the Read C command (50h ), a cts as a pointer to ar ea C (the
spare memory area) that is bytes 512 to 527 or words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the
respective areas until another pointer code is issued. However, the Read B command is
effective for only one operation, once an operation has been execut ed in area B the pointer
returns automatically to area A.
The pointer ope ration s can also be used bef or e a prog ram op era tion, that is the appropriate
code (00h, 01h or 50h) can be issued before the program command 80h is issued (see
Figure 8).
Figure 7. Pointer operations
AI07592
Area A
(00h)
A
Area B
(01h) Area C
(50h)
bytes 0 - 255 bytes 256 - 511 bytes
512 - 527
CB
Pointer
(00h,01h,50h)
Page buffer
Area A
(00h)
A
Area C
(50h)
words 0 - 255 words
256 - 263
C
Pointer
(00h,50h)
Page buffer
x8 devices x16 devices
Device operations NAND512-A2C
22/55
Figure 8. Pointer operations for programming
6.2 Read memory array
Each operation to read the memory area starts with a pointer oper ation as shown in the
Section 6.1: Pointer operations . Once the area ( main or sp are) has be en select ed using th e
Read A, Read B or Read C commands four bus cycles (for 512-Mbit and 1-Gbit devices) or
three bus cycles (f or 128-Mbit and 256-Mbit de vices) are required to input the address (refer
to Table 6 and Table 7) of the data to be read.
The device defaults to read A mode after power-up or a reset operation.
When reading the spare area addresses:
●A0 to A3 (x8 devices)
●A0 to A2 (x16 devices)
are used to set the start address of the spare area while addresses:
●A4 to A7 (x8 devices)
●A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have been issued they do not need to be reissued
for subsequent read operations as the pointer remains in the respective area. However, the
Read B command is effective for only one operation, once an operation has been executed
in area B the pointer returns automatically to area A and so another Read B command is
required to st art another read operation in area B.
Once a Read command is issued tw o types of operations are available: random read and
page read.
6.2.1 Random read
Each time the command is issued the first read is random read.
ai07591
I/O Address
Inputs Data Input 10h
80h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA A
00h Address
Inputs Data Input 10h
80h
00h
I/O Address
Inputs Data Input 10h
80h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA B
01h Address
Inputs Data Input 10h
80h
01h
I/O Address
Inputs Data Input 10h
80h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
AREA C
50h Address
Inputs Data Input 10h
80h
50h
NAND512-A2C Device operations
23/55
6.2.2 Page read
After the random read access the page data is transferred to the page buffer in a time of
tWHBH (refer to Table 21 for value). Once the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequentially (from selected column address to
last column address) by pulsing the Read Enable signal.
Figure 9. Read (A,B,C) operations
6.2.3 Sequential row read
After the data in last column of the page is output, if the Read Enable signal is pulsed and
Chip Enable remains Low, then the next page is automatically loaded into t he page buffer
and the read ope rat ion contin ues . A sequen tial ro w read ope rat ion can only be used to read
within a b lock. If the block changes a new read command must be issued. Refer to
Figure 10: Sequential row read operations and Figure 11: Sequent ial row read block
diagrams for details about se quential row read operations. To terminate a sequential row
read operation, set to High the Chip Enable signal for more than tEHEL. Sequential row read
is not available when the Chip Enable don’t care option is enabled.
CL
E
W
AL
R
I/O
RB
00h/
01h/ 50h
ai07595c
Busy
Command
code
Address input Data output (sequentially)
tBLBH1
(read)
Device operations NAND512-A2C
24/55
Figure 10. Sequential row read operatio ns
Figure 11. Sequential r ow read block diagrams
Figure 12. Read block diagrams
1. Highest address depends on device density.
I/O
RB
Address inputs
ai07597
1st
page output
Busy
tBLBH1
(Read busy time)
00h/
01h/ 50h
Command
code
2nd
page output Nth
page output
BusyBusy
tBLBH1 tBLBH1
AI07598
Block
Area A
(1st half Page)
Read A command, x8 devices
Area B
(2nd half Page) Area C
(Spare) Area A
(main area) Area C
(Spare)
Read A command, x16 devices
Read B command, x8 devices Read C command, x8/x16 devices
Area A Area A/ B Area C
(Spare)
Area A
(1st half Page) Area B
(2nd half Page) Area C
(Spare)
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
1st page
2nd page
Nth page
Block
Block
Block
AI07596
A0-A7
A9-A26(1)
Area A
(1st half page)
Read A command, x8 devices
Area B
(2nd half page) Area C
(spare) Area A
(main area) Area C
(spare)
A0-A7
Read A command, x16 devices
A0-A7
Read B command, x8 devices
Area A
(1st half page) Area B
(2nd half page) Area C
(spare)
A0-A3 (x 8)
A0-A2 (x 16)
Read C command, x8/x16 devices
Area A Area A/ B Area C
(spare)
A9-A26(1)
A9-A26(1)
A9-A26(1)
A4-A7 (x 8), A3-A7 (x 16) are don't care
NAND512-A2C Device operations
25/55
6.3 Page program
The page prog ram o peration is t he standard op eration to p rogram data to the memo ry arra y.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before starting a page program operation a pointer operation can be performed to point to
the area to be programmed. Refer to the Section 6.1: Pointer operations and Figure 8 for
details.
Each page program operation co ns ists of five steps (see Figure 13):
1. One bus cycle is required to setup the Page Program command
2. Four bus cycles are then required to input the program address (refer to Table 6 and
Table 7)
3. The data is then input (up to 528 bytes/264 words) and loaded into the page buffer
4. One bus cycle is required to issue the confirm command to start the P/E/R controller
5. The P/E/R controller then programs the data into the arra y.
Once the prog ram operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successf ully programmed to '0'.
During the program operatio n, only the Read Status Register and Reset commands are
accepted, all other commands are ignored.
Once the prog r am oper a tion has co mplete d the P/E/ R contro ller bit SR6 is set t o ‘1’ and t he
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Figure 13. Page pr ogram operation
1. Before starting a page program operation a pointer operation can be performed. Refer to Section 6.1: Pointer operations for
details.
I/O
RB
Address Inputs SR0
ai07566
Data Input 10h 70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
Busy
tBLBH2
(Program Busy time)
Device operations NAND512-A2C
26/55
6.4 Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another pa g e.
The cop y bac k prog ram o peration d oes not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operat ion is particularly useful when a portion of a bloc k is update d and the re st of the b lock
needs to be copied to the newly assigne d block.
If the copy back program operation fails an error is signalled in the status register. However
as the standard external ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the number of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back progr am operation requires two steps:
1. The source page must be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 words/ 528 bytes from the page into the page buff er
2. When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 10 for the addresses that mu st be the same for the source and target
pages
3. The Program Confirm command (code 10h) is no more necessary on NAND512-A2C
devices. It is optional and has been maintained for backward compatibility.
After a copy back program operation, a partial-page program is not allowed in the target
page until the block has been erased.
See Figure 14 for an example of the copy back operation.
Figure 14. Copy ba ck operation
1. The Program Confirm command (code 10h) is no more necessary on NAND512-A2C devices. It is optional and has been
maintained for backward compatibility.
Table 10. Copy back program addresses
Density Same address for source and target pages
512 Mbits A25
I/O
RB
Source
Address Inputs SR0
ai13187
8Ah 70h00h
Copy Back
Code
Read
Code Read Status Register
Target
Address Inputs
tBLBH1
(Read Busy time)
10h(1)
Busy
tBLBH2
(Program Busy time)
NAND512-A2C Device operations
27/55
6.5 Block erase
Erase operations are done one block at a time. An erase operation sets all of th e bits in the
addressed block to ‘1’. All previous data in the bl ock is lost.
An erase operation consists of three steps (refer to Figure 15):
1. One bus cycle is required to setup the Block Erase command
2. Only three b us cycles f or 512-Mbit and 1-Gbit device s, or two f or 128-Mbit and 256-Mbit
devices are required to input the block address. The first cycle (A0 to A7) is not
required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the last
address cycle I/O2 to I/O7 must be set to VIL.
3. One bus cycle is required to issue the confirm command to start the P/E/R controller.
Once the erase operation has completed the status reg ister can be checked for errors.
Figure 15. Block erase operation
6.6 Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the oper ation that the de vice w as p erf o rming when the command was
issued, refer to Table 21 for the values.
I/O
RB
Block Address
Inputs SR0
ai07593
D0h 70h
60h
Block Erase
Setup Code Confirm
Code Read Status Register
Busy
tBLBH3
(Erase Busy time)
Device operations NAND512-A2C
28/55
6.7 Read status register
The device contains a status register which provides information on the current or previous
program or erase ope ration. The various bits in th e status register convey information and
errors on the operation.
The status register is read by issuing the Read Stat us Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
de vice separately, e ven when the Rea dy/Busy pins are common-wired. It is not ne cessary to
toggle the Chip Enable or Read Enable signals to update the content s of the status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Theref ore if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read .
The status registe r bits are summarized in Table 11: Status register bits. Refer to Table 11 in
conjunction with the following text descriptions.
6.7.1 Write protection bit (SR7)
The write protection bit can be used to identify if the device is protected or not. If the write
protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.7.2 P/E/R controller bit (SR6)
The program/erase /read controller bit indicates whet her the P/E/R controller is active or
inactive . When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.7.3 Error bit (SR0)
T he err or bit is used to identif y if a ny errors have been detected by th e P/E/ R cont ro ller. The
error bit is set to ’ 1’ when a progr am or er ase operat ion has f ailed to write the corre ct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully.
6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved
Table 11. Status register bits
Bit Name Logic level Definition
SR7 Write protect i on '1' Not protected
'0' Protected
SR6 Program/ erase/ read controller '1' P/E/R C inactive, device ready
'0' P/E/R C active, device busy
SR5, SR4, SR3, SR2, SR1 Reserved Don’t care
SR0 Generic error ‘1’ Error – operation failed
‘0’ No error – operation successful
NAND512-A2C Device operations
29/55
6.8 Read electronic signature
The device contains a manufacturer code and device code. To read th ese codes two steps
are required :
1. first use one bus write cycle to issue the Read Elect ro nic Sig natu re com m an d (9 0h ),
followed by an address input of 00h
2. then perform two bus read operations – the first reads the manufacturer code and the
second, the device code. Further bus read operations are ignored.
Refer to Table 12: Electronic signature, for information on the addresses.
Table 12. Electronic signature
Part number Manufacturer code Device code
NAND512R3A2C 20h 36h
NAND512W3A2C 76h
NAND512R4A2C 0020h 0046h
Software algorithms NAND512-A2C
30/55
7 Software algorithms
This section gives information on the software algorithms that Numonyx re commends to
implement to mana ge the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are prog rammed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage f or e xtended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see Table 14: Progr am, er ase times and prog r am erase end ura nce cycles for value)
and it is recommended to implement garbage collection, a wear-leveling al gorithm and an
error correction code, to extend the number of program and erase cycles and increase the
data retention.
To help integrate a NAND memory into an application Numonyx can provide a full ra nge of
software solutions: file system, sector management, drivers, and code management.
Contact the near est Numonyx sales office or visit www.numonyx.com for more details.
7.1 Bad block management
Devices with bad bl ocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block infor m ation is written prior to shipping. Any block where the 6th byte (x8 device)/1st
word (x16 device) in the spare area of the 1st page does not contain FFh is a bad block.
The bad block information must be read be fore any e rase is attempted as the bad block
inf o rmation ma y be e r ased. For the system to be able to recognize the bad blocks based on
the original inf ormation it is recommended to create a bad b loc k tab le f ollowing the f lowchart
shown in Figure 16.
7.2 NAND flash memory failure modes
Over the lifetime of the device additional bad blocks may develop.
To implement a highly reliable system, all the possible failure modes must be considered:
●Program/erase fa ilure: in this case the block has to be replaced by cop ying the data to a
valid block. These additional bad blocks can be identified as attempts to program or
erase them will give errors in the status register.
As the f ailure of a page progr am operat ion does not aff ect the data in other page s in the
same bl ock, t he bloc k can be repl aced by re-pr ogrammin g the current data and cop ying
the rest of the replaced block to an available valid block. The Copy Back Program
command can be use d to co py the data to a valid block. See Section 6.4: Copy back
program for more details
●Read failure: in this case, ECC correction must be implemented. To efficiently use the
memory space, it is mandatory to recover single-bit errors, which occur during read
operations, by using ECC without replacing the whole block.
Refer to Table 13 for the procedure to follow if an error occurs during an operation.
NAND512-A2C Soft wa re al go rit h ms
31/55
Figure 16. Bad block management flowchart
Table 13. NAND flash failure modes
Operation Procedure
Erase Block Replacement
Program Block Replacement
Read ECC
AI07588C
START
END
NO
YES
YES
NO
Block Address =
Block 0
Data
= FFh?
Last
block?
Increment
Block Address
Update
Bad Block table
Software algorithms NAND512-A2C
32/55
7.3 Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 17).
Figure 17. Garbage collection
7.4 Wear-leveling algorithm
For write-intensiv e applications, it is recommended to implement a wear-leveling algorithm
to monitor and sprea d the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leve ling levels:
●First level wear-leveling, new data is programmed to the free blocks that have had the
few est write cycles
●Second lev el wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
7.5 Error correction code
An error correction code (ECC) can be implemented in the NAND flash memories to identify
and correct errors in the data.
F or e very 2048 bits in the de vice the implementa tion of 22 bits of ECC (16 bits f or line parity
plus 6 bits for column parity ) is req uir ed .
Valid
page
Invalid
page Free
page
(erased)
Old area
AI07599B
New area (after GC)
NAND512-A2C Soft wa re al go rit h ms
33/55
An ECC model is av ailable in VHDL or Verilog. Contact the nearest Numonyx sales of fice for
more details.
Figure 18. Err or detection
7.6 Hardware simulation models
7.6.1 Behavioral simulation models
Denali softw are corporation models are pl atf orm independent fun ctional models designe d to
assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logi c behavior and timings of NAND flash devices, and so allow
software to be developed before hardware.
7.6.2 IBIS simulations models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
These models provide information such as AC characteristics , rise/fall times and package
mechanical data, all of which are measured or simula ted at v oltage and te mperatur e ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
New ECC generated
during read
XOR previous ECC
with new ECC
All results
= zero?
22 bit data = 0
YES
11 bit data = 1
NO
1 bit data = 1
Correctable
Error ECC Error
No Error
ai08332
>1 bit
= zero?
YES
NO
Program and erase times and endurance cycles NAND512-A2C
34/55
8 Program and erase times and endurance cycles
The progr am and eras e times and th e number of prog r am/er ase cycles per b lock are shown
in Table 14.
9 Maximum ratings
Stressing the device above the ratings listed in Table 15: Absolute maximum ratings, may
cause permanent damage to the device. These are stress ratings only and oper ation of the
device at these or any other conditions above t hose indicated in the operating sections of
this specification is not implied. Exp osur e to abso lute maximum rating conditions for
extended periods may affect device reliability.
Table 14. Program, erase times and program erase endurance cycles
Parameters NAND flash Unit
Min Typ Max
Page program time 200 500 µs
Block erase time 23ms
Program/erase cycles per block (with ECC) 100,000 cycles
Data retention 10 years
Table 15. Absolute maxim um ratings
Symbol Parameter Value Unit
Min Max
TBIAS Temperature under bias – 50 125 °C
TSTG Storage temperature – 65 150 °C
TLEAD Lead temperature during soldering 260 °C
VIO(1)
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
Input or output voltage 1.8 V devices – 0.6 2.7 V
3 V devices – 0.6 4.6 V
VDD Supply voltage 1.8 V devic es – 0.6 2.7 V
3 V devices – 0.6 4.6 V
NAND512-A2C DC and AC parameters
35/55
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parame ters in the DC and AC characteristics table s t hat
follow, are derived from tests performed under the measurement conditions summarized in
Table 16: Operating and AC measurement conditions. Design er s sho u l d che ck that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 16. Operating and AC measurement conditions
Parameter NAND flash Units
Min Max
Supply voltage (VDD)1.8 V devices 1.7 1.95 V
3 V devices 2.7 3.6 V
Ambient temperature (TA) Grade 6 –40 85 °C
Load capacitance (CL) (1 TTL GATE
and CL)1.8 V devices 30 pF
3 V devices 50 pF
Input pulses voltages 1.8 V devices 0 VDD V
3 V devices 0.4 2.4 V
Input and output timing ref. voltages 1.8 V de vices 0.9 V
3 V devices 1.5 V
Input rise and fall times 5 ns
Output circuit resistors, Rref 8.35 kΩ
Table 17. Capacitance(1)(2)
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double on stacked devices.
Symbol Parameter Test conditions Typ Max Unit
CIN Input capacitance VIN = 0 V 10 pF
CI/O Input/output
capacitance VIL = 0 V 10 pF
DC and AC parameters NAND512-A2C
36/55
M
Figure 19. Equivalent testing circuit f or AC characteristics measurement
Table 18. DC characteri stics, 1.8 V devices(1)
Symbol Parameter Test conditions Min Typ Max Unit
IDD1
Operating current
Sequential
read tRLRL minimum
E=VIL, IOUT = 0 mA –815mA
IDD2 Program – – 8 15 mA
IDD3 Erase – – 8 15 mA
IDD5 Standby current (CMOS) E=V
DD -0.2,
WP=0/VDD –10 50 µA
ILI Input leakage current VIN = 0 to VDDmax – – ±10 µA
ILO Output leakage current VOUT = 0 to VDDmax – – ±10 µA
VIH Input high voltage – VDD -0.4 – VDD +0.3 V
VIL Input low voltage –-0.3 –0.4 V
VOH Output high voltage level IOH = -100 µA VDD-0.1 – - V
VOL Output low voltage level IOL = 100 µA – – 0.1 V
IOL (RB)Output low current (RB) VOL = 0.1 V 3 4 mA
VLKO VDD supply voltage (erase and
program lockout) – – – 1.1 V
1. Leakage currents double on stacked devices.
Ai11085
NAND flash
CL
2Rref
VDD
2Rref
GND
GND
NAND512-A2C DC and AC parameters
37/55
Table 19. DC characteristics, 3 V devices(1)
Symbol Para meter Test conditions Min Typ Max Unit
IDD1
Operating current
Sequential
read tRLRL minimum
E=V
IL, IOUT =0mA –1020mA
IDD2 Program – – 10 20 mA
IDD3 Erase – – 10 20 mA
IDD4 Standby current (TTL), E=VIH, WP=0V/VDD ––1mA
IDD5 Standby current (CMOS) E=VDD-0.2, WP=0/VDD –10 50 µA
ILI Input leakage current VIN= 0 to VDDmax – – ±10 µA
ILO Output leakage current VOUT= 0 to VDDmax – – ±10 µA
VIH Input high voltage –2.0 – VDD+0.3 V
VIL Input low voltage –−0.3 –0.8 V
VOH Output high voltage level IOH = −400 µA 2.4 – – V
VOL Output low voltage level IOL = 2.1 mA – – 0.4 V
IOL (RB)Output low current (RB) VOL = 0.4 V 810 mA
VLKO VDD supply voltage (erase and
program lockout) – – – 1.5 V
1. Leakage currents double on stacked devices.
Table 20. AC characteristics for command, address, data input
Symbol Alt.
symbol Parameter 1.8 V
devices 3V
devices Unit
tALLWH tALS Address Latch Low to Write Enable High AL setup time Min 25 15 ns
tALHWH Address Latch High to Write Enable High
tCLHWH tCLS Command Latch High to Write Enable High CL setup time Min 25 15 ns
tCLLWH Command Latch Low to Write Enable High
tDVWH tDS Data Valid to Write Enable High Data setup time Min 20 15 ns
tELWH tCS Chip Enable Low to Write Enable High E setup time Min 30 20 ns
tWHALH tALH Write Enable High to Address Latch High AL hold time Min 10 5ns
tWHALL Write Enable High to Address Latch Low
tWHCLH tCLH Write Enable High to Command Latch High CL hold time Min 10 5ns
tWHCLL Write Enable High to Command Latch Low
tWHDX tDH Write Enable High to Data Transition Data ho ld time Min 10 5ns
tWHEH tCH Write Enable High to Chip Enable High E hold time Min 10 5ns
tWHWL tWH Write Enable High to Write Enable Low W High hold
time Min 15 10 ns
tWLWH tWP Write Enabl e L ow to Write Enable Hig h W pulse width Min 25 15 ns
tWLWL tWC Write Enabl e L ow to Write Enable Low Write cycle time Min 45 30 ns
DC and AC parameters NAND512-A2C
38/55
Table 21. AC characteristics for operations
Symbol Alt.
symbol Parameter 1.8 V
devices 3V
devices Unit
tALLRL1 tAR Address Latch Low to
Read Enable Low Read electronic signature Min 10 10 ns
tALLRL2 Read cycle Min 10 10 ns
tBHRL tRR Ready/Busy High to Read Enable Low Min 20 20 ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read busy time Max 15 12 µs
tBLBH2 tPROG Program busy time Max 500 500 µs
tBLBH3 tBERS Erase bu sy time Max 3 3 ms
tBLBH4 tRST
Reset busy time, during ready Max 5 5 µs
Reset busy time, during read Max 5 5 µs
Reset busy time, during program Max 10 10 µs
Reset busy time, during erase Max 500 500 µs
tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 10 ns
tDZRL tIR Data Hi-Z to Read Enable Low Min 0 0 ns
tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 30 30 ns
tELQV tCEA Chip Enable Low to Output Valid Max 45 35 ns
tRHRL tREH Read Enable High to
Read Enable Low Read Enable High hold time Min 15 10 ns
tRHQZ tRHZ Read Enable High to Output Hi-Z Max 30 30 ns
tEHQX TOH Chip Enable High or Read Enable High to Output Hold Min 10 10 ns
tRHQX
tRLRH tRP Read Enable Low to
Read Enable High Read Enable pulse width Min 25 15 ns
tRLRL tRC Read Enable Low to
Read Enable Low Read cycle time Min 50 30 ns
tRLQV tREA Read Enable Low to
Output Valid Read Enable access time Max 30 18 ns
Read ES access time(1)
tWHBH tRWrite Enable High to
Ready/Busy High Read busy time Max 15 12 µs
tWHBL tWB Write Enable High to Ready/Busy Low Max 100 100 ns
tWHRL tWHR Write Enable High to Read Enable Low Min 60 60 ns
tVHWH
tVLWH(2) tWW Write protection time Min 100 100 ns
1. ES = electronic signature.
2. During a program/erase enable operation, tVHWH is the delay from WP High to W High. During a program/erase disable
operation, tVLWH is the delay from WP Low to W High.
NAND512-A2C DC and AC parameters
39/55
Figure 20. Command Latch AC waveforms
Figure 21. Address Latch AC wavef orms
ai13105
CL
E
W
AL
I/O
tCLHWH
tELWH
tWHCLL
tWHEH
tWLWH
tALLWH tWHALH
Command
tDVWH tWHDX
(CL Setup time) (CL Hold time)
(Data Setup time) (Data Hold time)
(ALSetup time) (AL Hold time)
H(E Setup time) (E Hold time)
ai13106
CL
E
W
AL
I/O
tWLWH
tELWH tWLWL
tCLLWH
tWHWL
tALHWH
tDVWH
tWLWL tWLWL
tWLWHtWLWH tWLWH
tWHWL tWHWL
tWHDX
tWHALL
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
tWHALL
Adrress
cycle 1
tWHALL
(AL Setup time)
(AL Hold time)
Adrress
cycle 4
Adrress
cycle 3
Adrress
cycle 2
(CL Setup time)
(Data Setup time)
(Data Hold time)
(E Setup time)
Adrress
cycle 5
tWLWL
tWLWH
tDVWH
tWHDX
tWHWL
tWHALL
DC and AC parameters NAND512-A2C
40/55
Figure 22. Data Input Latch AC waveforms
Figure 23. Sequential data output after read AC waveforms
1. CL = Low, AL = Low, W = High.
tWHCLH
CL
E
AL
W
I/O
tALLWH
tWLWL
tWLWH
tWHEH
tWLWH
tWLWH
Data In 0 Data In 1 Data In
Last
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
ai13107
(Data Setup time)
(Data Hold time)
(ALSetup time)
(CL Hold time)
(E Hold time)
tEHQX
tEHQZ
ai08031b
NAND512-A2C DC and AC parameters
41/55
Figure 24. Read status register AC waveforms
Figure 25. Read electronic signature AC waveforms
1. Refer to Table 12 for the values of the manufacturer and device codes.
tEHQX
ai08032c
tCLHWH
tELWH
90h 00h Man.
code Device
code
CL
E
W
AL
R
I/O
tRLQV
Read Electronic
Signature
Command
1st Cycle
Address Manufacturer and
Device Codes
ai08039b
(Read ES Access time)
tALLRL1
DC and AC parameters NAND512-A2C
42/55
Figure 26. Page read A/read B operation AC waveforms
CL
E
W
AL
R
I/O
RB
tWLWL
tWHBL
tALLRL2
00h or
01h
Data
NData
N+1 Data
N+2 Data
Last
tWHBH tRLRL
tEHQZ
tRHQZ
ai08033c
Busy
Command
Code Address N Input Data Output
from Address N to Last Byte or Word in Page
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Read Cycle time)
tRLRH
tBLBH1
tRHQX
tEHQX
NAND512-A2C DC and AC parameters
43/55
Figure 27. Read C operation, one page AC waveforms
1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are don’t care.
CL
E
W
AL
R
I/O
RB
tWHALL
Data M Data
Last
tALLRL2
ai08035b
tWHBH
tBHRL
50h Add. M
cycle 1 Add. M
cycle 4
Add. M
cycle 3
Add. M
cycle 2
Busy
Command
Code Address M Input Data Output from M to
Last Byte or Word in Area C
DC and AC parameters NAND512-A2C
44/55
Figure 28. Page pr ogram AC waveforms
CL
E
W
AL
R
I/O
RB
SR0
ai08037
N
Last 10h
70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
tWLWL tWLWL tWLWL
tWHBL
tBLBH2
Page
Program
Address Input Data Input
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Write Cycle time)
(Program Busy time)
NAND512-A2C DC and AC parameters
45/55
Figure 29. Block erase AC waveforms
Figure 30. Reset AC waveforms
D0h60h SR0
70h
ai08038b
tWHBL
tWLWL
tBLBH3
Block Erase
Setup Command Block Erase
CL
E
W
AL
R
I/O
RB
Confirm
Code Read Status Register
Block Address Input
(Erase Busy time)
(Write Cycle time)
Add.
cycle 1 Add.
cycle 3
Add.
cycle 2
W
R
I/O
RB
tBLBH4
AL
CL
FFh
ai08043
(Reset Busy time)
DC and AC parameters NAND512-A2C
46/55
Figure 31. Program/erase enable waveforms
Figure 32. Pr ogram/erase disable waveforms
10.1 Ready/Busy signal electrical characteristics
Figure 33, Figure 34 and Figure 35 show the electrical characteristics for the Ready/Busy
signal. The v alue required for the resistor RP can be calculated using the following equation:
So,
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP
max is determined by the maximum value of tr.
W
RB
tVHWH
ai12477
WP
I/O 80h 10h
W
RB
tVLWH
ai12478
WP
I/O 80h 10h
High
RPmin VDDmax VOLmax
–()
IOL IL
+
-------------------------------------------------------------=
RPmin 1.8V()
1.85V
3mA IL
+
---------------------------=
RPmin 3V() 3.2V
8mA IL
+
---------------------------=
NAND512-A2C DC and AC parameters
47/55
Figure 33. Ready/Busy AC waveform
Figure 34. Ready/Busy load c ircuit
NI3087
busy
VOH
ready VDD
VOL
tftr
1.8 V device - VOL: 0.1 V, VOH : VDD - 0.1 V
3.3 V device - VOL: 0.4 V, VOH : 2.4 V
AI07563B
RP
VDD
VSS
RB
DEVICE
Open Drain Output
ibusy
DC and AC parameters NAND512-A2C
48/55
Figure 35. Resistor value versus waveform timings for Ready/Busy signal
1. T = 25°C.
10.2 Data protection
The Numonyx NAND device is designed to guarantee data protection during power
transitions.
A VDD detection cir cuit disables all NAND operations, if VDD is below the VLKO threshold.
In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept
Low (VIL) to guarantee hardware protection during power transitions as shown in the figure
below (Figure 36).
Figure 36. Data protection
Ai13188
VLKO
VDD
WP
Nominal Range
Locked
Locked
NAND512-A2C Package mechanical
49/55
11 Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related t o soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 37. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1. Drawing is not to scale.
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
Table 22. TSOP48 - 48 lead pl astic thin small outline, 12 x 20 mm, mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.200.047
A1 0.10 0.05 0.15 0.004 0.002 0.006
A2 1.00 0.95 1.05 0.039 0.037 0.041
B 0.22 0.17 0.27 0.009 0.007 0.011
C 0.10 0.21 0.004 0.008
CP 0.08 0.003
D1 12.00 11.90 12.10 0.472 0.468 0.476
E 20.00 19.80 20.20 0.787 0.779 0.795
E1 18.40 18.30 18.50 0.724 0.720 0.728
e 0.50 – – 0.020 – –
L 0.60 0.50 0.70 0.024 0.020 0.028
L1 0.80 0.031
α3° 0° 5° 3° 0° 5°
Package mechanical NAND512-A2C
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Figure 38. VFBGA55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, package outline
1. Drawing is not to scale.
D1
D
e
b
SD
BGA-Z61
ddd
A2
A1
A
SE E2
FE1
E1 E
D2
FE
FD1
FD
NAND512-A2C Package mechanical
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Table 23. VFBGA55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.05 0.041
A1 0.25 0.010
A2 0.65 0.026
b 0.45 0.40 0.50 0.018 0.016 0.020
D 8.00 7.90 8.10 0.315 0.311 0.319
D1 4.00 0.157
D2 5.60 0.220
ddd 0.10 0.004
E 10.00 9.90 10.10 0.394 0.390 0.398
E1 5.60 0.220
E2 8.80 0.346
e 0.80 0.031
FD 2.00 0.079
FD1 1.20 0.047
FE 2.20 0.087
FE1 0.60 0.024
SD 0.40 0.016
SE 0.40 0.016
Package mechanical NAND512-A2C
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Figure 39. VFBGA63 9x11x1.05mm - 6x8+15, 0.8 mm pitch, package outline
1. Drawing is not to scale.
E
D
e
D1
SD FD
SE
b
A2
FE
A1
A
BGA-Z75
ddd
FD1
D2
E2 E1
e
FE1
BALL "A1"
Table 24. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15 active ball arra y, 0.8 mm pitch, mec hanic al data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.05 0.041
A1 0.25 0.010
A2 0.65 0.026
b 0.45 0.40 0.50 0.018 0.016 0.020
D 9.00 8.90 9.10 0.354 0.350 0.358
D1 4.00 0.157
D2 7.20 0.283
ddd 0.10 0.004
E 11.00 10.90 11.10 0.433 0.429 0.437
E1 5.60 0.220
E2 8.80 0.346
e 0.80 0.031
FD 2.50 0.098
FD1 0.90 0.035
FE 2.70 0.106
FE1 1.10 0.043
SD 0.40 0.016
SE 0.40 0.016
NAND512-A2C Ordering information
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12 Ordering information
Note: Not all combinations are necessarily available. For a list of available devices or for further
information on any aspect of these products, ple ase contact your nearest Numonyx sales
office.
Table 25. Ordering information scheme
Example: NAND512R3A 2 C ZA 6 E
Device type
NAND = NAND flash memory
Density
512 = 512 Mbits
Operatin g voltage
R = VDD = 1.7 to 1.95 V
W = VDD = 2.7 to 3.6 V
Bus width
3 = x8
4 = x16
Family identifier
A = 528-byte/ 264-word page
Device options
0 = No option (Chip Enable ‘care’; sequential row read enabled)
2 = Chip Enable don’t care enabled
Prod uct version
C = third version
Package
N = TSOP48 12 x 20 mm
ZD = VFBGA55 8 x 10 x 1.05 mm
ZA = VFBGA63 9 x 11 x 1.05 mm
Temperature range
6 = –40 to 85 °C
Option
E = RoHS compliant package , standard packing
F = RoHS compliant package, tape & reel pack ing
Revision history NAND512-A2C
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13 Revision history
Table 26. Document revision history
Date Revision Changes
26-Oct-2006 0.1 Initial release.
08-Feb-2007 1
Datasheet status upgraded to ‘full datasheet’.
USOP48 package removed.
Data integrity of 100,000 specified for ECC implemented.
tWHBH1 removed from Table 21: AC characteristics for operations.
19-Mar-2008 2
Added: tvHWH and tVLWH in Tab le 21: AC characteristics for
operations, note 2 below the same table, Figure 31: Program/erase
enable waveforms and Figure 32: Program/erase disab le w avefo rms.
Modified: Section 3.9: Ready/Busy (RB), procedure for program
failure in Table 13: NAND flash failure modes, maximum value for
VLKO in Table 19: DC characteristics, 3 V devices and Figure 24:
Read status register AC waveforms.
Minor text changes.
14-May-2008 3 Applied Numonyx branding.
24-Sep-2008 4 Added the sequential row read option and the package VFBGA55
throughout the document.
09-Jun-2009 5
Document status upgraded from ‘full datasheet’ to ‘not for new
design’. Added security features on the co v er page and in Section 1:
Description. Updated Figure 33: Ready/Busy AC waveform and
Figure 35: Re sistor value versus waveform timings for Ready/Busy
signal. References to ECOPACK removed and replaced by RoHS
compliance. Modified dimension A2 of the VFBGA55 and VFBGA63
packages in Table 23 and Table 24. Removed NAND512W4A2C root
part number throughout the documen t.
NAND512-A2C
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