2015 Microchip Technology Inc. DS20005385A-page 1
MCP6V71/1U
Features
• High DC Precision (VDD = 5.5V):
-V
OS Drift: ±15 nV/°C (maximum)
-V
OS: ±8 µV (maximum)
-A
OL: 126 dB (minimum)
- PSRR: 115 dB (minimum)
- CMRR: 117 dB (minimum)
-E
ni: 0.45 µVP-P (typical), f = 0.1 Hz to 10 Hz
-E
ni: 0.15 µVP-P (typical), f = 0.01 Hz to 1 Hz
• Enhanced EMI Protection:
- Electromagnetic Interference Rejection Ratio
(EMIRR) at 1.8 GHz: 96 dB
• Low Power and Supply Voltages:
-I
Q: 170 µA/amplifier (typical)
- Wide Supply Voltage Range: 2V to 5.5V
• Small Packages:
- Singles in SC70, SOT-23
•Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 2 MHz (typical)
- Unity Gain Stable
• Extended Temperature Range: -40°C to +125°C
Typical Applications
• Portable Instrumentation
• Sensor Conditioning
• Temperature Measurement
• DC Offset Correction
• Medical Instrumentation
Design Aids
•FilterLab
® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Related Parts
• MCP6V01/2/3: Auto-Zeroed, Spread Clock
• MCP6V06/7/8: Auto-Zeroed
• MCP6V26/7/8: Auto-Zeroed, Low Noise
• MCP6V11/1U/2/4: Zero-Drift, Low Power
• MCP6V31/1U/2/4
• MCP6V61/1U: Zero-Drift 1MHz
Description
The Microchip Technology Inc. MCP6V71/1U family of
operational amplifiers provides input offset voltage
correction for very low offset and offset drift. These are
low-power devices, with a gain bandwidth product of
2 MHz (typical). They are unity gain stable, have virtu-
ally no 1/f noise, and have good Power Supply Rejec-
tion Ratio (PSRR) and Common Mode Rejection Ratio
(CMRR). These products operate with a single supply
voltage as low as 2V, while drawing 170 µA/amplifier
(typical) of quiescent current.
The MCP6V71/1U family has enhanced EMI protection
to minimize any electromagnetic interference from
external sources. This feature makes it well suited for
EMI sensitive applications such as power lines, radio
stations, and mobile communications, etc.
The Microchip Technology Inc. MCP6V71/1U op amps
are offered in single (MCP6V71 and MCP6V71U) pack-
ages. They were designed using an advanced CMOS
process.
Package Types
Typical Application Circui t
VIN+
VSS
VIN–
1
2
3
5
4
VDD
VOUT
MCP6V71
SOT-23 MCP6V71U
SC70, SOT-23
VIN–
VSS
VOUT
1
2
3
5
4
VDD
VIN+
U1
MCP6XXX
Offset Voltage Correction for Power Driver
C2
R2
R1R3
VDD/2
R4
VIN VOUT
R2
VDD/2
R5
U2
MCP6V71
170 µA, 2 MHz Zero-Drift Op Amps
MCP6V71/1U
DS20005385A-page 2 2015 Microchip Technology Inc.
Figure 1 and Figure 2 show input offset voltage versus
ambient temperature for different power supply volt-
ages.
FIGURE 1: Input Offset Voltage vs.
Temperature with VDD = 2V.
FIGURE 2: Input Offset Voltage vs.
Temperature with VDD = 5.5V.
As seen in Figure 1 and Figure 2, the MCP6V71/1U op
amps have excellent performance across temperature.
The input offset voltage temperature drift (TC1) shown
is well within the specified maximum values of
15 nV/°C at VDD = 5.5V and 30 nV/°C at VDD = 2V.
This performance supports applications with stringent
DC precision requirements. In many cases, it will not be
necessary to correct for temperature effects (i.e.,
calibrate) in a design. In the other cases, the correction
will be small.
-8
-6
-4
-2
0
2
4
6
8
-50-250 255075100125
Input Offset Voltage (µV)
Ambient Temperature (°C)
28 Samples
VDD = 2V
-8
-6
-4
-2
0
2
4
6
8
-50-250 255075100125
Input Offset Voltage (µV)
Ambient Temperature (°C)
28 Samples
V
DD
= 2V
28 Samples
VDD = 5.5V
2015 Microchip Technology Inc. DS20005385A-page 3
MCP6V71/1U
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD –V
SS .................................................................................................................................................................6.5V
Current at Input Pins ..............................................................................................................................................±2 mA
Analog Inputs (VIN+ and VIN–) (Note 1) .....................................................................................VSS – 1.0V to VDD+1.0V
All Other Inputs and Outputs ......................................................................................................VSS – 0.3V to VDD+0.3V
Difference Input Voltage .................................................................................................................................|VDD –V
SS|
Output Short Circuit Current ........................................................................................................................... Continuous
Current at Output and Supply Pins ......................................................................................................................±30 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD Protection on All Pins (HBM, CDM, MM)  2kV,1.5kV,400V
Note 1: See Section 4.2.1, Rail-to-Rail Inputs.
1.2 Specifications
†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteris tics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT =V
DD/2, VL=V
DD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Input Offset
Input Offset Voltage VOS -8 — +8 µV TA = +25°C
Input Offset Voltage Drift with
Temperature (Linear Temp. Co.)
TC1-30 — +30 nV/°C TA = -40 to +125°C,
VDD = 2V (Note 1)
-15 — +15 TA = -40 to +125°C,
VDD = 5.5V (Note 1)
Input Offset Voltage Quadratic
Te mp . C o.
TC2—-30—pV/°C
2TA = -40 to +125°C,
VDD = 2V
—-6— T
A = -40 to +125°C,
VDD = 5.5V (Note 1)
Input Offset Voltage Aging ∆VOS — ±0.75 — µV 408 hours Life Test
at +150°,
measured at +25°C
Power Supply Rejection Ratio PSRR 115 125 — dB
Input Bias Current and Impedance
Input Bias Current IB-50 ±1 +50 pA
Input Bias Current across Temperature IB—+20—pAT
A = +85°C
IB0+0.2+3nAT
A = +125°C
Note 1: For Design Guidance only; not tested.
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
MCP6V71/1U
DS20005385A-page 4 2015 Microchip Technology Inc.
Input Offset Current IOS -250 ±60 +250 pA
Input Offset Current across Temperature IOS —±50—pAT
A = +85°C
IOS -1±0.05+1nAT
A = +125°C
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||6 — Ω||pF
Common Mode
Common Mode
Input Voltage Range Low
VCML ——V
SS 0.2 V (Note 2)
Common Mode
Input Voltage Range High
VCMH VDD +0.3 — — V (Note 2)
Common Mode Rejection Ratio CMRR 111 122 — dB VDD = 2V,
VCM = -0.2V to 2.3V
(Note 2)
CMRR 117 130 — dB VDD = 5.5V,
VCM = -0.2V to 5.8V
(Note 2)
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 117 132 — dB VDD =2V,
VOUT = 0.3V to 1.8V
AOL 126 137 — dB VDD =5.5V,
VOUT = 0.3V to 5.3V
Output
Minimum Output Voltage Swing VOL VSS VSS +35 V
SS + 121 mV RL=2kΩ, G = +2,
0.5V input overdrive
VOL —V
SS +3.5 — mV R
L=20kΩ, G = +2,
0.5V input overdrive
Maximum Output Voltage Swing VOH VDD – 121 VDD –45 V
DD mV RL=2kΩ, G = +2,
0.5V input overdrive
VOH —V
DD –4.5 — mV R
L=20kΩ, G = +2,
0.5V input overdrive
Output Short Circuit Current ISC —±9—mAV
DD =2V
ISC —±26—mAV
DD =5.5V
Power Supply
Supply Voltage VDD 2—5.5V
Quiescent Current per amplifier IQ100 170 260 µA IO = 0
POR Trip Voltage VPOR 0.9 1.2 1.6 V
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteris tics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT =V
DD/2, VL=V
DD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: For Design Guidance only; not tested.
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
2015 Microchip Technology Inc. DS20005385A-page 5
MCP6V71/1U
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
Electrical Characteris tics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL=20kΩ to VL and CL= 30 pF (refer to Figure 1-4 and Figure 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions
Amplifier AC Response
Gain Bandwidth Product GBWP — 2 — MHz
Slew Rate SR — 1.0 — V/µs
Phase Margin PM — 60 — ° G = +1
Amplifier Noise Response
Input Noise Voltage Eni —0.15—µV
P-P f = 0.01 Hz to 1 Hz
Eni —0.45—µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —21—nV/√Hz f < 2 kHz
Input Noise Current Density ini —5—fA/√Hz
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC) IMD — 11 — µVPK VCM tone = 100 mVPK at 1 kHz, GN = 1
Amplifier Step Response
Start Up Time tSTR — 200 — µs G = +1, 0.1% VOUT settling (Note 2)
Offset Correction Settling Time tSTL —15— µsG = +1, V
IN step of 2V,
VOS within 100 µV of its final value
Output Overdrive Recovery Time tODR — 40 — µs G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 3)
EMI Protection
EMI Rejection Ratio EMIRR — 75 — dB VIN = 0.1 VPK, f = 400 MHz
—89— V
IN = 0.1 VPK, f = 900 MHz
—96— V
IN = 0.1 VPK, f = 1800 MHz
—98— V
IN = 0.1 VPK, f = 2400 MHz
Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-38 and Figure 2-39,
there is an IMD tone at DC, a residual tone at 1 kHz and other IMD tones and clock tones.
2: High gains behave differently; see Section 4.3.3, Offset at Power Up.
3: tODR includes some uncertainty due to clock edge timing.
TABLE 1-3: TEMPERATURE SPECIFICATIONS
Electrical Characteris tics: Unless otherwise indicated, all limits are specified for: VDD = +2V to +5.5V,
VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C (Note 1)
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC-70 JA —209 — °C/W
Thermal Resistance, 5L-SOT-23 JA —201 — °C/W
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
MCP6V71/1U
DS20005385A-page 6 2015 Microchip Technology Inc.
1.3 Timing Diagrams
FIGURE 1-1: Amplifier Start Up.
FIGURE 1-2: Offset Correction Settling
Time.
FIGURE 1-3: Output Overdrive Recovery.
1.4 Test Circuits
The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay out the bypass
capacitors as discussed in Section 4.3.10 “Supply
Bypassing and Filtering”. RN is equal to the parallel
combination of RF and RG to minimize bias current
effects.
FIGURE 1-4: AC and DC Test Circuit for
Most Noninverting Gain Conditions.
FIGURE 1-5: AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s Common
mode input voltage is VCM =V
IN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
FIGURE 1-6: Test Circuit for Dynamic
Input Behavior.
VDD
VOUT
1.001(VDD/3)
0.999(VDD/3)
tSTR
0V
2V to 5.5V
2V
VIN
VOS
VOS +100µV
VOS –100µV
tSTL
VIN
VOUT
VDD
VSS
tODR
tODR
VDD/2
VDD
RGRF
RN
VOUT
VIN
VDD/3
1µF
CLRL
VL
100 nF
RISO
MCP6V7X
VDD
RGRF
RN
VOUT
VDD/3
VIN
1µF
CLRL
VL
100 nF
RISO
MCP6V7X
VDD
VOUT
1µF
CL
VL
RISO
11.0 kΩ249Ω
11.0 kΩ500Ω
VIN
VREF =V
DD/3
0.1%
0.1% 25 turn
100 kΩ
100 kΩ
0.1%
0.1%
RL
0Ω
30 pF open
100 nF
1%
MCP6V7X
2015 Microchip Technology Inc. DS20005385A-page 7
MCP6V71/1U
2.0 TY PICAL PERFORM ANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS =GND, V
CM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
2.1 DC Input Precision
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input Offset Voltage
Quadratic Temp. Co.
FIGURE 2-4: Input Offset Voltage vs.
Power Supply Voltage with VCM =V
CML.
FIGURE 2-5: Input Offset Voltage vs.
Power Supply Voltage with VCM =V
CMH.
FIGURE 2-6: Input Offset Voltage vs.
Output Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
Percentage of Occurences
Input Offset Voltage (µV)
28 Samples
TA= 25ºC
VDD = 2V
VDD = 5.5V
0%
10%
20%
30%
40%
50%
60%
-12-10-8-6-4-2024681012
Percentage of Occurances
Input Offset Voltage Drift; TC
1
(nV/°C)
28 Samples
TA= -40°C to +125°C
VDD = 2V
VDD = 5.5V
0%
10%
20%
30%
40%
50%
60%
70%
80%
-200 -160 -120 -80 -40 0 40 80 120
Percentage of Occurrences
Input Offset Voltage's Quadratric Temp Co;
TC
2
(pV/°C
2
)
28 Samples
TA= -40°C to +125°C
VDD = 2V
VDD = 5.5V
-8
-6
-4
-2
0
2
4
6
8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Input Offset Voltage (µV)
Power Supply Voltage (V)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
Representative Part
V
CM
= V
CML
Input Offset Voltage (µV)
Power Supply Voltage (V)
-8
-6
-4
-2
0
2
4
6
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Offset Voltage (µV)
Output Voltage (V)
Representative Part
VDD = 2V
VDD = 5.5V
MCP6V71/1U
DS20005385A-page 8 2015 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
FIGURE 2-7: Input Offset Voltage vs.
Common Mode Voltage with VDD =2V.
FIGURE 2-8: Input Offset Voltage vs.
Common Mode Voltage with VDD =5.5V.
FIGURE 2-9: CMRR.
FIGURE 2-10: PSRR.
FIGURE 2-11: DC Open-Loop Gain.
FIGURE 2-12: CMRR and PSRR vs.
Ambient Temper atu re.
-8
-6
-4
-2
0
2
4
6
8
-0.5 -0.2 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5
Input Offset Voltage (µV)
Common Mode Input Voltage (V)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
V
DD
= 2V
Representative Part
-8
-6
-4
-2
0
2
4
6
8
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Offset Voltage (µV)
Common Mode Input Voltage (V)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= -40°C
V
DD
= 5.5V
Representative Part
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
-1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6
Percentage of Occurrences
1/CMRR (µV/V)
617 Samples
T
A
= +25ºC
V
DD
= 2V
V
DD
= 5.5V
0%
10%
20%
30%
40%
50%
60%
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
Percentage of Occurrences
1/PSRR (µV/V)
617 Samples
T
A
= +25ºC
0%
10%
20%
30%
40%
50%
60%
70%
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
Percentage of Occurrences
1/AOL (µV/V)
617 Samples
T
A
= +25ºC V
DD
= 5.5V
V
DD
= 2V
110
120
130
140
150
-50-25 0 255075100125
CMRR, PSRR (dB)
Ambient Temperature (°C)
PSRR
CMRR @ V
DD
= 5.5V
@ V
DD
= 2V
2015 Microchip Technology Inc. DS20005385A-page 9
MCP6V71/1U
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS =GND, V
CM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
FIGURE 2-13: DC Open-Loop Gain vs.
Ambient Temperature.
FIGURE 2-14: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA= +85°C.
FIGURE 2-15: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA= +125°C.
FIGURE 2-16: Input Bias and Offset
Currents vs. Ambient Temperature with
VDD =+5.5V.
FIGURE 2-17: Input Bias Current vs. Input
Voltage (below VSS).
110
120
130
140
150
160
170
-50-250 255075100125
DC Open-Loop Gain (dB)
Ambient Temperature (°C)
VDD= 5.5V
V
DD
= 2V
-1,000
-800
-600
-400
-200
0
200
400
600
800
1,000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Bias and Offset Currents
(pA)
Input Common Mode Voltage (V)
Input Bias Current
Input Offset Current
VDD = 5.5 V
TA= 85 ºC
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Bias and Offset Currents
(pA)
Input Common Mode Voltage (V)
In
p
ut Bias Current
Input Offset Current
VDD = 5.5 V
TA= 125 ºC
0.1
1
10
100
1000
25
35
45
55
65
75
85
95
105
115
125
Input Bias, Offset Currents (A)
Ambient Temperature (°C)
Input Bias Current
Input Offset Current
VDD = 5.5 V
1n
100
p
10
p
1
p
0.1
p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Current Magnitude (A)
Input Voltage (V)
TA= +125°C
TA= +85°C
TA= +25°C
T
A
= -40°C
1m
10µ
100n
10n
1n
100µ
1µ
100p
MCP6V71/1U
DS20005385A-page 10 2015 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
2.2 Other DC Volt ages and Currents
FIGURE 2-18: Input Common Mode
Voltage Headroom (Range) vs. Ambient
Temperature.
FIGURE 2-19: Output Voltage Headroom
vs. Output Current.
FIGURE 2-20: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-21: Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-22: Supply Current vs. Power
Supply Voltage.
FIGURE 2-23: Power-On Reset Trip
Voltage.
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-50-25 0 255075100125
Input Common Mode Voltage
Headroom (V)
Ambient Temperature (°C)
1 Wafer Lot
Upper (VCMH –V
DD)
Lower (VCML –V
SS)
1
10
100
1000
0.1 1 10
Output Voltage Headroom
(mV)
Output Current Magnitude (mA)
VDD = 5.5V
VDD = 2V
VDD -VOH
VOL -VSS
0
10
20
30
40
50
60
70
80
90
-50-25 0 255075100125
Output Voltage Headroom (mV)
Ambient Temperature (°C)
VDD -V
OH
V
DD
= 5.5V
VDD -V
OH
VOL -V
SS
VDD = 2V
RL= 20 kȍ
-40
-30
-20
-10
0
10
20
30
40
00.511.522.533.544.555.566.5
Output Short Circuit Current
(mA)
Power Supply Voltage (V)
TA= +125°C
TA= +85°C
TA= +25°C
T
A
=-40°C
TA= +125°C
TA= +85°C
TA= +25°C
TA= -40°C
0
20
40
60
80
100
120
140
160
180
200
00.511.522.533.544.555.566.5
Quiescent Current
(µA/Amplifier)
Power Supply Voltage (V)
TA= +125°C
TA= +85°C
TA= +25°C
TA= -40°C
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0.9
1.04
1.08
1.12
1.16
1.2
1.24
1.28
1.32
1.6
Percentage of Occurences
POR Trip Voltage (V)
800 Samples
1 Wafer Lot
TA= +25ºC
2015 Microchip Technology Inc. DS20005385A-page 11
MCP6V71/1U
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS =GND, V
CM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
FIGURE 2-24: Power-On Reset V oltage vs.
Ambient Temperature.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
-50-25 0 255075100125
POR Trip Voltage (V)
Ambient Temperature (°C)
800 Samples
1 Wafer Lot
MCP6V71/1U
DS20005385A-page 12 2015 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
2.3 Frequency Response
FIGURE 2-25: CMRR and PSRR vs.
Frequency.
FIGURE 2-26: Open-Loop Gain vs.
Frequency with VDD =2V.
FIGURE 2-27: Open-Loop Gain vs.
Frequency with VDD =5.5V.
FIGURE 2-28: Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
FIGURE 2-29: Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
FIGURE 2-30: Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
30
40
50
60
70
80
90
100
110
120
130
140
150
10 100 1000 10000 100000
CMRR, PSRR (dB)
Frequency (Hz)
10 100 1k 10k 100k
CMRR
PSRR+
PSRR-
Representative Part
-270
-240
-210
-180
-150
-120
-90
-60
-20
-10
0
10
20
30
40
50
1.E+04 1.E+05 1.E+06 1.E+07
f (Hz)
Open-Loop Phase (°)
Open-Loop Gain (dB)
Open-Loop Gain
Open-Loop Phase
VDD = 2V
CL= 30 pF
10k 100k 1M 10M
-270
-240
-210
-180
-150
-120
-90
-60
-20
-10
0
10
20
30
40
50
1.E+04 1.E+05 1.E+06 1.E+07
f (Hz)
Open-Loop Phase (°)
Open-Loop Gain (dB)
Open-Loop Gain
Open-Loop Phase
VDD = 5.5V
CL= 30 pF
10k 100k 1M 10M
0
10
20
30
40
50
60
70
80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50-250 255075100125
Gain Bandwidth Product
(MHz)
Ambient Temperature (°C)
GBWP
PM
VDD = 2V
Phase Margin (°)
VDD = 5.5V
30
40
50
60
70
80
90
0
0.5
1
1.5
2
2.5
3
-101234567
Phase Margin (º)
Gain Bandwidth Product (MHz)
Common Mode Input Voltage (V)
VDD = 5.5V
VDD = 2V
PM
GBWP
25
30
35
40
45
50
55
60
65
0
0.5
1
1.5
2
2.5
3
3.5
4
0123456
Phase Margin (º)
Gain Bandwidth Product (MHz)
Output Voltage (V)
VDD = 5.5V
PM
GBWP
VDD = 2V
2015 Microchip Technology Inc. DS20005385A-page 13
MCP6V71/1U
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS =GND, V
CM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
FIGURE 2-31: Closed-Loop Output
Impedance vs. Frequency with VDD =2V.
FIGURE 2-32: Closed-Loop Output
Impedance vs. Frequency with VDD =5.5V.
FIGURE 2-33: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-34: EMIRR vs Frequency.
FIGURE 2-35: EMIRR vs RF Input Peak
Voltage.
10
100
1000
10000
100000
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
Closed Loop Output
Impedance (:))
Frequency (Hz)
GN:
101 V/V
11 V/V
1 V/V
1k 10k 100k 1M 10M
VDD = 2V
100k
10k
1k
100
10
10
100
1000
10000
100000
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
Closed Loop Output
Impedance (Ω)
Frequency (Hz)
G
N
:
101 V/V
11 V/V
1 V/V
1k 10k 100k 1M 10M
V
DD
= 5.5V
100k
10k
1k
100
10
0.1
1
10
1000 10000 100000 1000000 10000000
Output Voltage Swing (V
P-P
)
Frequency (Hz)
VDD = 2V
VDD = 5.5V
1k 10k 100k 1M 10M
0
10
20
30
40
50
60
70
80
90
100
110
120
10 100 1000 10000
EMIRR (dB)
Frequency (Hz)
10M 100M 1G 10G
V
PK
= 100 mV
V
DD
= 5.5V
0
20
40
60
80
100
120
0.01 0.10 1.00 10.00
EMIRR (dB)
RF Input Peak Voltage (Vp)
EMIRR @ 2400 MHz
EMIRR @ 1800 MHz
EMIRR @ 900 MHz
EMIRR @ 400 MHz
VDD = 5.5V
MCP6V71/1U
DS20005385A-page 14 2015 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
2.4 Input Noise and Distortion
FIGURE 2-36: Input Noise Voltage Density
and Integrated Input Noise Voltage vs.
Frequency.
FIGURE 2-37: Input Noise Voltage Density
vs. Input Common Mode Voltage.
FIGURE 2-38: Intermodulation Distortion
vs. Frequency with VCM Dis tur ba nce (se e
Figure 1-6).
FIGURE 2-39: Intermodulation Distortion
vs. Frequency with VDD Disturbance
(see Figure 1-6).
FIGURE 2-40: Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD =2V.
FIGURE 2-41: Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD =5.5V.
1
10
100
1000
1
10
100
1000
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
Frequency (Hz)
Integrated Input Noise Voltage;
E
ni
(µV
P-P
)
Input Noise Voltage Density;
e
ni
(nV/¥+]
eni
Eni(0 Hz to f)
VDD = 5.5V, green
VDD = 2V, blue
1 10 100 1k 10k 100k
0
5
10
15
20
25
30
35
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Input Noise Voltage Density
Q9¥+]
Common Mode Input Voltage (V)
V
DD
= 2.0V
V
DD
= 5.5V
f < 2 kHz
1.E-2
1.E-1
1.E+0
1.E+1
1.E+2
1.E+3
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
IMD Spectrum, RTI (V
PK
)
Frequency (Hz)
1
10 100 1k 10k 100k
1m
100µ
10µ
1µ
100n
10n
G = 11 V/V
VCM tone = 100 mVPK, f = 1 kHz
DC tone
Residual
1 kHz tone
(due to resistor
mismatch)
ǻf = 64 Hz
ǻf = 2 Hz
VDD = 2.0V
VDD = 5.5V
1.E-2
1.E-1
1.E+0
1.E+1
1.E+2
1.E+3
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
IMD Spectrum, RTI (V
PK
)
Frequency (Hz)
1
10 100 1k 10k 100k
1m
100µ
10µ
1µ
100n
10n
G = 11 V/V
VCM tone = 100 mVPK, f = 1 kHz
DC tone
Residual
1 kHz tone
(due to resistor
mismatch)
ǻf = 64 Hz
ǻf = 2 Hz
VDD = 2.0V
VDD = 5.5V
0 102030405060708090100
Input Noise Voltage; e
ni
(t)
(0.1 µV/div)
Time (s)
VDD = 2V
NPBW = 10 Hz
NPBW = 1 Hz
0 102030405060708090100
Input Noise Voltage; e
ni
(t)
(0.1 µV/div)
Time (s)
V
DD
= 5.5V
NPBW = 10 Hz
NPBW = 1 Hz
2015 Microchip Technology Inc. DS20005385A-page 15
MCP6V71/1U
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS =GND, V
CM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
2.5 Time Response
FIGURE 2-42: Input Offset Voltage vs.
Time with Temperature Change.
FIGURE 2-43: Input Offset Voltage vs.
Time at Power-Up.
FIGURE 2-44: The M C P 6V7 1/1U Family
Shows No Input Phase Reversal with Overdrive.
FIGURE 2-45: Non in v erti ng Sma ll Sign al
Step Response.
FIGURE 2-46: Non in v erti ng Lar ge Signa l
Step Response.
FIGURE 2-47: Inverting Small Signal Step
Response.
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
-10
-5
0
5
10
15
20
25
30
35
40
45
0 102030405060708090100110120
PCB Temperature (ºC)
Input Offset Voltage (µV)
Time (s)
V
DD
= 5.5V
V
DD
= 2V
T
PCB
V
OS
Temperature increased by
using heat gun for 5 seconds.
-1
0
1
2
3
4
5
6
-5
0
5
10
15
20
25
30
012345678910
Power Supply Voltage (V)
Input Offset Voltage (mV)
Time (ms)
V
DD
= 5.5V
G = +1 V/V
POR Trip Point
V
DD
V
OS
-1
0
1
2
3
4
5
6
Input, Output Voltages (V)
Time (5 µs/div)
V
DD
= 5.5 V
G = +1 V/V
VOUT
VIN
00.511.522.533.544.55
Output Voltage (20 mV/div)
Time (µs)
VDD = 5.5V
G = +1 V/V
0
1
2
3
4
5
6
0 2.5 5 7.5 10 12.5 15 17.5 20
Output Voltage (V)
Time (µs)
VDD = 5.5 V
G = +1 V/V
00.511.522.533.544.55
Output Voltage (20 mV/div)
Time (µs)
VDD = 5.5 V
G = -1 V/V
MCP6V71/1U
DS20005385A-page 16 2015 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=20kΩ to VL and CL = 30 pF.
FIGURE 2-48: Inverting Large Signal Step
Response.
FIGURE 2-49: Slew Rate vs. Ambient
Temperature.
FIGURE 2-50: Output Overdrive Recovery
vs. Time with G = -10 V/V.
FIGURE 2-51: Output Overdrive Recovery
Time vs. Inverting Gain.
0
1
2
3
4
5
6
Output Voltage (V)
Time (2 µs/div)
VDD = 5.5 V
G = -1 V/V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50-250 255075100125
Slew Rate (V/µs)
Ambient Temperature (°C)
Falling Edge, V
DD
= 5.5V
Rising Edge, V
DD
= 5.5V
Falling Edge, V
DD
= 2V
Rising Edge, V
DD
= 2V
-1
0
1
2
3
4
5
6
7
Input and Output Voltage (V)
Time (50 µs/div)
VDD = 5.5 V
G = -10 V/V
0.5V Overdrive
VOUT GVIN
VOUT
GVIN
1 10 100 1000
Overdrive Recovery Time (s)
Inverting Gain Magnitude (V/V)
100µ
10
µ
1
µ
0.5V In
p
ut Overdrive
1m
VDD = 2.0V
VDD = 5.5V
tODR, high
tODR, low
2015 Microchip Technology Inc. DS20005385A-page 17
MCP6V71/1U
3.0 PIN DESCRIPT IONS
Descriptions of the pins are listed in Table 3-1.
3.1 Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2 Analog Inputs
The noninverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 2V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
TABLE 3-1: PIN FUNCTION TABLE
MCP6V71 MCP6V71U
Symbol Description
SOT-23 SOT-23,
SC-70
14V
OUT Output
22 V
SS Negative Power Supply
31V
IN+ Noninverting Input
43V
IN– Inverting Input
55 V
DD Positive Power Supply
MCP6V71/1U
DS20005385A-page 18 2015 Microchip Technology Inc.
4.0 APPLICATIONS
The MCP6V71/1U family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for precision applications with
requirements for small packages and low power. Its low
supply voltage and low quiescent current make the
MCP6V71/1U devices ideal for battery-powered
applications.
4.1 Overview of Zero-D rif t Operation
Figure 4-1 shows a simplified diagram of the
MCP6V71/1U zero-drift op amp. This diagram will be
used to explain how slow voltage errors are reduced in
this architecture (much better VOS, ∆VOS/∆TA (TC1),
CMRR, PSRR, AOL and 1/f noise).
FIGURE 4-1: Simplified Zero-Drift Op
Amp Functional Diagram.
4.1.1 BUILDING BLOCKS
The Main amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the low-
frequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.
The Auxiliary amplifier, chopper input switches and
chopper output switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequencies.
The low-pass filter reduces high-frequency content,
including harmonics of the chopping clock.
The output buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The oscillator runs at fOSC1 = 200 kHz. Its output is
divided by two, to produce the chopping clock rate of
fCHOP = 100 kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.
The digital control block controls switching and POR
events.
4.1.2 CHOPPING ACTION
Figure 4-2 shows the amplifier connections for the first
phase of the chopping clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.
FIGURE 4-2: First Chopping Clock Phase;
Equivalent Amplifier Diagram.
FIGURE 4-3: Second Chopping Clock
Phase; Equivalent Amplifier Diagram.
VIN+
VIN–Main
Buffer
VOUT
VREF
Amp.
Output
NC
Aux.
Amp.
Chopper
Input
Switches
Chopper
Output
Switches
Oscillator
Low-Pass
Filter
POR
Digital Control
VIN+
VIN–Main
Amp. NC
Aux.
Amp.
Low-Pass
Filter
VIN+
VIN–Main
Amp. NC
Aux.
Amp.
Low-Pass
Filter
2015 Microchip Technology Inc. DS20005385A-page 19
MCP6V71/1U
4.1.3 INTERMODULATION DISTORTION
(IMD)
These op amps will show intermodulation distortion
(IMD) products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference frequen-
cies. Each of the square wave clock’s harmonics has a
series of IMD tones centered on it. See Figure 2-38 and
Figure 2-39.
4.2 Other Functi onal Blocks
4.2.1 RAIL-TO-RAIL INPUTS
The input stage of the MCP6V71/1U op amps uses two
differential CMOS input stages in parallel. One
operates at low Common mode input voltage (VCM,
which is approximately equal to VIN+ and VIN– in
normal operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD +0.3V,
and down to VSS – 0.2V, at +25°C (see Figure 2-18).
The input offset voltage (VOS) is measured at
VCM =V
SS – 0.2V and VDD + 0.3V to ensure proper
operation.
4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-44 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2 Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
FIGURE 4-4: Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages well above VDD; their breakdown
voltage is high enough to allow normal operation, but
not low enough to protect against slow overvoltage
(beyond VDD) events. Very fast ESD events (that meet
the spec) are limited so that damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode
connected FETs for low leakage.
FIGURE 4-5: Protecting the Analog Inputs
Against High Voltages.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad VIN–
V1
VDD
D1
VOUT
V2
D2
U1
MCP6V7X
MCP6V71/1U
DS20005385A-page 20 2015 Microchip Technology Inc.
4.2.1.3 Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute Maxi-
mum Ratings †”). This requirement is independent of
the voltage limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
FIGURE 4-6: Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (VCM) is below ground (VSS); see
Figure 2-17.
4.2.2 RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V71/1U zero-drift
op amps is VDD – 5.9 mV (typical) and VSS +4.5mV
(typical) when RL=20kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-19 and Figure 2-20 for
more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.3 Application Tips
4.3.1 INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2 DC GAIN PLOTS
Figures 2-9 to 2-11 are histograms of the reciprocals
(in units of µV/V) of CMRR, PSRR and AOL,
respectively. They represent the change in input offset
voltage (VOS) with a change in Common mode input
voltage (VCM), power supply voltage (VDD) and output
voltage (VOUT).
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise and tester limitations, not unstable behavior.
Production tests make multiple VOS measurements,
which validate an op amp's stability; an unstable part
would show greater VOS variability, or the output would
stick at one of the supply rails.
4.3.3 OFFSET AT POWER UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the start-up time (like
tSTR).
It can be simple to avoid this extra start-up time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
V1
R1
VDD
D1
min(R1,R
2)>VSS –min(V
1,V
2)
2mA
VOUT
V2
R2
D2
min(R1,R
2)>max(V1,V
2)–V
DD
2mA
U1
MCP6V7X
VOS TA
 VOS TC1
TTC
2
T2
++=
Where:
∆T=T
A–25°C
VOS(TA) = input offset voltage at TA
VOS = input offset voltage at +25°C
TC1= linear temperature coefficient
TC2= quadratic temperature coefficient
2015 Microchip Technology Inc. DS20005385A-page 21
MCP6V71/1U
4.3.4 SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10 Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
4.3.5 SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small. Large input capacitances and source resis-
tances, together with high gain, can lead to positive
feedback and instability.
4.3.6 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-7: Output Resistor, RISO,
Stabilizes Capacitiv e Load s.
Figure 4-8 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/√GN). The y-axis is
the resistance (RISO).
GN is the circuit’s noise gain. For noninverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN= +2 V/V).
FIGURE 4-8: Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation is helpful.
4.3.7 STABILIZING OUTPUT LOADS
This family of zero-drift op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low-
impedance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-9 shows that the load on the output is
(RL+R
ISO)||(RF+R
G), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least 10 kΩ.
FIGURE 4-9: Output Load.
RISO
CL
VOUT
U1
MCP6V7X
1
10
100
1000
10000
1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Recommended R ISO (
Ω
)
Normalized Load Capacitance; CL/¥GN(F)
GN:
1 V/V
10 V/V
100 V/V
VDD = 5.5 V
R
L
= 20 kȍ
100p 1n 10n 100n 1µ
RGRF
VOUT
U1
MCP6V7X
RLCL
RISO
MCP6V71/1U
DS20005385A-page 22 2015 Microchip Technology Inc.
4.3.8 GAIN PEAKING
Figure 4-10 shows an op amp circuit that represents
noninverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel. The capacitance CFP represents the
parasitic capacitance coupling the output and nonin-
verting input pins.
FIGURE 4-10: Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG
.
CN and RN form a low-pass filter that affects the signal
at VP
. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.6 “Capacitive
Loads”), CG and the open-loop gain’s phase shift. An
approximate limit for RF is:
EQUATION 4-2:
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RN needs to be small, in order to prevent
positive feedback and oscillations. Large CN values
can also help.
4.3.9 REDUCING UNDESIRED NOISE
AND SIGNALS
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimize random analog noise
- Reduce interfering signals
• Good PCB layout techniques:
- Minimize crosstalk
- Minimize parasitic capacitances and
inductances that interact with fast switching
edges
• Good power supply design:
- Isolation from other parts
- Filtering of interference on supply line(s)
4.3.10 SUPPLY BYPASSING AND
FILTERING
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.
4.3.11 PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring, and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V71/1U op
amps’ minimum and maximum specifications.
4.3.11.1 PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
•PCB vias
RGRF
VOUT
U1
MCP6V7X
CG
RN
CN
VM
VP
CFP
RF10 k

12 pF
CG
--------------
GN
2
2015 Microchip Technology Inc. DS20005385A-page 23
MCP6V71/1U
Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in-depth information on
PCB layout techniques that minimize thermojunction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.
4.3.11.2 Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC
performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
To reduce interference:
- Keep traces and wires as short as possible
- Use shielding
- Use ground plane (at least a star ground)
- Place the input signal source near to the DUT
- Use good PCB layout techniques
- Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps
4.3.11.3 Miscellaneous Effects
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias-
current-related offsets.
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
Mechanical stresses can make some capacitor types
(such as some ceramics) output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
4.4 Typical Applications
4.4.1 WHEATSTONE BRIDGE
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
Common mode noise large. Amplifier designs with high
differential gain are desirable.
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single ended,
and there is a minimum of filtering; the CMRR is good
enough for moderate Common mode noise.
FIGURE 4-11: Simple Design.
4.4.2 RTD SENSOR
The ratiometric circuit in Figure 4-12 conditions a two-
wire RTD, for applications with a limited temperature
range. U1 acts as a difference amplifier, with a low-
frequency pole. The sensor’s wiring resistance (RW) is
corrected in firmware. Failure (open) of the RTD is
detected by an out-of-range voltage.
FIGURE 4-12: RTD Sensor.
VDD
RR
RR
100R
0.01C
ADC
VDD
0.2R
0.2R
1kΩ
U1
MCP6V71
RF
10 nF
ADC
VDD
RN
1.0 µF
VDD
RW
RT
RB
RRTD
RG
100Ω
1.00 kΩ
4.99 kΩ
34.8 kΩ
2.00 MΩ10.0 kΩ
U1
MCP6V71
RW
10.0 kΩ
RF
2.00 MΩ
10 nF
100 nF
MCP6V71/1U
DS20005385A-page 24 2015 Microchip Technology Inc.
4.4.3 OFFSET VOLTAGE CORRECTION
Figure 4-13 shows MCP6V71 (U2) correcting the input
offset voltage of another op amp (U1). R2 and C2
integrate the offset error seen at U1’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3). R4 and R5
attenuate the integrator’s output; this shifts the
integrator pole down in frequency.
FIGURE 4-13: Offset Correction.
4.4.4 PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V71/1U as a
comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
FIGURE 4-14: Precision Comparator.
U1
MCP6XXX
C2
R2
R1R3
VDD/2
R4
VIN VOUT
R2
VDD/2
R5
U2
MCP6V71
VIN
R3
R2
VDD/2
VOUT
R5
R4
R1
U1
MCP6V71
U2
MCP6541
2015 Microchip Technology Inc. DS20005385A-page 25
MCP6V71/1U
5.0 DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6V71/1U family of op amps.
5.1 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.2 Microchi p Advanced Part Sel ector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip web site
at www.microchip.com/maps, MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data Sheets, Purchase and Sampling of
Microchip parts.
5.3 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at
www.microchip.com/analog tools.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 1 (P/N
DS51667)
• MCP6XXX Amplifier Evaluation Board 2 (P/N
DS51668)
• MCP6XXX Amplifier Evaluation Board 3 (P/N
DS51673)
• MCP6XXX Amplifier Evaluation Board 4 (P/N
DS51681)
• Active Filter Demo Board Kit User’s Guide (P/N
DS51614)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N
SOIC14EV)
5.4 Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filteri ng Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
These Application Notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MCP6V71/1U
DS20005385A-page 26 2015 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead SC70 (MCP6V71U)Example:
Device Code
MCP6V71UT-E/LTY DUNN
5-Lead SOT-23 (MCP6V71, MCP6V71U) Example:
Device Code
MCP6V71T-E/OT AAAYY
MCP6V71UT-E/OT AAAZY
DU56
XXXXY
WWNNN AAAY4
40256
2015 Microchip Technology Inc. DS20005385A-page 27
MCP6V71/1U
5-Lead Plastic Small Outine Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-083B
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DS20005385A-page 28 2015 Microchip Technology Inc.
5-Lead Plastic Small Outine Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015 Microchip Technology Inc. DS20005385A-page 29
MCP6V71/1U
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DS20005385A-page 30 2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015 Microchip Technology Inc. DS20005385A-page 31
MCP6V71/1U
APPENDIX A: REVISION HISTORY
Revision A (March 2015)
• Original Release of this Document.
MCP6V71/1U
DS20005385A-page 32 2015 Microchip Technology Inc.
NOTES:
2015 Microchip Technology Inc. DS20005385A-page 33
MCP6V71/1U
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6V71T: Single Op Amp (Tape and Reel)
(SOT-23 only)
MCP6V71UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
Temperature Range: E = -40°C to +125°C (Extended)
Package: LTY* = Plastic Small Outline Transistor, SC-70, 5-lead
OT = Plastic Small Outline Transistor, SOT-23, 5-lead
*Y = Nickel palladium gold manufacturing designator.
Only available on the SC70 package.
PART NO. –X /XX
PackageTemperature
Range
Device
[X](1)
Tape and Reel
Examples:
a) MCP6V71T-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23 package
b) MCP6V71UT-E/OT Tape and Reel,
Extended temperature,
5LD SOT-23 package
c) MCP6V71UT-E/LTY Tape and Reel,
Extended temperature,
5LD SC-70 package
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
MCP6V71/1U
DS20005385A-page 34 2015 Microchip Technology Inc.
NOTES:
2015 Microchip Technology Inc. DS20005385A-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-164-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005385A-page 36 2015 Microchip Technology Inc.
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Worldwide Sales and Service
01/27/15