DS1884 SFP and PON ONU Controller with Digital LDD Interface General Description The DS1884 controls and monitors all functions for SFF, SFP, and SFP+ modules including all SFF-8472 functionality. The combination of the DS1884 with the MAX3710 supports all transmitter and receiver functionality. The DS1884 includes modulation current control and APC set-point control with tracking error adjustment. It continually monitors RSSI for LOS generation. A 13-bit analog-todigital converter (ADC) monitors VCC, temperature, laser bias, laser modulation, and receive power to meet all monitoring requirements. Receive power measurement is differential with support for common mode to VCC. A 9-bit digital-to-analog converter (DAC) is included with temperature compensation for APD bias control. Applications SFF, SFP, and PON ONU Modules Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/DS1884.related. Features S Meets All SFF-8472 Control and Monitoring Requirements S Companion Controller for the MAX3710 Laser Driver/Limiting Amplifier and MAX3945 Limiting Amplifier S MAX3710/DS1884 Combination Supports Broad Spectrum of Continuous Mode and PON Applications Up to 2.5GHz S Temperature Lookup Table (LUT) to Compensate for APC Tracking Error and Dual Closed-Loop Variables S Three Laser Control Modes Dual Closed Loop: Laser Bias and Laser Modulation Are Automatically Controlled with Multiple LUTs to Compensate Dual Closed-Loop Calibration Points APC Loop: Laser Bias Automatically Controlled, Laser Modulation Controlled by Temperature LUT Open Loop: Laser Bias and Laser Modulation Are Controlled by Temperature LUTs S 13-Bit ADC Laser Bias, Laser Power, and Receive Power Support Internal and External Calibration Differential Receive Power Input Scalable Dynamic Range Internal Direct-to-Digital Temperature Sensor Alarm and Warning Flags for All Monitored Channels S 9-Bit DAC with Temperature Compensation for APD Bias S Digital I/O Pins: Transmit Disable Input/Output, Rate Select Input/Output, LOS Input/Output, Transmit Fault Input/Output, and IN1 Status Monitor and Fault input S Comprehensive Fault Measurement System with Maskable Alarm/Warnings S Flexible Password Scheme Provides Three Levels of Security S 256-Byte A0h and 128-Byte Upper A2h EEPROM S I2C-Compatible Interface S 3-Wire Master to Communicate with the MAX3710 Laser Driver/Limiting Amplifier and MAX3945 Limiting Amplifier For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. 19-5928; Rev 1; 7/11 DS1884 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Startup Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3-Wire Digital Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical Operating Circuit--GPON ONU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical Operating Circuit--10G PON ONU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Alarms and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Differential RSSI Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Laser Bias and Laser Power Through TXMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Enhanced RSSI Monitoring (Dual Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 APD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PIN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Delta-Sigma Output and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Maxim Integrated 2 DS1884 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TXD, TXDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 IN1, TXF, Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DS1884 Master Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-Wire Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-Wire Slave Register Map and DS1884 Corresponding Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3-Wire Master Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DS1884 with MAX3710 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Open Loop Mode, DPC_EN = 0, APC_EN = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 APC Loop Mode, DPC_EN = 0, APC_EN = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Dual Closed-Loop Mode, DPC_EN = 1, APC_EN = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 BIAS, MODULATION, SET_2XAPC, TXCTRL5 LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MODULATION Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 BIAS Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Manual MAX3710 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I2C Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 A2h Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 A2h Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 A2h Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 A2h Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 A2h Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 A2h Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 A2h Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 A2h Table 09h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 A2h Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Lower Memory, Register 00h-01h: TEMP ALARM HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Lower Memory, Register 04h-05h: TEMP WARN HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Maxim Integrated 3 DS1884 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Lower Memory, Register 02h-03h: TEMP ALARM LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Lower Memory, Register 06h-07h: TEMP WARN LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 A2h Lower Memory, Register 08h-09h: VCC ALARM HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 0Ch-0Dh: VCC WARN HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 10h-11h: TXB ALARM HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 14h-15h: TXB WARN HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 18h-19h: TXP ALARM HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 1Ch-1Dh: TXP WARN HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 20h-21h: RSSI ALARM HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 24h-25h: RSSI WARN HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 0Ah-0Bh: VCC ALARM LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 0Eh-0Fh: VCC WARN LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 12h-13h: TXB ALARM LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 16h-17h: TXB WARN LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 1Ah-1Bh: TXP ALARM LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 1Eh-1Fh: TXP WARN LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 22h-23h: RSSI ALARM LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 26h-27h: RSSI WARN LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A2h Lower Memory, Register 28h-37h: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A2h Lower Memory, Register 38h-5Fh: EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A2h Lower Memory, Register 60h-61h: TEMP VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A2h Lower Memory, Register 62h-63h: VCC VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 A2h Lower Memory, Register 64h-65h: TXB VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 A2h Lower Memory, Register 66h-67h: TXP VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 A2h Lower Memory, Register 68h-69h: RSSI VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 A2h Lower Memory, Register 6Ah-6Dh: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 A2h Lower Memory, Register 6Eh: STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 A2h Lower Memory, Register 6Fh: UPDATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 A2h Lower Memory, Register 70h: ALARM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 A2h Lower Memory, Register 71h: ALARM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 A2h Lower Memory, Register 72h-73h: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 A2h Lower Memory, Register 74h: WARN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 A2h Lower Memory, Register 75h: WARN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 A2h Lower Memory, Register 76h-7Ah: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 A2h Lower Memory, Register 7Bh-7Eh: PASSWORD ENTRY (PWE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Maxim Integrated 4 DS1884 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Lower Memory, Register 7Fh: TBL SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 A2h Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 A2h Table 01h, Register 80h-BFh: EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 A2h Table 01h, Register C0h-F7h: EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 A2h Table 01h, Register F8h: ALARM EN3 OR EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 A2h Table 01h, Register F9h: ALARM EN2 OR EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 A2h Table 01h, Register FAh-FBh: RESERVED OR EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 A2h Table 01h, Register FCh: WARN EN3 OR EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 A2h Table 01h, Register FDh: WARN EN2 OR EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 A2h Table 01h, Register FEh-FFh: RESERVED OR EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 A2h Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A2h Table 02h, Register 80h: MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A2h Table 02h, Register 81h: Temperature Index (TINDEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 A2h Table 02h, Register 82h-83h: MODULATION VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 A2h Table 02h, Register 84h: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 A2h Table 02h, Register 85h: APC VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 A2h Table 02h, Register 86h-87h: SET_IBIAS VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 A2h Table 02h, Register 88h: DACFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 A2h Table 02h, Register 89h: CNFGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 A2h Table 02h, Register 8Ah: CNFGB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 A2h Table 02h, Register 8Bh: CNFGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 A2h Table 02h, Register 8Ch: DEVICE ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 A2h Table 02h, Register 8Dh: CNFGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 A2h Table 02h, Register 8Eh: RIGHT-SHIFT1 (RSHIFT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 A2h Table 02h, Register 8Fh: RIGHT-SHIFT0 (RSHIFT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 A2h Table 02h, Register 90h-91h: XOVER COARSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 A2h Table 02h, Register 92h-93h: VCC SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register 94h-95h: TXB SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register 96h-97h: TXP SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register 98h-99h: RSSI FINE SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register 9Ah-9Bh: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register 9Ch-9Dh: RSSI COARSE SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register 9Eh-9Fh: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 A2h Table 02h, Register A0h-A1h: XOVER FINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register A2h-A3h: VCC OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register A4h-A5h: TXB OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Maxim Integrated 5 DS1884 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Table 02h, Register A6h-A7h: TXP OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register A8h-A9h: RSSI FINE OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register AAh-ABh: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register ACh-ADh: RSSI COARSE OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 A2h Table 02h, Register AEh-AFh: INTERNAL TEMP OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A2h Table 02h, Register B0h-B3h: PW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A2h Table 02h, Register B4h-B7h: PW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 A2h Table 02h, Register B8h-BFh: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 A2h Table 02h, Register C0h: PW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 A2h Table 02h, Register C1h: PW_ENB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 A2h Table 02h, Register C2h-C6h: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A2h Table 02h, Register C7h: TBLSELPON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A2h Table 02h, Register C8h-C9h: DAC VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A2h Table 02h, Register CAh: INCBYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 A2h Table 02h, Register CBh: TXCTRL5 DPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 A2h Table 02h, Register CCh: IMODMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 A2h Table 02h, Register CDh: IBIASMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 A2h Table 02h, Register CEh: DEVICE ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 A2h Table 02h, Register CFh: DEVICE VER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 A2h Table 02h, Register D0h-DFh: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 A2h Table 02h, Register E0h: RXCTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 A2h Table 02h, Register E1h: RXCTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 A2h Table 02h, Register E2h: SETCML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A2h Table 02h, Register E3h: SETLOSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A2h Table 02h, Register E4h: TXCTRL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A2h Table 02h, Register E5h: TXCTRL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 A2h Table 02h, Register E6h: TXCTRL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 A2h Table 02h, Register E7h: TXCTRL4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 A2h Table 02h, Register E8h: TXCTRL5 APC OL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A2h Table 02h, Register E9h: TXCTRL6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A2h Table 02h, Register EAh: TXCTRL7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 A2h Table 02h, Register EBh: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A2h Table 02h, Register ECh: SETLOSH_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A2h Table 02h, Register EDh: SETLOSL_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 A2h Table 02h, Register EEh: SETLOSTIMER_3945 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 A2h Table 02h, Register EFh: 3WSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Maxim Integrated 6 DS1884 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Table 02h, Register F0h: 3WCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A2h Table 02h, Register F1h: ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A2h Table 02h, Register F2h: WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A2h Table 02h, Register F3h: READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A2h Table 02h, Register F4h: TXSTAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A2h Table 02h, Register F5h: TXSTAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A2h Table 02h, Register F6h: DPCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A2h Table 02h, Register F7h: RXSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A2h Table 02h, Register F8h-FFh: RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A2h Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 A2h Table 04h, Register 80h-A7h or 80h-9Fh: MODULATION or TXCTRL5 LUT . . . . . . . . . . . . . . . . . . . . . 86 A2h Table 04h, Register A8h-EFh: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 A2h Table 04h, Register F0h-F7h: MOD MAX LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 A2h Table 04h, Register F8h-FFh: MOD OFFSET or SET_IMOD LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 A2h Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 A2h Table 06h, Register 80h-A7h: BIAS or APC LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 A2h Table 06h, Register A8h-EFh: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 A2h Table 06h, Register F0h-F7h: BIAS MAX LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 A2h Table 06h, Register F8h-FFh: BIAS OFFSET or SET_IBIAS LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 A2h Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A2h Table 08h, Register 80h-F7h: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A2h Table 08h, Register F8h-FBh: BIASINC LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A2h Table 08h, Register FCh-FFh: MODINC LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A2h Table 09h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 A2h Table 09h, Register 80h-F7h: EMPTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 A2h Table 09h, Register F8h-FFh: DAC OFFSET LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Auxiliary Memory A0h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Auxiliary Memory A0h, Register 00h-FFh: EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Maxim Integrated 7 DS1884 SFP and PON ONU Controller with Digital LDD Interface LIST OF FIGURES Figure 1. ADC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 2. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 3. RSSI Differential Input for High-Side RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4. Laser Bias (TXB) and Laser Power (TXP) Monitoring Through TXMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5. RSSI in APD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. RSSI in PIN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 8. Recommended Shunt Reference and RC Filter for DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. Delta-Sigma Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12a. TXFOUT Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12b. TXFOUT Latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12c. TXFOUT During Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. 3-Wire Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. 3-Wire Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 15. Offset LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 16. MODULATION LUT (Open Loop and APC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 17. BIAS LUT (Open Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 18. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 19. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 20. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maxim Integrated 8 DS1884 SFP and PON ONU Controller with Digital LDD Interface LIST OF TABLES Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3. RSSI Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4. RSSI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5. 3-Wire Transaction Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. 3-Wire Register Map and DS1884 Corresponding Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7. DS1884 LUT Functions in Open Loop, APC Loop, and Dual Closed-Loop Modes . . . . . . . . . . . . . . . . . . . . 31 Table 8. DS1884 LUT Memory Map for 4-Row Table (Temperature Values Indicated in C) . . . . . . . . . . . . . . . . . . . . 32 Table 9. DS1884 LUT Memory Map for 4-Row Table (TINDEX Values Indicated in Hex) . . . . . . . . . . . . . . . . . . . . . . 32 Table 10. DS1884 LUT Memory Map for 5-Row Table (Temperature Values Indicated in C) . . . . . . . . . . . . . . . . . . . 32 Table 11. DS1884 LUT Memory Map for 5-Row Table (TINDEX Values Indicated in Hex) . . . . . . . . . . . . . . . . . . . . . . 32 Table 12. Temperature Resolution for Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Power Leveling Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maxim Integrated 9 DS1884 SFP and PON ONU Controller with Digital LDD Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on IN1, DAC, LOS, RSSIP, RSSIN, REFIN, RSEL, TXF, TXMON and TXD Pins Relative to Ground................. -0.5V to (VCC + 0.5V) (subject to not exceeding +6V) Voltage Range on VCC, SDA, SCL, TXFOUT and LOSOUT Pins Relative to Ground.................-0.5V to +6V Continuous Power Dissipation (TA = +70NC) TQFN (derate 28.6mW/NC above +70NC)................2285.7mW Operating Temperature Range........................... -40NC to +95NC Programming Temperature Range........................ 0NC to +95NC Storage Temperature Range............................. -55NC to +125NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.85 3.6 V Main Supply Voltage VCC High-Level Input Voltage (SDA, SCL, SDAOUT) VIH:1 0.7 x VCC VCC + 0.3 V Low-Level Input Voltage (SDA, SCL, SDAOUT) VIL:1 -0.3 +0.3 x VCC V High-Level Input Voltage (IN1, LOS, RSEL, TXD, TXF) VIH:2 2.0 VCC + 0.3 V Low-Level Input Voltage (IN1, LOS, RSEL, TXD, TXF) VIL:2 -0.3 +0.8 V TYP MAX UNITS 1 2 mA 1 FA (Note 1) DC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL Supply Current ICC Output Leakage (LOSOUT, SDA, SDAOUT, TXFOUT) ILO Low-Level Output Voltage (CSEL1OUT, CSEL2OUT, LOSOUT, SDA, SDAOUT, SCLOUT, TXDOUT, TXFOUT) VOL High-Level Output Voltage (CSEL1OUT, CSEL2OUT, SCLOUT, SDAOUT, TXDOUT) VOH Input Leakage Current (IN1, LOS, RSEL, SCL, TXD, TXF) CONDITIONS MIN (Notes 1, 2) IOL = 4mA 0.4 V IOL = 6mA IOH = 4mA 0.6 VCC 0.4 ILI V 1 FA Digital Power-On Reset POD 2.1 2.6 V Analog Power-On Reset POA 2.2 2.8 V Maxim Integrated 10 DS1884 SFP and PON ONU Controller with Digital LDD Interface DAC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Delta-Sigma Input Clock Frequency Reference Voltage Input (REFIN) SYMBOL CONDITIONS VREFIN Minimum 0.1F to GND RDS tINIT_DAC MAX MHz VCC V 0 VREFIN V 10 Bits 100 I See the Startup Timing Characteristics table ms VREFIN = 2.5V 45 From VCC > VCC LO alarm or warning UNITS 2 See the Delta-Sigma Output and Reference section for details (DAC FS[9:2] = FFh) Output Resolution Recovery After Power-Up TYP 2 fDS Output Range Output Impedance MIN ANALOG VOLTAGE MONITORING CHARACTERISTICS (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS ADC Resolution (Note 3) INL TA = +25NC tRR Update Rate for RSSIP-RSSIN Input/Supply Offset (TXMON, RSSIP, RSSIN, VCC) TYP MAX UNITS -3 +3 LSB -1 +1 LSB 13 DNL Update Rate for Temperature, TXMON (TXB/TXP), RSSIPRSSIN, VCC MIN Bits RSSIP-RSSIN requires only a coarse conversion (Note 4) 30 ms tR/R2 RSSIP-RSSIN requires a fine conversion 36 ms VOS (Notes 4, 5) -1 TXMON and RSSIP-RSSIN coarse (Notes 5, 6) Factory Setting Full Scale 0 +1 2.5 LSB V VCC (Note 6) 6.5536 RSSIP-RSSIN fine (Note 6) 312.5 V 1/256 NC Temperature LSB Weighting DIGITAL THERMOMETER CHARACTERISTICS (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Thermometer Error Maxim Integrated SYMBOL TERR CONDITIONS -40NC to +95NC MIN -2 TYP MAX UNITS +2 NC 11 DS1884 SFP and PON ONU Controller with Digital LDD Interface AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TXD Rising Edge to Fault Clear tOFF From h TXD (Notes 7, 8) 5 Fs TXD Falling Edge to TXDOUT Falling tON From i TXD (Note 9) 5 Fs Recovery After Power-Up: MAX3710 tINIT_3710 From h VCC > POA (Note 10) 1 ms Recovery After Power-Up: MAX3710 and MAX3945 tINIT_3945 From h VCC > VCC LO alarm or warning (Note 11) 1 ms 30 ms 12.5 ms Fault Assert Time (to TXFOUT = 1) tINITR1 From i TXD Fault Reset Time at Power-On (to TXFOUT = 0) tINITR2 From h VCC > POA, Figure 12c (Note 12) STARTUP TIMING CHARACTERISTICS (VCC= +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL Output Enable Time Following POA CONDITIONS MIN (Notes 12, 13) tINIT TYP MAX 13 UNITS ms 3-WIRE DIGITAL INTERFACE SPECIFICATION (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted. Timing is referenced to VIL(MAX) and VIH(MIN).) (See Figure 13.) PARAMETER SCLOUT Clock Frequency SCLOUT Duty Cycle SYMBOL CONDITIONS MIN TYP MAX UNITS fSCLOUT 1 MHz t3WDC 50 % 500 ns SDAOUT Setup Time tDS SDAOUT Hold Time tDH 100 ns CSEL1OUT, CSEL2OUT Pulse-Width Low tCSW 1 Fs CSEL1OUT, CSEL2OUT Leading Time Before the First SCLOUT Edge tL 1 Fs CSEL1OUT, CSEL2OUT Trailing Time After the Last SCLOUT Edge tT 1 Fs SDAOUT, SCLOUT Load Maxim Integrated CB3W Total bus capacitance on one line 10 pF 12 DS1884 SFP and PON ONU Controller with Digital LDD Interface I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.6V, TA = -40NC to +95NC, unless otherwise noted. Timing is referenced to VIL(MAX) and VIH(MIN).) (See Figure 18.) PARAMETER SCL Clock Frequency SYMBOL fSCL CONDITIONS (Note 14) MIN TYP 0 MAX UNITS 400 kHz Clock Pulse-Width Low tLOW 1.3 Fs Clock Pulse-Width High tHIGH 0.6 Fs Bus Free Time Between STOP and START Condition tBUF 1.3 Fs START Hold Time tHD:STA 0.6 Fs START Setup Time tSU:STA 0.6 Fs Data in Hold Time tHD:DAT 0 Data in Setup Time tSU:DAT 100 0.9 Fs ns Rise Time of Both SDA and SCL Signals tR (Note 15) 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF (Note 15) 20 + 0.1CB 300 ns 400 pF 20 ms MAX UNITS STOP Setup Time 0.6 tSU:STO Capacitive Load for Each Bus Line CB EEPROM Write Time tW Fs (Note 16) NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.85V to +3.6V, unless otherwise noted.) PARAMETER EEPROM Write Cycles SYMBOL CONDITIONS MIN At TA = +25NC 50,000 At TA = +85NC 10,000 TYP -- Note 1: All voltages are referenced to ground. Current entering the IC is considered positive, and current exiting the IC is considered negative. Note 2: Inputs are at supply rail. Outputs are not loaded. Does not include REFIN current. Measured using the Typical Operating Circuit--GPON ONU. Note 3: The ADC output is available internally as a 16-bit value. The 16 bits are derived by left-shifting the 13-bit ADC output by 3. Note 4: Guaranteed by design. Note 5: TXB (transmit bias) and TXP (transmit power) are separate ADC conversions that are performed on the same input pin, TXMON. Note 6: Full scale is user-programmable. Note 7: Time until faults are cleared (falling edge of TXFOUT). Note 8: Time until rising edge of TXDOUT. Note 9: Time until falling edge of TXDOUT. Note 10: Time until completion of initial MAX3710 control registers configuration. Note 11: Time until completion of initial MAX3945 and MAX3710 control registers configuration. Note 12: VCC LO alarm or warning is enabled, a VCC conversion is completed, and VCC is above VCC LO alarm or warning. See Figure 12c. Note 13: DAC output valid, 3-wire writes from LUTs complete, and digital outputs valid. Note 14: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode. Note 15: CB = Total capacitance of one bus line in pF. Note 16: EEPROM write begins after a STOP condition occurs. Maxim Integrated 13 DS1884 SFP and PON ONU Controller with Digital LDD Interface Typical Operating Characteristics (TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE +95C 0.65 0.60 +25C 0.55 0.50 -40C 0.45 0.9 VCC = 3.9V 0.8 SUPPLY CURRENT (mA) 0.40 0.7 0.6 0.5 0.3 0.2 0.35 0.1 SDA = SCL = VCC 0.30 2.85 3.10 3.35 3.60 SDA = SCL = VCC 0 3.85 10 -40 VCC (V) TXMON AND RSSI DNL 1 0 -1 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V -3 0 0.5 1.0 1.5 2.0 VCC = 3.3V 0.8 TXMON AND RSSI DNL (LSB) 2 TXMON AND RSSI INL (LSB) 1.0 DS1884 toc03 VCC = 3.3V -2 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 USING-FACTORY PROGRAMMED FULL-SCALE VALUE OF 2.5V -0.8 -1.0 0 2.5 0.5 1.0 1.5 2.0 2.5 TXMON AND RSSI INPUT VOLTAGE (V) TXMON AND RSSI INPUT VOLTAGE (V) DAC INL DAC DNL 1.5 0.8 0.6 DAC DNL (LSB) 1.0 0.5 0 -0.5 DS1884 toc06 1.0 DS1884 toc05 2.0 DAC INL (LSB) 60 TEMPERATURE (C) TXMON AND RSSI INL 3 0.4 0.2 0 -0.2 -0.4 -1.0 -0.6 -1.5 -0.8 -2.0 -1.0 0 100 200 300 DAC POSITION (DEC) Maxim Integrated VCC = 2.85V VCC = 3.3V 0.4 DS1884 toc04 SUPPLY CURRENT (mA) 0.70 DS1884 toc02 0.75 SUPPLY CURRENT vs. TEMPERATURE 1.0 DS1884 toc01 0.80 400 500 0 100 200 300 400 500 DAC POSITION (DEC) 14 DS1884 SFP and PON ONU Controller with Digital LDD Interface TXF LOSOUT SDAOUT SCLOUT CSEL1OUT Pin Configuration 24 23 22 21 20 TOP VIEW + Pin Description PIN NAME FUNCTION 1 CSEL2OUT 2 SCL I2C Serial-Clock Input 3 SDA Open-Drain I2C Serial-Data Input/ Output 4 TXFOUT Open-Drain Transmit Fault Output 5 LOS Loss-of-Signal Input Chip-Select Output. Part of the 3-wire interface to the MAX3945. CSEL2OUT 1 19 REFIN SCL 2 18 DAC 6 IN1 Digital Maskable Fault Input SDA 3 17 GND 7 TXD Transmit Disable Input TXFOUT 4 16 VCC 8, 15, 17 GND Ground LOS 5 15 GND 9 RSEL Rate Select Input IN1 6 14 VCC 10 TXDOUT TXD 7 13 TXMON 11, 12 RSSIP, RSSIN Differential External Monitor Input 13 TXMON External Monitor Input for Both Transmit Power (TXP) and Transmit Bias (TXB) DS1884 8 9 10 11 12 GND RSEL TXDOUT RSSIP RSSIN EP TQFN (4mm x 5mm x 0.75mm) Maxim Integrated Transmit Disable Output 14, 16 VCC Power-Supply Input 18 DAC DAC Output 19 REFIN 20 CSEL1OUT Chip-Select Output. Part of the 3-wire interface to the MAX3710. 21 SCLOUT Serial-Clock Output. Part of the 3-wire interface to the MAX3710. 22 SDAOUT Serial-Data Input/Output. Part of the 3-wire interface to the MAX3710. 23 LOSOUT Open-Drain Receive Loss-ofSignal Output 24 TXF Transmit Fault Input -- EP Exposed Pad. Connect to ground. Reference Input for DAC Full Scale 15 DS1884 SFP and PON ONU Controller with Digital LDD Interface Block Diagram REFIN A2h MEMORY EEPROM/SRAM SDA SCL I2C INTERFACE VCC EEPROM 256 BYTES AT A0h 10-BIT DELTA-SIGMA DAC ADC CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY SDAOUT VCC 3-WIRE MASTER TXB SCLOUT CSEL1OUT CSEL2OUT TXMON ANALOG MUX TXP RSSIP 13-BIT ADC DS1884 POA AND POD RESET RSSIN TXFOUT TEMPERATURE SENSOR TXD VCC CONFIGURABLE LOGIC TXF TXDOUT IN1 RSEL LOSOUT CONFIGURABLE LOGIC LOS GND Maxim Integrated 16 DS1884 SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit--GPON ONU DS3920 DC-DC OUTPUT CURRENT MONITOR APD-TIA MAX3710 LA LOS LOS DAC 3W MD AND DFB MOD DAC FAULT DISABLE BIAS DAC LPD LASER SIGNAL DETECT LDD MDIN BMON 3W 2.5V REF DC-DC CONTROL REFIN BENP/N DS1884 EEPROM IN1 TXF TXFOUT TXDOUT TXD TX_DISABLE DAC I2C TXMON RSSIP RSSIN Maxim Integrated TX_FAULT ADC SDA SCL RSEL LOS LOSOUT MODE_DEF2 (SDA) MODE_DEF1 (SCL) RATE SELECT LOS 17 DS1884 SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit--10G PON ONU DS3920 DC-DC OUTPUT CURRENT MONITOR 10G APD-TIA MAX3945 10G LA LOS 3W MAX3710 3W MD AND DFB MOD DAC FAULT DISABLE BIAS DAC LPD LASER SIGNAL DETECT LDD MDIN BMON 3W 2.5V REF DC-DC CONTROL REFIN BENP/N DS1884 EEPROM IN1 TXF TXFOUT TXDOUT TXD TX_DISABLE DAC I2C TXMON RSSIP RSSIN Maxim Integrated TX_FAULT ADC SDA SCL RSEL LOS LOSOUT MODE_DEF2 (SDA) MODE_DEF1 (SCL) RATE SELECT LOS 18 DS1884 SFP and PON ONU Controller with Digital LDD Interface Detailed Description Table 1. Acronyms ACRONYM DESCRIPTION ADC Analog-to-Digital Converter APC Automatic Power Control APD Avalanche Photodiode DAC Digital-to-Analog Converter LOS Loss of Signal LUT LUT NV Nonvolatile QT Quick Trip ROSA Monitors and Fault Detection Shadowed EEPROM SFF Small Form Factor SFP SFP+ Monitors The DS1884 monitors five ADC channels. This monitoring combined with the alarm enables (A2h Table 01h/05h) determines when/if the DS1884 turns off the MAX3710 DACs and triggers the TXFOUT and TXDOUT outputs. All the monitoring levels and interrupt masks are userprogrammable. See Figure 1. Receiver Optical Subassembly SEE SFF-8472 The DS1884 integrates the control and monitoring functionality required to implement an SFP or PON ONU system using the Maxim MAX3710 or other compatible laser driver and limiting amplifier. Key components of the DS1884 are shown in the Block Diagram and described in subsequent sections. Document Defining Register Map of SFPs and SFFs Small Form-Factor Pluggable Enhanced SFP TE Tracking Error. Deviation from linear of the relationship between transmitted power and monitor diode current. TIA Transimpedance Amplifier TOSA TXP Transmit Optical Subassembly Transmit Power ADC Monitors and Alarms The ADC monitors temperature (internal temp sensor), VCC, laser bias (TXB), laser power (TXP), and receive power (RSSIC for coarse, RSSIF for fine) using an analog multiplexer to measure them round-robin with a single ADC (see the ADC Timing section). The voltage channels have a customer-programmable full-scale range and all channels have a customer-programmable offset value that is factory programmed to a default value (Table 2). Table 2. ADC Default Monitor Full-Scale Ranges +FS SIGNAL +FS HEX -FS SIGNAL -FS HEX Temperature (C) SIGNAL (UNITS) 127.996 7FFFh -128 8000h VCC (V) 6.5528 FFF8h 0 0000h TXB, TXP, RSSIC, RSSIF (V) 2.4997 FFF8h 0 0000h SCALE REGISTERS ANALOG INPUT OFFSET REGISTERS ADC 13 RIGHT-SHIFT SETTINGS 13 SHIFT 13 COMPARE COUPLED* ALARM/ WARNING FLAGS ALARM AND WARNING THRESHOLDS TXFINT ALARM/ WARNING ENABLES *USER MUST CALIBRATE THE GAIN USING THE SCALE REGISTERS IN CASE RIGHT-SHIFTING IS DESIRED TO MAINTAIN CORRECT BIT WEIGHTING. Figure 1. ADC Channel Maxim Integrated 19 DS1884 SFP and PON ONU Controller with Digital LDD Interface Additionally, TXB, TXP, RSSIC, and RSSIF can right-shift results as described in the Right-Shifting ADC Result section. This allows customers with specified ADC ranges to calibrate the ADC input gain by a factor of 2n to measure small signals (thereby reducing the full scale by a factor of 2n). The DS1884 can then right-shift the results by n bits (effectively multiplying by a factor of 1/2n) to maintain the bit weight of their specification. See the Right-Shifting ADC Result and Enhanced RSSI Monitoring (Dual Range Functionality) sections for more information. alternate sending laser bias (TXB) and laser power (TXP) signals to the DS1884's TXMON input. Right-Shifting ADC Result If the weighting of the ADC digital reading must conform to a predetermined full-scale (PFS) value defined by a standard's specification (e.g., SFF-8472), then right-shifting can be used to adjust the PFS analog measurement range while maintaining the weighting of the ADC results. The DS1884's range is wide enough to cover all requirements; when the maximum input value is 1/2 of the full-scale value, rightshifting can be used to obtain greater accuracy. Alarms and Warnings The ADC results (after right-shifting, if used) are compared to the alarm and warning thresholds after each conversion, and the corresponding alarms and/or warnings are set, which can be programmed to create the internal signal TXFINT. The status of TXFINT can be read in A2h Lower Memory, Register 71h. TXFINT is one of the signals used to trigger TXFOUT. TXFOUT can be programmed to cause TXDOUT outputs. These ADC thresholds are user-programmable, as are the masking registers that can be used to prevent the alarms from triggering the TXFOUT and TXDOUT outputs. For instance, the maximum voltage might be 1/8 the specified PFS value, so only 1/8 the converter's range is effective over this range. An alternative is to calibrate the ADC's full-scale range to 1/8 the readable PFS value (by calibrating an input gain of about 8 using the scale registers) and use a right-shift value of 3. With this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standard's specification (i.e., SFF-8472). The right-shift operation on the ADC result is carried out based on the contents of right-shift control registers (A2h Table 02h, Register 8Eh and A2h Table 02h, Register 8Fh) in EEPROM. TXB, TXP, RSSIC, and RSSIF have 3 bits allocated to set the number of right-shifts. Up to seven right-shift operations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (Lower Memory, Registers 64h-69h). This is true during the setup of internal calibration as well as during subsequent data conversions. ADC Timing Five analog channels are digitized in a round-robin fashion in the order as shown in Figure 2. RSSI is measured twice to obtain coarse and fine measurements (RSSIC and RSSIF, respectively). The total time required to convert all channels is tRR (see the Analog Voltage Monitoring Characteristics table for details). After each TXMON conversion, a 3-wire communication is initiated to toggle the MON_SEL bit (bit 6 in the MAX3710's TXCTRL2 register, programmed through A2h Table 02h, Register E5h, bit 6). This causes the laser driver to tRR TEMP VCC TXB TOGGLE MON_SEL RSSIC RSSIF TXP TEMP TOGGLE MON_SEL NOTE: IF VCC LO ALARM OR WARNING IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LO ALARM THRESHOLD. Figure 2. ADC Round-Robin Timing Maxim Integrated 20 DS1884 SFP and PON ONU Controller with Digital LDD Interface Differential RSSI Input The DS1884 offers a fully differential input for RSSI that enables high-side monitoring of RSSI, as shown in Figure 3. This reduces board complexity by eliminating the need for a high-side differential amplifier or a current mirror. Laser Bias and Laser Power Through TXMON The DS1884 measures both laser bias (TXB) and laser power (TXP) through the same input pin, TXMON. The DS1884 commands the MAX3710 laser driver to output the correct monitor signal before each ADC conversions takes place. Figure 4 shows the two conversion paths. Each path has independent gain and offset calibration registers. VCC DS1884 RSSIP 680 ADC RSSIN ROSA Figure 3. RSSI Differential Input for High-Side RSSI Enhanced RSSI Monitoring (Dual Range Functionality) The DS1884 offers a feature to improve the accuracy and range of RSSI, which is most commonly used for monitoring RSSI. To achieve the SFF-8472 requirement of 0.1W/LSB over -40 to 8.2dBm, the DS1884 makes two measurements to effectively achieve a 16-bit conversion with a 13-bit physical ADC. This "dual range" calibration can operate in two modes: APD mode and PIN mode. APD Mode For systems with a nonlinear relationship between the ADC input and desired ADC result, the mode should be set to APD mode (Figure 5). The RSSI measurement of an APD receiver is one such application. Using the APD mode allows a piece-wise linear approximation of the nonlinear response of the APD's gain factor. The crossover point is the point between fine and coarse points. The ADC result transitions between the fine and coarse ranges with no hysteresis. Right-shifting, slope adjustment, and offset are configurable for both the fine and coarse ranges. Two registers, XOVER FINE and XOVER COARSE, determine the crossover point. The XOVER FINE register (A2h Table 02h, Register A0h-A1h) determines the maximum results returned by fine ADC conversions, before right-shifting. The XOVER COARSE register (A2h Table 02h, Register 90h-91h) determines the minimum results returned by coarse ADC conversions, before right-shifting. MAX3710 MAX3710 BMON BMON MON_SEL = 1 MON_SEL = 0 DS1884 TXB DS1884 TXB ADC TXMON ADC TXMON TXP TXP ADC ADC Figure 4. Laser Bias (TXB) and Laser Power (TXP) Monitoring Through TXMON Maxim Integrated 21 DS1884 SFP and PON ONU Controller with Digital LDD Interface CO AR SE CROSSOVER POINT FU LL -S CA LE RE SP ON SE RSSI RESULT ONSE CALE RESP FINE FULL-S IDEAL RESPONSE RSSI INPUT APD MODE Figure 5. RSSI in APD Mode PON SE RSSI RESULT RES ALE L-SC FUL FINE T= HIF S HT- IG ER FIN SE AR CO L CA L-S L FU E NS PO ES ER 3 HYSTERESIS RSSI INPUT FINE COARSE PIN MODE Figure 6. RSSI in PIN Mode PIN Mode The PIN mode is intended for systems with a linear relationship between the RSSI input and desired ADC result. The ADC result transitions between the fine and coarse ranges with hysteresis, as shown in Figure 6. Maxim Integrated In PIN mode, the thresholds between coarse and fine mode are a function of the number of right-shifts being used. With the use of right-shifting, the fine mode full scale is programmed to (1/2nth) of the coarse mode full scale. The DS1884 now auto ranges to choose the range that gives the best resolution for the measurement. Table 3 shows the threshold values for each possible number of right-shifts. 22 DS1884 SFP and PON ONU Controller with Digital LDD Interface Low-Voltage Operation The DS1884 contains two power-on reset (POR) levels. The lower level is a digital POR (POD) and the higher level is an analog POR (POA). At startup, before the supply voltage rises above POA, the outputs are disabled, all SRAM locations are set to their defaults, shadowed EEPROM locations are zero, and all analog circuitry is disabled. When VCC reaches POA, the SEE is recalled, and the analog circuitry is enabled. While VCC remains above POA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below POA, but is still above POD, the SRAM retains the SEE settings from the first SEE recall, but the device analog is shut down and the outputs are disabled. If the supply voltage recovers back above POA, the device immediately resumes normal operation. If the supply voltage falls below POD, the device SRAM is placed in its default state and another SEE recall is required to reload the nonvolatile settings. The EEPROM recall occurs the next time VCC next exceeds POA. Figure 7 shows the sequence of events as the voltage varies. Any time VCC is above POD, the I2C interface can be used to determine if VCC is below the POA level. This is accomplished by checking the RDYB bit in the STATUS byte (A2h Lower Memory, Register 6Eh). RDYB is set when VCC is below POA; when VCC rises above POA, RDYB is timed (within 500Fs) to go to 0, at which point the part is fully functional. For all device addresses sourced from EEPROM (A2h Table 02h, Register 8Ch), the default DEVICE ADDRESS is A2h until VCC exceeds POA, allowing the device address to be recalled from the EEPROM. Table 3. RSSI Hysteresis Threshold Values # OF RIGHTSHIFTS FINE MODE MAX (HEX) COARSE MODE MIN* (HEX) 0 FFF8h F000h 1 7FFCh 7800h 2 3FFEh 3C00h 3 1FFFh 1E00h 4 0FFFh 0F00h 5 07FFh 0780h 6 03FFh 03C0h 7 01FFh 01E0h *This is the minimum reported coarse mode conversion. Power-On Analog (POA) POA holds the DS1884 in reset until VCC is at a suitable level (VCC > POA) for the device to accurately measure with its ADC and compare analog signals with its quicktrip monitors. Because VCC cannot be measured by the ADC when VCC is less than POA, POA also asserts the VCC LO alarm, which is cleared by a VCC ADC conversion greater than the customer-programmable VCC low ADC limit. This allows a programmable limit to ensure that the head room requirements of the transceiver are satisfied during a slow power-up. The TXFOUT output does not latch until there is a conversion above the VCC low limit. The POA alarm is nonmaskable. See the LowVoltage Operation section for more information. Table 4. RSSI Configuration Registers REGISTER FINE MODE COARSE MODE Gain Register (RSSI FINE/COARSE SCALE) 98h-99h, A2h Table 02h 9Ch-9Dh, A2h Table 02h Offset Register (RSSI FINE/COARSE OFFEST) A8h-A9h, A2h Table 02h ACh-ADh, A2h Table 02h 8Eh, A2h Table 02h N/A RIGHT-SHIFT1 Register RSSIC and RSSIF Bits (RIGHT-SHIFT0) RSSIR Bit (UPDATE) RSSI Measurement (RSSI VALUE) Maxim Integrated 8Fh, A2h Table 02h 6Fh, A2h Lower Memory 68h-69h, A2h Lower Memory 23 DS1884 SFP and PON ONU Controller with Digital LDD Interface SEE RECALL SEE RECALL VPOA VCC VPOD SEE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 Figure 7. Low-Voltage Hysteresis Example Delta-Sigma Output and Reference VCC One delta-sigma output (DAC) is provided. This provides a 9-bit resolution output. The maximum voltage output is set by the input REFIN. An inexpensive shunt reference is recommended to generate the voltage applied to REFIN, as shown in Figure 8. The output includes the ability to compensate the APD bias for temperature as given by the following formula: 1k 0201 REFIN DS1884 2.5V 0.1F 0201 68.1k 0201 39.2k 0201 ZTL431A SOT23 DAC 1F 0402 20k 0201 CONNECT TO CONTROL INPUT ON DC-DC Figure 8. Recommended Shunt Reference and RC Filter for DAC Output DAC_INT = TINDEX[6:0] + DAC OFFSET If INV_DAC = 0, then DAC[9:0] = DAC_INT/DACFS x VREFIN. If INV_DAC = 1, then DAC[9:0] = [3FF - (DAC_INT/ DACFS)] x VREFIN. where: 1) INV_DAC is at A2h Table 02h, Register 8Dh, bit 7. 2) TINDEX is at A2h Table 02h, Register 81h. 3) DAC OFFSET is an 8-bit value, representing the 8 MSBs of a 10-bit value. The two LSBs are 0. 4) DACFS (A2h Table 02h, Register 88h) is an 8-bit value, representing the 8 MSBs of a 10-bit value. The two LSBs are 0. 5) DAC is a 10-bit value. 6) The DAC[9:0] is clamped at DACFS. 7) DAC_INT is an internal signal. Maxim Integrated 24 DS1884 SFP and PON ONU Controller with Digital LDD Interface O 1 2 3 4 5 6 7 Figure 9. Delta-Sigma Output The delta-sigma output uses pulse-density modulation. It provides much lower output ripple than a standard digital PWM output given the same clock rate and filter components. An RC filter is required on the DAC output as suggested in Figure 8. The external RC filter components are chosen based on ripple requirements, output load, delta sigma frequency, and desired response time. Before tINIT, the DAC output is high impedance. Maxim Integrated The reference input, REFIN, is the supply voltage for the DAC's output buffer. The voltage source connected to REFIN must be able to support the edge rate requirements of the delta sigma outputs. In a typical application, a 0.1uF capacitor should be connected between REFIN and ground. The DS1884's delta-sigma output is 9 bits. For illustrative purposes, a 3-bit example is provided in Figure 9. 25 DS1884 SFP and PON ONU Controller with Digital LDD Interface VCC TXDS RPU TXD C TXDC TXDIO Q C D TXD R TXDOUT Q S TXDFLT TXFOUTS TXFOUT TXFINT INVTXF TXF FAULT RESET TIMER (130ms) OUT IN tINITR1 IN OUT PINS TXFS POWER-ON RESET IN1EN IN1 IN1S Figure 10. Logic Diagram 1 6Eh) as the RXL bit. The RXL signal can be inverted (INV LOS = 1) before driving the open drain output transistor. RSELS 3-WIRE SET_LOS_3945 RSEL = PINS Figure 11. Logic Diagram 2 Digital I/O Pins Five digital inputs and three digital output pins are provided for monitoring and control. LOS, LOSOUT By default, the LOS pin is used to convert a standard comparator output for loss of signal (LOS) to an opencollector output (LOSOUT). The status of LOS can be read in the STATUS byte (A2h Lower Memory, Register Maxim Integrated RSEL The level of RSEL can be read by reading the STATUS register (A2h Lower Memory, Register 6Eh). The status of RSEL determines whether SETLOSL or SETLOSH is written to the MAX3945 register SET_LOS. TXD, TXDOUT TXDOUT is generated from a combination of TXFOUT and TXD (see the CNFGC register A2h Table 02h, Register 8Bh for enabling these options). A software control identical to TXD is available (TXDC, A2h Lower Memory, Register 6Eh). A TXD pulse is internally extended (tINITR1) to inhibit the latching of low alarms and warnings. The intended use is a direct connection to the MAX3710's DISABLE input if this is desired. When VCC < POA, TXDOUT is high impedance. 26 DS1884 SFP and PON ONU Controller with Digital LDD Interface IN1, TXF, Transmit Fault (TXFOUT) Output TXFOUT can be triggered by all alarms and warnings and also the pins TXF and IN1 (Figure 10). The ADC alarms and warnings require enabling (A2h Table 01h/05h, Registers F8h and FDh). See Figure 12a and Figure 12b for nonlatched and latched operation. Figure 12c describes this TXFOUT behavior during power-on. Latching of the alarms is controlled by CNFGB and CNFGC Registers (A2h Table 02h, Register 8Ah and A2h Table 02h, Register 8Bh). Die Identification The DS1884 has an ID hardcoded in its die. Two registers (DEVICE ID A2h Table 02h, Register CEh and DEVICE VER A2h Table 02h, Register CFh) are assigned for this feature. Register CEh reads 84h to identify with the device as the DS1884, and Register CFh reads the present device version. DETECTION OF TXFOUT FAULT TXFOUT Figure 12a. TXFOUT Nonlatched Operation DETECTION OF TXFOUT FAULT TXD OR TXF RESET TXFOUT Figure 12b. TXFOUT Latched VCC VPOA tINITR2 TXFOUT1 TXFOUT2 CONDITION 1: VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXF. VCC IS ABOVE CORRESPONDING VCC LO ALARM/WARNING THRESHOLD. CONDITION 2: VCC LO ALARM AND WARNING FLAGS ARE NOT ENABLED. Figure 12c. TXFOUT During Power-On Maxim Integrated 27 DS1884 SFP and PON ONU Controller with Digital LDD Interface DS1884 Master Communication Interface device(s). It is a 3-pin interface consisting of SDAOUT, a bidirectional data line; clock signal SCLOUT; and CSEL1OUT chip-select output (active high). A second, independent chip select (CSEL2OUT) is provided for use with the MAX3945. The DS1884 controls the MAX3710 using a proprietary 3-wire interface. The DS1884 configures the MAX3710 on startup and then continuously updates the MAX3710 with new LUT values. The DS1884 operates in one of three modes: open loop, APC loop, and dual closed loop. The DS1884 can also configure the MAX3945 on startup. The communication between the DS1884 and the MAX3710 and MAX3945 is transparent to the end user. In addition, commands can be issued to the MAX3710 and MAX3945 using the DS1884's manual mode. Protocol The DS1884 initiates a data transfer by asserting the CSEL1OUT or CSEL2OUT pin. It then starts to generate a clock signal after CSEL1OUT or CSEL2OUT has been set to 1. Each operation consists of 16 bit transfers (15-bit address/data, 1-bit RWN). All data transfers are MSB first. Write Mode (RWN = 0): The master generates 16 clock cycles at SCLOUT in total. It outputs 16 bits (MSB first) to the SDAOUT line at the falling edge of the clock. The master closes the transmission by setting CSEL1OUT and CSEL2OUT to 0. 3-Wire Master Interface The DS1884 acts as the master, initiating communication with and generating the clock for the Maxim slave Read Mode (RWN = 1): The master generates 16 clock cycles at SCLOUT in total. It outputs 8 bits (MSB first) to the SDAOUT line at the falling edge of the clock. The SDAOUT line is released after the RWN bit has been transmitted. The slave outputs 8 bits of data (MSB first) at rising edge of the clock. The master samples SDAOUT at the falling edge of SCLOUT. The master closes the transmission by setting the CSEL1OUT and CSEL2OUT to 0. Table 5. 3-Wire Transaction Detail BIT NAME 15:9 Address DESCRIPTION 8 RWN 0: write, 1: read 7:0 Data 8-bit read or write data 7-bit internal register address WRITE MODE CSEL_OUT tL tT tCH tCL 0 SCLOUT 1 2 3 4 5 6 7 8 9 A4 A3 A2 A1 A0 RWN D7 D6 10 11 12 13 14 15 tDS SDAOUT A6 A5 D5 D4 D3 D2 D1 D0 tDH READ MODE CSEL_OUT tL tT tCH tCL SCLOUT 0 1 2 3 4 5 6 7 A4 A3 A2 A1 A0 RWN 8 9 10 tRS tDS SDAOUT A6 A5 D7 D6 11 D5 12 D4 13 D3 14 D2 15 D1 D0 tDH NOTE: SEE THE 3-WIRE DIGITAL INTERFACE SPECIFICATION TABLE FOR DETAILS. CSEL_OUT IMPLIES CSEL1OUT OR CSEL2OUT. Figure 13. 3-Wire Interface Timing Diagram Maxim Integrated 28 DS1884 SFP and PON ONU Controller with Digital LDD Interface 3-Wire Slave Register Map and DS1884 Corresponding Location When the MAX3945 registers are written, the MAX3710 are also written simultaneously (Table 6). 3-Wire Master Flowchart Figure 14 explains the working of the 3-wire master in the DS1884 in all three opreating modes. These modes are described in the DS1884 with MAX3710 Operating Modes section. Table 6. 3-Wire Register Map and DS1884 Corresponding Location DS1884 REGISTER (A2h TABLE 02h) DS1884 REGISTER NAME MAX3710 ADDRESS MAX3710 REGISTER NAME MAX3945 ADDRESS MAX3945 REGISTER NAME 82h-83h MODULATION VALUE 0Eh SET_IMOD N/A N/A 85h APC VALUE 11h SET_2XAPC N/A N/A 86h-87h SET_BIAS VALUE 0Dh SET_IBIAS N/A N/A CAh INCBYTE[7:4] 0Fh BIASINC N/A N/A CAh INCBYTE[3:0] 10h MODINC N/A N/A CBh TXCTRL5 DPC 0Ah TXCTRL5 N/A N/A CCh IMODMAX 0Ch IMODMAX N/A N/A CDh IBIASMAX 0Bh IBIASMAX N/A N/A E0h RXCTRL1 01h RXCTRL1 00h RXCTRL1 E1h RXCTRL2 02h RXCTRL2 01h RXCTRL2 E2h SETCML 03h SET_CML 03h SET_CML E3h SETLOSH 04h SET_LOS N/A N/A E4h TXCTRL1 06h TXCTRL1 N/A N/A E5h TXCTRL2 07h TXCTRL2 N/A N/A E6h TXCTRL3 08h TXCTRL3 N/A N/A E7h TXCTRL4 09h TXCTRL4 N/A N/A E8h TXCTRL5 APC OL 0Ah TXCTRL5 N/A N/A E9h TXCTRL6 13h TXCTRL6 N/A N/A EAh TXCTRL7 05h TXCFG N/A N/A ECh SETLOSH_3945 N/A N/A 04h SET_LOS EDh SETLOSL_3945 N/A N/A 04h SET_LOS EEh SETLOSTIMER_3945 N/A N/A 12h SET_LOSTIMER F0h 3WCTRL F1h ADDRESS F2h WRITE F3h READ F4h TXSTAT2 1Fh TXSTAT2 N/A N/A F5h TXSTAT1 1Eh TXSTA1 N/A N/A F6h DPCSTAT 1Dh DPCSTAT N/A N/A F7h RXSTAT 1Ch RXSTAT N/A N/A Maxim Integrated Manual control of read/write from/to 3-wire slave devices; useful for determining correct settings for the slave devices and also for debugging. 29 DS1884 SFP and PON ONU Controller with Digital LDD Interface READ REGISTERS BIAS REG, MOD REG, RXSTAT, DPCSTAT, TXSTAT1, TXSTAT2, SET_2XAPC TXD_STANDBY TOGGLE MONSEL TXD = 1 OR POR = 1 Y N RESET (SET TXD_FLAG IF TXD = 1 AND SET POR_FLAG IF POR = 1) N IDLE WAIT FOR TEMP_CONV TXD = 0? EN_3945 = 1? N N Y TEMP_CONV = 1? Y Y N VCC > VCC LO? WRITE_LUT REGISTERS TXCTRL5 IMODMAX IBIASMAX SET_IMOD SET_IBIAS BIASINC MODINC SET_2XAPC Y WRITE CNTRL MAX3945 READ POR STICKY Y POR_FLAG = 1? N MANMODE = 1? APC_EN = 1? Y STICKY = 1? MANMODE ALLOWS THE USER TO COMMUNICATE WITH MAX3710 USING THE I2C INTERFACE ON DS1884 DPC_EN = 1? WRITE MODINC, SET_IMOD BIASINC, SET_IBIAS N TXD_FLAG = 1? WRITE MODINC, SET_IMOD RSTRT_3710 = 1 OR TXF_LATCHED = 1 STANDBY TOGGLE MONSEL BIT (TXCTRL2[6]) PERIODICALLY RESET FLAGS INC APC Y MANMODE = 1? Y TXD_FLAG = 1? N DPC_EN = 1? N Y WRITE CONTROL RXCTRL1, RXCTRL2, SET_CML, SET_LOS, TXCTRL1, TXCTRL2, TXCTRL3, TXCTRL4 N Y N POR_FLAG = 1? N Y WRITE TXCTRL6 Y WRITE ALL CONTROL REGISTERS IF ENABLED WRITE REGISTERS IBIASMAX IMODMAX TXCTRL5 Y TEMP_CONV = 1 AND DIS3W = 0 N Y TEMP_CONV = 1? AND DIS3W = 0 Y APC_EN = 1? N INC MOD INC BIAS, MOD Figure 14. 3-Wire Flowchart Maxim Integrated 30 DS1884 SFP and PON ONU Controller with Digital LDD Interface DS1884 with MAX3710 Operating Modes DS1884 to fully support the 10-bit bias DAC and 9-bit modulation DAC inside the MAX3710. The user has the option of selecting among open loop, APC loop, and dual closed-loop operation modes. These can be programmed using the DPC_EN and APC_EN bits in the MAX3710 TXCTRL3 register (Address H0x08), programmed through A2h Table 02h, Register E6h. Table 7 indicates what the values in each LUT corresponds to in each of the modes. LUT values are not automatically updated when changing between operating modes. Dual Closed-Loop Mode, DPC_EN = 1, APC_EN = 1 In dual closed-loop mode, the laser bias is controlled by an APC loop, while the modulation is controlled with an extinction ratio loop. The APC setpoint and extinction ratio setpoints are controlled using 8-bit LUTs with up to 2NC temperature resolution and 8-bit offset LUTs. Each loop is initialized using 8-byte LUTs. BIAS, MODULATION, SET_2XAPC, TXCTRL5 LUTs Open Loop Mode, DPC_EN = 0, APC_EN = 0 In open loop mode, the laser bias and modulation are both controlled using LUTs. Each LUT consists of an 8-bit LUT with up to 2NC temperature resolution and an 8-bit offset LUT. This allows the DS1884 to fully support the 10-bit bias DAC and 9-bit modulation DAC inside the MAX3710. LUTs allow temperature indexing the BIAS and MODULATION values and their respective offsets. Depending on the operation mode (see the DS1884 with MAX3710 Operating Modes section), the LUTs function differently, as indicated in Table 7. The LUTs have nonlinear temperature indexing. After every temperature conversion, based on the internal temperature read, a TINDEX value is calculated, which then indexes the LUT. The LUTs can index with a resolution as low as 2NC. APC Loop Mode, DPC_EN = 0, APC_EN = 1 In APC loop or single closed-loop mode, the laser bias is controlled by an APC loop, while the modulation is controlled using a temperature-indexed LUT. The APC setpoint is controlled using an 8-bit LUT with up to 2NC temperature resolution and an 8-bit offset LUT. The APC loop initial value is set by an 8-byte LUT. The modulation LUT consists of an 8-bit LUT with up to 2NC temperature resolution and an 8-bit offset LUT. This allows the This is illustrated in Table 8 , Table 9, Table 10, and Table 11, depending on whether a 4-row (80h-9Fh) or a 5-row (80h-A7h) LUT is indexed. BIAS and MODULATION LUTs are 5-row and TXCTRL5 and APC are 4-row LUTs. Further details can be found in the LUT descriptions. Table 7. DS1884 LUT Functions in Open Loop, APC Loop, and Dual Closed-Loop Modes TABLE REGISTER 80h-9Fh 04h 06h 08h OPEN LOOP -- APC LOOP -- DUAL CLOSED LOOP 8-bit TXCTRL5[7:0] 80h-A7h 8-Bit Modulation Value [7:0] 8-Bit Modulation Value [7:0] -- F0h-F7h IMODMAX[8:1] IMODMAX[8:1] IMODMAX[8:1] F8h-FFh Modulation Offset [9:2] Modulation Offset [9:2] SET_IMOD[8:1] (MOD Initial Value) 80h-9Fh -- 8-Bit APC Value [7:0] 8-Bit APC Value [7:0] 80h-A7h 8-Bit BIAS Value [7:0] -- -- F0h-F7h IBIASMAX[9:2] IBIASMAX[9:2] IBIASMAX[9:2] F8h-FFh BIAS Offset [9:2] SET_IBIAS[9:2] (BIAS Initial Value) SET_IBIAS[9:2] (BIAS Initial Value) F8h-FFh INCBYTE (set to all zeros) INCBYTE 7:4 = BIASINC 3:0 = MODINC (set to all zeros) INCBYTE 7:4 = BIASINC 3:0 = MODINC Maxim Integrated 31 DS1884 SFP and PON ONU Controller with Digital LDD Interface Table 8. DS1884 LUT Memory Map for 4-Row Table (Temperature Values Indicated in C) ROW BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 80h -40 -32 -24 -16 -8 -4 0 BYTE 7 +4 88h +8 +12 +16 +20 +24 +28 +32 +36 90h +40 +44 +48 +52 +56 +60 +64 +68 98h +72 +76 +80 +84 +88 +92 +96 +100 Table 9. DS1884 LUT Memory Map for 4-Row Table (TINDEX Values Indicated in Hex) ROW BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 80h 80 84 88 8C 90 92 94 BYTE 7 96 88h 98 9A 9C 9E A0 A2 A4 A6 90h A8 AA AC AE B0 B2 B4 B6 98h B8 BA BC BE C0 C2 C4 C6 Table 10. DS1884 LUT Memory Map for 5-Row Table (Temperature Values Indicated in C) ROW BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 80h -40 -32 -24 -16 -8 0 +8 BYTE 7 +16 88h +24 +28 +32 +36 +40 +44 +48 +52 90h +56 +58 +60 +62 +64 +66 +68 +70 98h +72 +74 +76 +78 +80 +82 +84 +86 A0h +88 +90 +92 +94 +96 +98 +100 +102 Table 11. DS1884 LUT Memory Map for 5-Row Table (TINDEX Values Indicated in Hex) ROW BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 80h 80 84 88 8C 90 94 98 BYTE 7 9C 88h A0 A2 A4 A6 A8 AA AC AE 90h B0 B1 B2 B3 B4 B5 B6 B7 98h B8 B9 BA BB BC BD BE BF A0h C0 C1 C2 C3 C4 C5 C6 C7 Maxim Integrated 32 DS1884 EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE TEMPCO. 1023 FDh 767 FCh FBh 511 0 -40C LUT BITS 7:0 LUT BITS 7:0 LUT BITS 7:0 255 FAh F9h F8h -8C +8C LUT BITS 7:0 LUT BITS 7:0 LUT BITS 7:0 FFh FEh LUT BITS 7:0 VALUE DETERMINED BY LUTs WITH CORRESPONDING OFFSET LUTs VALUE DETERMINED BY LUTs WITH CORRESPONDING OFFSET LUTs SFP and PON ONU Controller with Digital LDD Interface LUT BITS 7:0 EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE AND NEGATVE TEMPCO. 1023 767 FCh FBh FAh F9h 511 LUT BITS 7:0 F8h LUT BITS 7:0 255 0 +24C +40C +56C +72C +88C +104C -40C LUT BITS 7:0 -8C +8C OFFSET LUTs [8 REGISTERS] LUT BITS 7:0 LUT BITS 7:0 FDh LUT BITS 7:0 FEh LUT BITS 7:0 FFh LUT BITS 7:0 +24C +40C +56C +72C +88C +104C OFFSET LUTs [8 REGISTERS] Figure 15. Offset LUT MOD OFFSET[9:2] 9 8 7 6 5 4 3 DS1884 MODULATION VALUE 2 THE BIAS VALUE THAT IS RECALLED FROM THE LUT AND SENT TO THE MAX3710 IS CALCULATED AS FOLLOWS: MAX3710 SET_IMOD[8:0] BIAS OFFSET[9:2] MOD[7:0] 7 6 9 5 4 3 2 1 8 7 6 5 4 3 2 0 MAX3710 SET_IBIAS[9:0] POW_LEV[1:0] POWER LEVEL (dB) GAIN 00 0 2 01 -3 1 11 -6 0.5 BIAS[7:0] 7 Figure 16. MODULATION LUT (Open Loop and APC Mode) 6 5 4 3 2 1 0 Figure 17. BIAS LUT (Open Loop) Table 12. Temperature Resolution for Offsets ROW BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 F8h -40NC -8NC +8NC +24NC +40NC +56NC +72NC +88NC The offsets are also temperature indexed. Figure 15 illustrates how the offsets would affect the final output as the temperature varies. MODULATION Value Figure 16 shows how to calculate the MODULATION value that is recalled from the LUT and sent to the MAX3710. Table 12 shows the temperature resolution for the offsets. BIAS Value Figure 17 shows how to calculate the BIAS value that is recalled from the LUT and sent to the MAX3710. Maxim Integrated 33 DS1884 SFP and PON ONU Controller with Digital LDD Interface Table 13. Power Leveling Details LOOP OPERATING MODE POWER LEVEL (dB) 0 00 None 1X Open Loop -3 01 Right-shift value written to SET_IMOD once 01 -6 11 Right-shift value written to SET_IMOD twice 00 APC Loop Dual Closed Loop POW_LEV[1:0] KRMD[2:1] (MAX3710) 0 00 None 1X -3 01 Right-shift value written to SET_IMOD once 01 -6 11 Right-shift value written to SET_IMOD twice 00 0 00 None 1X -3 01 None 01 -6 11 None 00 Power Leveling The DS1884 supports power leveling as described in G.984.2. The POW_LEV[1:0] bits in UPDATE A2h Lower Memory, Register 6Fh allow for three power level settings: 0dB, -3dB, and -6dB. Depending on the operation mode, a combination of SET_IMOD and the KRMD bits (MAX3710 TXCTRL3 register) are adjusted to meet these power-level settings. The KRMD bits adjust the gain of the APC loop and extinction ratio loop. Manual MAX3710 Operations The master interface is controllable using four registers in the DS1884: 3WCTRL, ADDRESS, WRITE, READ. Commands can be manually issued while the DS1884 is in normal operation mode. It is also possible to suspend normal 3-wire commands so that only manual operation commands are sent (3WCTRL, A2h Table 04h, Register F8h-FFh). I2C Communication I2C Definition The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. Maxim Integrated MODULATION CHANGE START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 18 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 18 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 18 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (Figure 18). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read (Figure 18). The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. 34 DS1884 SFP and PON ONU Controller with Digital LDD Interface Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not-acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 18). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1884 responds to two slave addresses. The auxiliary memory always responds to a fixed I2C slave address, A0h. The Lower Memory and Tables 00h-08h respond to I2C slave addresses that can be configured to any value between 00h-FEh using the DEVICE ADDRESS byte (A2h Table 02h, Register 8Ch). The user also must set the ASEL bit (A2h Table 02h, Register 89h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates that it would write data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the device assumes the master is communicating with another I2C device and ignores the communications until the next START condition is sent. If the main device's slave address is programmed to be A0h, access to the auxiliary memory is disabled. Memory Address: During an I2C write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. SDA tBUF tF tLOW tHD:STA tSP SCL tHD:STA tHIGH tR tHD:DAT STOP START tSU:STA tSU:STO tSU:DAT REPEATED START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 18. I2C Timing Diagram Maxim Integrated 35 DS1884 SFP and PON ONU Controller with Digital LDD Interface I2C Protocol 2 See Figure 19 for an example of I C timing. counter wrapping around to the beginning of the present row. Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte write operations. For example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The device writes 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus free time or EEPROM write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time a EEPROM page is written, the device requires the EEPROM write time (tW) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address TYPICAL I2C WRITE TRANSACTION MSB START 1 MSB LSB 0 1 0 0 0 SLAVE ADDRESS* 1 R/W SLAVE ACK b7 LSB b6 b5 b4 b3 b2 b1 MSB SLAVE ACK b0 b7 LSB b6 b5 b4 REGISTER ADDRESS READ/ WRITE b3 b2 b1 b0 SLAVE ACK STOP DATA *IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY. IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 89h FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED ADDRESS FOR THE MAIN MEMORY IS A0h. EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS A2h A) SINGLE-BYTE WRITE -WRITE 00h TO REGISTER BAh START 1 0 1 0 0 0 1 0 B) SINGLE-BYTE READ -READ REGISTER BAh START 1 0 1 0 0 0 1 0 A2h C) TWO-BYTE WRITE -WRITE 01h AND 75h TO C8h AND C9h D) TWO-BYTE READ -READ C8h AND C9h BAh 00h SLAVE SLAVE SLAVE ACK 1 0 1 1 1 0 1 0 ACK 0 0 0 0 0 0 0 0 ACK BAh SLAVE SLAVE ACK 1 0 1 1 1 0 1 0 ACK STOP A3h REPEATED START 10100011 DATA SLAVE ACK DATA IN BAh A2h C8h 01h 75h START 1 0 1 0 0 0 1 0 SLAVE 1 1 0 0 1 0 0 0 SLAVE 0 0 0 0 0 0 0 1 SLAVE 0 1 1 1 0 1 0 1 SLAVE ACK ACK ACK ACK A2h C8h START 1 0 1 0 0 0 1 0 SLAVE 1 1 0 0 1 0 0 0 SLAVE ACK ACK REPEATED START A3h 1 0 1 0 0 0 1 1 SLAVE ACK MASTER NACK STOP MASTER ACK DATA IN C9h STOP DATA DATA IN C8h DATA MASTER NACK STOP Figure 19. Example I2C Timing Maxim Integrated 36 DS1884 SFP and PON ONU Controller with Digital LDD Interface because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the device, which allows the next page to be written as soon as the device is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tW to elapse before attempting to write again to the device. EEPROM Write Cycles: When EEPROM writes occur, the device writes the whole EEPROM memory page, even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page 1 byte at a time wears the EEPROM out 8x faster than writing the entire page at once. The device's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It can handle approximately 10x that many writes at room temperature. Writing to SRAM-shadowed EEPROM memory with SEEB = 1 does not count as a EEPROM write cycle when evaluating the EEPROM's estimated lifetime. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address pointer to a particular value. To do this, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Maxim Integrated Memory Organization The following sections provide the device's register definitions (see Figure 20 for the memory map). Each register or row of registers has an access descriptor that determines the password level required to read or write the memory. Level 2 password is intended for the module manufacture access only; level 1 password allows another level of protection for items the end consumer may wish to protect. Many registers are always readable, but require password access to write. There are a few registers that cannot be read without password access. The below access codes describe each mode used by the DS1884 with factory setting for the PW_ENA (A2h Table 02h, Register C0h ) and PW_ENB (A2h Table 02h, Register C1h) values set to factory settings. ACCESS CODE <0> READ ACCESS WRITE ACCESS At least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit separately for permissions. <1> Read all Write PW2 <2> Read all Write not applicable <3> Read all Write all, but the device hardware also writes to these bytes/bits <4> Read PW2 Write PW2 + mode_bit <5> Read all Write all <6> Read not applicable Write all <7> Read PW1 Write PW1 Write PW2 <8> Read PW2 <9> Read not applicable Write PW2 <10> Read PW2 Write not applicable <11> Read all Write PW1 37 DS1884 SFP and PON ONU Controller with Digital LDD Interface I2C ADDRESS A0h I2C ADDRESS A2h 00h 00h LOWER MEMORY NOTE: ALARM ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING MASK BIT IN REGISTERS 89h, TABLE 02h. MAIN DEVICE EEPROM (256 BYTES) AUXILIARY DEVICE PASSWORD ENTRY (PWE) (4 BYTES) TABLE SELECT BYTE 7Fh 80h 80h 80h TABLE 02h NONLOOKUP TABLE CONTROL AND CONFIGURATION REGISTERS TABLE 01h EEPROM (120 BYTES) FFh ALARMENABLE ROW (8 BYTES) FFh 80h 80h TABLE 06h BIAS/APC LUT EEPROM TABLE 09h TABLE 08h 9Fh A7h A7h E7h F7h F8h 80h TABLE 04h MODULATION/ TXCTRL5 LUT EEPROM 9Fh E0h 3W CONFIG FFh F0h MOD MAX LUT MOD OFFSET/ SET_IMOD LUT FFh F8h TABLE 05h FFh F0h BIAS MAX LUT BIAS OFFSET/ SET_IBIAS LUT FFh F8h F8h BIASINC LUT MODINC LUT FFh DAC OFFSET LUT FFh Figure 20. Memory Organization Maxim Integrated 38 DS1884 SFP and PON ONU Controller with Digital LDD Interface Register Descriptions The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/word's address. A total of 8 bytes are present on each row. For more information about each of these bytes, see the corresponding register description. A2h Lower Memory Register Map LOWER MEMORY WORD 0 WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME 00 <1>THRESHOLD 0 08 <1>THRESHOLD 1 VCC ALARM HI VCC ALARM LO VCC WARN HI VCC WARN LO 10 <1>THRESHOLD 2 TXB ALARM HI TXB ALARM LO TXB WARN HI TXB WARN LO 18 <1>THRESHOLD 3 TXP ALARM HI TXP ALARM LO TXP WARN HI TXP WARN LO 20 <1>THRESHOLD 4 RSSI ALARM HI RSSI ALARM LO RSSI WARN HI RSSI WARN LO BYTE 0/8 BYTE 1/9 BYTE 2/A TEMP ALARM HI BYTE 3/B BYTE 4/C TEMP ALARM LO BYTE 5/D BYTE 6/E TEMP WARN HI BYTE 7/F TEMP WARN LO 28-37 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY 38-5F <1>EEPROM EE EE EE EE EE EE EE EE 60 <2>ADC VALUES0 68 <0>ADC VALUES1 70 78 <5>ALARM/WARN <0> TABLE SELECT TEMP VALUE <2>RSSI VALUE VCC VALUE TXB VALUE <2>RESERVED <2>RESERVED ALARM3 ALARM2 RESERVED <5>RESERVED <5>RESERVED <5>RESERVED RESERVED <6>PWE WARN3 <6>PWE MSW TXP VALUE <0>STATUS WARN2 MSW <6>PWE LSW RESERVED <6>PWE LSW <3>UPDATE RESERVED <5>TBL SEL A2h Table 01h Register Map A2h TABLE 01h ROW (HEX) ROW NAME 80-BF C0-F7 F8 WORD 0 WORD 1 WORD 2 WORD 3 BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F <7>EEPROM EE EE EE EE EE EE EE EE <8>EEPROM EE EE EE EE EE EE EE EE ALARM EN3 ALARM EN2 RESERVED RESERVED WARN EN3 WARN EN2 RESERVED RESERVED <8>ALARM ENABLE Note: The ALARM ENABLE bytes (Registers F8h-FFh) can be configured to exist in A2h Table 05h instead of here at A2h Table 01h with the MASK bit (A2h Table 02h, Register 89h). If the row is configured to exist in A2h Table 05, then these locations are EE in A2h Table 01h. The access codes represent the factory default values of PW_ENA (A2h Table 02h, Register C0h) and PW_ENB (A2h Table 02h, Register C1h). ACCESS CODE Read Access Write Access <0> See each bit/byte separately Maxim Integrated <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> All All All PW2 All N/A PW1 PW2 N/A PW2 All PW2 N/A All and device hardware PW2 + mode bit All All PW1 PW2 PW2 N/A PW1 39 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h Register Map A2h TABLE 02h (PW2) ROW (HEX) ROW NAME 80 WORD 0 WORD 1 BYTE 0/8 BYTE 1/9 <0>CONFIG 0 <8>MODE <4>TINDEX 88 <8>CONFIG 1 DACFS CNFGA 90 <8>SCALE 0 XOVER COARSE 98 <8>SCALE 1 A0 <8>OFFSET 0 <8>OFFSET 1 A8 <9>PWD B0 B8 C0 <8>PWD ENABLE C8 <0>MAXROW D0-DF EMPTY E0 <8>3W CONFIG0 WORD 2 BYTE 3/B BYTE 4/C <4>MODULATION VALUE RESERVED CNFGB CNFGC DEVICE ADDRESS WORD 3 BYTE 5/D <4>APC BYTE 6/E CNFGD BYTE 7/F <4>SET_IBIAS VALUE VALUE RSHIFT1 RSHIFT0 VCC SCALE TXB SCALE RSSI FINE SCALE RESERVED RSSI COARSE SCALE RESERVED XOVER FINE VCC OFFSET TXB OFFSET TXP OFFSET RSSI FINE OFFSET RESERVED RSSI COARSE OFFSET INTERNAL TEMP OFFSET* PW1 MSW PW1 LSW PW2 MSW VALUE EMPTY BYTE 2/A TXP SCALE PW2 LSW EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY PW_ENA PW_ENB RESERVED RESERVED RESERVED RESERVED RESERVED TBLSELPON <4>IMODMAX <4>IBIASMAX <4>DAC <4>DAC VALUE VALUE <4>INCBYTE <4>TXCTRL5 DPC <10>DEVICE ID <10>DEVICE VER EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY RXCTRL1 RXCTRL2 SETCML SETLOSH TXCTRL1 TXCTRL2 TXCTRL3 TXCTRL4 SET_LOS E8 <8>3W CONFIG1 TXCTRL5 APC OL TXCTRL6 TXCTRL7 RESERVED SETLOSH_3945 SETLOSL_3945 F0 <0>3W CONFIG2 <8>3WCTRL <8>ADDRESS <8>WRITE <10>READ <10>TXSTAT2 <10>TXSTAT1 <10>DPCSTAT <10>RXSTAT EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY F8 EMPTY TIMER_3945 3WSET *The final result must be XORed with BB40h before writing to this register. **Do not write to this register. The access codes represent the factory default values of PW_ENA (A2h Table 02h, Register C0h) and PW_ENB (A2h Table 02h, Register C1h). ACCESS CODE Read Access Write Access <0> See each bit/byte separately Maxim Integrated <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> All All All PW2 All N/A PW1 PW2 N/A PW2 All PW2 N/A All and device hardware PW2 + mode bit All All PW1 PW2 PW2 N/A PW1 40 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 04h Register Map A2h TABLE 04h (MODULATION OR TXCTRL5 LUT) ROW (HEX) 80-A7 WORD 0 ROW NAME BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 BYTE 3/B <8>MODULATION/ BYTE 4/C WORD 3 BYTE 5/D BYTE 6/E BYTE 7/F SEE TABLE DESCRIPTION TXCTRL5 A8-EF EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY F0 <8>IMODMAX MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT F8 <8>MOD OFFSET/ SEE TABLE DESCRIPTION SET_IMOD LUT A2h Table 05h Register Map A2h TABLE 05h ROW (HEX) ROW NAME 80-F7 EMPTY F8 <8>ALARM WORD 0 ENABLE WORD 1 WORD 2 WORD 3 BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY BYTE 7/F EMPTY ALARM EN3 ALARM EN2 RESERVED RESERVED WARN EN3 WARN EN2 RESERVED RESERVED Note: A2h Table 05h is empty by default. It can be configured to contain the alarm and warning enable bytes from A2h Table 01h, Registers F8h-FFh with the MASK bit enabled (A2h Table 02h, Register 89h). In this case A2h Table 01h will be empty. A2h Table 06h Register Map A2h TABLE 06h (BIAS OR APC LUT) ROW (HEX) 80-A7 WORD 0 ROW NAME <8>BIAS/APC BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A LUT WORD 2 BYTE 3/B BYTE 4/C WORD 3 BYTE 5/D BYTE 6/E BYTE 7/F SEE TABLE DESCRIPTION A8-EF EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY F0 <8>IBIASMAX BIAS MAX LUT BIAS MAX LUT BIAS MAX LUT BIAS MAX LUT BIAS MAX LUT BIAS MAX LUT BIAS MAX LUT BIAS MAX LUT F8 <8>BIAS/SET_IBIAS OFF SEE TABLE DESCRIPTION The access codes represent the factory default values of PW_ENA (A2h Table 02h, Register C0h) and PW_ENB (A2h Table 02h, Register C1h). ACCESS CODE Read Access Write Access <0> See each bit/byte separately Maxim Integrated <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> All All All PW2 All N/A PW1 PW2 N/A PW2 All PW2 N/A All and device hardware PW2 + mode bit All All PW1 PW2 PW2 N/A PW1 41 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 08h Register Map A2h TABLE 08h (INC LUT) ROW (HEX) ROW NAME 80-F7 F8-FF WORD 0 WORD 1 WORD 2 WORD 3 BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY <8>INCROW BIASINC BIASINC BIASINC BIASINC MODINC MODINC MODINC MODINC A2h Table 09h Register Map A2h TABLE 09h (DAC OFFSET LUT) ROW (HEX) ROW NAME 80-F7 F8-FF EMPTY <8>DAC OFFSET WORD 0 BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 BYTE 3/B BYTE 4/C WORD 3 BYTE 5/D BYTE 6/E BYTE 7/F EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY DACOFF DACOFF DACOFF DACOFF DACOFF DACOFF DACOFF DACOFF Auxiliary A0h Memory Register Map AUXILIARY MEMORY (A0h) ROW (HEX) ROW NAME WORD 0 WORD 1 WORD 2 WORD 3 BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F 00-7F <5>AUX EE EE EE EE EE EE EE EE EE 80-FF <5>AUX EE EE EE EE EE EE EE EE EE The access codes represent the factory default values of PW_ENA (A2h Table 02h, Register C0h) and PW_ENB (A2h Table 02h, Register C1h). ACCESS CODE Read Access Write Access <0> See each bit/byte separately Maxim Integrated <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> All All All PW2 All N/A PW1 PW2 N/A PW2 All PW2 N/A All and device hardware PW2 + mode bit All All PW1 PW2 PW2 N/A PW1 42 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory Register Descriptions A2h Lower Memory, Register 00h-01h: TEMP ALARM HI A2h Lower Memory, Register 04h-05h: TEMP WARN HI FACTORY DEFAULT 7FFFh READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) 00h, 04h S 26 25 24 23 22 21 20 01h, 05h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0 Temperature measurement updates above this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit. A2h Lower Memory, Register 02h-03h: TEMP ALARM LO A2h Lower Memory, Register 06h-07h: TEMP WARN LO FACTORY DEFAULT 8000h READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) 02h, 06h S 26 25 24 23 22 21 20 03h, 07h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0 Temperature measurement updates below this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit. Maxim Integrated 43 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 08h-09h: VCC ALARM HI A2h Lower Memory, Register 0Ch-0Dh: VCC WARN HI A2h Lower Memory, Register 10h-11h: TXB ALARM HI A2h Lower Memory, Register 14h-15h: TXB WARN HI A2h Lower Memory, Register 18h-19h: TXP ALARM HI A2h Lower Memory, Register 1Ch-1Dh: TXP WARN HI A2h Lower Memory, Register 20h-21h: RSSI ALARM HI A2h Lower Memory, Register 24h-25h: RSSI WARN HI FACTORY DEFAULT FFFFh READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) 08h, 0Ch, 10h,14h, 18h, 1Ch, 20h, 24h 215 214 213 212 211 210 29 28 09h, 0Dh, 11h, 15h, 19h, 1Dh, 21h, 25h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Maxim Integrated 44 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 0Ah-0Bh: VCC ALARM LO A2h Lower Memory, Register 0Eh-0Fh: VCC WARN LO A2h Lower Memory, Register 12h-13h: TXB ALARM LO A2h Lower Memory, Register 16h-17h: TXB WARN LO A2h Lower Memory, Register 1Ah-1Bh: TXP ALARM LO A2h Lower Memory, Register 1Eh-1Fh: TXP WARN LO A2h Lower Memory, Register 22h-23h: RSSI ALARM LO A2h Lower Memory, Register 26h-27h: RSSI WARN LO FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) 0Ah, 0Eh, 12h, 16h, 1Ah, 1Eh, 22h, 26h 215 214 213 212 211 210 29 28 0Bh, 0Fh, 13h, 17h, 1Bh, 1Fh, 23h, 27h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. Maxim Integrated 45 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 28h-37h: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. A2h Lower Memory, Register 38h-5Fh: EE FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (EE) 38h-5Fh EE EE EE EE EE EE EE BIT 7 EE BIT 0 PW2 level access-controlled EEPROM. A2h Lower Memory, Register 60h-61h: TEMP VALUE FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 60h S 26 25 24 23 22 21 20 61h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0 Signed two's complement direct-to-temperature measurement. Maxim Integrated 46 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 62h-63h: VCC VALUE A2h Lower Memory, Register 64h-65h: TXB VALUE A2h Lower Memory, Register 66h-67h: TXP VALUE A2h Lower Memory, Register 68h-69h: RSSI VALUE POWER-ON VALUE 0000h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 62h, 64h, 66h, 68h 215 214 213 212 211 210 29 28 63h, 65h, 67h, 69h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Left-justified unsigned voltage measurement. A2h Lower Memory, Register 6Ah-6Dh: RESERVED POWER-ON VALUE 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are reserved. Maxim Integrated 47 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 6Eh: STATUS POWER-ON VALUE X0XX 0XXXb READ ACCESS All WRITE ACCESS See below description MEMORY TYPE Volatile Write Access 6Eh N/A All N/A All All N/A N/A N/A TXDS TXDC TXFIS RSELS RESERVED TXFOUTS RXL RDYB BIT 7 Maxim Integrated BIT 0 BIT 7 TXDS: TXD status bit. Reflects the logic state of the TXD pin (read-only). 0 = TXD pin is logic-low. 1 = TXD pin is logic-high. BIT 6 TXDC: TXD software control bit. This bit allows for software control that is identical to the TXD pin. See the section on TXD for further information. Its value is wired-ORed with the logic value of the TXD pin (writable by all users). 0 = (Default) 1 = Forces the device into a TXD state regardless of the value of the TXD pin. BIT 5 TXFIS: Reflects the status of the TXF pin. The status will also include any inversion caused by the INVTXFI bit (read-only). 0 = TXF pin is low (after any inversion caused by the INVTXFI bit). 1 = TXF pin is high (after any inversion caused by the INVTXFI bit). BIT 4 RSELS: RSEL status bit. Reflects the logic state of the RSEL pin (read-only). 0 = RSEL pin is logic-low. 1 = RSEL pin is logic-high. BIT 3 RESERVED BIT 2 TXFOUTS: TXFOUT status. Indicates the state the open drain output is attempting to achieve. 0 = TXFOUT is pulling low. 1 = TXFOUT is high impedance. BIT 1 RXL: Reflects the driven state of the LOS pin (read-only). 0 = LOS pin is driven low. 1 = LOS pin is pulled high. BIT 0 RDYB: Ready bar. 0 = VCC is above POA. 1 = VCC is below POA and/or too low to communicate over the I2C bus. 48 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 6Fh: UPDATE 6Fh POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS All and DS1884 Hardware MEMORY TYPE Volatile TEMP RDY VCC RDY TXB RDY TXP RDY RSSI RDY RSSIR POW_LEV1 BIT 7 BITS 7:3 BIT 2 BITS 1:0 Maxim Integrated POW_LEV0 BIT 0 Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified. RSSIR: RSSI range. Reports the range used for conversion update of RSSI. 0 = Fine range is the reported value. 1 = Coarse range is the reported value. POW_LEV[1:0]: Power level. This changes the MAX3710 bits KRMD[2:1] to adjust the MD input impedance. See the Power Leveling section for more details. 49 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 70h: ALARM3 70h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO TXB HI TXB LO BIT 7 TXP HI TXP LO BIT 0 BIT 7 TEMP HI: High alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 TEMP LO: Low Alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. BIT 5 VCC HI: High alarm status for VCC measurement. 0 = (Default) Last measurement was equal to or below threshold setting 1 = Last measurement was above threshold setting. BIT 4 VCC LO: Low alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (Default) Last measurement was below threshold setting. BIT 3 TXB HI: High alarm status for TXB measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 2 TXB LO: Low alarm status for TXB measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. BIT 1 TXP HI: High alarm status for TXP measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 0 TXP LO: Low alarm status for TXP measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. Maxim Integrated 50 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 71h: ALARM2 71h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile RSSI HI RSSI LO RESERVED RESERVED RESERVED IN1S RESERVED BIT 7 BIT 0 BIT 7 RSSI HI: High alarm status for RSSI measurement. A TXD event does not clear this alarm. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 RSSI LO: Low alarm status for RSSI measurement. A TXD event does not clear this alarm. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. BITS 5:3 TXFINT RESERVED BIT 2 IN1S: IN1 status bit. Reflects the logic state of the IN1 pin (read-only). 0 = IN1 pin is logic-low. 1 = IN1 pin is logic-high. BIT 1 RESERVED BIT 0 TXFINT: TXFOUT interrupt. This bit is the wired-ORed logic of all alarms and warnings wired-ANDed with their corresponding enable bits. The enable bits are found in A2h Table 01h/05h, Registers F8-FFh. A2h Lower Memory, Register 72h-73h: RESERVED POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE These registers are reserved. Maxim Integrated 51 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 74h: WARN3 74h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO TXB HI TXB LO BIT 7 TXP HI TXP LO BIT 0 BIT 7 TEMP HI: High warning status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 TEMP LO: Low warning status for temperature measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. BIT 5 VCC HI: High warning status for VCC measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 4 VCC LO: Low warning status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (Default) Last measurement was below threshold setting. BIT 3 TXB HI: High warning status for TXB measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 2 TXB LO: Low warning status for TXB measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. BIT 1 TXP HI: High warning status for TXP measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 0 TXP LO: Low warning status for TXP measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. Maxim Integrated 52 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 75h: WARN2 75h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile RSSI HI RSSI LO RESERVED RESERVED RESERVED RESERVED BIT 7 RESERVED BIT 0 BIT 7 RSSI HI: High warning status for RSSI measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 RSSI LO: Low warning status for RSSI measurement. 0 = (Default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. BITS 5:0 RESERVED RESERVED A2h Lower Memory, Register 76h-7Ah: RESERVED POWER-ON VALUE 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are reserved. Maxim Integrated 53 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 7Bh-7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE FFFF FFFFh READ ACCESS N/A WRITE ACCESS ALL MEMORY TYPE Volatile 7Bh 231 230 229 228 227 226 225 224 7Ch 223 222 221 220 219 218 217 216 7Dh 215 214 213 212 211 210 29 28 7Eh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 There are two passwords for the DS1884. Each password is 4 bytes long. The lower level password (PW1) will have all the access of a normal user plus those made available with PW1. The higher level password (PW2) will have all of the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside of PW2 memory. At power up, all PWE bits are set to 1. All reads at this location are 0. A2h Lower Memory, Register 7Fh: TBL SEL 7Fh POWER-ON VALUE TBLSELPON (A2h Table 02h, Register C7h). READ ACCESS All WRITE ACCESS All MEMORY TYPE Volatile 27 BIT 7 26 25 24 23 22 21 20 BIT 0 The upper memory tables of the DS1884 are accessible by writing the desired table value in this register. The power-on value of this register is defined by the value written to TBLSELPON (A2h Table 02, Register C7h). Maxim Integrated 54 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h Register Descriptions A2h Table 05h can be configured to contain the alarm and warning enable bytes from A2h Table 01h, Registers F8h- FFh with the MASK bit enabled (A2h Table 02h, Register 89h). In this case the corresponding bytes in A2h Table 01h are empty. A2h Table 01h, Register 80h-BFh: EEPROM POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) WRITE ACCESS PW2 or (PW1 and RWTBL1A) MEMORY TYPE Nonvolatile (EE) 80h-BFh EE EE EE EE EE EE EE BIT 7 EE BIT 0 EEPROM for PW1 and/or PW2 level access. A2h Table 01h, Register C0h-F7h: EEPROM POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1B) or (PW1 and RTBL1B) WRITE ACCESS PW2 or (PW1 and RWTBL1B) MEMORY TYPE Nonvolatile (EE) C0h-F7h EE EE EE BIT 7 EE EE EE EE EE BIT 0 EEPROM for PW1 and/or PW2 level access. Maxim Integrated 55 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register F8h: ALARM EN3 OR EE POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) F8h TEMP HI TEMP LO VCC HI VCC LO BIT 7 TXB HI TXB LO TXP HI TXP LO BIT 0 Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether this memory exists in A2h Table 01h or 05h. When in A2h Table 05h, this location at A2h Table 01h becomes EE. Maxim Integrated BIT 7 TEMP HI: 0 = Disables interrupt from TEMP HI alarm. 1 = Enables interrupt from TEMP HI alarm. BIT 6 TEMP LO: 0 = Disables interrupt from TEMP LO alarm. 1 = Enables interrupt from TEMP LO alarm. BIT 5 VCC HI: 0 = Disables interrupt from VCC HI alarm. 1 = Enables interrupt from VCC HI alarm. BIT 4 VCC LO: 0 = Disables interrupt from VCC LO alarm. 1 = Enables interrupt from VCC LO alarm. BIT 3 TXB HI: 0 = Disables interrupt from TXB HI alarm. 1 = Enables interrupt from TXB HI alarm. BIT 2 TXB LO: 0 = Disables interrupt from TXB LO alarm. 1 = Enables interrupt from TXB LO alarm. BIT 1 TXP HI: 0 = Disables interrupt from TXP HI alarm. 1 = Enables interrupt from TXP HI alarm. BIT 0 TXP LO: 0 = Disables interrupt from TXP LO alarm. 1 = Enables interrupt from TXP LO alarm. 56 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register F9h: ALARM EN2 OR EE F9h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) RSSI HI RSSI LO RESERVED RESERVED RESERVED RESERVED RESERVED BIT 7 RESERVED BIT 0 Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether this memory exists in A2h Table 01h or 05h. When in A2h Table 05h, this location at A2h Table 01h becomes EE. BIT 7 RSSI HI: 0 = Disables interrupt from RSSI HI alarm. 1 = Enables interrupt from RSSI HI alarm. BIT 6 RSSI LO: 0 = Disables interrupt from RSSI LO alarm. 1 = Enables interrupt from RSSI LO alarm. BITS 5:0 RESERVED A2h Table 01h, Register FAh-FBh: RESERVED OR EE POWER-ON VALUE 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. When in A2h Table 05h, this location at A2h Table 01h becomes EE. Maxim Integrated 57 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register FCh: WARN EN3 OR EE POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) FCh TEMP HI TEMP LO VCC HI VCC LO TXB HI BIT 7 TXB LO TXP HI TXP LO BIT 0 Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether this memory exists in A2h Table 01h or 05h. When in A2h Table 05h, this location at A2h Table 01h becomes EE. Maxim Integrated BIT 7 TEMP HI: 0 = Disables interrupt from TEMP HI warning. 1 = Enables interrupt from TEMP HI warning. BIT 6 TEMP LO: 0 = Disables interrupt from TEMP LO warning. 1 = Enables interrupt from TEMP LO warning. BIT 5 VCC HI: 0 = Disables interrupt from VCC HI warning. 1 = Enables interrupt from VCC HI warning. BIT 4 VCC LO: 0 = Disables interrupt from VCC LO warning. 1 = Enables interrupt from VCC LO warning. BIT 3 TXB HI: 0 = Disables interrupt from TXB HI warning. 1 = Enables interrupt from TXB HI warning. BIT 2 TXB LO: 0 = Disables interrupt from TXB LO warning. 1 = Enables interrupt from TXB LO warning. BIT 1 TXP HI: 0 = Disables interrupt from TXP HI warning. 1 = Enables interrupt from TXP HI warning. BIT 0 TXP LO: 0 = Disables interrupt from TXP LO warning. 1 = Enables interrupt from TXP LO warning. 58 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register FDh: WARN EN2 OR EE FDh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) RSSI HI RSSI LO RESERVED RESERVED BIT 7 RESERVED RESERVED RESERVED RESERVED BIT 0 Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (A2h Table 02h, Register 89h) determines whether this memory exists in A2h Table 01h or 05h. When in A2h Table 05h, this location at A2h Table 01h becomes EE. BIT 7 RSSI HI: 0 = Disables interrupt from RSSI HI warning. 1 = Enables interrupt from RSSI HI warning. BIT 6 RSSI LO: 0 = Disables interrupt from RSSI LO warning. 1 = Enables interrupt from RSSI LO warning. BITS 5:0 RESERVED A2h Table 01h, Register FEh-FFh: RESERVED OR EE POWER-ON VALUE 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. Maxim Integrated 59 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h Register Descriptions A2h Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB 3Fh PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Volatile INCROW LUT EN TXCTRL5 LUT EN BIAS LUT EN AEN MOD LUT EN BIT 7 APC LUT EN DAC LUT EN BIT 0 BIT 7 SEEB: 0 = (Default) Enables EEPROM writes to SEE bytes. 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE locations again for data to be written to the EEPROM. BIT 6 INCROW LUT EN: 0 = INCROW register is controlled by the user. The INCROW register value is written with the use of the 3-wire interface. This allows users to interactively test their modules by writing the INCROW register value. In APC loop mode, only BIASINC[3:0] is updated. In DPC loop mode, both BIASINC[3:0] and MODINC[3:0] are updated. 1 = (Default) Enables auto control for the INCROW register. BIT 5 TXCTRL5 LUT EN: 0 = TXCTRL5 DPC register is writable by the user and the LUT recalls are disabled. 1 = (Default) Enables auto control of the LUT for TXCTRL5. BIT 4 BIAS LUT EN: 0 = SET_IBIAS and IBIASMAX registers are controlled by the user. The SET_IBIAS and IBIASMAX value is written with the use of the 3-wire interface. This allows the user to interactively test their modules by directly controlling the SET_IBIAS and IBIASMAX. 1 = (Default) Enables LUT control of the SET_IBIAS and IBIASMAX. BIT 3 AEN: 0 = The temperature-calculated index value TINDEX is writable by the user and the updates of calculated indexes are disabled. This allows users to interactively test their modules by controlling the indexing for the look up tables. The recalled values from the LUTs appear in the DAC registers after the next completion of a temperature conversion. 1 = (Default) The internal temperature sensor determines the value of TINDEX BIT 2 MOD LUT EN: 0 = MODULATION VALUE and IMODMAX registers are controlled by the user. The MODULATION VALUE and IMODMAX values are written with the use of the 3-wire interface. This allows users to interactively test their modules by directly controlling the MODULATION VALUE and IMODMAX. 1 = (Default) Enables LUT control of MODULATION VALUE and IMODMAX. BIT 1 APC LUT EN: 0 = APC VALUE register is controlled by the user. The APC VALUE value is written with the use of the 3-wire interface. This allows users to interactively test their modules by directly controlling the APC VALUE register. 1 = (Default) Enables LUT control of APC VALUE. BIT 0 DAC LUT EN: 0 = DAC VALUE is writable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the values for DAC. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (Default) Enables auto control of the LUT for DAC VALUE. Maxim Integrated 60 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 81h: Temperature Index (TINDEX) 81h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL246 and AEN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h, 06h, and 08h. Temperature measurements below -40NC or above +102NC are clamped to 80h and C7h, respectively. The calculation of TINDEX is as follows: = TINDEX Temp_Value + 40C + 80h 2C For the temperature-indexed LUTs, the index used during the lookup function for each table is as follows: A2h Table 04h (MOD) 1 TINDEX6 TINDEX5 TINDEX4 TINDEX3 TINDEX2 TINDEX1 TINDEX0 A2h Table 06h (APC) 1 0 TINDEX6 TINDEX5 TINDEX4 TINDEX3 TINDEX2 TINDEX1 A2h Table 02h, Register 82h-83h: MODULATION VALUE FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and MOD LUT EN = 0) or (PW1 and RWTBL246 and MOD LUT EN = 0) MEMORY TYPE Volatile 82h 0 0 0 0 0 0 0 28 83h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The digital value used for MOD and recalled from A2h Table 04h at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. A2h Table 02h, Register 84h: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) This register is reserved. Maxim Integrated 61 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 85h: APC VALUE 85h FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and APC LUT EN = 0) or (PW1 and RWTBL246 and APC LUT EN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The digital value used for APC and recalled from A2h Table 06h in the APC and dual-closed-loop mode at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. A2h Table 02h, Register 86h-87h: SET_IBIAS VALUE FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and APC LUT EN = 0) or (PW1 and RWTBL246 and APC LUT EN = 0) MEMORY TYPE Volatile 86h 0 0 0 0 0 0 29 28 87h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The digital value used for BIAS and recalled from A2h Table 06h in the open-loop mode at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. A2h Table 02h, Register 88h: DACFS 88h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 29 BIT 7 28 27 26 25 24 23 22 BIT 0 DACFS sets the slope of the DAC's temperature compensation. In conjunction with DAC OFFSET and TINDEX, this allows the DAC to create an output that is linearly dependent on temperature. For further details see the DeltaSigma Output and Reference section. Maxim Integrated 62 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 89h: CNFGA 89h FACTORY DEFAULT 80h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED INV LOS ASEL MASK RESERVED BIT 7 BITS 7:6 INVTXFI BIT 0 RESERVED BIT 5 INV LOS: Inverts the buffered input pin LOS to output pin LOSOUT. 0 = Noninverted LOS to LOSOUT pin. 1 = Inverted LOS to LOSOUT pin. BIT 4 ASEL: Address select. 0 = Device address is A2h. 1 = DEVICE ADDRESS byte in A2h Table 02h, Register 8Ch is used as the device address. BIT 3 MASK: 0 = Alarm enable row exists at A2h Table 01h, Registers F8h-FFh. A2h Table 05h, Registers F8h- FFh are empty. 1 = Alarm enable row exists at A2h Table 05h, Registers F8h-FFh. A2h Table 01h, Registers F8h- FFh are empty. BITS 2:1 BIT 0 Maxim Integrated RESERVED RESERVED INVTXFI: Allow for inversion of signal driven by TXF input pin. 0 = (Default) TXF signal is not inverted. 1 = TXF signal is inverted. 63 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Ah: CNFGB FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 8Ah IN1S RESERVED RESERVED RESERVED RESERVED ALATCH RESERVED BIT 7 BIT 7 BITS 6:3 Maxim Integrated WLATCH BIT 0 INS1: Status of input pin IN1. RESERVED BIT 2 ALATCH: ADC alarm's comparison LATCH. A2h Table 01h, Registers 70h-71h. 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set. BIT 1 RESERVED BIT 0 WLATCH: ADC warning's comparison LATCH. A2h Table 01h, Registers 74h-75h. 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set. 64 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Bh: CNFGC 8Bh FACTORY DEFAULT 04h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) XOVEREN RESERVED TXDM3 RESERVED TXDFLT TXDIO RSSI_FC BIT 7 BIT 0 BIT 7 XOVEREN: Enables RSSI conversion to use the XOVER (A2h Table 02h, Register 90h-91h) value during RSSI conversions. 0 = Uses hysteresis for linear RSSI measurements. 1 = XOVER value is enabled for nonlinear RSSI measurements. BIT 6 RESERVED BIT 5 TXDM3: Enables TXD to reset alarms and warnings associated to RSSI during a TXD event. 0 = TXD event has no affect on the RSSI alarms and warnings. 1 = RSSI alarms and warnings are reset during a TXD event. BIT 4 RESERVED BIT 3 TXDFLT: See Figure 10. 0 = TXF pin has no affect on TXDOUT. 1 = TXF pin is enabled and ORed with other possible signals to create TXDOUT. BIT 2 TXDIO: See Figure 10. 0 = TXD input signal is enabled and ORed with other possible signals to create TXDOUT. 1 = (Default) TXD input signal has no affect on TXDOUT. BITS 1:0 Maxim Integrated RSSI_FF RSSI_FC and RSSI_FF: RSSI force coarse and RSSI force fine. Control bits for RSSI mode of operation on the RSSI conversion. 00b = (Default) Normal RSSI mode of operation. 01b = The fine settings of scale and offset are used for RSSI conversions. 10b = The coarse settings of scale and offset are used for RSSI conversions. 11b = Normal RSSI mode of operation. 65 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Ch: DEVICE ADDRESS FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 8Ch 26 25 24 23 22 21 BIT 7 20 BIT 0 This value becomes the I2C slave address for the main memory when ASEL (A2h Table 02h, Register 89h) bit is set. If A0h is programmed to this register, the AUXILIARY MEMORY is disabled. A2h Table 02h, Register 8Dh: CNFGD 8Dh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) INV_DAC RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BIT 7 BIT 7 BITS 6:0 RESERVED BIT 0 INV_DAC: 0 = DAC output is inverted. 1 = DAC output is not inverted. RESERVED A2h Table 02h, Register 8Eh: RIGHT-SHIFT1 (RSHIFT1) 8Eh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED BIT 7 TXB2 TXB1 TXB0 RESERVED TXP2 TXP1 TXP0 BIT 0 Allows for right-shifting the final answer of TXB and TXP voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. Maxim Integrated 66 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Fh: RIGHT-SHIFT0 (RSHIFT0) 8Fh FACTORY DEFAULT 30h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RSSIF2 RSSIF1 RSSIF0 RESERVED RSSIC2 RSSIC1 BIT 7 RSSIC0 BIT 0 Allows for right-shifting the final answer of RSSI fine and coarse voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. A2h Table 02h, Register 90h-91h: XOVER COARSE FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) MEMORY TYPE Nonvolatile (SEE) 90h 91h 215 214 213 212 211 210 29 27 26 25 24 23 22 21 BIT 7 28 0 BIT 0 Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to a 1 (A2h Table 02h, Register 8Bh). RSSI coarse conversion results (before right-shifting) less than this register are clamped to the value of this register. Maxim Integrated 67 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 92h-93h: VCC SCALE A2h Table 02h, Register 94h-95h: TXB SCALE A2h Table 02h, Register 96h-97h: TXP SCALE A2h Table 02h, Register 98h-99h: RSSI FINE SCALE A2h Table 02h, Register 9Ah-9Bh: RESERVED A2h Table 02h, Register 9Ch-9Dh: RSSI COARSE SCALE FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 92h, 94h, 96h, 98h, 9Ch 215 214 213 212 211 210 29 28 93h, 95h, 97h, 99h, 9Dh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Controls the scaling or gain of the full-scale voltage measurements. The factory-calibrated value produces a fullscale voltage of 6.5536V for VCC; 2.5V for TXB, TXP, and MON4; and 0.3125V for RSSI fine. A2h Table 02h, Register 9Eh-9Fh: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. Maxim Integrated 68 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register A0h-A1h: XOVER FINE FACTORY DEFAULT FFFFh READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) MEMORY TYPE Nonvolatile (SEE) A0h 215 214 213 212 211 210 29 28 A1h 27 26 25 24 23 22 21 0 BIT 7 BIT 0 Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to 1 (A2h Table 02h, Register 8Bh). RSSI fine conversion results (before right-shifting) greater than this register require a RSSI coarse conversion. A2h Table 02h, Register A2h-A3h: VCC OFFSET A2h Table 02h, Register A4h-A5h: TXB OFFSET A2h Table 02h, Register A6h-A7h: TXP OFFSET A2h Table 02h, Register A8h-A9h: RSSI FINE OFFSET A2h Table 02h, Register AAh-ABh: RESERVED A2h Table 02h, Register ACh-ADh: RSSI COARSE OFFSET FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) A2h, A4h, A6h, A8h, ACh S 215 214 213 212 211 210 29 A3h, A5h, A7h, A9h, ADh 28 27 26 25 24 23 22 21 BIT 7 BIT 0 Allows for offset control of these voltage measurements if desired. This number is two's complement. Maxim Integrated 69 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register AEh-AFh: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) AEh S 28 27 26 25 24 23 22 AFh 21 20 2-1 2-2 2-3 2-4 2-5 2-6 BIT 7 BIT 0 Allows for offset control of temp measurement if desired. The final result must be XORed with BB40h before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius. A2h Table 02h, Register B0h-B3h: PW1 FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 or (PW1 and WPW1) MEMORY TYPE Nonvolatile (SEE) B0h 231 230 229 228 227 226 225 224 B1h 223 222 221 220 219 218 217 216 B2h 215 214 213 212 211 210 29 28 B3h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing the password entry. All reads of this register are 00h. Maxim Integrated 70 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register B4h-B7h: PW2 FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) B4h 231 230 229 228 227 226 225 224 B5h 223 222 221 220 219 218 217 216 B6h 215 214 213 212 211 210 29 28 B7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without writing the password entry. All reads of this register are 00h. A2h Table 02h, Register B8h-BFh: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. Maxim Integrated 71 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register C0h: PW_ENA C0h FACTORY DEFAULT 10h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL89 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WA2 LOWER WAUXA BIT 7 Maxim Integrated WAUXB BIT 0 BIT 7 RWTBL89: Tables 08h-09h. 0 = (Default) read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 6 RWTBL1C: A2h Table 01h or 05h bytes F8-FFh. Table address is dependent on MASK bit (A2h Table 02h, Register 89h). 0 = (Default) read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 5 RWTBL2: Table 02h except for PW1 value locations (A2h Table 02h, Registers B0h-B3h). 0 = (Default) read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 4 RWTBL1A: Read and write A2h Table 01h, Registers 80h-BFh. 0 = Read and write access for PW2 only. 1 = (Default) read and write access for both PW1 and PW2. BIT 3 RWTBL1B: Read and write A2h Table 01h, Registers C0h-F7h. 0 = (Default) read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 2 WA2 LOWER: Write lower memory bytes 00h-5Fh in main memory. All users can read this area. 0 = (Default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. BIT 1 WAUXA: Write auxiliary memory, Registers 00h-7Fh. All users can read this area (see also A2h Table 02h, Register C1h, PW_ENB). 0 = (Default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. BIT 0 WAUXB: Write auxiliary memory, Registers 80h-FFh. All users can read this area (see also A2h Table 02h, Register C1h, PW_ENB). 0 = (Default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. 72 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register C1h: PW_ENB C1h FACTORY DEFAULT 03h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B BIT 7 Maxim Integrated WPW1 WAUXAU WAUXBU BIT 0 BIT 7 RWTBL46: Read and write Tables 04h and 06h. 0 = (Default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 6 RTBL1C: Read A2h Table 01h or A2h Table 05h, Registers F8h-FFh. Table address is dependent on the MASK bit (A2h Table 02h, Register 89h). 0 = (Default) Read access for PW2 only. 1 = Read access for both PW1 and PW2. BIT 5 RTBL2: Read A2h Table 02h except for PW1 value locations (A2h Table 02h, Registers B0h-B3h). 0 = (Default) Read access for PW2 only. 1 = Read access for both PW1 and PW2. BIT 4 RTBL1A: Read A2h Table 01h, Registers 80h-BFh. 0 = (Default) read access for PW2 only. 1 = Read access for both PW1 and PW2. BIT 3 RTBL1B: Read A2h Table 01h, Registers C0h-F7h. 0 = (Default) read access for PW2 only. 1 = Read access for both PW1 and PW2. BIT 2 WPW1: Write register PW1 (A2h Table 02h, Registers B0h-B3h). For security purposes these registers are not readable. 0 = (Default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. BIT 1 WAUXAU: Write auxiliary memory, Registers 00h-7Fh. All users can read this area (see also A2h Table 02h, Register C0h, PW_ENA). 0 = Write access for PW2 only. 1 = (Default) Write access for user, PW1, and PW2. BIT 0 WAUXBU: Write auxiliary memory, Registers 80h-FFh. All users can read this area (see also A2h Table 02h, Register C0h, PW_ENA) 0 = Write access for PW2 only. 1 = (Default) Write access for user, PW1, and PW2. 73 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register C2h-C6h: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. A2h Table 02h, Register C7h: TBLSELPON C7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Chooses the initial value for the TBL SEL byte (Lower Memory, Register 7Fh) at power-on. A2h Table 02h, Register C8h-C9h: DAC VALUE FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and BIAS LUT EN = 0) or (PW1 and RWTBL246 and BIAS LUT EN = 0) MEMORY TYPE Volatile C8h 0 0 0 0 0 0 29 28 C9h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Value written to DAC when DAC_EN = 0, or recalled from DAC LUT. Maxim Integrated 74 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register CAh: INCBYTE CAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and BIAS LUT EN = 0) or (PW1 and RWTBL246 and BIAS LUT EN = 0) MEMORY TYPE Volatile 23 22 21 20 23 22 21 BIT 7 20 BIT 0 7:4: Value written to MAX3710 BIASINC[3:0] from LUT. This must be set to 0 in open-loop mode. 3:0: Value written to MAX3710 MODINC[3:0] from LUT. This must be set to 0 in open-loop mode and APC mode. A2h Table 02h, Register CBh: TXCTRL5 DPC CBh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and APC LUT EN = 0) or (PW1 and RWTBL246 and APC LUT EN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Value written to MAX3710 TXCTRL5 from the TXCTRL5 LUT. The TXCTRL5 LUT is only active during the dual closed loop mode. For open loop and APC loop mode, see Register E8h. A2h Table 02h, Register CCh: IMODMAX CCh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile 28 27 26 25 BIT 7 24 23 22 21 BIT 0 Value written to MAX3710 IMODMAX from the MOD MAX LUT. Maxim Integrated 75 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register CDh: IBIASMAX CDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile 29 28 27 26 25 24 23 BIT 7 22 BIT 0 Value written to MAX3710 IBIASMAX from the BIAS MAX LUT. A2h Table 02h, Register CEh: DEVICE ID CEh FACTORY DEFAULT 84h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE ROM 1 0 0 0 0 1 BIT 7 0 0 BIT 0 Hardwired connections to show the device ID. A2h Table 02h, Register CFh: DEVICE VER FACTORY DEFAULT DEVICE VERSION READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE ROM CFh DEVICE VERSION BIT 7 BIT 0 Hardwired connections to show the device version. Maxim Integrated 76 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register D0h-DFh: EMPTY FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE None These registers do not exist. A2h Table 02h, Register E0h: RXCTRL1 E0h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E1h: RXCTRL2 E1h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated 77 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register E2h: SETCML E2h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E3h: SETLOSH E3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. Only written if SETLOSCTL is 1. If SETLOSCTL is 0, then SETLOSL register is used. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E4h: TXCTRL1 E4h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated 78 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register E5h: TXCTRL2 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 E5h 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register E6h: TXCTRL3 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 E6h 26 25 24 23 RESERVED RESERVED BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. For bits 2:1, see the POW_LEV[1:0] bits in A2h Lower Memory, Register 6Fh. A2h Table 02h, Register E7h: TXCTRL4 E7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated 79 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register E8h: TXCTRL5 APC OL E8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. This register is active only during the open loop and APC loop modes. See Register CBh for TXCTRL5 access during the dual closed-loop mode. A2h Table 02h, Register E9h: TXCTRL6 E9h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register EAh: TXCTRL7 EAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated 80 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register EBh: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) This register is reserved. A2h Table 02h, Register ECh: SETLOSH_3945 ECh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A2h Table 02h, Register EDh: SETLOSL_3945 EDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 A 3-wire slave register. Only written if SETLOSCTL is 0. If SETLOSCTL is 1, then the SETLOSH register is used. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. Maxim Integrated 81 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register EEh: SETLOSTIMER_3945 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 EEh 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. After either VCC exceeds POA (after a POR event), a Maxim laser driver TX_POR bit is set high (visible in 3-wire TXSTAT1 bit 7), or on a rising edge of TXD, this value is written to a Maxim laser driver through the 3-wire interface. A2h Table 02h, Register EFh: 3WSET EFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) TEMP_UPD RSTRT_3710 EN_3945 RESERVED RESERVED RESERVED RESERVED BIT 7 BIT 0 BIT 7 TEMP_UPD: 0 = Default 3-wire operation. 1 = All the control registers (from Register 0Eh-E8h and Register EAh) are written every temperature conversion. BIT 6 EN_3945: 0 = Bytes associated with the MAX3945 are not sent on the 3-wire bus. 1 = Bytes associated with the MAX3945 are transmitted on the 3-wire bus on power-up (after VCC crosses the VCC LO alarm). BIT 5 RSTRT_3710: 0 = TXCTRL6 is not sent to the MAX3710 except for the initial power-up. 1 = At falling edge of TXD, Register E9h (TXCTRL6) is written to MAX3710. BITS 4:0 Maxim Integrated RESERVED RESERVED 82 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register F0h: 3WCTRL F0h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile RESERVED RESERVED RESERVED RESERVED RESERVED 3WMAN_3945 BIT 7 BITS 7:3 3WRW 3WDIS BIT 0 RESERVED BIT 2 3WMAN_3945: When this bit is set when 3WRW is set, only the MAX3945 is written using CSELOUT2. BIT 1 3WRW: Initiates a 3-wire read or write operation. The write command uses the memory address found in the 3-wire ADDRESS register (A2h Table 02h, Register F1h) and the data from the 3-wire WRITE register (A2h Table 02h, Register F2h). The read command uses the memory address found in the 3-wire ADDRESS register (A2h Table 02h, Register F1h). The address determines whether a read or write operation is to be performed. This bit clears itself at the completion of the operation. 0 = (Default) Reads back as 0 when the read or write operation is completed. 1 = Initiates a 3-wire read or write operation. BIT 0 3WDIS: Disables all automatic communication across the 3-wire interface. This includes all updates from the LUTs, the APC loop, and status registers updates. The only 3-wire communication is with the manual mode of operation. 0 = (Default) Automatic communication is enabled. 1 = Disables automatic communication. A2h Table 02h, Register F1h: ADDRESS F1h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 This byte is used during manual 3-wire communication. When a manual read or write is initiated, this register contains the address for the operation. Maxim Integrated 83 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register F2h: WRITE F2h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 This byte is used during manual 3-wire communication. When a manual write is initiated, this register contains the address for the operation. A2h Table 02h, Register F3h: READ F3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 This byte is used during maunual 3-wire communication. When a manual read is initiated, the return data is stored in this register. A2h Table 02h, Register F4h: TXSTAT2 F4h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) 27 BIT 7 26 25 24 23 22 21 20 BIT 0 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every tRR (see the Analog Voltage Monitoring Characteristics table). Maxim Integrated 84 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register F5h: TXSTAT1 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) 27 F5h 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every tRR (see the Analog Voltage Monitoring Characteristics table). A2h Table 02h, Register F6h: DPCSTAT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) 27 F6h 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every tRR (see the Analog Voltage Monitoring Characteristics table). A2h Table 02h, Register F7h: RXSTAT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) 27 F7h 26 25 BIT 7 24 23 22 21 20 BIT 0 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every tRR (see the Analog Voltage Monitoring Characteristics table). A2h Table 02h, Register F8h-FFh: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved. Maxim Integrated 85 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 04h Register Descriptions A2h Table 04h, Register 80h-A7h or 80h-9Fh: MODULATION or TXCTRL5 LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) Open Loop and APC Loop (Modulation) 26 80h-A7h 25 24 23 22 21 20 2-1 25 24 23 22 21 20 Dual Closed Loop (TXCTRL5) 27 80h-9Fh 26 BIT 7 BIT 0 The digital value for the modulation DAC output or TXCTRL5 register in MAX3710. The MODULATION LUT is a set of registers assigned to hold the temperature profile for the MODULATION register. The temperature measurement is used to index the LUT (TINDEX, A2h Table 02h, Register 81h) in 2NC increments from -40NC to +102NC, starting at 80h. Values recalled from this EEPROM memory table are written into the MODULATION VALUE register (A2h Table 02h, Register 82h-83h) location, which holds the value until the next temperature conversion. The part can be placed into a manual mode (MOD LUT EN bit, A2h Table 02h, Register 80h), where MODULATION register is directly controlled for calibration. If the temperature compensation functionality is not required, then program the entire table to the desired modulation setting. The MODTC bit determines whether the 8-bit LUT values are loaded into the upper 8 bits or lower 8 bits of the 9-bit MOD DAC. See the BIAS, MODULATION, SET_2XAPC, TXCTRL5 LUTs section for more details. A2h Table 04h, Register A8h-EFh: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. A2h Table 04h, Register F0h-F7h: MOD MAX LUT F0h-F7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) 28 BIT 7 Maxim Integrated 27 26 25 24 23 22 21 BIT 0 86 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 04h, Register F8h-FFh: MOD OFFSET or SET_IMOD LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) Open Loop and APC Loop F8h-FFh 28 27 26 25 24 23 22 21 27 26 25 24 23 22 Dual Closed Loop (SET_IMOD) F8h-FFh 29 28 BIT 7 BIT 0 A2h Table 06h Register Descriptions A2h Table 06h, Register 80h-A7h: BIAS or APC LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) Open Loop 80h-A7h 27 26 25 24 23 22 21 20 25 24 23 22 21 20 APC and Dual Closed Loop 80h-A7h 27 BIT 7 26 BIT 0 The APC LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC. The temperature measurement is used to index the LUT (TINDEX, A2h Table 02h, Register 81h) in 4NC increments from -40NC to +100NC, starting at Register 80h. Values recalled from this EEPROM memory table are written into the APC DAC (A2h Table 02h, Register CDh) location, which holds the value until the next temperature conversion. The part can be placed into a manual mode (APC LUT EN bit, A2h Table 02h, Register 80h), where APC DAC can be directly controlled for calibration. If TE temperature compensation is not required by the application, program the entire LUT to the desired APC set point. Maxim Integrated 87 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 06h, Register A8h-EFh: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. A2h Table 06h, Register F0h-F7h: BIAS MAX LUT F0h-F7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) 29 28 27 26 25 24 23 BIT 7 22 BIT 0 A2h Table 06h, Register F8h-FFh: BIAS OFFSET or SET_IBIAS LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) Open Loop F8h-FFh 29 28 27 26 25 24 23 22 26 25 24 23 22 APC Loop and Dual Closed Loop (SET_IBIAS) F8h-FFh 29 BIT 7 Maxim Integrated 28 27 BIT 0 88 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 08h Register Descriptions A2h Table 08h, Register 80h-F7h: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. A2h Table 08h, Register F8h-FBh: BIASINC LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) Open Loop F8h-FBh 0 0 0 0 0 0 0 25 24 23 22 21 0 APC Loop and Dual Closed Loop F8h-FBh 27 26 BIT 7 20 BIT 0 A2h Table 08h, Register FCh-FFh: MODINC LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) Open Loop and APC Loop FCh-FFh 0 0 0 0 0 0 0 0 26 25 24 23 22 21 20 Dual Closed Loop FCh-FFh 27 BIT 7 Maxim Integrated BIT 0 89 DS1884 SFP and PON ONU Controller with Digital LDD Interface A2h Table 09h Register Descriptions A2h Table 09h, Register 80h-F7h: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. A2h Table 09h, Register F8h-FFh: DAC OFFSET LUT F8h-FFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) 29 28 27 26 25 24 23 BIT 7 22 BIT 0 Auxiliary Memory A0h Register Description Auxiliary Memory A0h, Register 00h-FFh: EEPROM 00h-FFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWAUXA) or (PW1 and RWAUXAU) WRITE ACCESS PW2 or (PW1 and RWAUXA) MEMORY TYPE Nonvolatile (EE) 27 26 25 BIT 7 24 23 22 21 20 BIT 0 Accessible with the slave address A0h. Maxim Integrated 90 DS1884 SFP and PON ONU Controller with Digital LDD Interface Ordering Information Applications Information Power-Supply Decoupling To achieve best results, it is recommended that the power supply is decoupled with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize lead inductance. Layout Considerations Connect all GND pins to a common ground plane. Connect all VCC pins together. SDA and SCL Pullup Resistors SDA is an open-collector output on the device that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics are within specification. Maxim Integrated PART TEMP RANGE PIN-PACKAGE DS1884T+ -40NC to +95NC 24 TQFN-EP* DS1884T+T -40NC to +95NC 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TQFN-EP T2445+1 21-0201 90-0083 91 DS1884 SFP and PON ONU Controller with Digital LDD Interface Revision History REVISION NUMBER REVISION DATE 0 6/11 Initial release 7/11 Added the continuous power dissipation information to the Absolute Maximum Ratings section; updated the AC Electrical Characteristics table typ values for tINIT_3710, tINIT_3945, and tINITR1; updated the 3-Wire Digital Interface Specification table values for tDS, tL, and tT; added the Typical Operating Characteristics section; updated the Delta-Sigma Output and Reference section; updated Figure 10 and 11; changed bit 3 from RSELC to RESERVED for A2h Lower Memory, Register 6Eh; changed bit 2 from INVRSOUT to RESERVED for A2h Table 02h, Register 89h; corrected the pin reference of TXFOUT to TXF for the bit 3 TXDFLT description in A2h Table 02h, Register 8Bh; changed the name of A2h Table 02h, Register C8h-C9h from MOD VALUE to DAC VALUE and updated the register description 1 DESCRIPTION PAGES CHANGED -- 10, 12, 14, 24, 26, 40, 48, 63, 65, 74 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2011 Maxim Integrated Products, Inc. 92 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.