MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 * * 2 * * * * * * Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption - Active Mode: 270 A at 1 MHz, 2.2 V - Standby Mode: 0.7 A - Off Mode (RAM Retention): 0.1 A Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations - Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to 1% - Internal Very-Low-Power Low-Frequency (LF) Oscillator - 32-kHz Crystal - High-Frequency (HF) Crystal up to 16 MHz - Resonator - External Digital Clock Source - External Resistor 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Three Capture/Compare Registers On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion * * * * * * * * Universal Serial Communication Interface - Enhanced UART Supporting Auto Baudrate Detection (LIN) - IrDA Encoder and Decoder - Synchronous SPI - I2CTM Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Bootstrap Loader On-Chip Emulation Module Family Members Include: - MSP430F2330 - 8KB + 256B Flash Memory - 1KB RAM - MSP430F2350 - 16KB + 256B Flash Memory - 2KB RAM - MSP430F2370 - 32KB + 256B Flash Memory - 2KB RAM Available in 40-Pin QFN Package and 49-Pin Die-Sized BGA Package (See Table 1) For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144) DESCRIPTION The Texas Instruments MSP430TM family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430F23x0 series is an ultra-low-power microcontroller with two built-in 16-bit timers, one universal serial communication interface (USCI), a versatile analog comparator, and 32 I/O pins. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. Available Options PACKAGED DEVICES (1) (2) TA -40C to 85C -40C to 105C (1) (2) PLASTIC 49-PIN DSBGA (YFF) PLASTIC 40-PIN QFN (RHA) MSP430F2330IYFF MSP430F2330IRHA MSP430F2350IYFF MSP430F2350IRHA MSP430F2370IYFF MSP430F2370IRHA - MSP430F2330TRHA - MSP430F2350TRHA - MSP430F2370TRHA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Development Tool Support All MSP430 microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging and programming through easy-to-use development tools. Recommended hardware options include: * Debugging and Programming Interface with Target Board - MSP-FET430U23X0 (RHA package) * Debugging and Programming Interface - MSP-FET430UIF (USB) - MSP-FET430PIF (Parallel Port) * Target Board - MSP-TS430QFN23X0 (RHA package) * Production Programmer - MSP-GANG430 2 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Device Pinout, RHA Package 31 32 33 35 34 36 38 37 1 30 2 29 3 28 4 27 5 26 Exposed Thermal Pad 6 25 20 19 18 P4.4/TB1 P4.3/TB0 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/UCA0RXD/UCA0SOMI P3.4/UCA0TXD/UCA0SIMO P3.3/UCB0CLK/UCA0STE P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL 17 21 15 22 10 16 23 9 13 8 14 24 11 7 12 DVCC XIN/P2.6/CA6 XOUT/P2.7/CA7 P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 39 40 AVCC D/AVSS RST/NMI TCK TMS TDI/TCLK TDO/TDI P4.7/TBCLK P4.6/TBOUTH/ACLK P4.5/TB2 RHA PACKAGE (TOP VIEW) Copyright (c) 2006-2011, Texas Instruments Incorporated 3 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Device Pinout, YFF Package YFF PACKAGE (TOP VIEW) A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 D5 D6 D7 E1 E2 E3 E4 E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 Package Dimensions The package dimensions for this YFF package are shown in the following table. See the package drawing at the end of this data sheet for more details. Table 2. YFF Package Dimensions 4 PACKAGED DEVICES D E MSP430F2370IYFF MSP430F2350IYFF MSP430F2330IYFF 3.20 0.05 mm 3.20 0.05 mm Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Functional Block Diagram XIN XOUT DVCC D/AVSS AVCC 1.x/P2.x P P3.x/P4.x 2x8 2x8 ACLK Basic Clock System+ SMCLK MCLK Flash RAM 32kB 16kB 8kB 2kB 2kB 1kB 16MHz CPU MAB incl. 16 Registers MDB Hardware Multiplier Emulation JTAG Interface Brownout Protection MPY, MPYS, MAC, MACS Ports P1/P2 2x8 I/O Interrupt capability Watchdog WDT+ 15-Bit Ports P3/P4 2x8 I/O Timer_A3 Timer_B3 Comp_A+ 3 CC Registers 3 CC Registers 8 Channels USCI A0: UART IrDA, SPI USCI B0: SPI, I2C RST/NMI Copyright (c) 2006-2011, Texas Instruments Incorporated 5 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 3. Terminal Functions TERMINAL NAME DESCRIPTION YFF RHA DVCC B3 1 XIN/P2.6/CA6 A2 2 I/O Input terminal of crystal oscillator/general-purpose digital I/O pin/Comparator_A input XOUT/P2.7/CA7 A3 3 I/O Output terminal of crystal oscillator/general-purpose digital I/O pin/Comparator_A input P1.0/TACLK B4 4 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 C4 5 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output P1.2/TA1 A5 6 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 B5 7 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK A6 8 I/O General-purpose digital I/O pin/SMCLK signal output P1.5/TA0 B6 9 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output P1.6/TA1 A7 10 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output P1.7/TA2 B7 11 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output P2.0/ACLK/CA2 C5 12 I/O General-purpose digital I/O pin/ACLK output/Comparator_A input P2.1/TAINCLK/CA3 C7 13 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK/Comparator_A input P2.2/CAOUT/TA0/CA4 C6 14 I/O General-purpose digital I/O pin/Comparator_A output/Timer_A, capture: CCI0B input/Comparator_A input P2.3/CA0/TA1 D7 15 I/O General-purpose digital I/O pin/Comparator_A input/Timer_A, compare: Out1 output P2.4/CA1/TA2 D6 16 I/O General-purpose digital I/O pin/Comparator_A input/Timer_A, compare: Out2 output P2.5/ROSC/CA5 E7 17 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency/Comparator_A input P3.0/UCB0STE/ UCA0CLK E6 18 I/O General-purpose digital I/O pin/USCIB0 slave transmit enable/USCIA clock input/output P3.1/UCB0SIMO/ UCB0SDA F7 19 I/O General-purpose digital I/O pin/USCIB0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/UCB0SOMI/ UCB0SCL F6 20 I/O General-purpose digital I/O pin/USCIB0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/UCB0CLK/ UCA0STE G7 21 I/O General-purpose digital I/O/USCIB0 clock input/output, USCIA0 slave transmit enable P3.4/UCA0TXD/ UCA0SIMO G6 22 I/O General-purpose digital I/O pin/USCIA0 transmit data output in UART mode, slave data in/master out in SPI mode P3.5/UCA0RXD/ UCA0SOMI G5 23 I/O General-purpose digital I/O pin/USCIA0 receive data input in UART mode, slave data out/master in in SPI mode P3.6 F5 24 I/O General-purpose digital I/O pin P3.7 G4 25 I/O General-purpose digital I/O pin P4.0/TB0 F4 26 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A input, compare: Out0 output P4.1/TB1 G3 27 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A input, compare: Out1 output P4.2/TB2 G2 28 I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A input, compare: Out2 output P4.3/TB0 F3 29 I/O General-purpose digital I/O pin/Timer_B, capture: CCI0B input, compare: Out0 output P4.4/TB1 G1 30 I/O General-purpose digital I/O pin/Timer_B, capture: CCI1B input, compare: Out1 output P4.5/TB2 F1 31 I/O General-purpose digital I/O pin/Timer_B, compare: Out2 output P4.6/TBOUTH/ACLK F2 32 I/O General-purpose digital I/O pin/switch all PWM digital outputs to high impedance Timer_B3: TB0 to TB2/ACLK output P4.7/TBCLK E2 33 I/O General-purpose digital I/O pin/input clock TBCLK - Timer_B3 TDO/TDI E1 34 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK D1 35 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS D2 36 I Test mode select. TMS is used as an input port for device programming and test. TCK C1 37 I Test clock. TCK is the clock input port for device programming and test. RST/NMI C2 38 I Reset input, nonmaskable interrupt input port. D/AVSS B1 39 6 I/O Digital supply voltage, positive terminal. Supplies all digital parts. Digital/analog supply voltage, negative terminal Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 3. Terminal Functions (continued) TERMINAL NAME AVCC DESCRIPTION YFF RHA I/O A1 40 QFN Pad - NA NA Analog supply voltage, positive terminal QFN package pad. Connection to D/AVSS recommended. Reserved A4, B2, C3, D3, D4, D5, E3, E4, E5 - NA BGA package GND balls. Connection to DVSS/AVSS is recommended. Copyright (c) 2006-2011, Texas Instruments Incorporated 7 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430TM CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 Instruction Set General-Purpose Register R11 The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 4 shows examples of the three types of instruction formats; Table 5 shows the address modes. General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions. Table 4. Instruction Word Formats EXAMPLE OPERATION Dual operands, source-destination INSTRUCTION FORMAT ADD R4,R5 R4 + R5 R5 Single operands, destination only CALL R8 PC (TOS), R8 PC JNE Jump-on-equal bit = 0 Relative jump, unconditional/conditional Table 5. Address Mode Descriptions ADDRESS MODE SYNTAX EXAMPLE OPERATION MOV Rs,Rd MOV R10,R11 R10 R11 Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) M(TCDAT) Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) M(Tab+R6) Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) R11 R10 + 2 R10 Immediate MOV #X,TONI MOV #45,TONI #45 M(TONI) 8 D (2) Register (1) (2) S (1) S = source D = destination Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 www.ti.com SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 Operating Modes The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: * Active mode (AM) - All clocks are active. * Low-power mode 0 (LPM0) - CPU is disabled. - ACLK and SMCLK remain active. MCLK is disabled. * Low-power mode 1 (LPM1) - CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. - DCO dc-generator is disabled if DCO not used in active mode. * Low-power mode 2 (LPM2) - CPU is disabled. - MCLK and SMCLK are disabled. - DCO dc-generator remains enabled. - ACLK remains active. * Low-power mode 3 (LPM3) - CPU is disabled. - MCLK and SMCLK are disabled. - DCO dc-generator is disabled. - ACLK remains active. * Low-power mode 4 (LPM4) - CPU is disabled. - ACLK is disabled. - MCLK and SMCLK are disabled. - DCO dc-generator is disabled. - Crystal oscillator is stopped. Copyright (c) 2006-2011, Texas Instruments Incorporated 9 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 6. Interrupt Vector Addresses INTERRUPT SOURCE INTERRUPT FLAG Power-up PORIFG External Reset RSTIFG Watchdog WDTIFG Flash key violation KEYV PC out of range (1) WORD ADDRESS PRIORITY Reset 0xFFFE 31, highest 0xFFFC 30 (2) NMI NMIIFG (non)-maskable Oscillator Fault OFIFG (non)-maskable Flash memory access violation ACCVIFG (2) (3) (non)-maskable Timer_B3 TBCCR0 CCIFG (4) maskable 0xFFFA 29 Timer_B3 TBCCR1 and TBCCR2, CCIFGs, TBIFG (2) (4) maskable 0xFFF8 28 Comparator_A+ CAIFG maskable 0xFFF6 27 Watchdog timer WDTIFG maskable 0xFFF4 26 Timer_A3 TACCR0 CCIFG (4) maskable 0xFFF2 25 Timer_A3 TACCR1 CCIFG, TACCR2 CCIFG, TAIFG (2) (4) maskable 0xFFF0 24 USCI_A0/USCI_B0 Receive USCI_B0 I2C Status UCA0RXIFG, UCB0RXIFG (2) (5) maskable 0xFFEE 23 USCI_A0/USCI_B0 Transmit USCI_B0 I2C Receive/Transmit UCA0TXIFG, UCB0TXIFG (2) (6) maskable 0xFFEC 22 0xFFEA 21 (1) (2) (3) (4) (5) (6) (7) (8) 10 SYSTEM INTERRUPT 0xFFE8 20 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (2) (3) maskable 0xFFE6 19 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (2) (3) maskable 0xFFE4 18 0xFFE2 17 0xFFE0 16 See (7) 0xFFDE 15 See (8) 0xFFDC to 0xFFC0 14 to 0, lowest A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or from within unused address range. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. Interrupt flags are located in the module. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0x0) disables the erasure of the flash if an invalid password is supplied. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if necessary. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device. Table 7. Interrupt Enable 1 Address 7 6 00h WDTIE OFIE NMIIE ACCVIE 5 4 1 0 ACCVIE NMIIE 3 2 OFIE WDTIE rw-0 rw-0 rw-0 rw-0 Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable Table 8. Interrupt Enable 2 Address 7 6 5 4 01h UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 USCI_A0 receive-interrupt enable USCI_A0 transmit-interrupt enable USCI_B0 receive-interrupt enable USCI_B0 transmit-interrupt enable Table 9. Interrupt Flag Register 1 Address 7 6 5 02h WDTIFG OFIFG RSTIFG PORIFG NMIIFG 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. Power-on reset interrupt flag. Set on VCC power up. Set via RST/NMI pin Table 10. Interrupt Flag Register 2 Address 7 6 03h UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG 5 4 3 2 1 0 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-0 rw-0 rw-0 rw-0 USCI_A0 receive-interrupt flag USCI_A0 transmit-interrupt flag USCI_B0 receive-interrupt flag USCI_B0 transmit-interrupt flag Copyright (c) 2006-2011, Texas Instruments Incorporated 11 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Memory Organization Table 11. Memory Organization MSP430F2330 Memory MSP430F2350 MSP430F2370 Size 8KB Flash 16KB Flash 32KB Main: interrupt vector Flash 0xFFFF - 0xFFC0 0xFFFF - 0xFFC0 0xFFFF - 0xFFC0 Main: code memory Flash 0xFFFF - 0xE000 0xFFFF - 0xC000 0xFFFF - 0x8000 Information memory Size 256 Byte 256 Byte 256 Byte Flash 0x10FF - 0x1000 0x10FF - 0x1000 0x10FF - 0x1000 Size 1KB 1KB 1KB ROM 0x0FFF - 0x0C00 0x0FFF - 0x0C00 0x0FFF - 0x0C00 Size 1KB 2KB 2KB 0x5FF - 0x0200 0x9FF - 0x0200 0x09FF - 0x0200 16-bit 0x01FF - 0x0100 0x01FF - 0x0100 0x01FF - 0x0100 8-bit 0x00FF - 0x0010 0x00FF - 0x0010 0x00FF - 0x0010 8-bit SFR 0x000F - 0x0000 0x000F - 0x0000 0x000F - 0x0000 Boot memory RAM Peripherals Bootstrap Loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide, literature number SLAU319. Table 12. BSL Function Pins BSL FUNCTION YFF PACKAGE PINS Data transmit C4 - P1.1 RHA PACKAGE PINS 5 - P1.1 Data receive C6 - P2.2 14 - P2.2 Flash Memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: * Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. * Segments 0 to n may be erased in one step, or each segment may be individually erased. * Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. * Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. 12 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: * Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-low-power LF oscillator. * Main clock (MCLK), the system clock used by the CPU. * Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. Table 13. DCO Calibration Data, Provided From Factory In Flash Info Memory Segment A DCO FREQUENCY CALIBRATION REGISTER SIZE CALBC1_1MHZ byte 0x10FF CALBC0_1MHZ byte 0x10FE CALBC1_8MHZ byte 0x10FD CALBC0_8MHZ byte 0x10FC CALBC1_12MHZ byte 0x10FB CALBC0_12MHZ byte 0x10FA CALBC1_16MHZ byte 0x10F9 CALBC0_16MHZ byte 0x10F8 1 MHz 8 MHz 12 MHz 16 MHz ADDRESS Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O There are four 8-bit I/O ports implemented--ports P1, P2, P3, and P4: * All individual I/O bits are independently programmable. * Any combination of input, output, and interrupt condition is possible. * Edge-selectable interrupt input capability for all eight bits of port P1 and P2. * Read/write access to port-control registers is supported by all instructions. * Each I/O has an individually programmable pullup/pulldown resistor. The MSP430F23x0 devices provide 32 total port I/O pins available externally. See the device pinout for more information. Watchdog Timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Copyright (c) 2006-2011, Texas Instruments Incorporated 13 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8, 8x16, and 8x8 bit operations. The module is capable of supporting signed and unsignedmultiplication as well as signed and unsignedmultiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. Comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14. Timer_A3 Signal Connections INPUT PIN NUMBER YFF RHA DEVICE INPUT SIGNAL B4 - P1.0 4 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER YFF RHA C7 - P2.1 13 - P2.1 TAINCLK INCLK C4 - P1.1 5 - P1.1 TA0 CCI0A C4 - P1.1 5 - P1.1 C6 - P2.2 14 - P2.2 TA0 CCI0B B6 - P1.5 9 - P1.5 VSS GND A5 - P1.2 6 - P1.2 A7 - P1.6 10 - P1.6 D7 - P2.3 15 - P2.3 A5 - P1.2 B5 - P1.3 14 MODULE INPUT NAME 6 - P1.2 7 - P1.3 VCC VCC TA1 CCI1A CAOUT (internal) CCI1B VSS GND VCC VCC CCR0 CCR1 TA0 TA1 TA2 CCI2A B5 - P1.3 7 - P1.3 ACLK (internal) CCI2B B7 - P1.7 11 - P1.7 VSS GND D6 - P2.4 16 - P2.4 VCC VCC CCR2 TA2 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 15. Timer_B3 Signal Connections INPUT PIN NUMBER YFF RHA DEVICE INPUT SIGNAL MODULE INPUT NAME E2 - P4.7 33 - P4.7 TBCLK TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER YFF RHA TBCLK INCLK F4 - P4.0 26 - P4.0 TB0 CCI0A F4 - P4.0 26 - P4.0 F3 - P4.3 29 - P4.3 TB0 CCI0B F3 - P4.3 29 - P4.3 VSS GND G3 - P4.1 27 - P4.1 G1 - P4.4 30 - P4.4 VCC VCC G3 - P4.1 27 - P4.1 TA1 CCI1A G1 - P4.4 30 - P4.4 TB1 CCI1B VSS GND VCC VCC G2 - P4.2 28 - P4.2 CCR0 CCR1 TB0 TB1 TB2 CCI2A G2 - P4.2 28 - P4.2 ACLK (internal) CCI2B F1 - P4.5 31 - P4.5 VSS GND VCC VCC CCR2 TB2 Universal Serial Communications Interface (USCI) The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. Copyright (c) 2006-2011, Texas Instruments Incorporated 15 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Peripheral File Map Table 16. Peripherals With Word Access MODULE Timer_B3 Timer_A3 Flash Memory Hardware Multiplier Watchdog Timer+ REGISTER NAME SHORT NAME ADDRESS OFFSET Capture/compare register TBCCR2 0x0196 Capture/compare register TBCCR1 0x0194 Capture/compare register TBCCR0 0x0192 Timer_B register TBR 0x0190 Capture/compare control TBCCTL2 0x0186 Capture/compare control TBCCTL1 0x0184 Capture/compare control TBCCTL0 0x0182 Timer_B control TBCTL 0x0180 Timer_B interrupt vector TBIV 0x011E Capture/compare register TACCR2 0x0176 Capture/compare register TACCR1 0x0174 Capture/compare register TACCR0 0x0172 Timer_A register TAR 0x0170 Capture/compare control TACCTL2 0x0166 Capture/compare control TACCTL1 0x0164 Capture/compare control TACCTL0 0x0162 Timer_A control TACTL 0x0160 Timer_A interrupt vector TAIV 0x012E Flash control 3 FCTL3 0x012C Flash control 2 FCTL2 0x012A Flash control 1 FCTL1 0x0128 Sum extend SUMEXT 0x013E Result high word RESHI 0x013C Result low word RESLO 0x013A Second operand OP2 0x0138 Multiply signed +accumulate/operand1 MACS 0x0136 Multiply+accumulate/operand1 MAC 0x0134 Multiply signed/operand1 MPYS 0x0132 Multiply unsigned/operand1 MPY 0x0130 Watchdog/timer control WDTCTL 0x0120 Table 17. Peripherals With Byte Access MODULE USCI_B0 16 REGISTER NAME SHORT NAME ADDRESS OFFSET USCI_B0 transmit buffer UCB0TXBUF 0x06F USCI_B0 receive buffer UCB0RXBUF 0x06E USCI_B0 status UCB0STAT 0x06D USCI_B0 bit rate control 1 UCB0BR1 0x06B USCI_B0 bit rate control 0 UCB0BR0 0x06A USCI_B0 control 1 UCB0CTL1 0x069 USCI_B0 control 0 UCB0CTL0 0x068 USCI_B0 I2C slave address UCB0SA 0x011A USCI_B0 I2C own address UCB0OA 0x0118 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 17. Peripherals With Byte Access (continued) MODULE USCI_A0 Basic Clock System+ Port P4 Port P3 Port P2 Port P1 Special Function REGISTER NAME SHORT NAME ADDRESS OFFSET USCI_A0 transmit buffer UCA0TXBUF 0x0067 USCI_A0 receive buffer UCA0RXBUF 0x0066 USCI_A0 status UCA0STAT 0x0065 USCI_A0 modulation control UCA0MCTL 0x0064 USCI_A0 baud rate control 1 UCA0BR1 0x0063 USCI_A0 baud rate control 0 UCA0BR0 0x0062 USCI_A0 control 1 UCA0CTL1 0x0061 USCI_A0 control 0 UCA0CTL0 0x0060 USCI_A0 IrDA receive control UCA0IRRCTL 0x005F USCI_A0 IrDA transmit control UCA0IRTCTL 0x005E USCI_A0 auto baud rate control UCA0ABCTL 0x005D Basic clock system control 3 BCSCTL3 0x0053 Basic clock system control 2 BCSCTL2 0x0058 Basic clock system control 1 BCSCTL1 0x0057 DCO clock frequency control DCOCTL 0x0056 Port P4 resistor enable P4REN 0x0011 Port P4 selection P4SEL 0x001F Port P4 direction P4DIR 0x001E Port P4 output P4OUT 0x001D Port P4 input P4IN 0x001C Port P3 resistor enable P3REN 0x0010 Port P3 selection P3SEL 0x001B Port P3 direction P3DIR 0x001A Port P3 output P3OUT 0x0019 Port P3 input P3IN 0x0018 Port P2 resistor enable P2REN 0x002F Port P2 selection P2SEL 0x002E Port P2 interrupt enable P2IE 0x002D Port P2 interrupt edge select P2IES 0x002C Port P2 interrupt flag P2IFG 0x002B Port P2 direction P2DIR 0x002A Port P2 output P2OUT 0x0029 Port P2 input P2IN 0x0028 Port P1 resistor enable P1REN 0x0027 Port P1 selection P1SEL 0x0026 Port P1 interrupt enable P1IE 0x0025 Port P1 interrupt edge select P1IES 0x0024 Port P1 interrupt flag P1IFG 0x0023 Port P1 direction P1DIR 0x0022 Port P1 output P1OUT 0x0021 Port P1 input P1IN 0x0020 SFR interrupt flag 2 IFG2 0x0003 SFR interrupt flag 1 IFG1 0x0002 SFR interrupt enable 2 IE2 0x0001 SFR interrupt enable 1 IE1 0x0000 Copyright (c) 2006-2011, Texas Instruments Incorporated 17 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin -0.3 V to 4.1 V (2) -0.3 V to (VCC + 0.3 V) 2 mA Diode current at any device terminal Storage temperature, Tstg (1) (3) Unprogrammed device -55C to 150C Programmed device -55C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. (2) (3) Recommended Operating Conditions (1) VCC Supply voltage (2), AVCC = DVCC = VCC VSS Supply voltage, AVSS = DVSS = VSS TA Operating free-air temperature fSYSTEM Processor frequency (maximum MCLK frequency) (1) (3) (see Figure 1) (1) (2) (3) MIN MAX During program execution 1.8 3.6 During flash memory programming 2.2 3.6 0 0 I version -40 85 T version -40 105 VCC = 1.8 V, Duty cycle = 50% 10% dc 4.15 VCC = 2.7 V, Duty cycle = 50% 10% dc 12 VCC 3.3 V, Duty cycle = 50% 10% dc 16 UNIT V V C MHz Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power-up. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Legend : System Frequency - MHz 16 MHz Supply voltage range during flash memory programming 12 MHz Supply voltage range during program execution 7.5 MHz 4.15 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage - V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area 18 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Active Mode Supply Current (Into DVCC + AVCC ) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz IAM,1MHz IAM,4kHz IAM,100kHz (1) (2) TEST CONDITIONS TA VCC MIN TYP MAX 2.2 V 270 370 Active mode (AM) current (1 MHz) fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 3V 390 550 2.2 V 226 Active mode (AM) current (1 MHz) fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 3V 318 -40C to 85C Active mode (AM) current (4 kHz) fMCLK = fSMCLK = fACLK = 32768 Hz / 8 = 4096 Hz, fDCO = 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = fDCO(0,0) 100 kHz, fACLK = 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -40C to 85C Active mode (AM) current (100 kHz) 6 14 -40C to 85C 3 9 3V 105C -40C to 85C 60 85 95 72 3V 105C A 17 2.2 V 105C A A 2 2.2 V 105C UNIT A 95 105 All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC) ACTIVE-MODE CURRENT vs SUPPLY VOLTAGE TA = 25C ACTIVE-MODE CURRENT vs DCO FREQUENCY 8.0 5.0 f DCO = 16 MHz TA = 85 C 7.0 6.0 f DCO = 12 MHz 5.0 4.0 f DCO = 8 MHz 3.0 2.0 Active Mode Current - mA Active Mode Current - mA 4.0 TA = 25 C 3.0 VCC = 3 V TA = 85 C 2.0 TA = 25 C 1.0 1.0 0.0 1.5 VCC = 2.2 V f DCO = 1 MHz 2.0 2.5 3.0 VCC - Supply Voltage - V Figure 2. Copyright (c) 2006-2011, Texas Instruments Incorporated 3.5 4.0 0.0 0.0 4.0 8.0 12.0 16.0 f DCO - DCO Frequency - MHz Figure 3. 19 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Low-Power-Mode Supply Currents (Into VCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ILPM0, 1MHz ILPM0, 100kHz ILPM2 Low-power mode 0 (LPM0) current (3) Low-power mode 0 (LPM0) current (3) Low-power mode 2 (LPM2) current (4) TEST CONDITIONS TA VCC fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40C to 85C fMCLK = 0 MHz, fSMCLK = fDCO(0, 0) 100 kHz, fACLK = 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -40C to 85C fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 -40C to 85C 105C 2.2 V -40C to 85C Low-power mode 3 (LPM3) current (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 TYP MAX 68 84 88 110 105C 2.2 V -40C to 85C 105C 36 -40C to 85C 85C 20 0.7 Low-power mode 3 current, (LPM3) (4) 0.85 3V ILPM4 Low-power mode 4 (LPM4) current (5) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 20 2.2 V 0.8 2.9 9 0.35 3V 1 11 -40C 0.5 2.2 V 0.5 1.7 2.7 105C 8.6 -40C 0.5 25C 3V A 3.5 105C 105C (3) (4) (5) 0.25 -40C to 25C 85C A 12 85C 85C (1) (2) 1.2 3.8 105C 25C A 1 10 85C 85C 32 3.3 105C -40C to 25C ILPM3, VLO 28 37 2.2 V -40C to 25C A 32 23 105C fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 50 54 3V 105C 45 50 40 2.2 V A 115 3V 105C UNIT 90 3V 105C -40C to 25C ILPM3, LFXT1 MIN A 0.5 1.9 3 9 All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, JTAG, RST/NMI, XIN (1)) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ TEST CONDITIONS Positive-going input threshold voltage VCC MIN Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT- ) RPull Pullup/pulldown resistor For pullup: VIN = VSS, For pulldown: VIN = VCC CI Input capacitance VIN = VSS or VCC (1) XIN only in bypass mode MAX 0.45 VCC 0.75 VCC 1 1.65 1.35 2.25 0.25 VCC 0.55 VCC 2.2 V 0.55 1.20 3V 0.75 1.65 2.2 V 0.2 1 3V 0.3 1 2.2 V 3V VIT- TYP 20 35 UNIT V V V 50 k 5 pF Inputs (Ports P1, P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) External interrupt timing TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag (1) VCC 2.2 V/3 V MIN TYP MAX UNIT 20 ns An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set with trigger signals shorter than t(int). Leakage Current (Ports P1, P2, P3, P4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current TEST CONDITIONS (1) (2) VCC 2.2 V/3 V MIN TYP MAX UNIT 50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Copyright (c) 2006-2011, Texas Instruments Incorporated 21 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Outputs (Ports P1, P2, P3, P4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA VOH High-level output voltage IOH(max) = -6 mA (2) IOH(max) = -1.5 mA (1) IOH(max) = -6 mA (2) IOL(max) = 1.5 mA VOL Low-level output voltage (2) 2.2 V 3V (1) 2.2 V IOL(max) = 6 mA (2) IOL(max) = 1.5 mA (1) IOL(max) = 6 mA (2) (1) VCC (1) 3V MIN MAX VCC - 0.25 VCC VCC - 0.6 VCC VCC - 0.25 VCC VCC - 0.6 VCC VSS VSS + 0.25 VSS VSS + 0.6 VSS VSS + 0.25 VSS VSS + 0.6 UNIT V V The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. Output Frequency (Ports P1, P2, P3, P4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fPx.y Port output frequency (with load) P1.4/SMCLK, CL = 20 pF, RL = 1 k (1) (2) fPortCLK Clock output frequency P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2) (1) (2) 22 VCC MIN TYP MAX 2.2 V 7.5 3V 12 2.2 V 7.5 3V 16 UNIT MHz MHz A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - Outputs One output loaded at a time. TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 VCC = 2.2 V P2.4 TA = 25C 20.0 I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 25.0 TA = 85C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P2.4 40.0 TA = 85C 30.0 20.0 10.0 0.0 0.0 2.5 0.5 VOL - Low-Level Output Voltage - V 1.5 2.0 2.5 3.0 Figure 4. Figure 5. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 3.5 0.0 VCC = 2.2 V P2.4 I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA 1.0 VOL - Low-Level Output Voltage - V 0.0 -5.0 -10.0 -15.0 -20.0 TA = 85C -25.0 0.0 TA = 25C TA = 25C 0.5 1.0 1.5 2.0 VOH - High-Level Output Voltage - V Figure 6. Copyright (c) 2006-2011, Texas Instruments Incorporated 2.5 VCC = 3 V P2.4 -10.0 -20.0 -30.0 -40.0 -50.0 0.0 TA = 85C TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH - High-Level Output Voltage - V Figure 7. 23 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com POR/Brownout Reset (BOR) (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC(start) See Figure 8 dVCC /dt 3 V/s V(B_IT-) See Figure 8 through Figure 10 dVCC /dt 3 V/s Vhys(B_IT-) See Figure 8 dVCC /dt 3 V/s td(BOR) See Figure 8 t(reset) Pulse length needed at RST/NMI pin to accepted reset internally (1) (2) VCC MIN TYP MAX 0.7 x V(B_IT-) 70 2.2 V/3 V 2 130 UNIT V 1.71 V 210 mV 2000 s s The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8 V. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 24 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) - V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw - Pulse Width - s 1 ns t pw - Pulse Width - s Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 t pw - Pulse Width - s 1000 tf tr t pw - Pulse Width - s Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal Copyright (c) 2006-2011, Texas Instruments Incorporated 25 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Main DCO Characteristics * * * All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: faverage = 32 x fDCO(RSEL,DCO) x fDCO(RSEL,DCO+1) MOD x fDCO(RSEL,DCO) + (32 - MOD) x fDCO(RSEL,DCO+1) DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX RSELx < 14 1.8 3.6 RSELx = 14 2.2 3.6 UNIT VCC Supply voltage range 3.0 3.6 fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V/3 V 0.06 0.14 MHz fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V/3 V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V/3 V 0.10 0.20 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V/3 V 0.14 0.28 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V/3 V 0.20 0.40 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.28 0.54 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V/3 V 0.39 0.77 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V/3 V 0.54 1.06 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V/3 V 0.80 1.50 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V/3 V 1.10 2.10 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V/3 V 1.60 3.00 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V/3 V 2.50 4.30 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V/3 V 3.00 5.50 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V/3 V 4.30 7.30 MHz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V/3 V 6.00 9.60 MHz fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V/3 V 8.60 13.9 MHz fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO) 2.2 V/3 V 1.55 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO) 2.2 V/3 V 1.05 1.08 1.12 ratio Duty cycle Measured at P1.4/SMCLK 2.2 V/3 V 40 50 60 RSELx = 15 26 V % Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Calibrated DCO Frequencies - Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA VCC MIN TYP MAX UNIT 25C 3V -1 0.2 +1 25C 3V 0.990 1 1.010 MHz % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25C 3V 7.920 8 8.080 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25C 3V 11.88 12 12.12 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25C 3V 15.84 16 16.16 MHz MAX UNIT Calibrated DCO Frequencies - Tolerance Over Temperature 0C to 85C over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fCAL(1MHz) fCAL(8MHz) fCAL(12MHz) fCAL(16MHz) TA VCC 1-MHz tolerance over temperature 0C to 85C 3V -2.5 0.5 +2.5 % 8-MHz tolerance over temperature 0C to 85C 3V -2.5 1 +2.5 % 12-MHz tolerance over temperature 0C to 85C 3V -2.5 1 +2.5 % 16-MHz tolerance over temperature 0C to 85C 3V -3 2 +3 % 2.2 V 0.97 1 1.03 3V 0.975 1 1.025 3.6 V 0.97 1 1.03 2.2 V 7.76 8 8.4 3V 7.8 8 8.2 3.6 V 7.6 8 8.24 2.2 V 11.64 12 12.36 3V 11.64 12 12.36 3.6 V 11.64 12 12.36 3V 15.52 16 16.48 15 16 16.48 1-MHz calibration value 8-MHz calibration value 12-MHz calibration value 16-MHz calibration value TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 0C to 85C BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 0C to 85C BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 0C to 85C BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 0C to 85C Copyright (c) 2006-2011, Texas Instruments Incorporated 3.6 V MIN TYP MHz MHz MHz MHz 27 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX 1-MHz tolerance over VCC 25C 8-MHz tolerance over VCC 25C 12-MHz tolerance over VCC 16-MHz tolerance over VCC UNIT 1.8 V to 3.6 V -3 2 +3 % 1.8 V to 3.6 V -3 2 +3 % 25C 2.2 V to 3.6 V -3 2 +3 % 25C 3 V to 3.6 V -6 2 +3 % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms 25C 1.8 V to 3.6 V 0.97 1 1.03 MHz fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms 25C 1.8 V to 3.6 V 7.76 8 8.24 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms 25C 2.2 V to 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms 25C 3 V to 3.6 V 15 16 16.48 MHz MIN TYP MAX UNIT Calibrated DCO Frequencies - Overall Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC 1-MHz tolerance overall -40C to 105C 1.8 V to 3.6 V -5 2 +5 % 8-MHz tolerance overall -40C to 105C 1.8 V to 3.6 V -5 2 +5 % 12-MHz tolerance overall -40C to 105C 2.2 V to 3.6 V -5 2 +5 % 16-MHz tolerance overall -40C to 105C 3 V to 3.6 V -6 3 +6 % fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, Gating time: 5 ms -40C to 105C 1.8 V to 3.6 V 0.95 1 1.05 MHz fCAL(8MHz) 8-MHz calibration value BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, Gating time: 5 ms -40C to 105C 1.8 V to 3.6 V 7.6 8 8.4 MHz fCAL(12MHz) 12-MHz calibration value BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, Gating time: 5 ms -40C to 105C 2.2 V to 3.6 V 11.4 12 12.6 MHz fCAL(16MHz) 16-MHz calibration value BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, Gating time: 2 ms -40C to 105C 3 V to 3.6 V 15 16 17 MHz 28 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - Calibrated 1-MHz DCO Frequency CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.03 Frequency - MHz 1.02 TA = 105 C 1.01 TA = 85 C 1.00 TA = 25 C 0.99 TA = -40 C 0.98 0.97 1.5 2.0 2.5 3.0 3.5 4.0 VCC - Supply Voltage - V Figure 11. Copyright (c) 2006-2011, Texas Instruments Incorporated 29 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ tDCO,LPM3/4 BCSCTL1 = CALBC1_8MHZ, DCO clock wake-up time DCOCTL = CALDCO_8MHZ from LPM3/4 (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ (1) (2) UNIT 2 2.2 V/3 V 1.5 s 1 BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ tCPU,LPM3/4 MAX 3V CPU wake-up time from LPM3/4 (2) 1 1 / fMCLK + tClock,LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 CLOCK WAKE-UP TIME FROM LPM3 vs DCO FREQUENCY DCO Wake Time - s 10.00 RSELx = 0 to 11 RSELx = 12 to 15 1.00 0.10 0.10 1.00 10.00 DCO Frequency - MHz Figure 12. 30 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com DCO With External Resistor ROSC (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fDCO,ROSC DCO output frequency with ROSC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25C DT Temperature drift DV Drift with VCC (1) VCC MIN TYP MAX UNIT 2.2 V 1.8 3V 1.95 DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.1 %/C DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 10 %/V MHz ROSC = 100 k. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = 50 ppm/C. Typical Characteristics - DCO With External Resistor ROSC DCO FREQUENCY vs ROSC VCC = 2.2 V, TA = 25C DCO FREQUENCY vs ROSC VCC = 3 V, TA = 25C 10.00 DCO Frequency - MHz DCO Frequency - MHz 10.00 1.00 RSELx = 4 0.10 0.01 10.00 100.00 1000.00 0.10 100.00 1000.00 10000.00 ROSC - External Resistor - kW ROSC - External Resistor - kW Figure 13. Figure 14. DCO FREQUENCY vs TEMPERATURE VCC = 3 V DCO FREQUENCY vs SUPPLY VOLTAGE TA = 25C 2.50 2.25 2.25 ROSC = 100k 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 -25 0 25 50 TA - Temperature - C Figure 15. Copyright (c) 2006-2011, Texas Instruments Incorporated 75 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 ROSC = 1M 0.25 ROSC = 100k 2.00 DCO Frequency - MHz 2.00 DCO Frequency - MHz RSELx = 4 0.01 10.00 10000.00 2.50 0.00 -50 1.00 ROSC = 1M 0.25 100 0.00 2.0 2.5 3.0 3.5 4.0 VCC - Supply Voltage - V Figure 16. 31 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Crystal Oscillator LFXT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 LF mode OALF Oscillation allowance for LF crystals CL,eff fFault,LF (1) (2) (3) (4) Integrated effective load capacitance, LF mode (2) XTS = 0, LFXT1Sx = 0 or 1 VCC MIN TYP 1.8 V to 3.6 V 1.8 V to 3.6 V MAX 32768 10000 32768 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF 500 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF 200 UNIT Hz 50000 Hz k XTS = 0, XCAPx = 0 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 Duty cycle, LF mode XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz 2.2 V/3 V 30 Oscillator fault frequency, LF mode (3) XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4) 2.2 V/3 V 10 50 pF 70 % 10000 Hz To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the crystal that is used. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC fVLO VLO frequency 2.2 V/3 V dfVLO/dT VLO frequency temperature drift (1) 2.2 V/3 V dfVLO/dVCC VLO frequency supply voltage drift (2) (1) (2) 32 1.8 V to 3.6 V MIN TYP MAX 4 12 20 UNIT kHz 0.5 %/C 4 %/V Calculated using the box method: I version: [MAX(-40...85C) - MIN(-40...85C)]/MIN(-40...85C)/[85C - (-40C)] T version: [MAX(-40...105C) - MIN(-40...105C)]/MIN(-40...105C)/[105C - (-40C)] Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V) Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Crystal Oscillator LFXT1, High-Frequency Mode (1) PARAMETER VCC MIN XTS = 1, XCAPx = 0, LFXT1Sx = 0 1.8 V to 3.6 V LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, XCAPx = 0, LFXT1Sx = 1 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, XCAPx = 0, LFXT1Sx = 2 fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 fLFXT1,HF1 fLFXT1,HF2 TEST CONDITIONS MAX UNIT 0.4 1 MHz 1.8 V to 3.6 V 1 4 MHz 1.8 V to 3.6 V 2 10 2.2 V to 3.6 V 2 12 3 V to 3.6 V fLFXT1,HF,logic OAHF CL,eff LFXT1 oscillator logic-level square-wave input frequency, HF mode Oscillation allowance for HF crystals (see Figure 17 and Figure 18) Integrated effective load capacitance, HF mode (2) (1) (2) (3) (4) (5) Oscillator fault frequency 2 16 1.8 V to 3.6 V 0.4 10 2.2 V to 3.6 V 0.4 12 3 V to 3.6 V 0.4 16 XTS = 1, XCAPx = 0, LFXT1Sx = 0, fLFXT1,HF = 1 MHz, CL,eff = 15 pF 2700 XTS = 1, XCAPx = 0, LFXT1Sx = 1, fLFXT1,HF = 4 MHz, CL,eff = 15 pF 800 XTS = 1, XCAPx = 0, LFXT1Sx = 2, fLFXT1,HF = 16 MHz, CL,eff = 15 pF 300 XTS = 1, XCAPx = 0 (3) XTS = 1, XCAPx = 0, Measured at P2.0/ACLK, fLFXT1,HF = 10 MHz Duty cycle, HF mode fFault,HF XTS = 1, XCAPx = 0, LFXT1Sx = 3 XTS = 1, XCAPx = 0, Measured at P2.0/ACLK, fLFXT1,HF = 16 MHz (4) TYP XTS = 1, XCAPx = 0, LFXT1Sx = 3 (5) 50 pF 60 2.2 V/3 V % 40 2.2 V/3 V MHz 1 40 MHz 30 50 60 300 kHz To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals. Copyright (c) 2006-2011, Texas Instruments Incorporated 33 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25C OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL,eff = 15 pF, TA = 25C 800 100000 LFXT1Sx = 2 XT Oscillator Supply Current - A Oscillation Allowance - W 700 10000 1000 LFXT1Sx = 2 100 LFXT1Sx = 0 LFXT1Sx = 1 600 500 400 300 LFXT1Sx = 1 200 100 LFXT1Sx = 0 10 0.1 1 10 Crystal Frequency - MHz Figure 17. 34 100 0 0 4 8 12 16 20 Crystal Frequency - MHz Figure 18. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% 10% tTA,cap Timer_A capture timing TA0, TA1, TA2 VCC MIN MAX 2.2 V 10 3V 16 2.2 V/3 V 20 UNIT MHz ns Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTB Timer_B clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% 10% tTB,cap Timer_B capture timing TB0, TB1, TB2 Copyright (c) 2006-2011, Texas Instruments Incorporated VCC MIN MAX 2.2 V 10 3V 16 2.2 V/3 V 20 UNIT MHz ns 35 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI USCI input clock frequency fmax,BITCLK Maximum BITCLK clock frequency (equals baud rate in MBaud) (1) t UART receive deglitch time (2) (1) (2) CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10% 2.2 V/3 V 2 2.2 V 50 150 3V 50 100 MAX UNIT fSYSTEM MHz MHz ns The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. USCI (SPI Master Mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19 and Figure 20) PARAMETER fUSCI USCI input clock frequency tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time (1) TEST CONDITIONS VCC MIN TYP SMCLK, ACLK Duty cycle = 50% 10% UCLK edge to SIMO valid, CL = 20 pF 2.2 V 110 3V 75 2.2 V 0 3V 0 MAX UNIT fSYSTEM MHz ns ns 2.2 V 30 3V 20 ns fUCxCLK = 1/2tLO/HI with tLO/HI max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. USCI (SPI Slave Mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 21 and Figure 22) PARAMETER TEST CONDITIONS VCC MIN TYP MAX tSTE,LEAD STE lead time, STE low to clock 2.2 V/3 V tSTE,LAG STE lag time, Last clock to STE high 2.2 V/3 V tSTE,ACC STE access time, STE low to SOMI data out 2.2 V/3 V 50 ns tSTE,DIS STE disable time, STE high to SOMI high impedance 2.2 V/3 V 50 ns tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time (1) 36 UCLK edge to SOMI valid, CL = 20 pF 50 UNIT ns 10 2.2 V 20 3V 15 2.2 V 10 3V 10 ns ns ns 2.2 V 75 110 3V 50 75 ns fUCxCLK = 1/2tLO/HI with tLO/HI max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 19. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 20. SPI Master Mode, CKPH = 1 Copyright (c) 2006-2011, Texas Instruments Incorporated 37 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 21. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 22. SPI Slave Mode, CKPH = 1 38 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 23) PARAMETER TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10% MAX UNIT fSYSTEM MHz 400 kHz fUSCI USCI input clock frequency fSCL SCL clock frequency tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.2 V/3 V 0 tSU,DAT Data setup time 2.2 V/3 V 250 ns tSU,STO Setup time for STOP 2.2 V/3 V 4 s tSP Pulse width of spikes suppressed by input filter 2.2 V 50 150 600 3V 50 100 600 2.2 V/3 V fSCL 100 kHz fSCL > 100 kHz fSCL 100 kHz fSCL > 100 kHz tHD,STA 2.2 V/3 V 2.2 V/3 V 0 4 s 0.6 4.7 s 0.6 ns ns tSU,STA tHD,STA SDA 1/fSCL tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 23. I2C Mode Timing Copyright (c) 2006-2011, Texas Instruments Incorporated 39 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS I(DD) CAON = 1, CARSEL = 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P2.3/CA0 and P2.4/CA1 VCC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 71 UNIT A A VIC Common-mode input voltage range CAON = 1 2.2 V/3 V 0 V(Ref025) Voltage at 0.25 VCC node / VCC PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P2.3/CA0 and P2.4/CA1 2.2 V/3 V 0.23 0.24 0.25 V(Ref050) Voltage at 0.5 VCC node / VCC PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P2.3/CA0 and P2.4/CA1 2.2 V/3 V 0.47 0.48 0.5 390 480 540 See Figure 27 and Figure 28 PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P2.3/CA0 and P2.4/CA1, TA = 85C 2.2 V V(RefVT) 3V 400 490 550 V(offset) Offset voltage (2) 2.2 V/3 V -30 30 mV Vhys Input hysteresis 2.2 V/3 V 0 0.7 1.4 mV TA = 25C, Overdrive 10 mV, Without filter: CAF = 0 (3) (see Figure 24 and Figure 25) 2.2 V 80 165 300 3V 70 120 240 TA = 25C, Overdrive 10 mV, With filter: CAF = 1 (3) (see Figure 24 and Figure 25) 2.2 V 1.4 1.9 2.8 3V 0.9 1.5 2.2 t(response) (1) (2) (3) 40 Response time (low-high and high-low) CAON = 1 VCC - 1 V mV ns s The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together. Response time measured at P2.2/CAOUT/TA0/CA4. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com 0V VCC 0 1 CAF CAON To Internal Modules Low-Pass Filter + _ V+ V- 0 0 1 1 CAOUT Set CAIFG Flag 2.0 s Figure 24. Comparator_A+ Module Block Diagram VCAOUT Overdrive V- 400 mV t (response) V+ Figure 25. Overdrive Definition CASHORT CA0 CA1 1 VIN + - Comparator_A+ CASHORT = 1 IOUT = 10A Figure 26. Comparator_A+ Short Resistance Test Condition Copyright (c) 2006-2011, Texas Instruments Incorporated 41 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Typical Characteristics - Comparator_A+ V(RefVT) vs TEMPERATURE VCC = 2.2 V V(RefVT) vs TEMPERATURE VCC = 2.2 V 650 650 VCC = 2.2 V 600 V(REFVT) - Reference Volts - mV V(REFVT) - Reference Volts - mV VCC = 3 V Typical 550 500 450 400 -45 -25 15 55 75 35 -5 TA - Free-Air Temperature - C 600 Typical 550 500 450 400 -45 95 -25 15 55 75 35 -5 TA - Free-Air Temperature - C Figure 27. Figure 28. SHORT RESISTANCE vs VIN/VCC 100 Short Resistance - kW 95 VCC = 1.8 V VCC = 2.2 V VCC = 3 V 10 VCC = 3.6 V 1 0 0.2 0.4 0.6 0.8 1.0 VIN/VCC - Normalized Input Voltage - V/V Figure 29. 42 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC (PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA 10 ms (1) tCPT Cumulative program time tCMErase Cumulative mass erase time 2.2 V/3.6 V 2.2 V/3.6 V 20 ms 104 Program/erase endurance 105 cycles tRetention Data retention duration TJ = 25C tWord Word or byte program time See (2) 30 tFTG tBlock, 0 Block program time for first byte or word See (2) 25 tFTG tBlock, 1-63 Block program time for each additional byte or word See (2) 18 tFTG Block program end-sequence wait time See (2) 6 tFTG Mass erase time See (2) 10593 tFTG See (2) 4819 tFTG tBlock, End tMass Erase tSeg Erase (1) (2) Segment erase time 100 years The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG). RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage (1) TEST CONDITIONS MIN CPU halted MAX UNIT 1.6 V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. JTAG Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTCK TCK input frequency (1) RInternal Internal pulldown resistance on TEST (2) (1) (2) VCC MIN TYP MAX UNIT 2.2 V 0 5 MHz 3V 0 10 MHz 2.2 V/3 V 25 35 55 k MIN MAX fTCK may be restricted to meet the timing requirements of the module selected. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions. JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse blow IFB Supply current into TEST during fuse blow tFB Time to blow fuse (1) TEST CONDITIONS TA = 25C 2.5 6 UNIT V 7 V 100 mA 1 ms After the fuse is blown, no further access to the JTAG/Test and emulation features is possible, and the JTAG block is switched to bypass mode. Copyright (c) 2006-2011, Texas Instruments Incorporated 43 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.7, Input/Output With Schmitt Trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x 44 Interrupt Edge Select Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 18. Port P1 (P1.0 to P1.7) Pin Functions PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TACLK 0 1 2 0 0 1 DVSS 1 1 I: 0, O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0, O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0, O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 I: 0, O: 1 0 1 1 P1.3 (I/O) P1.3/TA2 3 P1.4/SMCLK 4 P1.5/TA0 5 P1.4 (I/O) SMCLK P1.5 (I/O) I: 0, O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.6 (I/O) P1.6/TA1 6 I: 0, O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA1 1 1 P1.7 (I/O) P1.7/TA2 7 P1SEL.x I: 0, O: 1 P1.2 (I/O) P1.2/TA1 P1DIR.x Timer_A3.TACLK P1.1 (I/O) P1.1/TA0 CONTROL BITS / SIGNALS I: 0, O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA2 1 1 Copyright (c) 2006-2011, Texas Instruments Incorporated 45 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.0 to P2.4, Input/Output With Schmitt Trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P2REN.x P2DIR.x 0 Module X OUT 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS 0 1 Bus Keeper EN P2SEL.x P2IN.x P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 EN Module X IN D P2IE.x P2IRQ.x EN Q Set P2IFG.x P2SEL.x P2IES.x 46 Interrupt Edge Select Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 19. Port P2 (P2.0 to P2.4) Pin Functions PIN NAME (P2.x) P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 x 0 1 2 FUNCTION CAPD.x P2DIR.x P2SEL.x P2.0 (I/O) 0 I: 0, O: 1 0 ACLK 0 1 1 CA2 (2) 1 X X P2.1 (I/O) 0 I: 0, O: 1 0 Timer_A3.TAINCLK 0 0 1 DVSS 0 1 1 CA3 (2) 1 X X P2.2 (I/O) 0 I: 0, O: 1 0 CAOUT 0 1 1 TA0 0 0 1 X CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 (1) (2) 3 4 CONTROL BITS / SIGNALS (1) (2) 1 X P2.3 (I/O) 0 I: 0, O: 1 0 CA0 (2) 1 X X Timer_A3.TA1 0 1 1 P2.4 (I/O) 0 I: 0, O: 1 0 CA1 (2) 1 X X Timer_A3.TA2 0 1 1 X = Don't care Setting theCAPD.xbit disables the output driver as well as the input to prevent parasitic cross currentswhenapplying analog signals. Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2006-2011, Texas Instruments Incorporated 47 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CAPD.5 To DCO DCOR in DCO P2REN.5 0 P2DIR.5 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.5 DVSS P2.5/ROSC/CA5 Bus Keeper EN P2SEL.x P2IN.5 EN Module X IN D P2IE.5 P2IRQ.5 EN Q Set P2IFG.5 P2SEL.5 P2IES.5 Interrupt Edge Select Table 20. Port P2 (P2.5) Pin Functions PIN NAME (P2.x) P2.5/ROSC/CA5 (1) (2) 48 x 5 FUNCTION CONTROL BITS / SIGNALS (1) CAPD.5 DCOR P2DIR.5 P2SEL.5 P2.5 (I/O) 0 0 I: 0, O: 1 0 ROSC 0 1 X X DVSS 0 0 1 1 CA5 (2) 1 0 X X X = Don't care Setting theCAPD.xbit disables the output driver as well as the input to prevent parasitic cross currentswhenapplying analog signals. Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger BCSCTL3.LFXT1Sx = 11 P2.7/XOUT/CA7 LFXT1 off 0 LFXT1CLK 1 Pad Logic To Comparator From Comparator CAPD.6 P2SEL.7 P2REN.6 P2DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.6 DVSS P2.6/XIN/CA6 Bus Keeper EN P2SEL.6 P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q Set P2IFG.6 P2SEL.6 P2IES.6 Interrupt Edge Select Copyright (c) 2006-2011, Texas Instruments Incorporated 49 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 21. Port P2 (P2.6) Pin Functions PIN NAME (P2.x) P2.6/XIN/CA6 (1) (2) 50 x 6 FUNCTION CONTROL BITS / SIGNALS (1) CAPD.6 P2DIR.6 P2SEL.6 P2.6 (I/O) 0 I: 0, O: 1 0 XIN (default) X 1 1 CA6 (2) 1 X 0 X = Don't care Setting theCAPD.xbit disables the output driver as well as the input to prevent parasitic cross currentswhenapplying analog signals. Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger BCSCTL3.LFXT1Sx = 11 P2.6/XIN/TA1 LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 Pad Logic To Comparator From Comparator CAPD.7 P2SEL.6 P2REN.7 P2DIR.7 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.7 DVSS P2.7/XOUT Bus Keeper EN P2SEL.7 P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q Set P2IFG.7 P2SEL.7 P2IES.7 Interrupt Edge Select Copyright (c) 2006-2011, Texas Instruments Incorporated 51 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Table 22. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) P2.7/XOUT/CA7 (1) (2) 52 x 7 FUNCTION CONTROL BITS / SIGNALS (1) CAPD.7 P2DIR.7 P2SEL.7 P2.7 (I/O) 0 I: 0, O: 1 0 XOUT (default) X 1 1 CA7 (2) 1 X 0 X = Don't care Setting theCAPD.xbit disables the output driver as well as the input to prevent parasitic cross currentswhenapplying analog signals. Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin, regardless of the state of the associated CAPD.x bit. Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P3 Pin Schematic: P3.0 to P3.5, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 Module direction 1 P3OUT.x 0 Module X OUT DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3SEL.x P3IN.x EN Module X IN D Table 23. Port P3 (P3.0 to P3.5) Pin Functions PIN NAME (P3.x) x P3.0/UCB0STE/ UCA0CLK 0 P3.1/UCB0SIMO/ UCB0SDA 1 P3.2/UCB0SOMI/ UCB0SCL P3.3/UCB0CLK/ UCA0STE P3.4/UCA0TXD/ UCA0SIMO P3.5/UCA0RXD/ UCA0SOMI (1) (2) (3) 2 3 4 5 FUNCTION P3.0 (I/O) UCB0STE/UCA0CLK (2) P3.1 (I/O) UCB0SIMO/UCB0SDA (2) (3) P3.2 (I/O) UCB0SOMI/UCB0SCL (2) (3) P3.3 (I/O) UCB0CLK/UCA0STE (2) P3.4 (I/O) UCA0TXD/UCA0SIMO (2) P3.5 (I/O) UCA0RXD/UCA0SOMI (2) CONTROL BITS / SIGNALS (1) P3DIR.x P3SEL.x I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 X = Don't care The pin direction is controlled by the USCI module. If the I2C functionality is selected, the output drives only the logical 0 to VSS level. Copyright (c) 2006-2011, Texas Instruments Incorporated 53 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P3 Pin Schematic: P3.6 and P3.7, Input/Output With Schmitt Trigger Pad Logic P3REN.x P3DIR.x 0 0 1 P3OUT.x 0 Module X OUT DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.6 P3.7 P3SEL.x P3IN.x EN Module X IN D Table 24. Port P3 (P3.6 and P3.7) Pin Functions PIN NAME (P3.x) x FUNCTION CONTROL BITS / SIGNALS P3DIR.x P3SEL.x P3.6 6 P3.6 (I/O) I: 0, O: 1 0 P3.7 7 P3.7 (I/O) I: 0, O: 1 0 54 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB0 P4.4/TB1 P4.5/TB2 P4.6/TBOUTH/ACLK P4.7/TBCLK/ TBINCLK P4SEL.x P4IN.x EN Module X IN D Table 25. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) x FUNCTION P4.0 (I/O) P4.0/TB0 0 Timer_B3.CCI0A Timer_B3.OUT0 P4.1 (I/O) P4.1/TB1 1 Timer_B3.CCI1A Timer_B3.OUT1 2 3 4 5 P4.7/TBCLK 6 7 1 1 I: 0, O: 1 0 0 1 0 0 1 Timer_B3.OUT2 1 1 I: 0, O: 1 0 Timer_B3.CCI0B 0 1 Timer_B3.OUT0 1 1 I: 0, O: 1 0 Timer_B3.CCI1B 0 1 Timer_B3.OUT1 1 1 I: 0, O: 1 0 N/A 0 1 Timer_B3.OUT2 1 1 I: 0, O: 1 0 Timer_B3.TBOUTH 0 1 ACLK 1 1 I: 0, O: 1 0 0 1 P4.6 (I/O) P4.6/TBOUTH/ACLK 1 Timer_B3.CCI2A P4.5 (I/O) P4.5/TB2 0 0 1 P4.4 (I/O) P4.4/TB1 P4SEL.x 1 P4.3 (I/O) P4.3/TB0 P4DIR.x I: 0, O: 1 I: 0, O: 1 P4.2 (I/O) P4.2/TB2 CONTROL BITS / SIGNALS P4.7 (I/O) Timer_B3.TBCLK Copyright (c) 2006-2011, Texas Instruments Incorporated 55 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger TDO Controlled by JTAG Controlled by JTAG JTAG TDO/TDI Controlled by JTAG DVCC DVCC TDI Fuse Burn & T est Fuse Test and Emulation Module TDI/TCLK DVCC TMS TMS DVCC During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the T est Input Data for JT AG Circuitry TCK TCK 56 Copyright (c) 2006-2011, Texas Instruments Incorporated MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 30). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITEST Figure 30. Fuse Check Mode Current Copyright (c) 2006-2011, Texas Instruments Incorporated 57 MSP430F23x0 SLAS518E - AUGUST 2006 - REVISED AUGUST 2011 www.ti.com REVISION HISTORY LITERATURE NUMBER SUMMARY SLAS518 PRODUCT PREVIEW data sheet release SLAS518A PRODUCTION DATA data sheet release The USCI parameter section was revised, pages 36 to 39. Corrected the port schematics of port P2.6 and P2.7 Added in the DSBGA package version. SLAS518B Corrected WDTIFG description in IFG1 register. Corrected labels in Figure 17 and 18. Corrected test conditions of Comparator_A+ from P1.0, P1.1 to P2.3 and P2.4. Corrected the UART parameters. 58 SLAS518C Release of MSP430F2330IYFF and MSP430F2350IYFF SLAS518D Changed Tstg, Programmed device, to -40C to 150C in Absolute Maximum Ratings. SLAS518E Changed Tstg, Programmed device, to -55C to 150C in Absolute Maximum Ratings. Copyright (c) 2006-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 29-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) MSP430F2330IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2330IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2330IYFFR ACTIVE DSBGA YFF 49 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM MSP430F2330IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM MSP430F2330TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2330TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2350IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2350IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2350IYFFR ACTIVE DSBGA YFF 49 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM MSP430F2350IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM MSP430F2350TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2350TRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2370IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2370IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2370IYFFR ACTIVE DSBGA YFF 49 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM MSP430F2370IYFFT ACTIVE DSBGA YFF 49 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM MSP430F2370TRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) Addendum-Page 1 Samples CU NIPDAU Level-3-260C-168 HR PACKAGE OPTION ADDENDUM www.ti.com Orderable Device MSP430F2370TRHAT 29-Jul-2011 Status (1) ACTIVE Package Type Package Drawing VQFN RHA Pins 40 Package Qty 250 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device MSP430F2370IRHAR Package Package Pins Type Drawing VQFN RHA 40 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 1.1 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F2370IRHAR VQFN RHA 40 2500 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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