Description
The A1220, A1221, A1222, and A1223 Hall-effect sensor ICs
are extremely temperature-stable and stress-resistant devices
especially suited for operation over extended temperature ranges
to 150°C. Superior high-temperature performance is made
possible through dynamic offset cancellation, which reduces the
residual offset voltage normally caused by device overmolding,
temperature dependencies, and thermal stress. Each device
includes on a single silicon chip a voltage regulator, Hall-
voltage generator, small-signal amplifier, chopper stabilization,
Schmitt trigger, and a short-circuit protected open-drain output
to sink up to 25 mA. A south pole of sufficient strength turns
the output on. A north pole of sufficient strength is necessary
to turn the output off.
An onboard regulator permits operation with supply voltages
of 3 to 24 V. The advantage of operating down to 3 V is that
the device can be used in 3-V applications or with additional
external resistance in series with the supply pin for greater
protection against high voltage transient events.
Two package styles provide magnetically optimized packages
for most applications. Package type LH is a modified 3-pin
SOT23W surface mount package while UA is a three-pin ultra-
mini SIP for through hole mounting. Both packages are lead
(Pb) free, with 100% matte tin plated leadframes.
A1220-DS, Rev. 14
Features and Benefits
▪ Symmetrical latch switchpoints
▪ Resistant to physical stress
▪ Superior temperature stability
▪ Output short-circuit protection
▪ Operation from unregulated supply down to 3 V
▪ Reverse battery protection
▪ Solid-state reliability
▪ Small package sizes
Chopper Stabilized Precision Hall Ef fect Latches
Packages:
Functional Block Diagram
Not to scale
A1220, A1221, A1222, and A1223
3-pin SOT23W
(suffix LH)
(A1223)
(A1220, A1221
and A1222)
3-pin SIP (suffix UA)
Regulator
GND
VCC
VOUT
Control
Current Limit
Dynamic Offset
Cancellation
Sample and Hold
To All Subcircuits
Amp
Low-Pass
Filter
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Packing1Mounting Ambient, TABRP (Min) BOP (Max)
A1220ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 85ºC
–40 40
A1220ELHLT-T27-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1220EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1220LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 150ºCA1220LLHLT-T27-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1220LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1221ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 85ºC
–90 90
A1221ELHLT-T27-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1221EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1221LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 150ºCA1221LLHLT-T27-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1221LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1222ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 85ºC
–150 150
A1222ELHLX-T213-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1222EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1222LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 150ºCA1222LLHLX-T213-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1222LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1223ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 85ºC
–180 180
A1223ELHLX-T213-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1223EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1223LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 150ºCA1223LLHLX-T213-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1223LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
1Contact Allegro for additional packing options.
2Available through authorized Allegro distributors only.
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Forward Supply Voltage VCC 26.5 V
Reverse Supply Voltage VRCC –30 V
Output Off Voltage VOUT 26 V
Continuous Output Current IOUT 25 mA
Reverse Output Current IROUT –50 mA
Operating Ambient Temperature TA
Range E –40 to 85 ºC
Range L –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC
Pin-out Diagrams
Terminal List
Name Description Number
Package LH Package UA
VCC Connects power supply to chip 1 1
VOUT Output from circuit 2 3
GND Ground 3 2
1
3
2
GND
VOUT
VCC
Package UAPackage LH
1
2
3
GND
VOUT
VCC
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS Valid valid over full operating voltage and ambient temperature ranges; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.1Max. Unit2
Electrical Characteristics
Forward Supply Voltage VCC Operating, TJ < 165°C 3 – 24 V
Output Leakage Current IOUTOFF VOUT = 24 V, B < BRP ––10μA
Output Saturation Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 185 500 mV
Output Current Limit IOM B > BOP 30 – 60 mA
Power-On Time3tPO
VCC > 3.0 V, B < BRP(min) – 10 G,
B > BOP(max) + 10 G ––25μs
Chopping Frequency fC– 800 – kHz
Output Rise Time3,4 trRL = 820 Ω, CL = 20 pF – 0.2 2 μs
Output Fall Time3,4 tfRL = 820 Ω, CL = 20 pF – 0.1 2 μs
Supply Current ICC(ON) B > BOP
, VCC = 12 V – – 4 mA
ICC(OFF) B < BRP
, VCC = 12 V – – 4 mA
Reverse Supply Current IRCC VRCC = –30 V – – –5 mA
Supply Zener Clamp Voltage VZICC = 5 mA; TA = 25°C 28 – – V
Zener Impedance IZICC = 5 mA; TA = 25°C – 50 – Ω
Magnetic Characteristics
Operate Point BOP
A1220 5 22 40 G
A1221 15 50 90 G
A1222 70 110 150 G
A1223 100 150 180 G
Release Point BRP
A1220 –40 –23 –5 G
A1221 –90 –50 –15 G
A1222 –150 –110 –70 G
A1223 –180 –150 –100 G
Hysteresis BHYS
A1220
(BOP – BRP)
10 45 80 G
A1221 30 100 180 G
A1222 140 220 300 G
A1223 200 300 360 G
1Typical data are are at TA = 25°C and VCC = 12 V, and are for initial design estimations only.
21 G (gauss) = 0.1 mT (millitesla).
3Guaranteed by device design and characterization.
4CL = oscilloscope probe capacitance.
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions Value Units
Package Thermal Resistance RθJA
Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W
Package LH, 2-layer PCB with 0.463 in.
2 of copper area each
side connected by thermal vias 110 ºC/W
Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W
6
7
8
9
2
3
4
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
20 40 60 80 100 120 140 160 180
Maximum Allowable V
CC
(V)
TJ(max) = 165ºC; ICC = ICC(max)
Power Derating Curve
(R
QJA
= 228 ºC/W)
Package LH, 1-layer PCB
(R
QJA
= 110 ºC/W)
Package LH, 2-layer PCB
(R
QJA
= 165 ºC/W)
Package UA, 1-layer PCB
VCC(min)
VCC(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
20 40 60 80 100 120 140 160 180
Temperature (°C)
Power Dissipation, P
D
(mW)
Power Dissipation versus Ambient Temperature
(R
QJA
= 165 ºC/W)
Package UA, 1-layer PCB
(RQJA = 228 ºC/W)
Package LH, 1-layer PCB
(RQJA = 110 ºC/W)
Package LH, 2-layer PCB
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Average Supply Current (On) versus Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
ICC(AV) (mA)
Average Supply Current (On) versus Supply Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2 6 10 14 18 22 26
V
CC
(V)
Icc
(AV)
(mA)
Average Supply Current (Off) versus Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
I
CC(AV)
(mA)
Average Supply Current (Off) versus Supply Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2 6 10 14 18 22 26
V
CC
(V)
Icc
(AV)
(mA)
Saturation Voltage versus Temperature
0
50
100
150
200
250
300
-60 -40 -20 0 20 40 60 80 100 120 140 160
TA (°C)
V
OUT(SAT)
(mV)
2.6V
3.0V
3.8V
4.2V
12V
24V
Saturation Voltage versus Supply Voltage
0
50
100
150
200
250
300
0 2 4 6 8 101214161820222426
V
CC
(V)
V
OUT(SAT)
(mV)
3.0V
3.8V
4.2V
12V
24V
150°C
-40°C
25°C
150°C
-40°C
25°C
150°C
-40°C
25°C
3.0V
3.8V
4.2V
12V
24V
Characteristic Performance
A1220, A1221, A1222, and A1223 Electrical Characteristics
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
150
-40
25
(°C)
150
-40
25
(°C)
150
-40
25
(°C)
Operate Point versus Temperature
0
5
10
15
20
25
30
35
40
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
OP
(G )
3.0
3.8
4.2
12
24
Operate Point versus Supply Voltage
0
5
10
15
20
25
30
35
40
2 6 10 14 18 22 26
V
CC
(V)
B
OP
(G )
Release Point versus Temperature
-40
-35
-30
-25
-20
-15
-10
-5
0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
RP
(G )
3.0
3.8
4.2
12
24
Release Point versus Supply Voltage
-40
-35
-30
-25
-20
-15
-10
-5
0
2 6 10 14 18 22 26
V
CC
(V)
B
RP
(G )
Switchpoint Hysteresis versus Temperature
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
HYS
(G)
3.0
3.8
4.2
12
24
Switchpoint Hysteresis versus Supply Voltage
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
2 6 10 14 18 22 26
V
CC
(V)
B
HYS
(G)
(V)
(V)
(V)
A1220 Magnetic Characteristics
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operate Point versus Temperature
90
80
70
60
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
OP
(G )
Operate Point versus Supply Voltage
90
80
70
60
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
2 6 10 14 18 22 26
V
CC
(V)
B
OP
(G )
Release Point versus Temperature
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
RP
(G )
Release Point versus Supply Voltage
2 6 10 14 18 22 26
V
CC
(V)
B
RP
(G )
Switchpoint Hysteresis versus Temperature
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
HYS
(G)
Switchpoint Hysteresis versus Supply Voltage
2 6 10 14 18 22 26
V
CC
(V)
B
HYS
(G)
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
2.6
12
24
(V)
2.6
12
24
(V)
2.6
12
24
(V)
150
-40
25
(°C)
150
-40
25
(°C)
150
-40
25
(°C)
A1221 Magnetic Characteristics
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operate Point versus Temperature
150
140
130
120
110
100
90
80
70
-70
-80
-90
-100
-110
-120
-130
-140
-150
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
OP
(G )
Operate Point versus Supply Voltage
180
170
160
150
140
130
120
110
100
90
80
70
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
2 6 10 14 18 22 26
V
CC
(V)
B
OP
(G )
Release Point versus Temperature
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
RP
(G )
Release Point versus Supply Voltage
2 6 10 14 18 22 26
V
CC
(V)
B
RP
(G )
Switchpoint Hysteresis versus Temperature
300
280
260
240
220
200
180
160
140
-60 -40 -20 0 20 40 60 80 100 120 140 160
T
A
(°C)
B
HYS
(G)
Switchpoint Hysteresis versus Supply Voltage
2 6 10 14 18 22 26
V
CC
(V)
B
HYS
(G)
300
280
260
240
220
200
180
160
140
2.6
24
(V)
2.6
24
(V)
2.6
24
(V)
150
-40
25
(°C)
150
-40
25
(°C)
150
-40
25
(°C)
A1222 Magnetic Characteristics
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
CBYP
A122x
VOUT
GND
0.1 μF
VCC
Output
RL
VS
Operation
The output of these devices switches low (turns on) when a mag-
netic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see panel A of figure 1). After turn-on, the
output voltage is VOUT(SAT)
. The output transistor is capable of
sinking current up to the short circuit current limit, IOM, which is
a minimum of 30 mA. When the magnetic field is reduced below
the release point, BRP , the device output goes high (turns off).
The difference in the magnetic operate and release points is the
hysteresis, BHYS , of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is BOP, or latched off if
the last crossed switch point is BRP.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an indeterminate output state. The cor-
rect state is attained after the first excursion beyond BOP or BRP
.
Applications
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to reduce both external noise
and noise generated by the chopper stabilization technique. As is
shown in panel B of figure 1, a 0.1 μF capacitor is typical.
Extensive applications information for Hall effect devices is
available in:
• Hall-Effect IC Applications Guide, Application Note 27701
• Guidelines for Designing Subassemblies Using Hall-Effect
Devices, Application Note 27703.1
• Soldering Methods for Allegro’s Products – SMT and Through-
Hole, Application Note 26009
All are provided in Allegro Electronic Data Book, AMS-702, and
the Allegro Web site, www.allegromicro.com.
Figure 1. Switching behavior of latches. In panel A, on the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength,
and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited
when using a circuit such as that shown in panel B.
(A) (B)
Functional Description
BOP
BRP
BHYS
VCC
VOUT
VOUT(SAT)
Switch to Low
Switch to High
B+
B–
V+
0
0
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
Chopper Stabilization Technique
When using Hall effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall ele-
ment. This makes it difficult to process the signal while main-
taining an accurate, reliable output over the specified operating
temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The patented Allegro technique, namely
Dynamic Quadrature Offset Cancellation, removes key sources
of the output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulation-
demodulation process. The undesired offset signal is separated
from the magnetic field-induced signal in the frequency domain,
through modulation. The subsequent demodulation acts as a
modulation process for the offset, causing the magnetic field
induced signal to recover its original spectrum at baseband, while
the dc offset becomes a high-frequency signal. The magnetic
sourced signal then can pass through a low-pass filter, while the
modulated DC offset is suppressed. This configuration is illus-
trated in figure 2.
The chopper stabilization technique uses a 400 kHz high fre-
quency clock. For demodulation process, a sample and hold
technique is used, where the sampling is performed at twice the
chopper frequency (800 kHz). This high-frequency operation
allows a greater sampling rate, which results in higher accuracy
and faster signal-processing capability. This approach desensi-
tizes the chip to the effects of thermal and mechanical stresses,
and produces devices that have extremely stable quiescent Hall
output voltages and precise recoverability after temperature
cycling. This technique is made possible through the use of a
BiCMOS process, which allows the use of low-offset, low-noise
amplifiers in combination with high-density logic integration and
sample-and-hold circuits.
The repeatability of magnetic field-induced switching is affected
slightly by a chopper technique. However, the Allegro high
frequency chopping approach minimizes the affect of jitter and
makes it imperceptible in most applications. Applications that are
more likely to be sensitive to such degradation are those requiring
precise sensing of alternating magnetic fields; for example, speed
sensing of ring-magnet targets. For such applications, Allegro
recommends its digital device families with lower sensitivity
to jitter. For more information on those devices, contact your
Allegro sales representative.
Figure 2. Model of chopper stabilization technique
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, RJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RJC, is relatively
small component of RJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN (1)
T = PD × RJA (2)
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 1.6 mA, and RJA = 165 °C/W, then:
P
D = VCC × ICC = 12 V × 1.6 mA = 19 mW
T = PD × RJA = 19 mW × 165 °C/W = 3°C
T
J = TA + T = 25°C + 3°C = 28°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RJA and TA.
Example: Reliability for VCC at TA =
150°C, package LH, using a
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
RJA
=
228°C/W, TJ(max) =
165°C, VCC(max)
= 24 V, and
ICC(max) = 4 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
Tmax = TJ(max) – TA = 165
°C
–
150
°C = 15
°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax ÷ RJA = 15°C ÷ 228 °C/W = 66 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 66 mW ÷ 4 mA = 16.4 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
and VCC(max) is reliable under these conditions.
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
0.55 REF
Gauge Plane
Seating Plane
0.25 BSC
0.95 BSC
0.95
1.00
0.70 2.40
2
1
AActive Area Depth, 0.28 mm REF
B
C
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branding scale and appearance at supplier discretion
A
PCB Layout Reference View
Branded Face
CStandard Branding Reference View
N = Last two digits of device part number
T = Temperature code (letter)
1
NNT
N = Last three digits of device part number
1
NNN
2.90 +0.10
–0.20
4°±4°
8X 10° REF
0.180+0.020
–0.053
0.05 +0.10
–0.05
0.25 MIN
1.91 +0.19
–0.06
2.98 +0.12
–0.08
1.00 ±0.13
0.40 ±0.10
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
DHall element, not to scale
D
D
D
1.49
0.96
3
Package LH, 3-Pin (SOT-23W)
A1220 and
A1221 only
A1220, A1221,
A1222, and
A1223
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package UA, 3-Pin SIP
(A1220, A1221, and A1222)
231
0.79 REF
1.27 NOM
2.16
MAX
0.51
REF
45°
C
45°
B
E
E
E
2.04
1.44
Gate burr area
A
B
C
Dambar removal protrusion (6X)
A
D
E
D
Branding scale and appearance at supplier discretion
Hall element, not to scale
Active Area Depth, 0.50 mm REF
For Reference Only; not for tooling use (reference DWG-9049)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Standard Branding Reference View
= Supplier emblem
N = Last two digits of device part number
T = Temperature code
NNT
1
Mold Ejector
Pin Indent
Branded
Face
4.09 +0.08
–0.05
0.41 +0.03
–0.06
3.02 +0.08
–0.05
0.43 +0.05
–0.07
15.75 ±0.51
1.52 ±0.05
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package UA, 3-Pin SIP
(A1223)
231
1.27 NOM
1.02
MAX
45°
45°
C
1.52 ±0.05
B
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (6X)
A
D
E
E
E
1.44
2.04
E
Active Area Depth, 0.50 mm REF
Branding scale and appearance at supplier discretion
Hall element (not to scale)
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Mold Ejector
Pin Indent
DStandard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
NNN
1
0.41 +0.03
–0.06
0.43 +0.05
–0.07
14.99 ±0.25
4.09 +0.08
–0.05
3.02 +0.08
–0.05
0.79 REF
10°
Branded
Face
Chopper Stabilized Precision Hall Ef fect Latches
A1220, A1221,
A1222, and A1223
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2009-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Current
Revision Date Description of Revision
Rev. 14 July 12, 2012 Update UA package drawing
