FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
ICS841654I
IDT™ / ICS™ HCSL CLOCK GENERATOR 1 ICS841654AGI REV. A APRIL 17, 2008
GENERAL DESCRIPTION
The ICS841654I is an optimized PCIe and sRIO clock
generator and member of the HiPerClocks™ family
of high-performance clock solutions from IDT. The
device uses a 25MHz parallel crystal to generate
100MHz and 125MHz clock signals, replacing
solutions requiring multiple oscillator and fanout buffer solutions.
The device has excellent phase jitter (< 1ps rms) suitable to clock
components requiring precise and low-jitter PCIe or sRIO or both
clock signals. Designed for telecom, networking and industrial
applications, the ICS841654I can also drive the high-speed sRIO
and PCIe SerDes clock inputs of communication processors,
DSPs, switches and bridges.
FEATURES
• Four differential HCSL clock outputs: configurable for PCIe
(100MHz) and sRIO (100MHz or 125MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• RMS phase jitter at 100MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
BLOCK DIAGRAM PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ICS841654I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
VDD
REF_OUT
GND
QA0
nQA0
VDDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
VDDA
IREF
FSEL0
FSEL1
QB0
nQB0
VDDOB
GND
QB1
nQB1
MR/nOE
VDD
XTAL_IN
XTAL_OUT
GND
0
1
1
0
M = ÷20
÷NA
÷NB
OSC
FemtoClock
PLL
VCO = 500MHz
XTAL_IN
XTAL_OUT
REF_IN
REF_SEL
IREF
BYPASS
FSEL[0:1]
MR/nOE
nREF_OE
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
REF_OUT
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
IDT™ / ICS™ HCSL CLOCK GENERATOR 2 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
81,1V
DD
rewoP.snipylppuseroC
2TUO_FERtuptuO .tuptuokcolcycneuqerfecnereferdedne-elgniS
.slevelecafretniLTTVL/SOMCVL
22,51,7,3DNGrewoP.dnuorgylppusrewoP
,5,4
9,8
,0AQn,0AQ
1AQn,1AQ tupuO .slevelecafretniLSCH.sriaptuptuoAknaBlai
tnereffiD
6V
AODD
rewoP.stuptuoAknaBrofnipylppustuptuO
01EO_FERntupnIpulluP .E3elbaTeeS.elbasid/elbaneTUO_FERwolevitcA
.slevel
ecafretniLTTVL/SOMCVL
11SSAPYBtupnInwodlluP .noitarepossapybLLP/noitarepoLLPstceleS
.slevelecafretniLTTVL/S
OMCVL.C3elbaTeeS
21NI_FERtupnInwodlluP .tupnikcolcecnereferLLPdedne-elgniS
.slevelecafretniLTTVL/SOMCVL
31LES
_FERtupnInwodlluP .ecruosecnerefertupniehtstceleS.tcelesecnerefeR
.slevelecafretniLTTVL/SOMCVL.B3elbaTeeS
41V
ADD
rewoP.nipylppusgolanA
71,61 ,TUO_LATX
NI_LATX tupnI ,tuptuoehtsiTUO_LATX.ecafretnilatsyrctnanoserlellaraP
).
ecnereferLLP(.tupniehtsiNI_LATX
91EOn/RMtupnInwodlluP
,HGIHcigolnehW.elbanetuptuoWOLevitcA.teserretsamHGIH
evitcA
hgihnierastuptuolaitnereffidehtdnatesererasredividlanretnieht
ehtdnasredividlanretnieht,WOLcigol
nehW.)ZiH(ecnadepmi
ecafretniLTTVL/SOMCVL.D3elbaTeeS.delbaneerastuptuolaitnereffid
.slevel
12,02
52,42
1BQ
,1BQn
0BQ,0BQn tuptuO .slevelecafretniLSCH.sriaptuptuoBknaBlaitnereffiD
32V
BODD
rewoP.stuptuoBknaBrofnipylppustuptuO
72,62 ,1LESF
0LESF tupnInwodlluP.slevelecafretniLTTVL/SOMCVL.sniptceles
ycneuqerftuptuO
82FERItuptuO
rotsisernoisicerpdexifA.tuptuorotsiserlanretxeecnerefertnerrucLSCH
574=FERR( Ωdesutnerrucecnereferasedivorpdnuorgotnipsihtmorf)
kcolc]1:0[BQn/]1:0[BQdna]1:0[AQn/]1:0[AQedom-tnerruc
laitnereffidrof
.stuptuo
:ETON
nwodlluPdnapulluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
LLUPPU
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
IDT™ / ICS™ HCSL CLOCK GENERATOR 3 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 3B. REF_SEL FUNCTION TABLE
TABLE 3D. MR/nOE FUNCTION TABLE
TABLE 3C. BYPASS FUNCTION TABLE
tupnI
LES_FERecnerefeRtupnI
0)tluafed(LATX
1NI_FER
tupnI
SSAPYBnoitarugifnoCLLP
1ETON
0)tluafed(noLLP
1)N/ferf=BQ,AQ(dessapybLLP
.noitcnufsuonorhcnysA:1ETON
tupnI
EOn/RMnoitcnuF
1ETON
0)tluafed(delbanestuptuO
1)ecnadepmIhgiH(delbasidstuptuo,tesereciveD
.noitcnufsuonorhcnysA:1ETON
TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ)
TABLE 3E. nREF_OE FUNCTION T ABLE
tupnI
EO_FERnnoitcnuF
1ETON
0delbaneTUO_FER
1)tluafed()ecnadepmIhgiH(delbasidTUO_FER
.noitcnufsuonorhcnysA:1ETON
stupnIsgnitteSycneuqerFstuptuO
1LESF0LESFM 1:0AQn/1:0AQ1:0BQn/1:0BQ
0002)zHM001(5/OCV)tluafed()zHM001(5/OCV
0102)zHM0
01(5/OCV)zHM521(4/OCV
10 02)zHM001(5/OCVH=1:0BQn,L=1:0BQ
1102)zHM521(4/OCV)zHM521(4/OCV
IDT™ / ICS™ HCSL CLOCK GENERATOR 4 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDDOX + 0.5V
Package Thermal Impedance, θJA 64.4°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanAV
DD
02.0–3.3564.3V
V
,AODD
V
BODD
egatloVylppuStuptuO 531.33.3564.3V
I
DD
tnerruCylppuSrewoPdetanimretnU58Am
I
ADD
tnerruCylppuSgolanAdetanimretnU02Am
I
AODD
dna
I
BODD
tnerruCylppuStuptuO574=FERR,detanimretnU Ω%1±5Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
DD
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI
,LES_FER,NI_FER
,EOn/RM,SSAPYB
1LESF,0LESF
V
DD
V=
NI
V564.3=051Aµ
EO_FERnV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI
,LES_FER,NI_FER
,EOn/RM,SSAPYB
1LESF,0LESF
V
DD
V,V564.3=
NI
V0=5-Aµ
EO_FERnV
DD
V,V564.3=
NI
V0=051-Aµ
V
HO
;egatloVhgiHtupuO
1ETON TUO_FERV
DD
V564.3=6.2V
V
LO
;egatloVwoLtupuO
1ETON TUO_FERV
DD
V564.3=5.0V
Z
TUO
ecnadepmItuptuOTUO_FERV
DD
V564.3=02Ω
05htiwdetanimretstuptuO:1ETON ΩVot
DD
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
.margaidtiucriCtseTdaoLtuptuO
IDT™ / ICS™ HCSL CLOCK GENERATOR 5 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 52zHM
)RSE(ecnatsiseRs
eireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
.latsyrctnanoserlellarapFp81nagnisudeziretcarahC:ETON
TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuOTUO_FER52zHM
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%0206.008.1sn
cdoelcyCytuDtuptuO 9415%
TABLE 6B. HCSL AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 5/OCV001zHM
4/OCV521zHM
t
)Ø(tij ;)modnaR(rettiJesahPSMR
1ETON
,zHM001
)zHM02-zHM578.1( 44.0sp
,zHM521
)zHM02-zHM578.1( 44.0sp
t
)cc(tij3ETON;rettiJelcyC-ot-elcyC 53sp
t
)o(ks ;wekStuptuO
3,2ETON
,xAQn/xAQ
xBQn/xBQ 001sp
t
L
emiTkcoLLLP 001sm
V
HGIH
hgiHegatloVzHM521056007059Vm
V
WOL
woLegatloV 051-051Vm
V
SVO
toohsrevO,egatloV.xaM 3.0V
V
SDU
toohsrednU,egatloV.niM 3.0-V
V
br
egatloVkcabgniR 2.0V
V
SSORC
egatloVgnissorCetulosbA 002055Vm
ΔV
SSORC
VfonoitairaVlatoT
SSORC
llarevo
segde 061Vm
t
R
t/
F
emiTllaF/esiRtuptuO ,xAQn/xAQ
xBQn/xBQ
neewtebderusaem
V525.0otV571.0 001007sp
Δt
R
/Δt
F
noitairaVemiTllaF/esiR 521sp
cdoelcyCytuDtuptuO ,xAQn/xAQ
xBQn/xBQ 8425%
.zHM521dnazHM001tanekaterasnoitacifice
psllA:ETON
.tolPesioNesahPehtotreferesaelP:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastupt
uoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
.56dradnatSCEDEJhtiwecnadrocca
nidenifedsiretemarapsihT:3ETON
IDT™ / ICS™ HCSL CLOCK GENERATOR 6 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
OFFSET FREQUENCY (HZ)
➤
➤
➤
dBc
Hz
NOISE POWER
TYPICAL PHASE NOISE AT 100MHZ
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
OFFSET FREQUENCY (HZ)
➤
➤
➤
dBc
Hz
NOISE POWER
Filter
Raw Phase Noise Data
Phase Noise Result by adding
an Filter to raw data
Filter
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
IDT™ / ICS™ HCSL CLOCK GENERATOR 7 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
HCSL OUTPUT LOAD AC TEST CIRCUIT
475Ω
IREF
33Ω50Ω
50Ω
33Ω
49.9Ω
49.9Ω
HCSL
GND
2pF
2pF
Qx
nQx
0V
3.3V±5%
HCSL OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
CYCLE-TO-CYCLE JITTER
475Ω
IREF
50Ω
50Ω
HCSL
GND
0V
SCOPE
3.3V±5%
VDD,
VDDOA,
VDDOB
3.3V±5% 3.3V±5%
VDDA
VDD,
VDDOA,
VDDOB VDDA
SCOPE
Qx
LVCMOS
1.65V±5%
-1.65V±5%
GND
VDD
VDDA
1.65V±5%
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
HCSL OUTPUT SKEW
tsk(o)
Qy
Qx
nQy
nQx
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
nQA[0:1],
nQB[0:1]
QA[0:1],
QB[0:1]
IDT™ / ICS™ HCSL CLOCK GENERATOR 8 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
LVCMOS OUTPUT RISE/FALL TIME
20%
80% 80%
20%
t
R
t
F
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
tPW
REF_OUT
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL T IME
0.175V
0.525V 0.525V
0.175V
t
R
t
F
V
SWING
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD
Q - nQ
0.0V
Clock Period (Differential)
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
SE MEASUREMENT POINTS FOR DELTA CROSS POINT
Q
nQ
V
CROSS_DELTA
= 140mV
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
TSTABLE
V
RB
Q - nQ
-150mV
V
RB
= -100mV
V
RB
= +100mV
+150mV
0.0V
V
RB
TSTABLE
REF_OUT
nQAx,
nQBx
QAx, QBx
IDT™ / ICS™ HCSL CLOCK GENERATOR 9 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING
nQ
Q
V
CROSS_MAX
= 550mV
V
CROSS_MIN
= 250mV
V
MAX
= 1.15V
V
MIN
= -0.30V
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS841654I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, VDDOA and
VDDOB should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be
used for each pin.
Figure 1
illustrates this for a generic VDD pin
and also shows that VDDA requires that an additional10Ω
resistor along with a 10µF bypass capacitor be connected to
the VDDA pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V
.01μF
VDD
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HCSL OUTPUTS
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS OUTPUT
The unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
IDT™ / ICS™ HCSL CLOCK GENERATOR 10 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS841654I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2
below
FIGURE 2. CRYSTAL INPUt INTERFACE
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in
Figure 3.
The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTA L_I N
XTA L_O U T
VCC
R2
Ro
R1
Zo = 50
Rs
VCC
.1uf
VDD VDD
Zo = Ro + Rs
IDT™ / ICS™ HCSL CLOCK GENERATOR 11 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
SCHEMATIC LAYOUT
Figure 4
shows an example of ICS841654I application
schematic. In this example, the device is operated at VCC =
3.3V. The 18pF parallel resonant 25MHz crystal is used.
The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layout, the C1 and
FIGURE 4. ICS841654I SCHEMATIC LAYO U T
nREF_OE
TL3
Zo = 50
+
-
RU2
Not Install
R8
10
R4
475
TL5
Zo = 50
C8
.1uf
Zo = 50
R5 33
VDDOA=3.3V
VDD
C4
27pF
VDDOB=3.3V
MR / nO E
VDD
VCC OA
C2
10u
+
-
VDD OA
R12
50
LVCMOS
X1
25MHz
RD2
1K
R1 33
To Logic
Input
pins
C1
0.1u
VDD
C5
0.1u
VDDA
VDD
R7
50
C6
0.1u
Set Logic
Input to
'0'
BYPASS
Logic Control Input Examples
R13
50
Using for PCI Express
Add-In Card
To Logic
Input
pins
R2 33
RD1
Not Install
VDD=3.3V
VDD
VCCOB
C7
.1uf
REF_SEL
R6
50
VDD OB
U1
ICS841654I
1
2
3
4
5
14
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
12
13
28
27
26
25
VDD
REF_OUT
GND
QA0
nQA0
VDDA
VDDOA
GND
QA1
nQA1
nREF _OE
BYPASS
GND
XT A L _O U T
XT A L _I N
VDD
MR / nO E
nQB1
QB1
GND
VDDOB
nQB0
REF_IN
REF_SEL
IREF
FSEL0
FSEL1
QB0
TL2
Zo = 50
C3
27pF
Set Logic
Input to
'1'
VDD
TL4
Zo = 50
FSEL0
18pF
HCSL Termination
FSEL1
REF_OUT
VDD
VDD
RU1
1K
Using for PCI Express
Point-to-Point
Connection
C2 may be slightly adjusted for optimizing frequency
accuracy. One example of HCSL and one example of
LVCMOS terminations are shown in this schematic. The
decoupling capacitors should be located as close as possible
to the power pin.
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS841654I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS841654I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 85mA = 294.5mW
•Power (outputs)MAX = 50.06mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 50.06mW = 200.24mW
Total Power_MAX (3.465V, with all outputs switching) = 294.5mW + 200.24mW = 494.74mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.495W * 64.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θθ
θθ
θJA FOR 28-LEAD TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 60.4°C/W 58.5°C/W
IDT™ / ICS™ HCSL CLOCK GENERATOR 13 ICS841654AGI REV. A APRIL 17, 2008
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in
Figure 4.
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD is HIGH.
Power = (VDD_HIGH – VOUT
) * IOUT, since VOUT = IOUT * RL
= (VDD_HIGH – IOUT *
RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 50.06mW
FIGURE 4. HCSL DRIVER CIRCUIT AND TERMINATION
V
DD
V
OUT
R
L
50Ω
IC
➤
I
OUT = 17mA
R
REF =
475
Ω
± 1%
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ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
RECOMMENDED T ERMINATION
Figure 5A
is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
FIGURE 5A. RECOMMENDED TERMINATION
Figure 5B
is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50Ω impedance.
FIGURE 5B. RECOMMENDED TERMINATION
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS841654I is: 2954
TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 60.4°C/W 58.5°C/W
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N82
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D06.908.9
ECISAB01.8
1E00.602.6
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
IDT™ / ICS™ HCSL CLOCK GENERATOR 16 ICS841654AGI REV. A APRIL 17, 2008
ICS841654I
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TABLE 10. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
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www.IDT.com
For Sales
800-345-7015 (inside USA)
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Fax: 408-284-2775
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Corporate Headquarters
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6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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