September 1998 1/78
Rev. 2.4
ST62T80B/E80B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
■3.0 t o 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +85°C Operating Temperature Range
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 192 bytes
■Data EEPRO M: 128 by tes
■User Program mab le Options
■22 I/ O pi ns, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt genera tion
– Open-drain or push-pull output
– Analog Input
■10 I /O lines can sink up to 20m A t o d r ive LEDs
or TRIACs directly
■One 8-bit Timer/Counter with 7-bit
programmable prescaler
■One 8-bit Auto-Reload Timer with 7-bit
programmable prescaler (ARTimer)
■Digital Watchdog
■8-bit A/D Converter with 12 analog inputs
■8-bit Synchronous Peripheral Interface (SPI)
■8-bit Asynchronous Peripheral Interface (UART)
■LCD driver with 48 segment outputs, 8
backplane outputs, 8 software selectable
segment/backplane outputs and selectable
multipl exing ratio.
■32 kHz osc illator fo r sta n d- by LC D ope r a tio n
■On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
■One ex ternal Non-Maskable Interrupt
■ST6280-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE OTP
(Bytes) EPROM
(Bytes) LCD displ ay
ST62T80B 7948 - 4 x 56 or 16 x 48
ST62E80B 7948 4 x 56 or 16 x 48
(See end of Datasheet for Ordering Information)
PQFP100
CQFP100W
1047
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Table of Conten ts
78
Document
Page
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ST62T80B/E80B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.6 Data RAM/EEPROM and LCD RAM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . 12
1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 CLOCKS, RESET, INTERRUPTS AND PO WER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 32kHz STAND-BY OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 RESET In put . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Digital Watchdog Regist er (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2 Interrupt Proc edure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.1 W AIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.2 ST OP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.3 Exit from W AIT and STO P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.3 ARTimer alternate fu nction s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.4 SPI alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.5 UART alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.6 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.7 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.8 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.1 Timer O perating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.2 Timer O perating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 49
4.4.1 PORTS INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.2 CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.3 DATA TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.4 DATA RECEPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.5 INTERRUPT CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.6 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.7 LCD CONTROLLER-DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.7.1 Multipl exing ratio and frame frequen cy setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.7.2 Segm ent and co mmon plates driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.7.3 Stand by or STOP operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.7.4 L CD Mode Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.2 RECO MMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4 AC ELECTRICAL CHARACTERISTI CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.7 SPI CHARACTERIST ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.8 LCD ELECTRICAL CHARACTERIS TICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2 PACKAGE THERMAL CHARACTERISTIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
S T6280B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3 O RDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.1 Transfe r of Cu stomer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.2 Listin g Generation and Verificati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5/78
ST62T80B/E80B
1 G ENERAL DESCR IPTION
1.1 INTRODUCTION
The ST62T80B and ST62E80B devices are low
cost members o f the ST62xx 8-bit HCMOS fami ly
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx d evices
are based on a building block approach: a com-
mon core is surrounded by a number of on-chip
peripherals.
The ST62E80B is the erasable EPROM version of
the ST62T80B d evice, whi ch m ay be used to em-
ulate the ST62T80B devi ce, as well as the respec-
tive ST6280B ROM devices.
Figure 1 . Blo ck D ia gra m
TEST
NMI INTERRUPT
PROGRAM
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY OS CILLATOR RESET
DAT A ROM
USER
SELECTABLE
DAT A RAM
PORT A
PORT B
ARTIMER
DIGITAL
8 BIT CORE
TEST/VPP
8-BIT
A/D CONVERTER PA5 / Scl / 20mA Sink
VDDVSS OSCin OSCout RESET
WATCHDOG
Memory PO RT C
SPI (SERIAL
PERIPHERAL
INTERFACE)
192 Bytes
7948 bytes
DATA EEPR OM
128 By te s
PB0 / RXD / Ain
PC0..PC3 / 20mA Sink
S9..S56
COM9..COM16 / S1..S8
(VPP on EPROM/OT P versions only)
PB6 / ARTIMin / Ain
PB7 / ARTIMout / Ain
VLCD
VLCD1/5
VLCD2/5
OSC 32 kH z
TIMER
OSC32in
OSC32out
LCD DRIVER
VA0479
VLCD4/5
VLCD3/5
PC4..PC7 / Ain
PA6 / Sin / 20mA Sink
PA7 / Sout / 20mA Sink
PA4 / TIMER / 20mA Sink
PA2..PA3 / 20mA Sink
PB2..PB5 / Ain
PB1 / TXD / Ain
COM1..COM8
UART
1051
6/78
ST62T80B/E80B
INTRODUCTION ( Con t’ d)
OTP and EPROM devices are functionally identi-
cal. The RO M based versions offer the same func-
tionality selecting as ROM op tions the opt ions de-
fined in the programmable option byte of the
OTP/EPROM versions.OTP devices offer all the
advantages of user programmability at low cost,
which make them the ideal choic e in a wide range
of applications where frequent code changes, mul-
tiple code versions or last m inute p ro grammabi lity
are required.
These compact low-c ost devi ces feature one Tim-
er comprising an 8-bit counter and a 7-bit pro-
grammable prescaler, one 8-bit autoreload timer
with 7-bit programmable prescaler (ARTimer),
EEPROM data capability, a serial synchronous
port interface (SPI), an 8-bit A/ D Converter wi th 12
analog inputs, a Digital Watchdog timer, and a
complete L CD controller driver, m aking them well
suited for a wide range of automotive, appliance
and industrial applications.
Figure 2. ST6280B Pin Descrip tion
*Note: 20mA Sink
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
71
10099989796959493929190898887868584838281
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
COM16/S8
COM15/S7
COM14/S6
COM13/S5
COM12/S4
COM11/S3
COM10/S2
COM9/S1
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
OSC32in
OSC32out
PA2*
PA3*
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
PB6/ARTIMin/Ain
PB5/Ain
PB4/Ain
PB7/ARTIMout/Ain
PB3/Ain
PB2/Ain
PB1/Ain
PB0/Ain
TEST
OSCout
OSCin
RESET
PC7/Ain
PC6/Ain
PC5/Ain
PC4/Ain
PC3*
PC2*
PC1*
PC0*
NMI
VDD
VSS
VLCD
VLCD4/5
VLCD3/5
VLCD2/5
VLCD1/5
PA7/Sout*
PA6/Sin*
PA5/SCL*
PA4/TIM1
1052
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ST62T80B/E80B
1.2 PIN DESCRIPTIONS
VDD and VSS. Power is supplied to the MCU via
these two pins. VDD is the power connection and
VSS is the ground connection.
OSCin and OSCout. These pins are internally
connected to the on-chip osc illator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be con nected between these two pins.
The OS Cin pin is the input pin, the O SCout pin is
the output pin.
RESET. The active-low RESET pin is used to re-
start the microcon troller.
TEST/VPP. The TEST m ust be held a t VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the
EPROM/OT P programm ing M ode is entered.
NMI. The NMI pin provides t he capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive with Schmitt trigger charac-
teristics. The user c an s elect as option the avail a-
bility o f an o n- c hip pu ll -u p at thi s pin.
PA2-PA7. These 6 lines are organised as one I /O
port (A). Each line may be configure d under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs,
PA5/SCL, PA6/ Sin a nd P A 7/Sout c an be us ed re-
spectively as data clock, data in and cl ock pins for
the on-chip SPI, while PA4/TIMER can be used as
Timer I/O. In addition, PA2-P A7 can sink 20mA for
direct LED or TRIAC dri ve.
PB0...PB7. These 8 lines are organised as one I/O
port (B). Each line may be configure d under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, an-
alog inputs for the A/D converter. PB6/ARTIMin
and PB7/ARTI Mout are either P ort B I/O bits or the
input and out put of th e AR Timer. P B0 (resp. PB1)
can also be used as reception (resp. transmission)
line for the embedded UART.
PC0-PC7. These 8 lin es are organised as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resi stor, interrupt generating input with pull-up
resistor, open-drain or push-pull output, or analog
imputs for the A/D Converter. PC0-PC3 can sink
20mA for direct LED or TRIAC drive, while PC4-
PC7 can be used as analog inputs for the A/D
Converter.
COM1-COM8. These eight pins are the LCD pe-
ripheral comm on outputs. They are t he outputs of
the on-chip backplane voltage generator which is
used for multiplexing the LCD lines.
COM9/S1-COM16/S8. T hese pins are the 8 multi-
plexed common/segment lines. Under software
selected control, they can act as LCD common
outputs al lowing a 48 x 16 dot matrix operation, or
they can ac t as segm ent outputs alowwing 56 x 8
dot matrix operation.
S9-S56. These pins are the 48 LCD peripheral
segment outputs.
VLCD1/5, VLCD5/5 . Display supply voltage input s
for determining the display voltage levels on
common a nd segme nt pins during multiplex oper-
ation.
OSC32in and OSC32out. These pins are inter-
nally connected with the on-chip 32kHz oscillator
circuit. A 32.768kHz quartz crystal can be con-
nected between these two pins if it is necessary to
provide the LCD s tand-by clock and real time i nter-
rupt. OSC32in is the input pin, OSC32out is the
output pin.
1053
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ST62T80B/E80B
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three m emory spaces is
described in the following paragraph s.
Briefly, Program space contains user program
code in Program memory and user vectors; Data
space conta ins user data in R AM and in Program
memory, and S ta ck space acc om m odates six lev-
els of stack for subroutine and interrupt service
routine nest ing.
1.3.2 Program Sp ace
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the us er vectors. Program Space is
addressed via the 12-bit Program Counter regi ster
(PC register).
Program Space is organised in four 2K pages.
Three of them are addressed in the 000h-7FFh lo-
cations of the Program Space by the Program
Counter and by writing the appropriate code in the
Program ROM Page Register (PRPR register). A
common (STATIC) 2K page is available all the
time for interrupt vectors and common subrou-
tines, independently of the PRPR register content.
This “STATIC” page is directly addressed in the
0800h-0FFFh by the MSB of the Program Counter
register PC 11. Note this page can also be ad-
dressed in the 000-7FFh range. It is two different
ways of addressing the same physical memo ry.
Jump from a dynamic page to another dynamic
page is achieved by jumping back to the static
page, changi ng cont ent s of PRP R and t hen jump-
ing to the new dynamic page.
Figure 3. 8Kbytes Program Space Add ressing
Figure 4. Me m ory A d dre ssing D iag ram
PC
SPACE
000h
7FFh
800h
FFFh
0000h 1FFFh
Page 0 Page 1
Static
Page Page 2 Page 3
Page 1
Static
Page
ROM SPACE
PROG RAM SPAC E
PROGRAM
INTERRUPT &
RESET VECTORS ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA READ-ONLY
WINDOW
RAM / EEPROM
BANKING AREA
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
0-63
DATA SPAC E
0000h
0FF0h
0FFFh
MEMORY MEMORY
DATA READ-ONLY
MEMORY
VR01568
1054
9/78
ST62T80B/E80B
MEMORY MA P (Cont’d)
Table 1. ST62E80B/T80B Program Memory Map
Note: OTP/EPROM devices can be programmed
with the development tools available from STMicro-
ele c tronics (ST 6 2E 8X- EPB).
1.3.2.1 Program ROM Pag e Register (PRPR)
The PRPR register can be addressed like a RAM
location in the Data Space at the address CAh ;
nevertheless it is a write only register that cannot
be accessed with single-bit operations. This regis-
ter is us ed to selec t the 2-Kbyte ROM bank of the
Program Space that will be addressed. The
number of the page has to be l oaded in the PRPR
register. Refer to the Program Space description
for additional information concerning the use of
this register. The PRPR register is not modified
when an interrupt or a s ubrou tine occurs.
Care is required when handling the PRPR register
as it is write only. For this reason, it is not allowed
to change the PRPR contents while executing in-
terrupt service routine, as the service routine
cannot save and then restore its previous cont ent.
This operation may be necessary if common rou-
tines and i nterrupt service routines t ake more than
2K bytes ; in this case it could be necessary to di-
vide the interrupt service routine into a (minor) part
in the static page (start and end) and to a second
(major) part in one of the dynamic pages. If it is im-
possible to avoid the writing of this register in inter-
rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRP R it must write also
to the image register. The im age register must be
written before PRPR, so if an interrpt occurs be-
tween the two instructions the PRPR is not af-
fected.
Program ROM Page Register (PRPR)
Address: CAh — Write Only
Bits 2-7= Not u sed.
Bit 5-0 = PRPR1-PRPR0:
Program ROM Select.
These two bits select the corresponding page to
be addres sed in the lower part of the 4K program
address spac e as specified in Tab le 2.
This register is undefined on Reset. Neither read
nor single bi t ins tructions m ay be used to address
this register.
Table 2. 8Kbytes Program ROM Page Register
Coding
1.3.2.2 Prog ram Memory Protec tion
The Program Mem ory in OTP or EPR OM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protect ion is activated, it
is no longer possible, even for STM icroelect roni cs,
to gain access to the Program memory contents.
Returned p arts with a protec tion set can t heref ore
not be accepted.
ROM Page Device Address Description
Page 0 0000h-007Fh
0080h-07FFh Reserved
User ROM
Page 1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vecto r
Page 2 0000h-000Fh
0010h-07FFh Reserved
User ROM
Page 3 0000h-000Fh
0010h-07FFh Reserved
User ROM
70
------PRPR0PRPR1
PRPR1 PRPR0 PC bit 11 Memory Page
X X 1 Static Page (Page 1)
0 0 0 Page 0
0 1 0 Page 1 (Static Page
1 0 0 Page 2
1 1 0 Page 3
1055
10/78
ST62T80B/E80B
MEMORY MA P (Cont’d)
1.3.3 Data Space
Data Space accommodates all t he data necessary
for processi ng the user program. This space com-
prises the RAM resource, the proc essor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in Program
memory.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code t o be execut ed, as wel l as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in Program memo ry.
1.3.3.2 Data RAM/E EPRO M
In ST62T80B and ST62E80B devices, the data
space includes 60 by tes of RAM, the accumu lator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe-
ripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).
Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located be-
tween addresse s 00h and 3Fh.
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 3. Additional RAM /EEPROM Banks.
Table 4. ST62T80B/E 80B Data Memory Space
Device RAM EEPROM LCD RAM
ST62T80B/E80B 2 x 64 bytes 2 x 64 bytes 2 x 64 bytes
DATA RAM/EEPROM, LCD RAM 000h
03Fh
DATA ROM WINDOW AREA 040h
07Fh
X R EGISTE R 080h
Y R EGISTE R 081h
V R EGISTE R 082h
W REGISTER 08 3h
DATA RAM 084h
0BFh
PORT A DATA REGISTER 0C0h
PORT B DATA REGISTER 0C1h
SPI INTERRUP T DISABLE REGISTER 0C2h
PORT C DATA REGISTER 0C3h
PORT A DIRECTION REGISTER 0C4h
PORT B DIRECTION REGISTER 0C5h
PORT C DIRE CT ION REGISTER 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h*
DATA ROM WINDOW REGIST ER 0C9h*
ROM BANK SELECT REGISTER 0CAh*
DATA RAM/EEPROM, LCD BANK SELECT REGISTER 0CBh*
PORT A OPTION REGISTER 0CCh
RESERVED 0CDh
PORT B OPTION REGISTER 0CEh
PORT C O PTION REGISTER 0 CF h
A /D CONTRO L REGI STER 0D0h
A/D D ATA REGISTER 0D1h
TIMER 1 PRESCALER RE G I ST ER 0D2h
TI M ER 1 COUNTER REGIS T E R 0D3h
TIMER 1 STATUS/CONTROL REGISTER 0D4h
RESERVED 0D5h
UART DATA RE GIST ER 0 D6h
UART CO NT ROL REGISTER 0D7h
WAT CHDOG RE GISTER 0D8h
RESERVED 0D9h
0DAh
32kHz OSCILLATOR CONTROL REGISTER 0DBh
L CD MODE CONTRO L RE G ISTE R 0 DCh*
SPI DATA REGISTER 0D Dh
RESERVED 0DEh
EEPROM CONTROL REGISTER 0DFh
RESERVED 0E0h
0E4h
ARTIMER M ODE/CON T ROL REGISTER 0E5h
ARTIMER STATUS/CONTR O L REGIST ER 0 0E6 h
ARTIMER STATUS/CONTR O L REGIST ER 1 0E7 h
RESERVED
ARTIMER RELOAD/CAPTURE REGISTER 0E9h
ARTIMER COMPARE REGISTER 0EAh
ARTIMER LOAD REGISTER 0EBh
RESERVED 0ECh
0FEh
ACCUMULATOR OFFh
* WRI T E ONLY RE GI STER
1056
11/78
ST62T80B/E80B
MEMORY MA P (Cont’d)
1.3.5 Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 1FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved i n steps of 64 byt es along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM locat ion
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is us ed to positi on the
64-byte read-only data win dow (from add re ss 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte t o b e read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the inst ruction
(as least significant bits) and the content of the
DWR register (as mos t significant bit s), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space , with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
writ ten to prior to the first access to the Data read-
only memory window area.
Data Wi ndow Reg iste r (DWR)
Address: 0C9h — W rite Only
Bits 6, 7 = Not used .
Bit 5-0 = DWR5-DWR0:
Data read-only memory
Window Register Bits.
These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution:
This register is u ndefined on reset. Nei-
ther read nor single bit i ns tructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine c annot save and then rest ore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an ima ge of the regi ster m ust be saved i n a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image r egister must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only mem ory Window Memo ry Add ressing
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DAT A ROM
WINDOW REGISTER
CONTENTS D ATA SPACE ADDRESS
40h-7Fh
IN INSTRUCTION
PROG RAM SPACE AD DRESS
765432 0
543210
543210
READ
1
67891011
01
VR0A1573
12
1
0DATA SPAC E ADDRESS
59h
0000
01001
11
Example:
(DWR)
DWR=28h
1100000 0001
ROM
ADDRESS:A19h 11
13
01
1057
12/78
ST62T80B/E80B
MEMORY MA P (Cont’d)
1.3.6 Data RAM/EEPROM and LCD RAM Bank
Register (DRBR)
Address: CBh — Writ e only
Bit 7 = This bit is not used
Bit 6 - DRBR6. This bit, when set, selects LCD
RAM Page 1.
Bit 5 - DRBR5. This bit, when set, selects LCD
RAM Page 2.
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM
Page 1.
Bit2. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1 .
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0 .
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address CBh of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR reg ister can be addressed l ike a RAM
Data Space at the address CBh; nevertheless it is
a write only register that canno t be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The number of banks has to be load-
ed in the DRBR register and the instruction has to
point to the s elected locat ion a s if it was in bank 0
(from 00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefo re it m ust be wri tten be fore the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occu rs.
Notes :
Care is required when handling the DRBR regis ter
as it is write only. For this reason, it is not allo wed
to chan ge the DRBR con tents while ex ecuting in-
terrupt service routine, as the s ervice rou tine c an-
not save and then restore its previous content. If it
is impossibl e t o avoid the writing of this registe r in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing er rors.
Table 5. Data RAM Bank Register Set-up
70
- DRBR6 DRBR5 DRBR4 DRBR3 - DRBR1 DRBR0
DRBR ST62T80B/E80B
00 None
01 EEPROM Page 0
02 EEPROM Page 1
08 RAM Page 1
10h RAM Page 2
20h LCD RAM Page 1
40h LCD RAM Page 2
other Reserved
1058
13/78
ST62T80B/E80B
MEMORY MA P (Cont’d)
1.3.7 EEPRO M Descr iption
EEPROM memory is located in 64-byte pages in
data space. This memory m ay be used by the user
program for non-volatile data storage.
Data space from 00h to 3Fh is paged as described
in Table 6. EEPROM locations are accessed di-
rectly by addressing these paged sections of data
space.
The EEPROM does not requi re dedicat ed in struc-
tions for read or write access. Once selected via the
Data RAM Bank Register, the active EEPROM
page is contr olled by the EEPROM Control Regis-
ter (EECT L), which is described below.
Bit E20FF of the EECTL register must be reset prior
to any write or read access t o the E EPRO M . If no
bank has been selected, or if E2OFF is set, any ac-
cess is mean ingle ss.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
Any access to the E EPR OM w hen E2B USY is s et
is meaningless.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM location is read just like any other data loca-
tion, also in te rms of access time.
Writing to the EE PR OM ma y b e carried ou t in two
modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse-
quent speed and power consumption advant ages,
the latter being particularly important in battery
powered ci rcuits).
General N otes:
Data should be written directly to the intended ad-
dress in EEPROM space. There is no buffer mem-
ory bet ween dat a RAM and the EEPROM space.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to rea d the status of E2BUSY. This
implies that as l ong as th e EEPROM is busy, it is
not possible to c hange the status of the EEP ROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Care is required when dealing with t he EECTL reg-
ister, as some bits are write only. For this reason,
the EECTL c ontents m ust no t be altered while ex-
ecuting an interrupt service routine.
If it is impossible to avoid writing to this register
within an interrupt service routine, an imag e of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to t he image register. The image register
must be written to first so that, if an interrupt oc-
curs be tween t he two in structions, the E E CTL wi ll
not be affected.
Ta bl e 6. . Row Arr ang ement for Para llel Wr iting of EEPROM Location s
Dataspace
addresses.
Banks 0 and 1.
Byte01234567
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
1059
14/78
ST62T80B/E80B
MEMORY MA P (Cont’d)
Additional Notes on Parallel Mode:
If the user wishes to perform parallel program-
ming, the first step should be to set the E2PAR2
bit. From this time on, the EEPROM will be ad-
dressed in write mode, the ROW address will be
latched an d it w ill be po ssible to change it onl y at
the end of the programming cycle, or by resetting
E2PAR2 without programming the EEPROM. Af-
ter the ROW addres s is latched, the MCU can only
“see” the selected EEPROM row and any attempt
to write or read other rows will produc e errors.
The EEPROM should not be read while E2PAR2
is set.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
the user can load dat a in all or in part of the ROW.
Setting E2PAR1 will modify the EEPROM regis-
ters corresponding to the ROW latches accessed
after E2PAR2. For example, if the software sets
E2PAR2 and accesses the EEPROM by wr iti n g t o
addresses 18h, 1Ah and 1Bh, and then sets
E2PAR1, thes e three registers will be modified si-
multaneously; the remaining bytes in the row will
be unaff ected.
Note that E2PAR2 is internally reset at the end of
the programming cycle. This implies that the user
must set the E2P AR2 bit between two par allel pro-
gramming cycles. Note that if the user tries to set
E2PAR1 whi le E2PAR2 is not set, there will be no
programming cycle and t he E2PAR1 bi t will be un-
affected. Consequently, the E2PAR1 bit cannot be
set if E2ENA is low. The E2PAR1 bit can be set by
the user, only if the E2ENA and E2PAR2 bits a re
also set.
EEPROM Control Register (EECTL)
Address: DFh — Read/Write
Reset status: 00h
Bit 7 = D7:
Unused .
Bit 6 = E2OFF:
Stand-by Enable Bit.
WRITE ONLY.
If this bit is set the EEPROM is disabled (any access
will be meaningless) and the power consumption of
the EEPR O M is reduced to it s lowest value.
Bit 5-4 = D5-D4:
Reserved.
MUST be kept reset.
Bit 3 = E2PAR1:
Parallel Start Bit.
WRITE ONL Y.
Once in Parallel Mode, as soon as the user software
sets the E2PAR1 bit, parallel writing of the 8 adja-
cent registers will start. This bit is internally reset at
the end of the program ming procedure. Note that
less than 8 bytes can be written if required, the un-
defined bytes being unaffected by the parallel pro-
gramming cycle; this is explained in greater detail in
the Additional Notes on Parallel Mode overleaf .
Bit 2 = E2PAR2:
Parallel Mode En. Bit.
WRITE
ONLY. This bit must be set by the user program i n
order to perform parallel programming. If E2PAR2
is set and the parallel start bit (E2PAR1) is reset,
up to 8 adjacent bytes can be written simultane-
ously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2, A1 and A0 are the changing bits, as
illustrated in T able 6. E2PAR2 i s aut om atically re-
set at the end of any parallel programm ing proce-
dure. It can be reset by the user software before
starting the progra mming procedure, thus leaving
the EEPRO M regi sters u n changed.
Bit 1 = E2BUSY:
EEPROM Busy Bit.
READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-
ming mode. The user program should test it before
any EEPROM read or write operat ion; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
pro gr es s w ill b e c o mplet ed .
Bit 0 = E2ENA:
EEPROM En a ble Bit.
WRITE ON-
LY. This bit enables programming of t he EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2E NA is low is mean ingless and will
not trigger a write cycle.
70
D7 E2OFF D5 D4 E2PAR1 E2PAR2 E2BUSY E2ENA
1060
15/78
ST62T80B/E80B
1.4 PROGRAMMING MODES
1.4.1 Option Byte
The Op tion Byte allows configuration c apabilit y to
the MCUs. Option byte’s content is automatically
read, and the selec ted options enabl ed, when the
chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
The option byte is located in a non-user map. No
address has to be specified.
EPROM Code Option Byte
Bit 7-5. Reserved.
Bi t 5= PROTECT. This bit allows the protection of
the software contents against piracy. When the bit
PROTECT is set high, readout of the OTP con-
tents is prevented by ha rdware. No pro gramming
equipment is able to gain access to the user pro-
gram. When this bit is low, the user program can
be read.
Bi t 4 . Reserved.
Bit 3 = NMI PULL. . This bit must be set high to en-
able the internal pull-up resistor. When low, no
pull-up is provided.
Bi t 2 . Reserved.
Bit 1 = WDACT. This bit c ontrols t he watchdog ac-
tivation. When it is high, hardware activation is se-
lected. The software activation is selected when
WDACT is low.
Bit 0 = Reserved.
The Opt ion byte is written during program m ing e i-
ther by using the PC menu (PC driven Mode) or
automaticall y (stand-alone mode)
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/VPP pin. The
programming flow of the ST62T80B/E80B is de-
scribed in the User Manual of the EPROM Pro-
gramm ing Board.
The MCUs can be programmed with the
ST62E8xB EPROM programming tools available
from STMicr oelectr onics.
1.4.3 EEP ROM Data Memory
EEPROM data pages are supplied in the virgin
state FFh. Partial or total programming of EEP-
ROM data memory can be performed either
through the applicat ion software, or through an ex-
ternal programmer. Any STMicroelectronics tool
used for the program me mory (OT P /EPROM ) c an
al so be u se d to progra m the EEPR O M d at a me m-
ory.
1.4.4 EPROM Erasing
The EPROM of the windowed package of the
MCUs m ay be erased b y exposure to Ul tra V iolet
light. The erasure characteristic of the MCUs is
such that erasure begins when the mem ory is ex-
posed to light with a wave lengths shorter than ap-
proximately 4000Å. It should be noted that sun-
lights and some types of fluorescent lamps have
wavelength s in the range 3000-4000Å.
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unint ent ional er asur e problem s when test-
ing the application in such an environment .
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul-
traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 15W-
sec/cm2. T he eras ure tim e wi th t his do sage i s ap-
proximately 15 to 20 minutes using an ultraviolet
lamp with 12000µW/cm2 power rating. The
ST62E80 B should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.
70
--
PRO-
TECT -NMI
PULL -WDACT-
1061
16/78
ST62T80B/E80B
2 CE NTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via t he serial data bus and indirectly, for
interrupt purposes, through the control registers.
2.2 CPU REGIST ERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraph s.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The a ccumula tor can be ad dressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Indirect Re gisters (X, Y). These t wo indi rect reg-
isters are used as pointers to memory locati ons in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM loc ations at ad-
dresses 80h ( X) and 81h (Y). They can also be ac-
cessed with the di rect, short direct, or bit di rect ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect regi sters as any other reg-
ister of the data spac e.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W ). They c an al so be ac ces sed us ing the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
Program Cou nter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
PROGRAM
RESET
OPCODE FLAG
VALUES 2
CONTROLLER
FLAGS ALU
A-DATA B-DATA
ADDRESS/READ LINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULTS TO DATA SPACE (WRITE L INE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin OSCout
ADDRESS
DECODER 256
12 Program Counter
and
6 LAYER STACK
0,01 TO 8MH z
VR01811
1062
17/78
ST62T80B/E80B
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where th ey are added; the resul t is then
shifted back into t he PC. The program counter c an
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL inst ructi onPC= Call addres s
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=I nterrupt vector
- Reset PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal inst ructionPC= PC + 1
Flags (C, Z ). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three norm al modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pa ir (CN, ZN) is used
during Normal operation, another pair is us ed dur-
ing Interrupt mode (CI , ZI), and a third pair i s used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses t he Interrupt flags (resp . the NM I flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in it s own c ontext (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus ret ain their st atus.
The Carry flag is set when a c arry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit test ed in a bit test instruction; it also partici-
pate s in the rotate left instruction.
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatical ly when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
automatica lly selected af t er the reset of t he MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call ( or i nter-
rupt request) occurs, the contents of each level are
shifted into the next hi gher level, whil e the content
of the P C is shifted into the first level (the origin al
contents o f the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each l evel is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are exec ut-
ed, and consequently the last return address will
be lost. It will also remai n in its highest position if
the stack is empty and a RET or RETI is exec uted.
In this case the next instructio n will be executed.
Figu re 7. ST6 C P U Pr ogramm in g M ode
l
SHORT
DIRECT
ADDRESSING
MODE
VREGISTER
WREGISTER
PROGRAM COUNTER
SIX LEVELS
STACK REGISTER
CZNORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
INDEX
REGISTER
VA000423
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0b11
ACCUMULATOR
YREG.POINTER
XREG.POINTER
CZ
CZ
1063
18/78
ST62T80B/E80B
3 CL OCKS, RESE T, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 Mai n Oscil lator
The M C U f ea tu res a Main Osc illator wh ic h c an be
driven by an ex ternal clock, or used in conjunc tion
with an AT -cut parallel resonant crystal or a s uita-
ble ceramic resonator.
Figure 8 ill u s trates various po ss i b le o sc illa t or con-
figurations using an external crystal or ceramic res-
onator, an external clo ck input. CL1 an CL2 should
have a capacitance in the range 12 to 22 pF for an
oscillator frequency in t he 4-8 MHz range.
The internal MCU clock Frequ ency (FINT) is di vid-
ed by 13 to drive t he CPU c ore an d by 12 to drive
the A/D converter and the watchdog timer, while
clock used to drive on-chip peripherals depends
on the peripheral as shown in the clock circuit
block diagram.
With an 8MHz oscillator f requency , the fastest ma-
chine cycle is th erefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Progra m Counter). An i nstruction may requi re
two, four, o r five machine cycles for execution.
Figure 8. Oscillator Configuration s
Figure 9. Cloc k C ir cuit Block Di agram
OSCin OSCout
CL1n CL2
ST6xxx
CRYSTAL/RESONATOR CLOCK
OSCin OSCout
ST6xxx
EXTERNAL CLOCK
NC
VA0016
VA0015A
MAIN
OSCILLATOR
Core
: 13
: 12
Timer 1 & 2
Watchdog
POR
fINT
ADC
OSCin
OSCout
fOSC
fINT
OSC32in
OSC32out
32kHz
OSCILLATOR
MUX LCD
CONTROLLER
DRIVER
EOCR bit 5
(START/STOP)
1064
19/78
ST62T80B/E80B
CLOCK SYSTEM (Cont’d)
3.1.2 32kHz STAND-BY OS CILLATOR
An additi onal 32k Hz stand-by on chip oscillator al-
lows to generate real t i me interrupts and to supply
the clock to the LCD driver with the main oscillator
stopped. This enables the MCU to perform real
time functions with the LCD displ ay running while
keeping advantages of low power consumption.
Figure 9 shows the 32kHz oscillator block dia-
gram.
A 32.768kHz quartz crystal must be connecte d to
the OSC32in and OSC32out pins to perform the
real time cl ock operat ion. T wo ex t ernal capacit ors
of 15-22pF each must be connected between the
oscillator pins and ground. The 3 2k Hz oscil lator is
managed by the dedicated status/control register
32OCR.
As long as the 32kHz stand-by oscillator is ena-
bled, 32kHz internal clock is available to drive LCD
controller driver. This clock is divide by 214 to gen-
erate interrupt request every 500ms . The periodic
interrupt request serves as reference timebase for
re a l time fun c ti on s.
Note: When the 32kHz stand-by oscillator is
stopped (bit 5 of the Status/Control register
cleared) the divider chain is supplied with a clock
signal synchronous with machine cycle (fINT/13),
this produces an interrupt request every 13x214
clock cycle (i.e. 26.624ms) with an 8MHz quartz
crystal.
32kHz Osc illator Register (32OCR)
Address: DBh - Read/Write
Bit 7 = EOSCI.
Enable Oscillator Interrupt
. This bit,
when set, enables the 32kHz oscillator interrupt
request.
Bit 6 = OSCEOC.
Oscillator Interrupt Flag
. Th i s b i t
indicates when the 32kHz oscillator has measured
a 500ms elapsed time (providing a
32.768kHzquartz crystal is connected to the
32kHz oscillator dedicated pins). An interrupt re-
quest can be generated in relation to the state of
EOSCI bit. This bit must be cleared by the user
program before leaving the interrupt service rou-
tine.
Bit 5 = START/STOP. O
scillator Start/Stop bit
.
This bit, when set, enables the 32kHz s tand-by os-
cillator and the free running divider chain is sup-
plied by the 32kHz oscillator signal. When this bit
is cleared to zero the divider chain is supplied with
fINT/13.
This regis ter is cleared during reset.
Note:
To achieve minimum power consumption in STOP
mode (no system clock), the stand-by oscillator
must be switched of f (r eal time function not availa-
ble) by clearing the Start/Stop bit in the oscillator
status/control regis ter.
Figure 10. 32kHz Oscillator Block Diagram
70
EOSCI OSCEOC S/S D4 D3 D2 D1 D0
OSC32KHz
EOSCI OSCEOC START
STOP XX XXX
INT
OSC32IN
OSC32OUT
2x15...22pF
32.768kHz
Crystal fINT/13
OSC32KHz MUX
1
0DIV 214
1065
20/78
ST62T80B/E80B
3.2 RESETS
The MCU can be reset in three ways:
– by t he external Reset input being pulled low;
– by Power-on Reset;
– by t he digital Watchdog peripheral timing out.
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU i nternal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to t he
external signal. Therefore even short pulses on
the RESET pin are ac ceptable, provide d VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low .
If RESET activation occurs in the RUN or WAIT
modes, processi ng of the user program is stopped
(RUN mode only ), the Inputs and Output s are c on-
figured as inputs with pull-up resistors and the
main Osc illator is restarted. When the level on the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
I f RESET pin activation occurs i n t he STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the lev el of the RESET pin the n goes high,
the initialization sequence is executed following
expiry of the internal delay period.
3.2.2 Power-on Reset
The function of the PO R circuit cons ists in wak ing
up the MCU at an appropriate stage during the
power-on sequence. At the beginning of this se-
quence, the MCU is configured in the Reset state:
all I/O ports are configured as inputs with pull-up
resistors and no instruction is executed. When t he
power supply voltage rises to a sufficient level, t he
oscillator starts to operate, whereupon an internal
delay is initiated, in orde r to allow the oscillator to
fully stabilize before exec uting t he first instruct ion.
The initialization sequence is exec uted immediate-
ly following the internal delay.
The internal delay is generated by an on-chip coun-
ter. The int ernal reset line is released 2048 internal
clock cycles after release of the external reset.
Notes:
To ensure correct start-up, the user should take
care that the reset signal is not released before the
VDD level is sufficient to allow MCU operation at
the chosen frequency (see Recommended Oper-
ating Conditions).
A proper reset s ignal for a slo w rising V DD supply
can g enerally be pro vided b y an external RC net-
work connected to the RESET pi n.
Figure 11. Reset and Interrupt Processi ng
INT LATCH CL EA RED
NMI MASK SE T
RESET
( IF PRESENT )
SELECT
NMI MODE FLAG S
IS RESET STILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTIO N
LOAD PC
VA000427
1066
21/78
ST62T80B/E80B
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated . This, am ongs t ot h-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built - in s tabilisat io n d elay period.
3.2.4 Application Notes
No external resistor is requi red betw een VDD and
the Reset pi n, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
edge of VDD. The typica l threshold is in the region
of 2 volts, but the actual value of the detected
threshold depends on the way in which VDD rise s.
The POR circuit is
NOT
designed to supervise
static, or slowly rising or falling VDD.
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the begi nni ng of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU i s
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable int errupt s. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. I f, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 12. Reset and Interrupt Processi ng
Figure 13. Reset Block Diagram
RESET
RESET
VECTOR
JP JP:2 BYTES/4 CYCLES
RETI RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROU TINE
VA00181
VDD
RESET
300kΩ
2.8kΩ
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
fOSC
RESET
ON RESET
VA0200B
1067
22/78
ST62T80B/E80B
RESETS (Cont’d)
Table 7. Register Reset Status
Register Address(es) Status Comment
EEPROM Control Register
Port Data Registers
Port A,B Direction Register
Port A,B Option Register
Interrupt Option Register
SPI Registers
LCD Mode Control Register
32kHz Oscillator Register
0DFh
0C0h, 0C1h, 0C3h
0C4h to 0C6h
0CCh, 0CEh, OCFh
0C8h
0C2h, 0DDh
0DCh
0DBh
00h
EEPROM enabled
I/O are Input with pull-up
Interrupt disabled
SPI disabled
LCD display off
Interrupt disabled
UART Control
UART Data Register 00h UART disabled
X, Y, V, W, Register
Accumulator
Data RAM
Data RAM/EEPROM/LCDRAM Page Register
Data ROM Window Register
EEPROM
A/D Result Register
080H TO 083H
0FFh
084h to 0BFh
0CBh
0C9h
00h to 03Fh
0D0h
Undefined As written if programmed
TIMER 1 Status/Control
TIMER 1 Counter Register
TIMER 1 Prescaler Register
Watchdog Counter Registe r
A/D Control Register
0D4h
0D3h
0D2h
0D8h
0D1h
00h
FFh
7Fh
FEh
40h
TIMER 1 disabled/Max count
loaded
A/D in Standby
AR TIMER Mode Control Register
AR TIMER Status/Control 1 Register
AR TIMER Status/Control 2Register
AR TIMER Compare Register
AR TIMER Load Register
AR TIMER Reload/Capture Register
0E5h
0E6h
0E7h
0EAh
0EBh
0E9h
00h
Undefined
AR TIMER stopped
As written if programmed
1068
23/78
ST62T80B/E80B
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement dow n to 00h and res et the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
Watchdog behaviour is governed by one option,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) (See Table 8).
In the SOF TWARE op tion, the Watchdog is disa-
bled until bit C of the DWDR register has been set .
When the Watchdog is disabled, low power Stop
mode is available. On ce activated, the Watchdog
cannot be disabled , except by rese tting the MCU.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog cont inues to countdown.
When the MCU exits STOP mode ( i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
Table 8. Recommended Option Choices
Functions Required Recommended Options
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”
1069
24/78
ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
regist er (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 . This register is set to 0FEh on Re-
set: bit C is cleared to “0”, which disables the
Watchdog; the timer downcounter bits, T0 to T5,
and the SR b it are all set to “1 ”, thus sele cting the
longest Watchdog timer period. This time period
can be set to the user’s requirements by setting
the appropriate value for bits T0 to T5 in the
DWDR register. The SR bit must be set to “1”,
since it is this bit which generates the Reset signal
when it changes to “0”; clearing this bit would gen-
erate an immediate Reset.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR regist er corres pon ds , in f act, to T0 a nd bit
2 to T5. The user should bear in mind the f act that
these bits are i nverted and shifted with respect to
the physical counter bits when writi ng to this regis-
ter. The relationship between the DWDR register
bits and the physical i mplementation of the Watch-
dog timer downcounter is illustrated in F igure 13.
Only the 6 most significant bi ts may be used t o de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, t hi s is equival ent to timer peri-
ods ranging from 384µs to 24.576ms).
Figure 14. Watchdog Counter Control
WATCHDOG CONTROL REGISTER
D0
D1
D3
D4
D5
D6
D7
WATCHDOG COUNTER
C
SR
T5
T4
T3
T2
T1
D2
T0
OSC ÷12
RESET
VR02068A
÷28
1070
25/78
ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog R egister (DWDR)
Address: 0D8h — Read/ Write
Reset status: 1111 1110b
Bit 0 = C:
Watchdog Control bit
If the hardware option is sel ected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When t he software option is se-
lected, th e Watchdo g function is activated by set -
ting bit C to 1, and cannot then be disabl ed (save
by resetting the MCU).
When C is kept low the counter can be used as a
7-bit timer.
This bit is cleared to “0” on Reset.
Bit 1 = SR:
Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) i t is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0:
Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcou nter and bit-2 (T5) is the MSB.
These bits are set to “1” on Reset.
3.3.2 App li cation Notes
The Wat chdog plays an important s upporting role
in the high noise immunit y of ST62xx devices, and
should be used wherever possible. Watchdo g re-
lated options s houl d be s elect ed on t he ba sis of a
trade-off between application security and STOP
mode av ailability.
When S T OP m ode is not requ ired, hardware acti-
vation should be preferred, as it provides maxi-
mum security, especially during power-on.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember t hat the
bits are in reverse order).
The software activation option should be chosen
only when the Watch dog count er is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH
70
T0 T1 T2 T3 T4 T5 SR C
1071
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ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instruction s are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode ), or within the first 27 instructions
executed following a Reset (hardware activation).
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
Figure 15. Digital Watchdog Block Diagram
RSFF
8
DATA BUS VA00010
-2 -12
OSCILLATOR
RESET
WRITE
RESET
DB0
R
S
Q
DB1.7 SETLOAD
78
-2
SET
CLOCK
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ST62T80B/E80B
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priori ty interrupt). Each s ource is asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vec tors a re locat ed in Pro-
gram space (see Table 1 ).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with t he address of the i nter-
rupt vector (i.e. of the Jump instruction), which
then caus es a Jump to the relevant interrupt serv-
ice routine, t hus servicing the interrupt.
Interrupt sources are linked to events either on ex-
ternal pins, or o n chip periphe rals. Several event s
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt rou tine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are proc essed by the proces sor
core according to thei r pr iority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source i s fixed.
Table 9. Interrupt Vector Map
3.4.1 Interrupt requ est
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Regist er (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU fro m STOP/WAIT modes.
Interrupt request from t he Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
ically reset by the core at the beginning of t he non-
maskable interrupt service routine.
Interrupt request from source #1 can be configu-
red eithe r as edge or l ev el sensitive by set ting ac-
cordingly the LES bit of the I nterrupt Option Regis-
ter (IOR).
Interrupt request from sourc e #2 are always edge
sensitive. The e dge polarity can be configured by
set ting acco rdin gly the ESB b it of th e Interr upt Op-
tion Register (IOR).
Interrupt request from sources #3 & #4 are level
sensitive.
In edge s ensit ive mode, a latch is s et when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being proc essed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interr upt pin when
the MC U sampl es the line afte r instruction execu-
tion.
At the end of every instruction, th e MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is no t executed and the appropri-
ate interrupt serv ice routine is executed instead.
Table 10. Interrupt Option Register Description
Interrupt Sour ce Priority V ector Address
Interrupt source #0 1 (FFCh-FFDh)
Interrupt source #1 2 (FF6h-FF7h)
Interrupt source #2 3 (FF4h-FF5h)
Interrupt source #3 4 (FF2h-FF3h)
Interrupt source #4 5 (FF0h-FF1h) GEN SET Enable all interrupts
CLEARED Disable all interrupts
ESB SET Rising edge mode on inter-
rupt source #2
CLEARED Falling edge mode on inter-
rupt source #2
LES SET Level-sensitive mode on in-
terrupt sourc e #1
CLEARED Falling edge mode on inter-
rupt source #1
OTHERS NOT USED
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ST62T80B/E80B
INTERRUPTS (Cont’d)
3.4.2 Interrupt Pr oced ure
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can con sider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the tim e at which i t occurred. A s a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags f or nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The following list summarizes the interrupt proce-
dure:
MCU
– The interrupt is detected.
– The C and Z flags are replaced by the interrupt
fl ags (or by the NMI fl ags).
– The PC contents are stored in the first level of
the stack.
– The normal interrupt lines are i nhibited (NMI still
active).
– The fi rst internal latch is cleared.
– The associated interrupt vector is loaded in the PC.
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL m ode and especially during the execu-
tion of an "ldi IOR, 00h" instruction (disabling all
maskable int errupts): if the interrupt arrives duri ng
the first 3 cycles of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
User
– User selected registers are saved within the in-
terrupt service routine (normally on a software
stack).
– The source of the interrupt is found by polling the
interrupt flags (if more than one s ourc e is associ-
ated with the same vector).
– The in t er ru p t is se rvic e d.
– Return from interrupt (RETI)
MCU
– Automaticall y the MCU switches back to the nor-
mal f l ag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used wit hin the interrupt r outine i n a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 16. Interrupt Processi ng Flow Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
WAS
THE INSTRUCTION
A RETI ?
?
CLEAR
INTERRUPT MASK
SELECT
PROGRAM FLAGS
"POP"
THE STACKED PC
?CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
SELECT
INTERNAL MODE FLAG
PUSH THE
PC INTO THE STACK
LOAD PC FROM
INTERRUPT VECTOR
(FFC/FFD)
SET
INTERRUPT MASK
NO
NO
YES IS THE CORE
ALREADY IN
NORMAL MODE?
VA000014
YES
NO
YES
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ST62T80B/E80B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Opt ion Register (IO R) is used to en-
able/disable the individual interrupt sources and to
select the operating mod e of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused
.
Bit 6 = LES:
Level/Edge Selection bit
.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB:
Ed ge Sel ect ion bit
.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN:
Global Enable Interrupt
. When this bit
is set to one, all inte rrupts are e nabled . W hen t his
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the G EN bit i s low, t he NM I interrupt is ac-
tive but cannot cause a wake up from ST OP /WAIT
modes.
This regis ter is cleared on reset.
3.4.4 Interrupt so urces
Interrupt sources available on the
ST62E80 B/T80B are summarize d in the Table 11
with associated m ask bit to enable/disabl e the in-
terrupt request.
Table 11. Interrupt Request s and Mask Bi ts
70
- LES ESB GEN - - - -
Peripheral Register Address
Register Mask bit Masked Interrupt Source Interrupt
source
GENERAL IOR C8h GEN All Interru pts, excluding NMIAll
TIMER 1 TSCR1 D4h ETI TMZ: TIMER Overflow source 3
A/D CONVERTER ADCR D1h EAI EOC: End of Conversion source 4
SPI SPI C2h ALL End of Transmission source 1
Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin source 2
Port PBn ORP B-DR PB C1h-C 5h O RPBn -DRP Bn PBn pin source 2
Port PCn ORP C-DR PC C6h-C Fh O RPCn -DRP Cn PCn pin source 2
32kHz OSC 32OCR DBh EOSCI OSCEOC source 3
ARTIMER ARMC E5h OVIE
CPIE
EIE
OVF: ARTIMER Overflow
CPF: Successful Compare
EF: Active edge on ARTIMin source 3
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ST62T80B/E80B
INTERRUPTS (Cont’d)
Figure 17. Interrupt Block Diagram
PORT A
PBE
VDD
FR OM R EGI STER PORT A,B,C
SINGLE BIT ENABLE
FF
CLK Q
CLR
I0 Start
INT #0 NMI (FFC,D))
INT #2 (F F4,5)
NMI
POR T B
Bits
SPI FF
CLK Q
CLR 0
MUX
1
I1 Start
IOR bit 6 (LES)
PBE FF
CLK Q
CLR
IOR bit 5 (ESB) I2 Start
INT #1 (FF6,7)
INT #3 (FF2,3)
INT #4 (FF0,1)
IOR bit 4(GEN)
PORT C
TMZ
ETI
OVF
OVIE
OSCEOC
EOSCI
EAI
EOC
RESTART
STOP/WAIT
FROM
PBE
TIMER1
ARTIMER
OSC32kHz
A/D CONV ERT ER
CPF
CPIE
EF
EIE
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ST62T80B/E80B
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs i n order to
reduce the product ’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraph s.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be cons idered as being in a “s oftwa re f roze n”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa-
bility o f m o nitoring external e ve nts. Th e acti ve os-
cillator is not stopped in order to provide a clock
signal to the peripherals. Timer counting may be
enabled as well as the Timer interrupt, before en-
tering the WA IT mode: t his allows the WAIT mode
to be exited when a Timer interrupt occurs. The
same applies to other peripherals which use the
clock signal.
If the W AIT mode is exited due to a Re set (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
mode, the MCU’s behavi our depends on the state
of the processor core prior to the WAIT inst ruction,
but also on the kind of interrupt request which is
generated. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumpt ion mode. In this oper-
ating mode, t he microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention voltage, and the ST62xx c ore wa its for the
occurrence of an external interrupt request or a
Reset to exit the ST OP stat e.
If the STOP state is exited due to a Reset ( by acti-
vating the external pin) the MCU will enter a nor-
mal reset procedure. Behaviour in response to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt reques t that is gener-
ated.
This case will be described in the following para-
graphs. T he processor core generat es a delay af-
ter occurrence of the interrupt reque st, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
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ST62T80B/E80B
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart s equence depends on the original state
of the MCU (normal, int errupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
Interrupts do not affect the oscillator selection.
3.5.3.1 Normal Mo de
If the MCU was in the main routine when the WAIT
or STOP inst ruction was executed, exit from S top
or Wait mode will occur as s oon as an i nterrupt oc-
curs; the related interrupt routine is exec uted and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pendi ng.
3.5.3.2 Non Maskab le Interrupt M ode
If the STO P or WAIT instruc tion has been execut-
ed during exec ution of the non-ma skab le interrupt
routine, the MCU ex its from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STO P or WAIT in struction is ex-
ecuted, and the MCU remains i n non-maskable in-
terrupt mode, even if another interrupt has been
generated.
3.5.3.3 Normal Interrupt Mode
If the MCU was i n interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
– If the i nterrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the in terrupt m ode. A t the end of t his rou-
tine pending interrupts will be serviced in accord-
ance with their priority.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
interrupt mode.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes , the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
– placing all peripherals in their power down
modes bef ore ente ring STOP mod e;
When the hardware act ivated Wat chdog i s selec t-
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion w ill be ex ec u t ed in its pla c e.
If all interrupt sources are di sabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in-
terrupt, it will stop it generating a wake-up signal.
The WAIT and STO P instructions are not execut-
ed if an enabl ed interrupt request is pending.
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ST62T80B/E80B
4 ON- CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurations:
– Input wit hout pull -up or interrupt
– Input w ith pull-up and interrupt
– Input wit h pull-up, but without int errupt
– Analog input
– Pus h-pull output
– Open drain output
The lines are organised as bytewise Ports.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed wi t h the P A0 line of Port A).
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured a s inputs , or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data regi sters can be read to get
the effective l ogic levels of the pins, but they can
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
Single-bit operations o n I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
The O pt ion registers (O Rx) are us ed t o se lect t he
different port options available both in input and in
output mode.
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
Figure 18. I/O Po rt Block Diagram
VDD
RESET
SIN CO NT ROL S
SOUT
SHIFT
REGISTER
DATA
DATA
DIRECTION
REGISTER
REGISTER
OPTION
REGISTER
INPUT/OUTPUT
TO INTERRUPT
VDD
TO ADC VA00413
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ST62T80B/E80B
I/O POR TS (Cont’d)
4.1.1 Operati ng Mod es
Each pin may be individually programmed as input
or output wit h various configurations.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) an d Option reg-
isters (OR). Table 12 illustrates the various port
configurations whic h can be selected by us er soft-
ware.
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
can be individually programm ed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
4.1.1.2 Interru pt Op tions
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
4.1.1.3 Analog Input Options
Som e pins can be con figured as analog in puts by
programmi ng the OR and DR registers acc ording-
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Converter.
ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Table 12. I/O Port Option Selection
Note: X = Don’t care
DDR OR DR Mode Option
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)
1080
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ST62T80B/E80B
I/O POR TS (Cont’d)
4.1.2 Safe I/O State S witching Seq uence
Switching the I/O ports from one state to a nother
should be done in a sequenc e whi ch ens ures t hat
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure
18. All other transitions are potentially risky and
should be avo ided when changing the I/O operat -
ing mode, as it i s most likely that undesirable side-
effects will be experienced, s uch as spur ious inter-
rupt generation or two pins s horted together by t he
analog multipl exer.
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, sinc e these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data r egis-
ter la tches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it i s better
to limit the use of single bit instructions on data
registers to when the whol e (8-bit) port is in output
mode. In t he case of inputs or of mixed inputs and
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the who le
copy register can be written to the port data regis-
ter:
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by sof tware (AND instruction).
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The us er must take care not to switch output s with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturban ce to
the conversion .
Figure 19. Diagram showing S afe I/O State Transition s
Note *. xxx = DDR, O R, DR Bits respectively
Interrupt
pull-up
Output
Open Drain
Output
Push-pull
Input
pull-up (Res et
state)
Input
Analog
Output
Open Drain
Output
Push-pull
Input
010*
000
100
110
011
001
101
111
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ST62T80B/E80B
I/O POR TS (Cont’d)
Table 13. I/O Port configu ration for the ST62T80B /E80B
Note 1. Provided the correct configuration has been selected .
MODE AVAILABLE ON(1) SCHEMATIC
Input PA2-PA7
PB0-PB7
PC0-PC7
Input
with pull up
(Reset state)
PA2-PA7
PB0-PB7
PC0-PC7
Input
with pull up
with interrupt
PA2-PA7
PB0-PB7
PC0-PC7
Analog Input PB0-PB7
PC4-PC7
Open drain output
5mA
Open drain output
20mA
PA2-PA7
PB0-PB7
PC0-PC7
PA2-PA7
PC0-PC3
Push-pull outpu t
5mA
Push-pull outpu t
20mA Sink
PA2-PA7
PB0-PB7
PC0-PC7
PA2-PA7
PC0-PC3
Data in
Interrupt
Data in
Interrupt
Data in
Interrupt
Data out
ADC
Data out
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ST62T80B/E80B
I/O POR TS (Cont’d)
4.1.3 ARTimer alternate functions
When bit PWMOE of register ARMC is low, pin
ARTIMout/PB7 is configured as any standard pin
of port B through the port registers. When PW-
MOE is high, ARTIMout/PB7 is the PWM output,
independent ly of the port registe rs configuration.
ARTIMin/PB6 is c on nec ted to th e A R T imer input.
It is configured through the port registers as any
standard pin of port B. T o use ARTIMin/PB6 as AR
Timer input, it must be confi gured as input through
DDRB.
4.1.4 SPI alternate functions
PA6/Sin and PA5/Scl pins must be configured as
input through the DDR and OR registers to be
used as data in and data clock (Slave mode) for
the SPI. All input modes are available and I/O's
can be read independently of the SPI at any time.
PA7/Sout must be confi gured in open drain output
mode to be used as data out for the SPI . In output
mode, the value present on the pin is the port data
register content only if PA 7 is defined as push pull
output, while serial t ransmission is possible onl y in
open drain mode.
4.1.5 UART al ternate functions
PB1/RXD1 pin must be configured as input
through the DDR and OR registers to be used as
reception line for the UART. All input modes are
available and PB1 can be read independently of
the UART at any time.
PB0/TXD1 pin must be configured as output
through the DDR and OR registers to be used as
transmission line for the UART. Value present on
the pin i n output mode is the Data register cont ent
as long as no transmission is active.
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ST62T80B/E80B
Figure 2 0. P eri pheral Interf ace Confi guration of S eri al I/O TI m er 1 , ART imer
PA7/Sout
PA6/Sin
PA5/SCL
PA4/TIM1
PB6/ARTIMin
PB7/ARTIMout
VR01661
IN
OUT
TIMER1
TIMIN
PWMOE
ARTimer
TIMOUT
CLOCK
IN
SPI
OUT
DR
DR
DR
MUX 0
1DR
DR
MUX 1
0
PP/OD
PP/OD
PP/OD
MUX 1
0DR
OPR
OPR
OPR
VDD
PB0/RXD1
PID
0
MUX 1
PB1/TXD1
VDD
DR
RXD
UART
IARTOE
TXD
PID DR
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ST62T80B/E80B
I/O POR TS (Cont’d)
4.1.6 I/O Port Option Registers
ORA/B/C (CCh PA, CEh PB, CFh PC)
Read/Write
Bit 7-0 = Px7 - Px0:
Port A, B, C Option Register
bits.
4.1.7 I/O Port Data Direction Registers
DDRA/B/C (C4h PA, C5h PB, C6h PC)
Read/Write
Bit 7-0 = Px7 - Px0:
Port A, B, C Data Direction
Registers bits.
4.1.8 I/O Port Data Registers
DRA/B/C (C0h PA, C1h PB, C3h PC)
Read/Write
Bit 7-0 = Px7 - Px0:
Port A, B, C Data Registers
bits.
70
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
70
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
70
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
1085
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ST62T80B/E80B
4.2 TIMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bi t program-
mable prescaler, giving a maximum count of 215.
The peripheral may be c onfigured in three different
operating modes.
Figure 20 shows the Timer Block Diagram. The
external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, while the s tate of
the 7-bit presc ale r can be read in t he PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraph s.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
The prescaler input can be the internal frequency
fINT divided by 12 or an external clock applied to
the TIMER pin. The prescaler decrements on the
rising edge. Dep ending on t he division factor pro-
grammed by PS2, PS1 and PS0 bi ts in the TSCR.
The clock input of t he timer/counter register is mul-
tiplexed to different sources. Fo r division factor 1,
the clock input of the prescaler is also that of tim-
er/counter; for factor 2, bit 0 of the prescaler regis-
ter is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres-
caler input clock. For factor 4, bit 1 of the PSC is
connected t o the c lock inp ut o f TCR, and s o forth.
The prescaler initializ e bit, P SI, i n the TSCR regis-
ter must be set to “1” to allow the prescaler (and
hence the counter) to st art. If i t is cleared to “0”, all
the presca ler bits are set to “1” and the coun ter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of t he PS2/PS1/ PS0 bits in the control reg-
ister.
Figure 21 illustrat e s the Timer’s working pr inci p l e.
Figure 21. Timer Block Diagram
DATABUS 8
8
88
8-BIT
COUNTER
6
5
4
3
2
1
0
PSC STATUS/CONTROL
REGISTER
b7 b6 b5 b4 b3 b2 b1 b0
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
SELECT
1 OF 7
3
LATCH
SYNCHRONIZATION
LOGIC
TIMER INTERRUPT
LINE
VA00009
:12
fOSC
1086
41/78
ST62T80B/E80B
TIMER (Cont’d)
4.2.1 Timer Op erati ng Mod es
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (fINT ÷ 12 or TIMER pin signal), and to
the output mode.
4.2.1.1 Gated Mod e
(TOUT = “0”, DOUT = “1”)
In this mode the prescaler is decremented by the
Timer c lock input (f INT ÷ 12 ), but ONLY w hen the
signal on the TIMER pin is held high (allowing
pulse w idth m easurement). This mod e is se lected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
4.2.1.2 Event Counter Mo de
(TOUT = “0”, DOUT = “0”)
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
4.2.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler cl ock input (fINT ÷ 12).
The user c an select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. Th e TMZ bit can be tested u nder program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bit of the T SCR and trans-
fer it to the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
Ta bl e 14 . Tim er Operati ng M odes
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer I nterrupt) bit set to one, an
interrupt requ est is g enerated a s described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR regi ster is set to
one.
Figure 22. Tim er W orking P ri nc i pl e
TOUT DOUT Timer Pin Timer Function
0 0 Input Event Counter
0 1 Input Gated Input
1 0 Output Output “0”
1 1 Output Output “1”
BIT0 BIT1 BIT2 BIT3 BIT6BIT5BIT4
CLOCK
7-BIT PRESCALE R
8-1 MUL TIPLEXER
8-BI T COUNTER
BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
10 234 567
PS0
PS1
PS2
VA00186
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ST62T80B/E80B
TIMER (Cont’d)
4.2.3 Application Notes
The user can select the presence of an on-chip
pull-up on the TIMER pin as opti on.
TMZ is set when t he counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts w hen leaving the inte rrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, whil e the 7-bit prescaler is l oad-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt i s disabled.
If the Timer is programmed in output mode, the
DOUT bit is transferred to the TIMER pin when
TMZ is set to one (by software or due to counter
decrement ). When TMZ is high, the latch is trans-
parent and DOUT is copied to the timer pi n. When
TMZ goes low, DOUT is latched.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decre ment to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC regis ters can be read accurately at any time.
1088
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ST62T80B/E80B
4.3 AUTO-RELOAD TIMER
The Auto-Reload Timer (AR Timer) on-chip pe-
ripheral consists of an 8-bit timer/counter with
compare and cap ture/reload capabilities and of a
7-bit prescaler with a clock multiplexer, enabling
the clock inpu t to be selected as fINT, fINT/3 or an
external clock source. A Mode Control Register,
ARMC, two Status Cont rol Registers, ARS C0 and
ARSC1, an output pin, ARTIMout, and an input
pin, ARTIMin, allow the Auto-Reload Timer to be
used in 4 modes:
– Auto-reload (PWM generation),
– Output compare and reload on ext ernal event
(PLL),
– Input capture and output compar e for time meas-
urement.
– Input capture and output compare for period
measurement.
The AR Timer can be used to wake the MCU from
WAIT mode either with an internal or with an exter-
nal clock. It also can be used to wake the MCU
from STOP mode, if used with an external clock
signal connected t o the ARTIM in pin. A Load reg-
ister allows the program to read and write the
counter on the fly.
4.3.1 AR Timer Description
The AR COUNTER is an 8-bit up-counter incre-
mented on the input clock’s rising edge. The coun-
ter is loaded from the ReLoad/Capture Register,
ARRC, for auto-reload or capture operations, as
well as for initialization. Direct access to the AR
counter is not possible; however, by reading or
writing the ARLR load register, it is possible to
read or write the counter’s conten ts on the fly.
The AR Timer’s input clock can be either the i nter-
nal clock (from the Oscillator Divider), the internal
clock divided by 3, or the clock signal connected to
the ARTIMin pin. Selection between these clock
sources is effected by suitably programming bits
CC0-CC1 of t he ARSC1 regi ster. The output of the
AR Multiplexer feeds the 7-bit programmable AR
Prescaler, ARPSC, which selects one of the 8
available taps of the prescaler, as defined by
PSC0-PSC2 in the AR Mode Control Register.
Thus the division factor of the prescaler can be set
to 2n (where n = 0, 1,..7).
The clock input to the AR counter is enabl ed by the
TEN (Timer Enable) bit in the ARMC register.
When TEN i s reset, the AR counter is stopped and
the prescaler and counter contents are frozen.
When TEN is s et, the AR counter runs at the rate
of the selected clock source. The counter is
cleared on system reset.
The AR counter may also be initialized by writing
to the ARLR load register, which also causes an
immediate c opy of the value to be placed in t he AR
counter, regardless of wh ether the counter is run-
ning or not. Initialization of the counter, by either
method, will also clear the ARPSC register, where-
upon counting will start from a known value.
4.3.2 Ti mer Operating Modes
Four different operating modes are available for
the AR Timer:
Auto-reload Mode with PWM Generation. This
mode allo ws a Puls e Wi dth Modulated signal to be
generated on the ARTIMout pin with minimum
Core processing overhead.
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
edge of the cl ock signal.
When a counter overflow occurs, the counter is
automatically reloaded wit h the contents of the Re-
load/Capture Register, ARCC, and ARTIMout is
set. When the counter reaches the value con-
tained in the c omp are register (ARCP), ARTIMout
is re se t.
On overflow, the OVF flag of the ARSC0 register is
set and an overf low interrupt request is generated
if the overflow interrupt enable bit, OVIE, in the
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare val ue, the
CPF flag of the ARSC 0 register is set and a com-
pare interrupt r equest is generated, if the Compare
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set . The i nterrupt service rou-
tine may then adjust the PWM period by loading a
new value into ARCP. The CPF flag must be reset
by user software.
The PWM signal is generated on the ARTIMout
pin (refer to the B lock Di agram ). The f requency of
this signal is controlled by the prescaler setting
and by the auto-reload value present in the Re-
load/Capture register, ARRC. The duty cycle of
the PWM signal is controlled by the Compare Reg-
ister, ARCP.
1089
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
Figure 2 3. AR Ti m er B lo ck D iag ram
DATA BUS
8
8
8
COMPARE
8
RELOAD/CAPTURE
DATA BUS
AR TIMER
VR01660A
88
R
S
TCLD
OVIE
PWMOE
OVF
LOAD
ARTIMout
M
SYNCHRO
ARTIMin SL0-SL1
INT
f
PB6/
AR
REGISTER
EF
REGISTER
LOAD
AR
U
X
fINT /3 AR PR ESCALER
7-Bit
CC0-CC1
AR COUNTER
8-Bit
AR COMPARE
REGISTER
OVF
EIE
EF
INTERRUPT
CPF
CPIE
CPF
DRB7
DDRB7
PB7/
PS0-PS2
88
1090
45/78
ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of PWM output signal. To obtain a signal on ARTI-
Mout, the co ntents of the ARCP register must be
greater than t he contents of the ARRC regist er.
The maximum available resolution for the ARTI-
Mout duty cycle is:
Resolution = 1/[255-(ARRC)]
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com-
pare Register, ARCP, must be in the range from
(ARRC) to 255.
The ARTC counter is initialized by writing to the
ARRC register and by t hen setting the TCLD (T im-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and selec tion of t he clock source i s con-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status Control Regist er, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Fi gure 24 . A ut o- relo ad Timer PW M Function
COUNTER
COMPAR E
VALUE
RELOAD
REGISTER
PWM OUTPUT
t
t
255
000
VR001852
1091
46/78
ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
Capture Mode with PWM Generation. In this
mode, the AR counter operates as a free running
8-bit counter fed by the prescaler output. The
counter is incremented on ever y clock rising edge.
An 8-bit capture operation from the co unter to the
ARRC register is pe rformed on every active edge
on the AR TIMin pin, when enab led by E dge Con-
trol bits SL0, SL1 in the ARSC1 register. At the
same time, the External Flag, EF, in the ARSC0
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
in the ARMC reg ister, is set. The E F flag must be
reset by user software.
Each ARTC overflow sets ARTIMout, while a
match between t he c ounter and A RCP (Compa re
Register) resets ARTIMout and sets the compare
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A P WM signal i s generated on ARTI-
Mout. The CPF flag must be reset by user soft-
ware.
The frequency of the generated signal is deter-
mined by the prescaler setting. The duty cycle is
determined by the ARCP register.
Initialization and reading of the counter are identi-
cal to the auto-rel oad mode (see previous descrip-
tion).
Enabling and selection of clock sources is cont rol-
led by the CC0 and CC1 bits in the AR Status Con-
trol Register, ARSC1.
The prescaler division ratio is selected by pro-
gramming the PS0, PS1 and PS2 bits in the
ARSC1 Register.
In Capture mode, the allowed clock sources are
the internal clock and th e internal clock divide d by
3; the external ARTIMin input pin should not be
used as a clock source.
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi-
cal to the previous o ne, with the differe nce that a
capture condition also resets the counter and the
prescaler, thus allowing eas y measurem ent of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
Load on External Input. The count er operates as
a free running 8-bit counter fed by the prescaler.
the count is incremented on every clock rising
edge.
Each counter overflow sets the ARTIMout pin. A
match between the counter and ARCP (Compare
Register) resets the ARTIMout pin and sets the
compare fl ag, CPF. A compare interrupt request is
generated if the related compa re interrupt enab le
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
software.
Initialization of the counter is as described in the
previous par agraph. I n additi on, if the external AR-
TIMin input is enabled, an active edge on the input
pin will copy the contents of t he ARRC register i nto
the counter, whether the count er is running or not.
Notes:
The allowed AR Timer clock sources are the fol-
lowing:
The clock frequen cy should not be modified while
the count er is counting, since the c ounter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Loading of the counter by any mean s (by auto-re-
load, through ARLR, ARRC or by the Core) r esets
the prescaler at the same time.
Care should be taken when both the Capture inter-
rupt and the Overflow interrup t are us ed. Capture
and ov erflow are asynchronous . If the c apture oc -
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by s oftware, in the interrupt routine), the Ex-
ternal Interrupt Flag, EF, may be cleared simul-
taneusly wi thout the interrupt being taken into ac-
count.
The solut ion consists in resetting the OVF flag by
writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
occ ured , it w ill b e proc ess ed whe n the MCU e xits
from the interrupt routine (the second interrupt is
latched).
AR Timer Mode Clock Sources
Auto-reload mode fINT, fINT/3, ARTIMin
Capture mode fINT, fINT/3
Capture/Reset mode fINT, fINT/3
External Load mode fINT, fINT/3
1092
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
4.3.3 AR Timer Registers
AR Mode Control Register (ARMC)
Address: D5h — Read/Write
Reset status: 00h
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be read and writt en to by the Core
and it is cleared on system reset (th e AR Timer is
disabled).
Bit 7 = TLCD:
Timer Load Bit.
This bit, when set,
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPS C, are cleared in order to
initialize the timer before starting to count. This bit
is write-o nly and any attempt to read i t will yield a
logical zero.
Bit 6 = TEN
: Timer Clock Enable.
This bit, when
set, allows the ti mer to count . When cleared, it will
stop the timer and freeze ARPSC and A RTSC.
Bit 5 = PWMOE:
PWM Output Enable.
This bit,
when set, enables the PWM output on the ARTI-
Mout pin. When reset, the PWM output is disabled.
Bit 4 = EIE:
External Interrupt Enable.
This bit,
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 3 = CPIE:
Compare Interrupt Enable.
This bit,
when set, enables the co mpare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. If CPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 2 = OVIE:
Overflow Interrupt
. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is m as ked.
If OVIE is set and the related flag, OVF in the
ARSC 0 register is also set, an interrupt request is
generated.
Bit 1-0 = ARMC1-ARMC0:
Mode Co ntrol Bi ts 1-0
.
These are the operating mode control bits. The fol-
lowing bit com binations will sele ct the v arious op-
erating modes :
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain t he AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edg e and prescaler
mu lt iple x er s ett ing.
ARSC0 register bits 0,1 and 2 contain the int errupt
flags of the AR Timer. These bits are read normal-
ly. Each o ne may be reset by software. Writing a
one does not affect the bit value.
AR Status Control Register 0 (ARSC0)
Address: D6h — Read/Cl ear
Bits 7-3 = D7-D3:
Unused
Bit 2 = EF:
External Interrupt Flag.
This bit is set by
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 1 = CPF:
Compare I nterrupt Flag.
Thi s b it is se t
if the contents of the counter and the ARCP regis-
ter are eq ual. Th e f lag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF:
Overflow Interr upt F lag.
This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
70
TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0 ARMC1 ARMC0 Operating Mode
0 0 Auto-reload Mode
0 1 Capture Mode
10
Capture Mode with Reset
of ARTC and ARPSC
11
Load on External Edge
Mode
70
D7 D6 D5 D4 D3 EF CPF OVF
1093
48/78
ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
AR Status Contr ol Register 1(ARSC1)
Address: D7h — Read/Write
Bist 7-5 = PS2-PS0:
Prescaler Division Selection
Bits 2-0.
These bi ts determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 15. Prescaler Division Ratio Selection
Bit 4 = D4:
Reserved
. Must be kept reset.
Bit 3-2 = SL1-SL0:
Timer Input Edge Control Bits 1-
0.
These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sens it ive; if set, it is falling edge sen-
sitive.
Bit 1-0 = CC1-CC0:
Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following Table
2 :
Table 16. Clock Sour ce Selection.
AR Load Regi ster ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: DBh — Read/Write
Bit 7-0 = D7-D0:
Load Register Data Bits.
These
are the load register data bits.
AR Reload/Capture Register. The ARRC re-
load/capture register is used to hold the auto-re-
load value which is automatically loaded into the
counter when overflow occurs.
AR Reload/Capture (ARRC)
Address: D9h — Read/Write
Bit 7-0 = D7-D0:
Reload/Capture Data Bits
. These
are the Reload/Capture regist er data bit s.
AR Compare Register. The CP compare register
is used to hold the com pare value for the compare
function.
AR Compare Register (ARCP)
Address: DAh — Read/Write
Bit 7-0 = D7-D0:
Compare Data Bits
. These are
the Com pare register data bits.
70
PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0
PS2 PS1 PS0 ARPSC Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
SL1 SL0 Edge Detection
X 0 Disabled
0 1 Rising Edge
1 1 Falling Edge
CC1 CC0 Clock Source
00F
int
01F
int Divided by 3
1 0 ART IMin Input Clock
1 1 Reserved
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
1094
49/78
ST62T80B/E80B
4.4 U. A. R. T. (Uni versal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with an appropriate software routine, giv es a seri al
interface providing communication with common
baud rates (up to 38 ,400 Baud wi th an 8MHz ex-
ternal oscillator) and flexible character formats.
Operating in Half-Duplex mode only, the UART
uses 11-bit characters comprising 1 start bit, 9 data
bits and 1 Stop bit. Parity is supported by software
only for transmit and for checking the received par-
ity bit (bit 9). Transmitted data is sent directly, while
received data is buffered allowing further data
characters to be received while the data is being
read out of th e receive buffer register. Data t rans-
mit has pr iority over dat a being r eceived.
The UART is supplied with an MCU internal clock
that is also available in WAIT mode of the processor.
4.4.1 PORTS INTERFACING
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these t wo I /O lines through the relevant po rts reg-
isters. The I/O line common with RXD li ne must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as outpu t mode (Pus h-pull or open drain ).
The transmitted dat a is inverted and can therefore
use a single tran sistor bu ffering stage. Define d as
input, the RXD line can be read at any time as an
I/O line during the UART operation. The TXD pin
follows I/O port registers value when UARTOE bit
is cleared, which means when no serial tran smis-
sion is in progress. As a consequence, a perma-
nent high level has to be written onto the I/O port in
order to achieve a proper stop condition on the
TXD l i ne when no transmiss ion is acti ve.
Figure 25. UART Blo ck Diagram
CONT ROL LOGI C
TO CORE
START
DETECTOR
DATA SHIFT
REGISTER
D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL REGISTER
BA UD RAT E
RECEIVE BUFFER
REGISTER
PROGRAMMABLE
DIVIDER
DIN DOUT
D9
BAUD RATE x 8
WRITE
READ
RXD1
TXD1
UARTOE
RX and TX
INTERRUPTS
TXD
DR 0
MUX
1
fOSC
VR02009
1095
50/78
ST62T80B/E80B
4.4.2 CLOCK GENER ATION
The UART contains a built-in divider of the MCU
internal clock for most common Baud Rates as
shown in Table 18. Other baud rate values can be
calculated f rom the chosen oscillator frequency di-
vided by the Divisor value shown.
The divided clock provides a frequency that is 8
times the desired baud rate. This allows the Data
reception mechanism to provide a 2 to 1 m ajority
voting system to determine the logic state of the
asynchronous incom in g serial logi c bit by tak ing 3
timed samples within the 8 time states.
The bits no t sampled provide a bu ffer to co mpen-
sate for frequency offsets between sender and re-
ceiver.
4.4.3 DATA TRANSMISSION
Transmission is fixed to a format of one start bit,
nine data b its and one s top bit. The st art and s top
bits are automatically generated by the UART. The
nine databi t s are under control of the user and are
flexible in use. Bits 0..7 are typical ly used as data
bits while bit 9 is typically used as parity, but can
also be a 9th data bit or an additional Stop bit. As
parity is not generated by the UART, it should be
calculated by program and inserted in the appro-
priate position of the dat a (i.e as bit 7 for 7-bit data,
with Bit 9 set to 1 giving two effective stop bits or
as the independent bit 9).
Figure 26. Data Sa mpling Points
The character options are summarised in the fol-
lowing table.
Table 17. . Char acter Options
Bit 9 remains in the stat e programmed f or consec-
utive transmissions until changed by the user or
until a charac ter is rece ived wh en t he st ate of t his
bit is changed to that of the incoming bit 9. The
recommended procedure is thus to set the value of
this bit before transmission is started.
Transmission is started by writing to the Data Reg-
ister (the Baud Rate and Bit 9 should be set before
this action). The UARTOE signal switches the out-
put multipl exer to the UART output an d a start bit
is sent (a 0 for one bit time) f ollowed by the 8 data
values (lsb first) and the value o f the Bit9 b it. T he
output is then set to 1 for a peri od of one bit time to
generate a S top bit, a nd then the UART OE sign al
returns the TXD1 line to its alternate I/O function.
The end of transmission is flagged by setting
TXMT to 1 and an interrupt is generated if ena-
bled. The TXMT flag is reset by writing a 0 to the
bit position, it is als o cleared automatically when a
new character is written to the Data Register.
TXMT can be set to 1 by software to generate a
software interrupt so care must be taken in manip-
ulating the Control Register.
Figure 27. Character Format
VR02010
1 BIT
012 345678
SAMPLES
Start Bit 8 Data 1 Software Parity 1 Stop
Start Bit 9 Data No Parity 1 Stop
Start Bit 8 Data No Parity 2 Stop
Start Bit 7 Data 1 Software Parity 2 Stop
VR02012
POSITION 128
10
BIT
BIT
START STOP
BIT
POSSIBLE
NEXT
CHARACTER
START
D0 D1 D7 D8
START OF DATA
9
1096
51/78
ST62T80B/E80B
4.4.4 DATA RECEPTION
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time ( 8
states) to accommodate the Start bit, and t hen as-
sembles the following serial data stream into the
data register. The data in the ninth bit position is
copied into Bit 9, rep lacing any prev ious val ue s et
for transmission. After all 9 bits have been re-
ceived, the Receiver waits for the duration of one
bit (for the Stop bit) and then transfers the received
data into the buffer register, allowing a following
character to be received. The interrupt flag
RXRDY is set to 1 as the data is transferred to the
buffer register and, if e nabled , will generat e an i n-
terrupt.
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
tr ansmissio n. This i mplies th at a handsha king sys-
tem must be implement ed, as polling of the UART
to detect reception is not available.
Figure 28. .UART Data Output
4.4.5 INTERRUPT CAPABILITIES
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enab led b y set-
ting TXIEN and RXIEN bit i n the UARTCR r egister,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.4.6 REGISTERS
UART Data Register (UARTDR)
Address: D6h, Read/Write
Bit7-Bit0.
UART data bits
. A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets t he transmit in terrupt flag T XMT. A read of
this register returns the data from the Receive
buffer.
Warning
. No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
Table 18. . Baudrate Selection
TXD1
TXD
PO RT DA T A 0
MUX
1
OUTPUT
UARTOE
VR02011
70
D7 D6 D5 D4 D3 D2 D1 D0
BR2 BR2 BR0 fINT Division Baud Rate
fINT = 8MHz fINT = 4MHz
0 0 0 6.656 1200 600
0 0 1 3.328 2400 1200
0 1 0 1.664 4800 2400
0 1 1 832 9600 4800
1 0 0 416 19200 9600
1 0 1 256 31200 15600
1 1 0 208 38400 19200
1 1 1 Reserved
1097
52/78
ST62T80B/E80B
REGISTERS (Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
Bit 7 = RXRDY.
Receiver Ready
. This flag be-
comes active as soon as a complete byte has
been received and copied into the receive buffer. It
may be cleared by writing a zero to it. Writing a
one is possible. If t he interrupt enable bit RXIEN is
set to one, a soft ware interrup t will be gene ra ted.
Bit 6 = TXMT.
Transmitter Empty
. This flag be-
comes active as soon as a complete byte has
been sent . I t may be cleared by writing a zero to it.
It is automatically cleared by the action of writing a
data value into the UART data register.
Bit 5 = RXIEN.
Receive Interrupt Enable
. When
this bit is set to 1, the receive interrupt is enabled.
Writing to RXIEN doe s not affect the status of the
interrupt flag RXRDY.
Bit 4 = TXIEN.
Transmit Interrupt Enable
. When
this bit is set to 1, t he transmit interrupt is enabled.
Writing to TXI EN does not affect the s tatus of t he
interrupt flag TXRDY.
Bit 3-1= BR2..BR0.
Baudrate select
. These bits
select the operating baud rate of the UART, de-
pending on the frequency of fOSC. Care should be
taken not to change these bits during communica-
tion as writing to these bits has an immediate ef-
fect.
Bit 0 = DAT9.
Parity/Data Bit 9
. This bit represents
the 9th bit of the data character that is received or
transmitted. A write to this bit sets the level for the
bit 9 to be transmitted, so it must always be set to
the correct level before transmission. If used as
parity, the value has f irst to be calculated by soft-
ware. Rea ding this bit wi ll return the 9th bit of the
received character.
70
RXRDY TXMT RXIEN TXIEN BR2 BR1 BR0 DAT9
1098
53/78
ST62T80B/E80B
4.5 A/D CONVERTER (ADC)
The A /D c onvert er periphera l i s an 8-bit analog to
digital convert er with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock freq uency
of 8MHz).
The AD C converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twel ve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data regis ters (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O p in i s se lected as an analog in put s i-
multaneously, to avoi d device malfunction.
The ADC uses t wo registers in the data space: the
ADC data conv ersion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
A conversi on is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the En d Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is a utomatically set to “1”, in order to
flag that conversion is complete and t hat the data
in the ADC da ta conversion regist er is val id. E ach
conversion has to be separately initi at ed by writing
to the STA bit.
The STA bit is continuously scanned so t hat, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0 ” .
The A/D converter features a maskable interrupt
associated with the end of conversio n. T his inter-
rupt is associated with interrupt vector #4 an d oc-
curs when t he EOC bit is s et (i.e. when a conver-
sion is completed). T he interrupt is masked using
the EAI (interrupt mask) bit in the control register.
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. I f PDS=“1”, the A/D is powered and en-
abled for conversio n. This bit mus t be set at least
one instructi on bef ore the beginning of t he conver-
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset t o 40h and the
ADC interrupt is masked (EAI=0).
Figure 29. ADC Block Diagram
4.5.1 App li cation Notes
The A /D c onvert er doe s not f eature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB f or the opt imum conversion accurac y. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
When select ed as an analog channel, the input pin
is internally connected to a capacitor Cad of typi-
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beg inning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source i s c alculated us-
ing the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband. ASI can be higher if Cad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
CO NTROL REGIST ER
CONVERTER
VA00418
RESULT REGISTER
RESET
INTERRUPT
CLOCK
AV
AVDD
Ain
8
CORE
CO NTROL SI GNA LS
SS
8
CORE
1099
54/78
ST62T80B/E80B
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. S uch switching will affect the sup-
ply voltages used as analog references.
The accuracy of the conversion depends on the
quality of the power supplies (VDD and VSS). The
user must take special care to ensure a well regu-
lated reference voltage is present on the VDD and
VSS pins (power supply vol tage variations must be
less than 5V/ms). This impl ies, in particular, that a
suitable decoupling capacitor is used at the VDD
pin.
The converter resolution is given by::
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain cons tant during conversion.
Conversion resolution can be improved if the pow-
er supply voltage (VDD) to the microcontroller is
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. N evertheles s, th e W A IT i ns truction should be
executed as soon as possible after the beginning
of the conversio n, because exec ut ion of the WAIT
instruction may cause a sma ll variation of the VDD
voltage. The negative ef fect of t his variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still worki ng. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accurac y.
A/D Converter Control Register (ADCR)
Address: 0D1h — Re ad/Write
Bit 7 = EAI:
Enable A/D Interrupt.
If this bi t is se t to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
Bit 6 = EOC:
End of convers ion.
Read O nly
. This
read only bit indicates when a conversion has
been completed. This bit is au tomatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
Bit 5 = STA
: Start of Conversion. Write Only
. Writ -
ing a “1” to this bit will start a conv ersion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is wri te only, any
attempt to read it will show a logical zero.
Bit 4 = PDS
: Power Down Selection.
This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (id le
mode).
Bit 3-0 = D3-D0. Not used
A/D Converter Data Register (ADR)
Address: 0D0h — Re ad only
Bit 7-0 = D7-D0
: 8 Bit A/D Conversion Result.
V
DD
V
SS
–
256
----------------------------
70
EAI EOC STA PDS D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
1100
55/78
ST62T80B/E80B
4.6 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of indus-
try standard SPI specificat ions. The on-chip SPI is
controlled by small and simple user software to
perform serial data exchange. The serial shift
clock can be implemented either b y software (us-
ing the bit-set and bit-reset instructions), with the
on-chip Timer 1 by externally connecting the SPI
clock pin t o the timer pin or by direct ly applying an
external cloc k to the Scl line.
The peripheral is composed by an 8 -bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can b e tied together
to implement two wires protocols (I²C-bus, etc).
When data is serialized, the MSB is the first bit. Sin
has to be programmed as input. For seri al output
operation Sout has to be programmed as open-
drain output.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same extern al
pins. With t hese 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-B US,
I²C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be gener ated af-
ter eight clock pulses. Figure 29 shows the SPI
block diagram.
Th e SC L lin e c lo cks, o n t he fallin g e dg e, t he shift
register and the counter. To al low SPI operation in
slave mode, the SCL pin mu st be program m ed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
In m aste r m ode, S CL is programm ed as output , a
clock sign al must be generated by sof t ware t o set
and reset the port line.
Figure 30. SPI Block Diagram
Set Res
CLK
RESET
4-Bit Count er
(Q4=High after Clock8)
Data Reg
Direction
I/O Port
8-Bit Data
Shift Re gis te r
Reset
Load
DOUT
Output
Enable
8-Bit Tristate Data I/O
RESET
I/O Port
I/O Port
CP
CP
DIN
D0............................D7
to Processor Data Bus
Q4
Q4
OPR Reg.
DIN
SCL
Sin
Sout
SP I Int errupt Di sable Regi ster
SP I Data Register
Data Reg
Direction
Data Reg
Direction
DOUT
Write
Read
MUX
0
1
Interrupt
VR01504
1101
56/78
ST62T80B/E80B
SERIAL PERIPHERAL INTERFACE (Cont’d)
After 8 clock pulses (D7..D0) t he out put Q 4 of the
4-bit binary counter becomes low, disabling the
clock from the counter and the data/shift register.
Q4 enables the clock to generate an interrupt on
the 8th clock falling edge as long as no res et of the
counter (processor write into the 8-bit data/shift
register) takes place. After a processor reset the
interrupt is disabled. The interrupt is active when
writing data in the shift register and desactivated
when writing an y data i n t he SPI Interrupt Disable
register.
The generation of an interrupt to the Core provides
information that new data i s availabl e ( input mode)
or that transmission is completed (output mode),
allowing the Co re to generat e an acknowledge on
the 9th clock pulse (I²C-bus).
The interrupt is initiated by a high to low transition,
and therefore interrupt opt ions must be set accord-
ingly as defined i n the interrupt section.
After powe r on rese t, or after writing the data/shift
register, the co unter is res et to z ero and the clock
is enabled. In this condition the data shift register
is ready for reception. No start condition has to be
detected. Through the user s of tware the Core may
pull down the Sin line (Acknowledge) and slow
down the SCL, as long as it is needed to carry out
data from the shift register.
I²C-bus Master-Slave, Receiver-T rans m itter
When pins Sin and Sout are externally connected
together it is pos sible to use t he S P I as a receiver
as well a s a tran smitter. Throug h s oftw are routine
(by using bit-set and bit-reset on I/O line) a clock
can be generated allowing I ²C-bus to work i n mas-
ter mode.
When implementing an I²C-bus protocol, the start
condition can be detected by setting the processor
into a wait for start c on dition by enablin g the inter-
rupt of the I/O port used for the Sin line. This frees
the processor from p olling the Sin and SCL lines.
After the transmission/reception the processor has
to poll for the STOP condition .
In slave mode the user software can slow down
the SCL clock frequency by simply putting the SCL
I/O line in output open-drain mode and writing a
zero into t he corresponding data regist er bit.
As it is possibl e to directly read the Sin pin directly
through the port register, the software can det ect a
difference between internal data and external data
(master mode). Similar condi tion can be applied to
the cl oc k.
Three ( Fo ur) Wi re Se rial B us
It is possible to use a single general purpose I/O
pin (with the corresponding interrupt enabled) as a
chip enable pin. SCL acts as active or passive
clock pin, Sin as data in and S out as data out (four
wire bus). Sin and S out can be connected together
externally t o implem ent three wire bus.
Note:
When the SPI is not used, the three I/O lines (Sin,
SCL, Sout) can be used as normal I/O, with the fol-
lowing limitation: bit Sout cannot be used in open
drain mode as this enables t he shif t register out put
to the port.
It is recommended, in order to avoid spurious in-
terrupts from the SPI, to disable the SPI interrupt
(the default state after reset) i.e. no write must be
made to t he 8-bi t shif t regist er. An explicit interrupt
disable may be made in software by a dummy
write to the SPI interrupt disable register.
SPI Data/Shift Register
Address: DDh - Read/Write (SDSR)
A write into this regis ter enables SPI Interrupt after
8 clock pulses.
SPI Interrupt Disable Register
Address: C2h - Read/Writ e (SIDR)
A dummy write to this register disables SPI Inter-
rupt.
70
D7 D6 D5 D4 D3 D2 D1 D0
70
D7 D6 D5 D4 D3 D2 D1 D0
1102
57/78
ST62T80B/E80B
4.7 LCD CONTROLL ER-DRIVER
On-chip LCD driver includes all features required
for LCD driving, including multiplexing of the com-
mon plates. Multiplexing allows to increase display
capability without increasing the number of seg-
ment outputs. In that case, the display c apability is
equal to the product of the number of common
plates with t he number of segment outputs.
A dedicated LCD RAM is used to store the pattern
to be displayed while control logic generates ac-
cordingly all the waveforms sent onto the segment
or common outputs. Segments voltage supply is
MCU supply independant, and included driving
stages allow direct connection to the LCD panel.
The multiplexing ratio (Number of common plates)
and the base LCD frame frequency is software
configurable to achieve the best trade-off con-
trast/display capability for each display panel.
The 32Khz clock used for the LCD controller is
derivated from t he MCU’s internal clock and t here-
fore does not require a dedicated oscillator. The
division factor is set by the three bits HF0..HF2 of
the LCD Mode Control Register LCDCR as sum-
marized in Table 19 for recommanded oscillator
quartz val ues. In case of osc illator fa ilure, all seg-
ment and common lines are swi tched to ground to
avoid any DC biasing of the LCD elements.
Table 19. Oscillator Selection Bits
Notes:
1. The usage fOSC values different from those
defined in t his table cause the LCD to operate at a
reference frequenc y different from 32.768kHz, ac-
cording to division factor of Tab le 19.
2. It is not recommended to select an internal
frequency l ower than 32.768kHz as the clock su-
pervisor circuit may switch off the LCD peripheral
if lower frequency is det ected.
Figure 31. LCD Block Diagram
MCU
Oscillator
fOSC
HF2 HF1 HF0 Division Factor
0 0 0 Clock disabled: Display off
1.048MHz 0 1 1 32
2.097MHz 1 0 0 64
4.194MHz 1 0 1 128
8.388MHz 1 1 0 256
DATA BUS
CONTROL
REGISTER
LCD
RAM
SEGMENT
DRIVER
COMMON
DRIVER
VOLTAGE
DIVIDER
CONTROLLER
CLOCK
SELECTION
VLCD 1/5 2/5
VLCD VLCD BACKPLANES SEGMENTS
fint
OSC 32kHz
( W hen avai labl e )
VR02099A
32kHz
3/ 5
VLCD 4/5
VLCD
1103
58/78
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
4.7.1 Multiplexing ratio and frame frequency
setting
Up to 16 common plates COM1..COM16 can be
used for multiplexing ratio of 1/8, 1/11 and 1/16.
The selection is made by the bits MUX11 and
MUX16 of the LCDCR as shown in the Table 20.
Table 20. Multiplexing ratio
If the 1/1 multiplexing ratio is chosen, LCD seg-
ments are refreshed with a frame frequency Flcd
derived from 32Khz clock with a division ratio de-
fi ned by the bit s LF0..LF2 of the LCDCR.
When a higher multiplexing ratio is set, refreshment
frequency is decreased acco rdingly (Table 21).
Table 21. LCD Frame Frequency Selecti on
4.7.2 Segmen t and comm on plates driving
LCD panels physical structure requires precise
timings and stepped voltage values on common
and segment outputs. Timings are managed by
the LCD controller, while voltages are generated
through an external resistive bridge. In 1/11 and
1/8 multiplexing mode, VLCD 2/5 and VLDCD 3/5
are shorted as seen on Figure 31.
Figure 32.Bias Config for 1/2 Duty
Note: For display volt ages VLCD < 4.5V the resis-
tivity of the divider may be too high for some appli-
cations (especially using 1/3 or 1/4 duty display
mode). In that case an external resistive divider
must be used to achieve the desired resistivity.
MUX11 MUX16 Display Mode Active backplanes
0 0 1/8 mux.ratio COM1-8
1 0 1/11 mux.ratio COM1-16
0 1 1/16 mux.ratio COM1-16
1 1 - Reserved
LF1 LF0 Base
fLCD
(Hz)
Frame Frequ ency fF (Hz)
1/8
mux.ratio 1/11
mux.ratio 1/16
mux.ratio
0 1 128 128 93 64
1 0 170 170 124 85
0 0 256 256 186 128
1 1 512 512 372 256
1 1 Reserved
VLCD
VL CD 4/5
VL CD 3/5
VL CD 2/5
VL CD 1/5
GND
C4
C3
C2
C1 C1
C2
C3
GND
VLCD
R5
R4
R3
R2
R1
R4
R3
R2
R1
1/4 bias
(1/11, 1/8 MUX)
R2 to R5 should be 1KΩ to 200K Ω
C1 to C5 should be 0µF to 0.3 µF VR001662
VLCD 4/5
VLCD 3/5
VLCD 2/5
VLCD 1/5
(1/ 16 M UX )
1/5 bias
C5
Contrast
VS
VS
Contrast
C4
1104
59/78
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
Address Mapping of the Display Segm ents
The LCD RAM is located in the ST6280B data
space in two pages of 64 bytes from addresses
00h to 3Fh. The LCD f orms a matrix of 56 segment
lines (c olumns) and 8 backplane lines (rows) or 48
segment lines and 11 or 16 backplane lines ac-
cording to the chosen operating mode. Each bit of
the LCD RAM is mapped to one dot of the LCD
matrix, as described in F igure 32. If a b it is set, t h e
corresponding LCD dot is switched on; if it is reset,
the dos is switched of f.
If 1/8 duty c ycle mo de is selected (56 x 8 dot ma-
trix), only RAM page 1 is used for display data
storage. In this case page 2 is compl etely free for
common data storage.
If 1/16 duty cycle mode is selected (48 x 16 dot
matrix), RAM page 1 and 2 are used for display
data storage. In this case addresses 00 to 07 in
both pages are free for common data storage.
If 1/11 duty cycle mode is selected (48 x 11 dot
matrix), RAM pages 1 and 2 are used for display
data storage. In this case addresses 00 to 07 in
both pages and bits 3 to 7 in RAM page 2 are free
for co m mon data storage.
In all display mode s 16 bytes from address 38h to
3Fh in RAM pages 1 a nd 2 are f ree c om m on dat a
storage.
After reset, t he LCD RAM is not initialized and con-
tains arbitrary inf ormation. As the LCD cont rol reg-
ister is reset, the LCD is compl etely switched off.
Fi gure 33 . A ddr essing M app i ng of the LC D RA M
1/11 MUX (48 x 11 = 528 dots LCD-RAM Address
COM1 bit0
00 01 - 07 08 - 37 38 - 3E 3F Page 1
COM2 bit1
COM3 bit2
COM4 bit3
COM5 bit4
COM6 bit5
COM7 bit6
COM8 bit7
COM9 bit0 00 01 - 07 08 - 37 38 - 3E 3F
Page 2
COM10 bit1
COM11 bit2
COM12 bit3 00 01 - 07 08 - 37 38 - 3E 3F 5bitx48
free data
storage
COM13 bit4
COM14 bit5
COM15 bit6
COM16 bit7 S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
12-89-56
16 bytes free for
data storage 16 bytes free for
data storage
1105
60/78
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
Addressing Mapping of the LCD RAM (Cont’d)
Addressing Mapping of the LCD RAM (Cont’d)
1/8 MUX (56 x 8 = 448 dots LCD-RAM Address
COM1 bit0
00 01 - 07 08 - 37 38 - 3E 3F Page 1
COM2 bit1
COM3 bit2
COM4 bit3
COM5 bit4
COM6 bit5
COM7 bit6
COM8 bit7
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
12-89-56
LCD RAM Page 2: 64 bytes free for data storage 16 bytes free for
data storage
1/16 MUX (48 x 16 = 768 dots LCD-RAM Address
COM1 bit0
00 01 - 07 08 - 37 38 - 3E 3F Page 1
COM2 bit1
COM3 bit2
COM4 bit3
COM5 bit4
COM6 bit5
COM7 bit6
COM8 bit7
COM9 bit0 00 01 - 07 08 - 37 38 - 3E 3F
Page 2
COM10 bit1
COM11 bit2
COM12 bit3 00 01 - 07 08 - 37 38 - 3E 3F
COM13 bit4
COM14 bit5
COM15 bit6
COM16 bit7 S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
12-89-56
16 bytes free for
data storage 16 bytes free for
data storage
1106
61/78
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
4.7.3 Stand b y or STOP operation mo de
No clock from the main oscillator is available in
STOP mode for the LCD controller, and the con-
troller is switched off when the STOP instruction is
executed. All segment and common l ines are then
switched to ground to avoid any DC biasing of the
LCD elements .
Operation in STOP mode remain possible by
switching to the OSC32Khz, by setting the
HF0..HF2 bit of LCDCR accordingly (Table 22).
Care must be taken for the oscillator switching that
LCD function change is only effective at the end of
a frame. Therefore it must be guaranteed that
enough clock pulses are deliv ered before enteri ng
into STOP mode. Otherwise the LCD function is
switched off at STOP inst ruction execution.
Table 22. Oscillator Source Sel ection
4.7.4 LCD Mo de Control Register (LCDCR)
Address: DCh - Read/Write
Bits 7-6 = MUX16, MUX11.
Multiplexing ratio se-
lect bits
. The se bits sele ct the num ber of common
backplanes used by the LCD control.
Bits 5-3 = HF0, HF1, HF2.
Oscillator select bits
.
These bits allow the LCD c ontroller to be suppli ed
with the correct frequency when different high
main oscillator frequencies are selected as system
clock. Table 19 shows the set-up for di fferent clock
crystals.
Bits 2 = Reserved.
Bits 1-0 = LF 0, LF1.
Base frame frequ ency select
bits.
These bits control the LCD b ase operational
frequency of the LCD common lines.
LF0, LF1 define the 32kHz division factor as
shown in Table 23
Table 23. 32kHz Division Factor for Base
Frequency Selection
HF2 HF1 HF0 Division Factor
0 0 0 Clock disabled: Display off
0 0 1 Auxiliary 32kHz oscillator
0 1 0 Reserved
1 1 1 Reserved
Others Division from MCU fINT
70
MUX16 MUX11 HF2 HF1 HF0 - LF1 LF0
LF1 LF0 32kHz Division Factor
0 0 512
0 1 386
1 0 256
1 1 192
0 0 128
1107
62/78
ST62T80B/E80B
5 SOFTW AR E
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the val ue of the bit when the SET
or RES i nstr uctio n is processe d.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram spac e c ontains t he inst ructions whi ch are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and In-
put/Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
sta nts). Sta ck sp ace contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in t he location which follows the opcode. Di-
rect addressing allows the user to direct ly address
the 256 bytes in Data Space mem ory with a single
two-byte instruction.
Sh or t D ir ect . T he core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the sel ection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h ar e
also indirect registers).
Extended. In the extended add ressing m ode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative . The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perf orm a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction . If the condition is not true , the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whe ther the branch is a f orward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to th e address of t he rel ative inst ruc tion to
obtain the address of the branch.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte i n whi ch the specified bit must be
set or cleared. Thus, any bi t in the 256 locations of
Data spac e memory can be set or cleared.
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is th ree-byte long. T he bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the rang e of -127 to + 128. This
displacement can be determined using a label,
which is converted by the assembler.
Indirect. In the indirect addressing mode, t he byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indi rect reg-
ister is selected by the bit 4 of the opc ode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mod e, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
1108
63/78
ST62T80B/E80B
5.3 INSTRUCTION SET
The ST6 c ore offers a s et of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipu lation. The following par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Loa d & S tore. These instru ctions use o ne, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory us ing
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the ot her i s always
immediat e data.
Table 24. Load & Store Instructions
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in RO M memory)
rr. Da t a space register
∆. Affected
* . Not A ff ected
Instruction Addressing Mode Bytes Cycles Flags
ZC
LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *
1109
64/78
ST62T80B/E80B
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand i s always the acc umulator whil e
the other can be either a data space memory con-
tent or an immed iate v al ue i n rel ation with t he ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the ac cumulator.
Table 25. Arithmetic & Logic Instruction s
Notes:
X,Y.Indirect Re gi ster Poi nters, V & W Short D i rect Reg i st ersD. Af fected
# . Immediate data (stored in ROM memory)* . Not Affected
r r . Data space register
Instruction Addressing Mode Bytes Cycles Flags
ZC
ADD A, (X) Indirect 1 4 ∆∆
ADD A, (Y) Indirect 1 4 ∆∆
ADD A, rr Direct 2 4 ∆∆
ADDI A, #N Immediate 2 4 ∆∆
AND A, (X) Indirect 1 4 ∆∆
AND A, (Y) Indirect 1 4 ∆∆
AND A, rr Direct 2 4 ∆∆
ANDI A, #N Immediate 2 4 ∆∆
CLR A Short Direct 2 4 ∆∆
CLR r Direct 3 4 * *
COM A Inherent 1 4 ∆∆
CP A, (X) Indirect 1 4 ∆∆
CP A, (Y) Indirect 1 4 ∆∆
CP A, rr Direct 2 4 ∆∆
CPI A, #N Immediate 2 4 ∆∆
DEC X Short Direct 1 4 ∆*
DEC Y Short Direct 1 4 ∆*
DEC V Short Direct 1 4 ∆*
DEC W Short Direct 1 4 ∆*
DEC A Direct 2 4 ∆*
DEC rr Direct 2 4 ∆*
DEC (X) Indirect 1 4 ∆*
DEC (Y) Indirect 1 4 ∆*
INC X Short Direct 1 4 ∆*
INC Y Short Direct 1 4 ∆*
INC V Short Direct 1 4 ∆*
INC W Short Direct 1 4 ∆*
INC A Direct 2 4 ∆*
INC rr Direct 2 4 ∆*
INC (X) Indirect 1 4 ∆*
INC (Y) Indirect 1 4 ∆*
RLC A Inherent 1 4 ∆∆
SLA A Inherent 2 4 ∆∆
SUB A, (X) Indirect 1 4 ∆∆
SUB A, (Y) Indirect 1 4 ∆∆
SUB A, rr Direct 2 4 ∆∆
SUBI A, #N Immediate 2 4 ∆∆
1110
65/78
ST62T80B/E80B
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 26. Conditional Branch Instructions
Notes:
b. 3-bit address rr. Dat a space registe r
e. 5 bi t s i gned displ aceme nt in the range -15 to +16 < F128M> ∆ . Affected. The tested bit is shifted into carry.
ee. 8 bit si gned displ aceme nt in the range -126 to +1 29 * . Not Affec t ed
Table 27. Bit Manipulation Instructions
Notes:
b. 3-bit address; * . Not<M> Affected
rr. Da t a space register;
Table 28. Control Instructions
Notes:
1. This ins t ruction i s deac tivated<N>and a WAIT i s automatical l y ex ecuted in st ead of a STOP if the watchd og functi on i s selected.
∆ . Affected
*. Not Affected
Table 29. Jump & Call Instruc tions
Notes:
abc. 12-bit address;
* . Not A ff ected
Instruction Branch If Bytes Cycles Flags
ZC
JRC e C = 1 1 2 * *
JRNC e C = 0 1 2 * *
JRZ e Z = 1 1 2 * *
JRNZ e Z = 0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆
Instruction Addressing Mode Bytes Cycles Flags
ZC
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Instruction Addressing Mode Bytes Cycles Flags
ZC
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Instruction Ad dressing Mode Bytes Cycl es Flags
ZC
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
1111
66/78
ST62T80B/E80B
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW 0
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111
LOW
HI HI
0
0000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 0
0000
e abc e b0,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
1
0001
2 JRNZ4 CALL2 JRNC5 JRS2 JRZ4 INC2 JRC4 LDI 1
0001
e abc e b0,rr,ee e x e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2
0010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP 2
0010
e abc e b4,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
3
0011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI 3
0011
e abc e b4,rr,ee e a,x e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
4
0100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD 4
0100
e abc e b2,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
5
0101
2 JRNZ4 CALL2 JRNC5 JRS2 JRZ4 INC2 JRC4 ADDI 5
0101
e abc e b2,rr,ee e y e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
6
0110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC 6
0110
e abc e b6,rr,ee e # e (x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
7
0111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 7
0111
e abc e b6,rr,ee e a,y e #
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
8
1000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr,ee e # e (x),a
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
9
1001
2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 9
1001
e abc e b1,rr,ee e v e #
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
A
1010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND A
1010
e abc e b5,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
B
1011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI B
1011
e abc e b5,rr,ee e a,v e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
C
1100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB C
1100
e abc e b3,rr,ee e # e a,(x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
D
1101
2 JRNZ4 CALL2 JRNC5 JRS2 JRZ4 INC2 JRC4 SUBI D
1101
e abc e b3,rr,ee e w e a,nn
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
E
1110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC E
1110
e abc e b7,rr,ee e # e (x)
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
F
1111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC F
1111
e abc e b7,rr,ee e a,w e #
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
Abbreviations for Addressing Modes: Leg end:
dir Dir ect # Indica te s Illega l Instr uctions
sd Short Direct e 5 Bit Displ aceme nt
imm I m m edi ate b 3 Bit Addres s
inh Inhe rent rr 1 byt e datasp ace address
ext Extended nn 1 byt e i m m edi ate dat a
b.d Bit Direc t abc 12 bit address
bt Bit Test ee 8 bit Dis pl acement
pcr Program Counter Relative
ind Indirect
2JRC
e
1prc
Mnemonic
Addressin g Mode
Bytes
Cycle
Operand
1112
67/78
ST62T80B/E80B
Opcode Map Summary (Continued)
LOW 8
1000 9
1001 A
1010 B
1011 C
1100 D
1101 E
1110 F
1111
LOW
HI HI
0
0000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD 0
0000
e abc e b0,rr e rr,nn e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind
1
0001
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 1
0001
e abc e b0,rr e x e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2
0010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP 2
0010
e abc e b4,rr e a e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
3
0011
2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 CP 3
0011
e abc e b4,rr e x,a e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
4
0100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD 4
0100
e abc e b2,rr e e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
5
0101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD 5
0101
e abc e b2,rr e y e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
6
0110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC 6
0110
e abc e b6,rr e e (y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
7
0111
2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 INC 7
0111
e abc e b6,rr e y,a e rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
8
1000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr e # e (y),a
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
9
1001
2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 9
1001
e abc e b1,rr e v e rr,a
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
A
1010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND A
1010
e abc e b5,rr e a e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
B
1011
2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 AND B
1011
e abc e b5,rr e v,a e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
C
1100
2 JRNZ4 JP2 JRNC4 RES2 JRZ2 RET2 JRC4 SUB C
1100
e abc e b3,rr e e a,(y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
D
1101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB D
1101
e abc e b3,rr e w e a,rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
E
1110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC E
1110
e abc e b7,rr e e (y)
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
F
1111
2 JRNZ4 JP2 JRNC4 SET2 JRZ4 LD2 JRC4 DEC F
1111
e abc e b7,rr e w,a e rr
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
Abbreviations for Addressing Modes: Leg end:
dir Dir ect # Indica te s Illega l Instr uctions
sd Short Direct e 5 Bit Displ aceme nt
imm I m m edi ate b 3 Bit Addres s
inh Inhe rent rr 1 byt e datasp ace address
ext Extended nn 1 byt e i m m edi ate dat a
b.d Bit Direc t abc 12 bit address
bt Bit Test ee 8 bit Dis pl acement
pcr Program Counter Relative
ind Indirect
2JRC
e
1prc
Mnemonic
Addressin g Mode
Bytes
Cycle
Operand
1113
68/78
ST62T80B/E80B
6 ELE CTRIC AL CHARACT ERI S TI CS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than VDD.
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (VDD
or VSS).
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from: Tj= TA + PD x Rth JA
Where:TA = Ambient Temperature.
RthJA = Pµackage thermal r esistance
(junction-to ambient).
PD = Pint + Pport.
Pint = I DD x VDD (chip internal power).
Pport = P ort power dissipation (deter-
mined by the user).
Notes:
- Stresses above those listed as "absolute max imum ratings" may cause permanent damage to the device. This is a stress rating only and
func tiona l o peration of the device at these condit i ons is not implied. Ex posure to maximum rating conditi ons for ext ended periods may
affect device reliability.
- (1) Within thes e limits, clamping diodes are guarantee to be not conductive. Voltages outside these limit s are authorised as long as injection
current is kept within the specification.
Symbol Parameter Value Unit
VDD Supply Voltage -0.3 to 7.0 V
VIInput Voltage VSS - 0.3 to VDD + 0.3(1) V
VOOutput Voltage VSS - 0.3 to VDD + 0.3(1) V
IOCurrent Drain per Pin Excluding VDD, VSS ±10 mA
IVDD Total Current into VDD (source) 50 mA
IVSS Total Current out of VSS (sink) 50 mA
Tj Junction Temperature 150 °C
TSTG Storage Temperature -60 to 150 °C
1114
69/78
ST62T80B/E80B
6.2 RECOMMENDE D OPERATING CONDITI ONS
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversi on. For a -1m A injection, a maximum 10 KΩ is recommanded.
2. An oscillator frequency above 1MHz is recommended for reliable A/D results.
Figure 3 4. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VO LTAGE (V DD)
The shaded area is outside the recommended operating range; device funct ionality is not guaranteed under these conditions.
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
TAOperating Temperat ure 6 Suffix Version
1 Suffix Version -40
085
70 °C
VDD Operating Supp ly Vo ltage fOSC = 2MHz
fosc= 8MHz 3.0
4.5 6.0
6.0 V
fOSC Oscillator Frequency2) VDD = 3V
VDD = 4.5V 0
02.0
8.0 MHz
IINJ+ Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (negative) VDD = 4.5 to 5.5V -5 mA
8
7
6
5
4
3
2
1
2.533.544.555.56
SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
FUNCTIONAL ITY IS NOT
GUARANTEED IN
THIS AREA
1115
70/78
ST62T80B/E80B
6.3 DC ELECTRICAL CHARACTERISTICS
(TA = -40 to +85°C unless othe rw ise specified)
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals runnin g
(3) All peripherals i n stand- by
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
VIL Input Low Level Voltage
All Input pins VDD x 0.3 V
VIH Input High Level Voltage
All Input pins VDD x 0.7 V
VHys Hysteresis Voltage (1)
All Input pins VDD= 5V
VDD= 3V 0.2
0.2 V
VOL
Low Level Output Voltage
All Output pins VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 5mA 0.1
0.8 V
Low Level Output Voltage
20 mA Sink I/O pins VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +10mA
VDD= 5.0V; IOL = +20mA
0.1
0.8
1.3
VOH High Level Output Voltage
All Output pins VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -5.0mA 4.9
3.5 V
RPU Pull-up Resistance All Input pins 40 100 200 ΚΩ
RESET pin 150 350 900
IIL
IIH
Input Leakage Current
All Input pins but RESET VIN = VSS (No Pull-Up configured)
VIN = VDD 0.1 1.0 µA
Input Leakage Current
RESET pin VIN = VSS
VIN = VDD -8 -16 -30
10
IDD
Supply Current in RESET
Mode VRESET=VSS
fOSC=8MHz 7mA
Supply Current in
RUN Mode (2) VDD=5.0V fINT=8MHz 7 mA
Supply Current in WAIT
Mode (3) VDD=5.0V fINT=8MHz 2 mA
Supply Current in STOP
Mode (3) ILOAD=0mA
VDD=5.0V 10 µA
1116
71/78
ST62T80B/E80B
6.4 AC ELECTRICAL CHARACTERISTICS
(TA = -40 to +85°C unless othe rw ise specified)
Notes:
1. Period for which VDD has to be connect ed at 0V to all ow inte rnal Re set function at next pow er-up.
6.5 A/D CONVERTER CHARACT ERIS TICS
(TA = -40 to +85°C unless othe rw ise specified)
Notes:
1. Noise at AVDD, AVSS <10mV
2. With oscill ator f requencies less t han 1MH z, th e A/D Converter acc uracy is decrea sed. .
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
tREC Supply Recovery Time (1) 100 ms
TWR Minimum Pulse Width (VDD = 5V)
RESET pin
NMI pin 100
100 ns
TWEE EEPROM Write Time TA = 25°C
TA = 85°C 5
10 10
20 ms
Endurance EEPROM WRITE/ERASE Cycle 300,000 1 million cycles
Retention EEPROM Data Retention TA = 55°C 10 years
CIN Input Capacitance All Inputs Pins 10 pF
COUT Output Capacitance All Outputs Pins 10 pF
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
Res Resolution 8 Bit
ATOT Total Accuracy (1) (2) fOSC > 1.2MHz
fOSC > 32kHz ±2
±4LSB
tCConversion Time fOSC = 8MHz 70 µs
ZIR Zero Input Reading Conversion result when
VIN = VSS 00 Hex
FSR Full Scale Reading Conversion result when
VIN = VDD FF Hex
ADIAnalog Input Curre nt Durin g
Conversion VDD= 4.5V 1.0 µA
ACIN An alog Input Capa citanc e 2 5 pF
1117
72/78
ST62T80B/E80B
6.6 TIMER CHARACTERISTICS
(TA = -40 to +85°C unless othe rw ise specified)
Note*: When available.
6.7 SPI CHARACTERISTICS
(TA = -40 to +85°C unless othe rw ise specified)
6.8 LCD ELECTRICAL CHARACTERISTICS
(TA = -40 to +85°C unless othe rw ise specified)
Notes:
1. The DC offset refers to all segment and common outputs. It is the difference between the measured voltage value and nominal va lu e fo r
ev e ry vo ltage le vel.
2. An exte rnal resi stor net work is requir ed when VL CD is lower then 4 .5 V.
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
fIN Input Frequency on TIMER Pin* MHz
tWPulse Width at TIMER Pin* VDD = 3.0V
VDD >4.5V 1
125 µs
ns
f
INT
8
----------
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
FCL Clock Frequency Applied on Scl 1 MHz
tSU Set-up Time Applied on Sin 50 ns
thHold Time Applied onSin 100 ns
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
Vos DC Offset Volt age VLCD = Vdd, no load 50 mV
VOH COM High Level, Output Voltage
SEG High Level, Output Voltage I=100µA, VLCD=5V
I=50µA, VLCD=5V 4.5
V
VOL COM Low Level, Output Voltage
SEG Low Level, Output Voltage I=100µA, VLCD=5V
I=50µA, VLCD=5V 0.5
VLCD Display Voltage See Note 2 VDD -0.2 10
1118
73/78
ST62T80B/E80B
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 35. 100-Pin Plastic Quad Flat Package Short Footpri nt
Figure 36. 100-Pin Cerami c Qua d Flat Package Lo ng Footprint
PQFP100
Dim mm inches
Min Typ Max Min Typ Max
A3.40 0.134
A1 0.25 0.010
A2 2.55 2.80 3.05 0.100 0.110 0.120
B0.22 0.38 0.009 0.015
C0.13 0.23 0.005 0.009
D22.95 23.20 23.45 0.904 0.913 0.923
D1 19.90 20.00 20.10 0.783 0.787 0.791
D3 18.85 0.742
E16.95 17.20 17.45 0.667 0.677 0.687
E1 13.90 14.00 14.10 0.547 0.551 0.555
E3 12.35 0.486
e0.65 0.026
K0° 7°
L0.65 0.80 0.95 0.026 0.031 0.037
L1 1.60 0.063
Number of Pins
N 100 ND 30 NE 20
Dim mm inches
Min Typ Max Min Typ Max
A3.24 0.128
A1 0.20 0.008
B0.22 0.35 0.38 0.009 0.014 0.015
C0.13 0.15 0.23 0.005 0.006 0.009
D23.35 23.90 24.45 0.919 0.941 0.963
D1 19.57 20.00 20.43 0.770 0.787 0.804
D3 18.85 0.742
E17.35 17.90 18.45 0.683 0.705 0.726
E1 13.61 14.00 14.39 0.536 0.551 0.567
E3 12.35 0.486
e 0.65 0.026
G13.75 14.00 14.25 0.541 0.551 0.561
G1 19.75 20.00 20.25 0.778 0.787 0.797
G2 1.17 0.046
L0.35 0.80 0.014 0.031
Ø8.89
Number of Pins
N 100
CQFP100W
1119
74/78
ST62T80B/E80B
GENERAL INFORMATION (Cont’d)
7.2 PACKAGE THERMAL CHARACTERISTIC
7.3 .ORDERING INFORMATION
Table 30. O TP/EPROM VERSION ORDERING INFORMATION
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
RthJA Thermal Resistance PQFP100 70 °C/W
CQFP100W 70
Sales Type Program
Memory (Bytes) I/O Temperature Range Package
ST62E80BG1 7948 (EPROM) 22 0 to 70° C CQFP100 W
ST62T80BQ6 7948 (OTP) -40 to 85°C PQFP100
1120
September 1998 75/78
Rev. 2.4
ST6280B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
■3.0 t o 6.0V Supply Operating Range
■8 MHz Maximum Clock Frequency
■-40 to +85°C Operating Temperature Range
■Run, Wait and Stop Modes
■5 Interrupt Vectors
■Look-up Table capability in Program Memory
■Data Storage in Program Memory:
User selectable size
■Data RAM: 192 bytes
■Data EEPRO M: 128 by tes
■22 I/ O pi ns, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt genera tion
– Open-drain or push-pull output
– Analog Input
– LCD segments (8 combiport lines)
■4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■Two 8-bit Timer/Counter with 7-bit
programmable prescaler
■Digital Watchdog
■8-bit A/D Converter with 12 analog inputs
■8-bit Synchronous Peripheral Interface (SPI)
■8-bit Asynchronous Peripheral Interface (UART)
■LCD driver with 45 segment outputs, 4
backplane outputs and selectable multiplexing
ratio.
■32 kHz osc illator fo r sta n d- by LC D ope r a tio n
■Powe r Supply Supervisor (PSS)
■On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
■One ex ternal Non-Maskable Interrupt
■ST6240-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
(See end of Datasheet for Ordering Information)
PQFP100
DEVICE ROM
(Bytes) I/O Pins
ST62T80B 7948 22
1121
76/78
ST6280B
1 G ENERAL DESCR IPTION
1.1 INTRODUCTION
The ST6280B is mask program med ROM version
of ST62T80B OTP dev ices.
They offer the same functionality as OT P devices,
selecting as ROM options the options defined in
the programmable option byte of the OT P version.
Figure 1 . Programm i ng wave form
1.2 ROM READOUT PROTECTION
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin.
Figure 2. Programming Circuit
No t e: ZPD15 is used for ov ervol tage prot ection
0.5s min
TEST
15
14V typ
10
5
TEST
100mA
4mA typ
VR02001
max
150 µs typ
t
VR02003
TEST
5V
100nF
47mF
PROTECT
100nF
VDD
VSS
ZPD15
15V
14V
1122
77/78
ST6280B
ST6280B MICROCONTROLLER OPTION LIST
Customer
Address
Contact
Phone No
Reference
STMicroel e ctroni cs re fere n ce s
Device: [ ] ST6280B
Package: [ ] Plastic Quad Flat Package (Tape & Reel)
Temperature Range: [ ] 0°C to + 70°C[ ] - 40°C to + 85°C
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum charac ter count: PQFP100: 10
Watchdog Selection: [ ] Software Activation
[ ] Hardware Acti va tio n
NMI Pull-Up Selection: [ ] Yes [ ] No
ROM Readout Protection:[ ] Standard (Fuse cannot be blown)
[ ] Enab led (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.
Comments :
Number of segments and back plane s used:
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes . . . . . . . . . . . . . . . . . .
Signature
Date
1123
78/78
ST6280B
1.3 ORDERING INFORMATION
The following s ection dea ls with t he procedure for
transfer of c ustomer codes to STM icroelectronics.
1.3.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal fil e gener-
ated by the development tool. All unused bytes
must be set to FFh.
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended.
1.3.2 Listing Generation and Veri fication
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
of the specific customer mask.
The STMicroelect ronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Table 1. ROM Memory Map for ST6280B
Table 2. ROM version Ord eri ng Inform ation
Informatio n furnished is belie ved to be a ccu rate and reliable. Ho wever, STMicroelectronics assumes no res ponsibility for the c onsequences
of us e of such in fo rma ti on nor fo r an y inf ri ng eme nt of p a tent s o r ot her ri ght s of t hi rd part i es w hic h m ay re sul t from i ts us e. No lic ense is granted
by i m pl i cation or oth erwise under any patent o r paten t rights of STMi croelectronic s. Specifications m entioned in this publi cation are s ubj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST l ogo is a regi st ered tradem ark of STMicroelectron i cs
1998 STMicroelectronics - All Rights Reserved.
Pur ch ase of I2C Components by STMicroelectronics convey s a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STM i croelectronics Grou p of Companies
Aus tralia - B razil - Canada - C h i na - Fr ance - Germany - It al y - Japan - Ko rea - Malaysia - Malta - Mexico - Mo rocco - The Nether l ands -
Singap ore - Spain - Sweden - S wi t zerlan d - T ai wan - Th ai l a nd - Uni ted Kingdom - U.S .A.
http://www.st.com
ROM Page Device Address Description
Page 0 0000h-007Fh
0080h-07FFh Reserved
User ROM
Page 1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Page 2 0000h-000Fh
0010h-07FFh Reserved
User ROM
Page 3 0000h-000Fh
0010h-07FFh Reserved
User ROM
Sales Type ROM I/O Temperature Range Package
ST6280BQ1/XXX
ST6280BQ6/XXX 7948 22 0 to +70°C
-40 to 85°C PQFP100
1124
