PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Version 1.2 June 2006 Website www.plxtech.com Technical Support www.plxtech.com/support Phone 408 774-9060 800 759-3735 FAX 408 774-2169 Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 June, 2006 PLX Technology, Inc. Copyright Information Copyright (c) 2005 - 2006 PLX Technology, Inc. All rights reserved. The information in this document is proprietary to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Order Number: 8111BB-SIL-DB-P1-1.2 ii PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Revision History Revision History Version Date 1.0 November, 2005 Initial Production release Silicon Revision BB. December, 2005 Table 16-2 - Corrected JTAG IDCODE values in Version column. Table 17-1 - Removed "Ambient Temperature" row. Table 18-2 - Corrected 161-Ball FBGA Package ball pitch dimension. Global (2 places) - Changed "PCI Express host" to "PCI Express Root Complex." Section 5.1.1.2 - Added note regarding No Snoop and Relaxed Ordering bits. Register 14-56, (Offset 68h; DEVCTL) PCI Express Device Control, Bits [3:0] - Added "Valid only in Forward Bridge mode" to bit descriptions. Register 14-82, (Offset 101Ch; POWER) Power - Added "(Forward Bridge Mode Only" to register title. Figure 18-3 - Corrected title. June, 2006 Reorganized Chapter 2, "Ball Descriptions." Other changes include: * Clarified reset for GPIO[3:2] in Forward and Reverse modes. * WAKEIN# definition, added "In Forward Bridge mode, pull WAKEIN# high." * IDSEL definitions, replaced "In Forward Bridge mode, IDSEL is grounded or pulled up to 3.3V" with "It is recommended to ground IDSEL in Forward Bridge mode to prevent it from floating." * PCIRST# definitions, changed "OD" to "TP". * PCLKO definitions, added "PCLKO can be connected to PCLKI to drive PCLKI." * Global - Corrected PME# references to PMEIN# and PMEOUT#. * Global - Corrected PEX_PERST# references to PERST#. Section 4.1.1.1, replaced last two sentences of second paragraph with "PCIRST# is asserted for at least 2 ms after the power levels are valid." Added new Chapter 9, "Bridge Operation," and renumbered all subsequent chapters. Corrected Table 18-2 (formerly Table 16-2) Version column values to reflect BB silicon revision. Registers split into two chapters - one for Forward Bridge mode (Chapter 15), the other for Reverse Bridge mode (Chapter 16). Register chapters, PCI Control register, bit 26, changed first sentence describing action when cleared. Chapter 19, "Electrical Specifications," changes (formerly Chapter 17): * Replaced Sections 19.1 and 19.2 with Section 19.1, "Power Sequence," and Section 19.1.1, "VIO." * Added new Table 19-2, "Package Thermal Resistance," and renumbered all subsequent tables. * Added Section 19.4.2, "SerDes Interface DC Characteristics." * Corrected VDD3.3 signal reference in Table 19-4 for VIH. Changed "TLB" references to "TLP". Miscellaneous changes for readability. Miscellaneous corrections. 1.1 1.2 Description of Changes PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 iii Data Book PLX Technology, Inc. Preface This document contains material that is proprietary to PLX. Reproduction without the express written consent of PLX is prohibited. All reasonable attempts are made to ensure the contents of this document are accurate; however no liability, expressed or implied is guaranteed. PLX reserves the right to modify this document, without notification, at any time. This PLX document is periodically updated as new information is made available. Scope This document describes the PEX 8111 bridge operation and provides operational data for customer use. Audience This data book provides the functional details of PLX Technology ExpressLaneTM PEX 8111 PCI Express-to-PCI Bridge, for hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the documents referenced below. * PLX Technology, Inc. 870 Maude Ave., Sunnyvale, CA 94085 USA Tel: 408 774-9060 or 800 759-3735, Fax: 408 774-2169, http://www.plxtech.com - PEX 8111 Quick Start Design Note * PCI Special Interest Group (PCI-SIG) 3855 SW 153rd Drive, Beaverton, OR 97006 USA Tel: 503 619-0569, Fax: 503 644-6708, http://www.pcisig.com - PCI Local Bus Specification, Revision 3.0 - PCI Local Bus Specification, Revision 2.2 - PCI to PCI Bridge Architecture Specification, Revision 1.1 - PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Express Base Specification, Revision 1.0a - PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 - PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a * The Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA Tel: 800 678-4333 (domestic only) or 732 981-0060, Fax: 732 981-1721, http://www.ieee.org - IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 - IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions iv PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Supplemental Documentation Abbreviations Supplemental Documentation Abbreviations Note: In this data book, shortened titles are provided to the previously listed documents. The following table lists these abbreviations. Abbreviation Document PCI r3.0 PCI Local Bus Specification, Revision 3.0 PCI r2.2 PCI Local Bus Specification, Revision 2.2 PCI-to-PCI Bridge r1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Power Mgmt. r1.1 PCI Bus Power Management Interface Specification, Revision 1.1 PCI Express r1.0a PCI Express Base Specification, Revision 1.0a PCI Express-to-PCI/ PCI-X Bridge r1.0 PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture Data Assignment Conventions Data Width PEX 8111 Convention 1 byte (8 bits) Byte 2 bytes (16 bits) Word 4 bytes (32 bits) DWORD/DWord/Dword PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 v Data Book PLX Technology, Inc. Terms and Abbreviations The following table lists common terms and abbreviations used in this document. Terms and abbreviations defined in the PCI Express r1.0a are not included in this table. Terms and Abbreviations Terms and Abbreviations vi Definition # Indicates an Active-Low signal. ACK Acknowledge Control Packet. A control packet used by a destination to acknowledge data packet receipt. A signal that acknowledges the signal receipt. ADB Allowable Disconnect Boundary. ADQ Allowable Disconnect Quantity. In PCI Express, the ADQ is a buffer size. Used to indicate memory requirements or reserves. BAR Base Address Register. Byte 8-bit quantity of data. CA Completion with Completer Abort status. CFG Access initiated by PCI Configuration transactions on the primary bus. Clock cycle One period of the PCI Bus clock. Completer Device addressed by a requester. CRS Configuration Retry Status. CSR Configuration Status register; Control and Status register; Command and Status register DAC Dual Address cycle. A PCI transaction wherein a 64-bit address is transferred across a 32-bit data path in two Clock cycles. Destination Bus Target of a transaction that crosses a bridge is said to reside on the destination bus. DLLP Data Link Layer Packet (originates at the Data Link Layer); can contain Flow Control (FCx DLLPs) acknowledge packets (ACK and NAK DLLPs); and power management (PMx DLLPs). Downstream Transactions that are forwarded from the primary bus to the secondary bus of a bridge are said to be flowing downstream. DWORD 32-bit quantity of data. ECRC End-to-end Cyclic Redundancy Check (CRC) EE Access initiated by the Serial EEPROM Controller during initialization. Endpoints Devices, other than the Root Complex and switches, that are requesters or completers of PCI Express transactions. * Endpoints can be PCI Express endpoints or legacy endpoints. * Legacy endpoints can support I/O and Locked transaction semantics. PCI Express endpoints do not support I/O and Locked transaction semantics. FCP Flow Control Packet devices on each link exchange FCPs, which carry header and data payload credit information for one of three packet types - Posted Requests, Non-Posted Requests, and Completions. Forward Bridge mode The primary bus is closest to the PCI Express Root Complex. host Computer that provides services to computers that connect to it on a network. Considered to be in charge of the other devices connected to the bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Terms and Abbreviations Terms and Abbreviations (Cont.) Terms and Abbreviations Definition HwInit Hardware initialized register or register bit. The register bits are initialized by a PEX 8111 hardware initialization mechanism or PEX 8111 Serial EEPROM register initialization feature. Register bits are Read-Only after initialization and are reset only with a Cold or Warm Reset. I CMOS Input. I/O CMOS Bi-Directional Input Output. Lane Differential signal pair in each direction. Layers PCI Express defines three layers: * Transaction Layer - The primary function of the Transaction Layer is assembly and disassembly of TLPs. The major components of a transaction layer packet (TLP) are Header, Data Payload, and an optional Digest Field. * Data Link Layer - The primary task of the Data Link Layer is to provide link management and data integrity, including error detection and correction. This layer defines the data control for PCI Express. * Physical Layer - The primary value to users is that this layer appears to the upper layers to be PCI. It connects the lower protocols to the upper layers. MM Access initiated by PCI Memory transactions on the primary or secondary bus, using the address range defined by PCI Base Address 0. MSI Message Signaled Interrupt. NAK Negative Acknowledge. Non-Posted Transaction A Memory Read, I/O Read or Write, or Configuration Read or Write that returns a completion to the master. NS No Snoop. O CMOS Output. OD Open Drain Output. Originating Bus Master of a transaction that crosses a bridge is said to reside on the originating bus. Packet Types There are three packet types: * TLP, Transaction Layer Packet * DLLP, Data Link Layer Packet * PLP, Physical Layer Packet PCI PCI Compliant PCI Peripheral Component Interconnect. A PCI Bus is a high-performance bus that is 32 bits or 64 bits wide. It is designed to be used with devices that contain high-bandwidth requirements (such as, the display subsystem). It is an I/O bus that has the ability to be dynamically configured. PCI Master (Initiator) Drives the Address phase and transaction boundary (FRAME#). Initiates a transaction and drives data handshaking (IRDY#) with the target. PCI Target Claims the transaction by asserting DEVSEL# and handshakes the transaction (TRDY#) with the initiator. PCI Transaction Read, Write, Read Burst, or Write Burst operation on the PCI Bus. Includes an Address phase, followed by one or more Data phases. PCI Transfer During a transfer, data is moved from the source to the destination on the PCI Bus. TRDY# and IRDY# assertion indicates a Data transfer. PCIE PCI Express. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 vii Data Book PLX Technology, Inc. Terms and Abbreviations (Cont.) Terms and Abbreviations Port Definition Interface between a PCI Express component and the link. Consists of transmitters and receivers. * An ingress port receives a packet. * An egress port transmits a packet. * A link is a physical connection between two devices that consists of xN lanes. * An x1 link consists of one Transmit and one Receive signal, where each signal is a differential pair. This is one lane. There are four lines or signals in an x1 link. ! $IFFERENTIAL 0AIR ! $IFFERENTIAL 0AIR IN EACH DIRECTION ONE ,ANE 4HIS IS AN X ,INK 4HERE ARE FOUR SIGNALS viii Posted Transaction Memory write that does not return a completion to the master. Primary Bus Bus closest to the PCI Express Root Complex (Forward Bridge mode) or the PCI host CPU (Reverse Bridge mode). PU Signal is internally pulled up. QoS Quality of Service. RC Root Complex. RCB Read Boundary Completion. Request packet A non-posted request packet transmitted by a requester has a completion packet returned by the associated completer. A posted request packet transmitted by a requester has no completion packet returned by the completer. Requester Device that originates a transaction or puts a transaction sequence into the PCI Express fabric. Reverse Bridge Mode The primary bus is closest to the PCI host CPU. RO Read-Only register or register bit. Register bits are Read-Only and cannot be altered by software. Register bits are initialized by a PEX 8111 hardware initialization mechanism or PEX 8111 Serial EEPROM register initialization feature. RO Relaxed Ordering. RsvdP Reserved and Preserved. Reserved for future RW implementations. Registers are Read-Only and must return 0 when read. Software must preserve value read for writes to bits. RsvdZ Reserved and Zero. Reserved for future RW1C implementations. Registers are Read-Only and must return 0 when read. Software must use 0 for writes to bits. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Terms and Abbreviations Terms and Abbreviations (Cont.) Terms and Abbreviations Definition RW Read-Write register. Register bits are Read-Write and set or cleared by software to the needed state. RW1C Read-Only Status. Write 1 to clear status register. Register bits indicate status when read; a set bit indicating a status event is cleared by writing 1. Writing 0 to RW1C bits has no effect. RX Received Packet. SC Successful Completion. Secondary Bus The bus farthest from the PCI Express Root Complex (Forward Bridge mode) or the PCI host CPU (Reverse Bridge mode). STRAP Strapping pads (such as, BAR0ENB#, FORWARD, and EXTARB) must be connected to H or L on the board. STS Sustained Three-State Output, Driven High for One CLK before Float. TC Traffic Class. TLP Translation Layer Packet. TP Totem Pole. TS Three-State Bi-Directional. TX Transmitted Packet. Upstream Transactions that are forwarded from the secondary bus to the primary bus of a bridge are said to be flowing upstream. UR Unsupported Request. VC Virtual Channel. WO Write-Only register. Used to indicate that a register is written by the Serial EEPROM Controller. Word 16-bit quantity of data. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 ix Data Book x PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 PCI Express Endpoint Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Data Transfer Pathways . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 2 1 1 1 2 2 2 3 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 Ball Description Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PCI Signal Pull-Up Resistors (Forward Bridge Mode Only) . . . . . . . . . . . . . . . . . . . . . 5 Ball Description - 144-Ball PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.1 PCI Express Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.2 PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.3 Clock, Reset, and Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.4 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.5 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.6 No Connect Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.7 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.8 Ball Tables - 144-Ball PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.9 Physical Ball Assignment - 144-Ball PBGA Package . . . . . . . . . . . . . . . . . . . 16 2.4 Ball Description - 161-Ball FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.1 PCI Express Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.3 Clock, Reset, and Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.4 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.5 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.6 No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.7 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.8 Ball Tables - 161-Ball FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.9 Physical Ball Assignment - 161-Ball FBGA Package . . . . . . . . . . . . . . . . . . . 29 Chapter 3 Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1 3.2 3.3 Chapter 4 Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Initialization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 Forward Bridge Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Forward Bridge Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.1 Fundamental Reset (Cold/Warm Reset) . . . . . . . . . . . . . . . . . . . . . 4.1.1.2 Primary Reset Due to Physical Layer Mechanism (Hot Reset) . . . . 4.1.1.3 Primary Reset Due to Data Link Down . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.4 Secondary Bus Reset by way of Bridge Control Register . . . . . . . . 4.1.1.5 Bus Parking during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Reverse Bridge Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Reverse Bridge Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Reverse Bridge Secondary Bus Reset by way of Bridge Control Register . . . PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 33 33 33 33 34 34 34 35 35 35 xi Contents Chapter 5 PLX Technology, Inc. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.1 Forward Bridge PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Forward Bridge Internally Generated Interrupts . . . . . . . . . . . . . . . . . . . . . . . 5.1.1.1 Virtual Wire Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1.2 Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Reverse Bridge PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Reverse Bridge Internally Generated Interrupts . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 INTx# Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.2 Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Serial EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6.1 6.2 6.3 6.4 Chapter 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Random Read/Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Serial EEPROM Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Serial EEPROM Low-Level Access Routines . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Serial EEPROM Read Status Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Serial EEPROM Write Data Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 Serial EEPROM Read Data Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 I/O Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 ISA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4.1 VGA Palette Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Memory-Mapped I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Memory Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Prefetchable Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Prefetchable Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3.1 Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3.2 Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4 VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 46 46 46 48 49 49 50 50 50 51 52 52 52 54 54 56 56 Configuration Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 8.1 8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 0 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1-to-Type 0 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Type 1-to-Type 1 Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Type 1-to-Special Cycle Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii 41 41 42 43 43 43 43 44 44 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7.1 7.2 Chapter 8 37 37 38 38 39 39 39 39 57 58 58 59 59 60 61 61 62 62 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Contents 8.7 PCI Express Enhanced Configuration Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7.1 Memory-Mapped Indirect (Reverse Bridge Mode Only) . . . . . . . . . . . . . . . . . 8.8 Configuration Retry Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.1 Forward Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.2 Reverse Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 9 Bridge Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 Forward Bridge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Forward Bridge Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Forward Bridge Buffer Size and Management . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Forward Bridge Requester ID and Tag Assignment . . . . . . . . . . . . . . . . . . . . 9.1.4 Forward Bridge PCI Express-to-PCI Forwarding (Downstream) . . . . . . . . . . . 9.1.4.1 Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4.2 Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4.3 Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5 Forward Bridge PCI-to-PCI Express Forwarding (Upstream) . . . . . . . . . . . . . 9.1.5.1 Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5.2 Write Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5.3 Read Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5.4 PCI Express Header Field Formation Rules . . . . . . . . . . . . . . . . . . . 9.1.5.5 Requester ID and Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5.6 Memory Write or Memory Write and Invalidate . . . . . . . . . . . . . . . . 9.1.5.7 Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5.8 Memory Read, Memory Read Line, or Memory Read Line Multiple . 9.1.5.9 I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5.10 I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.6 Forward Bridge PCI Transaction Terminations . . . . . . . . . . . . . . . . . . . . . . . . 9.1.6.1 PCI Master Termination Initiated by PEX 8111 . . . . . . . . . . . . . . . . 9.1.6.2 PCI Master Abort Received by PEX 8111 . . . . . . . . . . . . . . . . . . . . 9.1.6.3 Delayed Write Target Termination Response . . . . . . . . . . . . . . . . . 9.1.6.4 Posted Write Target Termination Response . . . . . . . . . . . . . . . . . . 9.1.6.5 Delayed Read Target Termination Response . . . . . . . . . . . . . . . . . 9.1.6.6 Target Retry Initiated by PEX 8111 . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.6.7 Target Disconnect Initiated by PEX 8111 . . . . . . . . . . . . . . . . . . . . . 9.1.6.8 Target Abort Initiated by PEX 8111 . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Reverse Bridge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Reverse Bridge PCI-to-PCI Express Forwarding (Downstream) . . . . . . . . . . 9.2.1.1 Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 10 63 63 64 64 64 65 66 66 66 67 67 68 70 73 73 73 73 74 74 75 75 76 78 78 79 80 80 81 81 82 82 83 83 84 85 85 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.1 Forward Bridge Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Forward Bridge PCI Express Originating Interface (Primary to Secondary) . 10.1.1.1 Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1.2 PCI Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1.3 PCI Address Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1.4 PCI Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . 10.1.1.5 PCI Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 10.1.1.6 PCI Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . 10.1.1.7 PCI Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 10.1.1.8 PCI Retry Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . 10.1.1.9 PCI Retry Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 87 87 88 88 89 89 89 90 90 90 90 xiii Contents PLX Technology, Inc. 10.1.2 Forward Bridge PCI Originating Interface (Secondary to Primary) . . . . . . . . 91 10.1.2.1 Received PCI Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.1.2.2 Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . 93 10.1.2.3 Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . . 93 10.1.3 Forward Bridge Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.1.3.1 PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . 94 10.1.3.2 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . 94 10.1.4 Forward Bridge "Other" Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.2 Reverse Bridge Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.2.1 Reverse Bridge PCI Express Originating Interface (Secondary to Primary) . 95 10.2.1.1 Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.2.1.2 PCI Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.2.1.3 PCI Address Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10.2.1.4 PCI Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . 96 10.2.1.5 PCI Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 97 10.2.1.6 PCI Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . 97 10.2.1.7 PCI Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 97 10.2.1.8 PCI Retry Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . . 97 10.2.1.9 PCI Retry Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . . 97 10.2.2 Reverse Bridge PCI Originating Interface (Primary to Secondary) . . . . . . . . 98 10.2.2.1 Received PCI Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2.2.2 Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . 100 10.2.2.3 Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . 100 10.2.3 Reverse Bridge Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.2.3.1 PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . 100 10.2.3.2 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . 100 10.2.4 Reverse Bridge PCI Express Error Messages . . . . . . . . . . . . . . . . . . . . . . 101 10.2.5 Reverse Bridge "Other" Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chapter 11 Exclusive (Locked) Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 11.1 Forward Bridge Exclusive Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Forward Bridge Lock Sequence across PEX 8111 . . . . . . . . . . . . . . . . . . . 11.1.2 Forward Bridge PCI Master Rules for Supporting LOCK# . . . . . . . . . . . . . 11.1.3 Forward Bridge Acquiring Exclusive Access across PEX 8111 . . . . . . . . . 11.1.4 Forward Bridge Non-Posted Transactions and Lock . . . . . . . . . . . . . . . . . . 11.1.5 Forward Bridge Continuing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Forward Bridge Completing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Forward Bridge Invalid PCI Express Requests while Locked . . . . . . . . . . . 11.1.8 Forward Bridge Locked Transaction Originating on PCI Bus . . . . . . . . . . . 11.1.9 Forward Bridge PCI Bus Errors while Locked . . . . . . . . . . . . . . . . . . . . . . . 11.1.9.1 PCI Master Abort during Posted Transaction . . . . . . . . . . . . . . . . 11.1.9.2 PCI Master Abort during Non-Posted Transaction . . . . . . . . . . . . 11.1.9.3 PCI Target Abort during Posted Transaction . . . . . . . . . . . . . . . . 11.1.9.4 PCI Target Abort during Non-Posted Transaction . . . . . . . . . . . . 11.2 Reverse Bridge Exclusive Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Reverse Bridge PCI Target Rules for Supporting LOCK# . . . . . . . . . . . . . . 11.2.2 Reverse Bridge Acquiring Exclusive Access across PEX 8111 . . . . . . . . . 11.2.3 Reverse Bridge Completing Exclusive Access . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Reverse Bridge PCI Express Locked Read Request . . . . . . . . . . . . . . . . . 11.2.5 Reverse Bridge Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv 103 103 104 104 104 104 104 105 105 105 105 105 105 105 106 106 106 106 106 106 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Chapter 12 Contents Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.1 Forward Bridge Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 Forward Bridge Link State Power Management . . . . . . . . . . . . . . . . . . . . . 12.1.1.1 Link Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1.2 Link State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Forward Bridge Power Management States . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2.1 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Forward Bridge Power Management Signaling . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Set Slot Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Reverse Bridge Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Reverse Bridge Active State Power Management (ASPM) . . . . . . . . . . . . 12.2.1.1 ASPM States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Reverse Bridge Power Management States . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2.1 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Reverse Bridge Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 Reverse Bridge PMEOUT# Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.5 Reverse Bridge Set Slot Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 13 PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 Forward Bridge PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1 Forward Bridge INTx# Interrupt Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 Forward Bridge Power Management Messages . . . . . . . . . . . . . . . . . . . . . 13.1.3 Forward Bridge Error Signaling Messages . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.4 Forward Bridge Locked Transactions Support . . . . . . . . . . . . . . . . . . . . . . 13.1.5 Forward Bridge Slot Power Limit Support . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.6 Forward Bridge Hot Plug Signaling Messages . . . . . . . . . . . . . . . . . . . . . . 13.2 Reverse Bridge PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Reverse Bridge INTx# Interrupt Message Support . . . . . . . . . . . . . . . . . . . 13.2.2 Reverse Bridge Power Management Message Support . . . . . . . . . . . . . . . 13.2.2.1 PME Handling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Reverse Bridge Error Signaling Message Support . . . . . . . . . . . . . . . . . . . 13.2.4 Reverse Bridge Locked Transaction Support . . . . . . . . . . . . . . . . . . . . . . . 13.2.5 Reverse Bridge Slot Power Limit Support . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 14 115 115 115 115 116 116 116 117 117 117 117 117 117 117 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.1 14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Single-Level Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Multi-Level Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 External Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Arbitration Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 15 107 107 107 108 109 109 110 110 111 111 111 112 112 113 113 113 119 119 119 119 120 120 Forward Bridge Mode Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 121 15.1 15.2 15.3 15.4 15.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1 PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . 15.5.2 PCI-Compatible Extended Capability Registers for PCI Express Interface 15.5.3 PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . 15.5.4 Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 121 121 122 122 123 124 124 125 126 127 xv Contents PLX Technology, Inc. 15.6 15.7 15.8 PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . PCI-Compatible Extended Capability Registers for PCI Express Interface . . . . . . PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.1 PCI Express Power Budgeting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.2 PCI Express Serial Number Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.9 Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 16 Reverse Bridge Mode Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . .181 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Chapter 17 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 241 241 241 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.1 IEEE Standard 1149.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.2 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.3 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1.4 JTAG Reset Input TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 243 244 245 245 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 19.1 19.2 19.3 19.4 19.5 xvi 181 182 182 182 183 184 184 185 186 187 188 204 222 222 224 225 Testability and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 18.1 Chapter 19 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1.1 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5.1 PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . 16.5.2 PCI-Compatible Extended Capability Registers for PCI Express Interface . 16.5.3 PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . 16.5.4 Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI-Compatible Configuration Registers (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . PCI-Compatible Extended Capability Registers for PCI Express Interface . . . . . . PCI Express Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.1 PCI Express Power Budgeting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.2 PCI Express Serial Number Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 17.1 17.2 17.3 17.4 Chapter 18 128 145 162 162 164 165 Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1.1 VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.1 PCI Bus DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.2 SerDes Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.5.1 SerDes Interface AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.5.2 PCI Bus 33-MHz AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.5.3 PCI Bus 66-MHz AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 247 248 249 250 250 251 254 254 255 256 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Chapter 20 Contents Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.1 20.2 20.3 Appendix A PEX 8111 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 A.1 A.2 A.3 Product Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 United States and International Representatives and Distributors . . . . . . . . . . . . . . 264 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 xvii Contents xviii PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Registers 15-1. (Offset 00h; PCIVENDID) PCI Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 15-2. (Offset 02h; PCIDEVID) PCI Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 15-3. (Offset 04h; PCICMD) PCI Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 15-4. (Offset 06h; PCISTAT) PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 15-5. (Offset 08h; PCIDEVREV) PCI Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-6. (Offset 09h; PCICLASS) PCI Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-7. (Offset 0Ch; PCICACHESIZE) PCI Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-8. (Offset 0Dh; PCILATENCY) PCI Bus Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-9. (Offset 0Eh; PCIHEADER) PCI Header Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 15-10. (Offset 0Fh; PCIBIST) PCI Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15-11. (Offset 10h; PCIBASE0) PCI Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15-12. (Offset 14h; PCIBASE1) PCI Base Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15-13. (Offset 18h; PRIMBUSNUM) Primary Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-14. (Offset 19h; SECBUSNUM) Secondary Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-15. (Offset 1Ah; SUBBUSNUM) Subordinate Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-16. (Offset 1Bh; SECLATTIMER) Secondary Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15-17. (Offset 1Ch; IOBASE) I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 15-18. (Offset 1Dh; IOLIMIT) I/O Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 15-19. (Offset 1Eh; SECSTAT) Secondary Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 15-20. (Offset 20h; MEMBASE) Memory Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 15-21. (Offset 22h; MEMLIMIT) Memory Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 15-22. (Offset 24h; PREBASE) Prefetchable Memory Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 15-23. (Offset 26h; PRELIMIT) Prefetchable Memory Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 15-24. (Offset 28h; PREBASEUPPER) Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . .140 15-25. (Offset 2Ch; PRELIMITUPPER) Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . .140 15-26. (Offset 30h; IOBASEUPPER) I/O Base Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 15-27. (Offset 32h; IOLIMITUPPER) I/O Limit Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 15-28. (Offset 34h; PCICAPPTR) PCI Capabilities Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15-29. (Offset 3Ch; PCIINTLINE) PCI Interrupt Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15-30. (Offset 3Dh; PCIINTPIN) PCI Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 15-31. (Offset 3Eh; BRIDGECTL) Bridge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 15-32. (Offset 40h; PWRMNGID) Power Management Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 15-33. (Offset 41h; PWRMNGNEXT) Power Management Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . .145 15-34. (Offset 42h; PWRMNGCAP) Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 15-35. (Offset 44h; PWRMNGCSR) Power Management Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 15-36. (Offset 46h; PWRMNGBRIDGE) Power Management Bridge Support . . . . . . . . . . . . . . . . . . . . . . . . . . .146 15-37. (Offset 47h; PWRMNGDATA) Power Management Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 15-38. (Offset 48h; DEVSPECCTL) Device-Specific Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 15-39. (Offset 50h; MSIID) Message Signaled Interrupts Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 15-40. (Offset 51h; MSINEXT) Message Signaled Interrupts Next Capability Pointer . . . . . . . . . . . . . . . . . . . . .148 15-41. (Offset 52h; MSICTL) Message Signaled Interrupts Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 15-42. (Offset 54h; MSIADDR) Message Signaled Interrupts Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 15-43. (Offset 58h; MSIUPPERADDR) Message Signaled Interrupts Upper Address . . . . . . . . . . . . . . . . . . . . .149 15-44. (Offset 5Ch; MSIDATA) Message Signaled Interrupts Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 15-45. (Offset 60h; PCIEXID) PCI Express Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 15-46. (Offset 61h; PCIEXNEXT) PCI Express Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 15-47. (Offset 62h; PCIEXCAP) PCI Express Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 15-48. (Offset 64h; DEVCAP) Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 15-49. (Offset 68h; DEVCTL) PCI Express Device Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 15-50. (Offset 6Ah; DEVSTAT) PCI Express Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 15-51. (Offset 6Ch; LINKCAP) Link Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 15-52. (Offset 70h; LINKCTL) Link Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 15-53. (Offset 72h; LINKSTAT) Link Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 15-54. (Offset 74h; SLOTCAP) Slot Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 xix Registers PLX Technology, Inc. 15-55. (Offset 78h; SLOTCTL) Slot Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-56. (Offset 7Ah; SLOTSTAT) Slot Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-57. (Offset 84h; MAININDEX) Main Control Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-58. (Offset 88h; MAINDATA) Main Control Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-59. (Offset 100h; PWRCAPHDR) Power Budgeting Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-60. (Offset 104h; PWRDATASEL) Power Budgeting Data Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-61. (Offset 108h; PWRDATA) Power Budgeting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-62. (Offset 10Ch; PWRBUDCAP) Power Budget Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-63. (Offset 110h; SERCAPHDR) Serial Number Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64. (Offset 114h; SERNUMLOW) Serial Number Low (Lower DWORD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65. (Offset 118h; SERNUMHI) Serial Number Hi (Upper DWORD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-66. (Offset 1000h; DEVINIT) Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67. (Offset 1004h; EECTL) Serial EEPROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-68. (Offset 1008h; EECLKFREQ) Serial EEPROM Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-69. (Offset 100Ch; PCICTL) PCI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-70. (Offset 1010h; PCIEIRQENB) PCI Express Interrupt Request Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-71. (Offset 1018h; IRQSTAT) Interrupt Request Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-72. (Offset 101Ch; POWER) Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-73. (Offset 1020h; GPIOCTL) General-Purpose I/O Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-74. (Offset 1024h; GPIOSTAT) General-Purpose I/O Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-75. (Offset 1030h; MAILBOX0) Mailbox 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-76. (Offset 1034h; MAILBOX1) Mailbox 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-77. (Offset 1038h; MAILBOX2) Mailbox 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-78. (Offset 103Ch; MAILBOX3) Mailbox 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-79. (Offset 1040h; CHIPREV) Chip Silicon Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-80. (Offset 1044h; DIAGCTL) Diagnostic Control (Factory Test Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-81. (Offset 1048h; TLPCFG0) TLP Controller Configuration 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-82. (Offset 104Ch; TLPCFG1) TLP Controller Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-83. (Offset 1050h; TLPCFG2) TLP Controller Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-84. (Offset 1054h; TLPTAG) TLP Controller Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-85. (Offset 1058h; TLPTIMELIMIT0) TLP Controller Time Limit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-86. (Offset 105Ch; TLPTIMELIMIT1) TLP Controller Time Limit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-87. (Offset 1060h; CRSTIMER) CRS Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-88. (Offset 1064h; ECFGADDR) Enhanced Configuration Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1. (Offset 00h; PCIVENDID) PCI Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2. (Offset 02h; PCIDEVID) PCI Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3. (Offset 04h; PCICMD) PCI Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4. (Offset 06h; PCISTAT) PCI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5. (Offset 08h; PCIDEVREV) PCI Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6. (Offset 09h; PCICLASS) PCI Class Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7. (Offset 0Ch; PCICACHESIZE) PCI Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8. (Offset 0Dh; PCILATENCY) PCI Bus Latency Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9. (Offset 0Eh; PCIHEADER) PCI Header Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10. (Offset 0Fh; PCIBIST) PCI Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11. (Offset 10h; PCIBASE0) PCI Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12. (Offset 14h; PCIBASE1) PCI Base Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13. (Offset 18h; PRIMBUSNUM) Primary Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14. (Offset 19h; SECBUSNUM) Secondary Bus Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15. (Offset 1Ah; SUBBUSNUM) Subordinate Bus Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16. (Offset 1Ch; IOBASE) I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17. (Offset 1Dh; IOLIMIT) I/O Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18. (Offset 1Eh; SECSTAT) Secondary Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19. (Offset 20h; MEMBASE) Memory Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20. (Offset 22h; MEMLIMIT) Memory Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21. (Offset 24h; PREBASE) Prefetchable Memory Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22. (Offset 26h; PRELIMIT) Prefetchable Memory Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23. (Offset 28h; PREBASEUPPER) Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . 16-24. (Offset 2Ch; PRELIMITUPPER) Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . 16-25. (Offset 30h; IOBASEUPPER) I/O Base Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx 160 160 161 161 162 162 163 163 164 164 164 165 166 167 167 169 170 171 172 174 174 174 174 174 175 175 176 177 178 178 179 179 179 179 188 188 189 190 191 191 192 192 192 192 193 193 194 194 194 195 195 196 197 197 198 198 199 199 199 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 16-26. 16-27. 16-28. 16-29. 16-30. 16-31. 16-32. 16-33. 16-34. 16-35. 16-36. 16-37. 16-38. 16-39. 16-40. 16-41. 16-42. 16-43. 16-44. 16-45. 16-46. 16-47. 16-48. 16-49. 16-50. 16-51. 16-52. 16-53. 16-54. 16-55. 16-56. 16-57. 16-58. 16-59. 16-60. 16-61. 16-62. 16-63. 16-64. 16-65. 16-66. 16-67. 16-68. 16-69. 16-70. 16-71. 16-72. 16-73. 16-74. 16-75. 16-76. 16-77. 16-78. 16-79. 16-80. 16-81. 16-82. 16-83. 16-84. Registers (Offset 32h; IOLIMITUPPER) I/O Limit Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 (Offset 34h; PCICAPPTR) PCI Capabilities Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 (Offset 3Ch; PCIINTLINE) PCI Interrupt Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 (Offset 3Dh; PCIINTPIN) PCI Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 (Offset 3Eh; BRIDGECTL) Bridge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 (Offset 40h; PWRMNGID) Power Management Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 (Offset 41h; PWRMNGNEXT) Power Management Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . .204 (Offset 42h; PWRMNGCAP) Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 (Offset 44h; PWRMNGCSR) Power Management Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 (Offset 46h; PWRMNGBRIDGE) Power Management Bridge Support . . . . . . . . . . . . . . . . . . . . . . . . . . .205 (Offset 47h; PWRMNGDATA) Power Management Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 (Offset 48h; DEVSPECCTL) Device-Specific Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 (Offset 50h; MSIID) Message Signaled Interrupts Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 (Offset 51h; MSINEXT) Message Signaled Interrupts Next Capability Pointer . . . . . . . . . . . . . . . . . . . . .207 (Offset 52h; MSICTL) Message Signaled Interrupts Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 (Offset 54h; MSIADDR) Message Signaled Interrupts Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 (Offset 58h; MSIUPPERADDR) Message Signaled Interrupts Upper Address . . . . . . . . . . . . . . . . . . . . .208 (Offset 5Ch; MSIDATA) Message Signaled Interrupts Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 (Offset 60h; PCIEXID) PCI Express Capability ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 (Offset 61h; PCIEXNEXT) PCI Express Next Capability Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 (Offset 62h; PCIEXCAP) PCI Express Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 (Offset 64h; DEVCAP) Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 (Offset 68h; DEVCTL) PCI Express Device Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 (Offset 6Ah; DEVSTAT) PCI Express Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 (Offset 6Ch; LINKCAP) Link Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 (Offset 70h; LINKCTL) Link Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 (Offset 72h; LINKSTAT) Link Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 (Offset 74h; SLOTCAP) Slot Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 (Offset 78h; SLOTCTL) Slot Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 (Offset 7Ah; SLOTSTAT) Slot Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 (Offset 7Ch; ROOTCTL) Root Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 (Offset 80h; ROOTSTAT) Root Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 (Offset 84h; MAININDEX) Main Control Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 (Offset 88h; MAINDATA) Main Control Register Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 (Offset 100h; PWRCAPHDR) Power Budgeting Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 (Offset 104h; PWRDATASEL) Power Budgeting Data Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 (Offset 108h; PWRDATA) Power Budgeting Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 (Offset 10Ch; PWRBUDCAP) Power Budget Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 (Offset 110h; SERCAPHDR) Serial Number Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 (Offset 114h; SERNUMLOW) Serial Number Low (Lower DWORD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 (Offset 118h; SERNUMHI) Serial Number Hi (Upper DWORD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 (Offset 1000h; DEVINIT) Device Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 (Offset 1004h; EECTL) Serial EEPROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 (Offset 1008h; EECLKFREQ) Serial EEPROM Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 (Offset 100Ch; PCICTL) PCI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 (Offset 1014h; PCIIRQENB) PCI Interrupt Request Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 (Offset 1018h; IRQSTAT) Interrupt Request Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 (Offset 1020h; GPIOCTL) General-Purpose I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 (Offset 1024h; GPIOSTAT) General-Purpose I/O Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 (Offset 1030h; MAILBOX0) Mailbox 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 (Offset 1034h; MAILBOX1) Mailbox 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 (Offset 1038h; MAILBOX2) Mailbox 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 (Offset 103Ch; MAILBOX3) Mailbox 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 (Offset 1040h; CHIPREV) Chip Silicon Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 (Offset 1044h; DIAGCTL) Diagnostic Control (Factory Test Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 (Offset 1048h; TLPCFG0) TLP Controller Configuration 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 (Offset 104Ch; TLPCFG1) TLP Controller Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 (Offset 1050h; TLPCFG2) TLP Controller Configuration 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 (Offset 1054h; TLPTAG) TLP Controller Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 xxi Registers PLX Technology, Inc. 16-85. (Offset 1058h; TLPTIMELIMIT0) TLP Controller Time Limit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16-86. (Offset 105Ch; TLPTIMELIMIT1) TLP Controller Time Limit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16-87. (Offset 1064h; ECFGADDR) Enhanced Configuration Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 xxii PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 1 1.1 Introduction Features * Forward and reverse transparent bridging between the PCI Express interface and PCI Bus * PCI Express Single-Lane Port (one virtual channel) * PCI Express 2.5 Gbps per direction * PCI Express full Split Completion protocol * 32-bit 66 MHz PCI Bus * Internal PCI Arbiter supporting up to 4 external PCI Masters * SPI serial EEPROM port * Internal 8-KB shared RAM available to the PCI Express interface and PCI Bus * Four GPIO balls * Low-power CMOS in 144-ball PBGA or161-ball FBGA package * 1.5V PCI Express interface operating voltage, 3.3V I/O, 5V tolerant PCI * Standards compliant - PCI Local Bus Specification, Revision 3.0 (PCI r3.0) - PCI to PCI Bridge Architecture Specification, Revision 1.1 (PCI-to-PCI Bridge r1.1) - PCI Bus Power Management Interface Specification, Revision 1.1 (PCI Power Mgmt. r1.1) - PCI Express Base Specification, Revision 1.0a (PCI Express r1.0a) - PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 (PCI ExpressBridge r1.0) 1.2 Overview The ExpressLaneTM PEX 8111 PCI Express-to-PCI Bridge allows for the use of ubiquitous PCI silicon with the high-performance PCI Express Network. As PCI Express systems proliferate, there remain many applications that do not need the extensive bandwidth nor performance features of PCI Express. With the PEX 8111, many existing chips and entire subsystems can be used, without modification, with PCI Express motherboards. 1.2.1 PCI Express Endpoint Interface * Full 2.5 Gbps per direction * Single lane and single virtual channel operation * Compatible with multi-lane and multi-virtual channel PCI Express chips * Packetized serial traffic with PCI Express Split Completion protocol * Data Link Layer CRC generator and checker * Automatic Retry of bad packets * Integrated low-voltage differential drivers * 8b/10b signal encoding * In-band interrupts and messages * Message Signaled Interrupt (MSI) support PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 1 Introduction 1.2.2 PLX Technology, Inc. PCI Bus Interface * PCI r3.0-compliant 32-bit, 66 MHz PCI interface * PCI Master Controller allows PCI Express access to PCI target devices * PCI Target Controller - Allows full transparent access to PCI Express resources - Allows Memory-Mapped access to shared RAM and Configuration registers * PCI Arbiter supports up to four external PCI Bus Masters * Power Management registers and PCI backplane PME# signal support * Message Signaled Interrupts (MSI) support 1.2.3 Configuration Registers * All internal registers are accessible from the PCI Express interface or PCI Bus * All internal registers are set up through an external serial EEPROM * Internal registers allow writes to and reads from an external serial EEPROM * Internal registers allow control of GPIO balls 1.2.4 Data Transfer Pathways * PCI transparent bridge access to PCI Express * PCI Memory-Mapped Single access to internal Configuration registers * PCI Memory-Mapped Single/Burst access to internal shared RAM * Indexed Addressing Capability registers (offsets 84h and 88h) * PCI Configuration access to PCI Configuration registers (Reverse Bridge mode only) * PCI Express transparent bridge access to PCI Bus targets * PCI Express Memory-Mapped Single access to internal Configuration registers * PCI Express Memory-Mapped Single/Burst access to internal shared RAM * PCI Express Configuration access to PCI Configuration registers (Forward Bridge mode only) 2 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 1.3 Block Diagrams Block Diagrams Figure 1-1. PEX 8111 Block Diagram P C I E xpress Interface Fully Transparent P C I E xpress to P C I B ridge P C I Interface PCI Bus PCI Express C onfiguration R egisters 8-K B S hared M em ory Figure 1-2. PEX 8111 Typical Forward Bridge Block Diagram Serial EEPROM Legacy PCI Chip PEX 8111 Proprietary PCI ASIC PCI-Based CPU PCI Bus PCI Express Figure 1-3. PEX 8111 Typical Reverse Bridge Block Diagram Serial EEPROM PEX 8111 PCI Express PCI Express I/O Device PCI Bus PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 3 Introduction 4 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 2 2.1 Ball Descriptions Ball Description Abbreviations Table 2-1. Ball Description Abbreviations (PBGA and FBGA Packages) Abbreviation # DIFF I I/O O Active low PCI Express Differential buffer Input Bi-Directional Output OD Open Drain Output PCI PCI-Compatible buffer, 26-mA drive PD 50K-Ohm Pull-Down resistor PU 50K-Ohm Pull-Up resistor S 2.2 Description Schmitt Trigger STS Sustained Three-State, driven high one Clock cycle before float TP Totem Pole TS Three-State PCI Signal Pull-Up Resistors (Forward Bridge Mode Only) The PCI balls discussed in this chapter are generic primary and secondary PCI interface balls that do not have internal resistors. When designing motherboards, system slot boards, adapter boards, backplanes, and so forth, the termination of these balls must follow the guidelines detailed in the PCI r3.0. The following guidelines are not exhaustive and should be read in conjunction with the appropriate PCI r3.0 sections. PCI Control signals require a pull-up resistor on the motherboard, to ensure that these signals are always at valid values when a PCI Bus agent is not driving the bus. For a 32-bit PCI Bus, these Control signals include the following: * DEVSEL# * INT[D:A]# * PERR# * STOP# * FRAME# * IRDY# * SERR# * TRDY# The INT[D:A]# balls require pull-up resistors, regardless of whether they are used. Depending on the application, M66EN can also require a pull-up resistor. The value of these pull-up resistors depends on the bus loading. The PCI r3.0 provides formulas for calculating the resistor values. When making adapter board devices where the PEX 8111 port is wired to the PCI connector, pull-up resistors are not required because they are pre-installed on the motherboard. Based on the above, in an embedded design, pull-up resistors can be required for PCI control signals on the bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 5 Ball Descriptions 2.3 PLX Technology, Inc. Ball Description - 144-Ball PBGA Package This section provides descriptions of the PEX 8111 144-Ball PBGA package signal balls. The signals are divided into six groups: * PCI Express Signals * PCI Signals * Clock, Reset, and Miscellaneous Signals * JTAG Interface Signals * Test Signals * No Connect Signal * Power and Ground Signals 2.3.1 PCI Express Signals Table 2-2. PCI Express Signals (9 Balls) (144-Ball PBGA Package) Signal Type Balls Description PERn0 I DIFF B7 Receive Minus PCI Express Differential Receive signal. PERp0 I DIFF A8 Receive Plus PCI Express Differential Receive signal. PERST# I/O 6 mA 3.3V B12 PCI Express Reset In Forward Bridge mode, PERST# is an input. Resets the entire PEX 8111 when asserted. In Reverse Bridge mode, PERST# is an output. Asserted when a PCI reset is detected. PETn0 O DIFF A4 Transmit Minus PCI Express Differential Transmit signal. PETp0 O DIFF B5 Transmit Plus PCI Express Differential Transmit signal. REFCLK- I DIFF B6 PCI Express Clock Input Minus PCI Express differential, 100-MHz spread spectrum reference clock. Connected to the PCI Express interface REFCLK- ball in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. REFCLK+ I DIFF A6 PCI Express Clock Input Plus PCI Express differential, 100-MHz spread spectrum reference clock. Connected to the PCI Express interface REFCLK+ ball in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. WAKEIN# I 3.3V C12 Wake In Signal In Forward Bridge mode, pull WAKEIN# high. In Reverse Bridge mode, WAKEIN# is an input, and indicates that the PCI Express Device requested a wakeup while the link remains in the L2 state. WAKEOUT# OD 6 mA 3.3V A9 Wake Out Signal In Forward Bridge mode, WAKEOUT# is an Open Drain output, which is asserted when PMEIN# is asserted and the link remains in the L2 state. 6 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.3.2 Table 2-3. Signal PCI Signals PCI Signals PCI Signals (63 Balls) (144-Ball PBGA Package) Type Balls Description I/O TS PCI J10, J12, J11, K12, L9, M9, K8, L8, K7, L7, M7, J6, K6, M6, L6, J5, H2, H1, G3, G2, G1, F4, F3, F2, E4, E3, E2, E1, D2, D1, C1, D3 Address/Data Bus (32 Balls) The PCI address and data are multiplexed onto the same bus. During the Address phase, AD[31:0] contain the physical address of the transfer. During the Data phase, AD[31:0] contain the data. AD31 is the most significant bit. Write data is stable when IRDY# is asserted, and Read data is stable when TRDY# is asserted. Data is transferred when both IRDY# and TRDY# are asserted. CBE[3:0]# I/O TS PCI Command/Byte Enable Bus (4 Balls) The Bus command and Byte Enables are multiplexed onto the same bus. During the Address phase, CBE[3:0]# contain the Bus command. During the Data phase, CBE[3:0]# contain the Byte Enables. CBE0# corresponds to byte 0 (AD[7:0]), and CBE3# corresponds to byte 3 (AD[31:24]). CBE[3:0]# Command 0000b Interrupt Acknowledge 0001b Special cycle 0010b I/O Read 0011b I/O Write M8, K5, H3, F1 0100b, 0101b Reserved 0110b Memory Read 0111b Memory Write 1000b, 1001b Reserved 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1101b Dual Address Cycle 1110b Memory Read Line 1111b Memory Write and Invalidate DEVSEL# I/O STS PCI PU (Forward Bridge mode only) FRAME# I/O STS PCI PU (Forward Bridge mode only) GNT[3:0]# I/O TS PCI AD[31:0] K4 Device Select Indicates that the target (bus slave) decoded its address during the current bus transaction. As an input, DEVSEL# indicates whether a device on the bus was selected. M5 Frame Driven by the initiator. Indicates access start and duration. When FRAME# is first asserted, the Address phase is indicated. When FRAME# is de-asserted, the transaction remains in the last Data phase. E11, F11, G9, G10 Bus Grant (4 Balls) Indicates that the central arbiter granted the bus to an agent. When the internal PCI arbiter is enabled, GNT[3:0]# are outputs used to grant the bus to external devices. When the internal PCI arbiter is disabled, GNT0# is an input used to grant the bus to the PEX 8111. GNT[3:1]# are placed into high-impedance state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 7 Ball Descriptions Table 2-3. Signal IDSEL PLX Technology, Inc. PCI Signals (63 Balls) (144-Ball PBGA Package) (Cont.) Type I PCI Balls K9 Description Initialization Device Select Valid only in Reverse Bridge mode. Used as a Chip Select during Configuration Read and Write cycles. Each PCI slot or device typically contains an IDSEL connected to a signal address line, allowing the PCI host to select individual sets of Configuration registers. In Forward Bridge mode, it is recommended to ground IDSEL to prevent the signal from floating. INTA#, INTB#, INTC#, INTD# I/O OD PCI PU (Forward Bridge mode only) E12, E9, D11, E10 Interrupt (4 Balls) Asserted to request an interrupt. After assertion, must remain asserted until the device driver clears it. INTx# is level-sensitive and asynchronous to the CLK. In Forward Bridge mode, INTx# is an input from PCI devices. All INTx# signals are mapped into Assert_INTx and Deassert_INTx messages on the PCI Express interface. In Reverse Bridge mode, INTI# is an output to the PCI Central Resource Function. All Assert_INTx and Deassert_INTx PCI Express messages are translated to INTx# transitions on the PCI Bus. IRDY# I/O STS PCI PU (Forward Bridge mode only) L5 Initiator Ready Indicates that the initiator (bus master) is ready to transfer data. Data phase is complete when both IRDY# and TRDY# are asserted. LOCK# I/O STS PCI M3 Lock Atomic Operation Indicates an atomic operation to a bridge that might require multiple transactions to complete. An output in Forward Bridge mode and an input in Reverse Bridge mode. D10 66 MHz Enable Indicates whether the PCI Bus is operating at 33 or 66 MHz. When low, and the PCLKO divider value in the Device Initialization register PCLKO Clock Frequency field is set to 011b, the PCLKO ball oscillates at 33 MHz with a 50% Duty cycle. When high, and the PCLKO divider value in the Device Initialization register PCLKO Clock Frequency field is set to 011b, the PCLKO ball oscillates at 66 MHz with a 33% Duty cycle. Read using the PCI Control register M66EN bit. Must be grounded in 33 MHz systems. J1 Parity Even parity is generated across AD[31:0], and CBE[3:0]#. That is, the number of ones (1) on AD[31:0], CBE[3:0]#, and PAR is an even number. PAR is valid one clock after the Address phase. For Data phases, PAR is valid one clock after IRDY# is asserted on Write cycles, and one clock after TRDY# is asserted on Read cycles. PAR has the same timing as AD[31:0], except it is delayed by one Clock cycle. The bus initiator drives PAR for Address and Write Data phases, and the target drives PAR for Read Data phases. F10 PCI Reset In Forward Bridge mode, PCIRST# is driven when a PCI Express reset is detected, or when the Bridge Control register Secondary Bus Reset bit is set. In Reverse Bridge mode, PCIRST# is an input that resets the entire PEX 8111. Reset is asserted and de-asserted asynchronously to CLK, and is used to bring a PCI device to an initial state. All PCI signals are asynchronously placed into a high-impedance state during reset. M66EN PAR PCIRST# 8 I PCI I/O TS PCI I/O TP PCI PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Table 2-3. Signal PCI Signals PCI Signals (63 Balls) (144-Ball PBGA Package) (Cont.) Type Balls Description PCI Clock Input All PCI signals, except RST# and interrupts, are sampled on the rising edge of PCLKI. The PCLK1 frequency varies from 0 to 66 MHz, and it must oscillate during the serial EEPROM initialization sequence. PCLKI I PCI D12 PERR# I/O STS PCI PU (Forward Bridge mode only) J3 I S PCI H12 Power Management Event In Valid only in Forward Bridge mode. Input used to monitor requests to change the system's power state. L12 Power Management Event Out Valid only in Reverse Bridge mode. Open Drain output used to request a change in the power state. PMEOUT# is not 5V tolerant. When used in a system with a 5V pull-up resistor on the PCI backplane PME# signal, an external voltage translation circuit is required. PMEIN# PMEOUT# OD 24 mA 3.3V REQ[3:0]# I/O TS PCI I/O OD PCI PU (Forward Bridge mode only) H11, G12, H9, G11 Parity Error Indicates that a Data Parity error occurred. Driven active by the receiving agent two clocks following the data that contained bad parity. Bus Request (4 Balls) Indicates that an agent requires use of the bus. When the internal PCI arbiter is enabled, REQ[3:0]# are inputs used to service external bus requests. When the internal PCI arbiter is disabled, REQ0# is an output used to request bus control, and REQ[3:1]# are unused inputs. J2 System Error Indicates that an Address Parity error, Data Parity error on the special cycle command, or other catastrophic error occurred. Driven active for one PCI clock period, and is synchronous to the CLK. Driven only in Reverse Bridge mode. STOP# I/O STS PCI PU (Forward Bridge mode only) L4 Stop Indicates that the target (bus slave) is requesting that the master stop the current transaction. After STOP# is asserted, STOP# must remain asserted until FRAME# is de-asserted, whereupon STOP# must be de-asserted. Also, DEVSEL# and TRDY# cannot be changed until the current Data phase completes. STOP# must be de-asserted in the clock following the completion of the last Data phase, and must be placed into a highimpedance state in the next clock. Data is transferred when both IRDY# and TRDY# are asserted, independent of STOP#. TRDY# I/O STS PCI PU (Forward Bridge mode only) M4 Target Ready Indicates that the target (bus slave) is ready to transfer data. Data phase is complete when both IRDY# and TRDY# are asserted. SERR# PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 9 Ball Descriptions 2.3.3 Table 2-4. PLX Technology, Inc. Clock, Reset, and Miscellaneous Signals Clock, Reset, and Miscellaneous Signals (13 Balls) (144-Ball PBGA Package) Signal Type BAR0ENB# I 3.3V PU E8 PCI Base Address 0 Register Enable When low, the PCI Base Address 0 register is enabled. When high, the PCI Base Address 0 register is enabled by the Device-Specific Control register PCI Base Address 0 Enable bit. EECLK O 3 mA TP 3.3V B2 Serial EEPROM Clock Provides the clock to the serial EEPROM. Frequency is determined by the Serial EEPROM Clock Frequency register, and varies from 2 to 25 MHz. EECS# O 3 mA TP 3.3V C4 Serial EEPROM Chip Select Active-low Chip Select. EERDDATA I 3.3V A1 Serial EEPROM Read Data Used to read data from the PEX 8111. A 47K-Ohm pull-up resistor is required. EEWRDATA O 3 mA TP 3.3V A2 Serial EEPROM Write Data Used to write data to the PEX 8111. EXTARB I 3.3V K11 External Arbiter Enable When low, the internal PCI arbiter services requests from an external PCI device. When high, the PEX 8111 requests the PCI Bus from an external arbiter. FORWARD I 3.3V PU L11 Bridge Select When low, the PEX 8111 acts as a PCI-to-PCI Express Bridge (reverse bridge). When high, the PEX 8111 acts as a PCI Express-to-PCI Bridge (forward bridge). GPIO[3:0] 10 I/O 12 mA 3.3V PU Balls Description A11, B10, A10, C9 General Purpose I/O (4 Balls) Program as an Input or Output general-purpose ball. Internal device status is also an output on GPIO[3:0]. Interrupts are generated on balls that are programmed as inputs. The General-Purpose I/O Control register is used to configure these I/O. GPIO0 defaults to a Link Status output. GPIO1 defaults to an input. When GPIO2 is low at the trailing edge of reset, the TLP Controller Configuration 0 register Limit Completion Flow Control Credit bit is set. When GPIO3 is low at the trailing edge of reset, the TLP Controller Configuration 0 register Delay Link Training bit is set. For Forward Bridge mode, reset is PERST#. For Reverse Bridge mode, reset is PCIRST#. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Table 2-4. JTAG Interface Signals Clock, Reset, and Miscellaneous Signals (13 Balls) (144-Ball PBGA Package) (Cont.) Signal Type Balls O 26 mA TP PCI PCLKO Description PCI Clock Output Buffered clock output derived from the internal 100-MHz reference clock, with the frequency depending on the Device Initialization register PCLKO Clock Frequency field. Signal frequency is 66 MHz when M66EN is high. PCLKO is always driven and oscillates when one of the following occurs: * PCI Express REFCLK-/+ input balls are active. * PCLKO clock divider in Device Initialization register is non-zero. H10 PCLKO can be connected to PCLKI as a source for the PCI input clock. O 6 mA 3.3V PWR_OK 2.3.4 JTAG Interface Signals (5 Balls) (144-Ball PBGA Package) Signal TDI TDO B9 JTAG Interface Signals Table 2-5. TCK Power OK Valid only in Forward Bridge mode. When the available power indicated in the Set Slot Power Limit message is greater than or equal to the power requirement indicated in the Power register, PWR_OK is asserted. Type Balls I M2 Test Clock Joint Test Action Group (JTAG) test clock. Sequences the TAP controller as well as all PEX 8111 JTAG registers. Ground when JTAG is not used. L3 Test Data Input Serial data input to all JTAG instruction and data registers. The Test Access Port (TAP) controller state, as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI is sampled into the JTAG registers on the rising edge of TCK. Hold open when JTAG is not used. L1 Test Data Output Serial data output for all JTAG instruction and data registers. The TAP controller state, as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed as the active connection between TDI and TDO for any given operation. TDO changes state on the falling edge of TCK and is only active during the shifting of data through the PEX 8111. Placed into a high-impedance state at all other times. Hold open when JTAG is not used. I PU O 12 mA 3.3V TS Description TMS I PU M12 Test Mode Select Mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The TMS state at the rising edge of TCK determines the sequence of states for the TAP controller. Hold open when JTAG is not used. TRST# I PU L10 Test Reset Resets the JTAG TAP controller when driven to ground. Ground when JTAG is not used. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 11 Ball Descriptions 2.3.5 PLX Technology, Inc. Test Signals Table 2-6. Test Signals (7 Balls) (144-Ball PBGA Package) Signal Type Balls Description BTON I M11 Test Enable Connect to ground for standard op operation. BUNRI I D8 Test Mode Select Connect to ground for standard operation. SMC I K1 Scan Path Mode Control Connect to ground for standard operation. TEST I A3 Test Mode Select Connect to ground for standard operation. TMC I C8 Test Mode Control Connect to ground for standard operation. TMC1 I B1 IDDQ Test Control Input Connect to ground for standard operation. TMC2 I M1 I/O Buffer Control Connect to ground for standard operation. 2.3.6 No Connect Signal Caution: Table 2-7. No Connect Signal - 1 Ball Signal Name NC1 12 Do not connect the following PEX 8111 ball to board electrical paths, as this ball is not connected within the PEX 8111. Type Location Reserved C2 Description No Connect Must remain open. Do not connect this ball to board electrical paths. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.3.7 Table 2-8. Signal Power and Ground Signals Power and Ground Signals Power and Ground Signals (46 Balls) (144-Ball PBGA Package) Type Balls Description AVDD Power E7 Analog Supply Voltage Connect to the +1.5V power supply. AVSS Ground C7 Analog Ground Connect to ground. GND Ground A12, B4, C3, C11, D9, E6, F12, G5, H4, H7, J4, J8, K2, K10 Ground (14 Balls) Connect to ground. VDD_P Power D5 PLL Supply Voltage Connect to the +1.5V filtered PLL power supply. VDD_R Power A7 Receiver Supply Voltage Connect to the +1.5V power supply. VDD_T Power A5 Transmitter Supply Voltage Connect to the +1.5V power supply. VDD1.5 Power C10, D4, F6, F8, G6, G7, J9, K3 VDD3.3 Power B3, B11, L2, M10 VDD5 Power F5, G8, H6 VDDQ Power E5, F9, G4, H5, H8, J7 VSS_C Ground D7 Common Ground Connect to ground. VSS_P0 Ground D6 PLL Ground Connect to ground. VSS_P1 Ground C6 PLL Ground Connect to ground. VSS_R Ground B8 Receiver Ground Connect to ground. VSS_RE Ground F7 Receiver Ground Connect to ground. VSS_T Ground C5 Transmitter Ground Connect to ground. PCI Express Interface Supply Voltage (8 Balls) Connect to the +1.5V power supply. I/O Supply Voltage (4 Balls) Connect to the +3.3V power supply. PCI I/O Clamp Voltage (3 Balls) Connect to the +5.0V power supply for PCI buffers. In a 3.3V PCI environment, connect to the 3.3V power supply. I/O Supply Voltage (6 Balls) Connect to the +3.3V power supply for PCI buffers. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 13 Ball Descriptions 2.3.8 Table 2-9. Grid PLX Technology, Inc. Ball Tables - 144-Ball PBGA Package Grid Order (144-Ball PBGA Package) Signal Grid Signal Grid Signal Grid Signal A1 EERDDATA D1 AD2 G1 AD11 K1 SMC A2 EEWRDATA D2 AD3 G2 AD12 K2 GND A3 TEST D3 AD0 G3 AD13 K3 VDD1.5 A4 PETn0 D4 VDD1.5 G4 VDDQ K4 DEVSEL# GND A5 VDD_T D5 VDD_P G5 A6 REFCLK+ D6 VSS_P0 G6 A7 VDD_R D7 VSS_C G7 A8 PERp0 D8 BUNRI G8 VDD1.5 VDD5 K5 CBE2# K6 AD19 K7 AD23 K8 AD25 A9 WAKEOUT# D9 GND G9 GNT1# K9 IDSEL A10 GPIO1 D10 M66EN G10 GNT0# K10 GND A11 GPIO3 D11 INTC# G11 REQ0# K11 EXTARB A12 GND D12 PCLKI G12 REQ2# K12 AD28 B1 TMC1 E1 AD4 H1 AD14 L1 TDO B2 EECLK E2 AD5 H2 AD15 L2 VDD3.3 B3 VDD3.3 E3 AD6 H3 CBE1# L3 TDI B4 GND E4 AD7 H4 GND L4 STOP# B5 PETp0 E5 VDDQ H5 VDDQ L5 IRDY# B6 REFCLK- E6 GND H6 VDD5 L6 AD17 B7 PERn0 E7 AVDD H7 GND L7 AD22 B8 VSS_R E8 BAR0ENB# H8 VDDQ L8 AD24 B9 PWR_OK E9 INTB# H9 REQ1# L9 AD27 B10 GPIO2 E10 INTD# H10 PCLKO L10 TRST# B11 VDD3.3 E11 GNT3# H11 REQ3# L11 FORWARD B12 PERST# E12 INTA# H12 PMEIN# L12 PMEOUT# C1 AD1 F1 CBE0# J1 PAR M1 TMC2 C2 NC1 F2 AD8 J2 SERR# M2 TCK C3 GND F3 AD9 J3 PERR# M3 LOCK# C4 EECS# F4 AD10 J4 GND M4 TRDY# C5 VSS_T F5 VDD5 J5 AD16 M5 FRAME# C6 VSS_P1 F6 VDD1.5 J6 AD20 M6 AD18 C7 AVSS F7 VSS_RE J7 VDDQ M7 AD21 C8 TMC F8 VDD1.5 J8 GND M8 CBE3# C9 GPIO0 F9 VDDQ J9 VDD1.5 M9 AD26 C10 VDD1.5 F10 PCIRST# J10 AD31 M10 VDD3.3 C11 GND F11 GNT2# J11 AD29 M11 BTON C12 WAKEIN# F12 GND J12 AD30 M12 TMS 14 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Ball Tables - 144-Ball PBGA Package Table 2-10. Signal Order (144-Ball PBGA Package) Grid Signal Grid Signal Grid Signal Grid Signal D3 AD0 F1 CBE0# E9 INTB# M1 TMC2 C1 AD1 H3 CBE1# D11 INTC# M12 TMS D1 AD2 K5 CBE2# E10 INTD# M4 TRDY# D2 AD3 M8 CBE3# L5 IRDY# L10 TRST# E1 AD4 K4 DEVSEL# M3 LOCK# D5 VDD_P E2 AD5 B2 EECLK C2 NC1 A7 VDD_R E3 AD6 C4 EECS# D10 M66EN A5 VDD_T E4 AD7 A1 EERDDATA E8 BAR0ENB# C10 F2 AD8 A2 EEWRDATA J1 PAR D4 F3 AD9 K11 EXTARB F10 PCIRST# F6 F4 AD10 L11 FORWARD D12 PCLKI F8 G1 AD11 M5 FRAME# H10 PCLKO G6 G2 AD12 A12 B7 PERn0 G7 G3 AD13 B4 A8 PERp0 J9 H1 AD14 C3 J3 PERR# K3 H2 AD15 C11 B12 PERST# B3 J5 AD16 D9 A4 PETn0 B11 L6 AD17 E6 B5 PETp0 L2 M6 AD18 F12 K6 AD19 G5 J6 AD20 M7 VDD1.5 VDD3.3 H12 PMEIN# M10 L12 PMEOUT# F5 H4 B9 PWR_OK G8 AD21 H7 B6 REFCLK- H6 L7 AD22 J4 A6 REFCLK+ E5 K7 AD23 J8 G11 REQ0# F9 L8 AD24 K2 H9 REQ1# G4 K8 AD25 K10 G12 REQ2# H5 M9 AD26 G10 GNT0# H11 REQ3# H8 L9 AD27 G9 GNT1# J2 SERR# J7 K12 AD28 F11 GNT2# K1 SMC D7 VSS_C J11 AD29 E11 GNT3# L4 STOP# D6 VSS_P0 J12 AD30 C9 GPIO0 M2 TCK C6 VSS_P1 J10 AD31 A10 GPIO1 L3 TDI B8 VSS_R E7 AVDD B10 GPIO2 L1 TDO F7 VSS_RE C7 AVSS A11 GPIO3 A3 TEST C5 VSS_T M11 BTON K9 IDSEL C8 TMC C12 WAKEIN# D8 BUNRI E12 INTA# B1 TMC1 A9 WAKEOUT# GND PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 VDD5 VDDQ 15 Ball Descriptions 2.3.9 PLX Technology, Inc. Physical Ball Assignment - 144-Ball PBGA Package Figure 2-1. 144-Ball PBGA Physical Ball Assignment (Underside View) M L K J H G F E D C B A TMS PMEOUT# AD28 AD30 PMEIN# REQ2# GND INTA# PCLKI WAKEIN# PERST# GND 12 BTON FORWARD EXTARB AD29 REQ3# REQ0# GNT2# GNT3# INTC# GND VDD3.3 GPIO3 11 VDD3.3 TRST# GND AD31 PCLKO GNT0# PCIRST# INTD# M66EN VDD1.5 GPIO2 GPIO1 10 AD26 AD27 IDSEL VDD1.5 REQ1# GNT1# VDDQ INTB# GND GPIO0 PWR_OK WAKEOUT# 9 CBE3# AD24 AD25 GND VDDQ VDD5 VDD1.5 BAR0ENB# BUNRI TMC VSS_R PERp0 8 AD21 AD22 AD23 VDDQ GND VDD1.5 VSS_RE AVDD VSS_C AVSS PERn0 VDD_R 7 AD18 AD17 AD19 AD20 VDD5 VDD1.5 VDD1.5 GND VSS_P0 VSS_P1 REFCLK- REFCLK+ 6 FRAME# IRDY# CBE2# AD16 VDDQ GND VDD5 VDDQ VDD_P VSS_T PETp0 VDD_T 5 TRDY# STOP# DEVSEL# GND GND VDDQ AD10 AD7 VDD1.5 EECS# GND PETn0 4 LOCK# TDI VDD1.5 PERR# CBE1# AD13 AD9 AD6 AD0 GND VDD3.3 TEST 3 TCK VDD3.3 GND SERR# AD15 AD12 AD8 AD5 AD3 NC1 EECLK EEWRDATA 2 TMC2 TDO SMC PAR AD14 AD11 CBE0# AD4 AD2 AD1 TMC1 EERDDATA 1 16 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.4 Ball Description - 161-Ball FBGA Package Ball Description - 161-Ball FBGA Package This section provides descriptions of the PEX 8111 161-Ball FBGA package signal balls. The signals are divided into six groups: * PCI Express Signals * PCI Signals * Clock, Reset, and Miscellaneous Signals * JTAG Interface Signals * Test Signals * No Connect Signals * Power and Ground Signals 2.4.1 PCI Express Signals Table 2-11. PCI Express Signals (9 Balls) (161-Ball FBGA Package) Signal Type Balls Description PERn0 I DIFF B9 Receive Minus PCI Express Differential Receive signal. PERp0 I DIFF A8 Receive Plus PCI Express Differential Receive signal. PERST# I/O 6 mA 3.3V C12 PCI Express Reset In Forward Bridge mode, PERST# is an input. Resets the entire PEX 8111 when asserted. In Reverse Bridge mode, PERST# is an output. Asserted when a PCI reset is detected. PETn0 O DIFF B5 Transmit Minus PCI Express Differential Transmit signal. PETp0 O DIFF A6 Transmit Plus PCI Express Differential Transmit signal. REFCLK- I DIFF A7 PCI Express Clock Input Minus PCI Express differential, 100-MHz spread spectrum reference clock. REFCLK- is connected to the PCI Express interface REFCLK- ball in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. B7 PCI Express Clock Input Plus PCI Express differential, 100 MHz spread spectrum reference clock. REFCLK+ is connected to the PCI Express interface REFCLK+ ball in Forward Bridge mode, and to an external differential clock driver in Reverse Bridge mode. REFCLK+ I DIFF WAKEIN# I 3.3V D14 Wake In Signal In Forward Bridge mode, pull WAKEIN# high. In Reverse Bridge mode, WAKEIN# is an input, and indicates that the PCI Express Device requested a wakeup while the link remains in the L2 state. WAKEOUT# OD 6 mA 3.3V A11 Wake Out Signal In Forward Bridge mode, WAKEOUT# is an Open Drain output, and asserted when PMEIN# is asserted and the link remains in the L2 state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 17 Ball Descriptions 2.4.2 PLX Technology, Inc. PCI Signals Table 2-12. PCI Signals (63 Balls) (161-Ball FBGA Package) Signal AD[31:0] Type Balls Description I/O TS PCI L13, J11, K12, L12, M10, P11, P10, P9, L9, N8, P8, M8, M7, L6, N6, P7, K2, J3, J1, H2, H3, H1, G4, F3, F2, F1, E2, E3, E1, D3, D1, D2 Address/Data Bus (32 Balls) The PCI address and data are multiplexed onto the same bus. During the Address phase, AD[31:0] contain the physical address of the transfer. During the Data phase, AD[31:0] contain the data. AD31 is the most significant bit. Write data is stable when IRDY# is asserted, and Read data is stable when TRDY# is asserted. Data is transferred when both IRDY# and TRDY# are asserted. M9, P6, K1, G1 Command/Byte Enable Bus (4 Balls) The Bus command and Byte Enables are multiplexed onto the same bus. During the Address phase, CBE[3:0]# contain the Bus command. During the Data phase, CBE[3:0]# contain the Byte Enables. CBE0# corresponds to byte 0 (AD[7:0]), and CBE3# corresponds to byte 3 (AD[31:24]). CBE[3:0]# Command 0000b Interrupt Acknowledge 0001b Special cycle 0010b I/O Read 0011b I/O Write 0100b, 0101b Reserved 0110b Memory Read 0111b Memory Write 1000b, 1001b Reserved 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1101b Dual Address Cycle 1110b Memory Read Line 1111b Memory Write and Invalidate CBE[3:0]# I/O TS PCI DEVSEL# I/O STS PCI PU (Reverse Bridge mode only) FRAME# I/O STS PCI PU (Reverse Bridge mode only) GNT[3:0]# 18 I/O TS PCI M4 Device Select Indicates that the target (bus slave) decoded its address during the current bus transaction. As an input, DEVSEL# indicates whether a device on the bus was selected. L5 Frame Driven by the initiator, and indicates the access start and duration. When FRAME# is first asserted, the Address phase is indicated. When FRAME# is de-asserted, the transaction remains in the last Data phase. F12, G11, J13, J14 Bus Grant (4 Balls) Indicates that the central arbiter granted the bus to an agent. When the internal PCI arbiter is enabled, GNT[3:0]# are outputs used to grant the bus to external devices. When the internal PCI arbiter is disabled, GNT0# is an input used to grant the bus to the PEX 8111, and GNT[3:1]# are placed into a high-impedance state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI Signals Table 2-12. PCI Signals (63 Balls) (161-Ball FBGA Package) (Cont.) Signal IDSEL Type I PCI Balls Description N10 Initialization Device Select Valid only in Reverse Bridge mode. Used as a Chip Select during Configuration Read and Write cycles. Each PCI slot or device typically contains an IDSEL connected to a signal address line, allowing the PCI host to select individual sets of Configuration registers. In Forward Bridge mode, it is recommended to ground IDSEL to prevent the signal from floating. INTA#, INTB#, INTC#, INTD# I/O OD PCI PU (Reverse Bridge mode only) F14, F13, E14, E13 Interrupt (4 Balls) Asserted to request an interrupt. After assertion, must remain asserted until the device driver clears it. INTx# is level-sensitive and asynchronous to the CLK. In Forward Bridge mode, INTx# is an input from PCI devices. All INTx# signals are mapped into Assert_INTx and Deassert_INTx messages on the PCI Express interface. In Reverse Bridge mode, INTx# is an output to the PCI Central Resource Function. All Assert_INTx and Deassert_INTx PCI Express messages are translated to INTx# transitions on the PCI Bus. IRDY# I/O STS PCI PU (Reverse Bridge mode only) P5 Initiator Ready Indicates that the initiator (bus master) is ready to transfer data. Data phase is complete when both IRDY# and TRDY# are asserted. LOCK# I/O STS PCI P4 Lock Atomic Operation Indicates an atomic operation to a bridge that might require multiple transactions to complete. Output in Forward Bridge mode and input in Reverse Bridge mode. D13 66 MHz Enable Indicates whether the PCI Bus is operating at 33 or 66 MHz. When low, and the PCLKO divider value in the Device Initialization register PCLKO Clock Frequency field is set to 011b, the PCLKO ball oscillates at 33 MHz with a 50% Duty cycle. When high, and the PCLKO divider value in the Device Initialization register PCLKO Clock Frequency field is set to 011b, the PCLKO ball oscillates at 66 MHz with a 33% Duty cycle. Read M66EN using the PCI Control register M66EN bit. Must be grounded in 33 MHz systems. J4 Parity Even parity is generated across AD[31:0], and CBE[3:0]#. That is, the number of ones (1) on AD[31:0], CBE[3:0]#, and PAR is an even number. PAR is valid one clock after the Address phase. For Data phases, PAR is valid one clock after IRDY# is asserted on Write cycles, and one clock after TRDY# is asserted on Read cycles. PAR has the same timing as AD[31:0], except it is delayed by one Clock cycle. The bus initiator drives PAR for Address and Write Data phases, and the target drives PAR for Read Data phases. G14 PCI Reset In Forward Bridge mode, driven when a PCI Express reset is detected, or the Bridge Control register Secondary Bus Reset bit is set. In Reverse Bridge mode, PCIRST# is an input that resets the entire PEX 8111. Reset is asserted and de-asserted asynchronously to CLK, and used to bring a PCI device to an initial state. All PCI signals are asynchronously placed into a high-impedance state during reset. M66EN PAR PCIRST# I PCI I/O TS PCI I/O TP PCI PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 19 Ball Descriptions PLX Technology, Inc. Table 2-12. PCI Signals (63 Balls) (161-Ball FBGA Package) (Cont.) Signal Balls Description PCLKI I PCI E12 PCI Clock Input All PCI signals, except RST# and interrupts, are sampled on the rising edge of PCLKI. The PCLK1 frequency varies from 0 to 66 MHz, and it must oscillate during the serial EEPROM initialization sequence. PERR# I/O STS PCI PU (Reverse Bridge mode only) L2 Parity Error Indicates that a Data Parity error occurred. Driven active by the receiving agent two clocks following the data that contained bad parity. I S PCI L14 Power Management Event In Valid only in Forward Bridge mode. Input used to monitor requests to change the system power state. M14 Power Management Event Out Valid only in Reverse Bridge mode. Open-drain output used to request a change in the power state. PMEOUT# is not 5V tolerant. When used in a system with a 5V pull-up resistor on the PCI backplane PME# signal, an external voltage translation circuit is required. H11, H12, K13, K14 Bus Request (4 Balls) Indicates that an agent requires use of the bus. When the internal PCI arbiter is enabled, REQ[3:0]# are inputs used to service external bus requests. When the internal PCI arbiter is disabled, REQ0# is an output used to request bus control, and REQ[3:1]# are unused inputs. L1 System Error Indicates that an Address Parity error, Data Parity error on the special cycle command, or other catastrophic error occurred. Driven active for one PCI clock period, and is synchronous to the CLK. Driven only in Reverse Bridge mode. STOP# I/O STS PCI PU (Reverse Bridge mode only) N4 Stop Indicates that the target (bus slave) is requesting that the master stop the current transaction. After STOP# is asserted, it must remain asserted until FRAME# is de-asserted, whereupon STOP# must be de-asserted. Also, DEVSEL# and TRDY# cannot be changed until the current data phase completes. STOP# must be de-asserted in the clock following the completion of the last Data phase, and must be placed into a highimpedance state in the next clock. Data is transferred when both IRDY# and TRDY# are asserted, independent of STOP#. TRDY# I/O STS PCI PU (Reverse Bridge mode only) M5 Target Ready Indicates that the target (bus slave) is ready to transfer data. Data phase is complete when both IRDY# and TRDY# are asserted. PMEIN# Type PMEOUT# OD 24 mA 3.3V REQ[3:0]# I/O TS PCI SERR# 20 I/O OD PCI PU (Reverse Bridge mode only) PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.4.3 Clock, Reset, and Miscellaneous Signals Clock, Reset, and Miscellaneous Signals Table 2-13. Clock, Reset, and Miscellaneous Signals (13 Balls) (161-Ball FBGA Package) Signal Type Balls Description BAR0ENB# I 3.3V PU A10 PCI Base Address 0 Register Enable When low, the PCI Base Address 0 register is enabled. When high, the PCI Base Address 0 register is enabled by the Device-Specific Control register PCI Base Address 0 Enable bit. EECLK O 3 mA TP 3.3V C2 Serial EEPROM Clock Provides the clock to the serial EEPROM. Frequency is determined by the Serial EEPROM Clock Frequency register, and varies from 2 to 25 MHz. EECS# O 3 mA TP 3.3V C5 Serial EEPROM Chip Select Active-low Chip Select. EERDDATA I 3.3V B3 Serial EEPROM Read Data Used to read data from the PEX 8111. A 47K-Ohm pull-up resistor is required. EEWRDATA O 3 mA TP 3.3V A3 Serial EEPROM Write Data Used to write data to the PEX 8111. EXTARB I 3.3V FORWARD I 3.3V PU M12 External Arbiter Enable When low, the internal PCI arbiter services requests from an external PCI device. When high, the PEX 8111 requests the PCI Bus from an external arbiter. M13 Bridge Select When low, the PEX 8111 acts as a PCI-to-PCI Express Bridge (reverse bridge). When high, the PEX 8111 acts as a PCI Express-to-PCI Bridge (forward bridge). PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 21 Ball Descriptions PLX Technology, Inc. Table 2-13. Clock, Reset, and Miscellaneous Signals (13 Balls) (161-Ball FBGA Package) (Cont.) Signal GPIO[3:0] PCLKO Type I/O 12 mA 3.3V PU O 26 mA TP PCI Balls Description B12, D11, A12, C10 General Purpose I/O (4 Balls) Program as an input or output general-purpose ball. Internal device status also has the ability to be an output on GPIO[3:0]. Interrupts are generated on balls that are programmed as inputs. The General-Purpose I/O Control register is used to configure these I/O. GPIO0 defaults to a Link Status output. GPIO1 defaults to an input. When GPIO2 is low at the trailing edge of reset, the TLP Controller Configuration 0 register Limit Completion Flow Control Credit bit is set. When GPIO3 is low at the trailing edge of reset, the TLP Controller Configuration 0 register Delay Link Training bit is set. For Forward Bridge mode, reset is PERST#. For Reverse Bridge mode, reset is PCIRST#. H14 PCI Clock Output Buffered clock output derived from the internal 100-MHz reference clock, with the frequency depending on the Device Initialization register PCLKO Clock Frequency field. Signal frequency is 66 MHz when M66EN is high. PCLKO is always driven and oscillates when one of the following occurs: * PCI Express REFCLK-/+ input balls are active, * PCLKO clock divider in Device Initialization register is non-zero. PCLKO can be connected to PCLKI as a source for the PCI input clock. PWR_OK 22 O 6 mA 3.3V B11 Power OK Valid only in Forward Bridge mode. When the available power indicated in the Set Slot Power Limit message is greater than or equal to the power requirement indicated in the Power register, PWR_OK is asserted. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.4.4 JTAG Interface Signals JTAG Interface Signals Table 2-14. JTAG Interface Signals (5 Balls) (161-Ball FBGA Package) Signal TCK TDI TDO Type Balls I M2 Test Clock JTAG test clock. Sequences the TAP controller, as well as all PEX 8111 JTAG registers. Ground when JTAG is not used. P3 Test Data Input Serial data input to all JTAG instruction and data registers. The TAP controller state, as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI is sampled into the JTAG registers on the rising edge of TCK. Hold open when JTAG is not used. M3 Test Data Output Serial data output for all JTAG instruction and data registers. The TAP controller state, as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed as the active connection between TDI and TDO for any given operation. TDO changes state on the falling edge of TCK and is only active during the shifting of data through the PEX 8111. Placed into a high-impedance state at all other times. Hold open when JTAG is not used. I PU O 12 mA TS 3.3V Description TMS I PU N12 Test Mode Select Mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The state of TMS at the rising edge of TCK determines the sequence of states for the TAP controller. Hold open when JTAG is not used. TRST# I PU N11 Test Reset Resets the JTAG TAP controller when driven to ground. Ground when JTAG is not used. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 23 Ball Descriptions 2.4.5 PLX Technology, Inc. Test Signals Table 2-15. Test Signals (7 Balls) (161-Ball FBGA Package) Signal Type Balls BTON I M11 Test Enable Connect to ground for standard operation. BUNRI I C9 Test Mode Select Connect to ground for standard operation. SMC I K3 Scan Path Mode Control Connect to ground for standard operation. TEST I C4 Test Mode Select Connect to ground for standard operation. TMC I D10 Test Mode Control Connect to ground for standard operation. TMC1 I D4 IDDQ Test Control Input Connect to ground for standard operation. TMC2 I M1 I/O Buffer Control Connect to ground for standard operation. 2.4.6 Description No Connect Signals Caution: Do not connect the following PEX 8111 balls to board electrical paths, as these balls are not connected within the PEX 8111. Table 2-16. No Connect Signals - 18 Balls Signal Name Type Location Description NC Reserved A1, A2, A13, A14, B1, B2, B13, B14, E5, N1, N2, N13, N14, P1, P2, P13, P14 No Connect (17 Balls) Must remain open. Do not connect these balls to board electrical paths. NC1 Reserved C3 24 No Connect Must remain open. Do not connect this ball to board electrical paths. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.4.7 Power and Ground Signals Power and Ground Signals Table 2-17. Power and Ground Signals (46 Balls) (161-Ball FBGA Package) Signal Type Balls Description AVDD Power C8 Analog Supply Voltage Connect to the +1.5V power supply. AVSS Ground C6 Analog Ground Connect to ground. GND Ground A4, C13, D5, D12, E4, E11, F11, J2, K4, K11, L4, M6, N9, P12 Ground (14 Balls) Connect to ground. VDD_P Power B6 PLL Supply Voltage Connect to the +1.5V filtered PLL power supply. VDD_R Power C7 Receiver Supply Voltage Connect to the +1.5V power supply. VDD_T Power D6 Transmitter Supply Voltage Connect to the +1.5V power supply. VDD1.5 Power B10, C1, C14, G2, G13, L3, L11, N7 VDD3.3 Power B4, C11, L10, N3 VDD5 Power G3, H13, L7 VDDQ Power F4, G12, H4, J12, L8, N5 VSS_C Ground D9 Common Ground Connect to ground. VSS_P0 Ground D7 PLL Ground Connect to ground. VSS_P1 Ground D8 PLL Ground Connect to ground. VSS_R Ground A9 Receiver Ground Connect to ground. VSS_RE Ground B8 Receiver Ground Connect to ground. VSS_T Ground A5 Transmitter Ground Connect to ground. PCI Express Interface Supply Voltage (8 Balls) Connect to the +1.5V power supply. I/O Supply Voltage (4 Balls) Connect to the +3.3V power supply. PCI I/O Clamp Voltage Connect to the +5.0V power supply for PCI buffers. In a 3.3V PCI environment, connect VDD5 to the 3.3V power supply. I/O Supply Voltage (6 Balls) Connect to the +3.3V power supply for PCI buffers. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 25 Ball Descriptions 2.4.8 PLX Technology, Inc. Ball Tables - 161-Ball FBGA Package Table 2-18. Grid Order (161-Ball FBGA Package) Grid A1 A2 Signal NC Grid Signal Grid Signal Grid Signal C14 VDD1.5 H2 AD12 M5 TRDY# D1 AD1 H3 AD11 M6 GND A3 EEWRDATA D2 AD0 H4 VDDQ M7 AD19 A4 GND D3 AD2 H11 REQ3# M8 AD20 A5 VSS_T D4 TMC1 H12 REQ2# M9 CBE3# A6 PETp0 D5 GND H13 VDD5 M10 AD27 A7 REFCLK- D6 VDD_T H14 PCLKO M11 BTON A8 PERp0 D7 VSS_P0 J1 AD13 M12 EXTARB A9 VSS_R D8 VSS_P1 J2 GND M13 FORWARD A10 BAR0ENB# D9 VSS_C J3 AD14 M14 PMEOUT# A11 WAKEOUT# D10 TMC J4 PAR N1 A12 GPIO1 D11 GPIO2 J11 AD30 N2 D12 GND J12 VDDQ N3 VDD3.3 D13 M66EN J13 GNT1# N4 STOP# D14 WAKEIN# J14 GNT0# N5 VDDQ E1 AD3 K1 CBE1# N6 AD17 A13 A14 B1 NC B2 NC B3 EERDDATA E2 AD5 K2 AD15 N7 VDD1.5 B4 VDD3.3 E3 AD4 K3 SMC N8 AD22 B5 PETn0 E4 GND K4 N9 GND B6 VDD_P E5 NC K11 N10 IDSEL B7 REFCLK+ E11 GND K12 AD29 N11 TRST# B8 VSS_RE E12 PCLKI K13 REQ1# N12 TMS B9 PERn0 E13 INTD# K14 REQ0# N13 B10 VDD1.5 E14 INTC# L1 SERR# N14 B11 PWR_OK F1 AD6 L2 PERR# P1 B12 GPIO3 F2 AD7 L3 VDD1.5 P2 F3 AD8 L4 GND P3 TDI F4 VDDQ L5 FRAME# P4 LOCK# B13 B14 NC GND NC C1 VDD1.5 F11 GND L6 AD18 P5 IRDY# C2 EECLK F12 GNT3# L7 VDD5 P6 CBE2# C3 NC1 F13 INTB# L8 VDDQ P7 AD16 C4 TEST F14 INTA# L9 AD23 P8 AD21 C5 EECS# G1 CBE0# L10 VDD3.3 P9 AD24 C6 AVSS G2 VDD1.5 L11 VDD1.5 P10 AD25 C7 VDD_R G3 VDD5 L12 AD28 P11 AD26 C8 AVDD G4 AD9 L13 AD31 P12 GND 26 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Ball Tables - 161-Ball FBGA Package Table 2-18. Grid Order (161-Ball FBGA Package) (Cont.) Grid Signal Grid Signal Grid Signal Grid C9 BUNRI G11 GNT2# L14 PMEIN# P13 C10 GPIO0 G12 VDDQ M1 TMC2 P14 C11 VDD3.3 G13 VDD1.5 M2 TCK C12 PERST# G14 PCIRST# M3 TDO C13 GND H1 AD10 M4 DEVSEL# Signal NC Table 2-19. Signal Order (161-Ball FBGA Package) Grid Signal Grid Signal Grid Signal Grid Signal D2 AD0 C2 EECLK B1 M3 TDO D1 AD1 C5 EECS# B2 C4 TEST D3 AD2 B3 EERDDATA B13 D10 TMC E1 AD3 A3 EEWRDATA B14 D4 TMC1 E3 AD4 M12 EXTARB E5 M1 TMC2 E2 AD5 M13 FORWARD N1 N12 TMS F1 AD6 L5 FRAME# N2 M5 TRDY# F2 AD7 A4 N13 N11 TRST# F3 AD8 C13 N14 B6 VDD_P G4 AD9 D5 P1 C7 VDD_R H1 AD10 D12 P2 D6 VDD_T H3 AD11 E4 P13 B10 H2 AD12 E11 P14 C1 J1 AD13 F11 J3 AD14 J2 K2 AD15 P7 NC C3 NC1 C14 D13 M66EN G2 K4 A10 BAR0ENB# G13 AD16 K11 J4 PAR L3 N6 AD17 L4 G14 PCIRST# L11 L6 AD18 M6 E12 PCLKI N7 M7 AD19 N9 H14 PCLKO B4 M8 AD20 P12 B9 PERn0 C11 P8 AD21 J14 GNT0# A8 PERp0 L10 N8 AD22 J13 GNT1# L2 PERR# N3 L9 AD23 G11 GNT2# C12 PERST# G3 P9 AD24 F12 GNT3# B5 PETn0 H13 P10 AD25 C10 GPIO0 A6 PETp0 L7 GND PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 VDD1.5 VDD3.3 VDD5 27 Ball Descriptions PLX Technology, Inc. Table 2-19. Signal Order (161-Ball FBGA Package) (Cont.) Grid Signal Grid Signal Grid Signal Grid Signal P11 AD26 A12 GPIO1 L14 PMEIN# F4 M10 AD27 D11 GPIO2 M14 PMEOUT# G12 L12 AD28 B12 GPIO3 B11 PWR_OK H4 K12 AD29 N10 IDSEL A7 REFCLK- J12 J11 AD30 F14 INTA# B7 REFCLK+ L8 L13 AD31 F13 INTB# K14 REQ0# N5 C8 AVDD E14 INTC# K13 REQ1# D9 VSS_C C6 AVSS E13 INTD# H12 REQ2# D7 VSS_P0 M11 BTON P5 IRDY# H11 REQ3# D8 VSS_P1 C9 BUNRI P4 LOCK# L1 SERR# A9 VSS_R G1 CBE0# A1 K3 SMC B8 VSS_RE K1 CBE1# A2 N4 STOP# A5 VSS_T P6 CBE2# A13 M2 TCK D14 WAKEIN# M9 CBE3# A14 P3 TDI A11 WAKEOUT# M4 DEVSEL# 28 NC VDDQ PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 2.4.9 Physical Ball Assignment - 161-Ball FBGA Package Physical Ball Assignment - 161-Ball FBGA Package Figure 2-2. 161-Ball FBGA Physical Ball Assignment (Underside View) P N M L K J H G F E D C B A NC NC PMEOUT# PMEIN# REQ0# GNT0# PCLKO PCIRST# INTA# INTC# WAKEIN# VDD1.5 NC NC 14 NC NC FORWARD AD31 REQ1# GNT1# VDD5 VDD1.5 INTB# INTD# M66EN GND NC NC 13 GND TMS EXTARB AD28 AD29 VDDQ REQ2# VDDQ GNT3# PCLKI GND PERST# GPIO3 GPIO1 12 AD26 TRST# BTON VDD1.5 GND AD30 REQ3# GNT2# GND GND GPIO2 VDD3.3 PWR_OK WAKEOUT# 11 AD25 IDSEL AD27 VDD3.3 TMC GPIO0 VDD1.5 BAR0ENB# 10 AD24 GND CBE3# AD23 VSS_C BUNRI PERn0 VSS_R 9 AD21 AD22 AD20 VDDQ VSS_P1 AVDD VSS_RE PERp0 8 Bottom View (PEX 8111) AD16 VDD1.5 AD19 VDD5 VSS_P0 VDD_R REFCLK+ REFCLK- 7 CBE2# AD17 GND AD18 VDD_T AVSS VDD_P PETp0 6 IRDY# VDDQ TRDY# FRAME# NC GND EECS# PETn0 VSS_T 5 LOCK# STOP# DEVSEL# GND GND PAR VDDQ AD9 VDDQ GND TMC1 TEST VDD3.3 GND 4 TDI VDD3.3 TDO VDD1.5 SMC AD14 AD11 VDD5 AD8 AD4 AD2 NC1 EERDDATA EEWRDATA 3 NC NC TCK PERR# AD15 GND AD12 VDD1.5 AD7 AD5 AD0 EECLK NC NC 2 NC NC TMC2 SERR# CBE1# AD13 AD10 CBE0# AD6 AD3 AD1 VDD1.5 NC NC 1 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 29 Ball Descriptions 30 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 3 3.1 Reset Summary Forward Bridge Mode Table 3-1 delineates which device resources are reset when each of the forward bridge reset sources are asserted. Table 3-1. Forward Bridge Reset Device Resources Reset Sources PCI Express Interface Logic PCI Interface Logic PCI RST# Ball Configuration Registers PCI Express PERST# ball PCI Express Link Down a PCI Express Hot Reset a Secondary Bus Reset bit D3 to D0 Power Management Reset a. General-Purpose I/O Control register is not reset for Link Down nor Hot Reset. 3.2 Reverse Bridge Mode Table 3-2 delineates which device resources are reset when each of the reverse bridge reset sources are asserted. Table 3-2. Reverse Bridge Reset Device Resources Reset Sources PCI Express Interface Logic PCI Interface Logic PCI PERST# Ball PCI Express Hot Reset Configuration Registers PCI RST# ball Secondary Bus Reset bit D3 to D0 Power Management Reset PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 31 Reset Summary 3.3 PLX Technology, Inc. Initialization Summary Certain PEX 8111 initialization sequences are described as follows: * No serial EEPROM, blank serial EEPROM, or invalid serial EEPROM - When the EERDDATA ball is always high, then an invalid serial EEPROM is detected. In this case, the default PCI Device ID (8111h) is selected. A 47K-Ohm pull-up resistor ensures that EERDDATA is high when no serial EEPROM is installed. - Enable the PCI Express and PCI interfaces, using default register values. * Valid serial EEPROM with Configuration register data - Enable the PCI Express and PCI interfaces, using register values loaded from the serial EEPROM. The Device Initialization register PCI Express Enable or PCI Enable bit should be the last bit set by the serial EEPROM. 32 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 4 4.1 Initialization Forward Bridge Initialization The actions that the PEX 8111 takes upon receipt of certain reset timing and interface initialization requirements are described in the following sections. 4.1.1 Forward Bridge Reset Behavior There are three types of reset that the PEX 8111 receives over the PCI Express primary interface: * Physical layer resets that are platform specific and referred to as Fundamental Resets (Cold/Warm Reset) * PCI Express Physical Layer mechanism (Hot Reset) * PCI Express Data Link transitioning to the Down state of primary interface These three primary interface reset sources are each described in the sections that follow. All primary interface reset events initiate a Secondary Bus Reset which resets the PCI Bus. In addition to primary interface reset sources, the PEX 8111 supports a PCI Bus reset by way of the Bridge Control register. After reset is de-asserted, a device attempting a Configuration access to the PCI Bus behind the PEX 8111 must wait for at least Trhfa (225) PCI clocks. 4.1.1.1 Fundamental Reset (Cold/Warm Reset) The PEX 8111 uses the PCI Express PERST# signal as a fundamental reset input. When PERST# assertion follows the power-on event, it is referred to as a Cold Reset. The PCI Express system also generates this signal without removing power; which is referred to as a Warm Reset. The PEX 8111 treats Cold and Warm Resets without distinction. The PEX 8111 state machines are asynchronously reset, and the Configuration registers are initialized to their default values when PERST# is asserted. The PEX 8111 also places its PCI outputs into a high-impedance state, unless it is configured as the PCI Bus parking agent. The PEX 8111 propagates the Warm/Cold Reset from its primary interface to PCI reset on the secondary interface. The PCI RST# signal is asserted while PERST# is asserted. PCIRST# is asserted for at least 2 ms after the power levels are valid. PCI_RST# is asserted concurrent with PERST# assertion. Once asserted, however, PCI_RST# remains asserted for 1.0 ms. If PERST# de-asserts during that time, PCI_RST# remains active until 1.0 ms has elapsed from the time it asserted. If PERST# is de-asserted after this time, PCI_RST# follows the PERST# de-assertion within two PCI 33-MHz clock cycles (approximately 60 ns). 4.1.1.2 Primary Reset Due to Physical Layer Mechanism (Hot Reset) PCI Express supports the Link Training Control Reset (a training sequence with the Hot Reset bit set), or Hot Reset, for propagating Reset requests downstream. When the PEX 8111 receives a Hot Reset on its PCI Express primary interface, it propagates that reset to the PCI RST# signal. In addition, the PEX 8111 discards all transactions being processed and returns all registers, state machines and externally observable state internal logic to the state-specified default or initial conditions. Software is responsible for ensuring that the Link Reset assertion and de-assertion messages are timed such that the PEX 8111 adheres to proper reset assertion and de-assertion durations on the PCI RST# signal. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 33 Initialization 4.1.1.3 PLX Technology, Inc. Primary Reset Due to Data Link Down When the PEX 8111 PCI Express primary interface remains in standard operation and, for whatever reason, the Link is down, the Transaction and Data Link Layers enter the DL_Down state. The PEX 8111 discards all transactions being processed and returns all registers, state machines and externally observable state internal logic to the state-specified default or initial conditions. In addition, the entry of the primary interface of the PEX 8111 into DL_Down status initiates a reset of the PCI Bus, using the PCI RST# signal. 4.1.1.4 Secondary Bus Reset by way of Bridge Control Register A PCI secondary interface reset is initiated by setting the Bridge Control register Secondary Bus Reset bit. This targeted reset is used for various reasons, including recovery from error conditions on the secondary bus, or to initiate re-enumeration. A write to the Secondary Bus Reset bit forces the assertion of the secondary interface PCI Reset (RST#) signal without affecting the primary interface or Configuration Space registers. Moreover, the logic associated with the secondary interface is re-initialized and transaction buffers associated with the secondary interface are cleared. RST# is asserted when the Secondary Bus Reset bit is set; therefore, software must take care to observe proper PCI reset timing requirements. Software is responsible for ensuring that the PEX 8111 does not receive transactions that require forwarding to the secondary interface while Secondary Bus Reset bit is set. 4.1.1.5 Bus Parking during Reset The PEX 8111 drives the secondary interface PCI Bus AD[31:0], CBE[3:0]#, and PAR signals to a logic low level (zero) when the secondary interface RST# is asserted. 34 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Reverse Bridge Initialization 4.2 Reverse Bridge Initialization 4.2.1 Reverse Bridge Reset Behavior A PCI Express Hot Reset (PCI Express Link Training Sequence) is generated for the following cases: * Bridge Control register Secondary Bus Reset bit is set * Power management state transitions from D3 to D0 PCI RST# assertion causes the PCI Express sideband Reset signal (PERST#) to assert. 4.2.2 Reverse Bridge Secondary Bus Reset by way of Bridge Control Register A PCI Express secondary interface reset is initiated by setting the Bridge Control register Secondary Bus Reset bit. This targeted reset is used for various reasons, including recovery from error conditions on the secondary bus, or to initiate re-enumeration. A write to the Secondary Bus Reset bit causes a PCI Express Link Reset Training Sequence to transmit without affecting the primary interface or Configuration Space registers. Moreover, the logic associated with the secondary interface is re-initialized and transaction buffers associated with the secondary interface are cleared. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 35 Initialization 36 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 5 5.1 Interrupts Forward Bridge PCI Interrupts In Forward Bridge mode, the PCI INTx# signals are inputs to the PEX 8111. The interrupt is routed to the PCI Express interface, using virtual wire interrupt messages. The PCI Express interface supports the INTx virtual wire interrupt feature for legacy systems that still support the PCI INTx# interrupt signals. PCI INTx# interrupts are "virtualized" in the PCI Express interface, using Assert_INTx and Deassert_INTx messages, where x is A, B, C, or D for the respective PCI INTx# interrupt signals defined in the PCI r3.0. This message pairing provides a mechanism to preserve the level-sensitive semantics of the PCI interrupts. The Assert_INTx and Deassert_INTx messages transmitted on the PCI Express link capture the asserting/de-asserting edge of the respective PCI INTx# signal. The Requester ID used in the PCI Express Assert_INTx and Deassert_INTx messages transmitted by the PEX 8111 (irrespective of whether the source is internal or external to the PEX 8111) equals the PEX 8111 primary interface Bus and Device Numbers. The Function Number sub-field is cleared to 0. 5.1.1 Forward Bridge Internally Generated Interrupts The following internal events can be programmed to generate an interrupt: * Serial EEPROM transaction completed * Any GPIO bit that is programmed as an input * Mailbox register written When one of these interrupts occurs, either a Virtual Wire interrupt or Message Signaled interrupt is produced. Both generated-interrupt methods are described, in detail, in the following two sections. The Mailbox registers can be written in one of two ways from the downstream side: * Configuration transaction, using indexed addressing. The Mailbox register can be accessed using the Main Control Register Index and Main Control Register Data registers to generate an interrupt. * Memory-Mapped transaction, utilizing the Address range defined by the PCI Base Address 0 register. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 37 Interrupts 5.1.1.1 PLX Technology, Inc. Virtual Wire Interrupts When MSI is disabled, virtual wire interrupts are used to support internal interrupt events. Internal interrupt sources are masked by the PCI Command register Interrupt Disable bit and routed to one of the virtual interrupts using the PCI Interrupt Pin register. PCI Express Assert_INTx and Deassert_INTx messages are not masked by the PCI Command register Bus Master Enable bit. The internal interrupt is processed the same as the corresponding PCI interrupt signal. 5.1.1.2 Message Signaled Interrupts The PCI Express interface supports interrupts using Message Signaled Interrupts (MSI). With this mechanism, a device signals an interrupt by writing to a specific memory location. The PEX 8111 uses the 64-bit Message Address version of the MSI capability structure and clears the No Snoop and Relaxed Ordering bits in the Requester Attributes. There are Address and Data Configuration registers associated with the MSI feature - Message Signaled Interrupts Address, Message Signaled Interrupts Upper Address, and Message Signaled Interrupts Data. When an internal interrupt event occurs, the value in the Message Signaled Interrupts Data Configuration register is written to the PCI Express address specified by the MSI Address Configuration registers. The MSI feature is enabled by the Message Signaled Interrupts Control register MSI Enable bit. When MSI is enabled, the virtual wire interrupt feature is disabled. MSI interrupts are generated independently of the PCI Command register Interrupt Disable bit. MSI interrupts are gated by the PCI Command register Bus Master Enable bit. Note: The No Snoop and Relaxed Ordering bits are cleared because the PEX 8111 does not support these features. 38 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 5.2 Reverse Bridge PCI Interrupts Reverse Bridge PCI Interrupts In Reverse Bridge mode, the PCI INTx# signals are outputs from the PEX 8111. Each INTx# signal is asserted or de-asserted when the corresponding PCI Express Assert_INTx or Deassert_INTx message is received. The INTx# signals are asserted independently of the PCI Command register Interrupt Disable bit, and only when the PEX 8111 remains in power state D0. 5.2.1 Reverse Bridge Internally Generated Interrupts The following internal events can be programmed to generate an interrupt: * Serial EEPROM transaction completed * Any GPIO bit that is programmed as an input * Mailbox register written When one of these interrupts occurs, either an INTx# signal interrupt or Message Signaled interrupt is produced. Both generated-interrupt methods are described, in detail, in the following two sections. The Mailbox registers can be written in one of two ways from the downstream side: * Configuration transaction, using indexed addressing. The Mailbox register can be accessed using the Main Control Register Index and Main Control Register Data registers to generate an interrupt. * Memory-Mapped transaction, utilizing the Address range defined by the PCI Base Address 0 register. 5.2.1.1 INTx# Signals When an internal interrupt event occurs, it causes a PCI INTx# signal to assert. Internal interrupt sources are masked by the PCI Command register Interrupt Disable bit and are routed to one of the INTx# signals, using the PCI Interrupt Pin register. The INTx# signals are asserted only when Message Signaled Interrupts are disabled. 5.2.1.2 Message Signaled Interrupts The PCI Bus supports interrupts using Message Signaled Interrupts (MSI). With this mechanism, a device signals an interrupt by writing to a specific memory location. The PEX 8111 uses the 64-bit Message Address version of the MSI capability structure. There are Address and Data Configuration registers associated with the MSI feature - Message Signaled Interrupts Address, Message Signaled Interrupts Upper Address, and Message Signaled Interrupts Data. When an internal interrupt event occurs, the value in the Message Signaled Interrupts Data Configuration register is written to the PCI Express address specified by the MSI Address Configuration registers. The MSI feature is enabled by the Message Signaled Interrupts Control register MSI Enable bit. When MSI is enabled, the INTx# interrupt signals for internally generated interrupts are disabled. MSI interrupts are generated independently of the PCI Command register Interrupt Disable bit. MSI interrupts are gated by the PCI Command register Bus Master Enable bit. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 39 Interrupts 40 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 6 6.1 Serial EEPROM Controller Overview The PEX 8111 provides an interface to SPI (Serial Peripheral Interface)-compatible serial EEPROMs. This interface consists of a Chip Select, Clock, Write Data, and Read Data balls, and operates at up to 25 MHz. Compatible 128-byte serial EEPROMs include the Atmel AT25010A, Catalyst CAT25C01, and ST Microelectronics M95010W. The PEX 8111 supports up to a 16 MB serial EEPROM, utilizing 1-, 2-, or 3-byte addressing. The PEX 8111 automatically determines the appropriate addressing mode. 6.2 Serial EEPROM Data Format The data in the serial EEPROM is stored in the format delineated in Table 6-1. Table 6-1. Serial EEPROM Data Location Value Description 0h 5Ah Validation Signature 1h Refer to Table 6-2 Serial EEPROM Format Byte 2h REG BYTE COUNT (LSB) Configuration register Byte Count (LSB) 3h REG BYTE COUNT (MSB) Configuration register Byte Count (MSB) 4h REGADDR (LSB) 1st Configuration Register Address (LSB) 5h REGADDR (MSB) 1st Configuration Register Address (MSB) 6h REGDATA (Byte 0) 1st Configuration Register Data (Byte 0) 7h REGDATA (Byte 1) 1st Configuration Register Data (Byte 1) 8h REGDATA (Byte 2) 1st Configuration Register Data (Byte 2) 9h REGDATA (Byte 3) 1st Configuration Register Data (Byte 3) Ah REGADDR (LSB) 2nd Configuration Register Address (LSB) Bh REGADDR (MSB) 2nd Configuration Register Address (MSB) Ch REGDATA (Byte 0) 2nd Configuration Register Data (Byte 0) Dh REGDATA (Byte 1) 2nd Configuration Register Data (Byte 1) Eh REGDATA (Byte 2) 2nd Configuration Register Data (Byte 2) Fh REGDATA (Byte 3) 2nd Configuration Register Data (Byte 3) REG BYTE COUNT + 4 MEM BYTE COUNT (LSB) Shared memory Byte Count (LSB) REG BYTE COUNT + 5 MEM BYTE COUNT (MSB) Shared memory Byte Count (MSB) REG BYTE COUNT + 6 SHARED MEM (Byte 0) 1st byte Shared memory REG BYTE COUNT + 7 SHARED MEM (Byte 1) 2nd byte of Shared memory SHARED MEM (Byte n) Last byte of Shared memory ...... ...... FFFFh PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 41 Serial EEPROM Controller PLX Technology, Inc. Table 6-2 delineates the Serial EEPROM Format Byte organization. Table 6-2. Bits Description 0 Configuration Register Load When cleared, and REG BYTE COUNT is non-zero, the Configuration data is read from the serial EEPROM and discarded. When set, Configuration registers are loaded from the serial EEPROM. The first Configuration Register address is located at bytes 3 and 4 in the serial EEPROM. 1 Shared Memory Load When set, shared memory is loaded from the serial EEPROM, starting at location REG BYTE COUNT + 6. The byte number to load is determined by the value in serial EEPROM locations REG BYTE COUNT + 4 and REG BYTE COUNT + 5. 7:2 6.3 Serial EEPROM Format Byte Reserved Initialization After the PEX 8111 Reset is de-asserted, the serial EEPROM internal status register is read to determine whether a serial EEPROM is installed. A pull-up resistor on the EERDDATA ball produces a value of FFh when there is no serial EEPROM installed. When a serial EEPROM is detected, the first byte (validation signature) is read. When a value of 5Ah is read, it is assumed that the serial EEPROM is programmed for the PEX 8111. The serial EEPROM address width is determined while this first byte is read. When the first byte is not 5Ah, then the serial EEPROM is assumed to be blank or programmed with invalid data. In this case, the PCI Express and PCI interfaces are enabled with device default settings. Also, the Serial EEPROM Control register Serial EEPROM Address Width field reports a value of 00b (undetermined width). When the serial EEPROM contains valid data, the second byte (Serial EEPROM Format Byte) is read to determine which serial EEPROM sections are loaded into the PEX 8111 Configuration registers and memory. Bytes 2 and 3 determine the number of serial EEPROM locations containing Configuration register addresses and data. Each Configuration register entry consists of two bytes of register address (bit 12 low selects the PCI Configuration registers; bit 12 high selects the Memory-Mapped Configuration registers) and four bytes of register Write data. When bit 1 of the Serial EEPROM Format Byte is set, locations REG BYTE COUNT + 4 and REG BYTE COUNT + 5 are read to determine the number of bytes to transfer from the serial EEPROM into shared memory. The REG BYTE COUNT must be a multiple of 6 and MEM BYTE COUNT must be a multiple of 4. The EECLK ball frequency is determined by the Serial EEPROM Clock Frequency register Serial EEPROM Clock Frequency field. The default clock frequency is 2 MHz. At this clock rate, it takes about 24 s per DWORD during Configuration register or shared memory initialization. For faster loading of large serial EEPROMs that support a faster clock, direct the first Configuration register load from the serial EEPROM to the Serial EEPROM Clock Frequency register. This increases the serial EEPROM clock frequency for subsequent DWORDs. Note: When operating in Forward Bridge mode, it is recommended t that the serial EEPROM sets the Device Initialization register PCI Express Enable bit. When operating in Reverse Bridge mode, it is recommended that the serial EEPROM sets the Device Initialization register PCI Enable bit. 42 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 6.4 Serial EEPROM Random Read/Write Access Serial EEPROM Random Read/Write Access A PCI Express or PCI Bus master uses the Serial EEPROM Control (EECTL) register to access the serial EEPROM. This register contains 8-bit Read and Write Data fields, Read and Write Start signals, and related Status bits. The following "C" routines demonstrate the firmware protocol required to access the serial EEPROM through the Serial EEPROM Control register. An interrupt is usually generated when the Serial EEPROM Control register Serial EEPROM Busy bit goes from true to false. 6.4.1 Serial EEPROM Opcodes READ_STATUS_EE_OPCODE = 5 WREN_EE_OPCODE = 6 WRITE_EE_OPCODE = 2 READ_EE_OPCODE = 3 6.4.2 Serial EEPROM Low-Level Access Routines int EE_WaitIdle() { int eeCtl, ii; for (ii = 0; ii < 100; ii++) { PEX 8111Read(EECTL, eeCtl); = /* read current value in EECTL */ if ((eeCtl & (1 << EEPROM_BUSY)) == 0) = /* loop until idle */ return(eeCtl); } PANIC("EEPROM Busy timeout!\n"); } void EE_Off() { EE_WaitIdle(); = /* make sure EEPROM is idle */ PEX 8111Write(EECTL, 0); = /* turn off everything (especially EEPROM_CS_ENABLE)*/ } int EE_ReadByte() { int eeCtl = EE_WaitIdle(); = /* make sure EEPROM is idle */ eeCtl |= (1 << EEPROM_CS_ENABLE) | (1 << EEPROM_BYTE_READ_START); PEX 8111Write(EECTL, eeCtl); = /* start reading */ eeCtl = EE_WaitIdle(); = /* wait until read is done */ return((eeCtl >> EEPROM_READ_DATA) & 0xff); = /* extract read data from EECTL */ } void EE_WriteByte(int val) { int eeCtl = EE_WaitIdle(); = /* make sure EEPROM is idle */ eeCtl &= ~(0xff << EEPROM_WRITE_DATA); = /* clear current WRITE value */ eeCtl |= (1 << EEPROM_CS_ENABLE) | (1 << EEPROM_BYTE_WRITE_START) | ((val & 0xff) << EEPROM_WRITE_DATA); PEX 8111Write(EECTL, eeCtl); } 6.4.3 Serial EEPROM Read Status Routine ... EE_WriteByte(READ_STATUS_EE_OPCODE); status = EE_ReadByte(); EE_Off(); ... PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 = /* read status opcode */ = /* get EEPROM status */ = /* turn off EEPROM */ 43 Serial EEPROM Controller 6.4.4 PLX Technology, Inc. Serial EEPROM Write Data Routine ... EE_WriteByte(WREN_EE_OPCODE); EE_Off(); EE_WriteByte(WRITE_EE_OPCODE); #ifdef THREE_BYTE_ADDRESS_EEPROM EE_WriteByte(addr >> 16); #endif EE_WriteByte(addr >> 8); EE_WriteByte(addr); for (ii = 0; ii < n; ii++) { EE_WriteByte(buffer[ii]); } EE_Off(); ... 6.4.5 = = = = = must first write-enable */ turn off EEPROM */ opcode to write bytes */ three-byte addressing EEPROM? */ transmit high byte of address */ = /* transmit next byte of address */ = /* transmit low byte of address */ = /* transmit data to be written */ = /* turn off EEPROM */ Serial EEPROM Read Data Routine ... EE_WriteByte(READ_EE_OPCODE); = #ifdef THREE_BYTE_ADDRESS_EEPROM = EE_WriteByte(addr >> 16); = #endif EE_WriteByte(addr >> 8); = EE_WriteByte(addr); = for (ii = 0; ii < n; ii++) { buffer[ii] = EE_ReadByte(buffer[ii]); } EE_Off(); = 44 /* /* /* /* /* /* opcode to write bytes */ /* three-byte addressing EEPROM? */ /* transmit high byte of address */ /* transmit next byte of address */ /* transmit low byte of address */ /* store read data in buffer */ /* turn off EEPROM */ PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 7 7.1 Address Spaces Introduction The PEX 8111 supports the following Address spaces: * PCI-compatible Configuration (00h to FFh; 256 bytes) * PCI Express Extended Configuration (100h to FFFh) * I/O (32-bit) * Memory (32-bit Non-Prefetchable) * Prefetchable Memory (64-bit) The first two spaces are used for accessing Configuration registers. (Refer to Chapter 8, "Configuration Transactions," for details.) PCI Express Extended Configuration space (100h to FFFh) is supported only in Forward Bridge mode. Table 7-1 lists which bus is primary or secondary for the PEX 8111 Forward and Reverse Bridge modes. The other three Address spaces determine which transactions are forwarded from the primary to secondary bus, and from the secondary to primary bus. The Memory and I/O ranges are defined by a set of Base and Limit registers in the Configuration Header. Transactions falling within the ranges defined by the Base and Limit registers are forwarded from the primary to secondary bus. Transactions falling outside these ranges are forwarded from the secondary to primary bus. The PEX 8111 does not perform Address Translation (flat address space) when transactions cross the bridge. Table 7-1. Primary and Secondary Bus Definitions for Forward and Reverse Bridge Modes Bridge Mode Primary Bus Secondary Bus Forward Bridge PCI Express PCI Reverse Bridge PCI PCI Express PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 45 Address Spaces 7.2 PLX Technology, Inc. I/O Space The I/O Address space determines whether to forward I/O Read or I/O Write transactions across the PEX 8111. PCI Express uses the 32-bit Short Address Format (DWORD-aligned) for I/O transactions. 7.2.1 Enable Bits The PEX 8111's response to I/O transactions is controlled by five Configuration register bits: * PCI Command register I/O Access Enable bit * PCI Command register Bus Master Enable bit * Bridge Control register ISA Enable bit * Bridge Control register VGA Enable bit * Bridge Control register VGA 16-Bit Decode bit The I/O Access Enable bit must be set for I/O transactions to be forwarded downstream. When cleared: * All I/O transactions on the secondary bus are forwarded to the primary bus * Forward Bridge mode - All primary interface I/O requests are completed with Unsupported Request status * Reverse Bridge mode - All I/O transactions are ignored (no DEVSEL# assertion) on the primary (PCI) bus The Bus Master Enable bit must be set for I/O transactions to be forwarded upstream. When cleared: * Forward Bridge mode - All I/O transactions on the secondary (PCI) bus are ignored * Reverse Bridge mode - All I/O requests on the secondary (PCI Express) bus are completed with Unsupported Request status The ISA Enable bit is discussed in Section 7.2.3, "ISA Mode." The VGA Enable and VGA 16-Bit Decode bits are discussed in Section 7.2.4, "VGA Mode." 7.2.2 I/O Base and Limit Registers The following I/O Base and Limit Configuration registers are used to determine whether to forward I/O transactions across the PEX 8111: * I/O Base (upper four bits of 8-bit register correspond to Address bits [15:12]) * I/O Base Upper 16 Bits (16-bit register corresponds to Address bits [31:16]) * I/O Limit (upper four bits of 8-bit register correspond to Address bits [15:12]) * I/O Limit Upper 16 Bits (16-bit register correspond to Address bits [31:16]) The I/O base consists of one 8-bit register and one 16-bit register. The upper four bits of the 8-bit I/O Base register define bits [15:12] of the I/O Base address. The lower four bits of the 8-bit register determine the I/O address capability of this device. The 16 bits of the I/O Base Upper 16 Bits register define bits [31:16] of the I/O Base address. The I/O limit consists of one 8-bit register and one 16-bit register. The upper four bits of the 8-bit I/O Limit register define bits [15:12] of the I/O Limit address. The lower four bits of the 8-bit register determine the I/O address capability of this device, and reflect the value of the same field in the I/O Base register. The 16 bits of the I/O Limit Upper 16 Bits register define bits [31:16] of the I/O Limit address. 46 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 I/O Base and Limit Registers Because Address bits [11:0] are not included in the Address space decoding, the I/O Address range has a granularity of 4 KB and is always aligned to a 4-KB Address Boundary space. The maximum I/O range is 4 GB. I/O transactions on the primary bus that fall within the range defined by the I/O Base and Limit registers are forwarded downstream to the secondary bus, and I/O transactions on the secondary bus that are within the range are ignored. I/O transactions on the primary bus that do not fall within the range defined by the I/O Base and Limit registers are ignored, and I/O transactions on the secondary bus that do not fall within the range are forwarded upstream to the primary bus. Figure 7-1 illustrates I/O forwarding. For 16-bit I/O addressing, when the I/O Base has a value greater than the I/O Limit, the I/O range is disabled. For 32-bit I/O addressing, when the I/O base specified by the I/O Base and I/O Base Upper 16 Bits registers has a value greater than the I/O limit specified by the I/O Limit and I/O Base Upper 16 Bits registers, the I/O range is disabled. In these cases, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. Figure 7-1. I/O Forwarding Downstream Upstream Primary Bus Secondary Bus I/O Limit 4 KB Multiple I/O Base I/O Address Space PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 47 Address Spaces 7.2.3 PLX Technology, Inc. ISA Mode The Bridge Control register ISA Enable bit supports I/O forwarding in a system that contains an ISA Bus. The ISA Enable bit only affects I/O addresses that are within the range defined by the I/O Base and Limit registers, and are in the first 64 KB of the I/O Address space. When the ISA Enable bit is set, the PEX 8111 does not forward downstream I/O transactions on the primary bus that are in the top 768 bytes of each 1-KB block within the first 64 KB of Address space. Only transactions in the bottom 256 bytes of each 1-KB block are forwarded downstream. When the ISA Enable bit is clear, all addresses within the range defined by the I/O Base and Limit registers are forwarded downstream. I/O transactions with addresses above 64 KB are forwarded according to the range defined by the I/O Base and Limit registers. When the ISA Enable bit is set, the PEX 8111 forwards upstream I/O transactions on the secondary bus that are in the top 768 bytes of each 1-KB block within the first 64 KB of Address space, although the address is within the I/O base and limit. All other transactions on the secondary bus are forwarded upstream when they fall outside the range defined by the I/O Base and Limit registers. When the ISA Enable bit is clear, all secondary bus I/O addresses outside the range defined by the I/O Base and Limit registers are forwarded upstream. As with all upstream I/O transactions, the PCI Command register Bus Master Enable bit must be set to enable upstream forwarding. Figure 7-2 illustrates I/O forwarding with the ISA Enable bit set. Figure 7-2. I/O Forwarding with the ISA Enable Bit Set Downstream Primary Bus Upstream Secondary Bus 900h - BFFh 800h - 8FFh 500h - 7FFh 400h - 4FFh 100h - 3FFh 000h - 0FFh 48 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 7.2.4 VGA Mode VGA Mode The Bridge Control register VGA Enable bit enables VGA Register accesses to be forwarded downstream from the primary to secondary bus, independent of the I/O Base and Limit registers. The Bridge Control register VGA 16-Bit Decode bit selects between 10- and 16-bit VGA I/O address decoding, and is applicable when the VGA Enable bit is set. The VGA Enable and VGA 16-Bit Decode bits control the following VGA I/O addresses: * 10-bit addressing - Address bits [9:0] = 3B0h through 3BBh, and 3C0h through 3DFh * 16-bit addressing - Address bits [15:0] = 3B0h through 3BBh, and 3C0h through 3DFh These ranges apply only to the first 64 KB of I/O Address space. 7.2.4.1 VGA Palette Snooping Separate VGA palette snooping is not supported by PCI Express-to-PCI bridges; however, the PEX 8111 supports palette snooping in Reverse Bridge mode. In Forward Bridge mode, the Bridge Control register VGA Enable bit determines whether VGA Palette accesses are forwarded from PCI Express-to-PCI. The PCI Command register VGA Palette Snoop bit is forced to 0 in Forward Bridge mode. The Bridge Control register VGA 16-Bit Decode bit selects between 10- and 16-bit VGA I/O palette snooping address decoding, and is applicable when the VGA Palette Snoop bit is set. The VGA Palette Snoop and VGA 16-Bit Decode bits control the following VGA I/O Palette Snoop addresses: * 10-bit addressing - Address bits [9:0] = 3C6h, 3C8h, and 3C9h * 16-bit addressing - Address bits [15:0] = 3C6h, 3C8h, and 3C9h The PEX 8111 supports the following three modes of palette snooping: * Ignore VGA palette accesses when there are no graphics agents downstream that need to snoop or respond to VGA Palette Access cycles (reads or writes) * Positively decode and forward VGA palette writes when there are graphics agents downstream of the PEX 8111 that require to snoop palette writes (reads are ignored) * Positively decode and forward VGA palette reads and writes when there are graphics agents downstream that require to snoop or respond to VGA Palette Access cycles (reads or writes) The Bridge Control register VGA Enable bit and PCI Command register VGA Palette Snoop bit select the PEX 8111's response to Palette accesses, as delineated in Table 7-2. Table 7-2. PEX 8111 Response to Palette Access VGA Enable VGA Palette Snoop 0 0 Ignore all Palette accesses 0 1 Positively decode Palette writes (ignore reads) 1 X Positively decode Palette reads and writes PEX 8111 Response to Palette Accesses Note: X is "Don't Care." PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 49 Address Spaces 7.3 PLX Technology, Inc. Memory-Mapped I/O Space The Memory-Mapped I/O Address space determines whether to forward Non-Prefetchable Memory Read or Write transactions across the PEX 8111. Map devices that experience side effects during reads, such as buffers, into this space. For PCI-to-PCI Express reads, prefetching occurs in this space only when the Memory Read Line or Memory Read Multiple commands are issued on the PCI Bus. For PCI Express-to-PCI reads, the byte number to read is determined by the Memory Read Request TLP. Transactions that are forwarded using this Address space are limited to a 32-bit range. 7.3.1 Enable Bits The PEX 8111's response to Memory-Mapped I/O transactions is controlled by three Configuration register bits: * PCI Command register Memory Space Enable bit * PCI Command register Bus Master Enable bit * Bridge Control register VGA Enable bit The Memory Space Enable bit must be set for Memory transactions to be forwarded downstream. When cleared: * All Memory transactions on the secondary bus are forwarded to the primary bus * Forward Bridge mode - All Non-Posted Memory Requests are completed with an Unsupported Request status, and Posted Write data is discarded * Reverse Bridge mode - All Memory transactions are ignored on the primary (PCI) bus The Bus Master Enable bit must be set for Memory transactions to be forwarded upstream. When cleared: * Forward Bridge mode - All Memory transactions on the secondary (PCI) bus are ignored * Reverse Bridge mode - All Non-Posted Memory Requests on the secondary (PCI Express) bus are completed with an Unsupported Request status, and Posted Write data is discarded The VGA Enable bit is discussed in Section 7.3.3, "VGA Mode." 7.3.2 Memory Base and Limit Registers The following Memory Base and Limit Configuration registers are used to determine whether to forward Memory-Mapped I/O transactions across the PEX 8111: * Memory Base (bits [15:4] of 16-bit register correspond to Address bits [31:20]) * Memory Limit (bits [15:4] of 16-bit register correspond to Address bits [31:20]) Bits [15:4] of the Memory Base register define bits [31:20] of the Memory-Mapped I/O Base address. Bits [15:4] of the Memory Limit register define bits [31:20] of the Memory-Mapped I/O Limit address. Bits [3:0] of each register are hardwired to 0h. Because Address bits [19:0] are not included in the Address space decoding, the Memory-Mapped I/O Address range has a granularity of 1 MB and is always aligned to a 1-MB Address Boundary space. The maximum Memory-Mapped I/O range is 4 GB. Memory transactions that fall within the range defined by the Memory Base and Limit registers are forwarded downstream from the primary to secondary bus, and Memory transactions on the secondary bus that are within the range are ignored. 50 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 VGA Mode Memory transactions that do not fall within the range defined by the Memory Base and Limit registers are ignored on the primary bus, and forwarded upstream from the secondary bus (provided they are not in the Address range defined by the set of Prefetchable Memory Address registers or forwarded downstream by the VGA mechanism). Figure 7-3 illustrates Memory-Mapped I/O forwarding. When the Memory Base is programmed to have a value greater than the Memory Limit, then the Memory-Mapped I/O range is disabled. In this case, all Memory transaction forwarding is determined by the Prefetchable Base and Limit registers and the Bridge Control register VGA Enable bit. Figure 7-3. Memory-Mapped I/O Forwarding Downstream Primary Bus Upstream Secondary Bus Memory Limit 1 MB Multiple Memory Base Memory-Mapped I/O Address Space 7.3.3 VGA Mode The Bridge Control register VGA Enable bit enables VGA Frame Buffer accesses to be forwarded downstream from the primary to secondary bus, independent of the Memory Base and Limit registers. The VGA Enable bit controls VGA Memory addresses 0A0000h through 0BFFFFh. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 51 Address Spaces 7.4 PLX Technology, Inc. Prefetchable Space The Prefetchable Address space determines whether to forward Prefetchable Memory Read or Write transactions across the PEX 8111. Map devices that do not experience side effects during reads into this space. * For PCI-to-PCI Express reads, prefetching occurs in this space for all Memory Read commands (Memory Read, Memory Read Line, and Memory Read Multiple) issued on the PCI Bus * For Memory Read commands, the Device-Specific Control register Blind Prefetch Enable bit must be set for prefetching to occur * For PCI Express-to-PCI reads, the byte number to read is determined by the Memory Read Request; therefore, prefetching does not occur 7.4.1 Enable Bits The PEX 8111's response to Prefetchable Address space is controlled by three Configuration register bits: * PCI Command register Memory Space Enable bit * PCI Command register Bus Master Enable bit * Bridge Control register VGA Enable bit For further details, refer to Section 7.3.1, "Enable Bits." 7.4.2 Prefetchable Base and Limit Registers The following Prefetchable Memory Base and Limit Configuration registers are used to determine whether to forward Prefetchable Memory transactions across the PEX 8111: * Prefetchable Memory Base (bits [15:4] of 16-bit register correspond to Address bits [31:20]) * Prefetchable Memory Base Upper 32 Bits (32-bit register corresponds to Address bits [63:32]) * Prefetchable Memory Limit (bits [15:4] of 16-bit register correspond to Address bits [31:20]) * Prefetchable Memory Limit Upper 32 Bits (32-bit register corresponds to Address bits [63:32]) Bits [15:4] of the Prefetchable Memory Base register define bits [31:20] of the Prefetchable Memory Base address. Bits [15:4] of the Prefetchable Memory Limit register define bits [31:20] of the prefetchable memory limit. For 64-bit addressing, the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are also used to define the space. Because Address bits [19:0] are not included in the Address space decoding, the Prefetchable Memory Address range has a granularity of 1 MB and is always aligned to a 1-MB Address Boundary space. The maximum Prefetchable Memory range is 4 GB with 32-bit addressing, and 261 bytes with 64-bit addressing. Memory transactions that fall within the range defined by the Prefetchable Memory Base and Limit registers are forwarded downstream from the primary to secondary bus, and Memory transactions on the secondary bus that are within the range are ignored. Memory transactions that do not fall within the range defined by the Prefetchable Memory Base and Limit registers are ignored on the primary bus, and forwarded upstream from the secondary bus (provided they are not in the Address range defined by the set of Memory-Mapped I/O Address registers or forwarded downstream by the VGA mechanism). 52 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Prefetchable Base and Limit Registers When the Prefetchable Memory Base is programmed to a value greater than the Prefetchable Memory Limit, then the Prefetchable Memory range is disabled. In this case, all Memory transaction forwarding is determined by the Memory Base and Limit registers and the Bridge Control register VGA Enable bit. Consider the four Prefetchable Memory Base and Limit registers when disabling the Prefetchable range. Figure 7-4 illustrates both Memory-Mapped I/O and Prefetchable Memory forwarding. In the illustration, Dual Address cycles (DAC) indicate 64-bit addressing. Figure 7-4. Memory-Mapped I/O and Prefetchable Memory Forwarding Downstream Primary Bus Upstream Secondary Bus DAC DAC Prefetchable Memory Limit 1 MB Multiple DAC SAC DAC 4-GB Boundary SAC Prefetchable Memory Base SAC SAC Memory-Mapped I/O Limit SAC 1 MB Multiple SAC Memory-Mapped I/O Base SAC SAC Prefetchable and Memory-Mapped I/O Memory Space SAC = Single Address Cycle DAC = Dual Address Cycle PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 53 Address Spaces 7.4.3 PLX Technology, Inc. 64-Bit Addressing Unlike Memory-Mapped I/O memory that must be below the 4-GB Address Boundary space, prefetchable memory is located below, above, or span the 4-GB Address Boundary space. Memory locations above the 4-GB Address Boundary space must be accessed using 64-bit addressing. PCI Express Memory transactions that use the Short Address (32-bit) format target the non-Prefetchable Memory space, or a Prefetchable Memory window below the 4-GB Address Boundary space. PCI Express Memory transactions that use the Long Address (64-bit) format target locations anywhere in the 64-bit Memory space. PCI Memory transactions that use Single Address cycles only target locations below the 4-GB Address Boundary space. PCI Memory transactions that use Dual Address cycles target locations anywhere in the 64-bit Memory space. The first Address phase of Dual Address transactions contains the lower 32 bits of the address, and the second Address phase contains the upper 32 bits of the address. When the upper 32 bits of the address are zero (0h), a Single Address transaction is always performed. 7.4.3.1 Forward Bridge Mode Below 4-GB Address Boundary Space If the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both cleared to 0, addresses above the 4-GB Address Boundary space are not supported. In Forward Bridge mode, if a PCI Express Memory transaction is detected with an address above 4 GB, the transaction is completed with Unsupported Request status. All Dual Address transactions on the PCI Bus are forwarded upstream to the PCI Express interface. Above 4-GB Address Boundary Space If the Prefetchable memory is located entirely above the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both set to non-zero values. If a PCI Express Memory transaction is detected with an address below 4 GB, the transaction is completed with Unsupported Request status, and all single address transactions on the PCI Bus are forwarded upstream to the PCI Express interface (unless the transactions fall within the Memory-Mapped I/O or VGA Memory range). A PCI Express Memory transaction above the 4-GB Address Boundary space, that falls within the range defined by the Prefetchable Memory Base, Prefetchable Memory Base Upper 32 Bits, Prefetchable Memory Limit, and Prefetchable Memory Limit Upper 32 Bits registers, is forwarded downstream and becomes a Dual Address cycle on the PCI Bus. If a Dual Address cycle is detected on the PCI Bus that is outside the range defined by these registers, it is forwarded upstream to the PCI Express interface. If a PCI Express Memory transaction above the 4-GB Address Boundary space does not fall within the range defined by these registers, it is completed with Unsupported Request status. If a PCI Dual Address cycle falls within the range determined by these registers, it is ignored. 54 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 64-Bit Addressing Spans 4-GB Address Boundary Space If the Prefetchable memory spans the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits register is cleared to 0, and the Prefetchable Memory Limit Upper 32 Bits register is set to a non-zero value. If a PCI Express Memory transaction is detected with an address below the 4-GB Address Boundary space, and is greater than or equal to the Prefetchable Memory Base address, then the transaction is forwarded downstream. A single address transaction on the PCI Bus is forwarded upstream to the PCI Express interface, if the address is less than the Prefetchable Memory Base address. If a PCI Express Memory transaction above the 4-GB Address Boundary space is less than or equal to the Prefetchable Memory Limit register, it is forwarded downstream to the PCI Bus as a Dual Address cycle. If a Dual Address cycle on the PCI Bus is less than or equal to the Prefetchable Memory Limit register, it is ignored. If a PCI Express memory transaction above the 4-GB Address Boundary space is greater than the Prefetchable Memory Limit register, it is completed with Unsupported Request status. If a Dual Address cycle on the PCI Bus is greater than the Prefetchable Memory Limit register, it is forwarded upstream to the PCI Express interface. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 55 Address Spaces 7.4.3.2 PLX Technology, Inc. Reverse Bridge Mode Below 4-GB Address Boundary Space If the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both cleared to 0, then addresses above the 4-GB Address Boundary space are not supported. In Reverse Bridge mode, if a Dual Address transaction on the PCI Bus is detected, the transaction is ignored. If a PCI Express Memory transaction is detected with an address above the 4-GB Address Boundary space, it is forwarded upstream to the PCI Bus as a Dual Address cycle. Above 4-GB Address Boundary Space If the Prefetchable memory is located entirely above the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both set to non-zero values. The PEX 8111 ignores all Single Address Memory transactions on the PCI Bus, and forwards all PCI Express Memory transactions with addresses below the 4-GB Address Boundary space upstream to the PCI Bus (unless they fall within the Memory-Mapped I/O or VGA Memory range). A Dual Address transaction on the PCI Bus that falls within the range defined by the Prefetchable Memory Base, Prefetchable Memory Base Upper 32 Bits, Prefetchable Memory Limit, and Prefetchable Memory Limit Upper 32 Bits registers is forwarded downstream to the PCI Express interface. If a PCI Express Memory transaction is above the 4-GB Address Boundary space and falls outside the range defined by these registers, it is forwarded upstream to the PCI Bus as a Dual Address cycle. Dual Address transactions on the PCI Bus that do not fall within the range defined by these registers are ignored. If a PCI Express Memory transaction above the 4-GB Address Boundary space falls within the range defined by these registers, it is completed with Unsupported Request status. Spans 4-GB Address Boundary Space If the Prefetchable memory spans the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits is cleared to 0, and the Prefetchable Memory Limit Upper 32 Bits register is set to a non-zero value. If a PCI Single Address cycle is greater than or equal to the Prefetchable Memory Base address, then the transaction is forwarded downstream to the PCI Express interface. If a PCI Express Memory transaction is detected with an address below the 4-GB Address Boundary space, and is less than the Prefetchable Memory Base address, then the transaction is forwarded upstream to the PCI Bus. If a Dual Address PCI transaction is less than or equal to the Prefetchable memory limit register, it is forwarded downstream to the PCI Express interface. If a PCI Express Memory transaction above the 4-GB Address Boundary space is less than or equal to the Prefetchable Memory Limit register, it is completed with Unsupported Request status. If a Dual Address PCI transaction is greater than the Prefetchable Memory Limit register, it is ignored. If a PCI Express Memory transaction above the 4-GB Address Boundary space is greater than the Prefetchable Memory Limit register, it is forwarded upstream to the PCI Bus as a Dual Address cycle. When a PCI Express Memory transaction above 4 GB is greater than the Prefetchable Memory Limit register, it is forwarded upstream to the PCI Bus as a Dual Address cycle. 7.4.4 VGA Mode The Bridge Control register VGA Enable bit enables VGA Frame Buffer accesses to be forwarded downstream from the primary to secondary bus, independent of the Prefetchable Memory Base and Prefetchable Memory Limit registers. The VGA Enable bit controls VGA Memory addresses 0A0000h through 0BFFFFh. 56 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 8 8.1 Configuration Transactions Introduction Configuration Requests are initiated only by the Root Complex in a PCI Express-based system, or by the Central Resource function in a PCI-based system. In the PCI r3.0, the term central resource is used to describe bus support functions supplied by the host system, typically in a PCI-compliant bridge or standard chipset. (Refer to the PCI r3.0, Section 2.4, for further details.) Devices in a PCI Express or PCI system have a Configuration space that is accessed using Type 0 or Type 1 Configuration transactions: * Type 0 Configuration transactions are used to access internal PEX 8111 Configuration registers * Type 1 Configuration transactions are used to access PEX 8111 devices that reside downstream The Configuration address is formatted as follows. Table 8-1. PCI Express 31 24 23 18 Device Number Bus Number Table 8-2. 19 16 15 Function Number 12 15 11 Single bit decoding of Device Number 10 1 0 Rsvd 8 7 2 Register Number 1 0 0 0 1 0 0 0 1 0 0 1 PCI Type 0 (at Target) 11 10 8 7 Function Number Rsvd 2 Register Number PCI Type 1 24 Rsvd 2 Register Address Function Number Rsvd 31 31 7 Extended Register Address Rsvd 16 Table 8-4. 8 PCI Type 0 (at Initiator) 31 Table 8-3. 11 23 16 Bus Number 15 11 Device Number PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 10 8 Function Number 7 2 Register Number 57 Configuration Transactions 8.2 PLX Technology, Inc. Type 0 Configuration Transactions The PEX 8111 only responds to Type 0 Configuration transactions on its primary bus that address the PEX 8111 configuration space. A Type 0 Configuration transaction is used to configure the PEX 8111, and is not forwarded downstream to the secondary bus. The PEX 8111 ignores Type 0 Configuration transactions on the secondary bus. Type 0 Configuration transactions always result in the transfer of 1 DWORD. When Configuration Write data is poisoned, the data is discarded, and a Non-Fatal Error message is generated, when enabled. 8.3 Type 1 Configuration Transactions Type 1 Configuration transactions are used for device configuration in a hierarchical bus system. The PEX 8111 responds to Type 1 Configuration transactions. Type 1 Configuration transactions are used when the transaction is intended for a device residing on a bus other than the one where the Type 1 request is issued. The Bus Number field in a Configuration transaction request specifies a unique bus in the hierarchy on which transaction targets reside. The PEX 8111 compares the specified Bus Number with two PEX 8111 Configuration registers - Secondary Bus Number and Subordinate Bus Number - to determine whether to forward a Type 1 Configuration transaction across the PEX 8111. When a Type 1 Configuration transaction is received on the primary interface, the following tests are applied, in sequence, to the Bus Number field to determine how the transaction must be handled: * If the Bus Number field is equal to the Secondary Bus Number register value, and the conditions for converting the transaction into a special cycle transaction are met, the PEX 8111 forwards the Configuration Request to the secondary bus as a special cycle transaction. When the conditions are not met, the PEX 8111 forwards the Configuration Request to the secondary bus as a Type 0 Configuration transaction. * If the Bus Number field is not equal to the Secondary Bus Number register value, but is within the range of the Secondary Bus Number and Subordinate Bus Number (inclusive) registers, the Type 1 Configuration Request is specifying a bus located behind the PEX 8111. In this case, the PEX 8111 forwards the Configuration Request to the secondary bus as a Type 1 Configuration transaction. * If the Bus Number field does not satisfy the above criteria, the Type 1 Configuration Request is specifying a bus that is not located behind the PEX 8111. In this case, the Configuration Request is invalid: - If the primary interface is PCI Express, a completion with Unsupported Request status is returned - If the primary interface is PCI, the Configuration Request is ignored, resulting in a Master Abort 58 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 8.4 Type 1-to-Type 0 Conversion Type 1-to-Type 0 Conversion The PEX 8111 performs a Type 1-to-Type 0 conversion when the Type 1 transaction is generated on the primary bus and is intended for a device directly attached to the secondary bus. The PEX 8111 must convert the Type 1 Configuration transaction to Type 0, thereby allowing the PEX 8111 to respond to it. Type 1-to-Type 0 conversions are performed only in the downstream direction. The PEX 8111 generates Type 0 Configuration transactions only on the secondary interface, never on the primary interface. 8.4.1 Forward Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI Express interface to a Type 0 transaction on the PCI Bus, when the following are true: * Type 1 Configuration Request Bus Number field is equal to the Secondary Bus Number register value. * Conditions for conversion to a special cycle transaction are not met. The PEX 8111 then performs the following on the secondary interface: 1. Clears Address bits AD[1:0] to 00b. 2. Derives Address bits AD[7:2] from the Configuration Request Register Address field. 3. Derives Address bits AD[10:8] from the Configuration Request Function Number field. 4. Clears Address bits AD[15:11] to 0h. 5. Decodes the Device Number field and asserts a single Address bit in the range AD[31:16] during the Address phase. 6. Verifies that the Configuration Request Extended Register Address field is zero (0h). When the value is non-zero, the PEX 8111 does not forward the transaction, and treats it as an Unsupported Request on the PCI Express interface, and a Received Master Abort on the PCI Bus. Type 1-to-Type 0 transactions are performed as Non-Posted transactions. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 59 Configuration Transactions 8.4.2 PLX Technology, Inc. Reverse Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI Bus to a Type 0 transaction on the PCI Express interface, when the following are true during the PCI Address phase: * Address bits AD[1:0] are 01b. * Type 1 Configuration Request Bus Number field (AD[23:16]) is equal to the Secondary Bus Number register value. * Bus command on CBE[3:0]# is a Configuration read or write. * Type 1 Configuration Request Device Number field (AD[15:11]) is zero (0h). When the value is non-zero, the transaction is ignored, resulting in a Master Abort. The PEX 8111 then creates a PCI Express Configuration Request, according to the following: 1. Sets the request Type field to Configuration Type 0. 2. Sets the Register Address field [7:2] from the Configuration Request Register Address field. 3. Clears the Extended Register Address field [11:8] to 0h. 4. Sets the Function Number field [18:16] from the Configuration Request Function Number field. 5. Clears the Device Number field [23:19] from the Configuration Request Device Number field (forced to 0h). 6. Sets the Bus Number field [31:24] from the Configuration Request Bus Number field. Type 1-to-Type 0 transactions are performed as Non-Posted (Delayed) transactions. 60 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 8.5 Type 1-to-Type 1 Forwarding Type 1-to-Type 1 Forwarding Type 1-to-Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of bridges are used. When the PEX 8111 detects a Type 1 Configuration transaction intended for a PCI Bus downstream from the secondary bus, it forwards the transaction unchanged to the secondary bus. In this case, the transaction target does not reside on the PEX 8111 secondary interface; however, is located on a bus segment further downstream. Ultimately, this transaction is converted to a Type 0 or special cycle transaction by a downstream bridge. 8.5.1 Forward Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI Express interface to a Type 1 transaction on the PCI Bus when the following are true: * Type 1 Configuration transaction is detected on the PCI Express. * Value specified by the Bus Number field is within the range of bus numbers between the Secondary Bus Number (exclusive) and Subordinate Bus Number (inclusive). The PEX 8111 then performs the following on the secondary interface: 1. Generates Address bits AD[1:0] as 01b. 2. Generates the PCI Register Number, Function Number, Device Number, and Bus Number from the PCI Express Configuration Request Register Address, Function Number, Device Number, and Bus Number fields, respectively. 3. Generates Address bits AD[31:24] as 0h. 4. Verifies that the Configuration Request Extended Register Address field is 0h. When the value is non-zero, the PEX 8111 does not forward the transaction, and returns a completion with Unsupported Request status on the PCI Express interface, and a Received Master Abort on the PCI Bus. Type 1-to-Type 1 Forwarding transactions are performed as Non-Posted transactions. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 61 Configuration Transactions 8.5.2 PLX Technology, Inc. Reverse Bridge Mode The PEX 8111 forwards a Type 1 transaction on the PCI Bus to a Type 1 transaction on the PCI Express interface when the following are true during the PCI Address phase: * Address bits AD[1:0] are 01b. * Value specified by the Bus Number field is within the range of bus numbers between the Secondary Bus Number (exclusive) and Subordinate Bus Number (inclusive). * Bus command on CBE[3:0]# is a Configuration read or write. The PEX 8111 then creates a PCI Express Configuration Request, according to the following: 1. Sets the Configuration Request Type field to Configuration Type 1. 2. Sets the Register Address field [7:2] from the Configuration Request Register Address field. 3. Clears the Extended Register Address field [11:8] to 0h. 4. Sets the Function Number field [18:16] from the Configuration Request Function Number field. 5. Sets the Device Number field [23:19] from the Configuration Request Device Number field. 6. Sets the Bus Number field [31:24] from the Configuration Request Bus Number field. Type 1-to-Type 1 Forwarding transactions are performed as Non-Posted (Delayed) transactions. 8.6 Type 1-to-Special Cycle Forwarding The Type 1 Configuration mechanism is used to generate special cycle transactions in hierarchical systems. Special cycle transactions are ignored by the PEX 8111 acting as a target, and are not forwarded across the PEX 8111. In Forward Bridge mode, special cycle transactions are only generated in the downstream direction (PCI Express-to-PCI). In Reverse Bridge mode, special cycle transactions are also generated in the downstream direction (PCI-to-PCI Express). A Type 1 Configuration Write Request on the PCI Express interface is converted to a special cycle on the PCI Bus when the following conditions are met: * Type 1 Configuration Request Bus Number field is equal to the Secondary Bus Number register value. * Device Number field is all ones (1h) * Function Number field is all ones (1h) * Register Address field is all zeros (0h) * Extended Register Address field is all zeros (0h) When the PEX 8111 initiates the transaction on the PCI Bus, the Bus command is converted from a Configuration write to a special cycle. The Address and Data fields are forwarded, unchanged, from the PCI Express-to-PCI Bus. Target devices that recognize the special cycle ignore the address, and the message is passed in the Data word. The transaction is performed as a Non-Posted transaction; however, the PCI target response (always Master Abort in this case) is not returned to PCI Express. After the Master Abort is detected on the PCI Bus, the successful completion TLP is returned to PCI Express. 62 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 8.7 PCI Express Enhanced Configuration Mechanisms PCI Express Enhanced Configuration Mechanisms The PCI Express Enhanced Configuration mechanism adds four extra bits to the Register Address field, to expand the space to 4,096 bytes. The PEX 8111 forwards Configuration transactions only when the Extended Register Address bits are all zeros (0h). This prevents address aliasing on the PCI Bus, which does not support Extended Register Addressing. When a Configuration transaction targets the PCI Bus and contains a non-zero value in the Extended Register Address bits, the PEX 8111 treats the transaction as if it received a Master Abort on the PCI Bus. The PEX 8111 performs the following: 1. Sets the appropriate status bits for the destination bus, as if the transaction had executed and received a Master Abort. 2. Generates a PCI Express completion with Unsupported Request status. 3. Indexed addressing of the Main Control Block registers. 8.7.1 Memory-Mapped Indirect (Reverse Bridge Mode Only) In Reverse Bridge mode, the PEX 8111 provides the capability for a PCI host to access the downstream PCI Express Configuration registers, using PCI Memory transactions. The 4-KB region of the Memory range defined by the PCI Base Address 0 register is used for this mechanism. Memory reads and writes to PCI Base Address 0 register offsets 2000h to 2FFFh result in a PCI Express Configuration transaction. The Transaction address is determined by the Enhanced Configuration Address register. The format of this Address register is delineated in Table 8-5. After the Enhanced Configuration Address register is programmed to point to a particular device, the entire PCI Express endpoint 4-KB Configuration space is directly accessed, using Memory Read and Write transactions. Only single DWORDs are transferred during Enhanced Configuration transactions. Table 8-5. 31 Enhanced Enable Enhanced Configuration Address Register Format 30 28 Rsvd 27 20 Bus Number 19 15 Device Number 14 12 Function Number PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 11 0 Rsvd 63 Configuration Transactions PLX Technology, Inc. 8.8 Configuration Retry Mechanism 8.8.1 Forward Bridge Mode Bridges are required to return a completion for all Configuration Requests that cross the PEX 8111 from PCI Express-to-PCI, prior to expiration of the Root Complex's Completion Timeout Timer. This requires that bridges take ownership of all Configuration Requests forwarded across the PEX 8111. When the Configuration Request to PCI successfully completes prior to the PEX 8111's CRS Timer (CRS Timer register, offset 1060h) expiration, the PEX 8111 returns a completion with Successful status to PCI Express. When the Configuration Request to PCI encounters an error condition prior to the CRS Timer expiration, the PEX 8111 returns an appropriate error completion to PCI Express. When the Configuration Request to PCI does not complete successfully or with an error, prior to CRS Timer expiration, then the PEX 8111 returns a completion with Configuration Retry Status (CRS) to PCI Express. Although the PEX 8111 returned a completion with CRS to PCI Express, the PEX 8111 continues to keep the Configuration transaction alive on the PCI Bus. The PCI r3.0 states that after a PCI master detects a Target Retry, it must continue to Retry the transaction until at least one DWORD is transferred. The PEX 8111 Retries the transaction until it completes on the PCI Bus, or until the PCI Express-to-PCI Retry Timer expires. When another PCI Express-to-PCI Configuration transaction is detected while the previous one is Retried, a completion with CRS is immediately returned. If the first Configuration transaction completes on the PCI Bus after the second Configuration transaction returns with a completion of CRS status on the PCI Express interface, the PEX 8111 discards the completion information. Bridges that implement this option are also required to implement bit 15 of the PCI Express Device Control register as the Bridge Configuration Retry Enable bit. When the Bridge Configuration Retry Enable bit is cleared, the PEX 8111 does not return a completion with CRS on behalf of Configuration Requests forwarded across the PEX 8111. The lack of a completion results in eventual Completion Timeout at the Root Complex. By default, bridges do not return CRS for Configuration Requests to a PCI device behind the PEX 8111, which might result in lengthy completion delays that must be comprehended by the Completion Timeout value in the Root Complex. 8.8.2 Reverse Bridge Mode In Reverse Bridge mode, the PEX 8111 detects completion with CRS status from a downstream PCI Express device. The Device-Specific Control register CRS Retry Control field determines the PEX 8111 response in Reverse Bridge mode when a PCI-to-PCI Express Configuration transaction is terminated with a Configuration Request Retry Status. Table 8-6. CRS Retry Control CRS Retry Control 64 Response 00b Retry one time after one second. When another CRS is received, Target Abort on the PCI Bus. 01b Retry eight times, one time per second. When another CRS is received, Target Abort on the PCI Bus. 10b Retry one time per second, until successful completion. 11b Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 9 9.1 Bridge Operation Forward Bridge Operation In Forward Bridge mode, the PEX 8111 presents a Type 1 Configuration Space header (bridge) on the PCI Express interface. There are no PCI-Compatible Configuration registers available on the PCI Bus. Three sets of Type 1 Configuration Space Header registers define the bridging operation between the PCI Express interface and PCI Bus. (Refer to Table 9-1.) The PEX 8111 also supports one PCI Base Address register (BAR), which allows a PCI Express or PCI Master to access Internal Configuration registers or shared memory. During bus enumeration, the addresses corresponding to the BAR are excluded from the bridging ranges of the six registers referenced in Table 9-1. Table 9-1. Type 1 Configuration Space Header Register Sets that Define Bridging Operation between PCI Express Interface and PCI Bus Register Set Description I/O Base and I/O Limit When I/O transactions on the PCI Express interface fall within the range specified by these registers, the transactions are forwarded to the PCI Bus. When I/O transactions on the PCI Bus fall outside the range specified by these registers, the transactions are forwarded to the PCI Express interface. Memory Base and Memory Limit When Non-Prefetchable Memory transactions on the PCI Express interface fall within the range specified by these registers, the transactions are forwarded to the PCI Bus. When Non-Prefetchable Memory transactions on the PCI Bus fall outside the range specified by these registers, the transactions are forwarded to the PCI Express interface. Prefetchable Memory Base and Prefetchable Memory Limit When Prefetchable Memory transactions on the PCI Express interface fall within the range specified by these registers, the transactions are forwarded to the PCI Bus. When Prefetchable Memory transactions on the PCI Bus fall outside the range specified by these registers, the transactions are forwarded to the PCI Express interface. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 65 Bridge Operation 9.1.1 PLX Technology, Inc. Forward Bridge Flow Control The PEX 8111 supports the Flow Control mechanism described in the PCI Express Base 1.0a, and provides the minimum flow requirements delineated in Table 9-2. The PEX 8111 advertises infinite credits (initial credit value of 0h) for Completion Header and Completion Data. Buffer space is allocated for the resulting completions. The unit of flow control (FC) for data is 16 bytes. For headers, it is the maximum size header plus TLP Digest. Table 9-2. Flow Control Mechanism Minimum Flow Requirements Credit Type 9.1.2 Minimum Advertisement PH (Posted Request Headers) 8 FC unit - credit value of 08h PD (Posted Request Data payload) 64 FC unit - credit value of 40h NPH (Non-Posted Request Header) 8 FC unit - credit value of 08h NPD (Non-Posted Request Data payload) 8 FC unit - credit value of 08h CPLH (Completion Headers) Infinite - credit value of 00h CPLD (Completion Data payload) Infinite - credit value of 00h Forward Bridge Buffer Size and Management The PEX 8111 provides adequate buffers to accept Data transfers from the PCI Express interface, and to deliver a Read Completion. For upstream requests (PCI-to-PCI Express), the PEX 8111 provides Buffer space for the resultant completion (data and/or header) before the transaction is forwarded to the PCI Express interface. 9.1.3 Forward Bridge Requester ID and Tag Assignment In certain cases, the PEX 8111 must generate a new Requester ID and Tag combination for transactions forwarded to the PCI Express interface. When the PEX 8111 generates a new Requester ID for a transaction forwarded from the secondary interface to the primary interface, the PEX 8111 assigns the PCI Express Requester ID, using the secondary interface's Bus Number, and clears the Device Number and Function Number fields to 0. The Requester ID is a 16-bit field formatted as follows, and the Tag is a unique 8-bit field. 15 8 7 Bus Number 3 2 Device Number 0 Function Number Outstanding Non-Posted transactions (such as transactions requiring a completion) forwarded to the PCI Express interface must have a unique Transaction ID, regardless of whether multiple PCI Express transactions were generated for a single PCI transaction. When a PCI Non-Posted transaction forwarded to the PCI Express interface crosses a 4-KB Address Boundary space, or a Read request exceeds the PCI Express Device Control register Maximum Read Request Size field value, the resulting multiple PCI Express transactions require unique Transaction IDs. 66 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge PCI Express-to-PCI Forwarding (Downstream) 9.1.4 Forward Bridge PCI Express-to-PCI Forwarding (Downstream) 9.1.4.1 Transaction Types Table 9-3 delineates the PCI Express transactions that must be forwarded to the PCI Bus. Table 9-4 delineates the PCI transactions that must be performed on the secondary interface. Table 9-3. Transactions Forwarded to PCI Bus Primary Interface - PCI Express Command Secondary Interface - PCI Command Memory Write Request Memory Write or Memory Write and Invalidate Memory Read Request Memory Read, Memory Read Line, or Memory Read Line Multiple Memory Read Request - Locked Memory Read, Memory Read Line, or Memory Read Line Multiple I/O Write Request I/O Write I/O Read Request I/O Read Type 1 Configuration Write Request Type 0 or Type 1 Configuration Write or special cycle Type 1 Configuration Read Request Type 0 or Type 1 Configuration Read Message Request - Vendor-Defined N/A Message Request with Data Payload - Vendor-Defined N/A Completion or Completion with Data N/A Table 9-4. Transactions Performed on Secondary Interface PEX 8111 Initiator on Secondary Interface PEX 8111 Target on Secondary Interface Interrupt Acknowledge No No Special Cycle Yes No I/O Read Yes Yes I/O Write Yes Yes Memory Read Yes Yes Memory Write Yes Yes Configuration Read Yes No Configuration Write Yes No Memory Read Line Multiple Yes Yes Dual Address Cycle Yes Yes Memory Read Line Yes Yes Memory Write and Invalidate Yes Yes Transaction Type PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 67 Bridge Operation 9.1.4.2 PLX Technology, Inc. Write Transactions PCI Express-to-PCI Write transactions are Posted or Non-Posted, as delineated in Table 9-5. The PEX 8111 accepts Posted transactions without requiring that a completion be returned to the PCI Express interface. Non-Posted Writes do not generate a completion until the transaction completes on the secondary (PCI) bus. Table 9-5. Posted or Non-Posted PCI Express Writes PCI Express Transaction Forwarding Memory Write Request Posted I/O Write Request Non-Posted Type 0 Configuration Write Request Not forwarded Type 1 Configuration Write Request Non-Posted Memory Write Request A PCI Express-to-PCI Memory Write request is performed as a PCI Memory Write or Memory Write and Invalidate transaction. When the PEX 8111 accepts each PCI Express Memory Write request TLP, the Posted Write queue issues a Write request, consisting of the following: * Address (64 bits) * Byte Enables for the first and last DWORDs * TLP total Byte Count (10 bits) * Sequence Number (6 bits) The PCI Express Base 1.0a states that no TLPs can cross a 4-KB Address Boundary space; therefore, boundary checking does not need be performed when each Write request is forwarded to the PCI Bus. When a TLP crosses a 4-KB Address Boundary space, it is treated as a malformed TLP. When the TLP Controller's Posted Write Data queue fills to capacity, the PCI Express Master stops sending data. After transaction ordering requirements on the PCI Bus are met, the PEX 8111 requests the secondary PCI Bus. When the grant is received and the bus is idle, the PEX 8111 drives FRAME#, and the address and command. On the following Clock cycle, the first Data word is driven onto the bus and IRDY# is asserted. Data is transferred to the PCI Target when TRDY# is asserted, and continues transferring until the last word is read from the queue. When a Target Disconnect is detected, the current burst terminates. If there is data remaining in the queue, another Burst Write is initiated with the updated address. This Burst Write continues until the queue is empty, indicating the end of the Write transaction. When a PCI Express-to-PCI Posted Write terminates with a PCI Target Abort, PCI Master Abort, or PCI Retry Abort, the remainder of the data is read from the queue and discarded. An ERR_NONFATAL message is sent to the PCI Express Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. 68 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge PCI Express-to-PCI Forwarding (Downstream) Translation to Memory Write and Invalidate The PEX 8111 supports translation of PCI Express Memory Write requests to PCI Memory Write and Invalidate (MWI) transactions. The PCI Command register Memory Write and Invalidate bit must be set, and the PCI Cache Line Size register must be set to a supported value. The MWI command can be used only when the PCI Express Byte Enables are contiguous. The address, Write request length, and first and last Byte Enables of each request are used to determine whether an MWI command can be used. The transaction length is loaded into an internal counter and compared to the Cache Line Size. An MWI transaction is initiated when the following three conditions exist: * Write request contains at least the number of bytes indicated by the Cache Line Size * Write request starts at a Cache Line boundary * All Byte Enables are asserted An internal counter is decremented as each word is transferred to the PCI Target. At each Cache Line boundary, the counter is used to determine whether there are at least the number of Cache Line Size bytes remaining. If the necessary number of Cache Line size bytes are present, the MWI burst continues; otherwise, the MWI terminates and a Memory Write command transfers the remaining bytes. When a Memory Write request does not begin or end on a Cache Line boundary, the request is segmented into multiple transactions. The bytes up to the first Cache Line boundary are transferred using a Memory Write command. An MWI transaction is then used to transfer the Write data beginning on the aligned Cache Line boundary, including all subsequent complete cache lines up to the final aligned Cache Line boundary contained in the original Memory Write request. A Memory Write transaction is then used to transfer the remaining bytes of the original Memory Write request. I/O and Configuration Writes PCI Express I/O Writes and Type 1 Configuration Writes are Non-Posted Write transactions. That is, the Completion TLP is not returned to the primary (PCI Express) interface until the transaction completes on the secondary (PCI) interface. The forwarding address range of the I/O Writes is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. When the PEX 8111 accepts each PCI Express I/O Write or Type 1 Configuration Write request TLP, the Non-Posted Transaction queue issues a Write request, consisting of the following: * Transaction type * Address (32 bits) * Byte Enables for a single DWORD * TLP total Byte Count (always a value of 1) * Sequence number (6 bits) Because all I/O Writes and Type 1 Configuration Writes are 1 DWORD in length, this DWORD is always the first and last DWORD. These Write transactions complete on the PCI Bus, before the Completion TLP is returned to the PCI Express interface. PCI Express I/O Write requests are translated to PCI I/O Write transactions. PCI Express Configuration Writes are translated to PCI Configuration transactions. The Configuration Write address can be modified to indicate a Type 0, Type 1, or special cycle. Configuration transaction forwarding is discussed in Chapter 8, "Configuration Transactions." PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 69 Bridge Operation PLX Technology, Inc. After the transaction ordering requirements are met, the PEX 8111 requests the secondary (PCI) interface. When the grant is received and the bus is idle, the PEX 8111 drives FRAME#, and the address and command. On the following Clock cycle, the Data word is driven onto the bus and IRDY# is asserted. Data is transferred to the PCI Target when TRDY# is asserted, and the transaction terminates. Only single words are transferred for these transactions. When the transaction successfully completes on the secondary interface, a Completion TLP is transmitted to the PCI Express Initiator. When the transaction terminates with a Master Abort, a completion with Unsupported Request status is returned to the PCI Express interface and the data is discarded. When the transaction terminates with a Target Abort, a completion with Completer Abort status is returned to the PCI Express interface and the data is discarded. An ERR_NONFATAL message is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. When the transaction terminates with a Retry, the PEX 8111 repeats the transaction until the data transfer is complete or an error condition is detected. When the PEX 8111 is unable to deliver Write data after the number of attempts determined by the PCI Control register PCI Express-to-PCI Retry Count field, a completion with Completer Abort status is returned to the PCI Express interface, and the data is discarded. A ERR_NONFATAL message is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. 9.1.4.3 Read Transactions PCI Express-to-PCI Read transactions are Prefetchable or Non-Prefetchable, as delineated in Table 9-6. Because a PCI Express Read request always specifies the number of bytes to read, the PEX 8111 never reads more data than requested. When translating a PCI Express Memory Read request into a PCI transaction, the PEX 8111 uses its Prefetchable and Non-Prefetchable Memory windows to determine the proper PCI Read command to use. Table 9-6. Prefetchable or Non-Prefetchable PCI Express-to-PCI Read Transactions PCI Express Transaction Prefetchable Memory Read Request Yes, when in Prefetchable space I/O Read Request Non-Prefetchable Type 0 Configuration Read Request Not forwarded Type 1 Configuration Read Request Non-Prefetchable Non-Prefetchable Memory Read Transactions When a PCI Express Memory Read falls within Non-Prefetchable Address space, the PEX 8111 uses the PCI Memory Read command to read the number of bytes requested in the PCI Express Memory Read request. The forwarding address range is determined by the Memory Base, Memory Limit, Prefetchable Memory Base, and Prefetchable Memory Limit registers and Bridge Control register VGA Enable bit. 70 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge PCI Express-to-PCI Forwarding (Downstream) Prefetchable Memory Read Transactions When a PCI Express Memory Read falls within Prefetchable Address space, the PEX 8111 uses the PCI Memory Read, Memory Read Line, or Memory Read Line Multiple command. The command type is based on the starting address and the number of bytes in the request. The PEX 8111 does not extend the length of the burst, but reads the number of bytes requested, as per the PCI ExpressBridge r1.0. That is, the PEX 8111 does not prefetch data from the PCI Target, regardless of whether the data is located in Prefetchable Memory space. (Refer to Table 9-7.) Memory Read Line transactions are terminated at a Cache Line boundary when there is not at least one cache line of data remaining to read, or if the transaction can be converted to a Memory Read Line Multiple transaction. Any remaining words are read, using a Memory Read command. Table 9-7. Prefetchable Memory Read Transactions Command Status Memory Read Used when less than a cache line of data is read. Memory Read Line Used when at least one cache line of data is read, and the starting address is not on a Cache Line boundary. Memory Read Line Multiple Used when at least one cache line of data is read, and the starting address is on a Cache Line boundary. Memory Read Request When the PEX 8111 accepts each PCI Express Memory Read request, the Non-Posted Transaction queue issues a Read request, consisting of the following: * Transaction type (Memory Read) * Address (64 bits) * Byte Enables for the first and last DWORD * TLP total Byte Count of (10 bits) * Sequence Number (6 bits) A Memory Read, Memory Read Line, or Memory Read Line Multiple command is performed on the PCI Bus, depending upon the starting address, Byte Enables, and Read request length. After the transaction ordering requirements are met, the PEX 8111 requests the secondary (PCI) interface. When the grant is received and the bus is idle, the PEX 8111 drives FRAME# and the address and command. On the following Clock cycle, IRDY# is asserted. Read data is transferred to the PEX 8111 when TRDY# is asserted, and continues transferring until the Read request length is satisfied or the Target disconnects. As the data is read from the PCI Bus, it is written to the Non-Posted Transaction Completion queue. When the transaction terminates with a Master Abort, a completion with Unsupported Request status is returned to the PCI Express interface. When the transaction terminates with a Target Abort, a completion with Completer Abort status is returned to the PCI Express interface. An ERR_NONFATAL messages is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. When the transaction terminates with a Retry, the PEX 8111 repeats the transaction until the Data transfer is complete or an error condition is detected. When the PEX 8111 is unable to complete the Read transaction after the number of attempts specified by the PCI Control register PCI-to-PCI Express Retry Count field, a completion with Completer Abort status is returned to the PCI Express interface. When a transaction terminates with a PCI Disconnect, the PEX 8111 starts a new Read transaction at the current address, and attempts to complete reading the requested number of bytes. After the transaction is complete, a completion is transmitted to the PCI Express Initiator. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 71 Bridge Operation PLX Technology, Inc. The PEX 8111 does not service a new Memory Read request from the Host (performs Retries on the PCI Bus) until it receives a Completion from the previous Read request sent by the Host or the PCI-toPCI Express Retry Count is exceeded. Memory Read Request Locked A PCI Express Memory Read Request Locked is similar to a normal Memory Read request. Refer to Chapter 11, "Exclusive (Locked) Access," for details. I/O and Configuration Reads PCI Express I/O Reads and Type 1 Configuration Reads are Non-Prefetchable Read transactions. That is, the Byte Enable information is preserved and no additional bytes are requested. The forwarding address range of the I/O Reads is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. When the PEX 8111 accepts each PCI Express I/O Read or Type 1 Configuration Read request, the Non-Posted Transaction queue issues a Read request, consisting of the following: * Transaction type (I/O or Configuration Type 1 Read) * Address (32 bits) * Byte Enables for a single DWORD * TLP total Byte Count (always a value of 1) * Sequence Number (6 bits) An I/O Read or Configuration Read command is performed on the PCI Bus. The Configuration Read address can be modified to indicate a Type 0, Type 1, or special cycle. Configuration transaction forwarding is discussed in Chapter 8, "Configuration Transactions." After the transaction ordering requirements are met, the PEX 8111 requests the secondary (PCI) interface. When the grant is received and the bus is idle, the PEX 8111 drives FRAME#, and the address and command. On the following Clock cycle, IRDY# is asserted. Read data is transferred to the PEX 8111 when TRDY# is asserted, and the transaction terminates. Only single DWORDs are transferred for these transactions. When the transaction terminates with a Master Abort, a completion with Unsupported Request status is returned to the PCI Express interface. When the transaction terminates with a Target Abort, a completion with Completer Abort status is returned to the PCI Express interface. An ERR_NONFATAL message is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. When the transaction terminates with a Retry, the PEX 8111 repeats the transaction until the Data transfer is complete or an error condition is detected. When the PEX 8111 is unable to complete the Read transaction after the number of attempts specified by the PCI Control register PCI-to-PCI Express Retry Count field, a completion with Timeout status is returned to the PCI Express interface. After the transaction is complete, a completion is transmitted to the PCI Express Initiator. The PEX 8111 does not service a new I/O Read request or Type 1 Configuration Read from the Host (performs Retries on the PCI Bus) until it receives a Completion from the previous Read request sent by the Host or the PCI-to-PCI Express Retry Count is exceeded. 72 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge PCI-to-PCI Express Forwarding (Upstream) 9.1.5 Forward Bridge PCI-to-PCI Express Forwarding (Upstream) 9.1.5.1 Transaction Types Table 9-8 delineates the PCI transactions forwarded upstream to the PCI Express interface. Table 9-8. PCI Transactions Forwarded Upstream to PCI Express Interface Secondary Interface - PCI Command 9.1.5.2 Primary Interface - PCI Express Command Memory Write or Memory Write and Invalidate Memory Write Request Memory Read, Memory Read Line or Memory Read Line Multiple Memory Read Request I/O Write I/O Write Request I/O Read I/O Read Request Write Decomposition PCI Write transactions transfer Byte Enables with every Data phase; however, the PCI Express interface supports Byte Enables only on the first and last DWORDs of a request. Furthermore, non-contiguous Byte Enables are permitted only for requests of 1 or 2 DWORDs in length, and requests with no Byte Enables set must use a length of 1 DWORD. Therefore, in certain cases, the PEX 8111 must break up PCI Write requests into multiple PCI Express requests. Byte Enables are always set in PCI Memory Write and Invalidate transactions; therefore, these transactions are not broken up into two separate transactions due to non-contiguous Byte Enables. PCI Express Write transactions cannot cross 4-KB Address boundaries; therefore, PCI Writes are terminated with a Disconnect at 4-KB boundaries. Additionally, PCI Writes are terminated with a Disconnect when the Maximum Payload Size is reached. 9.1.5.3 Read Decomposition PCI Express Read transactions cannot cross 4-KB Address boundaries; therefore, PCI Reads that cross a 4-KB Address Boundary space are broken up into multiple PCI Express Read transactions. When a PCI Read request crosses a 4-KB Address Boundary space, the PEX 8111 disconnects at the boundary. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 73 Bridge Operation 9.1.5.4 PLX Technology, Inc. PCI Express Header Field Formation Rules Table 9-9 delineates the PCI Express Header Field Formation rules. Table 9-9. PCI Express Header Field Formation Rules Header Item 9.1.5.5 Rule Fmt[1:0] Single address PCI cycles (below the 4-GB Address Boundary space) use a 3-DWORD header. Dual Address cycles (at or above the 4-GB boundary) use a 4-DWORD header. Write requests use a request format with data. Type[4:0] Populated, based upon the command translations described in Section 9.1.4.1, "Transaction Types." TC[3:0] For requests, this field must be cleared to 0. For completions, this field must contain the value supplied in the corresponding request. Attr[1:0] These bits include the Relaxed Ordering and No Snoop attributes. Always cleared to 0. TD Cleared to 0. The PEX 8111 does not support ECRC in the TLP Digest. EP Set to 1 when the PEX 8111 is forwarding an Uncorrectable Data error from the PCI Bus. Length[9:0] PCI Write or Read request length, rounded up to nearest DWORD-aligned boundary. Requester ID[15:0] Assigned by the PEX 8111, comprised of the Bus, Device and Function Numbers. Tag[7:0] Sequentially assigned by the PEX 8111. First DWORD Byte Enable[3:0] and Last DWORD Byte Enable[3:0] First and last Byte Enables. Address[63:2] (4-DWORD header) or Address[31:2] (3-DWORD header) Transaction DWORD starting address. Value is derived from the Byte address of the PCI transaction, by rounding the address down to the nearest DWORD-aligned boundary. Requester ID and Tag The PEX 8111 uses the Bus Number (from the Secondary Bus Number register), Device Number (always a value of 0), and Function Number (always a value of 0) to create the Requester ID. The 8-bit Tag is created by the TLP Controller, and is unique for each transaction. Requester ID 15 8 7 Bus Number 74 Tag 3 2 Device Number 0 Function Number 7 0 Tag PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 9.1.5.6 Forward Bridge PCI-to-PCI Express Forwarding (Upstream) Memory Write or Memory Write and Invalidate Memory Write or Memory Write and Invalidate transactions are performed as a PCI Express Memory Write request. The forwarding address range is determined by the Memory Base, Memory Limit, Prefetchable Memory Base, and Prefetchable Memory Limit registers and Bridge Control register VGA Enable bit. Writes cannot cross 4-KB Address boundaries. Write data posting is required for these transactions. The PEX 8111 terminates these transactions with a Retry when the PEX 8111 is locked from the PCI Express interface. When the PEX 8111 determines that a PCI Write transaction is to be forwarded to the PCI Express interface, DEVSEL# and TRDY# are asserted, assuming that there is sufficient space in the 8-DWORD buffer. When there is insufficient Buffer space, the PEX 8111 responds with a Retry. When there is sufficient space, the PEX 8111 accepts Write data until one of the following occurs: * PCI Initiator terminates the transaction by de-asserting FRAME# * 4-KB Address Boundary space is reached * Buffer fills and the Secondary Latency Timer (Forward Bridge mode) or PCI Bus Latency Timer (Reverse Bridge mode) times out * Maximum Payload Size is reached * No Byte Enables, or Partial Byte Enables, are detected during Memory Write When one of these events occurs, the PEX 8111 terminates the PCI transaction with a Disconnect. If no Byte Enables, or partial Byte Enables, are asserted during a DWORD transaction, the Write transaction must be broken up into two separate transactions. The data with no Byte Enables, or partial Byte Enables and the corresponding address are written into the Posted Write Data queue as a new transaction. The TLP Controller prioritizes these transactions. When the Posted Write's Sequence Number is less than that of the Non-Posted transaction, the Posted Write is performed first. When the Posted Write's Sequence Number is greater than that of the Non-Posted transaction, the transactions alternate. 9.1.5.7 Delayed Transactions Non-posted PCI transactions (except Memory Write transactions) are performed as Delayed transactions on the PCI Bus. A Delayed transaction occurs when the PEX 8111 responds to a NonPosted transaction with a Retry, and forwards the request to the PCI Express interface. When the associated completion returns from the PCI Express Target, the PEX 8111 buffers the completion until the PCI Initiator Retries the transaction. The following information is latched from the PCI Bus and stored into the Non-Posted Transaction queue when a new Delayed transaction is detected: * Address * Address Parity * Command * Byte Enables * Data for Write transactions * Data Parity for Write transactions After latching the above information, the PCI transaction terminates with a Retry. The PEX 8111 then transmits the Delayed transaction request upstream to the PCI Express interface: * When the Delayed request is a Read (Memory, I/O, or Configuration), the Read data is read from the PCI Express interface and stored in the TLP Controller. * When the Delayed request is a Write (I/O or Configuration), the Write data is delivered to the PCI Express Target. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 75 Bridge Operation PLX Technology, Inc. At the completion of a Delayed Read, the request in the Non-Posted Transaction queue is tagged as complete. The request is removed from the Non-Posted Transaction queue when the transaction is Retried and completed on the PCI Bus. The PEX 8111 differentiates between PCI transactions by comparing the current transaction with the transaction stored in the Non-Posted Transaction queue. When the Bridge Control register Secondary Parity Error Response Enable bit is cleared to 0, the Address and Data Parity bits are ignored during the comparison. The Byte Enables are ignored when the Read is from the Prefetchable Memory space. When the compare matches a Non-Posted Transaction queue entry, but the transaction is not completed on the PCI Express interface, the transaction is not re-queued, but terminates with a Retry. When the compare matches a Non-Posted Transaction queue entry, and the transaction completed on the PCI Express interface, the transaction completes on the PCI Bus. For a Non-Posted Write, TRDY# is returned, thereby completing the transaction. For a Read transaction, Read data is returned to the PCI Initiator. The PEX 8111 can queue up to four delayed transactions. These transactions are performed on the PCI Express interface in the order that they occurred on the PCI Bus. After Non-Posted Writes are completed on the PCI Express interface, they are completed on the PCI Bus in the order that the PCI Initiator Retries them. Non-Posted Reads are always completed on the PCI Bus in the order they complete on the PCI Express interface. A bridge is permitted to discard a Delayed request. The PEX 8111 never discards a Delayed request that is not completed on the PCI Express interface. A bridge is allowed to discard a Delayed completion in the following two cases only: * If Prefetched data remains in the Delayed Read Data queue when the PCI Initiator terminates the Read transaction, the data is discarded. * Each entry in the Non-Posted Transaction queue has an associated Secondary Discard Timer. The timer is activated when a Read or Write transaction completes on the PCI Express interface. If the PCI Initiator does not Retry the Delayed transaction before the timer times out, the Delayed request and completion are removed from the Non-Posted Transaction queue. The Bridge Control register Discard Timer Status bit is set. In addition, the PEX 8111 transmits an Error message to the PCI Express interface, if enabled, by the Bridge Control register Discard Timer SERR# Enable and PCI Command register SERR# Enable bits. 9.1.5.8 Memory Read, Memory Read Line, or Memory Read Line Multiple Memory Read, Memory Read Line, or Memory Read Line Multiple transactions are performed as a PCI Express Memory Read request. The forwarding address range is determined by the Memory Base, Memory Limit, Prefetchable Memory Base, and Prefetchable Memory Limit registers and Bridge Control register VGA Enable bit. Reads cannot cross 4-KB Address boundaries. This transaction is performed as a Delayed transaction on the PCI Bus. When the PEX 8111 determines that a PCI Read transaction is to be forwarded to the PCI Express interface, DEVSEL# and STOP# are asserted, indicating a Retry. The Address, Address Parity, Command, and Byte Enables are stored in an entry in the Non-Posted Transaction queue, assuming that there is sufficient space in the queue. If there is insufficient space, the transaction is Retried without entering the transaction into the queue. After the request reaches the top of the Non-Posted Transaction queue, a Memory Read request is transmitted to the PCI Express interface. The number of bytes requested from the PCI Express interface is determined by the PCI command, the address space, and the Device-Specific Control register Blind Prefetch Enable bit. (Refer to Table 9-10.) 76 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge PCI-to-PCI Express Forwarding (Upstream) When the starting address and Read request length causes the Read to cross a 4-KB Address Boundary space, the Read request length is truncated so the 4-KB Address Boundary space is not crossed. When the Read request length is greater than the value of the PCI Express Device Control register Maximum Read Request Size field, the request length is truncated to the specified size. When the Read is to Non-Prefetchable Memory, the Byte Enables are passed from the PCI Bus. When the Read is to Prefetchable memory, all Byte Enables are asserted in the PCI Express request. When the Memory Read request does not successfully complete on the PCI Express interface, the Read request entry in the Non-Posted Transaction queue is appropriately marked. When the transaction is Retried on the PCI Bus, it terminates with a Target Abort response. When the Memory Read request successfully completes on the PCI Express interface, the Read request entry in the Non-Posted Transaction queue is marked as complete. When the transaction successfully completes on the PCI Express interface, and all ordering constraints with Posted Write transactions are satisfied, the PEX 8111 transfers data to the PCI Initiator when the Initiator Retries the transaction. The PEX 8111 asserts TRDY# and drives data until the final DWORD is transferred from the queue to the PCI Initiator. When the Initiator terminates the transaction before all queue data is transferred, the remaining data is read from the queue and discarded. Table 9-10. Bytes Requested by PCI Express Interface Determined by PCI Command, Address Space, Register, and Bit after Request Reaches Top of Queue Address Space Blind Prefetch Enable Number of DWORDs Requested Non-prefetchable - 1 Prefetchable 0 1 Prefetchable 1 Cache Line Size Memory Read Line - - Cache Line Size Memory Read Line Multiple - - 2 Cache Line Sizes PCI Transaction Memory Read Blind Prefetch When Blind Prefetch mode is enabled (Device-Specific Control register Blind Prefetch Enable bit is set), the PEX 8111 can prefetch a user-defined data block from the host when a Memory Read transaction is performed, instead of one DWORD at a time in standard operation. Prefetching can improve Read performance, because the PEX 8111 can burst its Prefetchable data onto the PCI Bus when the Endpoint requests it. The PEX 8111 discards remaining unused data. The Prefetch Size can be programmed from 0 to 4 KB of data, by way of the PCI Control register Programmed Prefetch Size field. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 77 Bridge Operation 9.1.5.9 PLX Technology, Inc. I/O Write I/O Write transactions are performed as a PCI Express I/O Write request. The forwarding address range is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. This transaction is performed as a Delayed transaction on the PCI Bus. Posting these transactions is not permitted. A completion must be received from the PCI Express Target before the transaction is completed on the PCI Bus. When the PEX 8111 determines that a PCI I/O Write transaction is to be forwarded to the PCI Express interface, DEVSEL# and STOP# are asserted, indicating a Retry. The Address, Address Parity, Command, Data, Data Parity, and Byte Enables are stored into an entry in the Non-Posted Transaction queue, assuming that there is sufficient space in the queue. If there is insufficient space, the transaction is Retried without entering the transaction into the queue. After the request reaches the top of the Non-Posted Transaction queue, an I/O Write request is transmitted to the PCI Express interface. The Byte Enables are passed through from the PCI Bus, and only 1 DWORD is transferred. When the Write request does not successfully complete on the PCI Express interface, the Write request entry in the Non-Posted Transaction queue is appropriately marked. When the transaction is Retried on the PCI Bus, it terminates with a Target Abort response. When the I/O Write request successfully completes on the PCI Express interface, the I/O Write request entry in the Non-Posted Transaction queue is marked as complete. When the transaction successfully completes on the PCI Express interface, the PEX 8111 asserts TRDY# to complete the transaction when the Initiator Retries the transaction. The I/O Write request is removed from the Non-Posted Transaction queue when the PCI Initiator Retries the transaction and the transaction completes (successfully or not) on the PCI Express interface. 9.1.5.10 I/O Read I/O Read transactions are performed as a PCI Express I/O Read request. The forwarding address range is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. This transaction is performed as a Delayed transaction on the PCI Bus. When the PEX 8111 determines that a PCI I/O Read transaction is to be forwarded to the PCI Express interface, DEVSEL# and STOP# are asserted, indicating a Retry. The Address, Command, Address Parity, and Byte Enables are stored into an entry in the Non-Posted Transaction queue, assuming that there is sufficient space in the queue. If there is insufficient space, the transaction is Retried without entering the transaction into the queue. After the request reaches the top of the Non-Posted Transaction queue, an I/O Read request is transmitted to the PCI Express interface. The Byte Enables are passed through from the PCI Bus, and only 1 DWORD is requested. When all ordering constraints with Posted Write transactions are satisfied, the PEX 8111 transfers data to the PCI Initiator when the Initiator Retries the transaction. The PEX 8111 asserts TRDY# and drives a single DWORD of data from the queue to the PCI Initiator. If the I/O Read request does not successfully complete on the PCI Express interface, the Read request entry in the Non-Posted Transaction queue is appropriately marked. When the transaction is Retried on the PCI Bus, it terminates with a Target Abort response. When the I/O Read request successfully completes on the PCI Express interface, the Read request entry in the Non-Posted Transaction queue is marked as complete. 78 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 9.1.6 Forward Bridge PCI Transaction Terminations Forward Bridge PCI Transaction Terminations Table 9-11 delineates the transaction termination methods used by PCI Initiators. Table 9-12 delineates the transaction termination methods used by PCI Targets. Table 9-11. PCI Initiator Transaction Termination Methods Termination Methods Description Normal Termination The Initiator de-asserts FRAME# at the beginning of the last Data phase and de-asserts IRDY# at the end of the last Data phase if the Target asserts TRDY# or STOP#. Master Abort If the Initiator does not detect DEVSEL# asserted from the Target within five Clock cycles after asserting FRAME#, the transaction terminates with a Master Abort. If FRAME# remains asserted, the Initiator deasserts FRAME# on the next cycle, then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is de-asserted, IRDY# can be de-asserted on the next Clock cycle following detection of the Master Abort condition. Table 9-12. PCI Target Transaction Termination Methods Termination Methods Description Normal Termination TRDY# and DEVSEL# are asserted in conjunction with FRAME# de-assertion and IRDY# assertion. Target Retry STOP# and DEVSEL# asserted without TRDY# during the first Data phase. No Data transfers occur during the transaction, and the Initiator must repeat the transaction. Target Disconnect with Data STOP# and DEVSEL# asserted with TRDY#, which indicates that this is the last transfer of the transaction. If FRAME# is de-asserted, this is considered a normal termination, although STOP# is asserted. Target Disconnect without Data STOP# and DEVSEL# are asserted without TRDY# after previous data transfers occurred, which indicates that no further Data transfers occur during this transaction. Target Abort STOP# is asserted without DEVSEL# and TRDY#, which indicates that the Target is never able to complete this transaction. DEVSEL# must be asserted for at least one Clock cycle during the transaction; otherwise, the Initiator detects a Master Abort. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 79 Bridge Operation 9.1.6.1 PLX Technology, Inc. PCI Master Termination Initiated by PEX 8111 The PEX 8111, as a PCI Initiator, uses normal termination if the Target asserts DEVSEL# within five Clock cycles of FRAME# assertion. As an Initiator, the PEX 8111 terminates a transaction when any of the following occur: * During a Delayed Write transaction (I/O or Configuration Write), a single DWORD is delivered * During a Non-Prefetchable Read (Memory, I/O, or Configuration), a single DWORD is read from the Target * In the case of a Prefetchable Read transaction, the number of words requested in the PCI Express request are read from the PCI Target * In the case of a Posted Write transaction, the last word for the transaction is written to the PCI Target * In the case of a Burst transfer, with the exception of Memory Write and Invalidate transactions, the Master Latency Timer expires and the PCI Bus Grant is de-asserted * The Target terminates the transaction with a Retry, Disconnect, or Target Abort When a Posted Write or Prefetchable Read transaction terminates because of a latency timeout, another transaction is initiated to complete the transfer. 9.1.6.2 PCI Master Abort Received by PEX 8111 When the PEX 8111, as a PCI Initiator, does not detect DEVSEL# asserted from the Target within five Clock cycles after asserting FRAME#, the PEX 8111 terminates the transaction with a Master Abort. In Forward Bridge mode, the Secondary Status register Secondary Received Master Abort bit is set. In Reverse Bridge mode, the PCI Status register Received Master Abort bit is set. Refer to Chapter 10, "Error Handling," and Chapter 11, "Exclusive (Locked) Access," for further details. 80 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 9.1.6.3 Forward Bridge PCI Transaction Terminations Delayed Write Target Termination Response When the PEX 8111 initiates a Delayed Write transaction on the PCI Bus, it responds to certain Target terminations as delineated in Table 9-13. Table 9-13. PEX 8111 Response to Target Terminations upon Delayed Write Transactions Target Termination 9.1.6.4 PEX 8111 Response Normal Return completion with Successful Completion status to the PCI Express interface. Target Retry Repeat Write transaction for up to 224 attempts. Target Disconnect Return completion with Successful Completion status to the PCI Express interface. Target Abort Return completion with Completer Abort status to the PCI Express interface. Discard Delayed Write request. Forward Bridge mode - Set the Secondary Status register Secondary Received Target Abort bit. Reverse Bridge mode - Set the PCI Status register Received Target Abort bit. Posted Write Target Termination Response When the PEX 8111 initiates a Posted Write transaction on the PCI Bus, it responds to certain Target terminations as delineated in Table 9-14. Table 9-14. PEX 8111 Response to Target Terminations upon Posted Write Transactions Target Termination PEX 8111 Response Normal No action. Target Retry Repeat Write transaction for up to 224 attempts. Target Disconnect Initiate Write transaction to deliver remaining Posted Write data. Target Abort Discard Posted Write data. Forward Bridge mode - Set the Secondary Status register Secondary Received Target Abort bit. Reverse Bridge mode - Set the PCI Status register Received Target Abort bit. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 81 Bridge Operation 9.1.6.5 PLX Technology, Inc. Delayed Read Target Termination Response When the PEX 8111 initiates a Delayed Read transaction on the PCI Bus, it responds to certain Target terminations as delineated in Table 9-15. Table 9-15. PEX 8111 Response to Target Terminations upon Delayed Read Transactions Target Termination 9.1.6.6 PEX 8111 Response Normal Return completion with Successful Completion status to the PCI Express interface. Target Retry Repeat Read transaction for up to 224 attempts. Target Disconnect Initiate Read transaction to obtain remaining Read data. Target Abort Return completion with Completer Abort status to the PCI Express interface. Discard Delayed Read request. Forward Bridge mode - Set the Secondary Status register Secondary Received Target Abort bit. Reverse Bridge mode - Set the Set the PCI Status register Received Target Abort bit. Target Retry Initiated by PEX 8111 The PEX 8111 returns a Target Retry to a PCI Initiator when any of the following conditions are met: * Delayed Write transactions - Transaction is entering the Non-Posted Transaction queue - Transaction is stored into the Non-Posted Transaction queue; however the transaction is not completed on the PCI Express interface - Non-Posted Transaction queue is full, and the transaction cannot be queued - Transaction with the same address and bus command is queuing - Locked sequence is propagated across the PEX 8111, and the Write transaction is not a Locked transaction * Delayed Read transactions - Transaction is entering the Non-Posted Transaction queue - Transaction is stored in the Non-Posted Transaction queue, but the Read data is not yet available - Read was received from the PCI Express interface; however, a Posted Write transaction precedes it - Non-Posted Transaction queue is full, and the transaction cannot be queued - Transaction with the same address and bus command was queued - Locked sequence is propagated across the PEX 8111, and the Read transaction is not a Locked transaction - PEX 8111 is currently discarding previously prefetched Read data * Posted Write transactions - PCI-to-PCI Express 8-DWORD Write buffer is not empty - Locked sequence is propagated across the PEX 8111, and the Write transaction is not a Locked transaction 82 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 9.1.6.7 Forward Bridge PCI Transaction Terminations Target Disconnect Initiated by PEX 8111 The PEX 8111 returns a Target Disconnect to a PCI Initiator when any of the following conditions are met: * A 4-KB Address Boundary space or Cache Line boundary is reached * 8-DWORD Posted Write buffer fills and the Secondary Latency Timer (Forward Bridge mode) or PCI Bus Latency Timer (Reverse Bridge mode) times out * 8-DWORD Read buffer becomes empty and the Secondary Latency Timer (Forward Bridge mode) or PCI Bus Latency Timer (Reverse Bridge mode) times out * Maximum Payload Size is reached * Byte Enables not set for Posted Write 9.1.6.8 Target Abort Initiated by PEX 8111 The PEX 8111 returns a Target Abort to a PCI Initiator when the PEX 8111 is unable to obtain Read data from, or write data to, the PCI Express interface. Refer to Chapter 10, "Error Handling," for further details. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 83 Bridge Operation 9.2 PLX Technology, Inc. Reverse Bridge Operation In Reverse Bridge mode, the PEX 8111 presents a Type 1 Configuration Space header on the PCI Bus. There are no PCI-Compatible Configuration registers available on the PCI Express interface. Three sets of Type 1 Configuration Space Header registers define the bridging operation between the PCI Bus and PCI Express interface. (Refer to Table 9-16.) The PEX 8111 also supports one PCI Base Address register (BAR), which allows a PCI Express or PCI Master to access internal Configuration registers or shared memory. During bus enumeration, the addresses corresponding to the BAR are excluded from the bridging ranges of the six registers referenced in Table 9-16. Table 9-16. Type 1 Configuration Space Header Register Sets that Define Bridging Operation between PCI Bus and PCI Express Interface Register Set 84 Description I/O Base and I/O Limit When I/O transactions on the PCI Bus fall within the range specified by these registers, the transactions are forwarded to the PCI Express interface. When I/O transactions on the PCI Express interface fall outside the range specified by these registers, the transactions are forwarded to the PCI Bus. Memory Base and Memory Limit When Non-Prefetchable Memory transactions on the PCI Bus fall within the range specified by these registers, the transactions are forwarded to the PCI Express interface. When Non-Prefetchable Memory transactions on the PCI Express interface fall outside the range specified by these registers, the transactions are forwarded to the PCI Bus. Prefetchable Memory Base and Prefetchable Memory Limit When Prefetchable Memory transactions on the PCI Bus fall within the range specified by these registers, the transactions are forwarded to the PCI Express interface. When Prefetchable Memory transactions on the PCI Express interface fall outside the range specified by these registers, the transactions are forwarded to the PCI Bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Reverse Bridge PCI-to-PCI Express Forwarding (Downstream) 9.2.1 Reverse Bridge PCI-to-PCI Express Forwarding (Downstream) 9.2.1.1 Transaction Types Table 9-17 delineates the PCI transactions forwarded to the PCI Express interface. Table 9-18 delineates the PCI transactions performed on the primary interface. The data paths and control logic for Reverse Bridge mode are the same as those used for Forward Bridge mode, except that address decoding based upon the Configuration registers are located on the PCI Bus. Table 9-17. PCI Transactions Forwarded to PCI Express Interface Primary Interface - PCI Command Secondary Interface - PCI Express Command Memory Write or Memory Write and Invalidate Memory Write Request Memory Read, Memory Read Line, or Memory Read Line Multiple Memory Read Request Memory Read, Memory Read Line, or Memory Read Line Multiple, LOCK# asserted Memory Read Request - Locked I/O Write I/O Write Request I/O Read I/O Read Request Type 1 Configuration Write Type 0 or Type 1 Configuration Write Request Type 1 Configuration Read Type 0 or Type 1 Configuration Read Request Table 9-18. PCI Transactions Performed on Primary Interface PEX 8111 Initiator on Primary Interface PEX 8111 Target on Primary Interface Interrupt Acknowledge No No Special Cycle No No I/O Write Yes Yes I/O Read Yes Yes Memory Write Yes Yes Memory Read Yes Yes Configuration Write No Yes Configuration Read No Yes Memory Write and Invalidate Yes Yes Memory Read Line Yes Yes Memory Read Line Multiple Yes Yes Dual Address Cycle Yes Yes Transaction PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 85 Bridge Operation 86 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 10 10.1 Error Handling Forward Bridge Error Handling For all errors detected by the PEX 8111, it sets the appropriate error status bit [both legacy PCI error bit(s) and PCI Express error status bit(s)], and optionally generates an error message on PCI Express. Each error condition has a default error severity level, with a corresponding error message generated on PCI Express. Error message generation on the PCI Express interface is controlled by four Control bits: * PCI Command register SERR# Enable bit * PCI Express Device Control register Fatal Error Reporting Enable bit * PCI Express Device Control register Non-Fatal Error Reporting Enable bit * PCI Express Device Control register Correctable Error Reporting Enable bit PCI Express ERR_FATAL messages are enabled for transmission when the SERR# Enable or Fatal Error Reporting Enable bit is set. ERR_NONFATAL messages are enabled for transmission when either the SERR# Enable or Non-Fatal Error Reporting Enable bit is set. ERR_COR messages are enabled for transmission when the Correctable Error Reporting Enable bit is set. The PCI Express Device Status register Fatal Error Detected, Non-Fatal Error Detected, and Correctable Error Detected status bits are set for the corresponding errors on PCI Express, regardless of the Error Reporting Enable bits. 10.1.1 Forward Bridge PCI Express Originating Interface (Primary to Secondary) This section describes error support for transactions that cross the PEX 8111 when the originating side is the PCI Express interface, and the destination side is the PCI Bus. When a Write Request or Read Completion is received with a poisoned TLP, the entire data payload of the PCI Express transaction must be considered as corrupt. Invert the parity for all data when completing the transaction on the PCI Bus. Table 10-1 provides the translation a bridge must perform when it forwards a non-posted PCI Express request (read or write) to the PCI Bus, and the request is immediately completed on the PCI Bus, either normally or with an error condition. Table 10-1. Translation Performed when Bridge Forwards a Non-Posted PCI Express Request Immediate PCI Termination PCI Express Completion Status Data Transfer with Parity error (reads) Successful (poisoned TLP) Completion with Parity error (Non-Posted writes) Unsupported Request Master Abort Unsupported Request Target Abort Completer Abort PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 87 Error Handling 10.1.1.1 PLX Technology, Inc. Received Poisoned TLP When the PEX 8111 PCI Express interface receives a Write request or Read Completion with poisoned data, the following occur: * PCI Status register Detected Parity Error bit is set * PCI Status register Master Data Parity Error bit is set when the poisoned TLP is a Read Completion and the PCI Command register Parity Error Response Enable bit is set * ERR_NONFATAL message is generated on PCI Express, when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set * Parity bit associated with each DWORD of data is inverted * For a poisoned write request, the Secondary Status register Secondary Master Data Parity Error bit is set when the Bridge Control register Secondary Parity Error Response Enable bit is set, and the PEX 8111 sees PERR# asserted when the inverted parity is detected by the PCI target device 10.1.1.2 PCI Uncorrectable Data Errors The following sections describe how errors are handled when forwarding non-poisoned PCI Express transactions to the PCI Bus, and an Uncorrectable PCI error is detected. Immediate Reads When the PEX 8111 forwards a Read Request (I/O, Memory, or Configuration) from the PCI Express and detects an Uncorrectable Data error on the secondary bus while receiving an immediate response from the completer, the following occur: * Secondary Status register Secondary Master Data Parity Error bit is set when the Bridge Control register Secondary Parity Error Response Enable bit is set * Secondary Status register Secondary Detected Parity Error bit is set * PERR# is asserted on the secondary interface when the Bridge Control register Secondary Parity Error Response Enable bit is set After detecting an Uncorrectable Data error on the destination bus for an Immediate Read transaction, the PEX 8111 continues to fetch data until the Byte Count is satisfied or the target ends the transaction. When the PEX 8111 creates the PCI Express completion, it forwards it with Successful Completion and poisons the TLP. Posted Writes When the PEX 8111 detects PERR# asserted on the PCI secondary interface while forwarding a non-poisoned Posted Write transaction from PCI Express, the following occur: * Secondary Status register Secondary Master Data Parity Error bit is set when the Bridge Control register Secondary Parity Error Response Enable bit is set * ERR_NONFATAL message is generated on PCI Express, when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set * After the error is detected, the remainder of the data is forwarded 88 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge PCI Express Originating Interface (Primary to Secondary) Non-Posted Writes When the PEX 8111 detects PERR# asserted on the PCI secondary interface while forwarding a non-poisoned non-posted write transaction from PCI Express, the following occur: * Secondary Status register Secondary Master Data Parity Error bit is set when the Bridge Control register Secondary Parity Error Response Enable bit is set * PCI Express completion with Unsupported Request status is generated * ERR_NONFATAL message is generated on PCI Express, when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set 10.1.1.3 PCI Address Errors When the PEX 8111 forwards transactions from PCI Express-to-PCI, PCI Address errors are reported by SERR# assertion. When the PEX 8111 detects SERR# asserted, the following occur: * Secondary Status register Secondary Received System Error bit is set * ERR_FATAL message is generated on PCI Express, when the following conditions are met: - Bridge Control register Secondary SERR# Enable bit is set - PCI Command register SERR# Enable bit or PCI Express Device Control register Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the Secondary SERR# Enable and SERR# Enable bits are set 10.1.1.4 PCI Master Abort on Posted Transaction When a Posted Write transaction forwarded from PCI Express-to-PCI results in a Master Abort on the PCI Bus, the following occur: * Entire transaction is discarded * Secondary Status register Secondary Received Master Abort bit is set * ERR_NONFATAL message is generated on PCI Express when the following conditions are met: - Bridge Control register Master Abort Mode bit is set - PCI Command register SERR# Enable bit or PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the Master Abort Mode and SERR# Enable bits are set 10.1.1.5 PCI Master Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express-to-PCI results in a Master Abort on the PCI Bus, the following occur: * Completion with Unsupported Request status is returned on PCI Express * Secondary Status register Secondary Received Master Abort bit is set PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 89 Error Handling 10.1.1.6 PLX Technology, Inc. PCI Target Abort on Posted Transaction When a transaction forwarded from PCI Express-to-PCI results in a Target Abort on the PCI Bus, the following occur: * Entire transaction is discarded * Secondary Status register Secondary Received Target Abort bit is set * ERR_NONFATAL message is generated on PCI Express when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set 10.1.1.7 PCI Target Abort on Non-Posted Transaction When a transaction forwarded from PCI Express-to-PCI results in a Target Abort on the PCI Bus, the following occur: * Completion with Completer Abort status is returned on the PCI Express * Secondary Status register Secondary Received Target Abort bit is set * PCI Status register Signaled Target Abort bit is set * ERR_NONFATAL message is generated on PCI Express when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set 10.1.1.8 PCI Retry Abort on Posted Transaction When a transaction forwarded from PCI Express-to-PCI results in the maximum number of PCI Retries (selectable in the PCI Control register), the following occur: * Remaining data is discarded * Interrupt Request Status register PCI Express-to-PCI Retry Interrupt bit is set 10.1.1.9 PCI Retry Abort on Non-Posted Transaction When a transaction forwarded from PCI Express-to-PCI results in the maximum number of PCI Retries (selectable in the PCI Control register), the following occur: * Completion with the Completer Abort status is returned on PCI Express * Interrupt Request Status register PCI Express-to-PCI Retry Interrupt bit is set * PCI Status register Signaled Target Abort bit is set 90 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 10.1.2 Forward Bridge PCI Originating Interface (Secondary to Primary) Forward Bridge PCI Originating Interface (Secondary to Primary) This section describes error support for transactions that cross the PEX 8111 when the originating side is the PCI Bus, and the destination side is PCI Express. The PEX 8111 supports TLP poisoning as a transmitter to permit proper forwarding of Parity errors that occur on the PCI interface. Posted Write data received on the PCI interface with bad parity is forwarded to PCI Express as Poisoned TLPs. Table 10-2 provides the error forwarding requirements for Uncorrectable data errors detected by the PEX 8111 when a transaction targets the PCI Express interface. Table 10-3 describes the PEX 8111's behavior on a PCI Delayed transaction that is forwarded by a bridge to PCI Express as a Memory Read request or an I/O Read/Write request, and the PCI Express interface returns a completion with UR or CA status for the request. Table 10-2. Error Forwarding Requirements Received PCI Error Forwarded PCI Express Error Write with Parity error Write request with poisoned TLP Read Completion with Parity error in Data phase Read completion with poisoned TLP Configuration or I/O Completion with Parity error in Data phase Read/Write completion with Completer Abort Status Table 10-3. PEX 8111 Behavior on a PCI Delayed Transaction PCI Express Completion Status PCI Immediate Response Master Abort Mode = 1 Master Abort Mode = 0 Unsupported Request (on Memory Read or I/O Read) Target Abort Normal completion, return FFFF_FFFFh Unsupported Request (on I/O Write) Target Abort Normal completion Completer Abort PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Target Abort 91 Error Handling 10.1.2.1 PLX Technology, Inc. Received PCI Errors Uncorrectable Data Error on Non-Posted Write When a Non-Posted write is addressed such that it crosses the PEX 8111, and the PEX 8111 detects an Uncorrectable Data error on the PCI interface, the following occur: * Secondary Status register Secondary Detected Parity Error status bit is set. * If the Bridge Control register Secondary Parity Error Response Enable bit is set, the transaction is discarded and is not forwarded to PCI Express. The PERR# signal is asserted on the PCI Bus. * If the Bridge Control register Secondary Parity Error Response Enable bit is not set, the data is forwarded to PCI Express as a poisoned TLP. Also, set the PCI Status register Master Data Parity Error bit when the PCI Command register Parity Error Response Enable bit is set. The PERR# signal is not asserted on the PCI Bus. Uncorrectable Data Error on Posted Write When the PEX 8111 detects an Uncorrectable Data error on the PCI secondary interface for a Posted Write transaction that crosses the PEX 8111, the following occur: * PCI PERR# signal is asserted when the Bridge Control register Secondary Parity Error Response Enable bit is set * Secondary Status register Secondary Detected Parity Error status bit is set * Posted Write transaction is forwarded to PCI Express as a poisoned TLP * PCI Status register Master Data Parity Error bit is set when the PCI Command register Parity Error Response Enable bit is set Uncorrectable Data Error on PCI Delayed Read Completions When the PEX 8111 forwards a non-poisoned Read Completion from PCI Express-to-PCI, and it detects PERR# asserted by the PCI master, the remainder of the completion is forwarded. When the PEX 8111 forwards a poisoned Read Completion from PCI Express-to-PCI, the PEX 8111 proceeds with the above mentioned actions when it detects the PERR# signal asserted by the PCI master; however, no error message is generated on PCI Express. Uncorrectable Address Error When an uncorrectable address error is detected by the PEX 8111, and parity error detection is enabled by way of the Bridge Control register Secondary Parity Error Response Enable bit, the following occur: * Transaction is terminated with a Target Abort * Secondary Status register Secondary Detected Parity Error status bit is set, independent of the setting of the Bridge Control register Secondary Parity Error Response Enable bit * Secondary Status register Secondary Signaled Target Abort bit is set * ERR_FATAL message is generated on PCI Express when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set 92 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 10.1.2.2 Forward Bridge PCI Originating Interface (Secondary to Primary) Unsupported Request (UR) Completion Status The PEX 8111 provides two methods for handling a PCI Express completion received with Unsupported Request (UR) status in response to a request originated by the PCI interface. The response is controlled by the Bridge Control register Master Abort Mode bit. In either case, the PCI Status register Received Master Abort bit is set. Master Abort Mode Bit Cleared This is the default PCI compatibility mode, and an Unsupported Request is not considered to be an error. When a Read transaction initiated on the PCI results in the return of a completion with Unsupported Request status, the PEX 8111 returns FFFFFFFFh to the originating master and terminates the Read transaction on the originating interface normally (by asserting TRDY#). When a Non-Posted Write transaction results in a completion with Unsupported Request status, the PEX 8111 completes the Write transaction on the originating bus normally (by asserting TRDY#) and discards the Write data. Master Abort Mode Bit Set When the Bridge Control register Master Abort Mode bit is set, the PEX 8111 signals a Target Abort to the originating master of an Upstream Read or Non-Posted Write transaction when the corresponding request on the PCI Express interface results in a completion with UR Status. In addition, the Secondary Status register Secondary Signaled Target Abort bit is set. 10.1.2.3 Completer Abort (CA) Completion Status When the PEX 8111 receives a completion with Completer Abort status on the PCI Express primary interface in response to forwarded non-posted PCI transactions, the PCI Status register Received Target Abort bit is set. A CA response can result in a Delayed Transaction Target Abort on the PCI Bus. The PEX 8111 provides data to the requesting PCI agent, up to the point where data was successfully returned from the PCI Express interface, then signals Target Abort. The Secondary Status register Secondary Signaled Target Abort bit is set when signaling Target Abort to a PCI agent. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 93 Error Handling PLX Technology, Inc. 10.1.3 Forward Bridge Timeout Errors 10.1.3.1 PCI Express Completion Timeout Errors The PCI Express Completion Timeout mechanism allows requesters to abort a non-posted request when a completion does not arrive within a reasonable length of time. Bridges, when acting as initiators on PCI Express on behalf of internally generated requests or when forwarding requests from a secondary interface, behave as endpoints for requests of which they take ownership. When a completion timeout is detected and the link is up, the PEX 8111 responds as if a completion with Unsupported Request status is received. The following action is taken: * ERR_NONFATAL message is generated on PCI Express when the following conditions are met: - PCI Command register SERR# Enable bit is set -OR- - PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set When the link is down, the PCI Control register PCI Express-to-PCI Retry Count field determines the number of PCI Retries before a Master Abort is returned to the PCI Bus. 10.1.3.2 PCI Delayed Transaction Timeout Errors The PEX 8111 includes Delayed Transaction Timers for each queued Delayed transaction. When a Delayed transaction timeout is detected, the following occur: * ERR_NONFATAL message is generated on PCI Express when the following conditions are met: - Bridge Control register Discard Timer SERR# Enable bit is set - PCI Command register SERR# Enable bit or PCI Express Device Control register Non-Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the SERR# Enable bit is set * Bridge Control register Discard Timer Status bit is set 10.1.4 Forward Bridge "Other" Errors PCI devices assert SERR# when detecting errors that compromise system integrity. When the PEX 8111 detects SERR# asserted on the secondary (PCI) bus, the following occur: * Secondary Status register Secondary Received System Error bit is set * ERR_FATAL message is generated on PCI Express, when the following conditions are met: - Bridge Control register Secondary SERR# Enable bit is set - PCI Command register SERR# Enable bit or PCI Express Device Control register Fatal Error Reporting Enable bit is set * PCI Status register Signaled System Error bit is set when the Secondary SERR# Enable and SERR# Enable bits are set 94 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 10.2 Reverse Bridge Error Handling Reverse Bridge Error Handling For all errors detected by the PEX 8111, it sets the appropriate error status bit [both legacy PCI error bit(s) and PCI Express error status bit(s)]. PCI Express Error messages are not generated in Reverse Bridge mode. 10.2.1 Reverse Bridge PCI Express Originating Interface (Secondary to Primary) This section describes error support for transactions that cross the PEX 8111 when the originating side is the PCI Express (secondary) interface, and the destination side is the PCI (primary) interface. Table 10-4 provides the translation the PEX 8111 performs when it forwards a non-posted PCI Express request (read or write) to the PCI Bus, and the request is immediately completed on the PCI Bus, either normally or with an error condition. Table 10-4. 10.2.1.1 PEX 8111 Translation - Non-Posted PCI Request Immediate PCI Termination PCI Express Completion Status Data Transfer with Parity error (reads) Successful (poisoned TLP) Completion with Parity error (Non-Posted writes) Unsupported Request Master Abort Unsupported Request Target Abort Completer Abort Received Poisoned TLP When a Write Request or Read Completion is received by the PCI Express interface, and the data is poisoned, the following occur: * Secondary Status register Secondary Detected Parity Error bit is set * Secondary Status register Secondary Master Data Parity Error bit is set when the poisoned TLP is a Read Completion and the Bridge Control register Secondary Parity Error Response Enable bit is set * Parity bit associated with each DWORD of data is inverted * For a poisoned Write request, the PCI Status register Master Data Parity Error bit is set when the PCI Command register Parity Error Response Enable bit is set, and the PEX 8111 sees PERR# asserted when the inverted parity is detected by the PCI target device PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 95 Error Handling 10.2.1.2 PLX Technology, Inc. PCI Uncorrectable Data Errors The following sections describe how errors are handled when forwarding non-poisoned PCI Express transactions to the PCI Bus, and an Uncorrectable PCI error is detected. Immediate Reads When the PEX 8111 forwards a Read Request (I/O or Memory) from the PCI Express secondary interface and detects an Uncorrectable Data error on the PCI primary bus while receiving an immediate response from the completer, the following occur: * PCI Status register Master Data Parity Error bit is set when the PCI Command register Parity Error Response Enable bit is set * PCI Status register Detected Parity Error bit is set * PERR# is asserted on the PCI interface when the PCI Command register Parity Error Response Enable bit is set After detecting an Uncorrectable Data error on the destination bus for an immediate Read transaction, the PEX 8111 continues to fetch data until the Byte Count is satisfied or the target ends the transaction. When the PEX 8111 creates the PCI Express completion, it forwards it with Successful Completion status and poisons the TLP. Non-Posted Writes When the PEX 8111 detects PERR# asserted on the PCI primary interface while forwarding a non-poisoned Non-Posted Write transaction from PCI Express, the following occur: * PCI Status register Master Data Parity Error bit is set when the PCI Command register Parity Error Response Enable bit is set * PCI Express completion with Unsupported Request status is returned Posted Writes When the PEX 8111 detects PERR# asserted on the PCI primary interface while forwarding a non-poisoned Posted Write transaction from PCI Express, the following occur: * PCI Status register Master Data Parity Error bit is set when the PCI Command register Parity Error Response Enable bit is set * After the error is detected, the remainder of the data is forwarded 10.2.1.3 PCI Address Errors When the PEX 8111 forwards transactions from PCI Express-to-PCI, PCI Address errors are reported by SERR# assertion by the PCI target. The PEX 8111 ignores the SERR# assertion, and allows the PCI Central Resource Function to service the error. 10.2.1.4 PCI Master Abort on Posted Transaction When a transaction forwarded from PCI Express-to-PCI results in a Master Abort on the PCI Bus, the following occur: * Entire transaction is discarded * PCI Status register Received Master Abort bit is set 96 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 10.2.1.5 Reverse Bridge PCI Express Originating Interface (Secondary to Primary) PCI Master Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express-to-PCI results in a Master Abort on the PCI Bus, the following occur: * PCI Express completion with Unsupported Request status is returned * PCI Status register Received Master Abort bit is set 10.2.1.6 PCI Target Abort on Posted Transaction When a Posted transaction forwarded from PCI Express-to-PCI results in a Target Abort on the PCI Bus, the following occur: * Entire transaction is discarded * PCI Status register Received Target Abort bit is set 10.2.1.7 PCI Target Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express-to-PCI results in a Target Abort on the PCI Bus, the following occur: * PCI Express completion with Completer Abort status is returned * PCI Status register Received Target Abort bit is set 10.2.1.8 PCI Retry Abort on Posted Transaction When a Posted transaction forwarded from PCI Express-to-PCI results in a Retry Abort on the PCI Bus, the following occur: * Entire transaction is discarded * Interrupt Request Status register PCI Express-to-PCI Retry Interrupt bit is set 10.2.1.9 PCI Retry Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express-to-PCI results in a Retry Abort on the PCI Bus, the following occur: * PCI Express completion with Completer Abort status is returned * Interrupt Request Status register PCI Express-to-PCI Retry Interrupt bit is set * Secondary Status register Secondary Signaled Target Abort bit is set PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 97 Error Handling 10.2.2 PLX Technology, Inc. Reverse Bridge PCI Originating Interface (Primary to Secondary) This section describes error support for transactions that cross the PEX 8111 when the originating side is the PCI Bus, and the destination side is PCI Express. The PEX 8111 supports TLP poisoning as a transmitter, to permit proper forwarding of Parity errors that occur on the PCI interface. Posted Write data received on the PCI interface with bad parity is forwarded to PCI Express as Poisoned TLPs. Table 10-5 provides the error forwarding requirements for Uncorrectable Data errors detected by the PEX 8111 when a transaction targets the PCI Express interface. Table 10-6 describes the PEX 8111's behavior on a PCI Delayed transaction that is forwarded to PCI Express as a Memory Read request or an I/O Read/Write request, and the PCI Express interface returns a completion with UR or CA status for the request. Table 10-5. Error Forwarding Requirements Received PCI Error Forwarded PCI Express Error Write with Parity error Write request with poisoned TLP Read Completion with Parity error in Data phase Read completion with poisoned TLP Configuration or I/O Completion with Parity error in Data phase Read/Write completion with Completer Abort Status Table 10-6. PEX 8111 Behavior on a PCI Delayed Transaction PCI Express Completion Status Master Abort Mode = 1 Master Abort Mode = 0 Unsupported Request (on Memory Read or I/O Read) Target Abort Normal completion, return FFFF_FFFFh Unsupported Request (on I/O Write) Target Abort Normal completion Completer Abort 98 PCI Immediate Response Target Abort PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 10.2.2.1 Reverse Bridge PCI Originating Interface (Primary to Secondary) Received PCI Errors Uncorrectable Data Error on Non-Posted Write When a Non-Posted write is addressed such that it crosses the PEX 8111, and the PEX 8111 detects an uncorrectable data error on the PCI interface, the following occur: * PCI Status register Detected Parity Error status bit is set. * If the PCI Command register Parity Error Response Enable bit is set, the transaction is discarded and is not forwarded to PCI Express. The PCI PERR# signal is asserted. * If the PCI Command register Parity Error Response Enable bit is not set, the data is forwarded to the PCI Express interface as a poisoned TLP. The Secondary Status register Secondary Master Data Parity Error bit is set when the Bridge Control register Secondary Parity Error Response Enable bit is set. The PCI PERR# signal is not asserted. Uncorrectable Data Error on Posted Write When the PEX 8111 detects an Uncorrectable Data error on the PCI interface for a Posted Write transaction that crosses the PEX 8111, the following occur: * PCI PERR# signal is asserted when the PCI Command register Parity Error Response Enable bit is set * PCI Status register Detected Parity Error status bit is set * Posted Write transaction is forwarded to PCI Express as a poisoned TLP * Secondary Status register Secondary Master Data Parity Error bit is set when the Bridge Control register Secondary Parity Error Response Enable bit is set Uncorrectable Data Error on PCI Delayed Read Completions When the PEX 8111 forwards a non-poisoned or poisoned Read Completion from PCI Express-to-PCI, and PERR# is asserted by the PCI master, the following occur: * Remainder of the completion is forwarded * PCI Central Resource Function services the PERR# assertion Uncorrectable Address Error When an uncorrectable address error is detected by the PEX 8111 and Parity error detection is enabled by way of the PCI Command register Parity Error Response Enable bit, the following occur: * Transaction is terminated with a Target Abort * PCI Status register Signaled Target Abort bit is set * PCI Status register Detected Parity Error status bit is set, independent of the setting of the PCI Command register Parity Error Response Enable bit * SERR# is asserted, when enabled by way of the PCI Command register SERR# Enable bit * PCI Status register Signaled System Error bit is set when SERR# is asserted PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 99 Error Handling 10.2.2.2 PLX Technology, Inc. Unsupported Request (UR) Completion Status The PEX 8111 provides two methods for handling a PCI Express completion received with Unsupported Request (UR) status in response to a request originated by the PCI interface. The response is controlled by the Bridge Control register Master Abort Mode bit. In either case, the Secondary Status register Secondary Received Master Abort bit is set. Master Abort Mode Bit Cleared This is the default PCI compatibility mode, and an Unsupported Request is not considered to be an error. When a Read transaction initiated on the PCI side of the bridge results in the return of a completion with UR status, the PEX 8111 returns FFFF_FFFFh to the originating master and terminates the Read transaction on the originating interface normally (by asserting TRDY#). When a Non-Posted Write transaction results in a completion with UR status, the PEX 8111 completes the Write transaction on the originating bus normally (by asserting TRDY#) and discards the Write data. Master Abort Mode Bit Set When the Bridge Control register Master Abort Mode bit is set, the PEX 8111 signals a Target Abort to the originating master of a downstream Read or Non-Posted Write transaction when the corresponding request on the PCI Express interface results in a completion with UR status. Moreover, the PCI Status register Signaled Target Abort bit is set. 10.2.2.3 Completer Abort (CA) Completion Status When the PEX 8111 receives a completion with Completer Abort status on the PCI Express interface in response to Forwarded Non-Posted PCI transactions, the Secondary Status register Secondary Received Target Abort bit is set. A completion with CA status results in a Delayed Transaction Target Abort on the PCI Bus. The PEX 8111 provides data to the requesting PCI agent, up to the point where data was successfully returned from the PCI Express interface, then signals Target Abort. The PCI Status register Signaled Target Abort status bit is set when signaling Target Abort to a PCI agent. 10.2.3 Reverse Bridge Timeout Errors 10.2.3.1 PCI Express Completion Timeout Errors The PCI Express Completion Timeout mechanism allows requesters to abort a non-posted request when a completion does not arrive within a reasonable length of time. Bridges, when acting as initiators on PCI Express on behalf of internally-generated requests and requests forwarded from a secondary interface, behave as endpoints for requests that they take ownership of. When a completion timeout is detected and the link is up, the PEX 8111 responds as when an unsupported request completion is received. When the link is down, the PCI Control register PCI-to-PCI Express Retry Count field determines the number of PCI Retries before a Master Abort is returned to the PCI Bus. 10.2.3.2 PCI Delayed Transaction Timeout Errors The PEX 8111 includes Delayed Transaction Timers for each queued Delayed transaction. When a Delayed transaction timeout is detected, the following occur: * Bridge Control register Discard Timer Status bit is set * Delayed request is removed from the Non-Posted Transaction queue * SERR# is asserted when the PCI Command register SERR# Enable bit is set 100 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 10.2.4 Reverse Bridge PCI Express Error Messages Reverse Bridge PCI Express Error Messages When the PEX 8111 detects an ERR_FATAL, ERR_NONFATAL, or ERR_COR error, or receives an ERR_FATAL, ERR_NONFATAL, or ERR_COR message, the PCI SERR# signal is asserted when the corresponding Reporting Enable bit in the Root Control register is set. When an ERR_FATAL or ERR_NONFATAL message is received, the Secondary Status register Secondary Received System Error bit is set, independent of the reporting Enable bits in the Root Control register. When an Unsupported Request is received by the PEX 8111, an Interrupt Request Status register interrupt status bit is set. This status bit is enabled to generate an INTx# or MSI interrupt. 10.2.5 Reverse Bridge "Other" Errors PCI devices assert SERR# when detecting errors that compromise system integrity. The PEX 8111 never monitors the SERR# ball in Reverse Bridge mode; instead, it allows the PCI Central Resource Function to service the SERR# interrupt. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 101 Error Handling 102 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 11 11.1 Exclusive (Locked) Access Forward Bridge Exclusive Accesses The exclusive access mechanism allows non-exclusive accesses to proceed in the face of exclusive accesses. This allows a master to hold a hardware lock across several accesses without interfering with non-exclusive Data transfers. Masters and targets not involved in the exclusive accesses are allowed to proceed with non-exclusive accesses while another master retains a bus lock. Exclusive access support in the PEX 8111 is enabled by the PCI Control register Locked Transaction Enable bit. When this bit is cleared, PCI Express Memory Read Locked requests are terminated with a completion with UR status. 11.1.1 Forward Bridge Lock Sequence across PEX 8111 Locked transaction sequences are generated by the Host CPU as one or more reads followed by a number of writes to the same locations. In Forward Bridge mode, the PEX 8111 supports only Locked transactions in the downstream direction (PCI Express-to-PCI). Upstream Locked transactions are not allowed. The initiation of a Locked transaction sequence through the PEX 8111 is as follows: 1. Locked transaction starts with a Memory Read Locked request. 2. Successive Reads for the Locked transaction also use Memory Read Locked requests. 3. Successful Memory Read Locked requests use the CplDLk Completion type, CplD. Unsuccessful Memory Read Locked requests use the CplLk Completion type. (For further details, refer to the PCI Express Base 1.0a, Table 2-3.) 4. When the Locked Completion for the first Locked Read request is returned, the PEX 8111 does not accept new requests from the PCI Bus. 5. Writes for the locked sequence use Memory Write requests. 6. PEX 8111 remains locked until it is unlocked by the PCI Express interface. Unlock is then propagated to the PCI Bus by terminating the locked sequence. 7. PCI Express Unlock message is used to indicate the end of a locked sequence. Upon receiving an Unlock message, the PEX 8111 unlocks itself. When the PEX 8111 is not locked, it ignores the Unlock message. When the Locked Read request is queued in the PCI Express-to-PCI Non-Posted Transaction queue, subsequent Non-Posted, Non-Locked requests from the PCI Express interface are completed with Unsupported Request status. Requests queued before the Locked Read request are allowed to complete. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 103 Exclusive (Locked) Access 11.1.2 PLX Technology, Inc. Forward Bridge PCI Master Rules for Supporting LOCK# The PEX 8111 must obey the following rules when performing locked sequences on the PCI Bus: * Master accesses only a single resource during a Lock operation. * First transaction of a lock operation must be a Memory Read transaction. * LOCK# must be asserted during the Clock cycle following the Address phase and remain asserted to maintain control. * LOCK# must be released when the initial transaction of the lock request is terminated with Retry (Lock was not established). * LOCK# must be released when an access is terminated by Target Abort or Master Abort. * LOCK# must be de-asserted between consecutive lock operations for a minimum of one Clock cycle while the bus remains in the Idle state. 11.1.3 Forward Bridge Acquiring Exclusive Access across PEX 8111 When a PCI Express Locked Memory Read request appears at the output of the non-posted request queue, the locked request is performed on the PCI Bus. The PEX 8111 monitors the PCI LOCK# ball state when attempting to establish lock. When LOCK# is asserted, the PEX 8111 does not request the PCI Bus to start the transaction. After LOCK# is de-asserted and the PCI Bus is idle, REQ# is asserted. While waiting for GNT#, the PEX 8111 continues to monitor LOCK#. When LOCK# is busy, the PEX 8111 de-asserts REQ# because another agent gained control of LOCK#. When the PEX 8111 is granted the bus and LOCK# is not asserted, ownership of LOCK# is obtained. The PEX 8111 is free to perform an exclusive operation when the current transaction completes. LOCK# is de-asserted during the first Address phase, and then is asserted one Clock cycle later. A Locked transaction is not established on the bus until the first Data phase of the first transaction completes (IRDY# and TRDY# asserted). When the target terminates the first transaction with Retry, the PEX 8111 terminates the transaction and releases LOCK#. After the first Data phase completes, the PEX 8111 holds LOCK# asserted until the Lock operation completes or a Master Abort or Target Abort causes an early termination. 11.1.4 Forward Bridge Non-Posted Transactions and Lock The PEX 8111 must consider itself locked when a Locked Memory Read Request is detected on the output of the non-posted request queue, although no data is transferred. This condition is referred to as a target-lock. While in target-lock, the PEX 8111 does not process new requests on PCI Express. The PEX 8111 locks the PCI Bus when lock sequence on the PCI Bus completes. A target-lock becomes a full-lock when the locked request is completed on the PCI Express. At this point, the PCI Express master established the lock. 11.1.5 Forward Bridge Continuing Exclusive Access When the PEX 8111 performs another transaction to a locked target, LOCK# is de-asserted during the Address phase. The locked target accepts and responds to the request. LOCK# is asserted one Clock cycle after the Address phase to keep the target in the locked state and allow the PEX 8111 to retain ownership of LOCK# beyond the end of the current transaction. 11.1.6 Forward Bridge Completing Exclusive Access When the PEX 8111 receives an Unlock message from the PCI Express, it de-asserts LOCK# on the PCI Bus. 104 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 11.1.7 Forward Bridge Invalid PCI Express Requests while Locked Forward Bridge Invalid PCI Express Requests while Locked When the PEX 8111 is locked, it only accepts PCI Express Memory Read Lock or Memory Write transactions that are being forwarded to the PCI Bus. Other transaction types are terminated with a completion with Unsupported Request status, including Non-Posted accesses to internal Configuration registers and shared memory. 11.1.8 Forward Bridge Locked Transaction Originating on PCI Bus Locked transactions originating on the secondary bus are not allowed to propagate to the primary bus. When a Locked transaction is performed on the PCI Bus and intended for the PEX 8111, the PEX 8111 ignores the transaction. 11.1.9 Forward Bridge PCI Bus Errors while Locked 11.1.9.1 PCI Master Abort during Posted Transaction When a PCI Master Abort occurs during a PCI Express-to-PCI Locked Write transaction, the PEX 8111 de-asserts LOCK#, thereby releasing the PCI bus from the locked state. Also, the PCI Express interface is released from the locked state, although no Unlock Message is received. Write data is discarded. Refer to Section 10.1.1.4, "PCI Master Abort on Posted Transaction," for additional details describing the action taken when a Master Abort is detected during a Posted transaction. 11.1.9.2 PCI Master Abort during Non-Posted Transaction When a PCI Master Abort occurs during a PCI Express-to-PCI Locked Read transaction, the PEX 8111 de-asserts LOCK#, thereby releasing the PCI Bus from the locked state. Also, the PCI Express interface is released from the locked state, although no Unlock Message is received. A CplLk with Unsupported Request status is returned to the PCI Express interface. Refer to Section 10.1.1.5, "PCI Master Abort on Non-Posted Transaction," for additional details describing the action taken when a Master Abort is detected during a Non-Posted transaction. 11.1.9.3 PCI Target Abort during Posted Transaction When a PCI Target Abort occurs during a PCI Express-to-PCI Locked Write transaction, the PEX 8111 de-asserts LOCK#, thereby releasing the PCI bus from the locked state. Also, the PCI Express interface is released from the locked state, although no Unlock message is received. Write data is discarded. Refer to Section 10.1.1.6, "PCI Target Abort on Posted Transaction," for additional details describing the action taken when a Target Abort is detected during a Posted transaction. 11.1.9.4 PCI Target Abort during Non-Posted Transaction When a PCI Target Abort occurs during a PCI Express-to-PCI Locked Read transaction, the PEX 8111 de-asserts LOCK#, thereby releasing the PCI Bus from the locked state. Also, the PCI Express interface is released from the locked state, although no Unlock Message is received. A CplLk with Completer Abort status is returned to the PCI Express interface. Refer to Section 10.1.1.7, "PCI Target Abort on Non-Posted Transaction," for additional details describing the action taken when a Target Abort is detected during a Non-Posted transaction. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 105 Exclusive (Locked) Access 11.2 PLX Technology, Inc. Reverse Bridge Exclusive Accesses A reverse bridge is allowed to pass Locked transactions from the primary interface (PCI Bus) to the secondary interface (PCI Express interface). When a locked request (LOCK# asserted) is initiated on the PCI Bus, then a Memory Read Locked Request is issued to the PCI Express interface. All subsequent Locked Read transactions targeting the PEX 8111 use the Memory Read Locked Request on the PCI Express interface. All subsequent Locked Write transactions use the Memory Write Request on the PCI Express interface. The PEX 8111 must transmit the Unlock message when PCI Lock sequence is complete. Exclusive access support in the PEX 8111 is enabled by the PCI Control register Locked Transaction Enable bit. When this bit is cleared, the PCI LOCK# ball is ignored, and Locked transactions are treated as Unlocked transactions. 11.2.1 Reverse Bridge PCI Target Rules for Supporting LOCK# * The PEX 8111, acting as a target of an access, locks itself when LOCK# is de-asserted during the Address phase and is asserted during the following Clock cycle. * Lock is established when LOCK# is de-asserted during the Address phase, asserted during the following Clock cycle, and data is transferred during the current transaction. * After lock is established, the PEX 8111 remains locked until both FRAME# and LOCK# are sampled de-asserted, regardless of how the transaction is terminated. * The PEX 8111 is not allowed to accept new requests (from PCI or PCI Express) while it remains in a locked condition, except from the owner of LOCK#. 11.2.2 Reverse Bridge Acquiring Exclusive Access across PEX 8111 A PCI master attempts to forward a Locked Memory Read transaction to the PCI Express interface. The transaction is terminated by the PEX 8111 with a Retry, and the locked request is written to the PCI-to-PCI Express Non-Posted Transaction queue. When this locked request reaches the top of the queue, the locked request is performed on the PCI Express interface as a Memory Read Lock Request. When the PCI Express responds with a locked completion, the locked request is updated with completion status. When the PCI master Retries the locked memory read request, the PEX 8111 responds with TRDY#, thereby completing the lock sequence. When the PEX 8111 is locked, it only accepts PCI Locked transactions that are being forwarded to the PCI Express interface. Other bus transactions are terminated with a Retry, including accesses to internal Configuration registers and shared memory. All PCI Express requests are terminated with a completion with Unsupported Request status. 11.2.3 Reverse Bridge Completing Exclusive Access When the PEX 8111 detects LOCK# and FRAME# de-asserted, it transmits an Unlock message to the PCI Express interface. 11.2.4 Reverse Bridge PCI Express Locked Read Request When a Locked Read Request is performed on the PCI Express interface, the PEX 8111 responds with a completion with Unsupported Request status. 11.2.5 Reverse Bridge Limitations In a system with multiple PCI masters that perform exclusive transactions to the PCI Express interface, the PCI Control register Locked Transaction Enable bit must be set. 106 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 12 12.1 Power Management Forward Bridge Power Management PCI Express defines Link power management states, replacing the bus power management states that were defined by the PCI Power Mgmt. r1.1. Link states are not visible to PCI Power Mgmt. r1.1 legacycompatible software, and are derived from the power management D states or by Active State power management protocols. 12.1.1 Forward Bridge Link State Power Management 12.1.1.1 Link Power States Table 12-1 delineates the link power states supported by the PEX 8111 in Forward Bridge mode. Table 12-1. Supported Link Power States (Forward Bridge Mode) Link Power State Description L0 Active state. All PCI Express operations are enabled. L0s A low resume latency, energy-saving "standby" state. L1 Higher latency, lower power "standby" state. L1 support is required for PCI Power Mgmt. r1.1-compatible power management. L1 is optional for Active State Link power management. All platform-provided main power supplies and component reference clocks must remain active at all times in L1. The PEX 8111 internal PLLs are shut off in L1, enabling greater energy savings at a cost of increased exit latency. The L1 state is entered when all functions of a downstream component on a given PCI Express Link are programmed to a D-state other than D0, or when the downstream component requests L1 entry (Active State Link PM) and receives positive acknowledgement for the request. Exit from L1 is initiated by an upstream initiated transaction targeting the downstream component, or by the need of the downstream component to initiate a transaction heading upstream. Transition from L1 to L0 is typically a few microseconds. TLP and DLLP communication over a Link that remains in the L1 state is prohibited. The PEX 8111 only requests L1 entry for PCI Power Mgmt. r1.1-compatible power management. When PMEIN# is asserted, the PEX 8111 requests a transition from L1 to L0. L2/L3 Ready Staging point for removal of main power. L2/L3 Ready transition protocol support is required. The L2/L3 Ready state is related to PCI Power Mgmt. r1.1 D-state transitions. L2/L3 Ready is the state that a given Link enters into when the platform is preparing to enter its system sleep state. Following the completion of the L2/L3 Ready state transition protocol for that Link, the Link is then ready for L2 or L3. Depending upon the implementation choices of the platform with respect to providing a Vaux supply, after main power is removed, the Link settles into L2 (that is, Vaux is provided), or into a zero power "off" state (refer to L3). The PEX 8111 does not support L2; therefore, it settles into the L3 state. The L2/L3 Ready state entry transition process must start as soon as possible following the PME_TO_Ack TLP acknowledgment of a PM_TURN_OFF message. The downstream component initiates L2/L3 Ready entry by injecting a PM_Enter_L23 DLLP onto its Transmit port. TLP and DLLP communication over a Link that remains in L2/L3 Ready is prohibited. The device exits from L2/L3 Ready to L0 when an upstream-initiated transaction targeting the downstream device occurs before main power is removed and the platform power manager decides not to enter the system sleep state. A Link's transition into the L2/L3 Ready state is one of the final stages involving PCI Express protocol, leading up to the platform entering into in a system sleep state wherein main power is shut off (such as, ACPI S3 or S4 sleep state). L2 Not supported. Auxiliary powered link deep energy-saving state. L3 Link-off state. Power-off state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 107 Power Management 12.1.1.2 PLX Technology, Inc. Link State Transitions Figure 12-1 highlights the L-state transitions which occur during the course of Link operations. The arc indicated in the illustration indicates the case wherein the platform does not provide Vaux. Link PM Transitions from an L-state to another L-state pass through the L0 state during the transition process with the exception of the L2/L3 Ready to L2 or L3 transitions. In this case, the Link transitions from L2/ L3 Ready directly to L2 or L3 when main power to the component is removed. (This follows along with a D-state transition from D3, for the corresponding component.) The following sequence, leading up to entering a system sleep state, illustrates the multi-step Link state transition process: 1. System software directs all functions of a downstream component to D3hot. 2. The downstream component then initiates the transition of the Link to L1 as required. 3. System software then causes the Root Complex to broadcast the PME_Turn_Off message in preparation for removing the main power source. 4. This message causes the subject Link to transition (return) to L0 to transmit it, and enable the downstream component to respond with PME_TO_Ack. 5. After the PME_TO_Ack is transmitted, the downstream component initiates the L2/L3 Ready transition protocol. In summary: * L0 -> L1 -> L0 -> L2/L3 Ready * L2/L3 Ready entry sequence is initiated at the completion of the PME_Turn_Off/PME_TO_Ack protocol handshake Figure 12-1. L-State Transitions during Link Operations Link Down - Transient pseudo-state to get back to L0 - entered through Fundamental Reset, Hot Reset, or Transmission by the Upstream Component Link reinitialization through LTSSM Detect state Return to L0 through LTSSM L0s .FTS sub-state LDn L0s L0 Return to L0 through LTSSM Recovery state L2 L1 L2/L3 Ready - Pseudo-state to prepare component for loss of power and reference clock(s) L2/L3 Ready L3 This arc indicates the case where the platform does not provide or the device does not use Vaux. In this case, the L2/L3 Ready state transition protocol results in a state of readiness for loss of main power, and once main power is removed the Link settles into the L3 state. Note: In this case, the L2/L3 Ready state transition protocol results in a state of readiness for loss of main power, and after removal, the Link settles into the L3 state. 108 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Forward Bridge Power Management States It is also possible to remove power without first placing all devices into D3hot: 1. System software causes the Root Complex to broadcast the PME_Turn_Off message in preparation for removing the main power source. 2. The downstream component responds with PME_TO_Ack. 3. After the PME_TO_Ack is transmitted, the downstream component initiates the L2/L3 Ready transition protocol. In summary: * L0 -> L2/L3 Ready 12.1.2 Forward Bridge Power Management States The PEX 8111 provides the Configuration registers and support hardware required by the PCI Power Mgmt. r1.1. The PCI Capabilities Pointer register points to the Base address of the Power Management registers (offset 40h in the PEX 8111). The PEX 8111 also supports the PCI Express Active State Link Power Management protocol, as described in Section 12.1.1. 12.1.2.1 Power States Table 12-2 delineates the power states supported by the PEX 8111, selectable by way of the Power Management Control/Status register Power State field. When transitioning from D0 to another state, the PCI Express link transitions to link state L1. System software must allow a minimum recovery time following a D3hot-to-D0 transition of at least 10 ms, prior to accessing the function. For example, this recovery time is used by the D3hot-to-D0 transitioning component to bootstrap its component interfaces (such as, from serial ROM) prior to being accessible. Attempts to target the function during the recovery time (including configuration request packets) results in undefined behavior. Table 12-2. Supported Power States (Forward Bridge Mode) Power State Description D0_uninitialized Power-on default state. This state is entered when power is initially applied. The PCI Command register I/O Access Enable, Memory Space Enable, and Bus Master Enable bits are all cleared to 0. D0_active Fully operational. At least one of the following PCI Command register bits must be set: * I/O Access Enable * Memory Space Enable * Bus Master Enable D1 Light sleep. Only PCI Express Configuration transactions are accepted. Other types of transactions are terminated with an Unsupported Request. All PCI Express requests generated by the PEX 8111 are disabled except for PME messages. D2 Heavy sleep. Same restrictions as D1. D3hot Function context not maintained. Only PCI Express Configuration transactions are accepted. Other types of transactions are terminated with an Unsupported Request. All PCI Express requests generated by the PEX 8111 are disabled except for PME messages. From this state, the next power state is D3cold or D0_uninitialized. When transitioning from D3hot-to-D0, the entire PEX 8111 is reset. D3cold Device is powered-off. A power-on sequence transitions a function from the D3cold state to the D0_uninitialized state. At this point, software must perform a full initialization of the function to re-establish all functional context, completing the restoration of the function to its D0_active state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 109 Power Management 12.1.3 PLX Technology, Inc. Forward Bridge Power Management Signaling PCI devices assert PMEIN# on a PEX 8111 ball to signal a Power Management Event (PME). The PEX 8111 converts the PMEIN# signal, received on the PCI side of the bridge, to PCI Express PME messages. There are no internal events that cause a PME message to transmit upstream. Power Management messages are used to support Power Management Events signaled by devices downstream of the PEX 8111. System software must identify the source of a PCI Power Management Event that is reported by a PM_PME message. When the PME comes from an agent on a PCI Bus, then the PM_PME Message Requester ID reports the Bus Number from which the PME was collected, and the Device Number and Function Number reported must both be 0. When the PME message is transmitted to the host, the Power Management Control/Status register PME Status bit is set and a 100 ms timer is started. When the status bit is not cleared within 100 ms, another PME message is transmitted. When the upstream device is powering down the downstream devices, it first places all devices into the D3hot state. It then transmits a PCI Express PME_Turn_Off message. After the PEX 8111 receives this message, it does not transmit further PME messages upstream. The PEX 8111 then transmits a PME_TO_Ack message to the upstream device and places its link into the L2/L3 Ready state. It is now ready to be powered-down. When the upstream device returns the PEX 8111 power state to D0, PME messages are re-enabled. The PCI Express PME_Turn_Off message terminates at the PEX 8111, and is not communicated to the PCI devices. The PEX 8111 does not issue a PM_PME message on behalf of a downstream PCI device while its upstream Link remains in the L2/L3 non-communicating state. To avoid loss of PCI backplane PME# assertions in the conversion of the level-sensitive PME# signal to the edge-triggered PCI Express PM_PME message, the PEX 8111 polls the PCI PMEIN# ball every 256 ms. A PCI Express PM_PME message is generated when PMEIN# is asserted. 12.1.4 Set Slot Power When a PCI Express link first comes up, or the Root Complex Slot Capabilities register Slot Power Limit Value or Slot Power Limit Scale fields are changed, the Root Complex transmits a Set Slot Power message. When the PEX 8111 receives this message, it updates the Device Capabilities register Captured Slot Power Limit Value and Captured Slot Power Limit Scale fields. When the available power indicated by the Device Capabilities register Captured Slot Power Limit Value and Captured Slot Power Limit Scale fields is greater than or equal to the power requirement indicated in the Power register, the PWR_OK signal is asserted. 110 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 12.2 Reverse Bridge Power Management Reverse Bridge Power Management The PEX 8111 supports Active State Power Management (ASPM) in Reverse Bridge mode. The default is that L1 be enabled and L0s be disabled. 12.2.1 Reverse Bridge Active State Power Management (ASPM) 12.2.1.1 ASPM States Table 12-3 delineates the link power states supported by the PEX 8111 in Reverse Bridge mode. Table 12-3. Supported Link Power States (Reverse Bridge Mode) Link Power State Description L0 Active state. All PCI Express operations are enabled. L0s A low-resume latency, energy-saving "standby" state. When enabled by the serial EEPROM or external driver, the PEX 8111 transmitter transitions to L0s after a low resume latency, energy-saving "standby" state. L0s support is required for Active State Link power management. It is not applicable to PCI Power Mgmt. r1.1-compatible power management. All main power supplies, component reference clocks, and components' internal PLLs must be active at all times during L0s. TLP and DLLP communication over a link that remains in L0s is prohibited. The L0s state is exclusively used for active-state power management. The PCI Express physical layer provides mechanisms for quick transitions from this state to the L0 state. When common (distributed) reference clocks are used on both sides of a given Link, the transition time from L0s to L0 is typically fewer than 100 symbol times. L1 Higher-latency, lower-power "standby" state. L1 support is required for PCI Power Mgmt. r1.1-compatible power management. L1 is optional for Active State Link power management. All platform provided main power supplies and component reference clocks must remain active at all times in L1. A component's internal PLLs are shut off in L1, enabling greater energy savings at a cost of increased exit latency. The L1 state is entered when all functions of a downstream component on a given PCI Express Link are programmed to a D-state other than D0, or when the downstream component requests L1 entry (Active State Link PM) and receives positive acknowledgement for the request. Exit from L1 is initiated by an upstream initiated transaction targeting the downstream component, or by the downstream component's need to initiate a transaction heading upstream. Transition from L1 to L0 is typically a few microseconds. TLP and DLLP communication over a link that remains in the L1 state is prohibited. L2/L3 Ready Staging point for removal of main power. L2/L3 Ready transition protocol support is required. The L2/L3 Ready state is related to PCI Power Mgmt. r1.1 D-state transitions. L2/L3 Ready is the state that a given Link enters into when the platform is preparing to enter its system sleep state. Following the completion of the L2/L3 Ready state transition protocol for that Link, the Link is then ready for L2 or L3; the link is not actually in either of those states until main power is removed. If the platform implements a Vaux Supply voltage, after main power is removed, the link settles into the L2 state; otherwise, it settles into the L3 state. The PEX 8111 does not have Vaux capability; however, it supports L2 when the system Vaux supply is used as the main power to the PEX 8111. The L2/L3 Ready state entry transition process must start as soon as possible following PME_TO_Ack TLP acknowledgment of a PM_TURN_OFF message. The downstream component initiates L2/L3 Ready entry by injecting a PM_Enter_L23 DLLP onto its Transmit port. TLP and DLLP communication over a Link that remains in L2/L3 Ready is prohibited. The device exits from L2/L3 Ready to L0 when an upstream-initiated transaction targeting the downstream device occurs before main power is removed and the platform power manager decides not to enter the system sleep state. A Link's transition into the L2/L3 Ready state is one of the final stages involving PCI Express protocol leading up to the platform entering into in a system sleep state wherein main power is shut off (for example, ACPI S3 or S4 sleep state). L2 Auxiliary-powered link deep energy-saving state. L3 Link-off state. Power-off state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 111 Power Management 12.2.2 PLX Technology, Inc. Reverse Bridge Power Management States The PEX 8111 provides the Configuration registers and support hardware required by the PCI Power Mgmt. r1.1. The PCI Capabilities Pointer register points to the Base address of the Power Management registers (offset 40h in the PEX 8111). 12.2.2.1 Power States Table 12-4 delineates the power states supported by the PEX 8111, selectable by way of the Power Management Control/Status register Power State field. Table 12-4. Supported Power States (Reverse Bridge Mode) Power State Description D0_uninitialized Power-on default state. This state is entered when power is initially applied. The PCI Command register I/O Access Enable, Memory Space Enable, and Bus Master Enable bits are all cleared to 0. D0_active 112 Fully operational. At least one of the following PCI Command register bits must be set: * I/O Access Enable * Memory Space Enable * Bus Master Enable D1 Light sleep. Only PCI Configuration transactions are accepted. No Master cycles are allowed, and the INTx# interrupts are disabled. The PMEOUT# signal is asserted by the PEX 8111 and the PCI clock continues to run in this state. D2 Heavy sleep. Same as D1, except that the PCI host stops the PCI clock. D3hot Function context not maintained. Only PCI Configuration transactions are accepted. From this state, the next power state is D3cold or D0_uninitialized. When transitioning from D3hot-to-D0, the entire PEX 8111 is reset. D3cold Device is powered-off. A power-on sequence transitions a function from the D3cold state to the D0_uninitialized state. At this point, software must perform a full initialization of the function to re-establish all functional context, completing the restoration of the function to its D0_active state. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 12.2.3 Reverse Bridge Power Down Sequence Reverse Bridge Power Down Sequence During a link power-down, the following sequence occurs: 1. PCI host places downstream PCI Express device in D3 power state. 2. Downstream device initiates a transition to the L1 link state. 3. PCI host places PEX 8111 in the D3 power state. 4. PEX 8111 initiates a transition to L0 on the link. 5. PEX 8111 generates a PCI Express PME_Turn_Off message to the PCI Express downstream device. 6. Downstream device responds with a PME_TO_Ack message. 7. Downstream device transmits a DLLP to request transition to the L2/L3 Ready state (L2.Idle link state). 8. PEX 8111 acknowledges the request, completing the transition to the L2.Idle link state. 9. PMEOUT# signal is asserted to the PCI host. 10. PCI host can now remove power from the PEX 8111. 12.2.4 Reverse Bridge PMEOUT# Signal PME messages from the PCI Express interface are translated to the PCI backplane PMEOUT# signal on the PEX 8111. The Power Management Control/Status register PME Status bit is set when a PCI Express PME message is received, the WAKEIN# signal is asserted, a beacon is detected, or the link transitions to the L2/L3 Ready state. PMEOUT# is asserted when the PME Status bit is set and PME is enabled. 12.2.5 Reverse Bridge Set Slot Power When a PCI Express link first comes up, or the PEX 8111 Slot Capabilities register Slot Power Limit Value or Slot Power Limit Scale fields are changed, the PEX 8111 transmits a Set Slot Power message to the downstream PCI Express device. When the downstream device receives this message, it updates the Device Capabilities register Captured Slot Power Limit Value and Captured Slot Power Limit Scale fields. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 113 Power Management 114 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 13 13.1 PCI Express Messages Forward Bridge PCI Express Messages PCI Express defines a set of messages that are used as a method for in-band communication of events (such as interrupts), generally replacing the need for sideband signals. These messages are also used for general-purpose messaging. PCI Express-to-PCI bridge support requirements for these messages are described in the following sections. PCI Express messages are routed explicitly or implicitly depending on specific bit field encodings in the message request header. An explicitly routed message is routed based on a specific address or on an ID field contained within the message header. The destination of an implicitly routed message is inferred from the message Type field. 13.1.1 Forward Bridge INTx# Interrupt Signaling INTx# Interrupt Signaling messages are used for in-band communication of the state of the PCI line-based interrupts INTA#, INTB#, INTC#, and INTD# for downstream devices. (Refer to Section 5.1, "Forward Bridge PCI Interrupts," for details.) 13.1.2 Forward Bridge Power Management Messages Power Management Messages are used to support Power Management Events signaled by sources integrated into the PEX 8111 and for downstream devices. (Refer to Section 12.1, "Forward Bridge Power Management," for details.) 13.1.3 Forward Bridge Error Signaling Messages Error Signaling messages are transmitted by the PEX 8111 on its PCI Express primary interface, to signal errors for any of the following: * A particular transaction * The Link Interface * Errors internal to the PEX 8111 * PCI-related errors detected on the secondary interface The message types include ERR_COR, ERR_FATAL, and ERR_NONFATAL. The relevant Mask bits are located in the PCI Express Capability Structure. (Refer to Section 10.1, "Forward Bridge Error Handling," for details.) PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 115 PCI Express Messages 13.1.4 PLX Technology, Inc. Forward Bridge Locked Transactions Support The PCI Express Unlock Message is used to support Locked Transaction sequences in the downstream direction. (Refer to Section 11.1, "Forward Bridge Exclusive Accesses," for details.) 13.1.5 Forward Bridge Slot Power Limit Support The Set Slot Power Limit message is transmitted to endpoints, including bridges, by the Root Complex or a switch. The PEX 8111 supports and complies with these messages. These messages are particularly relevant to bridges implemented on add-in boards. (Refer to Section 12.1, "Forward Bridge Power Management," for details.) 13.1.6 Forward Bridge Hot Plug Signaling Messages The PEX 8111 does not support Hot Plug signaling, and ignores the associated messages. 116 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Reverse Bridge PCI Express Messages 13.2 Reverse Bridge PCI Express Messages 13.2.1 Reverse Bridge INTx# Interrupt Message Support The PEX 8111 controls the state of the corresponding PCI interrupt pins based on the Assert_INTx and Deassert_INTx messages received. 13.2.2 Reverse Bridge Power Management Message Support The PEX 8111 generates a PME_Turn_Off message when placed into power state D3. The PEX 8111 then waits for the PME_TO_Ack message from the downstream device before proceeding with the power-down sequence. 13.2.2.1 PME Handling Requirements The PEX 8111 translates PME messages from the PCI Express interface to the PCI backplane PME# signal. The PEX 8111 converts the edge-triggered PMEs on the PCI Express interface to the level-triggered PME# signal on the PCI Bus. The PEX 8111 signals PMEOUT# on the PCI Bus for the following: * PCI Express WAKEIN# signal is asserted while the link is in the L2 state * PCI Express beacon is received while the link is in the L2 state * PCI Express PM_PME message is received For compatibility with existing software, the PEX 8111 does not signal PMEOUT# unless the PME signaling is enabled by the Power Management Control/Status register PME Enable bit. The PEX 8111 sets the Power Management Control/Status register PME Status bit when PMEOUT# is signaled and de-asserts PMEOUT# when the PME Enable or PME Status bit is cleared. All PME messages received while the PME Enable bit is cleared are ignored and the PME Status bit is not set during this time. 13.2.3 Reverse Bridge Error Signaling Message Support The PEX 8111 converts all ERR_COR, ERR_FATAL, and ERR_NONFATAL messages to SERR# on the PCI interface. 13.2.4 Reverse Bridge Locked Transaction Support The PEX 8111 is allowed to pass Locked transactions from the primary interface to the secondary interface. The PEX 8111 uses the Memory Read Locked request to initiate a locked sequence when a locked request is transmitted on the PCI Bus. All subsequent Locked Read transactions targeting the PEX 8111 use the Memory Read Locked request on the PCI Express interface. All subsequent Locked Write transactions use the Memory Write request on the PCI Express interface. The PEX 8111 transmits the Unlock message when the PCI Lock sequence is complete. (Refer to Section 11.2, "Reverse Bridge Exclusive Accesses," for details.) 13.2.5 Reverse Bridge Slot Power Limit Support The Set Slot Power Limit message is transmitted to endpoints, including bridges, by the Root Complex or a Switch. The PEX 8111 supports and complies with these messages. These messages are particularly relevant to bridges implemented on add-in boards. (Refer to Section 12.2, "Reverse Bridge Power Management," for details.) PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 117 PCI Express Messages 118 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 14 14.1 PCI Arbiter Overview A PCI system using the PEX 8111 utilizes an external bus arbiter, or the PEX 8111 internal arbiter. This internal arbiter accepts bus requests from up to four external PCI devices. The PCI Express-to-PCI bridge controller logic also requests control of the PCI Bus. 14.2 Internal Arbiter Mode When the EXTARB signal is de-asserted, the PEX 8111 accepts and arbitrates PCI requests from up to four external devices. The PEX 8111 supports single and multi-level arbiter modes, selected by the PCI Control register PCI Multi-Level Arbiter bit. 14.2.1 Single-Level Mode The four external requests and the PCI Express-to-PCI Bridge Controller request are placed into a single-level arbiter. After a device is granted the bus, it becomes the lowest level requester. All devices have the same priority. For example, when all internal and external agents are requesting the bus, then the order of the agents granted the bus would be: * PEX 8111 PCI Initiator * External Requester 0 * External Requester 1 * External Requester 2 * External Requester 3 * Bridge and so forth. 14.2.2 Multi-Level Mode The four external requests are placed into a two-level Round Robin arbiter with the PCI Express-to-PCI Bridge Controller. Level 0 alternates between the PCI Express-to-PCI Bridge controller and level 1, guaranteeing that the PCI Express-to-PCI Bridge is granted up to 50% of the accesses. Level 1 consists of the four external PCI requesters. For example, when all internal and external agents are requesting the bus, then the order of the agents that are granted the bus would be: * PEX 8111 PCI Initiator * External Requester 0 * PEX 8111 PCI Initiator * External Requester 1 * PEX 8111 PCI Initiator * External Requester 2 * PEX 8111 PCI Initiator * External Requester 3 and so forth. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 119 PCI Arbiter 14.3 PLX Technology, Inc. External Arbiter Mode When the EXTARB signal is asserted, the PEX 8111 PCI request inputs to the internal arbiter are disabled. The PEX 8111 generates a PCI Request (REQ0#) to an external arbiter when it must use the PCI Bus. The PCI Grant input (GNT0#) to the PEX 8111 allows it to become the PCI Bus master. 14.4 Arbitration Parking The PCI Bus is not allowed to float for more than eight Clock cycles. When there are no requests for the bus, the arbiter selects a device to drive the bus to a known state, by driving its GNT# ball active. When the EXTARB signal is de-asserted (Internal Arbiter mode), the PEX 8111 selects a PCI master to be parked on the bus during idle periods. The PCI Control register PCI Arbiter Park Select field determines which master is parked on the bus. When parked (GNT# driven during idle bus), the PEX 8111 drives AD[31:0], CBE[3:0]#, and PAR to a known state. The PEX 8111 drives AD[31:0], CBE[3:0]#, and PAR with the previous output value. In Forward Bridge mode, the PEX 8111 parks on the PCI Bus during reset, independent of the EXTARB signal, and drives AD[31:0], CBE[3:0]#, and PAR low. 120 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 15 15.1 Forward Bridge Mode Configuration Registers Register Description This chapter describes the PEX 8111 Configuration registers specific to Forward Bridge mode. Registers specific to Reverse Bridge mode are discussed in Chapter 16. The PCI-Compatible Forward Bridge Mode Configuration registers are accessed by the PCI Express Root Complex, using the PCI Configuration Address space. All Configuration registers are accessed from the PCI Express interface or PCI Bus, using the 64-KB memory space defined by the PCI Base Address 0 register. Registers that are written by the Serial EEPROM Controller are also written using Memory Writes through the PCI Base Address 0 register. When the Configuration registers are accessed using Memory transactions to the PCI Base Address 0 register, the register map delineated in Table 15-1 is used. The Serial EEPROM Controller writes to Configuration registers. An upper Address bit is used to select one of two register spaces, as delineated in Table 15-2. Each register is 32 bits wide, and is accessed one byte, word, or DWORD at a time. These registers utilize Little Endian byte ordering, which is consistent with the PCI r3.0. The least significant byte in a DWORD is accessed at Address 0. The least significant bit in a DWORD is 0, and the most significant bit is 31. After the PEX 8111 is powered up or reset, the registers are set to their default values. Writes to unused registers are ignored, and reads from unused registers return a value of 0. Table 15-1. Forward Bridge Mode PCI Base Address 0 Register Map Address Offset Register Space 0000h - 0FFFh PCI-Compatible Configuration registers 1000h - 1FFFh Main Configuration registers 2000h - 2FFFh - 8000h - 9FFFh 8-KB internal shared memory Table 15-2. Selecting Register Space AD12 15.1.1 Register Space 0 PCI-Compatible Configuration registers 1 Main Configuration registers Indexed Addressing In addition to Memory-Mapped accesses, the PEX 8111 Main Configuration registers can be accessed using the Main Control Register Index and Main Control Register Data registers. This method allows all Main Configuration registers to be accessed using Configuration transactions, rather than Memory transactions. First, the Main Configuration register offset is written to the Main Control Register Index register (offset 84h). Then, the Main Configuration register is written or read by accessing the Main Control Register Data register (offset 88h). PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 121 Forward Bridge Mode Configuration Registers 15.2 PLX Technology, Inc. Configuration Access Types Table 15-3 delineates configuration access types referenced by the registers in this chapter. Table 15-3. Configuration Access Types Access Type 15.3 Description CFG Initiated by PCI Configuration transactions on the primary bus. MM Initiated by PCI Memory transactions on the primary or secondary bus, using the Address range defined by the PCI Base Address 0 register. EE Initiated by the Serial EEPROM Controller during initialization. Register Attributes Table 15-4 delineates the register attributes used to indicate access types provided by each register bit. Table 15-4. Register Attribute HwInit Description Hardware Initialized Register bits are initialized by firmware or hardware mechanisms such as ball strapping (on the BAR0ENB#, EXTARB, and FORWARD balls) or serial EEPROM. Bits are Read-Only after initialization and reset only with "Fundamental Reset." RO Read-Only Register Register bits are Read-Only and cannot be altered by software. Register bits are initialized by a PEX 8111 hardware initialization mechanism or PEX 8111 Serial EEPROM register initialization feature. RsvdP Reserved and Preserved Reserved for future RW implementations. Registers are Read-Only and must return 0 when read. Software must preserve value read for writes to bits. RsvdZ Reserved and Zero Reserved for future RW1C implementations. Registers are Read-Only and must return 0 when read. Software must use 0 for writes to bits. RW RW1C WO 122 Access Provided by Register Bits Read-Write Register Register bits are Read-Write and set or cleared by software to the needed state. Read-Only Status, Write 1 to Clear Status Register Register bits indicate status when read; a set bit indicating a status event is cleared by writing 1. Writing 0 to RW1C bits has no effect. Write-Only Used to indicate that a register is written by the Serial EEPROM Controller. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 15.4 Register Summary Register Summary Table 15-5. Forward Bridge Mode Register Summary Register Group PCI-Compatible Configuration Registers (Type 1) PCI Express Extended Capability Registers PCI Space PCI Express Configuration Memory-Mapped, BAR0 PCI Express Configuration Memory-Mapped, BAR0 Address Range 00h - 0FFh 100h - 1FFh Main Control Registers Memory-Mapped, BAR0 1000h - 10FFh PCI Express Configuration Registers Using Enhanced Configuration Access Memory-Mapped, BAR0 2000h - 2FFFh 8-KB Shared Memory instead of General Purpose Memory Memory-Mapped, BAR0 8000h - 9FFFh PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 123 Forward Bridge Mode Configuration Registers PLX Technology, Inc. 15.5 Register Maps 15.5.1 PCI-Compatible Configuration Registers (Type 1) Table 15-6. Forward Bridge Mode PCI-Compatible Configuration (Type 1) Register Map PCI Configuration Register Offset 31 24 23 16 15 0 00h PCI Device ID PCI Vendor ID 04h PCI Status PCI Command 08h 0Ch PCI Device Revision ID PCI Class Code PCI Built-In Self-Test (Not Supported) PCI Header Type PCI Bus Latency Timer 10h PCI Base Address 0 14h PCI Base Address 1 18h 1Ch Secondary Latency Timer Subordinate Bus Number Secondary Status PCI Cache Line Size Secondary Bus Number Primary Bus Number I/O Limit I/O Base 20h Memory Limit Memory Base 24h Prefetchable Memory Limit Prefetchable Memory Base 28h 2Ch 30h Prefetchable Memory Base Upper 32 Bits Prefetchable Memory Limit Upper 32 Bits I/O Limit Upper 16 Bits 34h 38h 3Ch 124 8 7 I/O Base Upper 16 Bits PCI Capabilities Pointer Reserved PCI Base Address for Expansion ROM (Not Supported) Bridge Control PCI Interrupt Pin PCI Interrupt Line PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 15.5.2 PCI-Compatible Extended Capability Registers for PCI Express Interface PCI-Compatible Extended Capability Registers for PCI Express Interface Table 15-7. Forward Bridge Mode PCI-Compatible Extended Capability for PCI Express Interface Register Map PCI Configuration Register Offset 40h 44h 31 24 23 16 15 Power Management Next Capability Pointer Power Management Capabilities Power Management Data 8 7 Power Management Bridge Support Device-Specific Control 4Ch Reserved Message Signaled Interrupts Next Capability Pointer Message Signaled Interrupts Control 54h Message Signaled Interrupts Address 58h Message Signaled Interrupts Upper Address 5Ch Reserved 60h PCI Express Capabilities PCI Express Device Status PCI Express Capability ID PCI Express Device Control Link Capabilities Link Status 74h 78h PCI Express Next Capability Pointer Device Capabilities 6Ch 70h Message Signaled Interrupts Capability ID Message Signaled Interrupts Data 64h 68h Power Management Capability ID Power Management Control/Status 48h 50h 0 Link Control Slot Capabilities Slot Status Slot Control 7Ch - 80h Reserved 84h Main Control Register Index 88h Main Control Register Data PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 125 Forward Bridge Mode Configuration Registers 15.5.3 PLX Technology, Inc. PCI Express Extended Capability Registers Table 15-8. Forward Bridge Mode Power Budgeting Capability and Device Serial Number Register Map PCI Express Configuration Register Offset 100h 31 20 19 Power Budgeting Next Capability Offset 104h 0 Power Budgeting PCI Express Extended Capability ID Power Budgeting Data Select Power Budgeting Data 10Ch 126 Power Budgeting Capability Version 8 7 Reserved 108h 110h 16 15 Power Budget Capability Reserved Serial Number Next Capability Offset Serial Number Capability Version Serial Number PCI Express Extended Capability ID 114h Serial Number Low (Lower DWORD) 118h Serial Number Hi (Upper DWORD) PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 15.5.4 Main Control Registers Main Control Registers Table 15-9. Forward Bridge Mode 32-Bit Main Control Register Map PCI Express Configuration Register Offset 31 0 1000h Device Initialization 1004h Serial EEPROM Control 1008h Serial EEPROM Clock Frequency 100Ch PCI Control 1010h PCI Express Interrupt Request Enable 1014h Reserved 1018h Interrupt Request Status 101Ch Power 1020h General-Purpose I/O Control 1024h General-Purpose I/O Status 1030h Mailbox 0 1034h Mailbox 1 1038h Mailbox 2 103Ch Mailbox 3 1040h Chip Silicon Revision 1044h Diagnostic Control (Factory Test Only) 1048h TLP Controller Configuration 0 104Ch TLP Controller Configuration 1 1050h TLP Controller Configuration 2 1054h TLP Controller Tag 1058h TLP Controller Time Limit 0 105Ch TLP Controller Time Limit 1 1060h CRS Timer 1064h Enhanced Configuration Address PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 127 Forward Bridge Mode Configuration Registers 15.6 PLX Technology, Inc. PCI-Compatible Configuration Registers (Type 1) Register 15-1. (Offset 00h; PCIVENDID) PCI Vendor ID Bit(s) 15:0 Description PCI Vendor ID Identifies the PEX 8111 manufacturer. The PEX 8111 returns the PLX PCI-SIG-assigned Vendor ID, 10B5h. CFG MM EE Default RO RW WO 10B5h CFG MM EE Default RO RW WO 8111h Register 15-2. (Offset 02h; PCIDEVID) PCI Device ID Bit(s) 15:0 128 Description PCI Device ID Identifies the particular device, as specified by the Vendor. The PEX 8111 returns the PLX-assigned Device ID, 8111h. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-3. (Offset 04h; PCICMD) PCI Command Bit(s) Description CFG MM EE Default 0 I/O Access Enable Enables the PEX 8111 to respond to I/O Space accesses on the primary interface (PCI Express). These accesses must be directed to a target on the PCI Bus, because the PEX 8111 does not have internal I/O-Mapped resources. 0 = PEX 8111 responds to all I/O Requests on its primary interface with an Unsupported Request completion RW RW WO 0 1 Memory Space Enable Enables the PEX 8111 to respond to Memory Space accesses on the primary interface (PCI Express). These accesses are directed to a target on the PCI Bus, or to internal Memory-Mapped registers. 0 = PEX 8111 responds to all Memory Requests on the primary interface with an Unsupported Request completion RW RW WO 0 2 Bus Master Enable Enables the PEX 8111 to issue Memory and I/O Read/Write requests on the primary interface (PCI Express). Requests other than Memory or I/O Requests are not controlled by this bit. 0 = PEX 8111 does not respond (issue a Target Abort) to Memory nor I/O transactions on the PCI Bus secondary interface. No Memory or I/O transactions are forwarded to the PCI Express primary interface. RW RW WO 0 3 Special Cycle Enable Does not apply to PCI Express; therefore, forced to 0. RO RO - 0 4 Memory Write and Invalidate 0 = Enables the PEX 8111 PCI Bus master logic to use the Memory Write command 1 = Enables the PEX 8111 PCI Bus master logic to use the Memory Write and Invalidate command RW RW WO 0 5 VGA Palette Snoop Does not apply to PCI Express; therefore, forced to 0. RO RO - 0 6 Parity Error Response Enable Controls the PEX 8111's response to Data Parity errors forwarded from the primary interface (such as, a poisoned TLP). 0 = PEX 8111 must ignore (but records status such as setting the PCI Status register Detected Parity Error bit) Data Parity errors detected and continue standard operation 1 = PEX 8111 must take its standard action when a Data Parity error is detected RW RW WO 0 7 Address Stepping Enable The PEX 8111 performs Address Stepping for PCI Configuration cycles; therefore this bit is Read/Write with an initial value of 1. RW RW WO 1 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 129 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-3. (Offset 04h; PCICMD) PCI Command (Cont.) Bit(s) 8 Description SERR# Enable Enables reporting of Fatal and Non-Fatal errors to the Root Complex. Note: Errors are reported when enabled through this bit or through the PCI Express Device Control register PCI Express-specific bits. CFG MM EE Default RW RW WO 0 9 Fast Back-to-Back Enable Does not apply to PCI Express; therefore, forced to 0. RO RO - 0 10 Interrupt Disable When set: * PEX 8111 is prevented from generating INTx# interrupt messages on behalf of functions integrated into the PEX 8111 * INTx# emulation interrupts previously asserted must be de-asserted There is no effect on INTx# messages generated on behalf of INTx# inputs associated with the PCI Bus secondary interface. RW RW WO 0 RsvdP RsvdP - 0h 15:11 130 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-4. (Offset 06h; PCISTAT) PCI Status Bit(s) CFG MM EE Default RsvdZ RsvdZ - 000b RO RO - 0 4 Capabilities List Indicates whether the PCI Capabilities Pointer at offset 34h is valid. Because all PCI Express devices are required to implement the PCI Express capability structure, this bit is hardwired to 1. RO RO - 1 5 66-MHz Capable Does not apply to PCI Express; therefore, forced to 0. RO RO - 0 6 Reserved RsvdZ RsvdZ - 0 7 Fast Back-to-Back Transactions Capable Does not apply to PCI Express; therefore, forced to 0. RO RO - 0 8 Master Data Parity Error Used to report data parity error detection by the PEX 8111. Set when the PCI Command register Parity Error Response Enable bit is set and either of the following two conditions occur: * Bridge receives a completion marked poisoned on primary interface * Bridge poisons a write request or read completion on primary interface Writing 1 clears this bit. RW1C RW1C - 0 RO RO - 00b 11 Signaled Target Abort Set when the PEX 8111 completes a request as a transaction target on its primary interface using Completer Abort completion status. Writing 1 clears this bit. RW1C RW1C - 0 12 Received Target Abort Set when the PEX 8111 receives a completion with Completer Abort completion status on its primary interface. Writing 1 clears this bit. RW1C RW1C - 0 13 Received Master Abort Set when the PEX 8111 receives a completion with Unsupported Request completion status on its primary interface. Writing 1 clears this bit. RW1C RW1C - 0 14 Signaled System Error Set when the PEX 8111 transmits an ERR_FATAL or ERR_NONFATAL message to the Root Complex, and the PCI Command register SERR# Enable bit is set. Writing 1 clears this bit. RW1C RW1C - 0 15 Detected Parity Error Set when the PEX 8111 receives a poisoned TLP on the primary interface, regardless of the PCI Command register Parity Error Response Enable bit state. Writing 1 clears this bit. RW1C RW1C - 0 2:0 3 Description Reserved Interrupt Status 1 = Indicates that an INTx# interrupt message is pending on behalf of functions integrated into the PEX 8111 Does not reflect the status of INTx# inputs associated with the secondary interface. 10:9 DEVSEL Timing Does not apply to PCI Express; therefore, forced to 0. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 131 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-5. (Offset 08h; PCIDEVREV) PCI Device Revision ID Bit(s) Description CFG MM EE Default 7:0 PCI Device Revision ID Identifies the PEX 8111 Silicon Revision. Bits [3:0] represent the minor revision number and bits [7:4] represent the major revision number. RO RO - 21h CFG MM EE Default Register 15-6. (Offset 09h; PCICLASS) PCI Class Code Bit(s) Description 7:0 Programming Interface RO RW WO 00h 15:8 Subclass Code RO RW WO 04h 23:16 Base Class Code RO RW WO 06h Register 15-7. (Offset 0Ch; PCICACHESIZE) PCI Cache Line Size Bit(s) Description CFG MM EE Default 7:0 PCI Cache Line Size Specifies the System Cache Line Size (in units of DWORDs). The value in this register is used by PCI master devices to determine whether to use Read, Memory Read Line, Memory Read Multiple, or Memory Write and Invalidate commands for accessing memory. The PEX 8111 supports Cache Line Sizes of 2, 4, 8, 16, or 32 DWORDs. Writes of values other than these result in a Cache Line Size of 0; however, the value written is returned when this register is read. RW RW WO 0h Register 15-8. (Offset 0Dh; PCILATENCY) PCI Bus Latency Timer Bit(s) Description CFG MM EE Default 7:0 PCI Bus Latency Timer Also referred to as Primary Latency Timer for Type 1 Configuration Space Header devices. The Primary/Master Latency Timer does not apply to PCI Express. RO RO - 0h Register 15-9. (Offset 0Eh; PCIHEADER) PCI Header Type Bit(s) 7:0 132 Description PCI Header Type Specifies the format of the second part of the pre-defined configuration header starting at offset 10h. For PCI bridges, this field is forced to 1h. CFG MM EE Default RO RO - 1h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-10. (Offset 0Fh; PCIBIST) PCI Built-In Self-Test Bit(s) 7:0 Description PCI Built-In Self-Test Not supported. Always returns a value of 0h. CFG MM EE Default RO RO - 0h Register 15-11. (Offset 10h; PCIBASE0) PCI Base Address 0 Bit(s) Description CFG MM EE Default 0 Space Type When low, this space is accessed as memory. When high, this space is accessed as I/O. RO RO - 0 Address Type Indicates the type of addressing for this space. 00b = Locate anywhere in 32-bit Address space 01b = Locate below 1 MB 10b = Locate anywhere in 64-bit Address space 11b = Reserved RO RW WO 10b Prefetch Enable 1 = Indicates that prefetching has no side effects on reads RO RW WO 1 RO RO - 0h RW RW WO 0h CFG MM EE Default RW RW WO 0h Note: Hardwired to 0. 2:1 3 15:4 Base Address This section of the Base address is ignored for a 64-KB space. Note: Hardwired to 0. 31:16 Base Address Specifies the upper 16 bits of the 32-bit starting Base address of the 64-KB Address space for the PEX 8111 Configuration registers and shared memory. Register 15-12. (Offset 14h; PCIBASE1) PCI Base Address 1 Bit(s) 31:0 Description Base Address 1 Determines the upper 32 bits of the address when PCI Base Address 0 is configured for 64-bit addressing. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 133 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-13. (Offset 18h; PRIMBUSNUM) Primary Bus Number Bit(s) 7:0 Description Primary Bus Number Used to record the Bus Number of the PCI Bus segment to which the primary interface of the PEX 8111 is connected. CFG MM EE Default RW RW WO 0h Register 15-14. (Offset 19h; SECBUSNUM) Secondary Bus Number Bit(s) Description CFG MM EE Default 7:0 Secondary Bus Number Used to record the Bus Number of the PCI Bus segment to which the PEX 8111 secondary interface is connected. RW RW WO 0h CFG MM EE Default RW RW WO 0h CFG MM EE Default RW RW WO 0h Register 15-15. (Offset 1Ah; SUBBUSNUM) Subordinate Bus Number Bit(s) 7:0 Description Subordinate Bus Number Used to record the Bus Number of the highest-numbered PCI Bus segment behind (or subordinate to) the PEX 8111. Register 15-16. (Offset 1Bh; SECLATTIMER) Secondary Latency Timer Bit(s) 7:0 134 Description Secondary Latency Timer Specifies (in PCI clock units) the Latency Timer value during secondary (PCI) Bus Master bursts. When the Latency Timer expires, the PEX 8111 must terminate its tenure on the bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-17. (Offset 1Ch; IOBASE) I/O Base Bit(s) Description CFG MM EE Default 3:0 I/O Base Address Capability Indicates the type of addressing for this space. 0000b = 16-bit I/O address 0001b = 32-bit I/O address All other values are reserved. RO RW WO 0000b 7:4 I/O Base Determines the starting address at which I/O transactions on the primary interface are forwarded to the secondary interface. The upper four bits of this register correspond to Address bits AD[15:12]. For address decoding purposes, the PEX 8111 assumes that the lower 12 Address bits, AD[11:0], of the I/O Base address are zero (0h). Therefore, the bottom of the defined I/O Address range is aligned to a 4-KB Address Boundary space, and the top is one less than a 4-KB Address Boundary space. RW RW WO 0h CFG MM EE Default 3:0 I/O Limit Address Capability Indicates the type of addressing for this space. 0000b = 16-bit I/O address 0001b = 32-bit I/O address All other values are reserved. The value returned in this field is derived from the I/O Base register I/O Base Address Capability field. RO RO - 0000b 7:4 I/O Limit Determines the I/O Space range forwarded from the primary interface to the secondary interface. The upper four bits of this register correspond to Address bits AD[15:12]. For address decoding purposes, the PEX 8111 assumes that the lower 12 Address bits, AD[11:0], of the I/O Limit address are FFFh. When there are no I/O addresses on the secondary side of the bridge, the I/O Limit field is programmed to a value smaller than the I/O Base register I/O Base field. In this case, the PEX 8111 does not forward I/O transactions from the primary bus to the secondary bus; however, the PEX 8111 does forward all I/O transactions from the secondary bus to the primary bus. RW RW WO 0h Register 15-18. (Offset 1Dh; IOLIMIT) I/O Limit Bit(s) Description PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 135 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-19. (Offset 1Eh; SECSTAT) Secondary Status Bit(s) 4:0 Description Reserved CFG MM EE Default RsvdZ RsvdZ - 0h RO RO - 0 RsvdZ RsvdZ - 0 5 Secondary 66-MHz Capable Indicates whether the PEX 8111 secondary interface is capable of operating at 66 MHz. 6 Reserved 7 Secondary Fast Back-to-Back Transactions Capable Indicates whether the PEX 8111 secondary interface is capable of decoding Fast Back-to-Back transactions when the transactions are from the same master but to different targets. (A bridge is required to support Fast Back-toBack transactions from the same master.) The PEX 8111 does not support Fast Back-to-Back decoding. RO RO - 0 8 Secondary Master Data Parity Error Reports data parity error detection by the PEX 8111 when it is the master of the transaction on the secondary interface. Set when the following three conditions are true: * Bridge is the bus master of the transaction on secondary interface * Bridge asserted PERR# (Read transaction) or detected PERR# asserted (Write transaction) * Bridge Control register Secondary Parity Error Response Enable bit is set Writing 1 clears this bit. RW1C RW1C - 0 RO RO - 01b RW1C RW1C - 0 10:9 Secondary DEVSEL Timing Encodes the secondary interface DEVSEL# timing. The encoding must indicate the slowest response time that the PEX 8111 uses to assert DEVSEL# on its secondary interface when responding as a target to a transaction other than a Configuration Read or Write. 01b = Indicates medium DEVSEL# timing Note: Hardwired to 01b. 11 136 Secondary Signaled Target Abort Reports Target Abort termination signaling by the PEX 8111 when it responds as the transaction target on its secondary interface. Writing 1 clears this bit. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-19. (Offset 1Eh; SECSTAT) Secondary Status (Cont.) Bit(s) Description CFG MM EE Default 12 Secondary Received Target Abort Reports Target Abort termination detection by the PEX 8111 when it is the transaction master on its secondary interface. Writing 1 clears this bit. RW1C RW1C - 0 13 Secondary Received Master Abort Reports Master Abort termination detection by the PEX 8111 when it is the transaction master on its secondary interface. Also set for a PCI Express-toPCI Configuration transaction with an extended address not equal to 0. Writing 1 clears this bit. RW1C RW1C - 0 14 Secondary Received System Error Reports SERR# assertion detection on the PEX 8111 secondary interface. Writing 1 clears this bit. RW1C RW1C - 0 15 Secondary Detected Parity Error Reports Address or Data Parity error detection by the PEX 8111 on its secondary interface. Set when any of the following three conditions are true: * Bridge detects an Address Parity error as a potential target * Bridge detects a Data Parity error when a Write transaction target * Bridge detects a Data Parity error when a Read transaction master Set irrespective of the Bridge Control register Secondary Parity Error Response Enable bit state. Writing 1 clears this bit. RW1C RW1C - 0 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 137 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-20. (Offset 20h; MEMBASE) Memory Base Bit(s) 3:0 15:4 Description Reserved Note: Hardwired to 0h. Memory Base Determines the starting address at which Memory transactions on the primary interface are forwarded to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Memory Base address are zero (0h). The bottom of the defined Memory Address range is aligned to a 1-MB Address Boundary space, and the top is one less than a 1-MB Address Boundary space. CFG MM EE Default RsvdP RsvdP - 0h RW RW WO - CFG MM EE Default RsvdP RsvdP - 0h RW RW WO - Register 15-21. (Offset 22h; MEMLIMIT) Memory Limit Bit(s) 3:0 15:4 138 Description Reserved Note: Hardwired to 0h. Memory Limit Determines the Memory Space range forwarded from the primary interface to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Memory Limit address are FFFFFh. When there are no Memory-Mapped I/O addresses on the secondary side of the bridge, the Memory Limit field must be programmed to a value smaller than the Memory Base register Memory Base field. When there is no Prefetchable memory, and no Memory-Mapped I/O on the secondary side of the bridge, the PEX 8111 does not forward Memory transactions from the primary bus to the secondary bus; however, it does forward all Memory transactions from the secondary bus to the primary bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-22. (Offset 24h; PREBASE) Prefetchable Memory Base Bit(s) Description CFG MM EE Default 3:0 Prefetchable Base Address Capability Indicates the type of addressing for this space. 0000b = 32-bit I/O address 0001b = 64-bit I/O address All other values are reserved. RO RW WO 0000b 15:4 Prefetchable Memory Base Determines the starting address at which Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Prefetchable Memory Base address are zero (0h). The bottom of the defined Prefetchable Memory Address range is aligned to a 1-MB Address Boundary space, and the top is one less than a 1-MB Address Boundary space. RW RW WO - CFG MM EE Default RO RO - 0000b RW RW WO - Register 15-23. (Offset 26h; PRELIMIT) Prefetchable Memory Limit Bit(s) 3:0 Description Prefetchable Limit Address Capability Indicates the type of addressing for this space. 0000b = 32-bit I/O address 0001b = 64-bit I/O address All other values are reserved. The value returned in this field is derived from the Prefetchable Memory Base register Prefetchable Base Address Capability field. 15:4 Prefetchable Memory Limit Determines the Prefetchable Memory space range forwarded from the primary interface to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Prefetchable Memory Limit address are FFFFFh. When there is no prefetchable memory on the secondary side of the bridge, the Prefetchable Memory Limit field must be programmed to a value smaller than the Prefetchable Memory Base register Prefetchable Memory Base field. When there is no Prefetchable memory, and no Memory-Mapped I/O on the secondary side of the bridge, the PEX 8111 does not forward Memory transactions from the primary bus to the secondary bus; however, it does forward all Memory transactions from the secondary bus to the primary bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 139 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-24. (Offset 28h; PREBASEUPPER) Prefetchable Memory Base Upper 32 Bits Bit(s) Description CFG MM EE Default 31:0 Prefetchable Memory Base Upper 32 Bits When the Prefetchable Memory Base register Prefetchable Base Address Capability field indicates 32-bit addressing, this register is Read-Only and returns 0h. When the Prefetchable Base Address Capability field indicates 64-bit addressing, this register determines the upper 32 bits of the starting address at which Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. RW RW WO 0h Register 15-25. (Offset 2Ch; PRELIMITUPPER) Prefetchable Memory Limit Upper 32 Bits Bit(s) Description CFG MM EE Default 31:0 Prefetchable Memory Limit Upper 32 Bits When the Prefetchable Memory Limit register Prefetchable Limit Address Capability field indicates 32-bit addressing, this register is Read-Only and returns 0h. When thePrefetchable Limit Address Capability field indicates 64-bit addressing, this register determines the upper 32 bits of the Prefetchable Memory range forwarded from the primary interface to the secondary interface. RW RW WO 0h CFG MM EE Default RW RW WO - CFG MM EE Default RW RW WO - Register 15-26. (Offset 30h; IOBASEUPPER) I/O Base Upper 16 Bits Bit(s) 15:0 Description I/O Base Upper 16 Bits When the I/O Base register I/O Base Address Capability field indicates 16-bit addressing, this register is Read-Only and returns 0h. When the I/O Base Address Capability field indicates 32-bit addressing, this register determines the upper 16 bits of the starting address at which I/O transactions on the primary interface are forwarded to the secondary interface. Register 15-27. (Offset 32h; IOLIMITUPPER) I/O Limit Upper 16 Bits Bit(s) 15:0 140 Description I/O Limit Upper 16 Bits When the I/O Limit register I/O Limit Address Capability field indicates 16-bit addressing, this register is Read-Only and returns 0h. When the I/O Limit Address Capability field indicates 32-bit addressing, this register determines the upper 16 bits of the I/O range forwarded from the primary interface to the secondary interface. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-28. (Offset 34h; PCICAPPTR) PCI Capabilities Pointer Bit(s) Description 7:0 PCI Capabilities Pointer Provides the offset location of the first New Capabilities register. 31:8 Reserved CFG MM EE Default RO RW WO 40h RsvdP RsvdP - 0h CFG MM EE Default RW RW WO 0h CFG MM EE Default RO RW WO 1h Register 15-29. (Offset 3Ch; PCIINTLINE) PCI Interrupt Line Bit(s) 7:0 Description PCI Interrupt Line Indicates to which system interrupt controller input the PEX 8111 Interrupt ball is connected. Device drivers and operating systems use this field. Register 15-30. (Offset 3Dh; PCIINTPIN) PCI Interrupt Pin Bit(s) 7:0 Description PCI Interrupt Pin Identifies the legacy interrupt message(s) used by the PEX 8111. Valid values are 1, 2, 3, and 4, which map to legacy interrupt messages for INTA#, INTB#, INTC#, and INTD#, respectively. 0h = Indicates that the PEX 8111 does not use legacy interrupt messages PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 141 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-31. (Offset 3Eh; BRIDGECTL) Bridge Control Bit(s) Description CFG MM EE Default 0 Secondary Parity Error Response Enable Controls the PEX 8111's response to Address and Data Parity errors on the PCI Bus secondary interface. 0 = PEX 8111 must ignore Parity errors detected and continue standard operation. A bridge must generate parity, regardless of whether Parity error reporting is disabled. Also, the PEX 8111 must always forward Posted Write data with poisoning, from PCI-to-PCI Express on a PCI Data Parity error, regardless of this bit's setting. 1 = PEX 8111 must take its standard action when a Parity error is detected. RW RW WO 0 1 Secondary SERR# Enable Controls forwarding of PCI Bus secondary interface SERR# assertions to the primary interface (PCI Express). The PEX 8111 transmits an ERR_FATAL message on the primary interface when all of the following are true: * SERR# is asserted on the secondary interface * This bit is set * PCI Command register SERR# Enable bit is set or PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bits are set RW RW WO 0 2 ISA Enable Modifies the PEX 8111's response to ISA I/O addresses that are enabled by the I/O Base and I/O Limit registers and located in the first 64 KB of the PCI I/O Address space. 1 = PEX 8111 blocks forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded when they address the last 768 bytes in each 1-KB block. RW RW WO 0 3 VGA Enable Modifies the PEX 8111's response to VGA-compatible addresses. When set, the bridge positively decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, blocks the forwarding of these addresses from the secondary to primary interface): * Memory accesses in the range 000A_0000h to 000B_FFFFh * I/O address in the first 64 KB of the I/O Address space [Address[31:16] for PCI Express are zero (0000h)] and where Address[9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA address aliases - Address[15:10] can be any value and is not used in decoding) When the VGA Enable bit is set, VGA address forwarding is independent of the ISA Enable bit value, and the I/O Address range and Memory Address ranges defined by the I/O Base and I/O Limit, Memory Base and Memory Limit, and Prefetchable Memory Base and Prefetchable Memory Limit registers. VGA address forwarding is qualified by the PCI Command register I/O Access Enable and Memory Space Enable bits. 0 = Does not forward VGA-compatible Memory and I/O addresses from the primary to secondary interface (addresses defined above), unless they are enabled for forwarding by the defined I/O and Memory Address ranges 1 = Forwards VGA-compatible Memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (when the I/O Access Enable and Memory Space Enable bits are set), independent of the I/O and Memory Address ranges and ISA Enable bit RW RW WO 0 142 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 15-31. (Offset 3Eh; BRIDGECTL) Bridge Control (Cont.) Bit(s) Description CFG MM EE Default 4 VGA 16-Bit Decode Enables the PEX 8111 to provide 16-bit decoding of the VGA I/O address, precluding the decoding of alias addresses every 1 KB. Useful only when bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and bridge forwarding. Enables system configuration software to select between 10- and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary to secondary, when the VGA Enable bit is set to 1. 0 = Execute 10-bit address decodes on VGA I/O accesses 1 = Execute 16-bit address decodes on VGA I/O accesses RW RW WO 0 RW RW WO 0 RW RW WO 0 RO RO - 0 Master Abort Mode Controls the PEX 8111's behavior when it receives a Master Abort termination on the PCI Bus or an Unsupported Request on PCI Express. 0 = Do not report Master Aborts * When PCI Express UR is received: - Return FFFF_FFFFh to PCI Bus for Reads - Complete Non-Posted Write normally on PCI Bus (assert TRDY#) and discard the Write data - Discard Posted PCI-to-PCI Express Write data * 5 When PCI transaction terminates with Master Abort: - Complete Non-Posted transaction with Unsupported Request - Discard Posted Write data from PCI Express-to-PCI 1 = Report Master Aborts * When PCI Express UR is received: - Complete Reads and Non-Posted Writes with PCI Target Abort - Discard Posted PCI-to-PCI Express Write data * When PCI transaction terminates with Master Abort: - Complete Non-Posted transaction with Unsupported Request - Discard Posted Write data from PCI Express-to-PCI - Transmit ERR_NONFATAL message for Posted Writes 6 Secondary Bus Reset 1 = Forces PCIRST# to be asserted on the secondary bus. Additionally, the PEX 8111 secondary bus interface, and buffers between the two interfaces (primary and secondary), must be initialized to their default state. The primary bus interface and Configuration Space registers must not be affected by setting this bit. Because PCIRST# is asserted while this bit is set, software must observe proper PCI Reset timing requirements. 7 Fast Back-to-Back Enable Not supported. Controls bridge ability to generate Fast Back-to-Back transactions to various secondary interface devices. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 143 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-31. (Offset 3Eh; BRIDGECTL) Bridge Control (Cont.) Bit(s) 8 9 Description Primary Discard Timer In Forward Bridge mode, this bit does not apply and is forced to 0. Secondary Discard Timer Selects the number of PCI clocks that the PEX 8111 waits for a master on the secondary interface to repeat a Delayed Transaction request. The counter starts after the completion (PCI Express Completion associated with the Delayed Transaction request) reaches the head of the PEX 8111 downstream queue (that is, all ordering requirements are satisfied and the PEX 8111 is ready to complete the Delayed Transaction with the originating master on the secondary bus). When the originating master does not repeat the transaction before the counter expires, the PEX 8111 deletes the Delayed Transaction from its queue and sets the Discard Timer Status bit. CFG MM EE Default RO RO - 0 RW RW WO 0 RW1C RW1C WO 0 RW RW WO 0 RsvdP RsvdP - 0h 0 = Secondary Discard Timer counts 215 PCI clock periods 1 = Secondary Discard Timer counts 210 PCI clock periods 10 Discard Timer Status Set to 1 when the Secondary Discard Timer expires and a Delayed Completion is discarded from a queue within the PEX 8111. Writing 1 clears this bit. 11 Discard Timer SERR# Enable When set to 1, enables the PEX 8111 to generate an ERR_NONFATAL Message on the primary interface when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 8111. 0 = Does not generate ERR_NONFATAL message on the primary interface as a result of the Secondary Discard Timer expiration 1 = Generates ERR_NONFATAL message on the primary interface when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 8111 15:12 144 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 15.7 PCI-Compatible Extended Capability Registers for PCI Express Interface PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-32. (Offset 40h; PWRMNGID) Power Management Capability ID Bit(s) 7:0 Description Power Management Capability ID Specifies the Power Management Capability ID. CFG MM EE Default RO RO - 01h Register 15-33. (Offset 41h; PWRMNGNEXT) Power Management Next Capability Pointer Bit(s) 7:0 Description PCI Power Management Next Capability Pointer Points to the first location of the next item in the New Capabilities Linked List, Message Signaled Interrupts. CFG MM EE Default RO RW WO 50h Register 15-34. (Offset 42h; PWRMNGCAP) Power Management Capabilities Bit(s) Description CFG MM EE Default 2:0 PME Version Default 010b indicates compliance with the PCI Power Mgmt. r1.1. RO RW WO 010b 3 PME Clock Does not apply to PCI Express; therefore, must always be a value of 0. RO RO - 0 4 Reserved RsvdP RsvdP - 0 5 Device-Specific Initialization Indicates that the PEX 8111 requires special initialization following a transition to the D0_uninitialized state before the generic class device driver uses it. RO RW WO 0 8:6 AUX Current Reports the 3.3Vaux auxiliary current requirements for the PCI function. When PCI backplane PMEOUT# generation from D3cold is not supported by the function, must return a value of 000b. RO RW WO 000b 9 D1 Support Indicates whether the PEX 8111 supports the D1 state. RO RW WO 1 10 D2 Support Indicates whether the PEX 8111 supports the D2 state. By default, D2 is not supported; however, with additional circuitry, the PEX 8111 can support D2. RO RW WO 0 PME Support Default 11001b indicates that the corresponding PEX 8111 port forwards PME messages in the D0, D3hot, and D3cold power states. XXXX1b = Assertable from D0 XXX1Xb = Assertable from D1 XX1XXb = Assertable from D2 X1XXXb = Assertable from D3hot 1XXXXb = Assertable from D3cold RO RW WO 11001b 15:11 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 145 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-35. (Offset 44h; PWRMNGCSR) Power Management Control/Status Bit(s) 1:0 Description Power State Used to determine or change the current power state. 00b = D0 01b = D1 10b = D2 11b = D3hot CFG MM EE Default RW RW WO 00b RsvdP RsvdP - 0h A transition from state D3 to state D0 causes a Hot Reset to occur. In states D1 and D2, when the corresponding D1 Support and D2 Support bits are set, PCI Memory and I/O accesses are disabled, as well as the PCI interrupt, and only Configuration cycles are allowed. In state D3hot, these functions are also disabled. 7:2 Reserved 8 PME Enable Enables a PME message to transmit upstream. RW RW WO 0 12:9 Data Select Not supported. Always returns a value of 0h. RO RO - 0h 14:13 Data Scale Not supported. Always returns a value of 00b. RO RO - 00b RW1C RW1C - 0 15 PME Status Indicates that a PME message was transmitted upstream. Writing 1 clears this bit. Register 15-36. (Offset 46h; PWRMNGBRIDGE) Power Management Bridge Support Bit(s) 5:0 Description Reserved CFG MM EE Default RsvdP RsvdP - 0h 6 B2/B3 Support Not supported in Forward Bridge mode; therefore, forced to 0. RO RO - 0 7 Bus Power/Clock Control Enable Not supported in Forward Bridge mode; therefore, forced to 0. RO RO - 0 CFG MM EE Default RO RO - 0h Register 15-37. (Offset 47h; PWRMNGDATA) Power Management Data Bit(s) 7:0 146 Description Power Management Data Not supported. Always returns a value of 0h. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-38. (Offset 48h; DEVSPECCTL) Device-Specific Control Bit(s) Description CFG MM EE Default 0 Blind Prefetch Enable 0 = Memory Read command on the PCI Bus that targets the PCI Express Memory space causes only 1 word to be read from the PCI Express interface. 1 = Memory Read command on the PCI Bus that targets the PCI Express Memory space causes at least one Cache Line to be read from the PCI Express interface. Additional Dwords can be read by setting the PCI Control register Programmed Prefetch Size field. RW RW WO 0 1 PCI Base Address 0 Enable 1 = Enables the PCI Base Address 0 space for Memory-Mapped access to the Configuration registers and shared memory. PCI Base Address 0 is also enabled when the BAR0ENB# ball is low. RW RW WO 0 2 L2 Enable Does not apply to Forward Bridge mode. RW RW WO 0 3 PMU Power Off 1 = Link transitioned to the L2/L3 Ready state, and is ready to power down RO RO - 0 7:4 PMU Link State Indicates the link state. 0001b = L0 0010b = L0s 0100b = L1 1000b = L2 All other values are reserved. RO RO - - 9:8 CRS Retry Control Does not apply to Forward Bridge mode. RW RW WO 00b 10 WAKE Out Enable 1 = WAKEOUT# signal is asserted when PMEIN# is asserted and the link remains in the L2 state RW RW WO 0 11 Beacon Generate Enable 1 = Beacon is generated when PMEIN# is asserted and the link remains in the L2 state RW RW WO 0 12 Beacon Detect Enable Does not apply to Forward Bridge mode. RW RW WO 0 13 PLL Locked High when internal PLL is locked. RO RO - - RsvdP RsvdP - 00b RO RO - - RsvdP RsvdP - 0h 15:14 Reserved 20:16 Link Training and Status State Machine Factory Test Only. 31:21 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 147 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-39. (Offset 50h; MSIID) Message Signaled Interrupts Capability ID Bit(s) 7:0 Description MSI Capability ID Specifies the Message Signaled Interrupts Capability ID. CFG MM EE Default RO RO - 5h Register 15-40. (Offset 51h; MSINEXT) Message Signaled Interrupts Next Capability Pointer Bit(s) Description CFG MM EE Default 7:0 MSI Next Capability Pointer Points to the first location of the next item in the New Capabilities Linked List, PCI Express Capability. RO RW WO 60h CFG MM EE Default 0 MSI Enable When set: * Enables the PEX 8111 to use MSI to request service * Virtual interrupt support for internal interrupt sources are disabled RW RW WO 0 3:1 Multiple Message Capable System software reads this field to determine the number of requested messages. The number of requested messages must be aligned to a power of two (when a function requires three messages, it requests four). Value Number of Messages Requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b Reserved RO RO - 000b 6:4 Multiple Message Enable System software writes to this field to indicate the number of allocated messages (equal to or less than the number of requested messages). The number of allocated messages is aligned to a power of two. Value Number of Messages Requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b Reserved RW RW WO 000b 7 MSI 64-Bit Address Capable 1 = PEX 8111 is capable of generating a 64-bit Message address RO RW WO 1 8 Per Vector Masking Capable Not supported. Forced to 0. RO RO - 0 RsvdP RsvdP - 0h Register 15-41. (Offset 52h; MSICTL) Message Signaled Interrupts Control Bit(s) 15:9 148 Description Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-42. (Offset 54h; MSIADDR) Message Signaled Interrupts Address Bit(s) Description 1:0 Reserved 31:2 MSI Address When the Message Signaled Interrupts Control register MSI Enable bit is set, the register contents specify the DWORD-aligned address for the MSI Memory Write transaction. Address bits [1:0] are driven to zero (00b) during the Address phase. CFG MM EE Default RsvdP RsvdP - 00b RW RW WO 0h Register 15-43. (Offset 58h; MSIUPPERADDR) Message Signaled Interrupts Upper Address Bit(s) Description CFG MM EE Default 31:0 MSI Upper Address Optionally implemented only when the PEX 8111 supports a 64-bit Message address when the Message Signaled Interrupts Control register MSI 64-Bit Address Capable bit is set. When the Message Signaled Interrupts Control register MSI Enable bit is set, the register contents specify the upper 32 bits of a 64-bit message. When the register contents are zero (0h), the PEX 8111 uses the 32-bit address specified by the Message Signaled Interrupts Address register. RW RW WO 0h Register 15-44. (Offset 5Ch; MSIDATA) Message Signaled Interrupts Data Bit(s) Description CFG MM EE Default 15:0 MSI Data When the Message Signaled Interrupts Control register MSI Enable bit is set, the Message data is driven onto the lower word of the AD Bus (AD[15:0]) of the Memory Write Transaction Data phase. The upper word (AD[31:16]) is always cleared to 0h. RW RW WO 0h 31:16 Reserved RsvdP RsvdP - 0h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 149 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-45. (Offset 60h; PCIEXID) PCI Express Capability ID Bit(s) 7:0 Description PCI Express Capability ID Specifies the PCI Express Capability ID. CFG MM EE Default RO RW - 10h Register 15-46. (Offset 61h; PCIEXNEXT) PCI Express Next Capability Pointer Bit(s) Description CFG MM EE Default 7:0 PCI Express Next Capability Pointer Points to the first location of the next item in the New Capabilities Linked List. RO RW WO 0h Register 15-47. (Offset 62h; PCIEXCAP) PCI Express Capabilities Bit(s) Description CFG MM EE Default 3:0 Capability Version Indicates the PCI Express capability structure version number. RO RW WO 1h 7:4 Device/Port Type Indicates the type of PCI Express logical device. 0000b = PCI Express Endpoint Device 0001b = Legacy PCI Express Endpoint Device 0100b = Root Port of PCI Express Root Complex 0101b = Upstream Port of PCI Express Switch 0110b = Downstream Port of PCI Express Switch 0111b = PCI Express-to-PCI/PCI-X Bridge 1000b = PCI/PCI-X-to-PCI Express Bridge All other values are reserved. RO RW WO 0111b Slot Implemented 1 = Indicates that the PCI Express Link associated with this port is connected to a slot RO RW WO 0 13:9 Interrupt Message Number When this function is allocated more than one MSI interrupt number, this field must contain the offset between the Base Message data and the MSI message generated when Slot Status register status bits of this capability structure are set. For the field to be correct, hardware must update it when the number of MSI messages assigned to the PEX 8111 changes. RO RO - 0h 15:14 Reserved RsvdP RsvdP - 00b 8 150 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-48. (Offset 64h; DEVCAP) Device Capabilities Bit(s) 2:0 Description Maximum Payload Size Supported Indicates the Maximum Payload Size that the PEX 8111 supports for TLPs. 000b = 128 bytes All other values are reserved. CFG MM EE Default RO RO - 000b RO RO - 00b RO RW WO 0 RO RW WO 000b Note: Because the PEX 8111 supports a Maximum Payload Size of only 128 bytes, this field is hardwired to 000b. 4:3 5 Phantom Functions Supported Not supported. Hardwired to 00b. Indicates support for the use of unclaimed Function Numbers to extend the number of outstanding transactions allowed, by logically combining unclaimed Function Numbers (called Phantom Functions) with the Tag identifier. Extended Tag Field Supported Indicates the maximum supported size of the Tag field. 0 = 5-bit Tag field is supported 1 = 8-bit Tag field is supported Note: 8-bit Tag field support must be enabled by the corresponding Control field in the PCI Express Device Control register. 8:6 Endpoint L0s Acceptable Latency Indicates the acceptable total latency that an Endpoint withstands due to the transition from the L0s state to the L0 state. It is essentially an indirect measure of the Endpoint internal buffering. Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port, to determine whether Active State Link PM L0s entry is used with no performance loss. 000b = Less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = More than 4 s PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 151 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-48. (Offset 64h; DEVCAP) Device Capabilities (Cont.) Bit(s) Description CFG MM EE Default 11:9 Endpoint L1 Acceptable Latency Indicates the acceptable total latency that an Endpoint withstands due to the transition from the L1 state to the L0 state. It is essentially an indirect measure of the Endpoint internal buffering. Power management software uses the report L1 Acceptable Latency number to compare against the L1 exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port, to determine whether Active State Link PM L1 entry is used with no performance loss. 000b = Less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = More than 64 s RO RW WO 000b 12 Attention Button Present Not supported. Forced to 0. RO RO - 0 13 Attention Indicator Present. Not supported. Forced to 0. RO RO - 0 14 Power Indicator Present Not supported. Forced to 0. RO RO - 0 RsvdP RsvdP - 000b 17:15 Reserved 25:18 Captured Slot Power Limit Value Specifies the upper limit on power supplied by slot in combination with the Slot Power Limit Scale value. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. Value is set by the Set Slot Power Limit message. RO RW WO 0h 27:26 Captured Slot Power Limit Scale Specifies the scale used for the Slot Power Limit Value. Value is set by the Set Slot Power Limit message. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x RO RW WO 00b 31:28 Reserved RsvdP RsvdP - 0h 152 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-49. (Offset 68h; DEVCTL) PCI Express Device Control Bit(s) Description CFG MM EE Default 0 Correctable Error Reporting Enable Controls Correctable error reporting. When a Correctable error is detected in Forward Bridge mode and this bit is set, an ERR_COR message is transmitted to the Root Complex. RW RW WO 0 1 Non-Fatal Error Reporting Enable Controls Non-Fatal error reporting. When a Non-Fatal error is detected in Forward Bridge mode and this bit is set, an ERR_NONFATAL message is transmitted to the Root Complex. RW RW WO 0 2 Fatal Error Reporting Enable Controls Fatal error reporting. When a Fatal error is detected in Forward Bridge mode and this bit is set, an ERR_FATAL message is transmitted to the Root Complex. RW RW WO 0 3 Unsupported Request Reporting Enable Controls Unsupported Request reporting. When an Unsupported Request response is received from the PCI Express in Forward Bridge mode and this bit is set, a ERR_NONFATAL message is transmitted to the Root Complex. RW RW WO 0 4 Enable Relaxed Ordering Not supported. Forced to 0. 1 = PEX 8111 is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require Strong Write ordering RO RO - 0 7:5 Maximum Payload Size Sets the maximum TLP Payload Size for the PEX 8111. As a receiver, the PEX 8111 must handle TLPs as large as the set value; as transmitter, the PEX 8111 must not generate TLPs exceeding the set value. Permissible values for transmitted TLPs are indicated in the Device Capabilities register Maximum Payload Size Supported field. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved RW RW WO 000b PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 153 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-49. (Offset 68h; DEVCTL) PCI Express Device Control (Cont.) Bit(s) CFG MM EE Default RW RW WO 0 RO RO - 0 RO RO - 0 RO RO - 0 14:12 Maximum Read Request Size The value specified in this register is the upper boundary of the PCI Control register Programmed Prefetch Size field if the Device-Specific Control register Blind Prefetch Enable bit is set. Sets the Maximum Read Request Size for the Device as a Requester. The PEX 8111 must not generate read requests with a size that exceeds the set value. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved RW RW WO 010b 15 Bridge Configuration Retry Enable 0 = PEX 8111 does not generate completions with Completion Retry Status on behalf of PCI Express-to-PCI Configuration transactions. 1 = PEX 8111 generates completions with Completion Retry Status on behalf of PCI Express-to-PCI Configuration transactions. Occurs after a delay determined by the CRS Timer register. RW RW WO 0 8 Description Extended Tag Field Enable 0 = PEX 8111 is restricted to a 5-bit Tag field 1 = Enables PEX 8111 to use an 8-bit Tag field as a requester Forced to 0 when the Device Capabilities register Extended Tag Field Supported bit is cleared. 9 Phantom Function Enable Not supported. Hardwired to 0. Auxiliary (AUX) Power PM Enable Not supported. Hardwired to 0. 1 = Enables a device to draw AUX power independent of PME AUX power 10 Devices that require AUX power on legacy operating systems must continue to indicate PME AUX power requirements. AUX power is allocated as requested in the Power Management Capabilities register AUX Current field, independent of the Power Management Control/Status register PME Enable bit. Enable No Snoop Not supported. Hardwired to 0. 1 = PEX 8111 is permitted to set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware-enforced cache coherency 11 154 Setting this bit to 1 does not cause a device to blindly set the No Snoop attribute on all transactions that it initiates. Although this bit is set to 1, a device only sets the No Snoop attribute on a transaction when it can guarantee that the transaction address is not stored in a system cache. The PEX 8111 never sets the No Snoop attribute; therefore, this bit is forced to 0. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-50. (Offset 6Ah; DEVSTAT) PCI Express Device Status Bit(s) Description CFG MM EE Default 0 Correctable Error Detected Indicates Correctable errors detected status. Errors are logged in this register, regardless of whether error reporting is enabled in the PCI Express Device Control register. RW1C RW1C - 0 1 Non-Fatal Error Detected Indicates Non-Fatal errors detected status. Errors are logged in this register, regardless of whether error reporting is enabled in the PCI Express Device Control register. RW1C RW1C - 0 2 Fatal Error Detected Indicates Fatal errors detected status. Errors are logged in this register, regardless of whether error reporting is enabled in the PCI Express Device Control register. RW1C RW1C - 0 3 Unsupported Request Detected Indicates that the PEX 8111 received an Unsupported Request. Errors are logged in this register, regardless of whether error reporting is enabled in the PCI Express Device Control register. RW1C RW1C - 0 4 AUX Power Detected Devices that require AUX power report this bit as set when the PEX 8111 detects AUX power. RO RO - 0 5 Transactions Pending Because the PEX 8111 does not internally generate Non-Posted transactions, this bit is forced to 0. RO RO - 0 RsvdZ RsvdZ - 0h 15:6 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 155 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-51. (Offset 6Ch; LINKCAP) Link Capabilities Bit(s) Description CFG MM EE Default 3:0 Maximum Link Speed Indicates the maximum Link speed of the given PCI Express Link. Set to 0001b for 2.5 Gbps. All other values are reserved. RO RO - 0001b 9:4 Maximum Link Width Indicates the maximum width of the given PCI Express Link. By default, the PEX 8111 has an x1 link; therefore, this field is hardwired to 00_0001b. All other values are not supported. RO RO - 00_0001b 11:10 Active State Link PM Support Indicates the level of active state power management supported on the given PCI Express Link. 01b = L0s Entry supported 11b = L0s and L1 supported 00b, 10b = Reserved RO RW WO 11b 14:12 L0s Exit Latency Indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this port requires to complete transition from L0s to L0. 000b = Less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = More than 4 s RO RW WO 100b 17:15 L1 Exit Latency Indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this port requires to complete transition from L1 to L0. 000b = Less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = More than 64 s RO RW WO 100b 23:18 Reserved RsvdP RsvdP - 0h 31:24 Port Number Indicates the PCI Express port number for the given PCI Express Link. RO RW WO 0h 156 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-52. (Offset 70h; LINKCTL) Link Control Bit(s) 1:0 Description Active State Link PM Control Controls the level of active state PM supported on the given PCI Express Link. 00b = Disabled 01b = L0s Entry supported 10b = Reserved 11b = L0s and L1 Entry supported CFG MM EE Default RW RW WO 00b RsvdP RsvdP - 0 Note: "L0s Entry Enabled" indicates the Transmitter entering L0s. 2 Reserved 3 Read Completion Boundary (RCB) Control 0 = Read Completion boundary is 64 bytes 1 = Read Completion boundary is 128 bytes RW RW WO 0 4 Link Disable Does not apply to Forward Bridge mode. RO RO - 0 5 Retrain Link Does not apply to Forward Bridge mode. RO RO - 0 6 Common Clock Configuration 0 = Indicates that the PEX 8111 and the component at the opposite end of the link are operating with asynchronous reference clock. Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies. 1 = Indicates that the PEX 8111 and the component at the opposite end of the link are operating with a distributed common reference clock. RW RW WO 0 7 Extended Sync 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. This mode provides external devices monitoring the link time to achieve bit and symbol lock before the link enters the L0 state and resumes communication. RW RW WO 0 RsvdP RsvdP - 0h 15:8 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 157 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-53. (Offset 72h; LINKSTAT) Link Status Bit(s) Description CFG MM EE Default 3:0 Link Speed Indicates the negotiated Link speed of the given PCI Express Link. Set to 0001b for 2.5 Gbps. All other values are reserved. RO RO - 0001b 9:4 Negotiated Link Width Indicates the negotiated width of the given PCI Express Link. By default, the PEX 8111 has an x1 link; therefore, this field is hardwired to 00_0001b. All other values are not supported. RO RO - 00_0001b 10 Link Training Error Does not apply to Forward Bridge mode. RO RO - 0 11 Link Training Does not apply to Forward Bridge mode. RO RO - 0 12 Slot Clock Configuration Indicates that the PEX 8111 uses the same physical reference clock that the platform provides on the connector. When the PEX 8111 uses an independent clock irrespective of the presence of a reference on the connector, this bit must be cleared. HwInit RW WO 0 Reserved RsvdZ RsvdZ - 000b 15:13 158 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-54. (Offset 74h; SLOTCAP) Slot Capabilities Bit(s) Description CFG MM EE Default 0 Attention Button Present Not supported. Forced to 0. RO RO - 0 1 Power Controller Present Not supported. Forced to 0. RO RO - 0 2 MRL Sensor Present Not supported. Forced to 0. RO RO - 0 3 Attention Indicator Present Not supported. Forced to 0. RO RO - 0 4 Power Indicator Present Not supported. Forced to 0. RO RO - 0 5 Hot Plug Surprise Not supported. Forced to 0. RO RO - 0 6 Hot Plug Capable Not supported. The PEX 8111 does not support Hot Plug operations; therefore, this bit is forced to 0. RO RO - 0 14:7 Slot Power Limit Value Does not apply to Forward Bridge mode. RO RW WO 25d 16:15 Slot Power Limit Scale Does not apply to Forward Bridge mode. RO RW WO 00b 18:17 Reserved RsvdP RsvdP - 00b 31:19 Physical Slot Number Not supported. Forced to 0h. RO RO - 0h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 159 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-55. (Offset 78h; SLOTCTL) Slot Control Bit(s) Description CFG MM EE Default 0 Attention Button Pressed Enable Not supported. Forced to 0. RW RW WO 0 1 Power Fault Detected Enable Not supported. Forced to 0. RW RW WO 0 2 MRL Sensor Changed Enable Not supported. Forced to 0. RW RW WO 0 3 Presence Detect Changed Enable Not supported. Forced to 0. RW RW WO 0 4 Command Completed Interrupt Enable Not supported. Forced to 0. RW RW WO 0 5 Hot Plug Interrupt Enable Not supported. Forced to 0. RW RW WO 0 7:6 Attention Indicator Control Not supported. Forced to 0. RW RW WO 00b 9:8 Power Indicator Control Not supported. Forced to 00b. RW RW WO 00b 10 Power Controller Control Not supported. Forced to 0. RW RW WO 0 RsvdP RsvdP - 0h 15:11 Reserved Register 15-56. (Offset 7Ah; SLOTSTAT) Slot Status Bit(s) CFG MM EE Default 0 Attention Button Pressed Not supported. Forced to 0. RO RO - 0 1 Power Fault Detected Not supported. Forced to 0. RO RO - 0 2 MRL Sensor Changed Not supported. Forced to 0. RO RO - 0 3 Presence Detect Changed Not supported. Forced to 0. RO RO - 0 4 Command Completed Not supported. Forced to 0. RO RO - 0 5 MRL Sensor State Not supported. Forced to 0. RO RO - 0 6 Presence Detect State Not supported. Forced to 1. RO RO - 1 RsvdP RsvdP - 0h 15:7 160 Description Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 15-57. (Offset 84h; MAININDEX) Main Control Register Index Bit(s) Description 11:0 Main Control Register Index Selects a Main Control register that is accessed by way of the Main Control Register Data register. 31:12 Reserved CFG MM EE Default RW RW WO 0h RsvdP RsvdP - 0h CFG MM EE Default RW RW WO 0h Register 15-58. (Offset 88h; MAINDATA) Main Control Register Data Bit(s) 31:0 Description Main Control Register Data Writes to and reads from this register are mapped to a Main Control register selected by the Main Control Register Index register. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 161 Forward Bridge Mode Configuration Registers PLX Technology, Inc. 15.8 PCI Express Extended Capability Registers 15.8.1 PCI Express Power Budgeting Registers Register 15-59. (Offset 100h; PWRCAPHDR) Power Budgeting Capability Header Bit(s) Description CFG MM EE Default 15:0 PCI Express Extended Capability ID PCI-SIG-defined ID Number that indicates the nature and format of the extended capability. RO RW WO 4h 19:16 Capability Version PCI-SIG-defined Version Number that indicates the version of the capability structure present. RO RW WO 1h 31:20 Next Capability Offset Contains the offset to the next PCI Express capability structure, or 000h when no other items exist in the New Capabilities Linked List. Set to 110h when Serial Number Capability must be enabled. RO RW WO 000h CFG MM EE Default RW RW WO 0h RsvdP RsvdP - 0h Register 15-60. (Offset 104h; PWRDATASEL) Power Budgeting Data Select Bit(s) Description 7:0 Data Select Register Indexes the Power Budgeting Data reported through the Power Budgeting Data register. Selects the DWORD of Power Budgeting Data that is to appear in the Power Budgeting Data register. The PEX 8111 supports values from 0 to 31 for this field. For values greater than 31, a value of 0h is returned when the Power Budgeting Data register is read. 31:8 Reserved 162 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI Express Power Budgeting Registers Register 15-61 returns the DWORD of Power Budgeting Data selected by the Power Budgeting Data Select register. When the Power Budgeting Data Select register contains a value greater than or equal to the number of operating conditions for which the PEX 8111 provides power information, this register returns all zeros (0). The PEX 8111 supports 32 operating conditions. Register 15-61. (Offset 108h; PWRDATA) Power Budgeting Data Bit(s) Description CFG MM EE Default 7:0 Base Power Specifies (in Watts) the base power value in the given operating condition. This value must be multiplied by the Data Scale, to produce the actual power consumption value. RO RW WO 0h 9:8 Data Scale Specifies the scale to apply to the Base Power value. The PEX 8111 power consumption is determined by multiplying the Base Power field contents with the value corresponding to the encoding returned by this field. 00b = 1.0x 10b = 0.01x 01b = 0.1x 11b = 0.001x RO RW WO 00b 12:10 PM Sub-State Specifies the power management sub-state of the operating condition being described. 000b = Default Sub-State All other values = Device-Specific Sub-State RO RW WO 000b 14:13 PM State Specifies the power management state of the operating condition being described. A device returns 11b in this field and Aux or PME Aux in the PM Type field to specify the D3cold PM state. An encoding of 11b along with any other PM Type field value specifies the D3hot state. 00b = D0 10b = D2 01b = D1 11b = D3 RO RW WO 00b 17:15 PM Type Specifies the type of operating condition being described. 000b = PME Aux 011b = Sustained 001b = Auxiliary 111b = Maximum 010b = Idle All other values = Reserved RO RW WO 000b 20:18 Power Rail Specifies the power rail of the operating condition being described. 000b = Power (12V) 111b = Thermal 001b = Power (3.3V) All other values = Reserved 010b = Power (1.8V) RO RW WO 000b 31:21 Reserved RsvdP RsvdP - 0h CFG MM EE Default RO RW WO 0 RsvdP RsvdP - 0h Register 15-62. (Offset 10Ch; PWRBUDCAP) Power Budget Capability Bit(s) 0 31:1 Description System Allocated 1 = Indicates that the PEX 8111 power budget is included within the system power budget, and software is to ignore Reported Power Budgeting Data for power budgeting decisions Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 163 Forward Bridge Mode Configuration Registers 15.8.2 PLX Technology, Inc. PCI Express Serial Number Registers Register 15-63. (Offset 110h; SERCAPHDR) Serial Number Capability Header Bit(s) Description CFG MM EE Default 15:0 PCI Express Extended Capability ID PCI-SIG-defined ID Number that indicates the nature and format of the extended capability. Forced to 0 when Serial Number Capability is disabled. RO RO - 3h 19:16 Capability Version PCI-SIG-defined Version Number that indicates the version of the capability structure present. Forced to 0h when Serial Number Capability is disabled. RO RO - 1h 31:20 Next Capability Offset Contains the offset to the next PCI Express capability structure or 000h when no other items exist in the New Capabilities Linked List. RO RO - 000h Register 15-64. (Offset 114h; SERNUMLOW) Serial Number Low (Lower DWORD) Bit(s) 31:0 Description PCI Express Device Serial Number Contains the lower DWORD of the IEEE-defined 64-bit extended unique identifier. Includes a 24-bit Company ID value assigned by the IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. Forced to 0h when Serial Number Capability is disabled. CFG MM EE Default RO RW WO 0h CFG MM EE Default RO RW WO 0h Register 15-65. (Offset 118h; SERNUMHI) Serial Number Hi (Upper DWORD) Bit(s) 31:0 164 Description PCI Express Device Serial Number Contains the upper DWORD of the IEEE defined 64-bit extended unique identifier. Includes a 24-bit Company ID value assigned by the IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. Forced to 0h when Serial Number Capability is disabled. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 15.9 Main Control Registers Main Control Registers Register 15-66. (Offset 1000h; DEVINIT) Device Initialization Bit(s) 3:0 4 5 Description CFG MM PCLKO Clock Frequency Controls the PCLKO ball frequency. When cleared to 0000b, the clock is stopped and remains at a logic low (0V) DC value. Non-zero values represent divisors of the 100-MHz REFCLK. The default value is 0011b, representing a frequency of 66 MHz. 0000b = 0 0001b = 100 0010b = 50 0011b = 33.3/66 (When M66EN is high, PCLKO frequency is 66 MHz) 0100b = 25 0101b = 20 0110b = 16.7 0111b = 14.3 1000b = 12.5 1001b = 11.1 1010b = 10 1011b = 9.1 1100b = 8.3 1101b = 7.7 1110b = 7.1 1111b = 6.7 RW 0011b PCI Express Enable 0 = All configuration accesses to the PEX 8111, configured in Forward Bridge mode, result in a completion status of Configuration Request Retry Status. 1 = PEX 8111 responds normally to PCI Express Configuration accesses. Automatically set when a valid serial EEPROM is not detected. RW 0 RW 0 RsvdP 0h PCI Enable 0 = All PCI accesses to the PEX 8111 result in a Target Retry response 1 = PEX 8111 responds normally to PCI accesses Automatically set when a valid serial EEPROM is not detected. 31:6 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 165 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-67. (Offset 1004h; EECTL) Serial EEPROM Control Bit(s) Description CFG MM 7:0 Serial EEPROM Write Data Determines the byte written to the serial EEPROM when the Serial EEPROM Byte Write Start bit is set. Represents an opcode, address, or data being written to the serial EEPROM. RW 0h 15:8 Serial EEPROM Read Data Determines the byte read from the serial EEPROM when the Serial EEPROM Byte Read Start bit is set. RO - RW 0 RW 0 RW 0 RO 0 16 Serial EEPROM Byte Write Start 1 = Value in the Serial EEPROM Write Data field is written to the serial EEPROM Automatically cleared when the Write operation is complete. 17 Serial EEPROM Byte Read Start 1 = A byte is read from the serial EEPROM, and accessed using the Serial EEPROM Read Data field Automatically cleared when the Read operation is complete. 18 19 Serial EEPROM Chip Select Enable 1 = Serial EEPROM Chip Select is enabled Serial EEPROM Busy 1 = Serial EEPROM Controller is busy performing a Byte Read or Write operation An interrupt is generated when this bit goes false. 20 Serial EEPROM Valid 1 = Serial EEPROM with 5Ah in the first byte is detected RO - 21 Serial EEPROM Present Set when the Serial EEPROM Controller determines that a serial EEPROM is connected to the PEX 8111. RO - 22 Serial EEPROM Chip Select Active Set when the EECS# ball to the serial EEPROM is active. The Chip Select can be active across multiple byte operations. RO - 24:23 Serial EEPROM Address Width Reports the installed serial EEPROM's addressing width. When the addressing width cannot be determined, 00b is returned. A non-zero value is reported only when the validation signature (5Ah) is successfully read from the first serial EEPROM location. 00b = Undetermined 01b = 1 byte 10b = 2 bytes 11b = 3 bytes RO - 30:25 Reserved RsvdP 0h RW 0 31 166 Serial EEPROM Reload Writing 1 to this bit causes the Serial EEPROM Controller to perform an initialization sequence. Configuration registers and shared memory are loaded from the serial EEPROM. Reading this bit returns 0 while initialization is in progress, and 1 when initialization is complete. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-68. (Offset 1008h; EECLKFREQ) Serial EEPROM Clock Frequency Bit(s) Description 2:0 Serial EEPROM Clock Frequency Controls the EECLK ball frequency. 000b = 2 MHz 001b = 5 MHz 010b = 8.3 MHz 011b = 10 MHz 100b = 12.5 MHz 101b = 16.7 MHz 110b = 25 MHz 111b = Reserved 31:3 Reserved Access Default RW 000b RsvdP 0h Register 15-69. (Offset 100Ch; PCICTL) PCI Control Bit(s) Access Default PCI Multi-Level Arbiter 0 = All PCI requesters are placed into a single-level Round-Robin arbiter, each with equal access to the PCI Bus 1 = Two-level arbiter is selected RW 0 PCI Arbiter Park Select Determines which PCI master controller is granted the PCI Bus when there are no pending requests. 000b = Last grantee 001b = PCI Express interface 010b, 011b = Reserved 100b = External Requester 0 101b = External Requester 1 110b = External Requester 2 111b = External Requester 3 RW 000b 4 Bridge Mode Reflects the FORWARD ball status. When low, the PEX 8111 operates as a Reverse Bridge (PCI-to-PCI Express). When high, the PEX 8111 operates as a Forward Bridge (PCI Express-to-PCI). RO - 5 PCI External Arbiter Reflects the EXTARB ball state. When low, the PEX 8111 enables its internal arbiter. It then expects external requests on REQ[3:0]# and issues bus grants on GNT[3:0]#. When high, the PEX 8111 asserts REQ0# and expects GNT0# from an external arbiter. RO - 6 Locked Transaction Enable 0 = PCI Express Memory Read Lock requests are completed with UR status, and the PCI LOCK# ball is not driven RW 0 7 M66EN Reflects the M66EN ball state. When low, the PEX 8111 PCI Bus is operating at 33 MHz. When high, the PEX 8111 PCI Bus is operating at 66 MHz. RO 0 0 3:1 Description PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 167 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-69. (Offset 100Ch; PCICTL) PCI Control (Cont.) Bit(s) Access Default RW 80h RW 0h 24 Memory Read Line Enable 0 = PEX 8111 issues a Memory Read command for transactions that do not start on a Cache boundary. 1 = Memory Read Line command is issued when a transaction is not aligned to a Cache boundary in Prefetchable Address space, and the Burst Transfer Size is at least one Cache Line of data. The PCI burst is stopped at the Cache Line boundary when the Burst Transfer Size is less than one Cache Line of data or when a Memory Read Multiple command is started. RW 1 25 Memory Read Multiple Enable 0 = PEX 8111 issues a Memory Read command for transactions that start on a Cache boundary. 1 = Memory Read Multiple command is issued when a transaction is aligned to a Cache boundary in Prefetchable Address space, and the Burst Transfer Size is at least one Cache Line of data. The PCI burst continues when the Burst Transfer Size remains greater than or equal to one cache line of data. RW 1 RW 0 RW 000b RsvdP 00b 15:8 23:16 Description PCI-to-PCI Express Retry Count Does not apply to Forward Bridge mode. PCI Express-to-PCI Retry Count Determines the number of times to Retry a PCI Express-to-PCI transaction before aborting the transfer (in units of 24 Retries). 0h = Indicates that the transaction is Retried forever 255 = Selects a Retry count of 224 26 Early Byte Enables Expected 0 = PEX 8111 expects PCI Bytes Enables to be valid after IRDY# is asserted 1 = PEX 8111 expects the PCI Byte Enables to be valid in the clock tick following the Address phase For maximum compatibility with non-compliant PCI devices, clear this bit to 0. For maximum performance, set this bit to 1. 29:27 Programmed Prefetch Size Valid only for Memory Read Line and Memory Read Multiple transactions, or Memory Read transactions accessing Prefetchable Memory space with the Device-Specific Control register Blind Prefetch Enable bit set. Determines the number of bytes requested from the PCI Express interface as a result of a PCI-to-PCI Express read. If a Prefetch size is specified, the Cache Line boundary requirements of the Memory Read Line and Memory Read Multiple commands are disabled and the number of bytes requested will match the Prefetch Size. Enable feature only when the PCI initiator reads all requested data without disconnecting. Otherwise, performance is impacted. The Prefetch Size is limited by the PCI Express Device Control register Maximum Read Request Size field. 000b = Disabled 001b = 64 bytes 010b = 128 bytes 011b = 256 bytes 100b = 512 bytes 101b = 1,024 bytes 110b = 2,048 bytes 111b = 4,096 bytes (4 KB; refer to Note) Note: If the Programmed Prefetch Size is 4 KB, the TLP Controller Configuration 0 register Limit Completion Flow Control Credit bit must be set. 31:30 168 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-70. (Offset 1010h; PCIEIRQENB) PCI Express Interrupt Request Enable Bit(s) 0 Description Serial EEPROM Done Interrupt Enable 1 = Enables a PCI Express interrupt to generate when a Serial EEPROM Read or Write transaction completes Access Default RW 0 RW 0 RsvdP 0 Note: Refer to Section 5.1, "Forward Bridge PCI Interrupts," for further details. 1 GPIO Interrupt Enable 1 = Enables a PCI Express interrupt to generate when an interrupt is active from one of the GPIO balls 2 Reserved 3 PCI Express-to-PCI Retry Interrupt Enable 1 = Enables a PCI Express interrupt to generate when the PCI Express-to-PCI Retry count is reached RW 0 4 Mailbox 0 Interrupt Enable 1 = Enables a PCI Express interrupt to generate when Mailbox 0 is written RW 0 5 Mailbox 1 Interrupt Enable 1 = Enables a PCI Express interrupt to generate when Mailbox 1 is written RW 0 6 Mailbox 2 Interrupt Enable 1 = Enables a PCI Express interrupt to generate when Mailbox 2 is written RW 0 7 Mailbox 3 Interrupt Enable 1 = Enables a PCI Express interrupt to generate when Mailbox 3 is written RW 0 8 Unsupported Request Interrupt Enable 1 = Enables a PCI interrupt to be generated when an Unsupported Request Completion response is received from the PCI Express interface RW 0 RsvdP 0h RW 1 30:9 31 Reserved PCI Express Internal Interrupt Enable 1 = Enables a PCI Express interrupt to be generated as a result of an internal PEX 8111 interrupt source. The internal interrupt is serviced as a Message Signaled Interrupt (MSI) or virtual wire interrupt. Note: Refer to Section 5.1, "Forward Bridge PCI Interrupts," for further details. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 169 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-71. (Offset 1018h; IRQSTAT) Interrupt Request Status Bit(s) Access Default RW1C 0 RO 0 0 Serial EEPROM Done Interrupt Set when a Serial EEPROM Read or Write transaction completes. Writing 1 clears this status bit. 1 GPIO Interrupt Conveys the interrupt status for the four GPIO balls. Set independently of the GPIO Interrupt Enable bits. This bit is an OR of the four individual GPIO status bits. 1 = General-Purpose I/O Status register is read to determine the cause of the interrupt 2 Reserved RsvdP 0 3 PCI Express-to-PCI Retry Interrupt Set when the PCI Express-to-PCI Retry count is reached. Writing 1 clears this status bit. RW1C 0 4 Mailbox 0 Interrupt Set when Mailbox 0 is written. Writing 1 clears this bit. RW1C 0 5 Mailbox 1 Interrupt Set when Mailbox 1 is written. Writing 1 clears this bit. RW1C 0 6 Mailbox 2 Interrupt Set when Mailbox 2 is written. Writing 1 clears this bit. RW1C 0 7 Mailbox 3 Interrupt Set when Mailbox 3 is written. Writing 1 clears this bit. RW1C 0 8 Unsupported Request Interrupt Set when an Unsupported Request Completion is received from the PCI Express interface, provided that the PCI Express Interrupt Request Enable register Unsupported Request Interrupt Enable bit is set. RW1C 0 Reserved RsvdZ 0h 31:9 170 Description PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-72. (Offset 101Ch; POWER) Power Bit(s) Description Access Default 7:0 Power Compare 0 Specifies the power required for this device and downstream PCI devices. It is compared with the Device Capabilities register Captured Slot Power Limit Value field. When the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK signal is asserted. Used when the Device Capabilities register Captured Slot Power Limit Scale field is 00b (scale = 1.0x). RW 0h 15:8 Power Compare 1 Specifies the power required for this device and downstream PCI devices. It is compared with the Device Capabilities register Captured Slot Power Limit Value field. When the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK signal is asserted. Used when the Device Capabilities register Captured Slot Power Limit Scale field is 01b (scale = 0.1x). RW 0h 23:16 Power Compare 2 Specifies the power required for this device and downstream PCI devices. It is compared with the Device Capabilities register Captured Slot Power Limit Value field. When the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK signal is asserted. Used when the Device Capabilities register Captured Slot Power Limit Scale field is 10b (scale = 0.01x). RW 0h 31:24 Power Compare 3 Specifies the power required for this device and downstream PCI devices. It is compared with the Device Capabilities register Captured Slot Power Limit Value field. When the Captured Slot Power Limit Value is greater than or equal to this field, the PWR_OK signal is asserted. Used when the Device Capabilities register Captured Slot Power Limit Scale field is 11b (scale = 0.001x). RW 0h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 171 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-73. (Offset 1020h; GPIOCTL) General-Purpose I/O Control Bit(s) Access Default 0 GPIO0 Data When programmed as an output, values written to this bit appear on the GPIO0 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO0 ball. RW 0 1 GPIO1 Data When programmed as an output, values written to this bit appear on the GPIO1 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO1 ball. RW 0 2 GPIO2 Data When programmed as an output, values written to this bit appear on the GPIO2 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO2 ball. RW 0 3 GPIO3 Data When programmed as an output, values written to this bit appear on the GPIO3 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO3 ball. RW 0 4 GPIO0 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO0 ball is an input 1 = GPIO0 ball is an output RW 1 5 GPIO1 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO1 ball is an input 1 = GPIO1 ball is an output RW 0 6 GPIO2 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO2 ball is an input 1 = GPIO2 ball is an output RW 0 7 GPIO3 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO3 ball is an input 1 = GPIO3 ball is an output RW 0 8 GPIO0 Interrupt Enable 1 = Changes on the GPIO0 ball (when programmed as an input) are enabled to generate an interrupt RW 0 9 GPIO1 Interrupt Enable 1 = Changes on the GPIO1 ball (when programmed as an input) are enabled to generate an interrupt RW 0 10 GPIO2 Interrupt Enable 1 = Changes on the GPIO2 ball (when programmed as an input) are enabled to generate an interrupt RW 0 11 GPIO3 Interrupt Enable 1 = Changes on the GPIO3 ball (when programmed as an input) are enabled to generate an interrupt RW 0 172 Description PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-73. (Offset 1020h; GPIOCTL) General-Purpose I/O Control (Cont.) Bit(s) Description Access Default RW 01b RsvdP 0h GPIO Diagnostic Select Selects diagnostic signals that are output on the GPIO balls. 00b = Normal GPIO operation 01b = GPIO0 driven high when Link is up. GPIO[3:1] operate according to the configuration specified by bits [7:5] of this register 10b = GPIO[3:0] driven with lower four bits of the LTSSM state machine for 2 seconds, alternating with GPIO[1:0] driven with the upper two bits of the LTSSM state machine for 1s 11b = GPIO[3:0] driven with PMU Linkstate (L2, L1, L0s, and L0) 13:12 31:14 LTSSM Codes 00h - L3_L2 (Fundamental Reset) 01h - Detect 02h - Polling.Active 03h - Polling.Configuration 04h - Polling.Compliance 05h - Reserved 06h - Reserved 07h - Reserved 08h - Reserved 09h - Configuration.Linkwidth.Start 0Ah - Configuration.Linkwidth.Accept 0Bh - Configuration.Lanenum.Wait & Accept 0Ch - Configuration.Complete 0Dh - Configuration.Idle 0Eh - L0 0Fh - L0 (Transmit E.I.Ordered-set) 10h - L0 (Wait E.I.Ordered-set) 12h - L1.Idle 14h - L2.Idle 15h - Recovery.Rcvrlock (Extended Sync enabled) 16h - Recovery.Rcvrlock 17h - Recovery.RcvrCfg 18h - Recovery.Idle 19h - Disabled (Transmit TS1) 1Ah - Disabled (Transmit E.I.Ordered-set) 1Dh - Disabled (Wait Electrical Idle) 1Eh - Disabled (Disable) 1Fh - Loopback.Entry 20h - Loopback.Active 21h - Loopback.Exit 22h - Reserved 23h - Hot Reset (Reset Active) 24h - Loopback.Actice (Transmit E.I.Ordered-set) 25h - Loopback.Active (Wait Electrical Idle) Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 173 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-74. (Offset 1024h; GPIOSTAT) General-Purpose I/O Status Bit(s) Description Access Default 0 GPIO0 Interrupt Set when the GPIO0 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 1 GPIO1 Interrupt Set when the GPIO1 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 2 GPIO2 Interrupt Set when the GPIO2 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 3 GPIO3 Interrupt Set when the GPIO3 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 Reserved RsvdZ 0h 31:4 Register 15-75. (Offset 1030h; MAILBOX0) Mailbox 0 Bit(s) 31:0 Description Access Default RW FEEDFACEh Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. Register 15-76. (Offset 1034h; MAILBOX1) Mailbox 1 Bit(s) 31:0 Description Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. Access Default RW 0h Access Default RW 0h Access Default RW 0h Register 15-77. (Offset 1038h; MAILBOX2) Mailbox 2 Bit(s) 31:0 Description Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. Register 15-78. (Offset 103Ch; MAILBOX3) Mailbox 3 Bit(s) 31:0 174 Description Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-79. (Offset 1040h; CHIPREV) Chip Silicon Revision Bit(s) Description 15:0 Chip Revision Returns the PEX 8111 current Silicon Revision number. 31:16 Reserved Access Default RO Current Revision RsvdP 0h Note: CHIPREV is the Silicon Revision, encoded as a 4-digit BCD value. The CHIPREV value for the third release of the chip (Rev. BB) is 0201h. The least-significant digit is incremented for mask changes, and the most-significant digit is incremented for major revisions. Register 15-80. (Offset 1044h; DIAGCTL) Diagnostic Control (Factory Test Only) Bit(s) Description Access Default 0 Fast Times Factory Test Only. RW 0 1 Force PCI Interrupt 1 = Forces the PCI INTx# interrupt signal to assert. The PCI Interrupt Pin register determines which INTx# signal is asserted. Effective only when the PCI Command register Interrupt Disable bit is low. RW 0 2 Force PCI SERR 1 = Forces the PCI SERR# interrupt signal to assert when the Bridge Control register Secondary SERR# Enable bit is set RW 0 3 Force PCI Express Interrupt 1 = Forces an interrupt to the PCI Express Root Complex, using Message Signaled interrupts or virtual INTx# interrupts RW 0 RsvdP 0h 31:4 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 175 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-81. (Offset 1048h; TLPCFG0) TLP Controller Configuration 0 Bit(s) Access Default CFG_NUM_FTS Forced NUM_FTS signal. NUM_FTS represents the number of Fast Training sequence (0 to 255). Refer to the PCI Express r1.0a, Section 4.2.4.3, for detailed information. RW 20h 8 CFG_ACK_FMODE PCI Express interface ACK_DLLP transmitting interval mode. 0 = PCI Express interface uses own interval value 1 = PCI Express interface uses CFG_ACK_COUNT as interval value RW 0 9 CFG_TO_FMODE PCI Express interface Timeout detection mode for replay timer. 0 = PCI Express interface uses own timer value 1 = PCI Express interface uses CFG_TO_COUNT as timer value RW 0 10 CFG_PORT_DISABLE 1 = SerDes in the PCI Express interface is disabled. This allows the endpoint to disable the PCI Express connection when powered up or before the configuration is completed. RW 0 11 CFG_RCV_DETECT Set when the PCI Express interface establishes the PCI Express connection. RO 0 12 CFG_LPB_MODE Link Loop-Back mode. 1 = PEX 8111 changes its LTSSM state to the Loop-Back state, becomes the Loop-Back master, and starts transmitting packets of pseudo random numbers RW 0 13 CFG_PORT_MODE 0 = Link PCI Express interface is configured as an upstream port (Endpoint) 1 = Link PCI Express interface is configured as a downstream port (Root Complex) RW 0 14 Reserved RsvdP 0 15 CFG_ECRC_GEN_ENABLE 1 = Link is allowed generate ECRC RW 0 7:0 Description The PEX 8111 does not support ECRC; therefore, this bit is cleared to 0. 176 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-81. (Offset 1048h; TLPCFG0) TLP Controller Configuration 0 (Cont.) Bit(s) Access Default 16 TLP_CPLD_NOSUCCESS_MALFORM_ENABLE 0 = Received completion is retained 1 = Completion received when completion timeout expired is treated as a malformed TLP and discarded RW 1 17 Scrambler Disable 0 = Data scrambling is enabled. 1 = Data scrambling is disabled. Set only when testing and debugging. RW 0 RW 0 19 Decode Primary Bus Number 0 = PEX 8111 ignores the Primary Bus Number in a PCI Express Type 0 Configuration Request. 1 = PEX 8111 compares the Primary Bus Number in a PCI Express Type 0 Configuration Request with the Primary Bus Number register. When they match, the request is accepted. Otherwise, an Unsupported Request is returned. This comparison occurs only after the first Type 0 Configuration write occurs. RW 0 20 Ignore Function Number 0 = PEX 8111 only responds to Function Number 0 during a Type 0 Configuration transaction. Accesses to other function numbers result in an Unsupported Request (PCI Express) or Master Abort (PCI). 1 = PEX 8111 ignores the Function Number in a PCI or PCI Express Type 0 Configuration request, and responds to all eight functions. RW 0 21 Check RCB Boundary 0 = PEX 8111 ignores Read Completion Boundary (RCB) violations. 1 = PEX 8111 checks for RCB violations. When detected, the PEX 8111 treats it as a malformed TLP (packet is dropped and a Non-Fatal Error message is transmitted). RW 0 RW 0 RW 1 RsvdP 0h Access Default 18 Description Delay Link Training 0 = Link training is allowed to commence immediately after PERST# is de-asserted 1 = Link training is delayed for 12 ms after PERST# is de-asserted When GPIO3 is low at the trailing edge of reset, this bit is automatically set. Because this bit is used during link training, it must be set by driving GPIO3 low during PERST# assertion. 22 Limit Completion Flow Control Credit 0 = PEX 8111 advertises infinite flow control credits for completions. 1 = PEX 8111 advertises completion flow control credits, based on available buffer storage. Must be set when the PCI Control register Programmed Prefetch Size field is set to 4 KB. When GPIO2 is low at the trailing edge of PERST#, this bit is automatically set. Because this bit is used during link training, it must be set by driving GPIO2 low during PERST# assertion. 23 31:24 L2 Secondary Bus Reset Does not apply to Forward Bridge mode. Reserved Register 15-82. (Offset 104Ch; TLPCFG1) TLP Controller Configuration 1 Bit(s) Description 20:0 CFG_TO_COUNT PCI Express interface Replay Timer timeout value when CFG_TO_FMODE is set to 1. RW D4h 30:21 CFG_ACK_COUNT PCI Express interface ACK DLLP transmitting interval value when CFG_ACK_FMODE is set to 1. RW 0h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 177 Forward Bridge Mode Configuration Registers PLX Technology, Inc. Register 15-82. (Offset 104Ch; TLPCFG1) TLP Controller Configuration 1 31 Reserved RsvdP 0 Register 15-83. (Offset 1050h; TLPCFG2) TLP Controller Configuration 2 Bit(s) Description Access Default 15:0 CFG_COMPLETER_ID0 Bits [15:8] = Bus Number Bits [7:3] = Device Number Bits [2:0] = Function Number The Bus, Device, and Function Numbers of a Configuration transaction to the PEX 8111 are latched in this register. The latched values are then used when generating the completion. RW 0h 26:16 Update Credit FC Controls a counter that determines the gap between UpdateFC DLLPs (in units of 62.5 MHz clocks = 16 ns = 4 symbol times). When data or headers are read from the TLP Controller, the Credit Allocation Manager transmits a set of UpdateFC DLLPs; posted, non-posted, and completion when the TLP Controller Configuration 0 register Limit Completion Flow Control Credit bit is set. While transmitting the set of DLLPs, the Credit Allocation Manager uses the counter value to insert gaps between the DLLPs. The Bus, Device, and Function Numbers of a Configuration transaction to the PEX 8111 are latched in this register. The latched values are then used when generating the completion. RW 1h 31:27 Reserved RsvdP 0h Register 15-84. (Offset 1054h; TLPTAG) TLP Controller Tag Bit(s) Description Access Default 7:0 TAG BME1 Message Request Tag field. RW 0h 15:8 TAG ERM Error Manager Tag field. RW 0h 23:16 TAG PME Power Manager Tag field. RW 0h 31:24 Reserved RsvdP 0h 178 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 15-85. (Offset 1058h; TLPTIMELIMIT0) TLP Controller Time Limit 0 Bit(s) Description Access Default 23:0 BME_COMPLETION_TIMEOUT_LIMIT Bus master engine completion timeout (in PCI clock units). The default value produces a 10-ms timeout. RW 51615h (M66EN low) A2C2Ah (M66EN high) 27:24 L2L3_PWR_REMOVAL_TIME_LIMIT Determines length of time before power is removed after entering the L2 state. Value to be at least 100 ns. Contains PCI clock units. RW 4h (M66EN low) 8h (M66EN high) 31:28 Reserved RsvdP 0h Register 15-86. (Offset 105Ch; TLPTIMELIMIT1) TLP Controller Time Limit 1 Bit(s) Description Access Default 10:0 ASPM_LI_DLLP_INTERVAL_TIME_LIMIT Determines time interval between two consecutive PM_ACTIVE_STATE_REQUEST_L1 DLLP transmissions. The default is 10 s for both 14Dh and 29Ah. Allow at least 10 s spent in LTSSM L0 and L0s state before the next PM_ACTIVE_STATE_REQUEST_L1 DLLP is transmitted. Refer to the PCI Express r1.0a Errata, page 19, for detailed information. Contains PCI clock units. RW 14Dh (M66EN low) 29Ah (M66EN high) 31:11 Reserved RsvdP 0h Register 15-87. (Offset 1060h; CRSTIMER) CRS Timer Bit(s) Description Access Default 15:0 CRS Timer Valid only when the PCI Express Device Control register Bridge Configuration Retry Enable bit is set. Determines the number of microseconds to wait before returning a completion with CRS status in response to a PCI Express-to-PCI Configuration transaction. When the timer times out and the completion with CRS status is returned, the transaction is discarded from the Non-Posted Transaction queue. RW 25d 31:16 Reserved RsvdP 0h Register 15-88. (Offset 1064h; ECFGADDR) Enhanced Configuration Address Bit(s) Description Access Default RsvdP 0h 11:0 Reserved 14:12 Configuration Function Number Provides the Function Number for an enhanced Configuration transaction. RW 000b 19:15 Configuration Device Number Provides the Device Number for an enhanced Configuration transaction. RW 0h 27:20 Configuration Bus Number Provides the Bus Number for an enhanced Configuration transaction. RW 0h 30:28 Reserved RsvdP 000b RW 0 31 Enhanced Configuration Enable Does not apply to Forward Bridge mode. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 179 Forward Bridge Mode Configuration Registers 180 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 16 16.1 Reverse Bridge Mode Configuration Registers Register Description This chapter describes the PEX 8111 Configuration registers specific to Reverse Bridge mode. Registers specific to Forward Bridge mode are discussed in Chapter 15. The PCI-Compatible Reverse Bridge mode Configuration registers are accessed by the PCI host, using the PCI Configuration Address space. All Configuration registers are accessed from the PCI Express interface or PCI Bus, using the 64-KB memory space defined by the PCI Base Address 0 register. Registers that are written by the Serial EEPROM Controller are also written using Memory Writes through the PCI Base Address 0 register. In Reverse Bridge mode, a PCI master cannot access the PCI Express Extended Capability registers by way of PCI Configuration transactions. When the Configuration registers are accessed using Memory transactions to the PCI Base Address 0 register, the address mapping delineated in Table 16-1 is used. The Serial EEPROM Controller writes to Configuration registers. An upper Address bit is used to select one of two register spaces, as delineated in Table 16-2. Each register is 32 bits wide, and is accessed one byte, word, or DWORD at a time. These registers utilize Little Endian byte ordering, which is consistent with the PCI r3.0. The least significant byte in a DWORD is accessed at Address 0. The least significant bit in a DWORD is 0, and the most significant bit is 31. After the PEX 8111 is powered up or reset, the registers are set to their default values. Writes to unused registers are ignored, and reads from unused registers return a value of 0. Table 16-1. Reverse Bridge Mode PCI Base Address 0 Register Map Address Offset 0000h - 0FFFh Register Space PCI-Compatible Configuration registers 1000h - 1FFFh Main Configuration registers 2000h - 2FFFh Memory-Mapped indirect access to downstream PCI Express Endpoint registers 8000h - 9FFFh 8-KB internal shared memory Table 16-2. Selecting Register Space AD12 Register Space 0 PCI-Compatible Configuration registers 1 Main Configuration registers PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 181 Reverse Bridge Mode Configuration Registers 16.1.1 PLX Technology, Inc. Indexed Addressing In addition to Memory-Mapped accesses, the PEX 8111 Main Configuration registers can be accessed using the Main Control Register Index and Main Control Register Data registers. This method allows all Main Configuration registers to be accessed using Configuration transactions, rather than Memory transactions. First, the Main Configuration register offset is written to the Main Control Register Index register (offset 84h). Then, the Main Configuration register is written or read by accessing the Main Control Register Data register (offset 88h). 16.2 Configuration Access Types Table 16-3 delineates configuration access types referenced by the registers in this chapter. Table 16-3. Configuration Access Types Access Type 16.3 Description CFG Initiated by PCI Configuration transactions on the primary bus. MM Initiated by PCI Memory transactions on the primary or secondary bus, using the Address range defined by the PCI Base Address 0 register. EE Initiated by the Serial EEPROM Controller during initialization. Register Attributes Table 16-4 delineates the register attributes used to indicate access types provided by each register bit. Table 16-4. Register Attribute HwInit Description Hardware Initialized Register bits are initialized by firmware or hardware mechanisms such as ball strapping (on the BAR0ENB#, EXTARB, and FORWARD balls) or serial EEPROM. Bits are Read-Only after initialization and reset only with "Fundamental Reset." RO Read-Only Register Register bits are Read-Only and cannot be altered by software. Register bits are initialized by a PEX 8111 hardware initialization mechanism or PEX 8111 Serial EEPROM register initialization feature. RsvdP Reserved and Preserved Reserved for future RW implementations. Registers are Read-Only and must return 0 when read. Software must preserve value read for writes to bits. RsvdZ Reserved and Zero Reserved for future RW1C implementations. Registers are Read-Only and must return 0 when read. Software must use 0 for writes to bits. RW RW1C WO 182 Access Provided by Register Bits Read-Write Register Register bits are Read-Write and set or cleared by software to the needed state. Read-Only Status, Write 1 to Clear Status Register Register bits indicate status when read; a set bit indicating a status event is cleared by writing 1. Writing 0 to RW1C bits has no effect. Write-Only Used to indicate that a register is written by the Serial EEPROM Controller. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 16.4 Register Summary Register Summary Table 16-5. Reverse Bridge Mode Register Summary Register Group PCI-Compatible Configuration Registers (Type 1) PCI Space PCI Configuration Memory-Mapped, BAR0 Address Range 00h - 0FFh PCI Express Extended Capability Registers Memory-Mapped, BAR0 100h - 1FFh Main Control Registers Memory-Mapped, BAR0 1000h - 10FFh PCI Express Configuration Registers Using Enhanced Configuration Access Memory-Mapped, BAR0 2000h - 2FFFh 8-KB Shared Memory instead of General Purpose Memory Memory-Mapped, BAR0 8000h - 9FFFh PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 183 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. 16.5 Register Maps 16.5.1 PCI-Compatible Configuration Registers (Type 1) Table 16-6. Reverse Bridge Mode PCI-Compatible Configuration (Type 1) Register Map PCI Configuration Register Offset 31 24 23 16 15 0 00h PCI Device ID PCI Vendor ID 04h PCI Status PCI Command 08h 0Ch PCI Device Revision ID PCI Class Code PCI Built-In Self-Test (Not Supported) PCI Header Type PCI Bus Latency Timer 10h PCI Base Address 0 14h PCI Base Address 1 18h 1Ch Reserved Subordinate Bus Number Secondary Status PCI Cache Line Size Secondary Bus Number Primary Bus Number I/O Limit I/O Base 20h Memory Limit Memory Base 24h Prefetchable Memory Limit Prefetchable Memory Base 28h 2Ch 30h Prefetchable Memory Base Upper 32 Bits Prefetchable Memory Limit Upper 32 Bits I/O Limit Upper 16 Bits 34h 38h 3Ch 184 8 7 I/O Base Upper 16 Bits PCI Capabilities Pointer Reserved PCI Base Address for Expansion ROM (Not Supported) Bridge Control PCI Interrupt Pin PCI Interrupt Line PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 16.5.2 PCI-Compatible Extended Capability Registers for PCI Express Interface PCI-Compatible Extended Capability Registers for PCI Express Interface Table 16-7. Reverse Bridge Mode PCI-Compatible Extended Capability for PCI Express Interface Register Map PCI Configuration Register Offset 40h 44h 31 24 23 16 15 Power Management Next Capability Pointer Power Management Capabilities Power Management Data 8 7 Power Management Bridge Support Device-Specific Control 4Ch Reserved Message Signaled Interrupts Next Capability Pointer Message Signaled Interrupts Control 54h Message Signaled Interrupts Address 58h Message Signaled Interrupts Upper Address 5Ch Reserved 60h PCI Express Capabilities PCI Express Next Capability Pointer PCI Express Capability ID Device Capabilities PCI Express Device Status 6Ch 70h Message Signaled Interrupts Capability ID Message Signaled Interrupts Data 64h 68h Power Management Capability ID Power Management Control/Status 48h 50h 0 PCI Express Device Control Link Capabilities Link Status 74h Link Control Slot Capabilities 78h Slot Status Slot Control 7Ch Reserved Root Control 80h Root Status 84h Main Control Register Index 88h Main Control Register Data PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 185 Reverse Bridge Mode Configuration Registers 16.5.3 PLX Technology, Inc. PCI Express Extended Capability Registers Table 16-8. Reverse Bridge Mode Power Budgeting Capability and Device Serial Number Register Map PCI Express Configuration Register Offset 100h 31 20 19 Power Budgeting Next Capability Offset 104h 0 Power Budgeting PCI Express Extended Capability ID Power Budgeting Data Select Power Budgeting Data 10Ch 186 Power Budgeting Capability Version 8 7 Reserved 108h 110h 16 15 Power Budget Capability Reserved Serial Number Next Capability Offset Serial Number Capability Version Serial Number PCI Express Extended Capability ID 114h Serial Number Low (Lower DWORD) 118h Serial Number Hi (Upper DWORD) PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 16.5.4 Main Control Registers Main Control Registers Table 16-9. Reverse Bridge Mode 32-Bit Main Control Register Map PCI Express Configuration Register Offset 31 0 1000h Device Initialization 1004h Serial EEPROM Control 1008h Serial EEPROM Clock Frequency 100Ch PCI Control 1010h Reserved 1014h PCI Interrupt Request Enable 1018h Interrupt Request Status 101Ch Reserved 1020h General-Purpose I/O Control 1024h General-Purpose I/O Status 1030h Mailbox 0 1034h Mailbox 1 1038h Mailbox 2 103Ch Mailbox 3 1040h Chip Silicon Revision 1044h Diagnostic Control (Factory Test Only) 1048h TLP Controller Configuration 0 104Ch TLP Controller Configuration 1 1050h TLP Controller Configuration 2 1054h TLP Controller Tag 1058h TLP Controller Time Limit 0 105Ch TLP Controller Time Limit 1 1060h Reserved 1064h Enhanced Configuration Address PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 187 Reverse Bridge Mode Configuration Registers 16.6 PLX Technology, Inc. PCI-Compatible Configuration Registers (Type 1) Register 16-1. (Offset 00h; PCIVENDID) PCI Vendor ID Bit(s) 15:0 Description PCI Vendor ID Identifies the PEX 8111 manufacturer. The PEX 8111 returns the PLX PCI-SIG-assigned Vendor ID, 10B5h. CFG MM EE Default RO RW WO 10B5h CFG MM EE Default RO RW WO 8111h Register 16-2. (Offset 02h; PCIDEVID) PCI Device ID Bit(s) 15:0 188 Description PCI Device ID Identifies the particular device, as specified by the Vendor. The PEX 8111 returns the PLX-assigned Device ID, 8111h. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-3. (Offset 04h; PCICMD) PCI Command Bit(s) Description CFG MM EE Default 0 I/O Access Enable Enables the PEX 8111 to respond to I/O space accesses on the primary interface (PCI). These accesses are directed to a target on the PCI Express interface, because the PEX 8111 does not have internal I/O-Mapped devices. 0 = PCI I/O accesses to the PEX 8111 result in a Master Abort RW RW WO 0 1 Memory Space Enable Enables the PEX 8111 to respond to Memory space accesses on the primary interface (PCI). These accesses are directed to a target on the PCI Express interface, or to internal Memory-Mapped registers. 0 = PCI Memory accesses to the PEX 8111 result in a Master Abort RW RW WO 0 2 Bus Master Enable 0 = PEX 8111 must disable response as a target to all Memory or I/O transactions on the PCI Express secondary interface (they cannot be forwarded to the primary interface). In this case, all Memory and I/O requests are terminated with an Unsupported Request completion. 1 = Enables the PEX 8111 to perform Memory or I/O transactions on the PCI Bus. Configuration transactions are forwarded from the PCI Express interface and performed on the PCI Bus, independent of this bit. RW RW WO 0 3 Special Cycle Enable Bridges do not respond to special cycle transactions; therefore, forced to 0. RO RO - 0 4 Memory Write and Invalidate 0 = Enables the PEX 8111 PCI Bus master logic to use the Memory Write command 1 = Enables the PEX 8111 PCI Bus master logic to use the Memory Write and Invalidate command RW RW WO 0 5 VGA Palette Snoop 1 = I/O writes in the first 64 KB of the I/O Address space with Address bits [9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA aliases - AD[15:10] are not decoded and are of any value) must be positively decoded on the PCI interface and forwarded to the PCI Express secondary interface RW RW WO 0 6 Parity Error Response Enable Enables PCI Parity checking. RW RW WO 0 7 Reserved RsvdP RsvdP - 0 8 SERR# Enable 1 = Enables the SERR# signal to assert RW RW WO 0 9 Fast Back-to-Back Enable The PEX 8111 PCI master interface does not perform Fast Back-to-Back transactions; therefore, forced to 0. RO RO - 0 RW RW WO 0 RsvdP RsvdP - 0h 10 Interrupt Disable 1 = PEX 8111 is prevented from asserting INTx# signals on behalf of functions integrated into the PEX 8111 There is no effect on INTx# signals asserted on behalf of INTx# messages associated with the PCI Express secondary interface. 15:11 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 189 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-4. (Offset 06h; PCISTAT) PCI Status Bit(s) CFG MM EE Default RsvdZ RsvdZ - 000b 3 Interrupt Status Reflects the PEX 8111 internal PCI interrupt status state. One of the INTx# signals is asserted when this bit is high, the PCI Command register Interrupt Disable bit is low, and the Power State is D0. RO RO - 0 4 Capabilities List Indicates when the PCI Capabilities Pointer at offset 34h is valid. RO RO - 1 5 66-MHz Capable Indicates whether the PEX 8111 is capable of running at 66 MHz. 0 = Indicates 33 MHz 1 = Indicates PEX 8111 is 66-MHz capable RO RW WO 1 6 Reserved RsvdZ RsvdZ - 0 7 Fast Back-to-Back Transactions Capable The PEX 8111 does not accept Fast Back-to-Back transactions; therefore, forced to 0. RO RO - 0 RW1C RW1C - 0 RO RO - 01b 11 Signaled Target Abort Reports Target Abort termination signaling by the PEX 8111 when it responds as the transaction target on its primary interface. This does not occur on the PEX 8111; therefore, this bit always returns 0. RsvdZ RsvdZ - 0 12 Received Target Abort Reports Target Abort termination detection by the PEX 8111 when it is the transaction master on its primary interface. Writing 1 clears this bit. RW1C RW1C - 0 13 Received Master Abort Reports Master Abort termination detection by the PEX 8111 when it is the transaction master on its primary interface. Writing 1 clears this bit. RW1C RW1C - 0 14 Signaled System Error Set when the PEX 8111 asserts the SERR# signal. Writing 1 clears this bit. RW1C RW1C - 0 15 Detected Parity Error Set when the PEX 8111 detects a parity error on incoming addresses or data from the PCI Bus, regardless of the PCI Command register Parity Error Response Enable bit state. Writing 1 clears this bit. RW1C RW1C - 0 2:0 8 Description Reserved Master Data Parity Error 1 = Indicates that a data parity error occurred when this device was the PCI Bus master. The PCI Command register Parity Error Response Enable bit must be set for this bit to be set. Writing 1 clears this bit. 10:9 190 DEVSEL Timing Determines how quickly this device responds to a transaction with DEVSEL#. 01b = Indicates a medium response PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-5. (Offset 08h; PCIDEVREV) PCI Device Revision ID Bit(s) Description CFG MM EE Default 7:0 PCI Device Revision ID Identifies the PEX 8111 Silicon Revision. Bits [3:0] represent the minor revision number and bits [7:4] represent the major revision number. RO RO - 21h CFG MM EE Default Register 16-6. (Offset 09h; PCICLASS) PCI Class Code Bit(s) Description 7:0 Programming Interface RO RW WO 00h 15:8 Subclass Code RO RW WO 04h 23:16 Base Class Code RO RW WO 06h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 191 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-7. (Offset 0Ch; PCICACHESIZE) PCI Cache Line Size Bit(s) Description CFG MM EE Default 7:0 PCI Cache Line Size Specifies the System Cache Line Size (in units of DWORDs). The value in this register is used by PCI master devices to determine whether to use Read, Memory Read Line, Memory Read Multiple, or Memory Write and Invalidate commands for accessing memory. The PEX 8111 supports Cache Line Sizes of 2, 4, 8, 16, or 32 DWORDs. Writes of values other than these result in a Cache Line Size of 0; however, the value written is returned when this register is read. RW RW WO 0h Register 16-8. (Offset 0Dh; PCILATENCY) PCI Bus Latency Timer Bit(s) Description CFG MM EE Default 7:0 PCI Bus Latency Timer Also referred to as Primary Latency Timer for Type 1 Configuration Space Header devices. Specifies (in PCI Clock units) the value of the Latency Timer during Bus Master bursts. When the Latency Timer expires, the PEX 8111 must terminate its tenure on the bus. RW RW WO 0h Register 16-9. (Offset 0Eh; PCIHEADER) PCI Header Type Bit(s) 7:0 Description PCI Header Type Specifies the format of the second part of the pre-defined configuration header starting at offset 10h. For PCI bridges, this field is forced to 1h. CFG MM EE Default RO RO - 1h CFG MM EE Default RO RO - 0h Register 16-10. (Offset 0Fh; PCIBIST) PCI Built-In Self-Test Bit(s) 7:0 192 Description PCI Built-In Self-Test Not supported. Always returns a value of 0h. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-11. (Offset 10h; PCIBASE0) PCI Base Address 0 Bit(s) Description CFG MM EE Default 0 Space Type When low, this space is accessed as memory. When high, this space is accessed as I/O. RO RO - 0 Address Type Indicates the type of addressing for this space. 00b = Locate anywhere in 32-bit Address space 01b = Locate below 1 MB 10b = Locate anywhere in 64-bit Address space 11b = Reserved RO RW WO 10b Prefetch Enable 1 = Indicates that prefetching has no side effects on reads RO RW WO 1 RO RO - 0h RW RW WO 0h CFG MM EE Default RW RW WO 0h Note: Hardwired to 0. 2:1 3 15:4 Base Address This section of the Base address is ignored for a 64-KB space. Note: Hardwired to 0. 31:16 Base Address Specifies the upper 16 bits of the 32-bit starting Base address of the 64-KB Address space for the PEX 8111 Configuration registers and shared memory. Register 16-12. (Offset 14h; PCIBASE1) PCI Base Address 1 Bit(s) 31:0 Description Base Address 1 Determines the upper 32 bits of the address when PCI Base Address 0 is configured for 64-bit addressing. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 193 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-13. (Offset 18h; PRIMBUSNUM) Primary Bus Number Bit(s) 7:0 Description Primary Bus Number Used to record the Bus Number of the PCI Bus segment to which the primary interface of the PEX 8111 is connected. CFG MM EE Default RW RW WO 0h Register 16-14. (Offset 19h; SECBUSNUM) Secondary Bus Number Bit(s) Description CFG MM EE Default 7:0 Secondary Bus Number Used to record the Bus Number of the PCI Bus segment to which the PEX 8111 secondary interface is connected. RW RW WO 0h CFG MM EE Default RW RW WO 0h Register 16-15. (Offset 1Ah; SUBBUSNUM) Subordinate Bus Number Bit(s) 7:0 194 Description Subordinate Bus Number Used to record the Bus Number of the highest-numbered PCI Bus segment behind (or subordinate to) the PEX 8111. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-16. (Offset 1Ch; IOBASE) I/O Base Bit(s) Description CFG MM EE Default 3:0 I/O Base Address Capability Indicates the type of addressing for this space. 0000b = 16-bit I/O address 0001b = 32-bit I/O address All other values are reserved. RO RW WO 0000b 7:4 I/O Base Determines the starting address at which I/O transactions on the primary interface are forwarded to the secondary interface. The upper four bits of this register correspond to Address bits AD[15:12]. For address decoding purposes, the PEX 8111 assumes that the lower 12 Address bits, AD[11:0], of the I/O Base address are zero (0h). Therefore, the bottom of the defined I/O Address range is aligned to a 4-KB Address Boundary space, and the top is one less than a 4-KB Address Boundary space. RW RW WO 0h CFG MM EE Default RO RO - 0000b RW RW WO 0h Register 16-17. (Offset 1Dh; IOLIMIT) I/O Limit Bit(s) 3:0 Description I/O Limit Address Capability Indicates the type of addressing for this space. 0000b = 16-bit I/O address 0001b = 32-bit I/O address All other values are reserved. The value returned in this field is derived from the I/O Base register I/O Base Address Capability field. 7:4 I/O Limit Determines the I/O Space range forwarded from the primary interface to the secondary interface. The upper four bits of this register correspond to Address bits AD[15:12]. For address decoding purposes, the PEX 8111 assumes that the lower 12 Address bits, AD[11:0], of the I/O Limit address are FFFh. When there are no I/O addresses on the secondary side of the bridge, the I/O Limit field is programmed to a value smaller than the I/O Base register I/O Base field. In this case, the PEX 8111 does not forward I/O transactions from the primary bus to the secondary bus; however, the PEX 8111 does forward all I/O transactions from the secondary bus to the primary bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 195 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-18. (Offset 1Eh; SECSTAT) Secondary Status Bit(s) CFG MM EE Default RsvdZ RsvdZ - 0h RO RO - 0 RsvdZ RsvdZ - 0 RO RO - 0 RW1C RW1C - 0 RO RO - 00b 11 Secondary Signaled Target Abort Set when the PEX 8111 completes a request as a transaction target on its secondary interface using Completer Abort completion status. Writing 1 clears this bit. RW1C RW1C - 0 12 Secondary Received Target Abort Set when the PEX 8111 receives a completion with Completer Abort completion status on its secondary interface. Writing 1 clears this bit. RW1C RW1C - 0 13 Secondary Received Master Abort Set when the PEX 8111 receives a completion with Unsupported Request completion status on its secondary interface. Writing 1 clears this bit. RW1C RW1C - 0 14 Secondary Received System Error Set when the PEX 8111 receives an ERR_FATAL or ERR_NONFATAL message from the downstream PCI Express device. Writing 1 clears this bit. RW1C RW1C - 0 15 Secondary Detected Parity Error Set by the PEX 8111 when it receives a poisoned TLP on the secondary interface, regardless of the Bridge Control register Secondary Parity Error Response Enable bit state. Writing 1 clears this bit. RW1C RW1C - 0 4:0 Reserved 5 Secondary 66-MHz Capable Not valid for PCI Express. Indicates whether the PEX 8111 secondary interface is capable of operating at 66 MHz. Forced to 0. 6 Reserved 7 Secondary Fast Back-to-Back Transactions Capable Not valid for PCI Express. Indicates whether the PEX 8111 secondary interface is capable of decoding Fast Back-to-Back transactions when the transactions are from the same master but to different targets. Forced to 0. 8 Secondary Master Data Parity Error Used to report Data Parity error detection by the PEX 8111. Set when the Bridge Control register Secondary Parity Error Response Enable bit is set and either of the following two conditions occur: * Bridge receives a completion marked poisoned on the secondary interface * Bridge poisons a Write Request or Read Completion on the secondary interface Writing 1 clears this bit. 10:9 196 Description Secondary DEVSEL Timing Not valid for PCI Express. Encodes the secondary interface DEVSEL# timing. Forced to 00b. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-19. (Offset 20h; MEMBASE) Memory Base Bit(s) 3:0 15:4 Description Reserved Note: Hardwired to 0h. Memory Base Determines the starting address at which Memory transactions on the primary interface are forwarded to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Memory Base address are zero (0h). The bottom of the defined Memory Address range is aligned to a 1-MB Address Boundary space, and the top is one less than a 1-MB Address Boundary space. CFG MM EE Default RsvdP RsvdP - 0h RW RW WO - CFG MM EE Default RsvdP RsvdP - 0h RW RW WO - Register 16-20. (Offset 22h; MEMLIMIT) Memory Limit Bit(s) 3:0 15:4 Description Reserved Note: Hardwired to 0h. Memory Limit Determines the Memory Space range forwarded from the primary interface to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Memory Limit address are FFFFFh. When there are no Memory-Mapped I/O addresses on the secondary side of the bridge, the Memory Limit field must be programmed to a value smaller than the Memory Base register Memory Base field. When there is no Prefetchable memory, and no Memory-Mapped I/O on the secondary side of the bridge, the PEX 8111 does not forward Memory transactions from the primary bus to the secondary bus; however, it does forward all Memory transactions from the secondary bus to the primary bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 197 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-21. (Offset 24h; PREBASE) Prefetchable Memory Base Bit(s) Description CFG MM EE Default 3:0 Prefetchable Base Address Capability Indicates the type of addressing for this space. 0000b = 32-bit I/O address 0001b = 64-bit I/O address All other values are reserved. RO RW WO 0000b 15:4 Prefetchable Memory Base Determines the starting address at which Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Prefetchable Memory Base address are zero (0h). The bottom of the defined Prefetchable Memory Address range is aligned to a 1-MB Address Boundary space, and the top is one less than a 1-MB Address Boundary space. RW RW WO - CFG MM EE Default RO RO - 0000b RW RW WO - Register 16-22. (Offset 26h; PRELIMIT) Prefetchable Memory Limit Bit(s) 3:0 Description Prefetchable Limit Address Capability Indicates the type of addressing for this space. 0000b = 32-bit I/O address 0001b = 64-bit I/O address All other values are reserved. The value returned in this field is derived from the Prefetchable Memory Base register Prefetchable Base Address Capability field. 15:4 198 Prefetchable Memory Limit Determines the Prefetchable Memory space range forwarded from the primary interface to the secondary interface. The upper 12 bits of this register correspond to Address bits AD[31:20]. For address decoding purposes, the PEX 8111 assumes that the lower 20 Address bits, AD[19:0], of the Prefetchable Memory Limit address are FFFFFh. When there is no prefetchable memory on the secondary side of the bridge, the Prefetchable Memory Limit field must be programmed to a value smaller than the Prefetchable Memory Base register Prefetchable Memory Base field. When there is no Prefetchable memory, and no Memory-Mapped I/O on the secondary side of the bridge, the PEX 8111 does not forward Memory transactions from the primary bus to the secondary bus; however, it does forward all Memory transactions from the secondary bus to the primary bus. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-23. (Offset 28h; PREBASEUPPER) Prefetchable Memory Base Upper 32 Bits Bit(s) Description CFG MM EE Default 31:0 Prefetchable Memory Base Upper 32 Bits When the Prefetchable Memory Base register Prefetchable Base Address Capability field indicates 32-bit addressing, this register is Read-Only and returns 0h. When the Prefetchable Base Address Capability field indicates 64-bit addressing, this register determines the upper 32 bits of the starting address at which Prefetchable Memory transactions on the primary interface are forwarded to the secondary interface. RW RW WO 0h Register 16-24. (Offset 2Ch; PRELIMITUPPER) Prefetchable Memory Limit Upper 32 Bits Bit(s) Description CFG MM EE Default 31:0 Prefetchable Memory Limit Upper 32 Bits When the Prefetchable Memory Limit register Prefetchable Limit Address Capability field indicates 32-bit addressing, this register is Read-Only and returns 0h. When thePrefetchable Limit Address Capability field indicates 64-bit addressing, this register determines the upper 32 bits of the Prefetchable Memory range forwarded from the primary interface to the secondary interface. RW RW WO 0h CFG MM EE Default RW RW WO - CFG MM EE Default RW RW WO - Register 16-25. (Offset 30h; IOBASEUPPER) I/O Base Upper 16 Bits Bit(s) 15:0 Description I/O Base Upper 16 Bits When the I/O Base register I/O Base Address Capability field indicates 16-bit addressing, this register is Read-Only and returns 0h. When the I/O Base Address Capability field indicates 32-bit addressing, this register determines the upper 16 bits of the starting address at which I/O transactions on the primary interface are forwarded to the secondary interface. Register 16-26. (Offset 32h; IOLIMITUPPER) I/O Limit Upper 16 Bits Bit(s) 15:0 Description I/O Limit Upper 16 Bits When the I/O Limit register I/O Limit Address Capability field indicates 16-bit addressing, this register is Read-Only and returns 0h. When the I/O Limit Address Capability field indicates 32-bit addressing, this register determines the upper 16 bits of the I/O range forwarded from the primary interface to the secondary interface. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 199 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-27. (Offset 34h; PCICAPPTR) PCI Capabilities Pointer Bit(s) Description 7:0 PCI Capabilities Pointer Provides the offset location of the first New Capabilities register. 31:8 Reserved CFG MM EE Default RO RW WO 40h RsvdP RsvdP - 0h CFG MM EE Default RW RW WO 0h CFG MM EE Default RO RW WO 1h Register 16-28. (Offset 3Ch; PCIINTLINE) PCI Interrupt Line Bit(s) 7:0 Description PCI Interrupt Line Indicates to which system interrupt controller input the PEX 8111 Interrupt ball is connected. Device drivers and operating systems use this field. Register 16-29. (Offset 3Dh; PCIINTPIN) PCI Interrupt Pin Bit(s) 7:0 200 Description PCI Interrupt Pin Selects which Interrupt pin the PEX 8111 uses. 1h = INTA# PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-30. (Offset 3Eh; BRIDGECTL) Bridge Control Bit(s) Description CFG MM EE Default 0 Secondary Parity Error Response Enable Controls the PEX 8111's response to Data Parity errors forwarded from the primary interface (such as, a poisoned TLP). 0 = PEX 8111 must ignore Data Parity errors detected and continue standard operation 1 = PEX 8111 must take its standard action when a Data Parity error is detected RW RW WO 0 1 Secondary SERR# Enable No effect in Reverse Bridge mode. Secondary bus error reporting using SERR# is controlled by the Root Control register. RW RW WO 0 2 ISA Enable Modifies the PEX 8111's response to ISA I/O addresses that are enabled by the I/O Base and I/O Limit registers and located in the first 64 KB of the PCI I/O Address space. 1 = PEX 8111 blocks forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded when they address the last 768 bytes in each 1-KB block. RW RW WO 0 3 VGA Enable Modifies the PEX 8111's response to VGA-compatible addresses. When set, the bridge positively decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, blocks the forwarding of these addresses from the secondary to primary interface): * Memory accesses in the range 000A_0000h to 000B_FFFFh * I/O address in the first 64 KB of the I/O Address space [Address[31:16] for PCI Express are zero (0000h)] and where Address[9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA address aliases - Address[15:10] can be any value and is not used in decoding) When the VGA Enable bit is set, VGA address forwarding is independent of the ISA Enable bit value, and the I/O Address range and Memory Address ranges defined by the I/O Base and I/O Limit, Memory Base and Memory Limit, and Prefetchable Memory Base and Prefetchable Memory Limit registers. VGA address forwarding is qualified by the PCI Command register I/O Access Enable and Memory Space Enable bits. 0 = Does not forward VGA-compatible Memory and I/O addresses from the primary to secondary interface (addresses defined above), unless they are enabled for forwarding by the defined I/O and Memory Address ranges 1 = Forwards VGA-compatible Memory and I/O addresses (addresses defined above) from the primary interface to the secondary interface (when the I/O Access Enable and Memory Space Enable bits are set), independent of the I/O and Memory Address ranges and ISA Enable bit RW RW WO 0 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 201 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-30. (Offset 3Eh; BRIDGECTL) Bridge Control (Cont.) Bit(s) Description CFG MM EE Default 4 VGA 16-Bit Decode Enables the PEX 8111 to provide 16-bit decoding of the VGA I/O address, precluding the decoding of alias addresses every 1 KB. Useful only when bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O decoding and forwarding by the PEX 8111. Enables system configuration software to select between 10- and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary to secondary, when the VGA Enable bit is set to 1. 0 = Execute 10-bit address decodes on VGA I/O accesses 1 = Execute 16-bit address decodes on VGA I/O accesses RW RW WO 0 RW RW WO 0 6 Secondary Bus Reset 1 = Causes a Hot Reset to be communicated on the secondary bus. Additionally, the PEX 8111 secondary bus interface, and buffers between the two interfaces (primary and secondary), must be initialized to their default state. The primary bus interface and Configuration Space registers are not affected by setting this bit. RW RW WO 0 7 Fast Back-to-Back Enable Not supported. Controls bridge ability to generate Fast Back-to-Back transactions to different devices on the secondary interface. RO RO - 0 Master Abort Mode Controls the PEX 8111's behavior when it receives a Master Abort termination on the PCI Bus or an Unsupported Request on PCI Express. 0 = Do not report Master Aborts * When PCI Express UR is received: - Return FFFF_FFFFh to PCI Bus for Reads - Complete Non-Posted Write normally on PCI Bus (assert TRDY#) and discard the Write data - Discard Posted PCI-to-PCI Express Write data * 5 When PCI transaction terminates with Master Abort: - Complete Non-Posted transaction with Unsupported Request - Discard Posted Write data from PCI Express-to-PCI 1 = Report Master Aborts * When PCI Express UR is received: - Complete Reads and Non-Posted Writes with PCI Target Abort - Discard Posted PCI-to-PCI Express Write data * When PCI transaction terminates with Master Abort: - Complete Non-Posted transaction with Unsupported Request - Discard Posted Write data from PCI Express-to-PCI - Transmit ERR_NONFATAL message for Posted Writes 202 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Configuration Registers (Type 1) Register 16-30. (Offset 3Eh; BRIDGECTL) Bridge Control (Cont.) Bit(s) 8 Description Primary Discard Timer Selects the number of PCI clocks that the PEX 8111 waits for a master on the primary interface to repeat a Delayed Transaction request. The counter starts after the completion (PCI Express Completion associated with the Delayed Transaction request) reaches the head of the PEX 8111 downstream queue (that is, all ordering requirements are satisfied and the PEX 8111 is ready to complete the Delayed Transaction with the originating master on the secondary bus). When the originating master does not repeat the transaction before the counter expires, the PEX 8111 deletes the Delayed Transaction from its queue and sets the Discard Timer Status bit. CFG MM EE Default RW RW WO 0 RO RO - 0 RW1C RW1C - 0 RW RW WO 0 RsvdP RsvdP - 0h 0 = Secondary Discard Timer counts 215 PCI clock periods 1 = Secondary Discard Timer counts 210 PCI clock periods 9 Secondary Discard Timer In Reverse Bridge mode, this bit does not apply and is forced to 0. 10 Discard Timer Status Set to 1 when the Primary Discard Timer expires and a Delayed Completion is discarded from a queue within the PEX 8111. 11 Discard Timer SERR# Enable When set to 1, enables the PEX 8111 to assert SERR# on the primary interface when the Primary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 8111. 0 = Does not assert SERR# on the primary interface as a result of the Primary Discard Timer expiration 1 = Generates SERR# on the primary interface when the Primary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 8111 15:12 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 203 Reverse Bridge Mode Configuration Registers 16.7 PLX Technology, Inc. PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-31. (Offset 40h; PWRMNGID) Power Management Capability ID Bit(s) 7:0 Description Power Management Capability ID Specifies the Power Management Capability ID. CFG MM EE Default RO RO - 01h Register 16-32. (Offset 41h; PWRMNGNEXT) Power Management Next Capability Pointer Bit(s) 7:0 Description PCI Power Management Next Capability Pointer Points to the first location of the next item in the New Capabilities Linked List, Message Signaled Interrupts. CFG MM EE Default RO RW WO 50h Register 16-33. (Offset 42h; PWRMNGCAP) Power Management Capabilities Bit(s) Description CFG MM EE Default 2:0 PME Version Default 010b indicates compliance with the PCI Power Mgmt. r1.1. RO RW WO 010b PME Clock When low, indicates that no PCI clock is required to generate PMEOUT#. When high, indicates that a PCI clock is required to generate PMEOUT#. RO RW WO 0 3 4 Reserved RsvdP RsvdP - 0 5 Device-Specific Initialization Indicates that the PEX 8111 requires special initialization following a transition to the D0_uninitialized state before the generic class device driver uses it. RO RW WO 0 8:6 AUX Current Reports the 3.3Vaux auxiliary current requirements for the PCI function. When PMEOUT# generation from D3cold is not supported by the function, must return a value of 000b. RO RW WO 000b 9 D1 Support Indicates whether the PEX 8111 supports the D1 state. RO RW WO 1 10 D2 Support Indicates whether the PEX 8111 supports the D2 state. RO RW WO 0 PME Support Default 11001b indicates that the corresponding PEX 8111 port forwards PME messages in the D0, D3hot, and D3cold power states. XXXX1b = Assertable from D0 XXX1Xb = Assertable from D1 XX1XXb = Assertable from D2 X1XXXb = Assertable from D3hot 1XXXXb = Assertable from D3cold RO RW WO 11001b 15:11 204 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-34. (Offset 44h; PWRMNGCSR) Power Management Control/Status Bit(s) CFG MM EE Default RW RW WO 00b RsvdP RsvdP - 0h PME Enable Enables the PMEOUT# signal to assert. RW RW WO 0 12:9 Data Select Not supported. Always returns a value of 0h. RO RO - 0h 14:13 Data Scale Not supported. Always returns a value of 00b. RO RO - 00b RW1C RW1C - 0 1:0 Description Power State Used to determine or change the current power state. 00b = D0 01b = D1 10b = D2 11b = D3hot A transition from state D3 to state D0 causes a Hot Reset to occur. In states D1 and D2, when the corresponding D1 Support and D2 Support bits are set, PCI Memory and I/O accesses are disabled, as well as the PCI interrupt; however, Configuration cycles are allowed. In state D3hot, these functions are also disabled. 7:2 8 15 Reserved PME Status When the PME Enable bit is set high, indicates that PMEOUT# is being driven. Writing 1 from the PCI Bus clears this bit. Register 16-35. (Offset 46h; PWRMNGBRIDGE) Power Management Bridge Support Bit(s) CFG MM EE Default RsvdP RsvdP - 0h 6 B2/B3 Support 0 = Indicates that, when the PEX 8111 function is programmed to D3hot, power is removed (B3) from its secondary bus. Useful only when bit 7 is set. 1 = Indicates that, when the PEX 8111 function is programmed to D3hot, its secondary bus PCI clock is stopped (B2). RO RW WO 0 7 Bus Power/Clock Control Enable 1 = Indicates that the bus power/clock control mechanism (as defined in the PCI-to-PCI Bridge r1.1, Section 4.7.1) is enabled RO RW WO 0 CFG MM EE Default RO RO - 0h 5:0 Description Reserved Register 16-36. (Offset 47h; PWRMNGDATA) Power Management Data Bit(s) 7:0 Description Power Management Data Not supported. Always returns a value of 0h. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 205 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-37. (Offset 48h; DEVSPECCTL) Device-Specific Control Bit(s) Description CFG MM EE Default 0 Blind Prefetch Enable 0 = Memory Read command on the PCI Bus that targets the PCI Express Memory space causes only 1 word to be read from the PCI Express interface. 1 = Memory Read command on the PCI Bus that targets the PCI Express Memory space causes at least one Cache Line to be read from the PCI Express interface. Additional Dwords can be read by setting the PCI Control register Programmed Prefetch Size field. RW RW WO 0 1 PCI Base Address 0 Enable 1 = Enables the PCI Base Address 0 space for Memory-Mapped access to the Configuration registers and shared memory. PCI Base Address 0 is also enabled when the BAR0ENB# ball is low. RW RW WO 0 2 L2 Enable 0 = Power state change to D3 does not cause the PEX 8111 to change the link state to L2 1 = Power state change to D3 causes the PEX 8111 to change the link state to L2 RW RW WO 0 3 PMU Power Off 1 = Link transitioned to the L2/L3 Ready state, and is ready to power down RO RO - 0 7:4 PMU Link State Indicates the link state. 0001b = L0 0010b = L0s 0100b = L1 1000b = L2 All other values are reserved. RO RO - - 9:8 CRS Retry Control Determines the PEX 8111 response when a PCI-to-PCI Express Configuration transaction is terminated with a Configuration Request Retry Status. 00b = Retry once after 1s. When another CRS is received, Target Abort on the PCI Bus. 01b = Retry eight times, one time per second. When another CRS is received, Target Abort on the PCI Bus. 10b = Retry one time per second until successful completion. 11b = Reserved RW RW WO 00b 10 WAKE Out Enable Does not apply to Reverse Bridge mode. RW RW WO 0 11 Beacon Generate Enable Does not apply to Reverse Bridge mode. RW RW WO 0 12 Beacon Detect Enable 1 = Beacon detected while the link is in the L2 state causes the Power Management Control/Status register PME Status bit to be set RW RW WO 0 13 PLL Locked High when the internal PLL is locked. RO RO - - RsvdP RsvdP - 00b RO RO - - RsvdP RsvdP - 0h 15:14 Reserved 20:16 Link Training and Status State Machine Factory Test Only. 31:21 Reserved 206 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-38. (Offset 50h; MSIID) Message Signaled Interrupts Capability ID Bit(s) 7:0 Description MSI Capability ID Specifies the Message Signaled Interrupts Capability ID. CFG MM EE Default RO RO - 5h Register 16-39. (Offset 51h; MSINEXT) Message Signaled Interrupts Next Capability Pointer Bit(s) Description CFG MM EE Default 7:0 MSI Next Capability Pointer Points to the first location of the next item in the New Capabilities Linked List, PCI Express Capability. RO RW WO 60h CFG MM EE Default MSI Enable When set: * Enables the PEX 8111 to use MSI to request service * INTx# outputs are disabled RW RW WO 0 3:1 Multiple Message Capable System software reads this field to determine the number of requested messages. The number of requested messages must be aligned to a power of two (when a function requires three messages, it requests four). Value Number of Messages Requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b Reserved RO RO - 000b 6:4 Multiple Message Enable System software writes to this field to indicate the number of allocated messages (equal to or less than the number of requested messages). The number of allocated messages is aligned to a power of two. Value Number of Messages Requested 000b 1 001b 2 010b 4 011b 8 100b 16 101b 32 110b, 111b Reserved RW RW WO 000b 7 MSI 64-Bit Address Capable 1 = PEX 8111 is capable of generating a 64-bit Message address RO RW WO 0 8 Per Vector Masking Capable Not supported. Forced to 0. RO RO - 0 RsvdP RsvdP - 0h Register 16-40. (Offset 52h; MSICTL) Message Signaled Interrupts Control Bit(s) 0 15:9 Description Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 207 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-41. (Offset 54h; MSIADDR) Message Signaled Interrupts Address Bit(s) Description 1:0 Reserved 31:2 MSI Address When the Message Signaled Interrupts Control register MSI Enable bit is set, the register contents specify the DWORD-aligned address for the MSI Memory Write transaction. Address bits [1:0] are driven to zero (00b) during the Address phase. CFG MM EE Default RsvdP RsvdP - 00b RW RW WO 0h Register 16-42. (Offset 58h; MSIUPPERADDR) Message Signaled Interrupts Upper Address Bit(s) Description CFG MM EE Default 31:0 MSI Upper Address Optionally implemented only when the PEX 8111 supports a 64-bit Message address when the Message Signaled Interrupts Control register MSI 64-Bit Address Capable bit is set. When the Message Signaled Interrupts Control register MSI Enable bit is set, the register contents specify the upper 32 bits of a 64-bit message. When the register contents are zero (0h), the PEX 8111 uses the 32-bit address specified by the Message Signaled Interrupts Address register. RW RW WO 0h Register 16-43. (Offset 5Ch; MSIDATA) Message Signaled Interrupts Data Bit(s) Description CFG MM EE Default 15:0 MSI Data When the Message Signaled Interrupts Control register MSI Enable bit is set, the Message data is driven onto the lower word of the AD Bus (AD[15:0]) of the Memory Write Transaction Data phase. The upper word (AD[31:16]) is always cleared to 0h. RW RW WO 0h 31:16 Reserved RsvdP RsvdP - 0h 208 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-44. (Offset 60h; PCIEXID) PCI Express Capability ID Bit(s) 7:0 Description PCI Express Capability ID Specifies the PCI Express Capability ID. CFG MM EE Default RO RW - 10h Register 16-45. (Offset 61h; PCIEXNEXT) PCI Express Next Capability Pointer Bit(s) Description CFG MM EE Default 7:0 PCI Express Next Capability Pointer Points to the first location of the next item in the New Capabilities Linked List. RO RW WO 0h Register 16-46. (Offset 62h; PCIEXCAP) PCI Express Capabilities Bit(s) Description CFG MM EE Default 3:0 Capability Version Indicates the PCI Express capability structure version number. RO RW WO 1h 7:4 Device/Port Type Indicates the type of PCI Express logical device. 0000b = PCI Express Endpoint Device 0001b = Legacy PCI Express Endpoint Device 0100b = Root Port of PCI Express Root Complex 0101b = Upstream Port of PCI Express Switch 0110b = Downstream Port of PCI Express Switch 0111b = PCI Express-to-PCI/PCI-X Bridge 1000b = PCI/PCI-X-to-PCI Express Bridge All other values are reserved. RO RW WO 1000b Slot Implemented 1 = Indicates that the PCI Express Link associated with this port is connected to a slot RO RW WO 0 13:9 Interrupt Message Number When this function is allocated more than one MSI interrupt number, this field must contain the offset between the Base Message data and the MSI message generated when Slot Status or Root Status register status bits of this capability structure are set. For the field to be correct, hardware must update it when the number of MSI messages assigned to the PEX 8111 changes. RO RO - 0h 15:14 Reserved RsvdP RsvdP - 00b 8 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 209 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-47. (Offset 64h; DEVCAP) Device Capabilities Bit(s) 2:0 Description Maximum Payload Size Supported Indicates the Maximum Payload Size that the PEX 8111 supports for TLPs. 000b = 128 bytes All other values are reserved. CFG MM EE Default RO RO - 000b RO RO - 00b RO RW WO 0 RO RW WO 000b Note: Because the PEX 8111 supports a Maximum Payload Size of only 128 bytes, this field is hardwired to 000b. 4:3 5 Phantom Functions Supported Not supported. Hardwired to 00b. This field indicates support for the use of unclaimed Function Numbers to extend the number of outstanding transactions allowed, by logically combining unclaimed Function Numbers (called Phantom Functions) with the Tag identifier. Extended Tag Field Supported Indicates the maximum supported size of the Tag field. 0 = 5-bit Tag field is supported 1 = 8-bit Tag field is supported Note: 8-bit Tag field support must be enabled by the corresponding Control field in the PCI Express Device Control register. 8:6 210 Endpoint L0s Acceptable Latency Indicates the acceptable total latency that an Endpoint withstands due to the transition from the L0s state to the L0 state. It is essentially an indirect measure of the Endpoint internal buffering. Power management software uses the reported L0s Acceptable Latency number to compare against the L0s exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port, to determine whether Active State Link PM L0s entry is used with no performance loss. 000b = Less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = More than 4 s PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-47. (Offset 64h; DEVCAP) Device Capabilities (Cont.) Bit(s) Description CFG MM EE Default 11:9 Endpoint L1 Acceptable Latency Indicates the acceptable total latency that an Endpoint withstands due to the transition from the L1 state to the L0 state. It is essentially an indirect measure of the Endpoint internal buffering. Power management software uses the report L1 Acceptable Latency number to compare against the L1 exit latencies reported by all components comprising the data path from this Endpoint to the Root Complex Root Port, to determine whether Active State Link PM L1 entry is used with performance loss. 000b = Less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = More than 64 s RO RW WO 000b 12 Attention Button Present Not supported. Forced to 0. RO RO - 0 13 Attention Indicator Present. Not supported. Forced to 0. RO RO - 0 14 Power Indicator Present Not supported. Forced to 0. RO RO - 0 RsvdP RsvdP - 000b 17:15 Reserved 25:18 Captured Slot Power Limit Value Specifies the upper limit on power supplied by slot in combination with the Slot Power Limit Scale value. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. Value is set by the Set Slot Power Limit message. RO RW WO 0h 27:26 Captured Slot Power Limit Scale Specifies the scale used for the Slot Power Limit Value. Value is set by the Set Slot Power Limit message. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x RO RW WO 00b 31:28 Reserved RsvdP RsvdP - 0h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 211 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-48. (Offset 68h; DEVCTL) PCI Express Device Control Bit(s) Description CFG MM EE Default 0 Correctable Error Reporting Enable Does not apply to Reverse Bridge mode. RW RW WO 0 1 Non-Fatal Error Reporting Enable Does not apply to Reverse Bridge mode. RW RW WO 0 2 Fatal Error Reporting Enable Does not apply to Reverse Bridge mode. RW RW WO 0 3 Unsupported Request Reporting Enable Does not apply to Reverse Bridge mode. RW RW WO 0 4 Enable Relaxed Ordering Not supported. Forced to 0. 1 = PEX 8111 is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require Strong Write ordering RO RO - 0 7:5 Maximum Payload Size Sets the maximum TLP Payload Size for the PEX 8111. As a receiver, the PEX 8111 must handle TLPs as large as the set value; as transmitter, the PEX 8111 must not generate TLPs exceeding the set value. Permissible values for transmitted TLPs are indicated in the Device Capabilities register Maximum Payload Size Supported field. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved RW RW WO 000b 212 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-48. (Offset 68h; DEVCTL) PCI Express Device Control (Cont.) Bit(s) CFG MM EE Default RW RW WO 0 RO RO - 0 RO RO - 0 RO RO - 0 14:12 Maximum Read Request Size The value specified in this register is the upper boundary of the PCI Control register Programmed Prefetch Size field if the Device-Specific Control register Blind Prefetch Enable bit is set. Sets the Maximum Read Request Size for the PEX 8111 as a Requester. The PEX 8111 must not generate read requests with a size that exceeds the set value. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved RW RW WO 010b 15 Bridge Configuration Retry Enable 0 = PEX 8111 does not generate completions with Completion Retry Status on behalf of PCI Express-to-PCI Configuration transactions 1 = PEX 8111 generates completions with Completion Retry Status on behalf of PCI Express-to-PCI Configuration transactions RW RW WO 0 8 Description Extended Tag Field Enable 0 = PEX 8111 is restricted to a 5-bit Tag field 1 = Enables PEX 8111 to use an 8-bit Tag field as a requester Forced to 0 when the Device Capabilities register Extended Tag Field Supported bit is cleared. 9 Phantom Function Enable Not supported. Hardwired to 0. Auxiliary (AUX) Power PM Enable Not supported. Hardwired to 0. 1 = Enables a device to draw AUX power independent of PME AUX power 10 Devices that require AUX power on legacy operating systems must continue to indicate PME AUX power requirements. AUX power is allocated as requested in the Power Management Capabilities register AUX Current field, independent of the Power Management Control/Status register PME Enable bit. Enable No Snoop Not supported. Hardwired to 0. 1 = PEX 8111 is permitted to set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware-enforced cache coherency 11 Setting this bit to 1 does not cause a device to blindly set the No Snoop attribute on all transactions that it initiates. Although this bit is set to 1, a device only sets the No Snoop attribute on a transaction when it can guarantee that the transaction address is not stored in a system cache. The PEX 8111 never sets the No Snoop attribute; therefore, this bit is forced to 0. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 213 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-49. (Offset 6Ah; DEVSTAT) PCI Express Device Status Bit(s) CFG MM EE Default 0 Correctable Error Detected Does not apply to Reverse Bridge mode. RW1C RW1C - 0 1 Non-Fatal Error Detected Does not apply to Reverse Bridge mode. RW1C RW1C - 0 2 Fatal Error Detected Does not apply to Reverse Bridge mode. RW1C RW1C - 0 3 Unsupported Request Detected Does not apply to Reverse Bridge mode. RW1C RW1C - 0 4 AUX Power Detected Devices that require AUX power report this bit as set when the PEX 8111 detects AUX power. RO RO - 0 5 Transactions Pending Because the PEX 8111 does not internally generate Non-Posted transactions, this bit is forced to 0. RO RO - 0 RsvdZ RsvdZ - 0h 15:6 214 Description Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-50. (Offset 6Ch; LINKCAP) Link Capabilities Bit(s) Description CFG MM EE Default 3:0 Maximum Link Speed Indicates the maximum Link speed of the given PCI Express Link. Set to 0001b for 2.5 Gbps. All other values are reserved. RO RO - 0001b 9:4 Maximum Link Width Indicates the maximum width of the given PCI Express Link. By default, the PEX 8111 has an x1 link; therefore, this field is hardwired to 00_0001b. All other values are not supported. RO RO - 00_0001b 11:10 Active State Link PM Support Indicates the level of active state power management supported on the given PCI Express Link. 01b = L0s Entry supported 11b = L0s and L1 supported 00b, 10b = Reserved RO RW WO 11b 14:12 L0s Exit Latency Indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this port requires to complete transition from L0s to L0. 000b = Less than 64 ns 001b = 64 ns to less than 128 ns 010b = 128 ns to less than 256 ns 011b = 256 ns to less than 512 ns 100b = 512 ns to 1 s 101b = 1 s to less than 2 s 110b = 2 to 4 s 111b = More than 4 s RO RW WO 100b 17:15 L1 Exit Latency Indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this port requires to complete transition from L1 to L0. 000b = Less than 1 s 001b = 1 s to less than 2 s 010b = 2 s to less than 4 s 011b = 4 s to less than 8 s 100b = 8 s to less than 16 s 101b = 16 s to less than 32 s 110b = 32 to 64 s 111b = More than 64 s RO RW WO 100b 23:18 Reserved RsvdP RsvdP - 0h 31:24 Port Number Indicates the PCI Express port number for the given PCI Express Link. RO RW WO 0h PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 215 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-51. (Offset 70h; LINKCTL) Link Control Bit(s) 1:0 Description Active State Link PM Control Controls the level of active state PM supported on the given PCI Express Link. 00b = Disabled 01b = L0s Entry supported 10b = Reserved 11b = L0s and L1 Entry supported CFG MM EE Default RW RW WO 00b RsvdP RsvdP - 0 Note: "L0s Entry Enabled" indicates the Transmitter entering L0s. 2 Reserved 3 Read Completion Boundary (RCB) Control 0 = Read Completion boundary is 64 bytes 1 = Read Completion boundary is 128 bytes RO RW WO 0 4 Link Disable Disables the link when set to 1. Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state. RW RW WO 0 RW RW WO 0 6 Common Clock Configuration 0 = Indicates that the PEX 8111 and the component at the opposite end of the link are operating with asynchronous reference clock. Components utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies. 1 = Indicates that the PEX 8111 and the component at the opposite end of the link are operating with a distributed common reference clock. RW RW WO 0 7 Extended Sync 1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0. This mode provides external devices monitoring the link time to achieve bit and symbol lock before the link enters the L0 state and resumes communication. RW RW WO 0 RsvdP RsvdP - 0h 5 Retrain Link 1 = Initiates link retraining Always returns 0 when read. 15:8 216 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-52. (Offset 72h; LINKSTAT) Link Status Bit(s) Description CFG MM EE Default 3:0 Link Speed Indicates the negotiated Link speed of the given PCI Express Link. Set to 0001b for 2.5 Gbps. All other values are reserved. RO RO - 0001b 9:4 Negotiated Link Width Indicates the negotiated width of the given PCI Express Link. By default, the PEX 8111 has an x1 link; therefore, this field is hardwired to 00_0001b. All other values are not supported. RO RO - 00_0001b 10 Link Training Error Indicates that a Link Training error occurred. Cleared by hardware upon successful training of the link to the L0 state. RO RO - 0 11 Link Training Indicates that Link training is in progress; hardware clears this bit after Link training is complete. RO RO - 0 12 Slot Clock Configuration Indicates that the PEX 8111 uses the same physical reference clock that the platform provides on the connector. When the PEX 8111 uses an independent clock irrespective of the presence of a reference on the connector, this bit must be cleared. HwInit RW WO 0 Reserved RsvdZ RsvdZ - 000b 15:13 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 217 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-53. (Offset 74h; SLOTCAP) Slot Capabilities Bit(s) Description CFG MM EE Default 0 Attention Button Present Not supported. Forced to 0. RO RO - 0 1 Power Controller Present Not supported. Forced to 0. RO RO - 0 2 MRL Sensor Present Not supported. Forced to 0. RO RO - 0 3 Attention Indicator Present Not supported. Forced to 0. RO RO - 0 4 Power Indicator Present Not supported. Forced to 0. RO RO - 0 5 Hot Plug Surprise Not supported. Forced to 0. RO RO - 0 6 Hot Plug Capable Not supported. The PEX 8111 does not support Hot Plug operations; therefore, this bit is forced to 0. RO RO - 0 14:7 Slot Power Limit Value In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot. The Power Limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. Writes to this register cause the PEX 8111 to transmit the Set Slot Power Limit message downstream. RO RW WO 25d 16:15 Slot Power Limit Scale Specifies the scale used for the Slot Power Limit Value. Writes to this register cause the PEX 8111 to transmit the Set Slot Power Limit message downstream. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x RO RW WO 00b 18:17 Reserved RsvdP RsvdP - 00b 31:19 Physical Slot Number Not supported. Forced to 0h. RO RO - 0h 218 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-54. (Offset 78h; SLOTCTL) Slot Control Bit(s) Description CFG MM EE Default 0 Attention Button Pressed Enable Not supported. Forced to 0. RW RW WO 0 1 Power Fault Detected Enable Not supported. Forced to 0. RW RW WO 0 2 MRL Sensor Changed Enable Not supported. Forced to 0. RW RW WO 0 3 Presence Detect Changed Enable Not supported. Forced to 0. RW RW WO 0 4 Command Completed Interrupt Enable Not supported. Forced to 0. RW RW WO 0 5 Hot Plug Interrupt Enable Not supported. Forced to 0. RW RW WO 0 7:6 Attention Indicator Control Not supported. Forced to 0. RW RW WO 00b 9:8 Power Indicator Control Not supported. Forced to 00b. RW RW WO 00b 10 Power Controller Control Not supported. Forced to 0. RW RW WO 0 RsvdP RsvdP - 0h 15:11 Reserved Register 16-55. (Offset 7Ah; SLOTSTAT) Slot Status Bit(s) Description CFG MM EE Default 0 Attention Button Pressed Not supported. Forced to 0. RO RO - 0 1 Power Fault Detected Not supported. Forced to 0. RO RO - 0 2 MRL Sensor Changed Not supported. Forced to 0. RO RO - 0 3 Presence Detect Changed Not supported. Forced to 0. RO RO - 0 4 Command Completed Not supported. Forced to 0. RO RO - 0 5 MRL Sensor State Not supported. Forced to 0. RO RO - 0 6 Presence Detect State Not supported. Forced to 1. RO RO - 1 RsvdP RsvdP - 0h 15:7 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 219 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-56. (Offset 7Ch; ROOTCTL) Root Control Bit(s) CFG MM EE Default 0 System Error on Correctable Error Enable 1 = System error (SERR#) is generated when an ERR_COR is reported by devices in the hierarchy associated with this Root Port, or by the Root Port itself RW RW WO 0 1 System Error on Non-Fatal Error Enable 1 = System error (SERR#) is generated when an ERR_NONFATAL is reported by devices in the hierarchy associated with this Root Port, or by the Root Port itself RW RW WO 0 2 System Error on Fatal Error Enable 1 = System error (SERR#) is generated when an ERR_FATAL is reported by devices in the hierarchy associated with this Root Port, or by the Root Port itself RW RW WO 0 3 PME Interrupt Enable 1 = Enables PME interrupt generation upon PME message receipt as reflected in the Root Status register PME Status bit. A PME interrupt is also generated when the PME Status bit is set when this bit is set from a cleared state. RW RW WO 0 RsvdP RsvdP - 0h CFG MM EE Default RO RO - - 16 PME Status Indicates that PME was asserted by the Requester ID indicated in the PME Requester ID field. Subsequent PMEs remain pending until this bit is cleared by software, by writing 1. RW1C RW1C - 0 17 PME Pending Indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software, the PME is delivered by hardware by setting the PME Status bit again and updating the Requester ID appropriately. Cleared by hardware when no other PMEs are pending. RO RO - - RsvdP RsvdP - 0h 31:4 Description Reserved Register 16-57. (Offset 80h; ROOTSTAT) Root Status Bit(s) 15:0 31:18 220 Description PME Requester ID Indicates the PCI Requester ID of the last PME requester. Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI-Compatible Extended Capability Registers for PCI Express Interface Register 16-58. (Offset 84h; MAININDEX) Main Control Register Index Bit(s) Description 11:0 Main Control Register Index Selects a Main Control register that is accessed by way of the Main Control Register Data register. 31:12 Reserved CFG MM EE Default RW RW WO 0h RsvdP RsvdP - 0h CFG MM EE Default RW RW WO 0h Register 16-59. (Offset 88h; MAINDATA) Main Control Register Data Bit(s) 31:0 Description Main Control Register Data Writes to and reads from this register are mapped to a Main Control register selected by the Main Control Register Index register. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 221 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. 16.8 PCI Express Extended Capability Registers 16.8.1 PCI Express Power Budgeting Registers Register 16-60. (Offset 100h; PWRCAPHDR) Power Budgeting Capability Header Bit(s) Description CFG MM EE Default 15:0 PCI Express Extended Capability ID PCI-SIG-defined ID Number that indicates the nature and format of the extended capability. RO RW WO 4h 19:16 Capability Version PCI-SIG-defined Version Number that indicates the version of the capability structure present. RO RW WO 1h 31:20 Next Capability Offset Contains the offset to the next PCI Express capability structure, or 000h when no other items exist in the New Capabilities Linked List. Set to 110h when Serial Number Capability must be enabled. RO RW WO 000h CFG MM EE Default RW RW WO 0h RsvdP RsvdP - 0h Register 16-61. (Offset 104h; PWRDATASEL) Power Budgeting Data Select Bit(s) Description 7:0 Data Select Register Indexes the Power Budgeting Data reported through the Power Budgeting Data register. Selects the DWORD of Power Budgeting Data that is to appear in the Power Budgeting Data register. The PEX 8111 supports values from 0 to 31 for this field. For values greater than 31, a value of 0h is returned when the Power Budgeting Data register is read. 31:8 Reserved 222 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCI Express Power Budgeting Registers Register 16-62 returns the DWORD of Power Budgeting Data selected by the Power Budgeting Data Select register. When the Power Budgeting Data Select register contains a value greater than or equal to the number of operating conditions for which the PEX 8111 provides power information, this register returns all zeros (0). The PEX 8111 supports 32 operating conditions. Register 16-62. (Offset 108h; PWRDATA) Power Budgeting Data Bit(s) Description CFG MM EE Default 7:0 Base Power Specifies (in Watts) the base power value in the given operating condition. This value must be multiplied by the Data Scale, to produce the actual power consumption value. RO RW WO 0h 9:8 Data Scale Specifies the scale to apply to the Base Power value. The PEX 8111 power consumption is determined by multiplying the Base Power field contents with the value corresponding to the encoding returned by this field. 00b = 1.0x 10b = 0.01x 01b = 0.1x 11b = 0.001x RO RW WO 00b 12:10 PM Sub-State Specifies the power management sub-state of the operating condition being described. 000b = Default Sub-State All other values = Device-Specific Sub-State RO RW WO 000b 14:13 PM State Specifies the power management state of the operating condition being described. A device returns 11b in this field and Aux or PME Aux in the PM Type field to specify the D3cold PM state. An encoding of 11b along with any other PM Type field value specifies the D3hot state. 00b = D0 10b = D2 01b = D1 11b = D3 RO RW WO 00b 17:15 PM Type Specifies the type of operating condition being described. 000b = PME Aux 011b = Sustained 001b = Auxiliary 111b = Maximum 010b = Idle All other values = Reserved RO RW WO 000b 20:18 Power Rail Specifies the power rail of the operating condition being described. 000b = Power (12V) 111b = Thermal 001b = Power (3.3V) All other values = Reserved 010b = Power (1.8V) RO RW WO 000b 31:21 Reserved RsvdP RsvdP - 0h CFG MM EE Default RO RW WO 0 RsvdP RsvdP - 0h Register 16-63. (Offset 10Ch; PWRBUDCAP) Power Budget Capability Bit(s) 0 31:1 Description System Allocated 1 = Indicates that the PEX 8111 power budget is included within the system power budget, and software is to ignore Reported Power Budgeting Data for power budgeting decisions Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 223 Reverse Bridge Mode Configuration Registers 16.8.2 PLX Technology, Inc. PCI Express Serial Number Registers Register 16-64. (Offset 110h; SERCAPHDR) Serial Number Capability Header Bit(s) Description CFG MM EE Default 15:0 PCI Express Extended Capability ID PCI-SIG-defined ID Number that indicates the nature and format of the extended capability. Forced to 0 when Serial Number Capability is disabled. RO RO - 3h 19:16 Capability Version PCI-SIG-defined Version Number that indicates the version of the capability structure present. Forced to 0h when Serial Number Capability is disabled. RO RO - 1h 31:20 Next Capability Offset Contains the offset to the next PCI Express capability structure or 000h when no other items exist in the New Capabilities Linked List. RO RO - 000h Register 16-65. (Offset 114h; SERNUMLOW) Serial Number Low (Lower DWORD) Bit(s) 31:0 Description PCI Express Device Serial Number Contains the lower DWORD of the IEEE-defined 64-bit extended unique identifier. Includes a 24-bit Company ID value assigned by the IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. Forced to 0h when Serial Number Capability is disabled. CFG MM EE Default RO RW WO 0h CFG MM EE Default RO RW WO 0h Register 16-66. (Offset 118h; SERNUMHI) Serial Number Hi (Upper DWORD) Bit(s) 31:0 224 Description PCI Express Device Serial Number Contains the upper DWORD of the IEEE defined 64-bit extended unique identifier. Includes a 24-bit Company ID value assigned by the IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. Forced to 0h when Serial Number Capability is disabled. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 16.9 Main Control Registers Main Control Registers Register 16-67. (Offset 1000h; DEVINIT) Device Initialization Bit(s) 3:0 4 5 Description CFG MM PCLKO Clock Frequency Controls the PCLKO ball frequency. When cleared to 0000b, the clock is stopped and remains at a logic low (0V) DC value. Non-zero values represent divisors of the 100-MHz REFCLK. The default value is 0011b, representing a frequency of 66 MHz. 0000b = 0 0001b = 100 0010b = 50 0011b = 33.3/66 (When M66EN is high, PCLKO frequency is 66 MHz) 0100b = 25 0101b = 20 0110b = 16.7 0111b = 14.3 1000b = 12.5 1001b = 11.1 1010b = 10 1011b = 9.1 1100b = 8.3 1101b = 7.7 1110b = 7.1 1111b = 6.7 RW 0011b PCI Express Enable Does not apply to Reverse Bridge mode. RW 0 RW 0 RsvdP 0h PCI Enable 0 = All PCI accesses to the PEX 8111 result in a Target Retry response 1 = PEX 8111 responds normally to PCI accesses Automatically set when a valid serial EEPROM is not detected. 31:6 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 225 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-68. (Offset 1004h; EECTL) Serial EEPROM Control Bit(s) Description CFG MM 7:0 Serial EEPROM Write Data Determines the byte written to the serial EEPROM when the Serial EEPROM Byte Write Start bit is set. Represents an opcode, address, or data being written to the serial EEPROM. RW 0h 15:8 Serial EEPROM Read Data Determines the byte read from the serial EEPROM when the Serial EEPROM Byte Read Start bit is set. RO - RW 0 RW 0 RW 0 RO 0 16 Serial EEPROM Byte Write Start 1 = Value in the Serial EEPROM Write Data field is written to the serial EEPROM Automatically cleared when the Write operation is complete. 17 Serial EEPROM Byte Read Start 1 = A byte is read from the serial EEPROM, and accessed using the Serial EEPROM Read Data field Automatically cleared when the Read operation is complete. 18 19 Serial EEPROM Chip Select Enable 1 = Serial EEPROM Chip Select is enabled Serial EEPROM Busy 1 = Serial EEPROM Controller is busy performing a Byte Read or Write operation An interrupt is generated when this bit goes false. 20 Serial EEPROM Valid 1 = Serial EEPROM with 5Ah in the first byte is detected RO - 21 Serial EEPROM Present Set when the Serial EEPROM Controller determines that a serial EEPROM is connected to the PEX 8111. RO - 22 Serial EEPROM Chip Select Active Set when the EECS# ball to the serial EEPROM is active. The Chip Select can be active across multiple byte operations. RO - 24:23 Serial EEPROM Address Width Reports the installed serial EEPROM's addressing width. When the addressing width cannot be determined, 00b is returned. A non-zero value is reported only when the validation signature (5Ah) is successfully read from the first serial EEPROM location. 00b = Undetermined 01b = 1 byte 10b = 2 bytes 11b = 3 bytes RO - 30:25 Reserved RsvdP 0h RW 0 31 226 Serial EEPROM Reload Writing 1 to this bit causes the Serial EEPROM Controller to perform an initialization sequence. Configuration registers and shared memory are loaded from the serial EEPROM. Reading this bit returns 0 while initialization is in progress, and 1 when initialization is complete. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-69. (Offset 1008h; EECLKFREQ) Serial EEPROM Clock Frequency Bit(s) Description 2:0 Serial EEPROM Clock Frequency Controls the EECLK ball frequency. 000b = 2 MHz 001b = 5 MHz 010b = 8.3 MHz 011b = 10 MHz 100b = 12.5 MHz 101b = 16.7 MHz 110b = 25 MHz 111b = Reserved 31:3 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Access Default RW 000b RsvdP 0h 227 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-70. (Offset 100Ch; PCICTL) PCI Control Bit(s) Access Default PCI Multi-Level Arbiter 0 = All PCI requesters are placed into a single-level Round-Robin arbiter, each with equal access to the PCI Bus 1 = Two-level arbiter is selected RW 0 PCI Arbiter Park Select Determines which PCI master controller is granted the PCI Bus when there are no pending requests. 000b = Last grantee 001b = PCI Express interface 010b, 011b = Reserved 100b = External Requester 0 101b = External Requester 1 110b = External Requester 2 111b = External Requester 3 RW 000b 4 Bridge Mode Reflects the FORWARD ball status. When low, the PEX 8111 operates as a Reverse Bridge (PCI-to-PCI Express). When high, the PEX 8111 operates as a Forward Bridge (PCI Express-to-PCI). RO - 5 PCI External Arbiter Reflects the EXTARB ball state. When low, the PEX 8111 enables its internal arbiter. It then expects external requests on REQ[3:0]# and issues bus grants on GNT[3:0]#. When high, the PEX 8111 asserts REQ0# and expects GNT0# from an external arbiter. RO - 6 Locked Transaction Enable The PCI LOCK# ball is ignored. 1 = Locked transactions are propagated through the PEX 8111 from the primary to secondary bus RW 0 7 M66EN Reflects the M66EN ball state. When low, the PEX 8111 PCI Bus is operating at 33 MHz. When high, the PEX 8111 PCI Bus is operating at 66 MHz. RO 0 RW 80h RW 0h 0 3:1 15:8 Description PCI-to-PCI Express Retry Count Valid only when the PCI Express link is down. Determines the number of times to Retry a PCI Type 1 Configuration transaction to PCI Express before aborting the transfer (in units of 214 Retries). 0h = Indicates that the transaction is Retried forever 255 = Selects a Retry count of 224 When the timer times out, a Master Abort is returned to the PCI Bus. 23:16 PCI Express-to-PCI Retry Count Determines the number of times to Retry a PCI Express-to-PCI transaction before aborting the transfer (in units of 24 Retries). 0h = Indicates that the transaction is Retried forever 255 = Selects a Retry count of 224 228 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-70. (Offset 100Ch; PCICTL) PCI Control (Cont.) Bit(s) Description Access Default 24 Memory Read Line Enable 0 = PEX 8111 issues a Memory Read command for transactions that do not start on a Cache boundary. 1 = Memory Read Line command is issued when a transaction is not aligned to a Cache boundary in Prefetchable Address space, and the Burst Transfer Size is at least one Cache Line of data. The PCI burst is stopped at the Cache Line boundary when the Burst Transfer Size is less than one Cache Line of data or when a Memory Read Multiple command is started. RW 1 25 Memory Read Multiple Enable 0 = PEX 8111 issues a Memory Read command for transactions that start on a Cache boundary. 1 = Memory Read Multiple command is issued when a transaction is aligned to a Cache boundary in Prefetchable Address space, and the Burst Transfer Size is at least one Cache Line of data. The PCI burst continues when the Burst Transfer Size remains greater than or equal to one Cache Line of data. RW 1 RW 0 RW 000b RsvdP 00b 26 Early Byte Enables Expected 0 = PEX 8111 expects PCI Bytes Enables to be valid after IRDY# is asserted 1 = PEX 8111 expects the PCI Byte Enables to be valid in the clock tick following the Address phase For maximum compatibility with non-compliant PCI devices, clear this bit to 0. For maximum performance, set this bit to 1. 29:27 Programmed Prefetch Size Valid only for Memory Read Line and Memory Read Multiple transactions, or Memory Read transactions accessing Prefetchable Memory space with the Device-Specific Control register Blind Prefetch Enable bit set. Determines the number of bytes requested from the PCI Express interface as a result of a PCIto-PCI Express read. If a Prefetch size is specified, the Cache Line boundary requirements of the Memory Read Line and Memory Read Multiple commands are disabled and the number of bytes requested will match the Prefetch Size. Enable feature only when the PCI initiator reads all requested data without disconnecting. Otherwise, performance is impacted. The Prefetch Size is limited by the PCI Express Device Control register Maximum Read Request Size field. 000b = Disabled 001b = 64 bytes 010b = 128 bytes 011b = 256 bytes 100b = 512 bytes 101b = 1,024 bytes 110b = 2,048 bytes 111b = 4,096 bytes (4 KB; refer to Note) Note: If the Programmed Prefetch Size is 4 KB, the TLP Controller Configuration 0 register Limit Completion Flow Control Credit bit must be set. 31:30 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 229 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-71. (Offset 1014h; PCIIRQENB) PCI Interrupt Request Enable Bit(s) 0 Description Serial EEPROM Done Interrupt Enable 1 = Enables a PCI interrupt to be generated when a Serial EEPROM Read or Write transaction completes Access Default RW 0 RW 0 RsvdP 0 Note: Refer to Section 5.2, "Reverse Bridge PCI Interrupts," for further details. 1 GPIO Interrupt Enable 1 = Enables a PCI interrupt to be generated when an interrupt is active from one of the GPIO balls 2 Reserved 3 PCI Express-to-PCI Retry Interrupt Enable 1 = Enables a PCI interrupt to be generated when the PCI Express-to-PCI Retry count is reached RW 0 4 Mailbox 0 Interrupt Enable 1 = Enables a PCI interrupt to be generated when Mailbox 0 is written RW 0 5 Mailbox 1 Interrupt Enable 1 = Enables a PCI interrupt to be generated when Mailbox 1 is written RW 0 6 Mailbox 2 Interrupt Enable 1 = Enables a PCI interrupt to be generated when Mailbox 2 is written RW 0 7 Mailbox 3 Interrupt Enable 1 = Enables a PCI interrupt to be generated when Mailbox 3 is written RW 0 8 Unsupported Request Interrupt Enable 1 = Enables a PCI interrupt to be generated when an Unsupported Request Completion response is received from the PCI Express RW 0 RsvdP 0h RW 1 30:9 31 Reserved PCI Internal Interrupt Enable 1 = Enables a PCI interrupt to be generated as a result of an internal PEX 8111 interrupt source Note: Refer to Section 5.2, "Reverse Bridge PCI Interrupts," for further details. 230 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-72. (Offset 1018h; IRQSTAT) Interrupt Request Status Bit(s) Description Access Default RW1C 0 RO 0 0 Serial EEPROM Done Interrupt Set when a Serial EEPROM Read or Write transaction completes. Writing 1 clears this status bit. 1 GPIO Interrupt Conveys the interrupt status for the four GPIO balls. Set independently of the GPIO Interrupt Enable bits. This bit is an OR of the four individual GPIO status bits. 1 = General-Purpose I/O Status register is read to determine the cause of the interrupt 2 Reserved RsvdP 0 3 PCI Express-to-PCI Retry Interrupt Set when the PCI Express-to-PCI Retry count is reached. Writing 1 clears this status bit. RW1C 0 4 Mailbox 0 Interrupt Set when Mailbox 0 is written. Writing 1 clears this bit. RW1C 0 5 Mailbox 1 Interrupt Set when Mailbox 1 is written. Writing 1 clears this bit. RW1C 0 6 Mailbox 2 Interrupt Set when Mailbox 2 is written. Writing 1 clears this bit. RW1C 0 7 Mailbox 3 Interrupt Set when Mailbox 3 is written. Writing 1 clears this bit. RW1C 0 8 Unsupported Request Interrupt Set when an Unsupported Request Completion is received from the PCI Express interface, provided that the PCI Interrupt Request Enable register Unsupported Request Interrupt Enable bit is set. RW1C 0 Reserved RsvdZ 0h 31:9 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 231 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-73. (Offset 1020h; GPIOCTL) General-Purpose I/O Control Bit(s) Access Default 0 GPIO0 Data When programmed as an output, values written to this bit appear on the GPIO0 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO0 ball. RW 0 1 GPIO1 Data When programmed as an output, values written to this bit appear on the GPIO1 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO1 ball. RW 0 2 GPIO2 Data When programmed as an output, values written to this bit appear on the GPIO2 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO2 ball. RW 0 3 GPIO3 Data When programmed as an output, values written to this bit appear on the GPIO3 ball. Reading this bit returns the value that was previously written. When programmed as an input, reading this bit returns the value present on the GPIO3 ball. RW 0 4 GPIO0 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO0 ball is an input 1 = GPIO0 ball is an output RW 1 5 GPIO1 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO1 ball is an input 1 = GPIO1 ball is an output RW 0 6 GPIO2 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO2 ball is an input 1 = GPIO2 ball is an output RW 0 7 GPIO3 Output Enable The GPIO Diagnostic Select field overrides this bit when a diagnostic output is selected. 0 = GPIO3 ball is an input 1 = GPIO3 ball is an output RW 0 8 GPIO0 Interrupt Enable 1 = Changes on the GPIO0 ball (when programmed as an input) are enabled to generate an interrupt RW 0 9 GPIO1 Interrupt Enable 1 = Changes on the GPIO1 ball (when programmed as an input) are enabled to generate an interrupt RW 0 10 GPIO2 Interrupt Enable 1 = Changes on the GPIO2 ball (when programmed as an input) are enabled to generate an interrupt RW 0 11 GPIO3 Interrupt Enable 1 = Changes on the GPIO3 ball (when programmed as an input) are enabled to generate an interrupt RW 0 232 Description PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-73. (Offset 1020h; GPIOCTL) General-Purpose I/O Control (Cont.) Bit(s) Description Access Default RW 01b RsvdP 0h GPIO Diagnostic Select Selects diagnostic signals that are output on the GPIO balls. 00b = Normal GPIO operation 01b = GPIO0 driven high when Link is up. GPIO[3:1] operate according to the configuration specified by bits [7:5] of this register 10b = GPIO[3:0] driven with lower four bits of the LTSSM state machine for 2 seconds, alternating with GPIO[1:0] driven with the upper two bits of the LTSSM state machine for 1s 11b = GPIO[3:0] driven with PMU Linkstate (L2, L1, L0s, and L0) 13:12 31:14 LTSSM Codes 00h - L3_L2 (Fundamental Reset) 01h - Detect 02h - Polling.Active 03h - Polling.Configuration 04h - Polling.Compliance 05h - Configuration.Linkwidth.Start & Accept 06h - Configuration.Lanenum.Wait & Accept 07h - Configuration.Complete 08h - Configuration.Idle 09h - Reserved 0Ah - Reserved 0Bh - Reserved 0Ch - Reserved 0Dh - Reserved 0Eh - L0 0Fh - L0 (Transmit E.I.Ordered-set) 10h - L0 (Wait E.I.Ordered-set) 12h - L1.Idle 14h - L2.Idle 15h - Recovery.Rcvrlock (Extended Sync enabled) 16h - Recovery.Rcvrlock 17h - Recovery.RcvrCfg 18h - Recovery.Idle 19h - Disabled (Transmit TS1) 1Ah - Disabled (Transmit E.I.Ordered-set) 1Dh - Disabled (Wait Electrical Idle) 1Eh - Disabled (Disable) 1Fh - Loopback.Entry 20h - Loopback.Active 21h - Loopback.Exit 22h - Hot Reset (Wait TS1 with Hot Reset) 23h - Hot Reset (Reset Active) 24h - Loopback.Actice (Transmit E.I.Ordered-set) 25h - Loopback.Active (Wait Electrical Idle) Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 233 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-74. (Offset 1024h; GPIOSTAT) General-Purpose I/O Status Bit(s) Description Access Default 0 GPIO0 Interrupt Set when the GPIO0 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 1 GPIO1 Interrupt Set when the GPIO1 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 2 GPIO2 Interrupt Set when the GPIO2 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 3 GPIO3 Interrupt Set when the GPIO3 ball state changes and the ball is programmed as an input. Writing 1 clears this bit. RW1C 0 Reserved RsvdZ 0h 31:4 Register 16-75. (Offset 1030h; MAILBOX0) Mailbox 0 Bit(s) 31:0 Description Access Default RW FEEDFACEh Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. Register 16-76. (Offset 1034h; MAILBOX1) Mailbox 1 Bit(s) 31:0 Description Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. Access Default RW 0h Access Default RW 0h Access Default RW 0h Register 16-77. (Offset 1038h; MAILBOX2) Mailbox 2 Bit(s) 31:0 Description Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. Register 16-78. (Offset 103Ch; MAILBOX3) Mailbox 3 Bit(s) 31:0 234 Description Mailbox Data Written or read from the PCI Express or PCI Bus. Interrupts are generated to the PCI Express interface or PCI Bus when this register is written. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-79. (Offset 1040h; CHIPREV) Chip Silicon Revision Bit(s) Description 15:0 Chip Revision Returns the PEX 8111 current Silicon Revision number. 31:16 Reserved Access Default RO Current Revision RsvdP 0h Note: CHIPREV is the Silicon Revision, encoded as a 4-digit BCD value. The CHIPREV value for the third release of the chip (Rev. BB) is 0201h. The least-significant digit is incremented for mask changes, and the most-significant digit is incremented for major revisions. Register 16-80. (Offset 1044h; DIAGCTL) Diagnostic Control (Factory Test Only) Bit(s) 0 1 Description Fast Times Factory Test Only. Force PCI Interrupt 1 = Forces the PCI INTx# interrupt signal to assert. The PCI Interrupt Pin register determines which INTx# signal is asserted. Access Default RW 0 RW 0 Effective only when the PCI Command register Interrupt Disable bit is low. 2 Force PCI SERR 1 = Forces the PCI SERR# interrupt signal to assert when the PCI Command register SERR# Enable bit is set RW 0 3 Force PCI Express Interrupt 1 = Forces an interrupt to the PCI Express Root Complex, using Message Signaled interrupts or virtual INTx# interrupts RW 0 RsvdP 0h 31:4 Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 235 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-81. (Offset 1048h; TLPCFG0) TLP Controller Configuration 0 Bit(s) Access Default CFG_NUM_FTS Forced NUM_FTS signal. NUM_FTS represents the number of Fast Training sequence (0 to 255). Refer to the PCI Express r1.0a, Section 4.2.4.3, for detailed information. RW 20h 8 CFG_ACK_FMODE PCI Express interface ACK_DLLP transmitting interval mode. 0 = PCI Express interface uses own interval value 1 = PCI Express interface uses CFG_ACK_COUNT as interval value RW 0 9 CFG_TO_FMODE PCI Express interface Timeout detection mode for replay timer. 0 = PCI Express interface uses own timer value 1 = PCI Express interface uses CFG_TO_COUNT as timer value RW 0 10 CFG_PORT_DISABLE 1 = SerDes in the PCI Express interface is disabled. This allows the endpoint to disable the PCI Express connection when powered up or before the configuration is completed. RW 0 11 CFG_RCV_DETECT Set when the PCI Express interface establishes the PCI Express connection. RO 0 12 CFG_LPB_MODE Link Loop-Back mode. 1 = PEX 8111 changes its LTSSM state to the Loop-Back state, becomes the Loop-Back master, and starts transmitting packets of pseudo random numbers RW 0 13 CFG_PORT_MODE 0 = Link PCI Express interface is configured as an upstream port (Endpoint) 1 = Link PCI Express interface is configured as a downstream port (Root Complex) RW 1 14 Reserved RsvdP 0 15 CFG_ECRC_GEN_ENABLE 1 = Link is allowed generate ECRC RW 0 7:0 Description The PEX 8111 does not support ECRC; therefore, this bit is cleared to 0. 236 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-81. (Offset 1048h; TLPCFG0) TLP Controller Configuration 0 (Cont.) Bit(s) Access Default 16 TLP_CPLD_NOSUCCESS_MALFORM_ENABLE 0 = Received completion is retained 1 = Completion received when completion timeout expired is treated as a malformed TLP and discarded RW 1 17 Scrambler Disable 0 = Data scrambling is enabled. 1 = Data scrambling is disabled. Set only when testing and debugging. RW 0 RW 0 19 Decode Primary Bus Number 0 = PEX 8111 ignores the Primary Bus Number in a PCI Express Type 0 Configuration Request. 1 = PEX 8111 compares the Primary Bus Number in a PCI Express Type 0 Configuration Request with the Primary Bus Number register. When they match, the request is accepted. Otherwise, an Unsupported Request is returned. This comparison occurs only after the first Type 0 Configuration write occurs. RW 0 20 Ignore Function Number 0 = PEX 8111 only responds to Function Number 0 during a Type 0 Configuration transaction. Accesses to other function numbers result in an Unsupported Request (PCI Express) or Master Abort (PCI). 1 = PEX 8111 ignores the Function Number in a PCI or PCI Express Type 0 Configuration request, and responds to all eight functions. RW 0 21 Check RCB Boundary 0 = PEX 8111 ignores Read Completion Boundary (RCB) violations 1 = PEX 8111 checks for RCB violations. When detected, the PEX 8111 treats it as a malformed TLP (packet is dropped and a Non-Fatal Error message is transmitted) RW 0 RW 0 RW 1 RsvdP 0h 18 Description Delay Link Training 0 = Link training is allowed to commence immediately after PCIRST# is de-asserted 1 = Link training is delayed for 12 ms after PCIRST# is de-asserted When GPIO3 is low at the trailing edge of reset, this bit is automatically set. Because this bit is used during link training, it must be set by driving GPIO3 low during PCIRST# assertion. 22 Limit Completion Flow Control Credit 0 = PEX 8111 advertises infinite flow control credits for completions 1 = PEX 8111advertises completion flow control credits, based on available buffer storage Must be set when the PCI Control register Programmed Prefetch Size field is set to 4 KB. When GPIO2 is low at the trailing edge of PCIRST#, this bit is automatically set. Because this bit is used during link training, it must be set by driving GPIO2 low during PCIRST# assertion. 23 31:24 L2 Secondary Bus Reset When clear and the PEX 8111 remains in the L2/L3 Ready state, PCI-to-PCI Express Configuration transactions are Retried until the PCI Control register PCI-to-PCI Express Retry Count expires. The PEX 8111 responds with a Master Abort. When set, and the PEX 8111 remains in the L2/L3 Ready state, PCI-to-PCI Express Configuration transactions result in a secondary bus reset. After the link training completes, the PCI-to-PCI Express Configuration transaction completes normally. Reserved PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 237 Reverse Bridge Mode Configuration Registers PLX Technology, Inc. Register 16-82. (Offset 104Ch; TLPCFG1) TLP Controller Configuration 1 Bit(s) Description Access Default 20:0 CFG_TO_COUNT PCI Express interface Replay Timer timeout value when CFG_TO_FMODE is set to 1. RW D4h 30:21 CFG_ACK_COUNT PCI Express interface ACK DLLP transmitting interval value when CFG_ACK_FMODE is set to 1. RW 0h RsvdP 0 31 Reserved Register 16-83. (Offset 1050h; TLPCFG2) TLP Controller Configuration 2 Bit(s) Description Access Default 15:0 CFG_COMPLETER_ID0 Bits [15:8] = Bus Number Bits [7:3] = Device Number Bits [2:0] = Function Number The Bus, Device, and Function Numbers of a Configuration transaction to the PEX 8111 are latched in this register. The latched values are then used when generating the completion. RW 0h 26:16 Update Credit FC Controls a counter that determines the gap between UpdateFC DLLPs (in units of 62.5 MHz clocks = 16 ns = 4 symbol times). When data or headers are read from the TLP Controller, the Credit Allocation Manager transmits a set of UpdateFC DLLPs; posted, non-posted, and completion when the TLP Controller Configuration 0 register Limit Completion Flow Control Credit bit is set. While transmitting the set of DLLPs, the Credit Allocation Manager uses the counter value to insert gaps between the DLLPs. The Bus, Device, and Function Numbers of a Configuration transaction to the PEX 8111 are latched in this register. The latched values are then used when generating the completion. RW 1h 31:27 Reserved RsvdP 0h Register 16-84. (Offset 1054h; TLPTAG) TLP Controller Tag Bit(s) Description Access Default 7:0 TAG BME1 Message Request Tag field. RW 0h 15:8 TAG ERM Error Manager Tag field. RW 0h 23:16 TAG PME Power Manager Tag field. RW 0h 31:24 Reserved RsvdP 0h 238 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Main Control Registers Register 16-85. (Offset 1058h; TLPTIMELIMIT0) TLP Controller Time Limit 0 Bit(s) Description Access Default 23:0 BME_COMPLETION_TIMEOUT_LIMIT Bus master engine completion timeout (in PCI clock units). The default value produces a 10-ms timeout. RW 51615h (M66EN low) A2C2Ah (M66EN high) 27:24 L2L3_PWR_REMOVAL_TIME_LIMIT Determines length of time before power is removed after entering the L2 state. Value to be at least 100 ns. Contains PCI clock units. RW 4h (M66EN low) 8h (M66EN high) 31:28 Reserved RsvdP 0h Register 16-86. (Offset 105Ch; TLPTIMELIMIT1) TLP Controller Time Limit 1 Bit(s) Description Access Default 10:0 ASPM_LI_DLLP_INTERVAL_TIME_LIMIT Determines time interval between two consecutive PM_ACTIVE_STATE_REQUEST_L1 DLLP transmissions. The default is 10 s for both 14Dh and 29Ah. Allow at least 10 s spent in LTSSM L0 and L0s state before the next PM_ACTIVE_STATE_REQUEST_L1 DLLP is transmitted. Refer to the PCI Express r1.0a Errata, page 19, for detailed information. Contains PCI clock units. RW 14Dh (M66EN low) 29Ah (M66EN high) 31:11 Reserved RsvdP 0h Register 16-87. (Offset 1064h; ECFGADDR) Enhanced Configuration Address Bit(s) Description Access Default RsvdP 0h 11:0 Reserved 14:12 Configuration Function Number Provides the Function Number for an enhanced Configuration transaction. RW 000b 19:15 Configuration Device Number Provides the Device Number for an enhanced Configuration transaction. RW 0h 27:20 Configuration Bus Number Provides the Bus Number for an enhanced Configuration transaction. RW 0h 30:28 Reserved RsvdP 000b RW 0 31 Enhanced Configuration Enable 0 = Accesses to the Base Address 0 register, offset 2000h, are not responded to by the PEX 8111 1 = Accesses to the Base Address 0 register, offset 2000h, are forwarded to the PCI Express interface as a Configuration Request PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 239 Reverse Bridge Mode Configuration Registers 240 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 17 17.1 Shared Memory Overview The PEX 8111 contains a 2 KB x 32-bit (8-KB) memory block that is accessed from the serial EEPROM, PCI Express interface, or PCI Bus. 17.2 Serial EEPROM Accesses When the Shared Memory Load bit in the Serial EEPROM Format byte is set, the shared memory is loaded from the serial EEPROM starting at location REG BYTE COUNT + 6. The number of bytes to load is determined by the value in serial EEPROM locations REG BYTE COUNT + 4 and REG BYTE COUNT + 5. The serial EEPROM data is always loaded into the shared memory starting at Address 0. Data is transferred from the serial EEPROM to the shared memory (in units of DWORDs). (Refer to Chapter 6, "Serial EEPROM Controller," for details.) 17.3 PCI Express Accesses The shared memory is accessed using the 64-KB Address space defined by the Base Address 0 register. The shared memory is located at offset 8000h in this space. PCI Express Posted Writes are used to write data to the shared memory. Single or Burst Writes are accepted, and PCI Express first and last Byte Enables are supported. When shared Memory Write data is poisoned, the data is discarded and an ERR_NONFATAL message is generated (when enabled). PCI Express Non-Posted reads are used to read data from the shared memory. Single or Burst reads are accepted. When the 8-KB Address Boundary space of the shared memory is reached during a Burst Write or Read, the address wraps around to the start of memory. 17.4 PCI Accesses The shared memory is accessed using the 64-KB Address space defined by the Base Address 0 register. The shared memory is located at Address offset 8000h in this space. PCI single or Burst writes are used to write data to the shared memory. PCI Byte Enables are supported for each DWORD transferred. PCI Single or Burst reads are used to read data from the shared memory. When the 8-KB Address Boundary space of the shared memory is reached during a Burst Write or Read, a PCI Disconnect is generated. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 241 Shared Memory 242 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 18 18.1 Testability and Debug JTAG Interface The PEX 8111 provides a Joint Test Action Group (JTAG) Boundary Scan interface, which is utilized to debug board connectivity for each ball. 18.1.1 IEEE Standard 1149.1 Test Access Port The IEEE Standard 1149.1 Test Access Port (TAP), commonly referred to as the JTAG debug port, is an architectural standard described in the IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture. This standard describes a method for accessing internal PEX 8111 facilities, using a four- or five-signal interface. The JTAG debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. The enhancements, which comply with the IEEE Standard 1149.1b-1994 Specifications for Vendor-Specific Extensions, are compatible with standard JTAG hardware for boundary-scan system testing. * JTAG Signals - JTAG debug port implements the four required JTAG signals (TCK, TDI, TDO, TMS) and the optional TRST# signal * JTAG Clock Requirements - TCK signal frequency range from DC to 10 MHz * JTAG Reset Requirements - Refer to Section 18.1.4, "JTAG Reset Input TRST#" PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 243 Testability and Debug 18.1.2 PLX Technology, Inc. JTAG Instructions Table 18-1 delineates the IEEE standard 1149.1 EXTEST, IDCODE, SAMPLE/PRELOAD, BYPASS, and PRIVATE instructions, provided by the JTAG debug port, and their input codes. PRIVATE instructions are for PLX use only. Invalid instructions behave as the BYPASS instruction. Table 18-2 delineates the IDCODE values returned by the PEX 8111. Table 18-1. EXTEST, IDCODE, SAMPLE/PRELOAD, BYPASS, and PRIVATE Instructions Instruction Input Code EXTEST 00000b IDCODE 00001b SAMPLE/PRELOAD 00011b BYPASS 11111b Comments 00011b 00100b 00101b IEEE Standard 1149.1-1990 00110b PRIVATEa 00111b 01000b 01001b 01010b a. Warning: Non-PLX use of PRIVATE instructions can cause the PEX 8111 to operate in a hazardous manner. Table 18-2. 244 PEX 8111 JTAG IDCODE Values PEX 8111 Version Part Number PLX Manufacturer Identity Least Significant Bit Bits 0010b 1000_0001_1101_0010b 000_0001_0000b 1 Hex 2h 81D2h 10h 1h Decimal 2 33234 16 1 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 18.1.3 JTAG Boundary Scan JTAG Boundary Scan Scan Description Language (BSDL), IEEE 1149.1b-1994, is a supplement to IEEE Standard 1149.11990 and IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture. BSDL, a subset of the IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL), which allows a rigorous description of testability features in components that comply with the standard. It is used by automated test pattern generation tools for package interconnect tests and Electronic Design Automation (EDA) tools for synthesized test logic and verification. BSDL supports robust extensions that are used for internal test generation and to write software for hardware debug and diagnostics. The primary components of BSDL include the logical port description, physical ball map, instruction set, and boundary register description. The logical port description assigns symbolic names to the PEX 8111 balls. Each ball contains a logical type of In, Out, In Out, Buffer, or Linkage that defines the logical direction of signal flow. The physical ball map correlates the PEX 8111 logical ports to the physical balls of a specific package. A BSDL description has several physical ball maps; each map is assigned a unique name. Instruction set statements describe the bit patterns that must be shifted into the Instruction register to place the PEX 8111 in the various test modes defined by the standard. Instruction set statements also support descriptions of instructions that are unique to the PEX 8111. The boundary register description lists each cell or shift stage of the Boundary register. Each cell contains a unique number; the cell numbered 0 is the closest to the Test Data Out (TDO) ball and the cell with the highest number is closest to the Test Data In (TDI) ball. Each cell contains additional information, including: * Cell type * Logical port associated with the cell * Logical function of the cell * Safe value * Control cell number * Disable value * Result value 18.1.4 JTAG Reset Input TRST# The TRST# input ball is the asynchronous JTAG logic reset. When TRST# is asserted, it causes the PEX 8111 TAP controller to initialize. In addition, when the TAP controller is initialized, it selects the PEX 8111 normal logic path (PCI Express interface-to-I/O). It is recommended that the following be taken into consideration when implementing the asynchronous JTAG logic reset on a board: * If JTAG functionality is required, consider one of the following: - TRST# input signal uses a low-to-high transition one time during the PEX 8111 boot-up, along with the RST# signal - Hold the PEX 8111 TMS ball high while transitioning the PEX 8111 TCK ball five times * If JTAG functionality is not required, the TRST# signal must be directly connected to ground PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 245 Testability and Debug 246 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 19 19.1 Electrical Specifications Power Sequence The power supply for the PEX8111BB I/O buffers are 3.3V (VDD3.3 and VDDQ) and core is 1.5V (VDD1.5, VDD_P, VDD_R, VDD_T, and AVDD). To fully comply with PCI r2.2 or PCI r3.0, a third power supply for VIO (VDD5) is also supported. VIO connects to a cathode of the high clamp diode in the PCI buffers. In a 5V system, set VIO to 5V, and in a 3.3V system, set to 3.3V. As in all multi-supply devices, ensure proper power-on procedures. Table 19-1 specifies the recommended PEX 8111 power-on and power-down sequences. If the sequences cannot be guaranteed, it is recommended that each power supply be turned-on/turned-off within 10 ms of one another. Caution: Exposure to sequences other than those recommended can affect reliability. Table 19-1. Power Sequence Power-On Sequence 19.1.1 Power-Down Sequence 1. VDD5 1. 1.5V 2. 3.3V 2. 3.3V 3. 1.5V 3. VDD5 VIO If the VIO voltage source is not powered and it presents a low-impedance path to ground, the PEX 8111's VIO balls can source high current, which could immediately damage the PEX 8111 or cause it undue long-term electrical stress. The amount of current each PCI ball/pad sources is dependent upon the device that is driving the signal/pad, or the value of the pull-up resistor when the signal is not driven. For designs and add-in boards that have an independent voltage source for VIO, for which proper power sequencing cannot be guaranteed, a resistor is strongly recommended between the VIO voltage source and PEX 8111 VIO balls (VDD5) to limit the current and protect the devices from damage or long-term undue stress. Use the following guidelines to determine the value of this required resistance: * 3.3V Signaling Environments - 40 to 200-Ohm resistance between the VIO voltage source and the PEX 8111 VIO balls is recommended if VIO is a maximum of 3.6 V * 3.3 or 5V Signaling Environments - 40 to 70-Ohm resistance is recommended A single resistor can be used if the VIO balls are bused, or multiple parallel resistors can be used between the VIO voltage source and VIO balls. The resistor power dissipation rating depends upon the resistance size and signaling environment. For example, if a single 50-Ohm resistor is used in a 5V-signaling environment, the worst-case power dissipation can result in 480 mW, calculated as follows: 480 mW = (V * V)/R (5.5V (Maximum Signal Amplitude, Plus 10%) - 0.6V (1 Diode Drop))2 50 Ohms If four, 200-Ohm resistors are used in parallel, each is required to dissipate 120 mW. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 247 Electrical Specifications PLX Technology, Inc. Any resistance value within the recommended ranges prevents damage to the PEX 8111, while providing sufficient clamping action to hold the Input Voltage (VIN) below its maximum rating. A resistance value at the lower end of the range is recommended to provide preferable clamping action, and a sufficient VIN margin. 19.2 Absolute Maximum Ratings Caution: Conditions that exceed the Absolute Maximum limits can destroy the PEX 8111. Table 19-2. Absolute Maximum Ratings Symbol Parameter Conditions VDD1.5, VDD_P, VDD_R, VDD_T, AVDD 1.5V Power Supply Voltages VDD3.3, VDDQ 3.3V Power Supply Voltages VDD5 5V Power Supply Voltage VI DC Input Voltage IOUT DC Output Current, per ball Min Max Unit -0.5 +1.8 V -0.5 +4.6 V -0.5 +6.6 V 3.3V buffer -0.5 +4.6 V 5V Tolerant buffer (PCI) -0.5 +6.6 V 3 mA Buffer -10 +10 mA 6 mA Buffer -20 +20 mA 12 mA Buffer -40 +40 mA 24 mA Buffer (PCI) -70 +70 mA -65 +150 C - 2 KV With Respect to Ground TSTG Storage Temperature No bias VESD ESD Rating R = 1.5K, C = 100 pF Table 19-3. Package Thermal Resistance 248 Package ThetaJC (C/W) 0 m/s ThetaJA (C/W) 0 m/s 13-mm square 144-ball PBGA 6.8 32.4 10-mm square 161-Ball FBGA 10.62 45.3 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Recommended Operating Conditions 19.3 Recommended Operating Conditions Caution: Conditions that exceed the Operating limits can cause the PEX 8111 to malfunction. Table 19-4. Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit VDD1.5, VDD_P, VDD_R, VDD_T, AVDD 1.5V Power Supply Voltages 1.4 1.6 V VDD3.3, VDDQ 3.3V Power Supply Voltages 3.0 3.6 V VDD5 5V Power Supply Voltage Note 1 4.75 5.25 V VN Negative Trigger Voltage 3.3V buffer 0.8 1.7 V 5V tolerant buffer (PCI) 0.8 1.7 V VP Positive Trigger Voltage 3.3V buffer 1.3 2.4 V 5V tolerant buffer (PCI) 1.3 2.4 V VIL Low Level Input Voltage 3.3V buffer 0 0.7 V 5V tolerant buffer (PCI) 0 0.8 V VIH High Level Input Voltage 3.3V buffer 1.7 VDD3.3 V 5V tolerant buffer (PCI) 2.0 VDD5 + 0.5 V 3 mA buffer (VOL = 0.4) 3 mA 6 mA buffer (VOL = 0.4) 6 mA 12 mA buffer (VOL = 0.4) 12 mA 24 mA buffer (VOL = 0.4) (PCI) 24 mA 3 mA buffer (VOH = 2.4) -3 mA 6 mA buffer (VOH = 2.4) -6 mA 12 mA buffer (VOH = 2.4) -12 mA 24 mA buffer (VOH = 2.4) (PCI) -24 mA 0 70 C 0 200 ns 0 200 ns 0 10 ms 0 10 ms IOL IOH Low Level Output Current High Level Output Current TA Operating Temperature tR Input Rise Times tF Input Fall Time tR Input Rise Times tF Input Fall Time Normal input Schmitt input Notes: 1. In a 3.3V-only system, the VDD5 balls can be connected to the 3.3V power supply (3.0 to 3.6V). 2. VIL and VIH for non-PCI buffered inputs, such as, JTAG, GPIO, and serial EEPROM signals and strapping signals (EXTARB, FWD, and so forth), are 3.3V LVTTL inputs (CMOS) VIL = 0.8V maximum and VIH = 2V minimum. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 249 Electrical Specifications 19.4 PLX Technology, Inc. DC Specifications Operating Conditions - VDD1.5 = 1.5V 0.1V, VDD3.3 = 3.3V 0.3V, TA = 0 to 70C Typical Values - VDD1.5 = 1.5V, VDD3.3 = 3.3V, TA = 25C Table 19-5. PCI Express Interface DC Specifications Symbol Parameter Conditions IVDD1.5 VDD1.5 Supply Current IVDDSERDES VDD_P, VDD_R, VDD_P, VDD_R, VDD_T, AVDD Supply Currents VDD_T, AVDD = 1.5V IVDD3.3 VDD3.3 Supply Current VDD3.3 = 3.3V IVDDQ VDDQ Supply Current VDDQ = 3.3V IVDD5 VDD5 Supply Current VDD5 = 5.0V Min Typ Max Unit 180 207 mA 19 22 mA .003 .004 mA VDD1.5 = 1.5V Notes: 1. IVDD1.5 + IVDDSERDES = 207 mA. 2. IVDD3.3 + IVDDQ = 22 mA. 19.4.1 PCI Bus DC Specification Operating Conditions - VDD1.5 = 1.5V 0.1V, VDD3.3 = 3.3V 0.3V, TA = 0 to 70C Typical Values - VDD1.5 = 1.5V, VDD3.3 = 3.3V, TA = 25C Table 19-6. PCI Bus DC Specification Symbol Parameter Conditions Min Typ Max Unit VIHd PCI 3.3V Input High Voltage 0.5 * VDD3.3 VDD3.3 V VILd PCI 3.3V Input Low Voltage 0 0.7 V VIH PCI 5.0V Input High Voltage 2.0 5.5 V VIL PCI 5.0V Input Low Voltage 0 0.8 V IIL Input Leakage -10 +10 A IOZ Hi-Z State Data Line Leakage 10 A VOH3 PCI 3.3V Output High Voltage IOUT = -500 A VOL3 PCI 3.3V Output Low Voltage IOUT = 1500 A VOH PCI 5.0V Output High Voltage IOUT = -12 mA VOL PCI 5.0V Output Low Voltage IOUT = 12 mA CIN Input Capacitance CCLK CLK Ball Capacitance CIDSEL IDSEL Ball Capacitance 250 0V < VIN < VDD5 Ball to GND 0.9 * VDD3.3 V 0.1 * VDD3.3 2.4 5 V V 0.4 V 10 pF 12 pF 8 pF PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 19.4.2 SerDes Interface DC Characteristics SerDes Interface DC Characteristics Table 19-7. PCI Bus DC Specification Item Conditions Min Typ Max Unit Differential Output Amplitude 0.85 1.01 1.02 V Emphasis Levels 3.25 3.61 3.76 dB TX Eye Width 0.85 0.92 0.96 UIa Maximum time between the jitter median and deviation from the median 0.02 0.03 0.07 UI TX rise time and fall time 0.19 0.27 0.40 UI RMS AC common mode voltage 9.2 12.8 18.2 mV Absolute delta of DC common mode voltage during L0 and electrical idle 0.5 25 97 mV Absolute delta of DC common mode voltage between D+ and D- 0.7 8.8 16.9 mV Electrical idle differential peak output voltage 2.35 4.81 9.0 mV The amount of voltage change allowed during receiver detection 401 460 484 mV TX DC common mode voltage 0.60 0.84 0.97 V TX short current 43.1 52.2 67.4 mA Maximum time to transition to a valid electrical idle after transmitting an electrical idle order set 4.4 5.2 6.4 UI Maximum time to transition to a valid TX specification after leaving an electrical idle condition 2.1 2.9 3.5 UI Differential return loss 11.4 14.1 16.4 dB Common mode return loss 6.5 10.2 12.3 dB DC differential TX impedance 95.2 107.6 116.9 Ohm Lane-to-Lane Output Skew 115 167 215 ps 0.175 - 3.3 V TX I/O Characteristics RX I/O Characteristics Differential input amplitude Jitter tolerance RX data input amplitude = 175 mV Sinusoidal jitter - 0.256 UI Backplane length - 30 inches RX differential return loss 15.6 19.1 21.8 dB RX common mode return loss 7.7 12.4 14.0 dB DC differential input impedance 92.7 107.0 115.8 Ohm DC input impedance 45.0 53.2 57.5 Ohm Power down input impedance 361 3380 - Ohm Electrical idle detect threshold 61 - 173 mV a. UI is Unit Interval. Given a data stream of a repeating pattern of alternating 1 and 0 values, the Unit Interval is the value measured by averaging the time interval between voltage transitions, over a time interval long enough to make all intentional frequency modulation of the source clock negligible. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 251 Electrical Specifications PLX Technology, Inc. Figure 19-1. 252 SIG-TEST Results PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 SerDes Interface DC Characteristics Figure 19-2. Near-End/Far-End Eye Diagram PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 253 Electrical Specifications PLX Technology, Inc. 19.5 AC Specifications 19.5.1 SerDes Interface AC Specification Table 19-8. PEX_REFCLK AC Specifications Symbol Parameter Test Conditions Min Max Unit 100 Notes PEX_REFCLK 100-MHz Differential Reference Clock Input VCM Input Common-Mode Voltage 0.6 0.65 0.7 V ClkInDC Input Clock Duty Cycle 40 50 60 % TR/TF Input Clock Rise/Fall Times 0.2 RCUIa VSW Differential Input Voltage Swingb 1.6 V RTERM Reference Clock Differential Termination JTCLK_REF Input Jitter (Peak-to-Peak) 0.6 MHz 110 Ohms 0.1 UI a. RCUI refers to the reference clock period (10 ns typical). b. AC coupling required. 254 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 19.5.2 PCI Bus 33-MHz AC Specifications PCI Bus 33-MHz AC Specifications Operating Conditions - VDD1.5 = 1.5V 0.1V, VDD3.3 = 3.3V 0.3V, TA = 0 to 70C Typical Values - VDD1.5 = 1.5V, VDD3.3 = 3.3V, TA = 25C Table 19-9. PCI Bus 33-MHz AC Specifications Symbol Parameter Conditions Min Max Unit Notes TCYC PCI CLK Cycle Time 30 ns TVAL CLK to Signal Valid Delay - Bused Signals 2 11 ns 2, 3 TVAL(ptp) CLK to Signal Valid Delay - Point-to-Point 2 12 ns 2, 3 TON Float to Active Delay 2 ns 7 TOFF Active to Float Delay ns 7 TSU Input Setup to CLK - Bused Signals 6 ns 3, 8 TSU(ptp) Input Setup to CLK - Point-to-Point 10,12 ns 3 TH Input Hold from CLK 0 ns TRST Reset Active Time after Power Stable 1 ms 5 TRST-CLK Reset Active Time after CLK Stable 100 s 5 TRST-OFF Reset Active to Output Float Delay TRHFA RST# High to First Configuration Access TRHFF RST# High to First FRAME# Assertion 28 ns 5, 6, 7 225 40 clocks 9 5 clocks Notes: 2. For parts compliant to the 5V signaling environment: Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load. Actual test capacitance varies; however, results must be correlated to these specifications. Faster buffers can exhibit ring back when attached to a 50 pF lump load but should be of no consequence when the output buffers are in full compliance with slew rate and V/I curve specifications. For parts compliant to the 3.3V signaling environment: Minimum times are evaluated with the same load used for slew rate measurement; maximum times are evaluated with a parallel RC load of 25 Ohms and 10 pF. 3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than bused signals. The setup for REQ# is 12. The setup for GNT# is 10. All other signals are bused. 5. CLK is stable when it meets the PCI CLK specifications. RST# is asserted and de-asserted asynchronously with respect to CLK. 6. All output drivers must be asynchronously floated when RST# is active. 7. For Active/Float timing measurement purposes, the Hi-Z or "off" state is defined as "total current delivered through the PEX 8111 ball is less than or equal to the leakage current specification." 8. Setup time applies only when the device is not driving the ball. Devices cannot drive and receive signals at the same time. 9. At 33 MHz, the PEX 8111 must be ready to accept a Configuration access within 1s after RST# is high. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 255 Electrical Specifications 19.5.3 PLX Technology, Inc. PCI Bus 66-MHz AC Specifications Operating Conditions - VDD1.5 = 1.5V 0.1V, VDD3.3 = 3.3V 0.3V, TA = 0 to 70C Typical Values - VDD1.5 = 1.5V, VDD3.3 = 3.3V, TA = 25C Table 19-10. PCI Bus 66-MHz AC Specifications Symbol Parameter Conditions Min Max Unit Notes TCYC PCI CLK Cycle Time 15 ns TVAL CLK to Signal Valid Delay - Bused Signals 2 6 ns 3, 8 TVAL(ptp) CLK to Signal Valid Delay - Point-to-Point 2 6 ns 3, 8 TON Float to Active Delay 2 ns 8, 9 TOFF Active to Float Delay ns 9 TSU Input Setup to CLK - Bused Signals 3 ns 3, 10 TSU(ptp) Input Setup to CLK - Point-to-Point 5 ns 3 TH Input Hold from CLK 0 ns TRST Reset Active Time after Power Stable 1 ms 5 TRST-CLK Reset Active Time after CLK Stable 100 s 5 TRST-OFF Reset Active to Output Float Delay 14 TRHFA RST# High to First Configuration Access TRHFF RST# High to First FRAME# Assertion ns 5, 6 225 40 clocks 9 5 clocks Notes: 3. REQ# and GNT# are point-to-point signals and have different input setup times than bused signals. The setup for REQ# and GNT# is 5 ns at 66 MHz. All other signals are bused. 5. When M66EN is asserted, CLK is stable when it meets the requirements in the PCI r3.0, Section 7.6.4.1. RST# is asserted and de-asserted asynchronously with respect to CLK. Refer to the PCI r3.0, Section 4.3.2, for further details. 6. All output drivers must be floated when RST# is active. 8. When M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton are reduced to 1 ns when a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is de-asserted. 9. For Active/Float timing measurement purposes, the Hi-Z or "off" state is defined as "total current delivered through the PEX 8111 ball is less than or equal to the leakage current specification." 10. Setup time applies only when the device is not driving the signal. Devices cannot drive and receive signals at the same time. Refer to the PCI r3.0, Section 3.10, item 9, for further details. 256 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Chapter 20 20.1 Physical Specifications PEX 8111 Package Specifications The PEX 8111 is offered in two package types: * 13-mm square 144-ball PBGA (Plastic BGA) package (refer to Table 20-1) * 10-mm square 161-Ball FBGA (Fine-Pitch BGA) package (refer to Table 20-2) Table 20-1. PEX 8111 144-Ball PBGA Package Specifications Parameter Specification Package Type Plastic Ball Grid Array Package Dimensions 13 x 13 mm (approximately 1.83 mm high) Ball matrix pattern 12 x 12 mm Ball pitch 1.00 mm Ball diameter 0.60 0.15 mm Ball spacing 0.40 mm Table 20-2. PEX 8111 161-Ball FBGA Package Specifications Parameter Specification Package Type Fine-Pitch Ball Grid Array Package Dimensions 10 x 10 mm (approximately 1.43 mm high) Ball matrix pattern 9 x 9 mm Ball pitch 0.65 mm Ball diameter 0.60 0.15 mm Ball spacing 0.40 mm PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 257 Physical Specifications 20.2 PLX Technology, Inc. Mechanical Drawings Figure 20-1. 258 144-Ball PBGA Mechanical Drawing PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 Mechanical Drawings Figure 20-2. 161-Ball FBGA Mechanical Drawing PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 259 Physical Specifications 20.3 PLX Technology, Inc. PCB Layouts Figure 20-3. 144-Ball PBGA PCB Layout bs a p ls p bs Center of package lw Edge of package Des ign Rule on board (general) BGA land dia. : a=450um BGA land Pitch : p=1000um Space btwn lands : b s = 550um Line/Space : l w/ls =100um/100um Red : traces on an upper signal layer for the PCB Blue : traces on a lower signal layer for PCB 2 signal layers are required due BGA lands. to routing only one trace between Note: Refer to the PEX 8111 Quick Start Design Note for the trace lengths and a detailed description of the PCI Express layout considerations. 260 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 June, 2006 PCB Layouts Figure 20-4. 161-Ball FBGA PCB Layout Note: Refer to the PEX 8111 Quick Start Design Note for the trace lengths and a detailed description of the PCI Express layout considerations. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 261 Physical Specifications 262 PLX Technology, Inc. PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 Appendix A General Information A.1 Product Ordering Information Contact your local PLX Sales Representative for ordering information. Table A-1. Product Ordering Information Part Number Description PEX8111-BB66BC PCI Express-to-PCI Bridge, Standard BGA Package (144-Ball, 13 x 13 mm) PEX8111-BB66FBC PCI Express-to-PCI Bridge, Fine-Pitch BGA Package (161-Ball, 10 x 10 mm) PEX8111-BB66BC F PCI Express-to-PCI Bridge, Standard BGA Package (144-Ball, 13 x 13 mm), Lead Free PEX8111-BB66FBC F PCI Express-to-PCI Bridge, Fine-Pitch BGA Package (161-Ball, 10 x 10 mm), Lead Free PEX8111-BB66 FBC F F - Lead Free I - Industrial Temperature B - Plastic Ball Grid Array package F - Fine Pitch (161-Ball package only) BB - Part Revision Code 66 - Speed Grade (66 MHz PCI Bus) 8111 - Part Number PEX - PCI Express product family PEX8111RDK-F Forward Bridge Reference Design Kit PEX8111RDK-R Reverse Bridge Reference Design Kit PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2 263 General Information A.2 PLX Technology, Inc. United States and International Representatives and Distributors PLX Technology, Inc., representatives and distributors are listed at www.plxtech.com. A.3 Technical Support PLX Technology, Inc., technical support information is listed at www.plxtech.com/support/, or call 408 774-9060 or 800 759-3735. 264 PEX 8111BB ExpressLane PCI Express-to-PCI Bridge Data Book Copyright (c) 2006 by PLX Technology Inc. All Rights Reserved - Version 1.2