AD9235BCPRL7-65 - Analog Devices, Inc.

12-Bit, 20/40/65 MSPS

3 V A/D Converter

AD9235

Rev. C

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Single 3 V supply operation (2.7 V to 3.6 V)

SNR = 70 dBc to Nyquist at 65 MSPS

SFDR = 85 dBc to Nyquist at 65 MSPS

Low power: 300 mW at 65 MSPS

Differential input with 500 MHz bandwidth

On-chip reference and SHA

DNL = ±0.4 LSB

Flexible analog input: 1 V p-p to 2 V p-p range

Offset binary or twos complement data format

Clock duty cycle stabilizer

APPLICATIONS

Ultrasound equipment

IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000

Battery-powered instruments

Hand-held scopemeters

Low cost digital oscilloscopes

FUNCTIONAL BLOCK DIAGRAM

SHA

VIN+

VIN–

DRVDD

8-STAGE

1 1/2-BIT

PIPELINE

CLK PDWN MODE

CLOCK

DUTY CYCLE

STABILIZER MODE

SELECT

DGND

OTR

D11

D0

AVDD

MDAC1

CORRECTION LOGIC

OUTPUT BUFFERS

REF

SELECT

AGND

0.5V

VREF

SENSE

AD9235

02461-001

REFT

REFB

A/D

4 16

12

3

Figure 1.

GENERAL DESCRIPTION

The AD9235 is a family of monolithic, single 3 V supply, 12-bit,

20/40/65 MSPS analog-to-digital converters (ADCs). This

family features a high performance sample-and-hold amplifier

(SHA) and voltage reference. The AD9235 uses a multistage

differential pipelined architecture with output error correction

logic to provide 12-bit accuracy at 20/40/65 MSPS data rates

and guarantee no missing codes over the full operating

temperature range.

The wide bandwidth, truly differential SHA allows a variety of

user-selectable input ranges and offsets including single-ended

applications. It is suitable for multiplexed systems that switch

full-scale voltage levels in successive channels and for sampling

single-channel inputs at frequencies well beyond the Nyquist

rate. Combined with power and cost savings over previously

available ADCs, the AD9235 is suitable for applications in

communications, imaging, and medical ultrasound.

A single-ended clock input is used to control all internal

conversion cycles. A duty cycle stabilizer (DCS) compensates

for wide variations in the clock duty cycle while maintaining

excellent overall ADC performance. The digital output data is

presented in straight binary or twos complement formats. An

out-of-range (OTR) signal indicates an overflow condition that

can be used with the most significant bit to determine low or

high overflow.

Fabricated on an advanced CMOS process, the AD9235 is avail-

able in a 28-lead TSSOP and a 32-lead LFCSP and is specified

over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. The AD9235 operates from a single 3 V power supply and

features a separate digital output driver supply to accommo-

date 2.5 V and 3.3 V logic families.

2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.

3. The patented SHA input maintains excellent performance for

input frequencies up to 100 MHz and can be configured for

single-ended or differential operation.

4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,

65 MSPS ADC. This allows a simplified upgrade path from

10 bits to 12 bits for 65 MSPS systems.

5. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

6. The OTR output bit indicates when the signal is beyond the

selected input range.

AD9235

Rev. C | Page 2 of 40

TABLE OF CONTENTS

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Digital Specifications ................................................................... 4

Switching Specifications .............................................................. 4

AC Specifications.......................................................................... 5

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels........................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Definitions of Specifications........................................................... 9

Equivalent Circuits......................................................................... 10

Typical Performance Characteristics ........................................... 11

Applying the AD9235 .................................................................... 15

Theory of Operation.................................................................. 15

Analog Input ............................................................................... 15

Clock Input Considerations...................................................... 16

Power Dissipation and Standby Mode .................................... 17

Digital Outputs ........................................................................... 18

Voltage Reference ....................................................................... 18

Operational Mode Selection..................................................... 19

TSSOP Evaluation Board .......................................................... 19

LFCSP Evaluation Board........................................................... 20

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 37

REVISION HISTORY

10/04—Data Sheet changed from Rev. B to Rev. C

Changes to Format .............................................................Universal

Changes to Specifications.................................................................3

Changes to the Ordering Guide.................................................... 37

5/03—Data Sheet changed from Rev. A to Rev. B

Added CP-32 Package (LFCSP)........................................Universal

Changes to Several Pin Names .........................................Universal

Changes to Features...........................................................................1

Changes to Product Description .....................................................1

Changes to Product Highlights........................................................1

Changes to Specifications.................................................................2

Replaced Figure 1 ..............................................................................3

Changes to Absolute Maximum Ratings ........................................5

Changes to Ordering Guide .............................................................5

Changes to Pin Function Descriptions...........................................6

New Definitions of Specifications Section.....................................7

Changes to TPCs 1 to 12...................................................................9

Changes to Theory of Operation Section.................................... 13

Changes to Analog Input Section..................................................13

Changes to Single-ended Input Configuration Section .............14

Replaced Figure 8 ............................................................................14

Changes to Clock Input Considerations Section ........................14

Changes to Table I ...........................................................................15

Changes to Power Dissipation and Standby Mode Section.......15

Changes to Digital Outputs Section..............................................15

Changes to Timing Section ............................................................15

Changes to Figure 13.......................................................................16

Changes to Figures 16 to 26 ...........................................................17

Added LFCSP Evaluation Board Section .....................................17

Inserted Figures 27 to 35 ................................................................25

Added Table III................................................................................30

Updated Outline Dimensions........................................................31

8/02—Data Sheet changed from Rev. 0 to Rev. A

Updated RU-28 Package................................................................ 24

AD9235

Rev. C | Page 3 of 40

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX,

unless otherwise noted.

Table 1.

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter Temp

Test

Level Min Typ Max Min Typ Max Min Typ Max

Unit

RESOLUTION Full VI 12 12 12 Bits

ACCURACY

No Missing Codes Guaranteed Full VI 12 12 12 Bits

Offset Error Full VI ±0.30 ±1.20 ±0.50 ±1.20 ±0.50 ±1.20 % FSR

Gain Error1Full VI ±0.30 ±2.40 ±0.50 ±2.50 ±0.50 ±2.60 % FSR

Differential Nonlinearity (DNL)2Full IV ±0.35 ±0.65 ±0.35 ±0.75 ±0.40 ±0.80 LSB

25°C I ±0.35 ±0.35 ±0.35 LSB

Integral Nonlinearity (INL)2 Full IV ±0.45 ±0.80 ±0.50 ±0.90 ±0.70 ±1.30 LSB

25°C I ±0.40 ±0.40 ±0.45 LSB

TEMPERATURE DRIFT

Offset Error Full V ±2 ±2 ±3 ppm/°C

Gain Error Full V ±12 ±12 ±12 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV

Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV

Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV

Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV

INPUT REFERRED NOISE

VREF = 0.5 V 25°C V 0.54 0.54 0.54 LSB rms

VREF = 1.0 V 25°C V 0.27 0.27 0.27 LSB rms

ANALOG INPUT

Input Span, VREF = 0.5 V Full IV 1 1 1 V p-p

Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p

Input Capacitance3Full V 7 7 7 pF

REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ

POWER SUPPLIES

Supply Voltages

AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V

DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V

Supply Current

IAVDD2 Full V 30 55 100 mA

IDRVDD2 Full V 2 5 7 mA

PSRR Full V ±0.01 ±0.01 ±0.01 % FSR

POWER CONSUMPTION

DC Input4Full V 90 165 300 mW

Sine Wave Input2 Full VI 95 110 180 205 320 350 mW

Standby Power5Full V 1.0 1.0 1.0 mW

1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

2 Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.

3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to for the equivalent analog input structure. Figure 5

4 Measured with dc input at maximum clock rate.

5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).

AD9235

Rev. C | Page 4 of 40

DIGITAL SPECIFICATIONS

Table 2.

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter Temp

Test

Level Min Typ Max Min Typ Max Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage Full IV 2.0 2.0 2.0 V

Low Level Input Voltage Full IV 0.8 0.8 0.8 V

High Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA

Low Level Input Current Full IV –10 +10 –10 +10 –10 +10 µA

Input Capacitance Full V 2 2 2 pF

LOGIC OUTPUTS1

DRVDD = 3.3 V

High-Level Output Voltage Full IV 3.29 3.29 3.29 V

(IOH = 50 µA)

High-Level Output Voltage Full IV 3.25 3.25 3.25 V

(IOH = 0.5 mA)

Low-Level Output Voltage Full IV 0.2 0.2 0.2 V

(IOL = 1.6 mA)

Low-Level Output Voltage Full IV 0.05 0.05 0.05 V

(IOL = 50 µA)

DRVDD = 2.5 V

High-Level Output Voltage Full IV 2.49 2.49 2.49 V

(IOH = 50 µA)

High-Level Output Voltage Full IV 2.45 2.45 2.45 V

(IOH = 0.5 mA)

Low-Level Output Voltage Full IV 0.2 0.2 0.2 V

(IOL = 1.6 mA)

Low-Level Output Voltage Full IV 0.05 0.05 0.05 V

(IOL = 50 µA)

1 Output voltage levels measured with 5 pF load on each output.

SWITCHING SPECIFICATIONS

Table 3.

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter Temp

Test

Level Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate Full VI 20 40 65 MSPS

Minimum Conversion Rate Full V 1 1 1 MSPS

CLK Period Full V 50.0 25.0 15.4 ns

CLK Pulse-Width High1Full V 15.0 8.8 6.2 ns

CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns

DATA OUTPUT PARAMETERS

Output Delay2 (tPD) Full V 3.5 3.5 3.5 ns

Pipeline Delay (Latency) Full V 7 7 7 Cycles

Aperture Delay (tA) Full V 1.0 1.0 1.0 ns

Aperture Uncertainty Jitter (tJ) Full V 0.5 0.5 0.5 ps rms

Wake-Up Time3Full V 3.0 3.0 3.0 ms

OUT-OF-RANGE RECOVERY TIME Full V 1 1 2 Cycles

1 For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.

2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.

3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

AD9235

Rev. C | Page 5 of 40

t

A

t

PD

= 6.0ns MAX

2.0ns MIN

N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N

A

NALO

G

INPUT

CLK

DATA

OUT

N–1

NN+1 N+2

N+3

N+4 N+5 N+6 N+7

N+8

02461-002

Figure 2. Timing Diagram

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX,

unless otherwise noted.

Table 4.

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO

fINPUT = 2.4 MHz 25°C V 70.8 70.6 70.5 dBc

fINPUT = 9.7 MHz Full IV 70.0 70.4 dBc

25°C I 70.6 dBc

fINPUT = 19.6 MHz Full IV 69.9 70.3 dBc

25°C I 70.4 dBc

fINPUT = 32.5 MHz Full IV 68.7 69.7 dBc

25°C I 70.1 dBc

fINPUT = 100 MHz 25°C V 68.7 68.5 68.3 dBc

SIGNAL-TO-NOISE RATIO

AND DISTORTION

fINPUT = 2.4 MHz 25°C V 70.6 70.5 70.4 dBc

fINPUT = 9.7 MHz Full IV 69.9 70.3 dBc

25°C I 70.5 dBc

fINPUT = 19.6 MHz Full IV 69.7 70.2 dBc

25°C I 70.3 dBc

fINPUT = 32.5 MHz Full IV 68.3 69.5 dBc

25°C I 69.9 dBc

fINPUT = 100 MHz 25°C V 68.6 68.3 67.8 dBc

TOTAL HARMONIC DISTORTION

fINPUT = 2.4 MHz 25°C V –88.0 –89.0 –87.5 dBc

fINPUT = 9.7 MHz Full IV –86.0 –79.0 dBc

25°C I –87.4 dBc

fINPUT = 19.6 MHz Full IV –85.5 –79.0 dBc

25°C I –86.0 dBc

fINPUT = 32.5 MHz Full IV –81.8 –74.0 dBc

25°C I –82.0 dBc

fINPUT = 100 MHz 25°C V –84.0 –82.5 –78.0 dBc

WORST HARMONIC

(SECOND OR THIRD)

fINPUT = 9.7 MHz Full IV –90.0 –80.0 dBc

fINPUT = 19.6 MHz Full IV –90.0 –80.0 dBc

fINPUT = 32.5 MHz Full IV –83.5 –74.0 dBc

AD9235

Rev. C | Page 6 of 40

AD9235BRU/BCP-20 AD9235BRU/BCP-40 AD9235BRU/BCP-65

Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit

SPURIOUS-FREE DYNAMIC RANGE

fINPUT = 2.4 MHz 25°C V 92.0 92.0 92.0 dBc

fINPUT = 9.7 MHz Full IV 80.0 88.5 dBc

25°C I 91.0 dBc

fINPUT = 19.6 MHz Full IV 80.0 89.0 dBc

25°C I 90.0 dBc

fINPUT = 32.5 MHz Full IV 74.0 83.0 dBc

25°C I 85.0 dBc

fINPUT = 100 MHz 25°C V 84.0 85.0 80.5 dBc

AD9235

Rev. C | Page 7 of 40

ABSOLUTE MAXIMUM RATINGS

Table 5.

Pin Name

With

Respect to Min Max Unit

ELECTRICAL

AVDD AGND –0.3 +3.9 V

DRVDD DGND –0.3 +3.9 V

AGND DGND –0.3 +0.3 V

AVDD DRVDD –3.9 +3.9 V

Digital

Outputs

DGND –0.3 DRVDD + 0.3 V

CLK, MODE AGND –0.3 AVDD + 0.3 V

VIN+, VIN– AGND –0.3 AVDD + 0.3 V

VREF AGND –0.3 AVDD + 0.3 V

SENSE AGND –0.3 AVDD + 0.3 V

REFB, REFT AGND –0.3 AVDD + 0.3 V

PDWN AGND –0.3 AVDD + 0.3 V

ENVIRONMENTAL1

Operating Temperature –40 +85 °C

Junction Temperature 150 °C

Lead Temperature (10 sec) 300 °C

Storage Temperature –65 +150 °C

1 Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead

LFCSP), θJA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on

a 4-layer board in still air, in accordance with EIA/JESD51-1.

Absolute maximum ratings are limiting values to be applied

individually and beyond which the serviceability of the circuit

may be impaired. Functional operability is not necessarily

implied. Exposure to absolute maximum rating conditions for

an extended period of time may affect device reliability.

EXPLANATION OF TEST LEVELS

Test

Levels Description

I 100% production tested.

II 100% production tested at 25°C and sample tested at

specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characteriza-

tion testing.

V Parameter is a typical value only.

VI 100% production tested at 25°C; guaranteed by de-

sign and characterization testing for industrial tem-

perature range; 100% production tested at tempera-

ture extremes for military devices.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-

trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation

or loss of functionality.

AD9235

Rev. C | Page 8 of 40

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AD9235

TOP VIEW

(Not to Scale)

MODE

SENSE

VREF

AVDD

REFT

REFB

OTR

D10

D9

D8

D7

DGND

DRVDD

AGND

VIN+

VIN–

PDWN

AVDD

AGND

D6

D5

D4

D0 (LSB)

CLK D1

D2

D3

D11 (MSB)

02461-003

Figure 3. 28-Lead TSSOP Pin Configuration

02461-004

24

23

22

21

1

2

3

32

AVDD

REFB

REFT

AVDD

AGND

VIN+

VIN–

AGND

20

19

18

17

D8

D9

D10

D11(MSB)

OTR

MODE

SENSE

VREF

9

10

11

12

13

D7

DGND

DRVDD

D6

D5

D4

D3

D2

14

15

16

4

5

6

7

8

D1

(LSB)D0

DNC

PDWN

DNC

CLK

DNC

31

30

29

28

27

26

25

AD9235

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

DNC = DO NOT CONNECT

Figure 4. 32-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

28-Lead TSSOP

Pin No.

32-Lead LFCSP Mnemonic Description

1 21 OTR Out-of-Range Indicator.

2 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.

3 23 SENSE Reference Mode Selection.

4 24 VREF Voltage Reference Input/Output.

5 25 REFB Differential Reference (−).

6 26 REFT Differential Reference (+).

7, 12 27, 32 AVDD Analog Power Supply.

8, 11 28, 31 AGND Analog Ground.

9 29 VIN+ Analog Input Pin (+).

10 30 VIN– Analog Input Pin (−).

13 2 CLK Clock Input Pin.

14 4 PDWN Power-Down Function Selection (Active High).

15 to 22, 25 to 28 7 to 14, 17 to 20 D0 (LSB) to D11 (MSB) Data Output Bits.

23 15 DGND Digital Output Ground.

24 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum.

0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.

1, 3, 5, 6 DNC Do Not Connect.

AD9235

Rev. C | Page 9 of 40

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay (tA)

The delay between the 50% point of the rising edge of the clock

and the instant at which the analog input is sampled.

Aperture Jitter (tJ)

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from

negative full scale through positive full scale. The point used as

negative full scale occurs ½ LSB before the first code transition.

Positive full scale is defined as a level 1 ½ LSBs beyond the last

code transition. The deviation is measured from the middle of

each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed no

missing codes to 12-bit resolution indicates that all 4096 codes

must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value

½ LSB below VIN+ = VIN–. Offset error is defined as the

deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB

above negative full scale. The last transition should occur at an

analog value 1 ½ LSB below the positive full scale. Gain error is

the deviation of the actual difference between first and last code

transitions and the ideal difference between first and last code

transitions.

Temperature Drift

The temperature drift for offset error and gain error specifies

the maximum change from the initial (25°C) value to the value

at TMIN or TMAX.

Power Supply Rejection Ratio

The change in full scale from the value with the supply

at the minimum limit to the value with the supply at its

maximum limit.

Total Harmonic Distortion (THD)1

The ratio of the rms sum of the first six harmonic components

to the rms value of the measured input signal.

1 AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

Signal-to-Noise and Distortion (SINAD)1

The ratio of the rms signal amplitude (set 0.5 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents below the Nyquist frequency, including harmonics but

excluding dc.

Effective Number of Bits (ENOB)

The ENOB for a device for sine wave inputs at a given input

frequency can be calculated directly from its measured SINAD

using the following formula

N = (SINAD − 1.76)/6.02

Signal-to-Noise Ratio (SNR)1

The ratio of the rms signal amplitude (set at 0.5 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents below the Nyquist frequency, excluding the first six

harmonics and dc.

Spurious-Free Dynamic Range (SFDR)1

The difference in dB between the rms amplitude of the input

signal and the peak spurious signal.

Two-Tone SFDR1

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product.

Clock Pulse Width and Duty Cycle

Pulse-width high is the minimum amount of time that the

clock pulse should be left in the Logic 1 state to achieve rated

performance. Pulse-width low is the minimum time the clock

pulse should be left in the low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the

guaranteed limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Output Propagation Delay (tPD)

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input

after a transition from 10% above positive full scale to 10%

above negative full scale, or from 10% below negative full scale

to 10% below positive full scale.

AD9235

Rev. C | Page 10 of 40

EQUIVALENT CIRCUITS

AVDD

VIN+, VIN–

02461-005

Figure 5. Equivalent Analog Input Circuit

AVDD

MODE

20kΩ

02461-006

Figure 6. Equivalent MODE Input Circuit

D11–D0,

OTR

DRVDD

02461-007

Figure 7. Equivalent Digital Output Circuit

02461-008

CLK,

PDWN

AVDD

Figure 8. Equivalent Digital Input Circuit

AD9235

Rev. C | Page 11 of 40

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS disabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V,

unless otherwise noted.

02461-009

FREQUENCY (MHz) 32.50 6.5 13.0 19.5 26.0

MAGNITUDE (dBFS)

0

–20

–40

–60

–80

–100

–120

SNR = 70.3dBc

SINAD = 70.2dBc

ENOB = 11.4 BITS

THD = –86.3dBc

SFDR = 89.9dBc

Figure 9. Single Tone 8K FFT with fIN = 10 MHz

02461-010

FREQUENCY (MHz) 91.065.0 71.5 78.0 84.5

MAGNITUDE (dBFS)

0

–20

–40

–60

–80

–100

–120

SNR = 69.4dBc

SINAD = 69.1dBc

ENOB = 11.2 BITS

THD = –81.0dBc

SFDR = 83.8dBc

Figure 10. Single Tone 8K FFT with fIN = 70 MHz

02461-011

FREQUENCY (MHz) 130.097.5 104.0 110.5 117.0 123.5

MAGNITUDE (dBFS)

0

–20

–40

–60

–80

–100

–120

SNR = 68.5dBc

SINAD = 66.5dBc

ENOB = 10.8 BITS

THD = –71.0dBc

SFDR = 71.2dBc

Figure 11. Single Tone 8K FFT with fIN = 100 MHz

02461-012

SAMPLE RATE (MSPS) 6540 45 50 55 60

SNR/SFDR (dBc)

100

95

90

80

70

60

85

75

65

55

50

SFDR (2V DIFF)

SNR (2V SE)

SNR (2V DIFF)

SFDR (2V SE)

Figure 12. AD9235-65: Single Tone SNR/SFDR vs.

fCLK with fIN = Nyquist (32.5 MHz)

02461-013

SAMPLE RATE (MSPS) 4020 25 30 35

SNR/SFDR (dBc)

100

95

90

85

80

75

70

65

60

55

50

SNR (2V SE)

SFDR (2V DIFF)

SNR (2V DIFF)

SFDR (2V SE)

Figure 13. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz)

02461-014

SAMPLE RATE (MSPS) 200 5 10 15

SNR/SFDR (dBc)

100

90

95

85

80

75

65

70

55

60

50

SFDR (2V DIFF)

SNR (2V DIFF)

SFDR (2V SE)

SNR (2V SE)

Figure 14. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz)

AD9235

Rev. C | Page 12 of 40

02461-015

AIN (dBFS) 0–30 –25 –20 –15 –10 –5

SNR/SFDR (dBFS and dBc)

100

90

80

70

60

50

40

SFDR

SINGLE-ENDED (dBFS)

SFDR

DIFFERENTIAL (dBc)

SNR

DIFFERENTIAL (dBFS)

SFDR

SINGLE-ENDED (dBc)

SNR

DIFFERENTIAL (dBc)

SNR

SINGLE-ENDED (dBc)

SFDR

DIFFERENTIAL (dBFS)

SNR

SINGLE-ENDED (dBFS)

Figure 15. AD9235-65: Single Tone SNR/SFDR vs.

AIN with fIN = Nyquist (32.5 MHz)

02461-016

AIN (dBFS) 0–30 –25 –20 –15 –10 –5

SNR/SFDR (dBFS and dBc)

100

90

80

70

60

50

40

SFDR

SINGLE-ENDED

(dBFS)

SNR

DIFFERENTIAL (dBc)

SNR

SINGLE-ENDED (dBc)

SNR

DIFFERENTIAL

(dBFS)

SNR

SINGLE-ENDED

(dBFS) SFDR

SINGLE-ENDED (dBc)

SFDR

DIFFERENTIAL

(dBc)

SFDR

DIFFERENTIAL (dBFS)

Figure 16. AD9235-40: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (20 MHz)

02461-017

AIN (dBFS) 0–30 –25 –20 –15 –10 –5

SNR/SFDR (dBFS and dBc)

100

90

80

70

60

50

40

SNR

DIFFERENTIAL(dBc)

SNR

SINGLE-ENDED (dBc)

SNR

DIFFERENTIAL (dBFS)

SNR

SINGLE-ENDED (dBFS)

SFDR

DIFFERENTIAL (dBc)

SFDR

SINGLE-ENDED (dBFS)

SFDR DIFFERENTIAL (dBFS)

SFDR

SINGLE-ENDED(dBc)

Figure 17. AD9235-20: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (10 MHz)

02461-018

INPUT FREQUENCY (MHz) 1250 25 50 75 100

SNR/SFDR (dBc)

95

90

85

80

75

70

65

SNR

SFDR

Figure 18. AD9235-65: SNR/SFDR vs. fIN

02461-019

INPUT FREQUENCY (MHz) 1250 25 50 75 100

SNR/SFDR (dBc)

95

90

85

80

75

70

65

SNR

SFDR

Figure 19. AD9235-40: SNR/SFDR vs. fIN

02461-020

INPUT FREQUENCY (MHz) 1250 25 50 75 100

SNR/SFDR (dBc)

95

90

85

80

75

70

65

SNR

SFDR

Figure 20. AD9235-20: SNR/SFDR vs. fIN

AD9235

Rev. C | Page 13 of 40

02461-021

FREQUENCY (MHz) 65.032.5 39.0 45.5 52.0 58.5

MAGNITUDE (dBFS)

0

–20

–40

–60

–80

–100

–120

SNR = 64.6dBFS

SFDR = 81.6dBFS

Figure 21. Dual Tone 8K FFT with fIN1 = 45 MHz and fIN2 = 46 MHz

02461-022

FREQUENCY (MHz) 97.565.0 71.5 78.0 84.5 91.0

MAGNITUDE (dBFS)

0

–20

–40

–60

–80

–100

–120

SNR = 64.3dBFS

SFDR = 81.1dBFS

Figure 22. Dual Tone 8K FFT with fIN1 = 69 MHz and fIN2 = 70 MHz

02461-023

FREQUENCY (MHz) 162.0130.0 136.5 143.0 149.5 156.0

MAGNITUDE (dBFS)

0

–20

–40

–60

–80

–100

–120

SNR = 62.5dBFS

SFDR = 75.6dBFS

Figure 23. Dual Tone 8K FFT with fIN1 = 144 MHz and fIN2 = 145 MHz

02461-024

A

IN

(dBFS) –6–24 –21 –18 –15 –12 –9

SNR/SFDR (dBFS)

95

90

85

80

75

70

65

60

1V SNR

1V SFDR

2V SNR

2V SFDR

Figure 24. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz

02461-025

A

IN

(dBFS) –6–24 –21 –18 –15 –12 –9

SNR/SFDR (dBFS)

95

90

85

80

75

70

65

60

1V SNR

1V SFDR

2V SNR

2V SFDR

Figure 25. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz and fIN2 = 70 MHz

02461-026

A

IN

(dBFS) –6–24 –21 –18 –15 –12 –9

SNR/SFDR (dBFS)

95

90

85

80

75

70

65

60

1V SNR

1V SFDR

2V SNR

2V SFDR

Figure 26. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz and fIN2 = 145 MHz

AD9235

Rev. C | Page 14 of 40

02461-027

SAMPLE RATE (MSPS) 6001020304050

ENOB (Bits)

9.7

12.2

11.7

11.2

10.7

10.2

SINAD (dBc)

75

72

69

66

63

60

AD9235-65:

1V SINAD

AD9235-40:

2V SINAD AD9235-65:

2V SINAD

AD9235-20:

2V SINAD

AD9235-20:

1V SINAD AD9235-40:

1V SINAD

Figure 27. SINAD vs. fCLK with fIN = Nyquist

02461-028

DUTY CYCLE (%) 6535 40 45 50 55 60

SINAD/SFDR (dBc)

90

80

70

60

50

40

30

SINAD: DCS OFF

SFDR: DCS OFF

SFDR: DCS ON

SINAD: DCS ON

Figure 28. SINAD/SFDR vs. Clock Duty Cycle

02461-029

SAMPLE RATE (MSPS) 80–40–30–20–100 10203040506070

SINAD/SFDR (dBc)

90

85

80

75

70

60

55

65

50

SINAD 2V DIFF

SINAD 1V DIFF

SFDR 1V DIFF

SFDR 2V DIFF

Figure 29. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz

02461-030

TEMPERATURE (°C) 80–40 0–20 204060

GAIN DRAFT (ppm/°C)

20

15

10

5

0

–5

–10

–15

–20

Figure 30. A/D Gain vs. Temperature Using an External Reference

02461-031

CODE 40000 500 1000 1500 2000 2500 3000 3500

INL (LSB)

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

Figure 31. Typical INL

02461-032

CODE 40000 500 1000 1500 2000 2500 3000 3500

DNL (LSB)

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

Figure 32. Typical DNL

AD9235

Rev. C | Page 15 of 40

APPLYING THE AD9235

THEORY OF OPERATION

The AD9235 architecture consists of a front end SHA followed

by a pipelined switched capacitor ADC. The pipelined ADC is

divided into three sections, consisting of a 4-bit first stage

followed by eight 1.5-bit stages and a final 3-bit flash. Each stage

provides sufficient overlap to correct for flash errors in the

preceding stages. The quantized outputs from each stage are

combined into a final 12-bit result in the digital correction logic.

The pipelined architecture permits the first stage to operate on a

new input sample while the remaining stages operate on

preceding samples. Sampling occurs on the rising edge

of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be ac- or

dc-coupled in differential or single-ended modes. The output-

staging block aligns the data, carries out the error correction,

and passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing adjustment of the

output voltage swing. During power-down, the output buffers

go into a high impedance state.

ANALOG INPUT

The analog input to the AD9235 is a differential switched

capacitor SHA that has been designed for optimum perform-

ance while processing a differential input signal. The SHA

input can support a wide common-mode range and maintain

excellent performance, as shown in Figure 34. An input

common-mode voltage of midsupply minimizes signal-

dependent errors and provides optimum performance.

Referring to Figure 33, the clock signal alternatively switches the

SHA between sample mode and hold mode. When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can be

placed across the inputs to provide dynamic charging currents.

This passive network creates a low-pass filter at the ADC’s

input; therefore, the precise values are dependent upon the

application. In IF undersampling applications, any shunt

capacitors should be removed. In combination with the driving

source impedance, they would limit the input bandwidth.

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

VIN+

VIN–

C

PAR

C

PAR

5pF

T

02461-033

H

T

H

Figure 33. Switched-Capacitor SHA Input

An internal differential reference buffer creates positive and

negative reference voltages, REFT and REFB, respectively, that

define the span of the ADC core. The output common mode of

the reference buffer is set to midsupply, and the REFT and

REFB voltages and span are defined as:

REFT = ½(AV D D + VREF)

REFB = ½(AV D D − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage

and, by definition, the input span is twice the value of the

VREF voltage.

02461-034

COMMON-MODE LEVEL (V) 3.00 0.5 1.0 1.5 2.0 2.5

THD (dBc)

–50

–90

–75

–80

–85

–55

–60

–65

–70

SNR (dBc)

90

85

80

75

70

65

60

55

50

SNR 35MHz 2V DIFF

THD 35MHz 2V DIFF

THD 2.5MHz 2V DIFF

SNR 2.5MHz 2V DIFF

Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level

AD9235

Rev. C | Page 16 of 40

The internal voltage reference can be pin-strapped to fixed

values of 0.5 V or 1.0 V, or adjusted within the same range as

discussed in the Internal Reference Connection section. Maxi-

mum SNR performance is achieved with the AD9235 set to the

largest input span of 2 V p-p. The relative SNR degradation is

3 dB when changing from 2 V p-p mode to 1 V p-p mode.

The SHA may be driven from a source that keeps the signal

peaks within the allowable range for the selected reference volt-

age. The minimum and maximum common-mode input levels

are defined as:

VCMMIN = VREF/2

VCMMAX = (AV DD + VREF)/2

The minimum common-mode input level allows the AD9235 to

accommodate ground-referenced inputs.

Although optimum performance is achieved with a differential

input, a single-ended source may be driven into VIN+ or VIN–.

In this configuration, one input accepts the signal, while the

opposite input should be set to midscale by connecting it to an

appropriate reference. For example, a 2 V p-p signal may be

applied to VIN+ while a 1 V reference is applied to VIN–. The

AD9235 then accepts an input signal varying between 2 V and

0 V. In the single-ended configuration, distortion performance

may degrade significantly as compared to the differential case.

However, the effect is less noticeable at lower input frequencies and

in the lower speed grade models (AD9235-40 and AD9235-20).

Differential Input Configurations

As previously detailed, optimum performance is achieved while

driving the AD9235 in a differential input configuration. For

baseband applications, the AD8138 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8138 is easily set to

AVDD/2, and the driver can be configured in a Sallen-Key filter

topology to provide band limiting of the input signal.

AD9235

VIN+

VIN–

AVDD

1Vp-p 49.9Ω

523Ω

1kΩ

1kΩ0.1µF

22Ω

15pF

499Ω

AGND

02461-035

AD8138

Figure 35. Differential Input Configuration Using the AD8138

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9235. This is especially true in IF

undersampling applications where frequencies in the 70 MHz to

100 MHz range are being sampled. For these applications,

differential transformer coupling is the recommended input

configuration, as shown in Figure 36.

02461-036

AD9235

VIN+

VIN–

AVDD

49.9Ω

22Ω

15pF

AGND

1kΩ

0.1µF

2

Vp-p

Figure 36. Differential Transformer-Coupled Configuration

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is degra-

dation in SFDR and in distortion performance due to the large

input common-mode swing. However, if the source

impedances on each input are matched, there should be little

effect on SNR performance. Figure 37 details a typical single-

ended input configuration.

02461-037

AD9235

VIN+

VIN–

AVDD

49.9Ω

22Ω

15pF

AGND

1kΩ

2

Vp-p

0.33µF

0.1µF10µF

Figure 37. Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result, may be sensi-

tive to clock duty cycle. Commonly a 5% tolerance is required

on the clock duty cycle to maintain dynamic performance char-

acteristics. The AD9235 contains a clock duty cycle stabilizer

(DCS) that retimes the nonsampling edge, providing an internal

clock signal with a nominal 50% duty cycle. This allows a wide

range of clock input duty cycles without affecting the perform-

ance of the AD9235. As shown in Figure 30, noise and distor-

tion performance are nearly flat over a 30% range of duty cycle.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately 100 clock cycles to

allow the DLL to acquire and lock to the new rate.

AD9235

Rev. C | Page 17 of 40

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (fINPUT) due only to aperture jitter (tJ) can be

calculated by

SNR Degradation = −20 × log10[2π × fINPUT × tJ]

In the equation, the rms aperture jitter, tJ, represents the root-

sum square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9235. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other meth-

ods), it should be retimed by the original clock at the last step.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 38, the power dissipated by the AD9235 is

proportional to its sample rate. The digital power dissipation

does not vary substantially between the three speed grades

because it is determined primarily by the strength of the digital

drivers and the load on each output bit. The maximum DRVDD

current can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits, 12 in the case of the

AD9235. This maximum current occurs when every output bit

switches on every clock cycle, i.e., a full-scale square wave at the

Nyquist frequency, fCLK/2. In practice, the DRVDD current is

established by the average number of output bits switching,

which is determined by the encode rate and the characteristics

of the analog input signal.

02461-038

SAMPLE RATE (MSPS) 600 1020304050

TOTAL POWER (mW)

325

300

275

250

225

200

175

150

125

100

75

50 AD9235-20

AD9235-40

AD9235-65

Figure 38. Total Power vs. Sample Rate with fIN = 10 MHz

For the AD9235-20 speed grade, the digital power consumption

can represent as much as 10% of the total dissipation. Digital

power consumption can be minimized by reducing the capaci-

tive load presented to the output drivers. The data in Figure 38

was taken with a 5 pF load on each output driver.

The analog circuitry is optimally biased so that each speed

grade provides excellent performance while affording reduced

power consumption. Each speed grade dissipates a baseline

power at low sample rates that increases linearly with the clock

frequency.

By asserting the PDWN pin high, the AD9235 is placed in

standby mode. In this state, the ADC typically dissipates 1 mW

if the CLK and analog inputs are static. During standby, the

output drivers are placed in a high impedance state. Reasserting

the PDWN pin low returns the AD9235 into its normal

operational mode.

Low power dissipation in standby mode is achieved by shutting

down the reference, reference buffer, and biasing networks. The

decoupling capacitors on REFT and REFB are discharged when

entering standby mode and then must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in standby mode, and shorter standby

cycles result in proportionally shorter wake-up times. With the

recommended 0.1 µF and 10 µF decoupling capacitors on REFT

and REFB, it takes approximately 1 sec to fully discharge the

reference buffer decoupling capacitors and 3 ms to restore full

operation.

AD9235

Rev. C | Page 18 of 40

Table 7. Reference Configuration Summary

Selected Mode SENSE Voltage Internal Switch Position Resulting VREF (V) Resulting Differential Span (V p-p)

External Reference AVDD N/A N/A 2 × External Reference

Internal Fixed Reference VREF SENSE 0.5 1.0

Programmable Reference 0.2 V to VREF SENSE 0.5 × (1 + R2/R1) 2 × VREF (See Figure 40)

Internal Fixed Reference AGND to 0.2 V Internal Divider 1.0 2.0

DIGITAL OUTPUTS

The AD9235 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

As detailed in Table 8, the data format can be selected for either

offset binary or twos complement.

Timing

The AD9235 provides latched data outputs with a pipeline delay

of seven clock cycles. Data outputs are available one propaga-

tion delay (tPD) after the rising edge of the clock signal. Refer to

Figure 2 for a detailed timing diagram.

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9235;

these transients can detract from the converter’s dynamic

performance.

The lowest typical conversion rate of the AD9235 is 1 MSPS. At

clock rates below 1 MSPS, dynamic performance may degrade.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD9235. The input range can be adjusted by varying the refer-

ence voltage applied to the AD9235, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly.

If the ADC is being driven differentially through a transformer,

the reference voltage can be used to bias the center tap

(common-mode voltage).

Internal Reference Connection

A comparator within the AD9235 detects the potential at the

SENSE pin and configures the reference into one of four possi-

ble states, which are summarized in Table 7. If SENSE is

grounded, the reference amplifier switch is connected to the

internal resistor divider (see Figure 39), setting VREF to 1 V.

Connecting the SENSE pin to VREF switches the reference

amplifier output to the SENSE pin, completing the loop and

providing a 0.5 V reference output. If a resistor divider is

connected as shown in Figure 40, the switch is again set to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

VREF = 0.5 × (1 + R2/R1)

ADC

CORE

SELECT

LOGIC

AD9235

VIN–

VREF

SENSE

VIN+

REFB

REFT

10µF 0.1µF

0.1µF10µF

0.1µF

0.5V

02461-039

+

Figure 39. Internal Reference Configuration

In all reference configurations, REFT and REFB drive the A/D

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

02461-040

SENSE

ADC

CORE

SELECT

LOGIC

AD9235

VREF

VIN–

VIN+

REFB

REFT

10µF 0.1µF

0.1µF10µF

0.1µF

0.5V

R2

R1

+

Figure 40. Programmable Reference Configuration

AD9235

Rev. C | Page 19 of 40

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or to improve thermal drift

characteristics. When multiple ADCs track one another, a single

reference (internal or external) may be necessary to reduce gain

matching errors to an acceptable level. A high precision external

reference may also be selected to provide lower gain and offset

temperature drift. Figure 41 shows the typical drift characteris-

tics of the internal reference in both 1 V and 0.5 V modes.

02461-041

TEMPERATURE (°C) 80–40–30–20–100 10203040506070

VREF ERROR (%)

1.2

1.0

0.8

0.6

0.4

0.2

0

VREF = 1.0V

VREF = 0.5V

Figure 41. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1 V.

If the internal reference of the AD9235 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 42

depicts how the internal reference voltage is affected by loading.

02461-042

LOAD (mA) 3.00 0.5 1.0 1.5 2.0 2.5

ERROR (%)

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

0.5V ERROR (%)

1V ERROR (%)

Figure 42. VREF Accuracy vs. Load

OPERATIONAL MODE SELECTION

As discussed earlier, the AD9235 can output data in either offset

binary or twos complement format. There is also a provision for

enabling or disabling the clock DCS. The MODE pin is a multi-

level input that controls the data format and DCS state. The

input threshold values and corresponding mode selections are

outlined in Table 8.

Table 8. Mode Selection

MODE Voltage Data Format Duty Cycle Stabilizer

AVDD Twos Complement Disabled

2/3 AVDD Twos Complement Enabled

1/3 AVDD Offset Binary Enabled

AGND (Default) Offset Binary Disabled

The MODE pin is internally pulled down to AGND by a 20 kΩ

resistor.

TSSOP EVALUATION BOARD

The AD9235 evaluation board provides the support circuitry

required to operate the ADC in its various modes and configu-

rations. The converter can be driven differentially, through an

AD8138 driver or a transformer, or single-ended. Separate

power pins are provided to isolate the DUT from the support

circuitry. Each input configuration can be selected by proper

connection of various jumpers (refer to the schematics). Figure 43

shows the typical bench characterization setup used to evaluate

the ac performance of the AD9235. It is critical that signal

sources with very low phase noise (<1 ps rms jitter) be used to

realize the ultimate performance of the converter. Proper filter-

ing of the input signal, to remove harmonics and lower the inte-

grated noise at the input, is also necessary to achieve the speci-

fied noise performance.

The AUXCLK input should be selected in applications requiring

the lowest jitter and SNR performance, i.e., IF undersampling

characterization. It allows the user to apply a clock input signal

that is 4× the target sample rate of the AD9235. A low-jitter,

differential divide-by-4 counter, the MC100LVEL33D, provides

a 1× clock output that is subsequently returned back to the CLK

input via JP9. For example, a 260 MHz signal (sinusoid) is

divided down to a 65 MHz signal for clocking the ADC. Note

that R1 must be removed with the AUXCLK interface. Lower

jitter is often achieved with this interface since many RF signal

generators display improved phase noise at higher output

frequencies and the slew rate of the sinusoidal output signal is

4× that of a 1× signal of equal amplitude.

Complete schematics and layout plots follow and demonstrate

the proper routing and grounding techniques that should be

applied at the system level.

AD9235

Rev. C | Page 20 of 40

LFCSP EVALUATION BOARD

The typical bench setup used to evaluate the ac performance

of the AD9235 is similar to the TSSOP Evaluation Board

connections (refer to the schematics for connection details).

The AD9235 can be driven single-ended or differentially

through a transformer. Separate power pins are provided to

isolate the DUT from the support circuitry. Each input

configuration can be selected by proper connection of

various jumpers (refer to the schematics).

An alternative differential analog input path using an AD8351

op amp is included in the layout but is not populated in produc-

tion. Designers interested in evaluating the op amp with the

ADC should remove C15, R12, and R3 and populate the op amp

circuit. The passive network between the AD8351 outputs and

the AD9235 allows the user to optimize the frequency response

of the op amp for the application.

DATA

CAPTURE

AND

PROCESSING

3V

–+3V

–

+

3V

–+3V

–+

REFIN

10MHz

REFOUT

HP8644, 2V p-p

SIGNAL SYNTHESIZER

HP8644, 2V p-p

CLOCK SYNTHESIZER

BAND-PASS

FILTER S4

XFMR

INPUT

S1

CLOCK

AVDD DUT

AVDD

GND GND DUT

DRVDD DVDD

AD9235

TSSOP EVALUATION BOARD J1

CLOCK

DIVIDER

02461-043

Figure 43. TSSOP Evaluation Board Connections

AD9235

Rev. C | Page 21 of 40

R20

1kΩ

R17

1kΩ

R42

1kΩ

R27

5kΩ

R4

10kΩ

R3

10kΩ

D7OD7

D11O

D10O

D9O

D8O

D7O

D6O

D5O

D4O

D3O

D2O

D1O

D0O

JP7

C37

0.1µF

DUTAVDD

VIN+

VIN–

OTRO

C36

0.1µF

C50

0.1µFU1

JP22

JP23

JP13

AVDD

DUTCLK

WHT

TP6

WHT

TP17

DUTDRVDD

WHT

TP5

AD9235

D0

D1

D2

D4

D7

D11

OTR

AVDD

SENSE

PDWN

REFB

VIN+

VIN–

AVDD

DGND

DRVDD

D5

MODE

CLK

D3

D6

D8

D9

D10

AGND

VREF

REFT

AGND

SHEET 3

RP4 22Ω

4

C1

10µF

10V

C20

10µF

10V

C34

0.1µF

C35

0.1µF

C21

10µF

10V

C57

0.1µFC22

10µF

10V

C40

0.001µF

C33

0.1µF

C32

0.1µF

C39

0.001µF

5

7

8

3

4

14

5

6

2

9

10

11

12

23

24

1

28

27

26

25

22

21

20

19

18

17

16

15

13

C38

0.1µF

C23

10µF

10V

C41

0.001µF

JP25

JP24

JP6

JP1

JP2

AVDD

JP12

AGND

DUTAVDDIN

C59

0.1µF

TP2

RED

DUTAVDD

C58

22µF

25V

TB1 2

FBEAD

L1

21

TB1 3

AVDDIN

C52

0.1µF

TP1

RED

AVDD

C47

22µF

25V

TB1 1

FBEAD

L2

21

JP11

AGND

DRVDDIN

C53

0.1µF

TP3

RED

DUTDRVDD

C48

22µF

25V

TB1 5

FBEAD

L3

21

TB1 4

DVDDIN

C14

0.1µF

TP4

RED DVDD

C6

22µF

25V

TB1 6

TP11

BLK TP12

BLK TP13

BLK TP14

BLK

TP9

BLK TP10

BLK TP15

BLK TP16

BLK

FBEAD

L4

21

D6O D6

RP4 22Ω

3

6

D5OD5

RP4 22Ω

2

7

D4O D4

RP4 22Ω

1

8

D3OD3

RP3 22Ω

4

5

D2O D2

RP3 22Ω

3

6

D1OD1

RP3 22Ω

2

7

D0O D0

RP3 22Ω

1

8

OTRO OTR

RP6 22Ω

4

5

RP6 22Ω

3

6

RP6 22Ω

2

7

RP6 22Ω

1

8

D11O D11

RP5 22Ω

4

5

D10O D10

RP5 22Ω

3

6

D9OD9

RP5 22Ω

2

7

D8O D8

RP5 22Ω

1

8

02461-044

+

++

+

Figure 44. TSSOP Evaluation Board Schematic, DUT

AD9235

Rev. C | Page 22 of 40

WHT

TP7

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

10

8

6

4

2

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

9

5

7

3

1

HDR40RAM

J1

HEADER RIGHT ANGLE MALE NO EJECTORS

OTR

C11

0.1µF

D11

D10

D9

D8

DUTCLK

U7

74VHC541

182

11

12

13

14

15

16

17

20

10

19

1

9

8

7

6

5

4

3

AVDD AVDD; 14

AVDD; 7

21

1256

AVDD

JP4

D2

D1

AUXCLK

MC100LVEL33D

U3

6

5

7

8

4

3

2

1

C13

0.1µF

R1

49.9Ω

AVDD

1N5712

A2

A3

A4

A5

A6

A7

A8

G1

G2 GND

VCC

Y2

Y3

Y4

Y5

Y6

Y7

Y8

A1 Y1

74VHC04

U8

74VHC04

U8

1N5712

CW

NC

INA

INB

INCOM

VCC

OUT

VEE

REF

U8 DECOUPLING

R19

500Ω

R2

10Ω

R18

500Ω

R7

22Ω

R11

49.9Ω

R15

90Ω

R13

113Ω

R26

10kΩ

R25

10kΩ

C26

0.1µF

C28

10µF

10V

C24

0.1µF

C5

10µF

10V

D5

C12

0.1µF

D3

D2

D1

D0

U6

74VHC541

182

11

12

13

14

15

16

17

20

10

19

1

9

8

7

6

5

4

3

21

A2

A3

A4

A5

A6

A7

A8

G1

G2 GND

VCC

Y2

Y3

Y4

Y5

Y6

Y7

Y8

A1 Y1

C4

10µF

10V

D4

D6

D7

DVDD

RP2 22Ω

8

9

RP2 22Ω

7

10

RP2 22Ω

6

11

RP2 22Ω

5

12

RP2 22Ω

4

13

RP2 22Ω

3

14

RP2 22Ω

2

15

RP2 22Ω

1

16

RP2 22Ω

8

9

RP2 22Ω

7

10

RP2 22Ω

6

11

RP2 22Ω

5

12

RP2 22Ω

4

13

RP2 22Ω

3

14

RP2 22Ω

2

15

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

DACLK

DOTR

DD11

DD10

DD9

DD8

RP2 22Ω

1

16

T2

T1–1T

6

1

252

1

34

S5

CLOCK

1

2

S1

R14

90Ω

R12

113Ω

C27

0.1µF

AVDD

U9 DECOUPLING

C8

10µF

10V

C10

0.1µF

JP9

34

74VHC04

U8 JP3

13 12

74VHC04

U8

11 10

U8

98

74VHC04

U8

02461-045

R9

22Ω

+

Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering

AD9235

Rev. C | Page 23 of 40

R32

1kΩ

R23

1kΩ

R16

1kΩ

C18

0.1µF

C2

VAL

C9

0.33µF

S2 2

1

21

AVDD

C7

0.1µF

R5

49.9Ω

C8

0.1µF

C16

0.1µF

C25

0.33µF

R37

499Ω

R6

40Ω

R10

40Ω

JP8

2

31

C15

10µF

10V

21C69

0.1µF

TP8

RED

JP5

C17

VAL

R8

1kΩ

AVDD

R41

1kΩ

R33

1kΩ

AVDD

AMP INPUT

S4 2

1

XFMR INPUT

ALT VEE

R34

523Ω

R35

499Ω

R31

49.9Ω

R36

499Ω

C19

10µF

10V

3

6

4

5

2

8

1

AD8138

U2

AB

C42

VAL

C45

VAL

T2

T1–1T

6

52

1

34

S3 2

1

SINGLE INPUT

JP46

C43

15pF

R22

22ΩVIN–

JP41

JP43

JP45

C44

15pF

R21

22ΩVIN+

JP40

JP42

C44B

02461-046

R24

49.9Ω

+IN VEE

VO– VOC

VO+

VCC

–IN

+

Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs

DD11

DD10

DD9

DD8

DD7

DD6

DD5

DD4

DD3

DD2

C30

0.1µFC31

0.01µF

C49

0.1µFC51

0.1µFC54

22pF

R28

49.9Ω

R29

49.9Ω

C55

22pF

C56

0.1µF

R30

2kΩ

DACLK

DD0

DD1

DVDD

S6

WHT

TP18

AD9762

U4

NC2

DB10

DB19

DB8

DB7

DB6

DB5

DB4

DB3

NC1

DB0

DB1

DB2

SLEEP

REFLO

REFIO

FSADJ

COMP1

ACOM

IOUTB

IOUTA

COMP2

AVDD

NC3

DCOM

DVDD

CLOCKMSB-DB11

02461-047

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

C29

0.1µFC46

0.01µF

Figure 47. TSSOP Evaluation Board Schematic, Optional DAC

AD9235

Rev. C | Page 24 of 40

02461-048

Figure 48. TSSOP Evaluation Board Layout, Primary Side

AD9235

Rev. C | Page 25 of 40

02461-049

Figure 49. TSSOP Evaluation Board Layout, Secondary Side

AD9235

Rev. C | Page 26 of 40

02461-050

Figure 50. TSSOP Evaluation Board Layout, Ground Plane

AD9235

Rev. C | Page 27 of 40

_

02461-051

Figure 51. TSSOP Evaluation Board Power Plane

AD9235

Rev. C | Page 28 of 40

02461-052

Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen

AD9235

Rev. C | Page 29 of 40

02461-053

Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen

AD9235

Rev. C | Page 30 of 40

123456

P13

P14

XFRIN1

NC

R SINGLE ENDED

R18

25Ω

EXTREF

1V MAX E1

R1

10kΩ

GND AVDD

GND

C22

10µF

GND

C8

0.1µF

P5

P6

P11

P1

P3

P4

22 MODE

REFB

REFT

AVDD

AGND

VIN+

AGND

AVDD

VIN–

AD9235

U4

VREF

SENSE

MODE

D11

OTR

D10

D9

D8

DRVDD

DGND

D7

D5

D6

D4

D3

D2

(LSB)

DRVDD

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

D6X

D5X

D4X

D2X

D3X

D1X

D0X

(MSB)

OVERRANGE BIT

AVDD

GND

DRVDD

VDL

GND

VAMP

P2

H1

MTHOLE6

3.0V

2.5V

5.0V

RP1 220Ω

R8

1kΩ

CLK

AVDD

R15

33Ω

GND

GND OR L1

FOR FILTER

GND

AVDD

R36

1kΩ

R26

1kΩ

GND

AVDD

GND

VIN+

VIN–

C19

15pF

C21

10pF

R2

XX

R10

36Ω

R42

0Ω

R12

0Ω

X

OUT

X

OUT

AMPIN

GND

X

OUT

B

X

OUT

B

R3

0Ω

R11

36Ω

C26

10pF

E 45

C16

0.1µF

C6

0.1µF

G

ND

AMP

C15

0.1µF

L1

10nH

GND

PRI SEC

GND

C18

0.1µF

J1

R7

1kΩ

2.5V

SENSE PIN SOLDERABLE JUMPER

E TO A EXTERNAL VOLTAGE DIVIDER

E TO B INTERNAL 1V REFERENCE (DEFAULT)

E TO C EXTERNAL REFERENCE

E TO D INTERNAL 0.5V REFERENCE

MODE PIN SOLDERABLE JUMPER

5 TO 1 TWOS COMPLEMENT/DCS OFF

5 TO 2 TWOS COMPLEMENT/DCS OFF

5 TO 3 OFFSET BINARY/DCS ON

5 TO 4 OFFSET BINARY/DCS OFF

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

DNC

CLK

DNC

PDWN

DNC

D0

D1

1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DRX

D13X

D12X

D10X

D11X

D9X

D8X

RP2 220Ω

H2

MTHOLE6

H3

MTHOLE6

H4

MTHOLE6

GND

3

R6

1kΩ

4

1

R5

1kΩ

GND

AVDDGND

D

C13

0.10µF

C

E

P8

B

P9

P10

P7 A

C29

10µF

GND

R9

10kΩ

GND

C12

0.1µF

GND

C9

0.10µFC11

0.1µF

GND

C7

0.1µF

R4

33kΩ

AVDD R13

1kΩ

R25

1kΩGND

GND C23

10pF

C5

0.1µF

AMPINB

T1

ADT 1–1 WT

1

52

6

43

X FRIN

GND

PRI SEC

OPTIONAL XFR

T2

FT C1–1–13

1

2

5

43

CT

R3, R17, R18

ONLY ONE SHOULD BE

ON BOARD AT A TIME

02461-054

+

D7X

Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT

AD9235

Rev. C | Page 31 of 40

DRX

D13X

GND

D2X

D1X

GND D0X

D11X

D12X

DRVDD

D10X

D9X

GND D8X

D7X

D5X

D6X

GND D4X

D3X

DRVDD

2CLK

2DB

2D7

GND

2D6

2D5

VCC

1D2

1D1

1CLK

2D4

2D3

GND

2D2

2D1

1D7

1D6

1D5

1D8

GND

VCC

1D4

1D3

GND

2QB

2Q7

GND

2Q6

2Q5

VCC

1Q2

1Q1

1OE

2Q4

2Q3

GND

2Q2

2Q1

1Q8

1Q7

1Q6

1Q5

GND

VCC

1Q4

1Q3

GND

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IN OUT

CLKAT/DAC

1

74LVTH162374

U1

CLKLAT/DA

C

GND

DRYMSB

LSB

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

GND DR

MSB

GND GND

HEADER 40

DRY

DRVDD

GND

AMPIN

AMPINB

GND GND

GND

VAMP

C27

0.1µF

C28

0.1µF

C35

0.10µFC17

0.1µF

R16

0Ω

R14

25Ω

R40

10kΩPWDN

RGP1

INHI

INLO

RPG2

R41

10kΩ

R35

25Ω

R34

1.2kΩ

AMP IN

AMP

AD8351

U3

POWER DOWN

USE R40 OR R41

C44

0.1µF

COMM

OPLO

OPH1

VPOS

VOCM

5

4

2

3

1

6

9

10

R33

25Ω

R41

10kΩ

R19

50Ω

VAMP

R38

1kΩ

R39

1kΩ

GND

C24

10µF

GND

C45

0.1µF

GND

R17

0Ω

7

GND

8

02461-055

2OE

+

Figure 55. LFCSP Evaluation Board Schematic, Digital Path

AD9235

Rev. C | Page 32 of 40

CLOCK TIMING ADJUSTMENTS

FOR A BUFFERED ENCODE USE R28

FOR A DIRECT ENCODE USE R27

GND

ENCX

ENC

R32

1kΩR37

25Ω

R23

0Ω

R22

0Ω

Rx

DNP

R28

0Ω

E50 E51

ENC

CLK

VDL GND

GND

VDL

GND

PWR

C43

0.1µF

R31

1kΩ

R30

1kΩ

R29

50Ω

J2

GND

VDL

1Y

ENCX

1

2

1B

1A

DR

SCHEMATIC SHOWS TWO GATE DELAY SETUP

FOR ONE DELAY REMOVE R22 AND R3 7 AND

ATTACH Rx (Rx = 0Ω)

C49

0.001µF

C48

0.001µF

C47

0.1µF

C1

0.1µF

C39

0.001µF

C38

0.001µF

C36

0.1µF

C34

0.1µF

C31

0.1µF

C30

0.001µF

C2

22µF

DRVDD

GND

C37

0.1µFC40

0.001µF

C20

10µF

VDL

GND

C46

10µF

VAMP

GND

C14

0.001µFC41

0.1µF

C33

0.1µF

AVDD

DIGITAL BYPASSINGANALOG BYPASSING

DUT BYPASSING

LATCH BYPASSING

C32

0.001µF

C25

10µF

C3

10µF

C4

10µF

C10

22µF

2Y

4

5

2B

2A

3Y

9

10

3B

3A

4Y

12

13

3

6

7

8

11

14

4B

4A

CLKAT/DAC

R20

1kΩ

E52 E53

VDL GND

R21

1kΩ

E31 E35

VDL GND

R24

1kΩ

E43 E44

VDL GND

R27

0Ω

GND

VDL DRVDD AVDD

02461-056

ENCODE

GND

74VCX86

+

+++++

Figure 56. LFCSP Evaluation Board Schematic, Clock Input

AD9235

Rev. C | Page 33 of 40

02461-057

Figure 57. LFCSP Evaluation Board Layout, Primary Side

02461-058

Figure 58. LFCSP Evaluation Board Layout, Secondary Side

02461-059

Figure 59. LFCSP Evaluation Board Layout, Ground Plane

02461-060

Figure 60. LFCSP Evaluation Board Layout, Power Plane

AD9235

Rev. C | Page 34 of 40

02461-061

Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen

02461-062

Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen

AD9235

Rev. C | Page 35 of 40

Table 9. LFCSP Evaluation Board Bill of Materials (BOM)

Item Qty. Omit1Reference Designator Device Package Value

Recommended Vendor/

Part Number

Supplied

by ADI

18 C1, C5, C7, C8, C9, C11,

C12, C13, C15, C16, C31, C33,

C34, C36, C37, C41, C43, C47

1

8 C6, C18, C27, C17,

C28, C35, C45, C44

Chip Capacitor 0603 0.1 µF

8 C2, C3, C4, C10, C20,

C22, C25, C29

2

2 C46, C24

Tantalum Capacitor TAJD 10 µF

3 8 C14, C30, C32, C38,

C39, C40, C48, C49

Chip Capacitor 0603 0.001 µF

4 3 C19, C21, C23 Chip Capacitor 0603 10 pF

5 1 C26 Chip Capacitor 0603 10 pF

9 E31, E35, E43, E44,

E50, E51, E52, E53

6

2 E1, E45

Header EHOLE Jumper Blocks

7 2 J1, J2 SMA Connector/50 Ω SMA

8 1 L1 Inductor 0603 10 nH

Coilcraft/

0603CS-10NXGBU

9 1 P2 Terminal Block TB6 Wieland/25.602.2653.0,

z5-530-0625-0

10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND

5 R3, R12, R23, R28, RX 11

6 R37, R22, R42, R16, R17, R27

Chip Resistor 0603 0 Ω

12 2 R4, R15 Chip Resistor 0603 33 Ω

13 14 R5, R6, R7, R8, R13, R20,

R21, R24, R25, R26,

R30, R31, R32, R36

Chip Resistor 0603 1 k Ω

14 2 R10, R11 Chip Resistor 0603 36 Ω

1 R29 15

1 R19

Chip Resistor 0603 50 Ω

16 2 RP1, RP2 Resistor Pack R_742 220 Ω Digi-Key

CTS/742C163220JTR

17 1 T1 ADT1-1WT AWT1-1T Mini-Circuits

18 1 U1 74LVTH162374

CMOS Register

TSSOP-48

19 1 U4 AD9235BCP ADC (DUT) LFCSP-32 Analog Devices, Inc. X

20 1 U5 74VCX86M SOIC-14 Fairchild

21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X

22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. X

23 1 T2 MACOM Transformer ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13

24 5 R9, R1, R2, R38, R39 Chip Resistor 0603 SELECT

25 3 R18, R14, R35 Chip Resistor 0603 25 Ω

26 2 R40, R41 Chip Resistor 0603 10 k Ω

27 1 R34 Chip Resistor 1.2 k Ω

28 1 R33 Chip Resistor 100 Ω

Total 82 34

1 These items are included in the PCB design but are omitted at assembly.

AD9235

Rev. C | Page 36 of 40

OUTLINE DIMENSIONS

28 15

141

8°

0°

COMPLIANT TO JEDEC STANDARDS MO-153AE

SEATING

PLANE

COPLANARITY

0.10

1.20 MAX

6.40 BSC

0.65

BSC

PIN 1

0.30

0.19 0.20

0.09

4.50

4.40

4.30

0.75

0.60

0.45

9.80

9.70

9.60

0.15

0.05

Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.30

0.23

0.18

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

12° MAX

1.00

0.85

0.80 SEATING

PLANE

COPLANARITY

0.08

1

32

8

9

25

24

16

17

0.50

0.40

0.30

3.50 REF

0.50

BSC

PIN 1

INDICATO

R

TOP

VIEW

5.00

BSC SQ

4.75

BSC SQ 3.25

3.10 SQ

2.95

PIN 1

INDICATOR

0.60 MAX

0.25 MIN

EXPOSED

PAD

(BOTTOM VIEW)

Figure 64. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body (CP-32-2)

Dimensions shown in millimeters

AD9235

Rev. C | Page 37 of 40

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9235BRU-20 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRURL7-20 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRUZ-201–40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRUZRL7-201 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRU-40 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRURL7-40 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRUZ-401 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRUZRL7-401 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRU-65 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRURL7-65 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRUZ-651 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BRUZRL7-651 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28

AD9235BCP-202–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPRL7-202 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPZ-201, 2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPZRL7-201, 2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCP-402 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPRL7-402 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPZ-401, 2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPZRL7-401, 2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCP-652 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPRL7-652 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPZ-651, 2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235BCPZRL7-651, 2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP) CP-32-2

AD9235-20PCB TSSOP Evaluation Board

AD9235-40PCB TSSOP Evaluation Board

AD9235-65PCB TSSOP Evaluation Board

AD9235BCP-20EB LFCSP Evaluation Board

AD9235BCP-40EB LFCSP Evaluation Board

AD9235BCP-65EB LFCSP Evaluation Board

1 Z = Pb-free part.

2 It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of

the package is achieved with exposed paddle soldered to the customer board.

AD9235

Rev. C | Page 38 of 40

NOTES

AD9235

Rev. C | Page 39 of 40

NOTES

AD9235

Rev. C | Page 40 of 40

NOTES

registered trademarks are the property of their respective owners.

C02461–0–10/04(C)