12-Bit, 20/40/65 MSPS 3 V A/D Converter AD9235 FEATURES FUNCTIONAL BLOCK DIAGRAM DRVDD AVDD VIN+ SHA 8-STAGE 1 1/2-BIT PIPELINE MDAC1 VIN- 4 REFT A/D 16 3 A/D REFB CORRECTION LOGIC 12 OTR OUTPUT BUFFERS D11 AD9235 VREF D0 APPLICATIONS Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes CLOCK DUTY CYCLE STABILIZER SENSE REF SELECT MODE SELECT 0.5V AGND CLK PDWN MODE DGND 02461-001 Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dBc to Nyquist at 65 MSPS SFDR = 85 dBc to Nyquist at 65 MSPS Low power: 300 mW at 65 MSPS Differential input with 500 MHz bandwidth On-chip reference and SHA DNL = 0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer Figure 1. GENERAL DESCRIPTION The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters (ADCs). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead TSSOP and a 32-lead LFCSP and is specified over the industrial temperature range (-40C to +85C). PRODUCT HIGHLIGHTS 1. The AD9235 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation. 4. The AD9235 pinout is similar to the AD9214-65, a 10-bit, 65 MSPS ADC. This allows a simplified upgrade path from 10 bits to 12 bits for 65 MSPS systems. 5. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 6. The OTR output bit indicates when the signal is beyond the selected input range. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD9235 TABLE OF CONTENTS Specifications..................................................................................... 3 Applying the AD9235 .................................................................... 15 DC Specifications ......................................................................... 3 Theory of Operation.................................................................. 15 Digital Specifications ................................................................... 4 Analog Input ............................................................................... 15 Switching Specifications .............................................................. 4 Clock Input Considerations...................................................... 16 AC Specifications.......................................................................... 5 Power Dissipation and Standby Mode .................................... 17 Absolute Maximum Ratings............................................................ 7 Digital Outputs ........................................................................... 18 Explanation of Test Levels........................................................... 7 Voltage Reference ....................................................................... 18 ESD Caution.................................................................................. 7 Operational Mode Selection ..................................................... 19 Pin Configurations and Function Descriptions ........................... 8 TSSOP Evaluation Board .......................................................... 19 Definitions of Specifications ........................................................... 9 LFCSP Evaluation Board........................................................... 20 Equivalent Circuits ......................................................................... 10 Outline Dimensions ....................................................................... 36 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 37 REVISION HISTORY 10/04--Data Sheet changed from Rev. B to Rev. C Changes to Format .............................................................Universal Changes to Specifications .................................................................3 Changes to the Ordering Guide.................................................... 37 5/03--Data Sheet changed from Rev. A to Rev. B Added CP-32 Package (LFCSP)........................................Universal Changes to Several Pin Names .........................................Universal Changes to Features...........................................................................1 Changes to Product Description .....................................................1 Changes to Product Highlights........................................................1 Changes to Specifications .................................................................2 Replaced Figure 1 ..............................................................................3 Changes to Absolute Maximum Ratings ........................................5 Changes to Ordering Guide .............................................................5 Changes to Pin Function Descriptions...........................................6 New Definitions of Specifications Section .....................................7 Changes to TPCs 1 to 12...................................................................9 Changes to Theory of Operation Section.................................... 13 Changes to Analog Input Section..................................................13 Changes to Single-ended Input Configuration Section .............14 Replaced Figure 8 ............................................................................14 Changes to Clock Input Considerations Section ........................14 Changes to Table I ...........................................................................15 Changes to Power Dissipation and Standby Mode Section .......15 Changes to Digital Outputs Section..............................................15 Changes to Timing Section ............................................................15 Changes to Figure 13.......................................................................16 Changes to Figures 16 to 26 ...........................................................17 Added LFCSP Evaluation Board Section .....................................17 Inserted Figures 27 to 35 ................................................................25 Added Table III ................................................................................30 Updated Outline Dimensions........................................................31 8/02--Data Sheet changed from Rev. 0 to Rev. A Updated RU-28 Package................................................................ 24 Rev. C | Page 2 of 40 AD9235 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input4 Sine Wave Input2 Standby Power5 Temp Full Test Level VI AD9235BRU/BCP-20 Min Typ Max 12 AD9235BRU/BCP-40 Min Typ Max 12 AD9235BRU/BCP-65 Min Typ Max 12 Full Full Full Full 25C Full 25C VI VI VI IV I IV I 12 12 12 Full Full V V 2 12 Full Full Full Full VI V V V 5 0.8 2.5 0.1 25C 25C V V 0.54 0.27 0.54 0.27 0.54 0.27 LSB rms LSB rms Full Full Full Full IV IV V V 1 2 7 7 1 2 7 7 1 2 7 7 V p-p V p-p pF k Full Full IV IV Full Full Full V V V 30 2 0.01 Full Full Full V VI V 90 95 1.0 0.30 0.30 0.35 0.35 0.45 0.40 2.7 2.25 3.0 3.0 1.20 2.40 0.65 0.50 0.50 0.35 0.35 0.50 0.40 0.80 1.20 2.50 0.75 0.50 0.50 0.40 0.35 0.70 0.45 0.90 2 12 35 3.6 3.6 5 0.8 2.5 0.1 2.7 2.25 3.0 3.0 1 165 180 1.0 1.30 3 12 35 3.6 3.6 55 5 0.01 110 1.20 2.60 0.80 5 0.8 2.5 0.1 2.7 2.25 3.0 3.0 300 320 1.0 Bits % FSR % FSR LSB LSB LSB LSB ppm/C ppm/C 35 3.6 3.6 100 7 0.01 205 Unit Bits mV mV mV mV V V mA mA % FSR 350 mW mW mW Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND). 2 Rev. C | Page 3 of 40 AD9235 DIGITAL SPECIFICATIONS Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS1 DRVDD = 3.3 V High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) DRVDD = 2.5 V High-Level Output Voltage (IOH = 50 A) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 A) 1 Temp Test Level AD9235BRU/BCP-20 Min Typ Max AD9235BRU/BCP-40 Min Typ Max AD9235BRU/BCP-65 Min Typ Max Full Full Full Full Full IV IV IV IV V 2.0 2.0 2.0 Full IV 3.29 3.29 3.29 V Full IV 3.25 3.25 3.25 V Full IV 0.2 0.2 0.2 V Full IV 0.05 0.05 0.05 V Full IV 2.49 2.49 2.49 V Full IV 2.45 2.45 2.45 V Full IV 0.2 0.2 0.2 V Full IV 0.05 0.05 0.05 V 0.8 +10 +10 -10 -10 0.8 +10 +10 -10 -10 2 0.8 +10 +10 -10 -10 2 2 Unit V V A A pF Output voltage levels measured with 5 pF load on each output. SWITCHING SPECIFICATIONS Table 3. Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse-Width High1 CLK Pulse-Width Low1 DATA OUTPUT PARAMETERS Output Delay2 (tPD) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty Jitter (tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME 1 2 3 Temp Test Level AD9235BRU/BCP-20 Min Typ Max AD9235BRU/BCP-40 Min Typ Max AD9235BRU/BCP-65 Min Typ Max Full Full Full Full Full VI V V V V 20 40 65 Full Full Full Full Full Full V V V V V V 1 50.0 15.0 15.0 1 25.0 8.8 8.8 3.5 7 1.0 0.5 3.0 1 1 15.4 6.2 6.2 3.5 7 1.0 0.5 3.0 1 For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models. Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB. Rev. C | Page 4 of 40 3.5 7 1.0 0.5 3.0 2 Unit MSPS MSPS ns ns ns ns Cycles ns ps rms ms Cycles AD9235 N+1 N N+2 N-1 tA ANALOG INPUT N+8 N+3 N+7 N+4 N+5 N+6 DATA OUT N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 tPD = 6.0ns MAX 2.0ns MIN N 02461-002 CLK Figure 2. Timing Diagram AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = -0.5 dBFS, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 4. Parameter SIGNAL-TO-NOISE RATIO fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz TOTAL HARMONIC DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz WORST HARMONIC (SECOND OR THIRD) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz Temp Test Level 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V Full Full Full IV IV IV AD9235BRU/BCP-20 Min Typ Max 70.0 AD9235BRU/BCP-40 Min Typ Max 70.8 70.4 70.6 AD9235BRU/BCP-65 Min Typ Max 70.6 69.9 70.5 69.9 68.7 68.5 69.7 70.1 68.3 70.6 70.3 70.5 70.5 70.4 69.7 dBc dBc dBc dBc dBc dBc dBc dBc 70.2 70.3 68.3 68.6 68.3 69.5 69.9 67.8 -88.0 -86.0 -87.4 -89.0 -87.5 -79.0 -85.5 -86.0 -84.0 -90.0 dBc dBc dBc dBc dBc dBc dBc dBc 70.3 70.4 68.7 -79.0 -81.8 -82.0 -78.0 -82.5 -74.0 -80.0 -90.0 -80.0 -83.5 Rev. C | Page 5 of 40 Unit -74.0 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9235 Parameter SPURIOUS-FREE DYNAMIC RANGE fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz Temp Test Level 25C Full 25C Full 25C Full 25C 25C V IV I IV I IV I V AD9235BRU/BCP-20 Min Typ Max 80.0 AD9235BRU/BCP-40 Min Typ Max 92.0 88.5 91.0 AD9235BRU/BCP-65 Min Typ Max 92.0 80.0 92.0 89.0 90.0 74.0 84.0 Rev. C | Page 6 of 40 85.0 83.0 85.0 80.5 Unit dBc dBc dBc dBc dBc dBc dBc dBc AD9235 ABSOLUTE MAXIMUM RATINGS Table 5. With Respect to Pin Name ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD DGND Digital Outputs CLK, MODE AGND VIN+, VIN- AGND VREF AGND SENSE AGND REFB, REFT AGND PDWN AGND ENVIRONMENTAL1 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature 1 Min Max Unit -0.3 -0.3 -0.3 -3.9 -0.3 +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 V V V V V -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 V V V V V V -40 +85 150 300 +150 C C C C -65 Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. EXPLANATION OF TEST LEVELS Test Levels I II III IV V VI Description 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. Typical thermal impedances (28-lead TSSOP), JA = 67.7C/W; (32-lead LFCSP), JA = 32.5C/W, JC = 32.71C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 7 of 40 AD9235 D10 SENSE 3 26 D9 VREF 4 25 D8 REFB 5 AD9235 24 DRVDD REFT 6 TOP VIEW (Not to Scale) 23 DGND 7 22 D7 AGND 8 21 D6 VIN+ 9 20 D5 VIN- 10 19 D4 AGND 11 18 D3 AVDD 12 17 D2 CLK 13 16 D1 PDWN 14 15 D0 (LSB) AVDD DNC CLK DNC PDWN DNC DNC (LSB)D0 D1 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD9235 TOP VIEW (Not to Scale) 24 VREF 23 SENSE 22 MODE 21 OTR 20 D11(MSB) 19 D10 18 D9 17 D8 DNC = DO NOT CONNECT Figure 3. 28-Lead TSSOP Pin Configuration 02461-004 D11 (MSB) 27 D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 DGND 15 DRVDD 16 28 02461-003 OTR 1 MODE 2 32 AVDD 31 AGND 30 VIN- 29 VIN+ 28 AGND 27 AVDD 26 REFT 25 REFB PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 32-Lead LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. 28-Lead TSSOP 1 2 3 4 5 6 7, 12 8, 11 9 10 13 14 15 to 22, 25 to 28 23 24 Pin No. 32-Lead LFCSP 21 22 23 24 25 26 27, 32 28, 31 29 30 2 4 7 to 14, 17 to 20 15 16 Mnemonic OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN- CLK PDWN D0 (LSB) to D11 (MSB) DGND DRVDD 1, 3, 5, 6 DNC Description Out-of-Range Indicator. Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. Reference Mode Selection. Voltage Reference Input/Output. Differential Reference (-). Differential Reference (+). Analog Power Supply. Analog Ground. Analog Input Pin (+). Analog Input Pin (-). Clock Input Pin. Power-Down Function Selection (Active High). Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DGND with a minimum. 0.1 F capacitor. Recommended decoupling is 0.1 F in parallel with 10 F. Do Not Connect. Rev. C | Page 8 of 40 AD9235 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Jitter (tJ) The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD)1 The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. 1 Signal-to-Noise and Distortion (SINAD)1 The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Effective Number of Bits (ENOB) The ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula N = (SINAD - 1.76)/6.02 Signal-to-Noise Ratio (SNR)1 The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR)1 The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Two-Tone SFDR1 The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulse Width and Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse-width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tPD) The delay between the clock logic threshold and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. C | Page 9 of 40 AD9235 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN- 02461-007 02461-005 D11-D0, OTR Figure 5. Equivalent Analog Input Circuit Figure 7. Equivalent Digital Output Circuit AVDD AVDD CLK, PDWN 02461-008 20k 02461-006 MODE Figure 6. Equivalent MODE Input Circuit Figure 8. Equivalent Digital Input Circuit Rev. C | Page 10 of 40 AD9235 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS disabled, TA = 25C, 2 V differential input, AIN = -0.5 dBFS, VREF = 1.0 V, unless otherwise noted. 0 100 SNR = 70.3dBc SINAD = 70.2dBc ENOB = 11.4 BITS THD = -86.3dBc SFDR = 89.9dBc SFDR (2V DIFF) 95 90 85 -40 SNR/SFDR (dBc) -60 -80 80 SNR (2V SE) 75 70 65 SNR (2V DIFF) 60 -100 55 0 6.5 13.0 19.5 FREQUENCY (MHz) 26.0 32.5 SFDR (2V SE) 50 40 02461-009 -120 Figure 9. Single Tone 8K FFT with fIN = 10 MHz 50 55 SAMPLE RATE (MSPS) 60 65 Figure 12. AD9235-65: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (32.5 MHz) 100 0 SNR = 69.4dBc SINAD = 69.1dBc ENOB = 11.2 BITS THD = -81.0dBc SFDR = 83.8dBc -20 95 90 85 -40 SNR/SFDR (dBc) MAGNITUDE (dBFS) 45 02461-012 MAGNITUDE (dBFS) -20 -60 -80 SFDR (2V DIFF) 80 SNR (2V SE) 75 SNR (2V DIFF) 70 65 SFDR (2V SE) 60 -100 78.0 84.5 FREQUENCY (MHz) 91.0 50 20 02461-010 71.5 Figure 10. Single Tone 8K FFT with fIN = 70 MHz 30 SAMPLE RATE (MSPS) 35 40 Figure 13. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz) 100 0 SNR = 68.5dBc SINAD = 66.5dBc ENOB = 10.8 BITS THD = -71.0dBc SFDR = 71.2dBc -20 SFDR (2V DIFF) 95 90 85 SNR/SFDR (dBc) -40 -60 -80 SFDR (2V SE) 80 75 SNR (2V SE) 70 65 SNR (2V DIFF) 60 -100 104.0 110.5 117.0 FREQUENCY (MHz) 123.5 Figure 11. Single Tone 8K FFT with fIN = 100 MHz 130.0 50 0 5 10 SAMPLE RATE (MSPS) 15 20 02461-014 55 -120 97.5 02461-011 MAGNITUDE (dBFS) 25 02461-013 55 -120 65.0 Figure 14. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz) Rev. C | Page 11 of 40 AD9235 100 SFDR SINGLE-ENDED (dBFS) 95 SFDR DIFFERENTIAL (dBFS) 90 SFDR DIFFERENTIAL (dBc) SFDR SNR DIFFERENTIAL (dBFS) 80 85 SNR/SFDR (dBc) SNR/SFDR (dBFS and dBc) 90 70 SNR SINGLE-ENDED (dBFS) 60 SFDR SINGLE-ENDED (dBc) SNR SINGLE-ENDED (dBc) 50 80 75 SNR 70 -20 -15 AIN (dBFS) -10 -5 0 65 02461-015 -25 0 90 125 70 SNR SINGLE-ENDED (dBFS) SFDR SINGLE-ENDED (dBc) SNR DIFFERENTIAL (dBc) SFDR 85 SNR/SFDR (dBc) SNR/SFDR (dBFS and dBc) SFDR SINGLE-ENDED (dBFS) SFDR DIFFERENTIAL SNR DIFFERENTIAL (dBc) (dBFS) 60 100 95 SFDR DIFFERENTIAL (dBFS) 90 80 50 75 INPUT FREQUENCY (MHz) Figure 18. AD9235-65: SNR/SFDR vs. fIN Figure 15. AD9235-65: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (32.5 MHz) 100 25 02461-018 SNR DIFFERENTIAL (dBc) 40 -30 80 75 SNR 70 50 SNR SINGLE-ENDED (dBc) -15 AIN (dBFS) -10 -5 0 65 0 25 50 75 INPUT FREQUENCY (MHz) 100 125 02461-019 -20 125 02461-020 -25 02461-016 40 -30 Figure 19. AD9235-40: SNR/SFDR vs. fIN Figure 16. AD9235-40: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (20 MHz) 95 100 SFDR DIFFERENTIAL (dBFS) SFDR SINGLE-ENDED (dBFS) 80 SNR DIFFERENTIAL (dBFS) SFDR DIFFERENTIAL (dBc) 90 SFDR SFDR SINGLE-ENDED(dBc) 85 SNR/SFDR (dBc) SNR/SFDR (dBFS and dBc) 90 70 SNR SINGLE-ENDED (dBFS) 60 SNR DIFFERENTIAL(dBc) 75 SNR 70 50 SNR SINGLE-ENDED (dBc) -25 -20 -15 AIN (dBFS) -10 -5 0 02461-017 40 -30 80 Figure 17. AD9235-20: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (10 MHz) Rev. C | Page 12 of 40 65 0 25 50 75 INPUT FREQUENCY (MHz) 100 Figure 20. AD9235-20: SNR/SFDR vs. fIN AD9235 0 95 SNR = 64.6dBFS SFDR = 81.6dBFS 2V SFDR 90 -20 1V SFDR SNR/SFDR (dBFS) MAGNITUDE (dBFS) 85 -40 -60 -80 80 75 2V SNR 70 1V SNR -100 45.5 52.0 FREQUENCY (MHz) 58.5 65.0 60 -24 Figure 21. Dual Tone 8K FFT with fIN1 = 45 MHz and fIN2 = 46 MHz -21 -18 -15 AIN (dBFS) -12 -9 -6 02461-024 39.0 02461-021 -120 32.5 65 Figure 24. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz 95 0 2V SFDR SNR = 64.3dBFS SFDR = 81.1dBFS 90 -20 1V SFDR -40 SNR/SFDR (dBFS) MAGNITUDE (dBFS) 85 -60 -80 80 75 2V SNR 70 1V SNR -100 78.0 84.5 FREQUENCY (MHz) 91.0 97.5 60 -24 Figure 22. Dual Tone 8K FFT with fIN1 = 69 MHz and fIN2 = 70 MHz -21 -18 -15 AIN (dBFS) -12 -9 -6 02461-025 71.5 02461-022 -120 65.0 65 Figure 25. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz and fIN2 = 70 MHz 0 95 SNR = 62.5dBFS SFDR = 75.6dBFS 90 -20 2V SFDR 1V SFDR SNR/SFDR (dBFS) -40 -60 -80 80 75 2V SNR 70 1V SNR -100 136.5 143.0 149.5 FREQUENCY (MHz) 156.0 162.0 60 -24 Figure 23. Dual Tone 8K FFT with fIN1 = 144 MHz and fIN2 = 145 MHz -21 -18 -15 AIN (dBFS) -12 -9 -6 02461-026 -120 130.0 65 02461-023 MAGNITUDE (dBFS) 85 Figure 26. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz and fIN2 = 145 MHz Rev. C | Page 13 of 40 AD9235 75 20 12.2 15 AD9235-65: 11.7 2V SINAD AD9235-40: 1V SINAD 10.7 66 GAIN DRAFT (ppm/C) 11.2 AD9235-20: 1V SINAD 10 ENOB (Bits) 69 SINAD (dBc) AD9235-40: 2V SINAD AD9235-20: 2V SINAD 72 AD9235-65: 1V SINAD 5 0 -5 -10 10.2 63 0 10 20 30 40 SAMPLE RATE (MSPS) 50 02461-027 9.7 60 60 -20 -40 Figure 27. SINAD vs. fCLK with fIN = Nyquist -20 0 20 40 TEMPERATURE (C) 60 80 02461-030 -15 Figure 30. A/D Gain vs. Temperature Using an External Reference 90 1.0 SFDR: DCS ON 0.8 80 0.6 SINAD: DCS ON 70 0.4 0.2 INL (LSB) SINAD/SFDR (dBc) SFDR: DCS OFF SINAD: DCS OFF 60 50 0 -0.2 -0.4 -0.6 40 -0.8 50 55 DUTY CYCLE (%) 60 65 -1.0 0 500 1000 Figure 28. SINAD/SFDR vs. Clock Duty Cycle 2000 2500 CODE 3000 3500 4000 3500 4000 Figure 31. Typical INL 90 85 1500 02461-031 45 02461-032 40 02461-028 30 35 1.0 SFDR 2V DIFF 0.8 0.6 0.4 SFDR 1V DIFF 70 DNL (LSB) 75 SINAD 2V DIFF 65 60 0.2 0 -0.2 -0.4 SINAD 1V DIFF -0.6 55 50 -40 -30 -20 -10 -0.8 0 10 20 30 40 50 SAMPLE RATE (MSPS) 60 70 80 02461-029 SINAD/SFDR (dBc) 80 Figure 29. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz -1.0 0 500 1000 1500 2000 2500 CODE Figure 32. Typical DNL Rev. C | Page 14 of 40 3000 AD9235 APPLYING THE AD9235 THEORY OF OPERATION The AD9235 architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. H T T 5pF VIN+ CPAR T 5pF VIN- The analog input to the AD9235 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 34. An input common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance. H Figure 33. Switched-Capacitor SHA Input An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: REFT = 1/2(AVDD + VREF) REFB = 1/2(AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. 90 -90 THD 2.5MHz 2V DIFF 85 -85 80 -80 THD 35MHz 2V DIFF 75 SNR (dBc) Referring to Figure 33, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC's input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. Rev. C | Page 15 of 40 -75 SNR 2.5MHz 2V DIFF -70 70 SNR 35MHz 2V DIFF 65 -65 60 -60 55 -55 50 0 0.5 1.0 1.5 2.0 COMMON-MODE LEVEL (V) 2.5 -50 3.0 Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level THD (dBc) ANALOG INPUT T 02461-034 The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. CPAR 02461-033 Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. AD9235 differential transformer coupling is the recommended input configuration, as shown in Figure 36. 22 15pF 2Vp-p The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: 1k 15pF 0.1F Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN-. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN-. The AD9235 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9235-40 and AD9235-20). 1k The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is degradation in SFDR and in distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 37 details a typical singleended input configuration. 0.33F 2Vp-p As previously detailed, optimum performance is achieved while driving the AD9235 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 49.9 499 22 AVDD VIN+ 499 15pF AD8138 AD9235 523 499 15pF VIN- AGND 02461-035 22 Figure 35. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9235. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, 1k 22 AVDD VIN+ Differential Input Configurations 1k VIN- AGND 49.9 10F 0.1F 1k 15pF 1k 22 1k 15pF AD9235 VIN- AGND 02461-037 The minimum common-mode input level allows the AD9235 to accommodate ground-referenced inputs. 0.1F AD9235 Figure 36. Differential Transformer-Coupled Configuration VCMMAX = (AVDD + VREF)/2 1k 49.9 22 VCMMIN = VREF/2 1Vp-p AVDD VIN+ 02461-036 The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9235 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. Figure 37. Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result, may be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9235 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9235. As shown in Figure 30, noise and distortion performance are nearly flat over a 30% range of duty cycle. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. Rev. C | Page 16 of 40 AD9235 325 High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated by The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9235. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. POWER DISSIPATION AND STANDBY MODE As shown in Figure 38, the power dissipated by the AD9235 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as IDRVDD = VDRVDD x CLOAD x fCLK x N where N is the number of output bits, 12 in the case of the AD9235. This maximum current occurs when every output bit switches on every clock cycle, i.e., a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the encode rate and the characteristics of the analog input signal. 250 225 200 175 AD9235-40 150 125 100 75 AD9235-20 50 0 10 20 30 40 SAMPLE RATE (MSPS) 50 60 02461-038 In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. AD9235-65 275 TOTAL POWER (mW) SNR Degradation = -20 x log10[2 x fINPUT x tJ] 300 Figure 38. Total Power vs. Sample Rate with fIN = 10 MHz For the AD9235-20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 38 was taken with a 5 pF load on each output driver. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. By asserting the PDWN pin high, the AD9235 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9235 into its normal operational mode. Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 10 F decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation. Rev. C | Page 17 of 40 AD9235 Table 7. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Internal Switch Position N/A SENSE SENSE Internal Divider DIGITAL OUTPUTS The AD9235 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. Resulting VREF (V) N/A 0.5 0.5 x (1 + R2/R1) 1.0 Resulting Differential Span (V p-p) 2 x External Reference 1.0 2 x VREF (See Figure 40) 2.0 SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as VREF = 0.5 x (1 + R2/R1) VIN+ VIN- REFT 0.1F ADC CORE + 10F 0.1F REFB As detailed in Table 8, the data format can be selected for either offset binary or twos complement. 10F The lowest typical conversion rate of the AD9235 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. 0.1F 0.5V SELECT LOGIC The AD9235 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9235; these transients can detract from the converter's dynamic performance. + SENSE 02461-039 Timing 0.1F VREF AD9235 Figure 39. Internal Reference Configuration In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VOLTAGE REFERENCE VIN+ A stable and accurate 0.5 V voltage reference is built into the AD9235. The input range can be adjusted by varying the reference voltage applied to the AD9235, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. VIN- REFT 0.1F ADC CORE 0.1F + 10F REFB 0.1F VREF 10F Internal Reference Connection + 0.1F R2 A comparator within the AD9235 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 39), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 40, the switch is again set to the Rev. C | Page 18 of 40 0.5V SELECT LOGIC SENSE R1 AD9235 Figure 40. Programmable Reference Configuration 02461-040 If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). AD9235 External Reference Operation OPERATIONAL MODE SELECTION The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 41 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. As discussed earlier, the AD9235 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 8. 1.2 1.0 VREF ERROR (%) VREF = 1.0V 0.8 MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled The MODE pin is internally pulled down to AGND by a 20 k resistor. VREF = 0.5V 0.6 TSSOP EVALUATION BOARD 0.4 0 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (C) 60 70 02461-041 0.2 80 Figure 41. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9235 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 42 depicts how the internal reference voltage is affected by loading. 0.05 0 -0.05 0.5V ERROR (%) -0.10 1V ERROR (%) -0.20 -0.25 0.5 1.0 1.5 LOAD (mA) The AUXCLK input should be selected in applications requiring the lowest jitter and SNR performance, i.e., IF undersampling characterization. It allows the user to apply a clock input signal that is 4x the target sample rate of the AD9235. A low-jitter, differential divide-by-4 counter, the MC100LVEL33D, provides a 1x clock output that is subsequently returned back to the CLK input via JP9. For example, a 260 MHz signal (sinusoid) is divided down to a 65 MHz signal for clocking the ADC. Note that R1 must be removed with the AUXCLK interface. Lower jitter is often achieved with this interface since many RF signal generators display improved phase noise at higher output frequencies and the slew rate of the sinusoidal output signal is 4x that of a 1x signal of equal amplitude. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. -0.15 0 The AD9235 evaluation board provides the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially, through an AD8138 driver or a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 43 shows the typical bench characterization setup used to evaluate the ac performance of the AD9235. It is critical that signal sources with very low phase noise (<1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. 2.0 2.5 3.0 02461-042 ERROR (%) Table 8. Mode Selection Figure 42. VREF Accuracy vs. Load Rev. C | Page 19 of 40 AD9235 LFCSP EVALUATION BOARD An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9235 allows the user to optimize the frequency response of the op amp for the application. 3V - REFIN HP8644, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER 3V + - 3V + - 3V + - AVDD GND DUT GND DUT S4 AVDD DRVDD XFMR INPUT AD9235 10MHz REFOUT HP8644, 2V p-p CLOCK SYNTHESIZER CLOCK DIVIDER TSSOP EVALUATION BOARD S1 CLOCK Figure 43. TSSOP Evaluation Board Connections Rev. C | Page 20 of 40 + DVDD J1 DATA CAPTURE AND PROCESSING 02461-043 The typical bench setup used to evaluate the ac performance of the AD9235 is similar to the TSSOP Evaluation Board connections (refer to the schematics for connection details). The AD9235 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). AD9235 RP3 22 D0O 1 8 RP5 22 D0 D8O RP3 22 D1O 2 7 D1 D9O 3 6 D2 D10O 4 5 D3 D11O 1 8 2 7 3 6 4 5 DUTAVDDIN TB1 2 AGND TB1 3 6 D10 4 5 D11 8 7 RP6 22 3 D6 6 WHT TP5 RP6 22 OTRO D7 2 C58 + 22F 25V AVDDIN TB1 1 3 2 D5 RP4 22 D7O D9 RP6 22 RP4 22 D6O 7 1 D4 RP4 22 D5O 2 RP6 22 RP4 22 D4O D8 RP5 22 RP3 22 D3O 8 RP5 22 RP3 22 D2O 1 RP5 22 FBEAD L1 4 5 OTR 2 C47 + 22F 25V C57 0.1F R4 10k C21 + 10F 10V C22 + 10F 10V C36 0.1F C39 0.001F JP24 JP12 DUTAVDD 1 JP22 DUTAVDD JP25 TP2 RED C59 0.1F FBEAD L2 R3 10k JP23 AD9235 C35 0.1F WHT TP17 C34 0.1F TP1 RED AVDD 1 C20 10F + 10V C52 0.1F C33 0.1F SHEET 3 C50 0.1F C32 0.1F JP13 AGND TB1 4 2 C48 + 22F 25V DVDDIN TB1 6 FBEAD L4 TP4 RED D1O 4 VREF D9 26 D2O 14 PDWN D8 25 D3O 5 REFB D7 22 D4O 6 REFT D6 21 D5O 2 MODE D5 20 D6O D4 19 D7O D3 18 D8O 11 AGND D2 17 D9O 12 AVDD D1 16 D10O 23 DGND D0 15 D11O VIN- 10 VIN- JP7 U1 24 DRVDD R17 1k JP1 R42 1k JP2 TP9 BLK TP10 BLK TP15 BLK TP12 BLK TP13 BLK TP14 BLK C38 0.1F DUTCLK WHT TP6 DUTDRVDD DUTAVDD C23 + 10F 10V CLK 13 C41 0.001F C1 + 10F 10V C37 0.1F C40 0.001F TP16 BLK DVDD 1 C14 0.1F D10 27 JP6 JP11 DUTDRVDD C53 0.1F 2 C6 + 22F 25V 1 D0O 3 SENSE TP11 BLK 02461-044 DRVDDIN TB1 5 FBEAD L3 TP3 RED R20 1k D11 28 9 VIN+ AVDD R27 5k OTR 1 8 AGND VIN+ AVDD OTRO 7 AVDD Figure 44. TSSOP Evaluation Board Schematic, DUT Rev. C | Page 21 of 40 AD9235 DVDD C12 0.1F AVDD 1 2 R11 49.9 6 T1-1T 1 5 2 4 3 1N5712 D2 1N5712 D1 T2 19 2 D0 3 D1 AVDD 8 7 6 5 MC100LVEL33D 1 U3 NC VCC OUT REF VEE 2 D3 INA 3 INB 4 INCOM D4 AVDD AVDD + C24 0.1F R13 113 C27 0.1F C28 10F 10V A1 Y1 A2 Y2 A5 Y5 A6 Y6 A7 Y7 A8 Y8 CW C13 0.1F 2 R1 49.9 3 D9 4 D10 AVDD; 14 AVDD; 7 D11 R7 U8 22 DUTCLK OTR 5 6 74VHC04 JP4 AVDD WHT TP7 1 U8 2 74VHC04 U8 3 8 9 10 17 5 6 7 8 9 RP2 22 16 DD0 2 RP2 22 15 DD1 3 RP2 22 14 DD2 1 13 12 7 RP2 22 10 DD6 8 RP2 22 9 DD7 1 RP2 22 16 DD8 19 RP2 22 15 DD9 3 RP2 22 14 DD10 4 RP2 22 13 DD11 25 RP2 22 12 6 RP2 22 11 7 RP2 22 10 31 33 34 DACLK 35 36 RP2 22 9 37 38 39 40 11 5 1 VCC G2 GND A1 Y1 A2 Y2 20 10 8 18 Y3 U7 15 A4 74VHC541 Y4 A5 Y5 A6 Y6 A7 Y7 A8 Y8 DOTR 15 17 21 23 27 29 14 16 18 20 22 24 26 28 30 32 17 16 A3 12 13 4 2 G1 11 RP2 22 13 DD3 5 RP2 22 12 DD4 6 RP2 22 11 DD5 C5 10F 10V + 2 R18 500 6 7 18 16 A3 U8 DECOUPLING C26 0.1F 19 R2 10 5 HDR40RAM J1 14 13 12 11 R9 22 JP3 4 74VHC04 U8 13 12 74VHC04 U8 11 10 AVDD C10 0.1F C8 10F 10V U9 DECOUPLING U8 9 02461-045 R19 500 4 10 14 9 D8 2 GND C11 0.1F JP9 1 VCC G2 6 1 CLOCK S1 G1 R15 90 R14 90 2 3 Y3 U6 15 A4 74VHC541 Y4 8 D7 1 20 1 5 7 D5 D6 AVDD R12 113 4 D2 R26 10k + 2 1 HEADER RIGHT ANGLE MALE NO EJECTORS AUXCLK S5 C4 10F 10V R25 10k 8 74VHC04 Figure 45. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering Rev. C | Page 22 of 40 AD9235 C7 0.1F R23 1k JP5 AVDD SINGLE INPUT S3 1 2 R5 49.9 C15 10F 10V AVDD 1 C9 0.33F JP42 R41 1k AVDD JP40 2 JP45 C69 0.1F R32 1k C2 VAL 1 2 4 VO+ 5 VO- AD8138 U2 8 +IN R31 49.9 6 2 VOC VIN+ R22 22 VIN- JP41 C42 VAL C43 15pF JP43 R10 40 VEE C45 VAL + 1 R36 499 C19 10F 10V 2 1 2 A AVDD XFMR INPUT B JP8 ALT VEE TP8 RED C17 VAL S4 1 6 T1-1T 1 2 5 2 R24 49.9 4 R16 1k 3 T2 R8 1k 3 C25 0.33F C16 0.1F Figure 46. TSSOP Evaluation Board Schematic, Analog Inputs DACLK AD9762 U4 DD0 1 MSB-DB11 DD1 2 DB10 CLOCK 28 DVDD 27 DD2 3 DB19 DCOM 26 DD3 4 DB8 DD4 5 DB7 AVDD 24 DD5 6 DB6 COMP2 23 DD6 7 DB5 IOUTA 22 DD7 8 DB4 IOUTB 21 DD8 9 DB3 ACOM 20 DD9 10 DB2 COMP1 19 DD10 11 DB1 FSADJ 18 DD11 12 DB0 REFIO 17 13 NC1 REFLO 16 14 NC2 SLEEP 15 DVDD C30 0.1F C31 0.01F C29 0.1F NC3 25 C46 0.01F WHT TP18 S6 R29 49.9 C56 0.1F C55 22pF R28 49.9 C49 0.1F R30 2k C51 0.1F Figure 47. TSSOP Evaluation Board Schematic, Optional DAC Rev. C | Page 23 of 40 C54 22pF 02461-046 C18 0.1F 02461-047 S2 C8 0.1F R6 40 VCC 1 R35 499 AMP INPUT 3 -IN C44 15pF C44B JP46 R33 1k R37 499 R34 523 R21 22 02461-048 AD9235 Figure 48. TSSOP Evaluation Board Layout, Primary Side Rev. C | Page 24 of 40 02461-049 AD9235 Figure 49. TSSOP Evaluation Board Layout, Secondary Side Rev. C | Page 25 of 40 02461-050 AD9235 Figure 50. TSSOP Evaluation Board Layout, Ground Plane Rev. C | Page 26 of 40 AD9235 02461-051 _ Figure 51. TSSOP Evaluation Board Power Plane Rev. C | Page 27 of 40 02461-052 AD9235 Figure 52. TSSOP Evaluation Board Layout, Primary Silkscreen Rev. C | Page 28 of 40 02461-053 AD9235 Figure 53. TSSOP Evaluation Board Layout, Secondary Silkscreen Rev. C | Page 29 of 40 AD9235 EXTREF 1V MAX E1 GND AVDD C D GND GND E AVDD C29 10F C11 0.1F P1 R7 1k GND C7 0.1F P3 R6 1k GND GND P4 3 4 5 P2 2 2 P5 C8 0.1F 3 GND GND 4 AMP CT E 45 PRI SEC GND GND OPTIONAL XFR T2 FT C1-1-13 X FRIN 1 5 2 3 4 PRI SEC GND XOUT CT XOUTB C16 0.1F C5 GND 0.1F R2 XX C19 15pF AGND 1 2 3 4 5 6 7 8 D8 D9 D11 D10 OTR D7 14 AD9235 U4 16 15 14 13 12 11 10 9 GND DRX D13X D12X D11X D10X D9X D8X D7X RP2 220 D5 12 VIN+ 30 VIN- D4 11 GND 31 AGND D3 10 AVDD 32 AVDD D2 9 OR L1 FOR FILTER DRVDD D6 13 29 VIN- H4 MTHOLE6 1 2 3 4 5 6 7 8 GND 1 2 3 4 5 (LSB) 6 7 8 16 15 14 13 12 11 10 9 D6X D5X D4X D3X D2X D1X D0X RP1 220 R11 36 CLK GND R3 0 GND XOUTB AMPINB C18 0.1F R8 1k C23 10pF P14 AVDD R15 33 AVDD R18 R SINGLE ENDED 25 R3, R17, R18 ONLY ONE SHOULD BE ON BOARD AT A TIME GND R13 1k R25 1k GND P13 GND SENSE PIN SOLDERABLE JUMPER E TO A EXTERNAL VOLTAGE DIVIDER E TO B INTERNAL 1V REFERENCE (DEFAULT) E TO C EXTERNAL REFERENCE E TO D INTERNAL 0.5V REFERENCE MODE PIN SOLDERABLE JUMPER 5 TO 1 TWOS COMPLEMENT/DCS OFF 5 TO 2 TWOS COMPLEMENT/DCS OFF 5 TO 3 OFFSET BINARY/DCS ON 5 TO 4 OFFSET BINARY/DCS OFF Figure 54. LFCSP Evaluation Board Schematic, Analog Inputs and DUT Rev. C | Page 30 of 40 02461-054 2 3 AVDD 28 D1 5 NC GND 27 GND VIN+ D0 6 C26 10pF AVDD DNC L1 10nH XFRIN1 1 R10 36 C21 10pF DGND 15 DNC C15 0.1F J1 R4 33k R12 0 DRVDD 16 REFT PDWN T1 ADT 1-1 WT REFB 26 DNC XOUT 25 CLK R26 1k DNC R36 1k MODE VREF AVDD AMPIN H3 MTHOLE6 (MSB) SENSE R42 0 H2 MTHOLE6 OVERRANGE BIT 4 24 23 22 21 20 19 18 17 C6 0.1F 6 VDL + 2 VAMP C9 0.10F 1 MODE 5.0V GND GND H1 GND MTHOLE6 1 GND P6 R5 1k 2.5V P10 GND B 2.5V DRVDD P7 A C12 0.1F C22 10F C13 0.10F P11 P8 AVDD R9 10k P9 3.0V R1 10k AD9235 MSB DRX D13X GND D12X D11X DRVDD D10X D9X GND D8X D7X D6X D5X GND D4X D3X DRVDD D2X D1X GND LSB D0X CLKLAT/DAC 74LVTH162374 U1 2OE 24 25 2CLK 26 2DB 2QB 23 27 2D7 22 28 GND GND 21 29 2D6 2Q6 20 30 2D5 2Q5 19 31 VCC VCC 18 32 2D4 33 2D3 34 GND HEADER 40 DRY 2 2 1 1 4 4 3 3 6 5 5 8 7 7 10 10 2Q4 17 12 12 9 9 11 11 2Q3 16 GND 15 14 14 13 13 GND 16 16 15 15 35 2D2 2Q2 14 18 18 17 17 36 2D1 2Q1 13 20 20 19 19 37 1D8 1Q8 12 22 22 21 21 38 1D7 1Q7 11 24 24 23 23 39 GND GND 10 26 26 25 25 40 1D6 1Q6 9 28 28 27 27 41 1D5 30 30 29 29 42 VCC 1Q5 8 7 V 32 32 31 31 43 1D4 1Q4 6 34 34 33 33 44 1D3 1Q3 5 36 36 35 35 45 GND GND 4 38 38 37 37 46 1D2 1Q2 3 40 40 39 39 47 1D1 1Q1 2 48 1CLK 2Q7 GND GND 1OE 1 IN 6 MSB GND 8 DRVDD GND GND DRVDD CC 1 DR DRY GND GND GND GND OUT VAMP R38 1k C44 0.1F R39 1k VAMP GND C24 10F POWER DOWN USE R40 OR R41 VAMP R41 10k + GND R41 10k AD8351 R40 10k U3 PWDN RGP1 C28 0.1F AMP IN INHI AMP INLO R19 50 GND R35 25 GND C45 GND 0.1F GND C35 0.10F RPG2 R33 25 1 10 2 9 3 8 4 7 5 6 R34 1.2k VOCM R14 25 VPOS OPH1 GND R16 0 C27 0.1F AMPINB OPLO COMM GND Figure 55. LFCSP Evaluation Board Schematic, Digital Path Rev. C | Page 31 of 40 R17 0 AMPIN C17 0.1F 02461-055 CLKAT/DAC Rev. C | Page 32 of 40 Figure 56. LFCSP Evaluation Board Schematic, Clock Input 02461-056 GND J2 ENCODE ENC ENCX R29 50 GND ANALOG BYPASSING C33 C32 0.001F 0.1F CLOCK TIMING ADJUSTMENTS GND C25 10F C43 0.1F R27 0 R28 0 GND R30 1k R31 1k VDL DRVDD VDL VDL VDL VDL CLK E43 E31 E52 E50 GND GND R24 1k E44 R21 1k E35 GND R20 1k E53 GND R32 1k E51 ENC GND C14 C41 0.001F 0.1F FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 DUT BYPASSING GND + + + C10 C4 C3 22F 10F 10F VDL DRVDD AVDD AVDD C30 0.001F 13 4B 12 4A 10 3B 4Y 3Y PWR 14 11 9 3A GND 8 2Y 7 6 3 C38 0.001F 5 2B 4 2A 2 1B 1Y 74VCX86 C31 C34 C36 0.1F 0.1F 0.1F 1 1A DIGITAL BYPASSING + C2 22F VDL GND ENCX C48 0.001F GND VAMP GND C49 0.001F LATCH BYPASSING C1 C47 0.1F 0.1F + C20 10F R23 0 CLKAT/DAC R37 25 Rx DNP R22 0 DR SCHEMATIC SHOWS TWO GATE DELAY SETUP FOR ONE DELAY REMOVE R22 AND R37 AND ATTACH Rx (Rx = 0) C39 0.001F VDL + C46 10F C37 0.1F C40 0.001F AD9235 02461-057 02461-059 AD9235 Figure 59. LFCSP Evaluation Board Layout, Ground Plane 02461-058 02461-060 Figure 57. LFCSP Evaluation Board Layout, Primary Side Figure 58. LFCSP Evaluation Board Layout, Secondary Side Figure 60. LFCSP Evaluation Board Layout, Power Plane Rev. C | Page 33 of 40 02461-062 02461-061 AD9235 Figure 61. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 62. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. C | Page 34 of 40 AD9235 Table 9. LFCSP Evaluation Board Bill of Materials (BOM) Item Qty. Omit1 Reference Designator 1 18 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C18, C27, C17, C28, C35, C45, C44 2 8 C2, C3, C4, C10, C20, C22, C25, C29 2 C46, C24 3 8 C14, C30, C32, C38, C39, C40, C48, C49 4 3 C19, C21, C23 5 1 C26 6 9 E31, E35, E43, E44, E50, E51, E52, E53 2 E1, E45 7 2 J1, J2 8 1 L1 Device Chip Capacitor Package 0603 Value 0.1 F Tantalum Capacitor TAJD 10 F Chip Capacitor 0603 0.001 F Chip Capacitor Chip Capacitor Header 0603 0603 EHOLE 10 pF 10 pF SMA Connector/50 Inductor SMA 0603 9 1 P2 Terminal Block TB6 10 11 1 5 Header Dual 20-Pin RT Angle HEADER40 Chip Resistor 0603 0 12 13 2 14 14 15 2 1 16 2 P12 R3, R12, R23, R28, RX R37, R22, R42, R16, R17, R27 R4, R15 R5, R6, R7, R8, R13, R20, R21, R24, R25, R26, R30, R31, R32, R36 R10, R11 R29 R19 RP1, RP2 17 18 1 1 T1 U1 19 20 21 22 23 24 25 26 27 28 Total 1 1 1 U4 U5 PCB U3 T2 R9, R1, R2, R38, R39 R18, R14, R35 R40, R41 R34 R33 6 1 1 82 1 1 5 3 2 1 1 34 Jumper Blocks 10 nH Chip Resistor Chip Resistor 0603 0603 33 1k Chip Resistor Chip Resistor 0603 0603 36 50 Resistor Pack R_742 220 ADT1-1WT 74LVTH162374 CMOS Register AD9235BCP ADC (DUT) 74VCX86M AD92XXBCP/PCB AD8351 Op Amp MACOM Transformer Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor AWT1-1T TSSOP-48 These items are included in the PCB design but are omitted at assembly. Rev. C | Page 35 of 40 LFCSP-32 SOIC-14 PCB MSOP-8 ETC1-1-13 0603 0603 0603 Recommended Vendor/ Supplied Part Number by ADI 1-1 TX SELECT 25 10 k 1.2 k 100 Coilcraft/ 0603CS-10NXGBU Wieland/25.602.2653.0, z5-530-0625-0 Digi-Key S2131-20-ND Digi-Key CTS/742C163220JTR Mini-Circuits Analog Devices, Inc. Fairchild Analog Devices, Inc. Analog Devices, Inc. M/A-COM/ETC1-1-13 X X X AD9235 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 3.25 3.10 SQ 2.95 17 16 9 0.30 0.23 0.18 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 EXPOSED PAD (BOTTOM VIEW) 0.80 MAX 0.65 TYP 12 MAX 1.00 0.85 0.80 PIN 1 INDICATOR 25 24 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 64. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body (CP-32-2) Dimensions shown in millimeters Rev. C | Page 36 of 40 AD9235 ORDERING GUIDE Model AD9235BRU-20 AD9235BRURL7-20 AD9235BRUZ-201 AD9235BRUZRL7-201 AD9235BRU-40 AD9235BRURL7-40 AD9235BRUZ-401 AD9235BRUZRL7-401 AD9235BRU-65 AD9235BRURL7-65 AD9235BRUZ-651 AD9235BRUZRL7-651 AD9235BCP-202 AD9235BCPRL7-202 AD9235BCPZ-201, 2 AD9235BCPZRL7-201, 2 AD9235BCP-402 AD9235BCPRL7-402 AD9235BCPZ-401, 2 AD9235BCPZRL7-401, 2 AD9235BCP-652 AD9235BCPRL7-652 AD9235BCPZ-651, 2 AD9235BCPZRL7-651, 2 AD9235-20PCB AD9235-40PCB AD9235-65PCB AD9235BCP-20EB AD9235BCP-40EB AD9235BCP-65EB 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) TSSOP Evaluation Board TSSOP Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board LFCSP Evaluation Board LFCSP Evaluation Board Package Option RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 Z = Pb-free part. It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. Rev. C | Page 37 of 40 AD9235 NOTES Rev. C | Page 38 of 40 AD9235 NOTES Rev. C | Page 39 of 40 AD9235 NOTES (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02461-0-10/04(C) Rev. C | Page 40 of 40