CAT93C57 2K-Bit Serial E7PROM I||CATALYST SEMICONODUCTSEBOAR FEATURES @ High Speed Operation: 1MHz @ Low Power CMOS Technology @ Wide Operating Voltage Range Voc = 4.5V to 5.5V Voc = 2-7V to 6.0V Veg = 2.5V to 6.0V Vig = 1.8V to 6.0V m Selectable x8 or x16 Memory Organization B Self-Timed Write Cycle with Auto-Clear @ Sequential Read Operation m@ Power-Up Inadvertant Write Protection m@ 100,000 Program/Erase Cycles @ 100 Year Data Retention a Commercial and Industrial Temperature Ranges DESCRIPTION The CAT93C57 is 2K-bit Serial E-PROM memory de- vices which can be configured as either 128 registers by 16 bits (ORG pin at Vcc) or 256 registers by 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C57 is manufactured using Catalysts advanced CMOS E2PROM floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP or SOIC packages. PIN CONFIGURATION DIP Package (P) SOIC Package (J) NC [Jet 8 ORG Voc C4 2 /) GND 7 csc 3 6 Do Sk co] 4 514 ol PIN FUNCTIONS Pin Name Function cs Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output Voc 1.8V to 6.0V Power Supply GND Ground NC No Connection ORG Memory Organization Note: When the ORG pin is connected to Vcc, the 128 x 16 organiza- tion is selected. When it is connected to ground, the 256 x 8 organiza- tion is selected. If the ORG pin is left unconnected, then an internal pullup device will select the 128 x 16 organization. SOIC Package (S) SOIC Package (K) cS (Je 8[5 Vcc cs Cet 8T3 Vceco SK (] 2 7fonc SK C2 7{(0 NC DIC] 3 6 [7] ORG DIC] 3 6 ORG DOC] 4 5 [2] GND DOC] 4 5 [9 GND 5041 FHD Fot BLOCK DIAGRAM Vec GND MEMORY ARRAY oRG 256 x 8 | | ADDRESS OR DECODER 128 x16 DATA REGISTER DI t OUTPUT BUFFER MODE DECODE cs LOGIC > sk CLOCK po *| GENERATOR 5048 uD Foe 1996 by Catalyst Semiconductar, Inc 3-17 Characteristics Subject to change without noticeCAT93C57 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias -55C to +125C Storage Temperature ................00 -65C to +150C Voltage on any Pin with Respect to Ground ............ 2.0V to +Vcc +2.0V Vcc with Respect to Ground |... -2.0V to +7.0V Package Power Dissipation *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Capability (Ta = 25C) 0... ceeseeene renee 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current?) ooo. 100 mA RELIABILITY CHARACTERISTICS | Symbol Parameter Min Max Units Reference Test Method Neno) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 Tor) Data Retention 100 Years MIL-STD-883, Test Method 1008 Vzap) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ITH) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS Voc = +1.8V to 6V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions Ieci Power Supply Current 3 mA DI = 0.0V, fsx = MHz (Operating) Vcc = 5.0V, CS = 5.0V Output Open Isp Power Supply Current 50 pA CS =0V (Standby) ILo Input Leakage Current 2 HA Vin = OV to Vcc ILo Output Leakage Current 10 HA Vout = OV to Vcc, (Including ORG Pin) CS =0V Vin Input Low Voltage -0.1 0.8 Vv 4.5V<Vec<5.5V Vin Input High Voltage 2 Vec+1 Vv Vit2 Input Low Voltage 0 VecX0.2 Vv 1.8V<Vcc<2.7V Vin2 Input High Voltage VccX0.7 Vec+1 Vv Vou Output Low Voltage 0.4 Vv 4.5V<Vcc<5.5V Voni Output High Voltage 2.4 Vv lo, = 2.1mMA lon = -400nA VoL2 Output Low Voltage 0.2 Vv 1.8VsVcc<2.7V Von2 Output High Voltage Voc-0.2 Vv lo. = 1mA Jon = -100uA (1) The minimum DC input is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Vcc +0.5V, which may overshoot to Vcc +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second, No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to Voc +1V. 3-18CAT93C57 INSTRUCTION SET Address Data Instruction | Start Bit] Opcode| 256x8 128x116 | 256 x 8 /128 x 16 Comments READ 1 10 A7-A0 A6-A0 Read Address AN-AO ERASE 1 11 A7-AO A6-AO0 Clear Address AN-AO WRITE 1 01 A7-A0 A6-A0 D7-Do |D15D0 Write Address AN-AO EWEN 1 00 TUMXKXXK | 11 XXXXX Write Enable EWDS 1 00 OOXXXXXX | OOXXXXX Write Disable ERAL 1 00 1OXXXXXX | 1OXXXXX Clear All Addresses WRAL 1 00 O1XXXXXX | O1XXXXX | D7-DO |D15-D0 Write All Addresses PIN CAPACITANCE Symbol Test Max. Units Conditions Cour) | OUTPUT CAPACITANCE (DO) 5 pF VouT=OV Cin?) INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF Vin=OV A.C. CHARACTERISTICS Limits Voc = Voc = 2.7V -6V Voc = 1.8V-6V* Vec = 2.5V-6V| 4.5V-5.5V Test SYMBOL| PARAMETER Min. | Max. | Min. | Max. | Min. | Max. |UNITS | Conditions tcss CS Setup Time 200 100 50 ns tosH CS Hold Time 0 0 0 ns tois DI Setup Time 400 200 100 ns toi DI Hold Time 400 200 100 ns tep1 Output Delay to 1 1 0.5 0.25 ys tppo Output Delay to 0 1 0.5 0.25 pS C. = 100pF tHz!3) Output Delay to High-Z 400 200 100 ns tew Program/Erase Pulse Width 10 10 10 ms tCSMIN Minimum CS Low Time 1 0.5 0.25 ps tskHI Minimum SK High Time 1 0.5 0.25 ys tskLow Minimum SK Low Time 1 0.5 0.25 ps tsv Output Delay to Status Valid 1 0.5 0.25 ps SKmax Maximum Clock Frequency DC 250 DC 500 DC } 1000 |} KHZ Note: Preliminary data (1) This parameter is tested initially and after a design or process change that affects the parameter. 3-19CAT93C57 DEVICE OPERATION The CAT93C57 is a 2048-bit nonvolatile memory in- tended for use with industry standard microprocessors. The CAT93C57 can be organized as either 128 registers by 16 bits, or as 256 registers by 8 bits. Seven 10-bit instructions (11-bit instruction in 256 by 8 organization) control the reading, writing and erase operations of the device. The CAT93C57 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy 1 into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the Di pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the CAT93CS57 is a logical 1 start bit, a 2-bit (or 4-bit) op code, a 7-bit address (8-bit address when organized as 256 x 8), and for write operations a 16-bit data field (8-bit data field when organized as 256 x 8). Figure 1. Sychronous Data Timing (1) SK YOY + tgxHi 'skLow * 'CSH 'DIH VALID ois 'cSMIN DBO Note: DATA VALID ea 5046 FHD FOa (1) The ORG pin is used to configure the device for x8 or x16 operation. When x8 organization is selected, AN = A7 and DN = 07. When x16 organization is selected, AN = A6 and ON = D15. 3-20CAT93C57 Figure 2. Read Instruction Timing (1) TU UU UU UU UU LEU Ud ex 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cs / Le Don't Care AN AN-1 o PTT OOO KIDED XXXII HIGH-Z DO Dummy o/ ~~ Dis. a nddress 6 Ds. ; Address +n By OAs. 0 1 Dis ve D7... 5046 FHD FO4 Note: (1) The ORG pin is used to configure the device for x8 or x16 operation. When x8 organization is selected, AN = A7 and DN = D7. When x16 organization is selected, AN = A6 and DN = D15. 3-21CAT93C57 Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C57 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed. The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tepo or tep1). After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next ad- dress and shift out the next data word in a sequential 2 READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (chip select) pin must be deselected for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking clear and cata store cycle of the memory location specified in the instruction. The clock- ing of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C57 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Claar before write, it is NOT necessary to erase a memory tocation before the WRITE command is sent. Figure 3. Write Instruction Timing () sk PLE LL LLL LLL OX cs f/f AN AN-4 Ag On Do OOF HIGH-Z BO cs K A status \ STANDBY VERIFY tsy Busy haz J READY HIGH-Z be te yy >} 5046 FHD FOS Figure 4. Erase Instruction Timing (1) PLL DOXA cs S/S STATUS VERIFY STANDBY >| t AN AN-4 Ao cs Di 1 1 1 4% , wale ee HIGH-Z BO 4% Busy /| READY wane Note: oe te yy ] 5046 FHD F07 (1) The ORG pin is used to configure the device for x8 or x16 operation. When x8 organization is selected, AN = A7 and DN = D7. When x16 organization is selected, AN = A6 and DN = D15. 3-22CAT93C57 Erase Upon receiving an ERASE command and address, the CS (chip select) pin must be deselected for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking clear cycle of the memory location specified in the instruction. The clocking of the SK pin is not neces- sary after the device has entered the self clocking mode. The ready/busy status of the CAT93C57 can be deter- mined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical 1 state. Erase/Write Enable and Disable The CAT93C57 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is en- abied, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C57 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. Erase All Upon receiving an ERAL command, the CS (chip select) pin must be deselected for a minimum of 250ns (tcsmin). The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C57 can be determined by selecting the device and polling the DO pin. Once cleared, the con- tents of all memory bits return to a logical 1 state. Figure 5. EWEN/EWDS Instruction Timing (1) s AXA AXA AX cs JS " TALS 8 A= AKA AIK) * ENABLE = 11 \ STANDBY 128 x 16 = 6 DON'T CARE BITS DISABLE =00 256 x 8 = 7 DON'T CARE BITS 5046 FHD FOS Figure 6. ERAL Instruction Timing (1) FLL LILPu XXX KREMER EKKK i at cs JS \ / STATUS VERIFY \ STANDBY | tos 128 x 16 =5 DON'T CARE BITS toy I > tyaz 256 x 8 = 6 DON'T CARE BITS HIGH-Z BO BUSY READY HIGH-Z te yyy __ > 5046 FHD FOd Note: (1) The ORG pin is used to configure the device for xB or x16 operation. When x8 organization is selected, AN = A7 and DN = D7. When x16 organization is selected, AN = A6 and ON = D15. 3-23CAT93C57 Write All Upon receiving a WRAL command and data, the CS device has entered the self clocking mode. The ready/ (chip select) pin must be deselected for a minimum of busy status of the CAT93C57 can be determined by 250ns (tcsmin). The falling edge of CS will start the self selecting the device and polling the DO pin. it IS NOT clocking data write to all memory locations in the device. necessary for all memory locations to be cleared before The clocking of the SK pin is not necessary after the the WRAL command is executed. Figure 7. WRAL Instruction Timing () PLE LLL LLL cs / STATUS VERIFY \ STANDBY ~ tes oJ \ 222 J QXRKKEKEKEXONK KOH , 128 x 16 = 5 DON'T CARE BITS tgy _o| >| tuz 256 x 8 = 6 DON'T CARE BITS BUSY / READY HIGH-Z |} tey _ >} 5046 FHD Foo Note: (1) The ORG pin is used to configure the device for x8 or x16 operation. When x8 organization is selected, AN = A7 and DN = D7, When x16 organization is selected, AN = A6 and DN = 015. PIN CONFIGURATION | Prefix Device # ' Suffix CAT 93057 Ss -2.5 TE7 Product Temperature Range Tape & Reet Number Blank = Commercial (0C to +70C) TE7: 500/Reel | = Industrial (-40C to +85C) TE13: 2000/Reel Package Operating Voltage P=PDIP Biank: 4.5 to 5.5V S$ = SOIC (JEDEC) 2.7: 2.7 to 6.0V J = SOIC (JEDEC) 2.5: 2.5 to 6.0V K = SOIC (EIAJ) 1.8: 1.8 to 6.0V Notes: (1) The device used in the above example is a 93C57S1-2.5TE7 (SOIC, Industrial Temperature, 2.5 Volt to 6 Volt Operating Voltage, Tape & Reel) 3-24