ZXGD3107N8
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ZXGD3107N8
SYNCHRONOUS MOSFET CONTROLLER IN SO-8
Description
ZXGD3107N8 synchronous controller is designed for driving a
MOSFET as an ideal rectifier. This is to replace a diode for increasing
the power transfer efficiency.
Proportional Gate drive control monitors the reverse voltage of the
MOSFET such that if body diode conduction occurs, a positive voltage
is applied to the MOSFET’s GATE pin. Once the positive voltage is
applied to the Gate, the MOSFET switches on allowing reverse
current flow. The controllersoutput voltage is then proportional to the
MOSFET drain-source voltage and this is applied to the Gate via the
driver. This action minimizes body diode conduction while enabling a
rapid MOSFET turn-off as drain current decays to zero.
Applications
Flyback Converters in:
AC-DC Adaptors
Set-Top Boxes
PoE Power Devices
Resonant Converters in:
Telecoms PSU
Laptop Adaptors
Computing Power Supplies ATX and Server PSU
Ordering Information (Note 4)
Product
Marking
Reel Size (inches)
Tape Width (mm)
Quantity Per Reel
ZXGD3107N8TC
ZXGD3107
13
12
2,500
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green" products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at http://www.diodes.com/products/packages.html.
Marking Information
Pin Name
Pin Function
VCC
Power Supply
DNC
Do Not Connect
BIAS
Bias Current
DRAIN
Drain Sense
REF
Reference Current
GND
Power Ground
GATE
Gate Drive
ZXGD = Product Type Marking Code, Line 1
3107 = Product Type Marking Code, Line 2
YY = Year (ex: 17 = 2017)
WW = Week (01 to 53)
Top View
Pin-Out
SO-8
ZXGD
3107
YY WW
Synchronous Rectifier
MOSFET
Transformer
RBIAS
RREF
ZXGD3107
DRAIN GATE GND
REF BIAS Vcc
C1
VG
VD
Typical Configuration
Vout
GND
Top View
GATE
GND
VCC
BIAS
DRAIN
REF
DNC
DNC
ZXGD3107N8
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ZXGD3107N8
Functional Block Diagram
Gate drive
amplitude control
Turn-on/off
control GATE
Vcc
GND
DRAIN
Threshold
voltage
control
REF BIAS
Driver
+Diff
amp
-
+
Hi volt
comparator
-
ZXGD3107
Pin Number
Pin Name
Pin Function and Description
1
VCC
Power supply
This supply pin should be closely decoupled to ground with a ceramic capacitor.
2, 6
DNC
Do not connect
Leave pin floating.
3
BIAS
Bias
Connect this pin to VCC via RBIAS resistor. Select RBIAS to source 0.56mA into this pin.
Refer to Table 1 and 2, in Application Information section.
4
DRAIN
Drain sense
Connect directly to the synchronous MOSFET drain terminal.
5
REF
Reference
Connect this pin to VCC via RREF resistor. Select RREF to source 1.23mA into this pin.
Refer to Table 1 and 2, in Application Information section.
7
GND
Ground
Connect this pin to the synchronous MOSFET source terminal and ground reference point.
8
GATE
Gate drive
This pin sinks and sources the ISINK and ISOURCE current to the synchronous MOSFET Gate.
ZXGD3107N8
ZXGD3107N8
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ZXGD3107N8
Absolute Maximum Ratings (@TA = +25°C, unless otherwise specified.)
Characteristic
Symbol
Value
Unit
Supply Voltage, Relative to GND
VCC
40
V
Drain Pin Voltage
VD
-3 to 200
V
Gate Output Voltage
VG
-3 to VCC + 3
V
Gate Driver Peak Source Current
ISOURCE
4
A
Gate Driver Peak Sink Current
ISINK
9
A
Reference Voltage
VREF
VCC
V
Reference Current
IREF
25
mA
Bias Voltage
VBIAS
VCC
V
Bias Current
IBIAS
100
mA
Thermal Characteristics (@TA = +25°C, unless otherwise specified.)
Characteristic
Symbol
Value
Unit
Power Dissipation
Linear Derating Factor
(Note 5)
PD
490
3.92
mW
mW/°C
(Note 6)
655
5.24
(Note 7)
720
5.76
(Note 8)
785
6.28
Thermal Resistance, Junction to Ambient
(Note 5)
RθJA
255
°C/W
(Note 6)
191
(Note 7)
173
(Note 8)
159
Thermal Resistance, Junction to Lead
(Note 9)
RθJL
55
C/W
Thermal Resistance, Junction to Case
(Note 10)
RθJC
45
°C/W
Operating Temperature Range
TJ
-40 to +150
°C
Storage Temperature Range
TSTG
-50 to +150
ESD Ratings (Note 11)
Characteristic
Symbol
Value
Unit
JEDEC Class
Electrostatic Discharge - Human Body Model
ESD HBM
1,500
V
1C
Electrostatic Discharge - Machine Model
ESD MM
200
V
B
Notes: 5. For a device surface mounted on minimum recommended pad layout FR-4 PCB with high coverage of single sided 1oz copper, in still air conditions; the
device is measured when operating in a steady-state condition.
6. Same as note (5), except pin 1 (VCC) and pin 7 (GND) are both connected to separate 5mm x 5mm 1oz copper heatsinks.
7. Same as note (6), except both heatsinks are 10mm x 10mm.
8. Same as note (6), except both heatsinks are 15mm x 15mm.
9. Thermal resistance from junction to solder-point at the end of each lead on pin 1 (VCC) or pin 7 (GND).
10. Thermal resistance from junction to top of the case.
11. Refer to JEDEC specification JESD22-A114 and JESD22-A115.
ZXGD3107N8
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ZXGD3107N8
Thermal Derating Curve
020 40 60 80 100 120 140 160
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 15mm x 15mm
5mm x 5mm
Minimum
Layout
Derating Curve
Junction Temperature (°C)
Max Power Dissipation (W)
10mm x 10mm
(°C )
ZXGD3107N8
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ZXGD3107N8
Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
VCC = 10V; RBIAS = 18kΩ (IBIAS = 0.56mA); RREF = 7.5kΩ (IREF = 1.23mA)
Characteristic
Symbol
Min
Typ
Max
Unit
Test Condition
Input Supply
Supply to GND Voltage
VCC(ON)
40
V
VD = -100mV @ ICC = 10µA
Supply to GND Voltage
VCC(OFF)
40
V
VD = 1V @ ICC = 10µA
Drain to GND Voltage
VD
200
V
ID = A
Quiescent Current
IQ
1.79
mA
VD ≥ 0mV
Gate Driver
Gate Peak Source Current
ISOURCE
2
A
Capacitive load: CL = 20nF
Gate Peak Sink Current
ISINK
7
Detector under DC Condition
Turn-off Threshold Voltage
VT
-20
-10
0
mV
VG = 1V
Capacitive load only
Gate Output Voltage
VG(OFF)
0.2
0.6
V
VD ≥ 1V
VG
5.0
7.8
VD = -50mV
8.0
9.4
VD = -100mV
Switching Performance
Turn-on Propagation Delay
tD(RISE)
70
ns
Rise and fall measured 10% to 90%
Refer to application test circuit below
Gate Rise Time
tR
175
Turn-off Propagation Delay
tD(FALL)
15
Gate Fall Time
tF
20
MOSFET Qg(tot) = 82nC
RDS(on) = 15mΩ
Flyback transformer
Magnetising inductance = 820μH
RBIAS
18KΩ
RREF
7.5KΩ
Vcc = 10V
Output load
Test conditions
Switching frequency = 100kHz
Continuous conduction mode
ZXGD3107
DRAIN GATE GND
REF BIAS Vcc
C1
1uF
VG
VD
Test Circuit for Switching Performance
7.5
ZXGD3107N8
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ZXGD3107N8
Typical Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
-100 -80 -60 -40 -20 0
0
2
4
6
8
10
12
14
-100 -80 -60 -40 -20 0
0
2
4
6
8
10
-50 0 50 100 150
-30
-25
-20
-15
-10
-5
0
-50 -25 0 25 50 75 100 125 150
30
35
130
140
150
160
170
180
190
200
210
220
230
0 2 4 6 8 10 12 14 16 18 20 22
0
20
40
60
80
100
120
140
160
180
-100 -80 -60 -40 -20 0
0
2
4
6
8
10
12
14
VCC = 5V
Capacitive load and
50k pull down
VCC = 15V
VCC = 12V
VCC = 10V
Transfer Characteristic
VG Gate Voltage (V)
VD Drain Voltage (mV)
TA = -40oC
TA = 25oC
TA = 125oC
Transfer Characteristic
VG Gate Voltage (V)
VD Drain Voltage (mV)
VCC = 10V
RBIAS=18k
RREF=9.1k
50k pull down
VCC = 10V
RBIAS=18k
RREF=7.5k
VG = 1V
50k pull down
Turn-off Threshold Voltage vs Temperature
Turn-off Threshold Voltage (mV)
Temperature (oC)
tOFF = tD(FALL) + tF
tON = tD(RISE) + tR
Switching vs Temperature
Switching Time (ns)
Temperature (oC)
VCC = 10V
RBIAS=18k
RREF=7.5k
CL=10nF
VCC = 5V
VCC = 10V
VCC = 12V
VCC = 15V
Supply Current vs Capacitive Load
Capacitance (nF)
Supply Current (mA)
RBIAS=18k
RREF=7.5k
f=500kHz
Capacitive load only
VCC = 5V
VCC = 15V
VCC = 12V
VCC = 10V
Transfer Characteristic
VG Gate Voltage (V)
VD Drain Voltage (mV)
ZXGD3107N8
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ZXGD3107N8
Typical Electrical Characteristics (Cont.) (@TA = +25°C, unless otherwise specified.)
-100 0 100 200 300
-2
0
2
4
6
8
10
-200 -100 0 100 200 300
-2
0
2
4
6
8
10
110 100
10
100
0200 400 600
-8
-6
-4
-2
0
2
4
110 100
0
2
4
6
8
10
10 100 1000 10000 100000
1
10
100
VCC=10V
RBIAS=18k
RREF=7.5k
CL=10nF
RL=0.1
VD
Switch On Speed
Voltage (V)
Time (ns)
VGVCC=10V
RBIAS=18k
RREF=7.5k
CL=10nF
RL=0.1
VG
VD
Switch Off Speed
Voltage (V)
Time (ns)
VCC=10V
RBIAS=18k
RREF=7.5k
RL=0.1
tON = tD(RISE) + tR
tOFF= tD(FALL) + tF
Switching vs Capacitive Load
Time (ns)
Capacitance (nF)
VCC=10V
RBIAS=18k
RREF=7.5k
CL=10nF
RL=0.1
ISOURCE
ISINK
Gate Drive Current
Gate Drive Current (A)
Time (ns)
VCC=10V
RBIAS=18k
RREF=7.5k
RL=0.1
-ISINK
Gate Current vs Capacitive Load
Peak Drive Current (A)
Capacitance (nF)
ISOURCE
CL=100nF
CL=33nF
CL=10nF
CL=3.3nF
CL=1nF
VCC=10V
RBIAS=18k
RREF=7.5k
RL=0.1
Supply Current vs Frequency
Frequency (Hz)
Supply Current (mA)
ZXGD3107N8
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ZXGD3107N8
Application Information
The purpose of the ZXGD3107N8 is to drive a MOSFET as a low-VF Schottky diode replacement in isolated AC-DC converter. When combined
with a low RDS(ON) MOSFET, the controller can yield significant power-efficiency improvement, while maintaining design simplicity and incurring
minimal component count. Figure 1 shows the typical configuration of ZXGD3107N8 for synchronous rectification in a low output voltage flyback
converter.
Synchronous MOSFET
Transformer
+ In
- In
PWM controller
CCM/CrCM/DCM
+Vout
- Vout
D
G
S
DRAIN
GATE GND
REF BIAS Vcc
Rref Rbias
ZXGD3107 C1
RsnubCsnub
Rd
Dsnub
Figure 1. Typical Flyback Application Schematic
Threshold Voltage and Resistor Setting
Proper selection of external resistors RREF and RBIAS is important for optimum device operation. RREF and RBIAS supply fixed current into the REF
and BIAS pins of the controller. IREF and IBIAS combines to set the turn-off threshold voltage level, VT. In order to set VT to -10mV, the
recommended IREF and IBIAS are 1.23mA and 0.56mA respectively.
The values for RREF and RBIAS are selected based on the VCC voltage. If the VCC pin is connected to the power converter’s output, the resistors
should be selected based on the nominal converter’s output voltage. Table 1 provides the recommended resistor values for different VCC voltages
to achieve a VT of -10mV.
Supply, VCC
Bias Resistor, RBIAS
Reference Resistor, RREF
5V
9.6kΩ
4kΩ
10V
18kΩ
7.5kΩ
12V
24kΩ
9.6kΩ
15V
30kΩ
12kΩ
Table 1. Recommended Resistor Values for Different VCC Voltages
ZXGD3107N8
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ZXGD3107N8
Application Information (Cont.)
Functional Descriptions
The operation of the device is described step-by-step with reference to the timing diagram in Figure 2.
1. The detector stage monitors the MOSFET drain-source voltage.
2. When, due to transformer action, the MOSFET body diode is forced to conduct there is a negative voltage on the drain pin due to the body
diode forward voltage.
3. When the negative drain voltage crosses the turn-off Threshold voltage VT, the detector stage outputs a positive voltage with respect to ground
after the turn-on delay time tD(FALL). This voltage is then fed to the MOSFET driver stage and current is sourced out of the GATE pin.
4. The controller goes into Proportional Gate drive control the Gate output voltage is proportional to the MOSFET on-resistance-induced drain-
source voltage. Proportional Gate drive ensures that MOSFET conducts during majority of the conduction cycle to minimize power loss in the body
diode.
5. As the drain current decays linearly toward zero, Proportional Gate drive control reduces the Gate voltage so the MOSFET can be turned off
rapidly at zero current crossing. The Gate voltage falls to 1V when the drain-source voltage crosses the detection threshold voltage to minimize
reverse current flow.
6. At zero drain current, the controller Gate output voltage is pulled low to VG(OFF) to ensure that the MOSFET is off.
10%
tr
td(rise)
VT
90%
tf
MOSFET
Drain Voltage
0A
90%
VG(off)
Body Diode
Conduction
td(fall)
10%
VD
MOSFET
Gate Voltage
MOSFET
Drain Current
VG
ID
1
2
34
5
6
Figure 2. Timing Diagram for a Critical Conduction Mode Flyback Converter
tD(RISE)
tR
tD(FALL)
VG(OFF)
tF
ZXGD3107N8
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ZXGD3107N8
Application Information (Cont.)
Gate Driver
The controller is provided with single channel high-current Gate drive output, capable of driving one or more N-channel power MOSFETs. The
controller can operate from VCC of 4.5V to drive both standard MOSFETs and logic level MOSFETs.
The GATE pin should be as close to the MOSFETs Gate as possible. A resistor in series with GATE pin helps to control the rise time and
decrease switching losses due to Gate voltage oscillation. A diode in parallel to the resistor is typically used to maintain fast discharge of the
MOSFET’s Gate.
Figure 3. Typical Connection of the ZXGD3107N8 to the Synchronous MOSFET
When the VCC/VOUT exceeds the maximum VGSS of the MOSFET (typically 20V) then GATE drive voltage needs reducing. It is recommended to
regulate the voltage on RBIAS as this fixes the max GATE output voltage level. The VCC pin can be directly driven from the VOUT up to a max of
40V, and if the converter’s output voltage is higher than 40V then it is also recommended to tie the VCC pin to a series voltage regulator. Figure 4
shows an example for 24V converter output, using the ZXTR2012FF regulator transistor to give a regulated 12V for the MOSFET gate drive.
Figure 4. Reduce GATE Drive Voltage to Less than the VGSS Max of the MOSFET using 12V Regulator Transistor ZXTR2012FF.
REF
DRAIN
GATE
GND
VCC
BIAS
ZXGD3107N8
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ZXGD3107N8
Application Information (Cont.)
Quiescent Current Consumption
The quiescent current consumption of the controller is the sum of IREF and IBIAS. For an application that requires ultra-low standby power
consumption, IREF and IBIAS can be further reduced by increasing the value of resistor RREF and RBIAS.
Bias Current
IBIAS
Ref Current
IREF
Bias Resistor
RBIAS
Ref Resistor
RREF
Quiescent Current
IQ
0.25
0.78
39.8k
11.9k
1.03mA
0.35
0.94
28.4k
9.8k
1.29mA
0.45
1.1
22.1k
8.4k
1.55mA
0.56
1.23
18k
7.5k
1.79mA
0.6
1.34
16.6k
6.9k
1.94mA
0.8
1.6
12.4k
5.8k
2.4mA
Table 2. Quiescent Current Consumption for Different Resistor Values at VCC = 10V
IREF also controls the Gate driver peak sink current whilst IBIAS controls the peak source current. At the default current value of IREF and IBIAS of
1.23mA and 0.56mA, the Gate driver is able to provide 2A source and 6A sink current. The Gate current decreases if IREF and IBIAS are reduced.
Care must be taken in reducing the controller quiescent current so that sufficient drive current is still delivered to the MOSFET particularly for high-
switching frequency application.
Layout Guidelines
When laying out the PCB, care must be taken in decoupling the ZXGD3107N8 closely to VCC and ground with 1μF low-ESR, low-ESL X7R type
ceramic bypass capacitor. If the converter’s output voltage is higher than 40V, a series voltage regulator between the converter’s output voltage
and the VCC pin can be used to get a stable VCC voltage.
GND is the ground reference for the internal high-voltage amplifier as well as the current return for the Gate driver. So the ground return loop
should be as short as possible. Sufficient PCB copper area should be allocated to the VCC and GND pin for heat dissipation especially for high-
switching frequency application.
Any stray inductance involved by the load current may cause distortion of the drain-to-source voltage waveform, leading to premature turn-off of
the synchronous MOSFET. In order to avoid this issue, drain-voltage sensing should be done as physically close to the drain terminals as possible.
The PCB track length between the controller drain pin and MOSFET’s terminal should be kept less than 10mm. MOSFET packages with low
internal-wire-bond inductance are preferred for high-switching frequency power conversion to minimize body diode conduction.
After the primary MOSFET turns-off, its drain voltage oscillates due to reverse recovery of the snubber diode. These high-frequency oscillations
are reflected across the transformer to the drain terminal of the synchronous MOSFET. The synchronous controller senses the drain-voltage
ringing, causing its Gate output voltage to oscillate. The synchronous MOSFET cannot be fully enhanced until the drain voltage stabilizes.
In order to prevent this issue, the oscillations on the primary MOSFET can be damped with either a series resistor Rd to the snubber diode or an
R-C network across the diode. Both methods reduce the oscillations by softening the snubber diode’s reverse recovery characteristic.
ZXGD3107N8
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Application Information (Cont.)
Figure 5. Primary Side Snubber Network to Reduce Drain Voltage Oscillations
DRAIN
REF
BIAS
GATE
GND
VCC
ZXGD3107N8
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ZXGD3107N8
Package Outline Dimensions
Please see http://www.diodes.com/package-outlines.html for the latest version.
SO-8
1
b
e
E
A
A1
(All sides)
±
c
Q
h
45°
R 0.1
D
E0
E1
L
Seating Plane
Gauge Plane
Suggested Pad Layout
Please see http://www.diodes.com/package-outlines.html for the latest version.
SO-8
CX
Y
Y1
X1
SO-8
Dim
Min
Max
Typ
A
1.40
1.50
1.45
A1
0.10
0.20
0.15
b
0.30
0.50
0.40
c
0.15
0.25
0.20
D
4.85
4.95
4.90
E
5.90
6.10
6.00
E1
3.80
3.90
3.85
E0
3.85
3.95
3.90
e
--
--
1.27
h
-
--
0.35
L
0.62
0.82
0.72
Q
0.60
0.70
0.65
All Dimensions in mm
Dimensions
Value (in mm)
C
1.27
X
0.802
X1
4.612
Y
1.505
Y1
6.50
ZXGD3107N8
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ZXGD3107N8
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final and determinative format released by Diodes Incorporated.
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written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
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