MT9V032L12STCES - Micron Technology, Inc.

Applications

Features

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Preliminary‡

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

MT9V032 Image Sensor

Limited Data Sheet

Micron’s MT9V032 is a 1/3-inch wide-VGA format CMOS

active-pixel digital image sensor with global shutter and high

dynamic range (HDR) operation. Designed to support interior

and exterior unattended surveillance imaging needs, the sen-

sor is ideal for a wide variety of imaging applications in real-

world environments. This wide-VGA CMOS image sensor features

DigitalClarity™, Micron’s breakthrough low-noise CMOS imaging

technology that achieves CCD image quality (based on signal-to-

noise ratio and low-light sensitivity) while maintaining the inher-

ent size, cost, and integration advantages of CMOS.

•Micron

® DigitalClarity® CMOS

imaging technology

• Array format: Wide-VGA, active

752H x 480V (360,960 pixels)

• Global shutter photodiode

pixels; simultaneous

integration and readout

• Monochrome or color: Near_IR

enhanced performance for use

with non-visible NIR

illumination

• Readout modes: progressive or

interlaced

• Shutter efficiency: >99%

• Simple two-wire serial

interface

• Register lock capability

•Window size: User

programmable to any smaller

format (QVGA, CIF, QCIF, etc.).

Data rate can be maintained

independent of window size

• Binning: 2 x 2 and 4 x 4 of the

full resolution

• ADC: On-chip, 10-bit column-

parallel (option to operate in

12-bit to 10-bit companding

mode)

•Automatic controls: Auto

exposure control (AEC) and

auto gain control (AGC);

variable regional and variable

weight AEC/AGC

• Support for four unique serial

control register IDs to control

multiple imagers on the same

bus

• Single sensor mode: 10-bit

parallel/stand-alone; 8-bit or

10-bit serial LVDS

• Stereo sensor mode:

Interspersed 8-bit serial LVDS

• Security surveillance camera

• High dynamic range imaging

• Unattended surveillance

• Stereo vision

•Video as input

•Machine vision

•Automation

Parameters

Optical format 1/3-inch

Active imager size 4.51mm(H) x 2.88mm(V)

5.35mm diagonal

Active pixels 752H x 480V

Pixel size 6.0µm x 6.0µm

Color filter array Monochrome or color RGB

Bayer pattern

Shutter type Global shutter—TrueSNAP™

technology

Maximum data rate/

master clock

26.6 Mp/s

26.6 MHz

Full resolution 752 x 480

Frame rate 60 fps (at full resolution)

ADC resolution 10-bit column-parallel

Responsivity 4.8 V/lux-s (550nm)

Dynamic range >55dB linear; >80dB−100dB

in HiDy mode

Supply voltage 3.3V +0.3V (all supplies)

Power consumption <320mW at maximum data

rate; 100µW standby

current

Operating temp. –30°C to +70°C

Packaging 48-pin LLCC

Output gain 15.3 e-/LSB

Read noise 25 e-RMS at 1X

Dark current 9,042 e-/pix/s at 55°C

Draft 8/ 31/ 2006

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Ordering Information

Preliminary

Ordering Information

General Description

The active imaging pixel array of the MT9V032 is 752H x 480V. It incorporates sophisti-

cated camera functions on-chip, such as binning (2 x 2 and 4 x 4 to improve sensitivity

when operating in smaller resolutions), windowing, and column and row mirroring. It is

programmable through a simple two-wire serial interface.

The MT9V032 can be operated in its default mode or be programmed for frame size,

exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-

size image at 60 frames per second (fps).

An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolu-

tion companded for 10-bits for small signals can be alternately enabled, enabling higher

digital accuracy for darker areas in the image.

In addition to a traditional, parallel logic output, the MT9V032 also features a serial low-

voltage differential signaling (LVDS) output. The sensor can be operated in a stereo-

camera mode, and the sensor, designated as a stereo-master, is able to merge the data

from itself and the stereo-slave sensor into one serial LVDS stream.

Figure 1: MT9V032 Block Diagram

Table 1: Available Part Numbers

Part Number Description

MT9V032L12STM ES 48-pin LLCC (mono)

MT9V032L12STC ES 48-pin LLCC (color)

MT9V032L12STMD ES Demo kit (mono)

MT9V032L12STMH ES Demo kit headboard only (mono)

MT9V032L12STCD ES Demo kit (color)

MT9V032L12STCH ES Demo kit headboard only (color)

Parallel

Video

Data Out

Serial

I/O

Control Register

ADCs

Active-Pixel

Sensor (APS)

Array

752H x 480V Timing and Control

Digital Processing

Analog Processing

Serial Video

LVDS Out

Slave Video LVDS In

(for stereo applications only)

Draft 8/ 31/ 2006

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Pin Descriptions

Preliminary

Figure 2: MT9V032 Quantum Efficiency Versus Wavelength

Pin Descriptions

Figure 3: 48-Pin LLCC Package Pinout Diagram

350 450 550 650 750 850 950 1050

Wavelength (nm)

) % ( y c n e i c i f f E m u t n a u Q

Blue

Green (B)

Green (R)

Red

12345644 43

19 20 21 22 23 24 25 2627 28 29 30

LVDSGND

BYPASS_CLKIN_N

BYPASS_CLKIN_P

SER_DATAIN_N

SER_DATAIN_P

LVDSGND

DGND

VDD

DOUT5

DOUT6

DOUT7

DOUT8

DOUT3

DOUT4

VAAPIX

VAA

AGND

VAA

AGND

STANDBY

RESET#

S_CTRL_ADR1

OUT

LINE_VALID

FRAME_VALID

STLN_OUT

EXPOSURE

DATA

SCLK

STFRM_OUT

LED_OUT

RSVD

S_CTRL_ADR0

VDDLVDS

SER_DATAOUT_N

SER_DATAOUT_P

SHFT_CLKOUT_N

SHFT_CLKOUT_P

GND

SYSCLK

PIXCLK

OUT

48 47 4645

Draft 8/ 31/ 2006

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Pin Descriptions

Preliminary

Table 2: Pin Descriptions

Only pins DOUT0 through DOUT9 may be tri-stated.

Pin Numbers Symbol Type Description Note

29 RSVD Input Connect to DGND.1

10 SER_DATAIN_N Input Serial data in for stereoscopy (differential negative). Tie to

1KΩ pull-up (to 3.3V) in non-stereoscopy mode.

11 SER_DATAIN_P Input Serial data in for stereoscopy (differential positive). Tie to

DGND in non-stereoscopy mode.

8 BYPASS_CLKIN_N Input Input bypass shift-CLK (differential negative). Tie to 1KΩ

pull-up (to 3.3V) in non-stereoscopy mode.

9 BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to DGND

in non-stereoscopy mode.

23 EXPOSURE Input Rising edge starts exposure in slave mode.

25 SCLK Input Two-wire serial interface clock. Connect to VDD with

1.5KΩ resistor even when no other two-wire serial

interface peripheral is attached.

28 OE Input DOUT enable pad, active HIGH. 2

30 S_CTRL_ADR0 Input Two-wire serial interface slave address bit 3.

31 S_CTRL_ADR1 Input Two-wire serial interface slave address bit 5.

32 RESET# Input Asynchronous reset. All registers assume defaults.

33 STANDBY Input Shut down sensor operation for power saving.

47 SYSCLK Input Master clock (26.6 MHz).

24 SDATA I/O Two-wire serial interface data. Connect to VDD with 1.5KΩ

resistor even when no other two-wire serial interface

peripheral is attached.

22 STLN_OUT I/O Output in master mode—start line sync to drive slave chip

in-phase; input in slave mode.

26 STFRM_OUT I/O Output in master mode—start frame sync to drive a slave

chip in-phase; input in slave mode.

20 LINE_VALID Output Asserted when DOUT data is valid.

21 FRAME_VALID Output Asserted when DOUT data is valid.

15 DOUT5 Output Parallel pixel data output 5.

16 DOUT6 Output Parallel pixel data output 6.

17 DOUT7 Output Parallel pixel data output 7.

18 DOUT8 Output Parallel pixel data output 8

19 DOUT9 Output Parallel pixel data output 9.

27 LED_OUT Output LED strobe output.

41 DOUT4 Output Parallel pixel data output 4.

42 DOUT3 Output Parallel pixel data output 3.

43 DOUT2 Output Parallel pixel data output 2.

44 DOUT1 Output Parallel pixel data output 1.

45 DOUT0 Output Parallel pixel data output 0.

46 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock.

2 SHFT_CLKOUT_N Output Output shift CLK (differential negative).

3SHFT_CLKOUT_POutput

Output shift CLK (differential positive).

4SER_DATAOUT_NOutput

Serial data out (differential negative).

5 SER_DATAOUT_P Output Serial data out (differential positive).

1, 14 VDD Supply Digital power 3.3V.

35, 39 VAA Supply Analog power 3.3V.

Draft 8/ 31/ 2006

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Pin Descriptions

Preliminary

Notes: 1. Pin 29 (RSVD) must be tied to GND.

2. Output enable (OE) tri-states signals DOUT0–DOUT9. No other signals are tri-stated with OE.

3. No connect. These pins must be left floating for proper operation.

Figure 4: Typical Configuration (connection): Parallel Output Mode

Notes: 1. LVDS signals are to be left floating.

40 VAAPIX Supply Pixel power 3.3V.

DDLVDS Supply Dedicated power for LVDS pads.

7, 12 LVDSGND Ground Dedicated GND for LVDS pads.

13, 48 DGND Ground Digital GND.

34, 38 AGND Ground Analog GND.

36, 37 NC NC No connect. 3

Table 2: Pin Descriptions (continued)

Only pins DOUT0 through DOUT9 may be tri-stated.

Pin Numbers Symbol Type Description Note

SYSCLK

LINE_VALID

FRAME_VALID

PIXCLK

OUT

(9:0)

STANDBY

EXPOSURE

RSVD

S_CTRL_ADR0

S_CTRL_ADR1

LVDSGND

LED_OUT

SDATA

SCLK

RESET#

VDDLVDS

GND

VAAPIX

Master Clock

0.1µF

To Controller

STANDBY from

Controller or

Digital GND

Two-Wire

Serial Interface

VAAPIX

To LED output

10K

1.5K

Draft 8/ 31/ 2006

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Preliminary

Electrical Specifications

Table 3: DC Electrical Characteristics

VPWR = 3.3V ±0.3V; TA = Ambient = 25°C

Symbol Definition Condition Min Typ Max Unit

VIH Input high voltage VPWR - 0.5 – VPWR + 0.3 V

VIL Input low voltage –0.3 – +0.8 V

IIN Input leakage current No pull-up resistor;

VIN = VPWR or VGND

–15.0 – +15.0 μA

VOH Output high voltage IOH = -4.0mA VPWR - 0.7 – – V

VOL Output low voltage IOL = 4.0mA ––0.3V

IOH Output high current VOH = VDD - 0.7 –9.0 – – μA

IOL Output low current VOL = 0.7 ––9.0μA

VAA Analog power supply Default settings 3.0 3.3 3.6 V

IPWRA Analog supply current Default settings – 35.0 60.0 μA

VDD Digital power supply Default settings 3.0 3.3 3.6 V

IPWRD Digital supply current Default settings, CLOAD= 10pF –35.060μA

VAAPIX Pixel array power supply Default settings 3.0 3.3 3.6 V

IPIX Pixel supply current Default settings 0.5 1.4 3.0 μΑ

VLVDS LVDS power supply Default settings 3.0 3.3 3.6 V

ILVDS LVDS supply current Default settings 11.0 13.0 15.0 μA

IPWRA

Standby

Analog standby supply current STANDBY = VDD 234μA

IPWRD

Standby

Clock Off

Digital standby supply current

with clock off

STANDBY = VDD, CLKIN = 0

MHz

124μA

IPWRD

Standby

Clock On

Digital standby supply current

with clock on

STANDBY = VDD, CLKIN = 27

MHz

–1.05– μA

Table 4: LVDS Driver DC Specifications

VPWR = 3.3V ±0.3V; TA = Ambient = 25°C

Symbol Definition Condition Min Typ Max Unit

|VOD| Output differential voltage

RLOAD = 100

Ω ±1%

250 – 400 mV

|DVOD| Change in VOD between

complementary output states

––50mV

VOS Output offset voltage 1.0 1.2 1.4 mV

DVOS Change in VOS between

complementary output states

––35mV

IOS Output current when driver

shorted to ground

–±10 ±12 μA

IOZ Output current when driver is

tri-state

–±1±10 μA

Draft 8/ 31/ 2006

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Preliminary

Notes: 1. Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Expo-

sure to absolute maximum rating conditions for extended periods may affect reliability.

Table 5: LVDS Receiver DC Specifications

VPWR = 3.3V ±0.3V; TA = Ambient = 25°C

Symbol Definition Condition Min Typ Max Unit

Vidth+ Input differential |VGPD| < 925mV –100 – +100 mV

IIN Input current ––

±20 μA

Table 6: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VSUPPLY Power supply voltage (all supplies) –0.3 +4.5 V

ISUPPLY Total power supply current –+200mA

IGND Total ground current –+200mA

VIN DC input voltage –0.3 VDDQ + 0.3 V

VOUT DC output voltage –0.3 VDDQ + 0.3 V

TSTG Storage temperature –40 +125 °C

Draft 8/ 31/ 2006

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of

their respective owners.

Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of

production devices.

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Package Dimensions

PDF: 09005aef824c9998/Source: 09005aef824c999c Micron Technology, Inc., reserves the right to change products or specifications without notice.

Preliminary

Package Dimensions

Figure 5: 48-Pin LLCC Package Outline Drawing

Notes: 1. All dimensions are in millimeters.

2. Optical center position relative to the package center = ±0.10 (X,Y).

SEATING

PLANE

4.4

11.43 ±0.10

LID MATERIAL: BOROSILICATE GLASS 0.55 THICKNESS

MOLD COMPOUND: PLASTIC LAMINATE

SUBSTRATE MATERIAL: PLASTIC LAMINATE

8.8

4.4

2.35 ±0.15

0.8

TYP 0.075

TYP

0.8

TYP

8.8

48 1

10.9

CTR

47X

0.93 ±0.15

48X

R 0.175

1.92 ±0.15

48X

0.40 ±0.05

11.43 ±0.10 10.9

CTR

LEAD FINISH:

Au PLATING, 0.50 MICRONS

MINIMUM THICKNESS

OVER Ni PLATING, 5 MICRONS

MINIMUM THICKNESS

5.715

OPTICAL CENTER1

FIRST

CLEAR

PIXEL

5.715

OPTICAL CENTER1

OPTICAL

AREA

OPTICAL AREA:

MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES B AND C : 1º

MAXIMUM TILT OF OPTICAL AREA RELATIVE TO SEATING PLANE A : 50 MICRONS

MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS D : 100 MICRONS

0.90

FOR REFERENCE

ONLY

1.45 ±0.125

0.35

FOR REFERENCE

ONLY