Package
HALF-BRIDGE GATE DRIVER IC
Features
•Floating channel up to +1200V
•Soft overcurrent shutdown
•Synchronization signal to synchronize shut down
with the other phases
•Integrated desaturation detection circuit
•Two stage turn on output for di/dt control
•Separate pull-up/pull-down output drive pins
•Matched delay outputs
•Under voltage lockout with hysteresis band
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IR2214SS/IR22141SS
24-Lead SSOP
VOFFSET 1200V max.
IO+/- (typ.) 2.0 A / 3.0A
VOUT 10.4V - 20V
Deadtime matching (max) 75nsec
Deadtime (typ) 330nsec
Desat blanking time (typ) 3µsec
DSH,DSL input voltage
threshold (typ) 8.0V
Soft shutdown time (typ) 9.6 µsec
Product Summary
Description
The IR2214SS/IR22141SS) is a gate driver suited to drive
a single half bridge in power switching applications. The
high gate driving capability (2A source, 3A sink) and the
low quiescent current enable bootstrap supply techniques in medium power
systems. The IR2214SS/IR22141SS driver features full short circuit protection by
means of the power transistor desaturation detection. The IR2214SS/IR22141SS
manages all the half-bridge faults by turning off smoothly the desaturated tran-
sistor through the dedicated soft shut down pin, therefore preventing over-volt-
ages and reducing EM emissions. In multi-phase system IR2214SS/IR22141SS
drivers communicate using a dedicated local network (SY_FLT and FAULT/SD
signals) to properly manage phase-to-phase short circuits. The system controller
may force shutdown or read device fault state through the 3.3 V compatible CMOS
I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the
control and power ground use
dedicated pins enabling
low-side emitter current
sensing as well. Under voltage
conditions in floating and low
voltage circuits are managed
independently.
Typical Connection
(Refer to Lead Assignments for
correct pin configuration). This/
These diagram(s) show electrical
connections only. Please refer to
our Application Notes and
DesignTips for proper circuit
board layout.
Data Sheet No. PD60213
ADVANCE DATA
DC+
DC-
DC BUS
(1200V)
VCC
LIN
HIN
FAULT/SD
VB
HOP
HON
SSDH
DSH
VS
LOP
LON
SSDL
DSL
COM
VSS
IR2214
FLT_CLR
SY_FLT
15 V
uP,
Control
Motor
IR2214SS/IR22141SS
2
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ADVANCE DATA
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output
drivers if the UV thresholds are not reached.
Note 2: Logic operational for VS from VSS-5 to VSS+1200V. Logic state held for VS from VSS-5V to VSS-VBS. (Please
refer to the Design Tip DT97-3 for more details).
Symbol Definition Min. Max. Units
VBHigh side floating supply voltage (Note 1) VS + 11.5 VS + 20
VSHigh side floating supply offset voltage Note 2 1200
VHO High side output voltage (HOP, HON and SSDH) VSVS + 20
VLO Low side output voltage (LOP, LON and SSDL) VCOM VCC
VCC Low side and logic fixed supply voltage (Note 1) 11.5 20
C O M Power ground - 5 5
VIN Logic input voltage (HIN, LIN and FLT_CLR) 0 VCC
VFLT Fault input/output voltage (FAULT/SD and SY_FLT) 0 VCC
VDSH High side DS pin input voltage VB - 20 VB
VDSL Low side DS pin input voltage VCC - 20 V CC
TAAmbient temperature -40 125 °C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absoute
voltages referenced to VSS. The VS offset rating is tested with all supplies biased at 15V differential.
V
Symbol Definition Min. Max. Units
VSHigh side offset voltage VB - 25 VB + 0.3
VBHigh side floating supply voltage -0.3 1225
VHO High side floating output voltage (HOP, HON and SSDH) VS - 0.3 VB + 0.3
VCC Low side and logic fixed supply voltage -0.3 25
COM Power ground VCC - 25 VCC + 0.3
VLO Low side output voltage (LOP, LON and SSDL) VCOM -0.3 VCC + 0.3
VIN Logic input voltage (HIN, LIN and FLT_CLR) -0.3 VCC + 0.3
VFLT FAULT input/output voltage (FAULT/SD and SY_FLT) -0.3 VCC + 0.3
VDSH High side DS input voltage VB -25 VB + 0.3
VDSL Low side DS input voltage VCC - 25 VCC + 0.3
dVs/dt Allowable offset voltage slew rate — 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C — 1.5 W
RthJA Thermal resistance, junction to ambient — 65 °C/W
TJJunction temperature — 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) — 30 0
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
V
°C
3
IR2214/IR22141(SS)
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ADVANCE DATA
Pin: VCC, VSS, VB, VS
Symbol Definition Min Typ Max Units Test Conditions
VCCUV+ Vcc supply undervoltage positive going threshold 9.3 10.2 11.4
VCCUV- Vcc supply undervoltage negative going threshold 8.7 9.3 10.3
VCCUVH Vcc supply undervoltage lockout hysteresis - 0.9 -
VBSUV+ (VB-VS) supply undervoltage positive going threshold 9.3 10.2 11.4 VS=0V, VS=1200V
VBSUV- (VB-VS) supply undervoltage negative going threshold 8.7 9.3 10.3 VS=0V, VS=1200V
VBSUVH (VB-VS) supply undervoltage lockout hysteresis - 0.9 -
V
ILK Offset supply leakage current - - 50 VB = VS = 1200V
IQBS Quiescent VBS supply current - 400 800 µA VIN = 0V or 3.3V
IQCC Quiescent Vcc supply current - 0.7 2.5 mA (No load)
VCC/VB
VCCUV/VBSUV
VSS/VS
comparator
UV internal
signal
Figure 1: Undervoltage diagram
HIN/LIN/
FLTCLR
VSS
schmitt
trigger
10k
internal
signal
Figure 2: HIN, LIN and FLTCLR diagram
Static Electrical Characteristics
VCC = 15 V, VSS = COM = 0 V, VS = 0 ÷ 1200 V and TA = 25 oC unless otherwise specified.
Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol Definition Min Typ Max Units Test Conditions
VIH Logic "1" input voltage 2.0 - -
VIL Logic "0" input voltage - - 0.8
VIHSS Logic input hysteresis 0.2 0.4 -
V VCC = VCCUV- to
20V
IIN+ Logic "1" input bias current - 370 - µA VIN = 3.3V
IIN- Logic "0" input bias current -1 - 0 VIN = 0V
RON,FLT FAULT/SD open drain resistance - 60 -
RON,SY SY_FLT open drain resistance - 60 -
Ω PW ? 7 µs
µA
≤
4
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ADVANCE DATA
The active bias is present only in IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS
respectively for DSL and DSH.
Symbol Definition Min Typ Max Units Test Conditions
VDESAT+ High desat input threshold voltage 7.2 8.0 8.8
VDESAT- Low desat input threshold voltage 6.3 7.0 7.7
VDSTH Desat input voltage hysteresis - 1.0 -
V See Fig. 16, 4
IDS+ High DSH or DSL input bias current - 21 - VDESAT = VCC or VBS
IDS- Low DSH or DSL input bias current - -160 - µA VDESAT = 0V
IDSB DSH or DSL input bias current (IR22141 only) - -20 - mA VDESAT =
(VCC or VBS) - 2V
Pin: DSL, DSH
DSL/DSH
VDESAT
COM/VS
comparator
100k
700k
VCC/VBS
SSD internal
signal
active
bias
Figure 4: DSH and DSL diagram
FAULT/SD
SY_FLT
VSS
schmitt
trigger
RON
fault/hold
internal signal
hard/soft shutdown
internal signal
Figure 3: FAULT/SD and SY_FLT diagram
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ADVANCE DATA
Pin: HOP, LOP
LOP/HOP
VCC/VB
on/off
internal signal
VOH
200ns
oneshot
Figure 5: HOP and LOP diagram
SSDL/SSDH
COM/VS
on/off
internal signal
RON,SSD
LON/HON
desat
internal signal
VOL
Figure 6: HON, LON, SSDH and SSDL diagram
Pin: HON, LON, SSDH, SSDL
Note 1: SSD operation only.
Symbol Definition Min Typ Max Units Test Conditions
VOH High level output voltage, VB – VHOP or Vcc –VLOP - 20 100
mV IO = 1mA
IO1+ Output high first stage short circuit pulsed current - 2 - VHOP/LOP=0V,
HIN or LIN= 1,
PW?200ns,
resistive load,
see Fig. 8
IO2+ Output high second stage short circuit pulsed current
- 1 - A
VHOP/LOP=0V,
HIN or LIN = 1,
400ns?PW?10µs,
resistive load,
see Fig. 8
≤
≤≤
Symbol Definition Min Typ Max Units Test Conditions
VOL Low level output voltage, VHON or VLON - 2.3 15
mV IO = 1mA
RON,SSD Soft Shutdown on resistance (Note 1) - 90 - Ω PW ? 7 µs
IO- Output low short circuit pulsed current - 3 - A VHOP/LOP=15V,
HIN or LIN = 0,
PW?10µs
≤
≤
6
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ADVANCE DATA
AC Electrical Characteristics
VCC = VBS = 15V, VS = VSS and TA = 25°C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn on propagation delay 220 440 660 VIN = 0 & 1
toff Turn off propagation delay 220 440 660 VS = 0 to 1200V
tr Turn on rise time (CLOAD=1nF) — 24 —
HOP shorted to HON,
LOP shorted to LON,
tf Turn off fall time (CLOAD=1nF) — 7 — Figure 7, 10
ton1 Turn on first stage duration time 120 200 280 Figure 8
tDESAT1 DSH to HO soft shutdown propagation delay at HO 2000 3300 4600
turn on VHIN= 1
tDESAT2 DSH to HO soft shutdown propagation delay after 1050 — — VDESAT = 15V,Fig.10
Blanking
tDESAT3 DSL to LO soft shutdown propagation delay at LO 2000 3300 4600
turn on VLIN = 1
tDESAT4 DSL to LO soft shutdown propagation delay after 1050 — — VDESAT = 15V,Fig.10
Blanking
tDS Soft shutdown minimum pulse width of desat 1000 — — Figure 9
tSS Soft shutdown duration period 5700 9600 13500 CL=TBD µF,
VDS=15V,Fig. 9
tSY_FLT, DSH to SY_FLT propagation delay at HO turn on — 3600 —
DESAT1 VHIN = 1
tSY_FLT, DSH to SY_FLT propagation delay after blanking 1300 — — VDS = 15V, Fig. 10
DESAT2
tSY_FLT, DSL to SY_FLT propagation delay at LO turn on — 3050 —
DESAT3 VLIN = 1
tSY_FLT, DSL to SY_FLT propagation delay after blanking 1050 — — VDESAT=15V,Fig.10
DESAT4
tBL DS blanking time at turn on — 3000 — VHIN = VLIN = 1
VDESAT=15V,Fig.10
Dead-time/Delay Matching Characteristics
DT Dead-time — 330 — Figure 11
MDT Dead-time matching, MDT=DTH-DTL — — 75 External DT=0nsec
Figure 11
PDM Propagation delay matching, — — 75 External DT>
Max(ton, toff) - Min(ton, toff)
ns
500nsec, Fig.7
T
VDS=15V, Fig 9
7
IR2214/IR22141(SS)
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ADVANCE DATA
HIN
LIN
HO (HOP=HON)
LO (LOP=LON)
10%
3.3V
10%
90% 90%
50% 50%
tr
ton toff tf
PWin
PWout
Figure 7: Switching Time Waveforms
Ton1
Io1+
Io2+
Figure 8: Output Source Current
8
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ADVANCE DATA
HIN/LIN
HO/LO
VDESAT+ VDESAT-
tSS
tDESAT
3.3V
DSH/DSL
tDS
SSD Driver Enable
Figure 9: Soft Shutdown Timing Waveform
9
IR2214/IR22141(SS)
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ADVANCE DATA
HIN
DSH
SY_FLT
HON
FAULT/SD
FLTCLR
LIN
LON
DSL
50%
50%
50%
8V
8V
8V 8V
50% 50% 50% 50%
50% 90% 90%
50%
10%
90%
50% 90%
10%
90%
50%
ton
tBL
SoftShutdown
tDESAT1
tSY_FLT,DESAT1
tBL tDESAT2
tSY_FLT,DESAT2
SoftShutdown
ton
tBL
tDESAT3
tSY_FLT,DESAT3
SoftShutdown
tBL tDESAT4
SoftShutdown
tSY_FLT,DESAT4
toff
Figure 10: Desat Timing
HIN
LIN
HO (HOP=HON)
LO (LOP=LON)
DTH DTL
50%
50%
50% 50%
50%
MDT=DTH-DTL
50%
Figure 11: Internal Dead-Time Timing
10
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ADVANCE DATA
Symbol Description
VCC Low side gate driver supply
VSS Logic Ground
HIN Logic input for high side gate driver outputs (HOP/HON)
LIN Logic input for low side gate driver outputs (LOP/LON)
FAULT/SD
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates fault
condition. As an input, shuts down the outputs of the gate driver regardless HIN/LIN status.
SY_FLT
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates SSD
sequence is occurring. As an input, an active low signal freezes both output status.
FLT_CLR Fault clear active high input. Clears latched fault condition (See figure 17)
LOP Low side driver sourcing output
LON Low side driver sinking output
DSL Low side IGBT desaturation protection input
SSDL Low side soft shutdown
COM Low side driver return
VB High side gate driver floating supply
HOP High side driver sourcing output
HON High side driver sinking output
DSH High side IGBT desaturation protection input
SSDH High side soft shutdown
VS High side floating supply return
Lead Definitions
SSOP24
1
12
24
13
SSDL
FLT_CLR
HIN
COM
SY_FLT
LON
FAULT/SD
VSS
LOP
VCC
DSL
HOP
SSDH
HON
N.C.
VS
N.C.
DSH
VB
N.C.
N.C.
N.C.
N.C.
LIN
24-Lead SSOP – IR2214SS
Lead Assignments
11
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ADVANCE DATA
Functional Block Diagram
SCHMITT
TRIGGER
INPUT
SHOOT
THROUGH
PREVENTION
(DT) Deadtime
LEVEL
SHIFTERS
LATCH
LOCAL DESAT
PROTECTION
SOFT SHUTDOWN
UV_VBS DETECT
di/dt control
Driver
UV_VCC
DETECT
LOCAL DESAT
PROTECTION
SOFTSHUTDOWN
di/dt control
Driver
on/off
on/off
desat
soft
shutdown
on/off
soft
shutdown
on/off (HS)
DesatHS
DesatLS
on/off (LS)
Hard ShutDown
internal Hold
SD
FAULT LOGIC
managemend
(See figure 14)
UV_VCC
VB
HOP
HON
SSDH
DSH
VS
LOP
LON
SSDL
DSL
COM
VSS
FLT_CLR
FAULT/SD
SY_FLT
LIN
HIN
VCC
FAULT
HOLDSSD
INPUT
HOLD
LOGIC
OUTPUT
SHUTDOWN
LOGIC
12
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ADVANCE DATA
NOTE1: a change of logic value of the signal labeled on lines (system variable) generates a state
transition.
NOTE2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event
happens in HIN.
Stable State
− FAULT
− HO=LO=0 (Normal
operation)
− HO/LO=1 (Normal
operation)
− UNDERVOLTAGE VCC
− SHUTDOWN (SD)
− UNDERVOLTAGE VBS
− FREEZE
Temporary State
− SOFT SHUTDOWN
− START UP SEQUENCE
System Variable
− FLT_CLR
− HIN/LIN
− UV_VCC
− UV_VBS
− DSH/L
− SY_FLT
− FAULT/SD
Start-Up
Sequence
FAULT
HO/LO=1
HO=LO=0
UnderVoltage
VCC
HO=LO=0
Freeze
ShutDown
SY_FLT
SY_FLT
SY_FLT
FLT_CLR
HIN/LIN
HIN/LIN
UV_VCC
UV_VCC
UV_VBS
FAULT/SD
DSH/L
DSH/L
FAULT/SD
FAULT/SD
FAULT/SD
FAULT/SD
UV_VBS
UV_VCC
DESAT
EVENT
UnderVoltage
VBS
HO=0, LO=LIN
Soft
ShutDown
State Diagram
13
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ADVANCE DATA
HO/LO
status
HOP/LOP HON/LON SSDH/SSDL
0 HiZ 0 HiZ
1 1 HiZ HiZ
SSD HiZ HiZ 0
LO/HO Output follows inputs (in=1->out=1, in=0->out=0)
LOn-1/HOn-1 Output keeps previous status
IR2214 Logic Table
NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required.
In order to avoid FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be
operated while SY_FLT is active.
INPUTS
INPUT/OUTPUT
Under Voltage
Yes: V< UV threshold
No : V> UV threshold
X : don’t care
OUTPUTS
Hin
Lin
FLT_CLR SY_FLT
SSD: desat (out)
HOLD: freezing (in)
FAULT/SD
SD: shutdown (in)
FAULT: diagnostic (out)
VCC V
BS HO LO
X X X X 0
(SD) X X 0 0
HIN LIN NOTE1 (FAULT) No No HO LO
1 0 0 1 1 No No 1 0
0 1 0 1 1 No No 0 1
0 0 0 1 1 No No 0 0
1 1 0 1 1 No No 0 0
1 0 0 (SSD) 1 No No SSD 0
0 1 0 (SSD) 1 No No 0 SSD
X X 0 (SSD) (FAULT) No No 0 0
X X 0 (SSD) (FAULT) No No 0 0
X X X 0
(HOLD) 1 No No HOn-1 LOn-1
X LIN X 1 1 No Yes 0 LO
X X X 1 0
(FAULT) Yes X 0 0
Normal
Operation
Anti Shoot
Through
Soft Shut Down (entering)
Soft Shut Down (finishing)
Freeze
Shut Down
Fault Clear
Operation
Under Voltage
Output drivers status description
14
IR2214/IR22141(SS)
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ADVANCE DATA
FEATURES DESCRIPTION
1. Start-up sequence
At power supply start-up it is recommended to
keep FLT_CLR pin active until supply voltages
are properly established. This prevents spurious
diagnostic signals being generated. All protection
functions are operating independently from
FLT_CLR status and output driver status reflects
the input commands.
When bootstrap supply topology is used for
supplying the floating high side stage, the
following start-up sequence is recommended
(see also figure 12):
1. Set Vcc
2. Set FLT_CLR pin to HIGH level
3. Set LIN pin to HIGH level and let the
bootstrap capacitor be charged
4. Release LIN pin to LOW level
5. Release FLT_CLR pin to LOW level
Figure 12 Start-up sequence
A minimum 15µs LIN and FLT-CLR pulse is
required.
VCC
FLT_CLR
LIN
LO
2. Normal operation mode
After start-up sequence has been terminated, the
device becomes fully operative (see grey blocks
in the State Diagram).
HIN and LIN produce driver outputs to switch
accordingly, while the input logic checks the input
signals preventing shoot-through events and
including DeadTime (DT).
3. Shut down
The system controller can asynchronously
command the Hard ShutDown (HSD) through the
3.3 V compatible CMOS I/O FAULT/SD pin. This
event is not latched.
In a multi-phase system, FAULT/SD signals are
or-wired so the controller or one of the gate drivers
can force simultaneous shutdown to the other
gate drivers through the same pin.
4. Fault management
IR2214 is able to manage both the supply failure
(undervoltage lock out on both low and high side
circuits) and the desaturation of both power
transistors.
4.1 Undervoltage (UV)
The Undervoltage protection function disables the
driver’s output stage preventing the power device
being driven with too low voltages.
Both the low side (VCC supplied) and the floating
side (VBS supplied) are controlled by a dedicate
undervoltage function.
Undervoltage event on the VCC (when
VCC < UVVCC-) generates a diagnostic signal by
forcing FAULT/SD pin low (see FAULT/SD section
and figure 14). This event disables both low side
and floating drivers and the diagnostic signal holds
until the under voltage condition is over. Fault
condition is not latched and the FAULT/SD pin is
released once VCC becomes higher than UVVCC+.
15
IR2214/IR22141(SS)
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ADVANCE DATA
The undervoltage on the VBS works disabling only
the floating driver. Undervoltage on VBS does not
prevent the low side driver to activate its output
nor generate diagnostic signals. VBS undervoltage
condition (VBS < UVVBS-) latches the high side
output stage in the low state. VBS must be
reestablished higher than UVVBS+ to return in
normal operating mode. To turn on the floating
driver HIN must be re-asserted high (rising edge
event on HIN is required).
4.2 Power devices desaturation
Different causes can generate a power inverter
failure: phase and/or rail supply short-circuit,
overload conditions induced by the load, etc…
In all these fault conditions a large current
increase is produced in the IGBT.
The IR2214 fault detection circuit monitors the
IGBT emitter to collector voltage (VCE) by means
of an external high voltage diode. High current in
the IGBT may cause the transistor to desaturate,
i.e. VCE to increase.
Once in desaturation, the current in power
transistor can be as high as 10 times the nominal
current. Whenever the transistor is switched off,
this high current generates relevant voltage
transients in the power stage that need to be
smoothed out in order to avoid destruction (by
over-voltages). The IR2214 gate driver accomplish
the transients control by smoothly turning off the
desaturated transistor by means of the SSD pin
activating a so called Soft ShutDown sequence
(SSD).
4.2.1 Desaturation detection: DSH/L function
Figure 13 shows the structure of the desaturation
sensing and soft shutdown block. This configu-
ration is the same for both high and low side
output stages.
Figure 13: high and low side output stage
tBL
Blanking
VB/Vcc
HON/LON
DSH/L
VS/COM
Ron,ss
HOP/LOP
tss
One Shot
VDESAT
(ton1)
ONE
SHOT
tDS
filter
SSDH/L
RDSH/L
P
Pr
re
eD
Dr
ri
iv
ve
er
r
sensing
diode
on/off
DesatHS/LS
desat
comparator
16
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ADVANCE DATA
FLTCLR
Q
QSET
CLR
S
R
FAULT/SD
SY_FLT
internal
HOLD
(external
hold)
(external hard
shutdown)
internal FAULT
(hard shutdown)
UVCC
DesatHS
DesatLS
Figure 14: fault management diagram
The external sensing diode should have
BV>1200V and low stray capacitance (in order
to minimize noise coupling and switching de-
lays). The diode is biased by an internal pull-up
resistor RDSH/L (equal to VCC/IDS- or VBS/IDS- for
IR2214) or by a dedicated circuit (see the active-
bias section for the IR22141). When VCE in-
creases, the voltage at DSH/L pin increases too.
Being internally biased to the local supply,
DSH/L voltage is automatically clamped. When
DSH/L exceeds the VDESAT+ threshold the com-
parator triggers (see figure 13). Comparator
output is filtered in order to avoid false
desaturation detection by externally induced
noise; pulses shorter than tDS are filtered out. To
avoid detecting a false desaturation during IGBT
turn on, the desaturation circuit is disabled by a
Blanking signal (TBL, see Blanking block in fig-
ure 13). This time is the estimated maximum
IGBT turn on time and must be not exceeded by
proper gate resistance sizing. When the IGBT is
not completely saturated after TBL, desaturation
is detected and the driver will turn off.
Eligible desaturation signals initiate the Soft
Shutdown sequence (SSD). While in SSD, the
output driver goes in high impedance and the
SSD pull-down is activated to turn off the IGBT
through SSDH/L pin. The SY_FLT output pin
(active low, see figure 14) reports the IR2214
status all the way long SSD sequence lasts (tSS).
Once finished SSD, SYS_FLT releases, and
IR2214 generates a FAULT signal (see the
FAULT/SD section) by activating FAULT/SD pin.
This generates a hard shut down for both high
and low output stages (HO=LO=low). Each driver
is latched low until the fault is cleared (see
FLT_CLR).
Figure 14 shows the fault management circuit.
In this diagram DesatHS and DesatLS are two
internal signals that come from the output stages
(see figure 13).
17
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ADVANCE DATA
It must be noted that while in Soft Shut Down,
both Under Voltage fault and external Shut Down
(SD) are masked until the end of SSD.
Desaturation protection is working independently
by the other entire control pin and it is disabled
only when the output status is off.
VCC
LIN
HIN
FLT_CLR
VB
HOP
HON
SSH
DSH
VS
LOP
LON
SSL
DSL
COMVSS
SY_FLT
FAULT/SD
IR2214
VCC
LIN
HIN
FLT_CLR
VB
HOP
HON
SSH
DSH
VS
LOP
LON
SSL
DSL
COMVSS
SY_FLT
FAULT/SD
IR2214
VCC
LIN
HIN
FLT_CLR
VB
HOP
HON
SSH
DSH
VS
LOP
LON
SSL
DSL
COMVSS
SY_FLT
FAULT/SD
IR2214
phase U phase V phase W
FAULT
4.2.2 Fault management in multi-phase
systems
In a system with two or more gate drivers the
IR2214 devices must be connected as in figure 15.
SY_FLT.
The bi-directional SY_FLT pins communicate
each other in the local network. The logic signal
is active low.
The device that detects the IGBT desaturation
activates the SY_FLT, which is then read by the
other gate drivers. When SYS_FLT is active all
the drivers hold their output state regardless the
input signals (HIN, LIN) they receive from the
controller (freeze state).
This feature is particularly important in phase-
to-phase short circuit where two IGBTs are
involved; in fact, while one is softly shutting-down,
the other must be prevented from hard shutdown
to avoid vanishing SSD.
In the Freeze state the frozen drivers are not
completely inactive because desaturation
detection still takes the highest priority.
SY_FLT communication has been designed for
creating a local network between the drivers.
There is no need to wire SY_FLT to the controller.
FAULT/SD
The bi-directional FAULT/SD pins communicates
each other and with the system controller. The
logic signal is active low.
When low, the FAULT/SD signal commands the
outputs to go off by hard shutdown. There are
three events that can force FAULT/SD low:
1. Desaturation detection event: the
FAULT\SD pin is latched low when SSD
is over, and only a FLT_CLR signal can
reset it.
Figure 15: IR2214 application in 3ph system.
18
IR2214/IR22141(SS)
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2. Undervoltage on VCC: the FAULT\SD pin
is forced low and held until the
undervoltage is active (not latched).
3. FAULT/SD is externally driven low either
from the controller or from another
IR2214 device. This event is not latched;
therefore the FLT_CLR cannot disable
it. Only when FAULT/SD becomes high
the device returns in normal operating
mode.
5. Active bias
For the purpose of sensing the power transistor
desaturation the collector voltage is read by an
external HV diode. The diode is normally biased
by an internal pull up resistor connected to the
local supply line (VB or VCC). When the transistor
is “on” the diode is conducting and the amount
of current flowing in the circuit is determined by
the internal pull up resistor value.
In the high side circuit, the desaturation biasing
current may become relevant for dimensioning
the bootstrap capacitor (see figure 19). In fact,
too low pull up resistor value may result in high
current discharging significantly the bootstrap
capacitor. For that reason typical pull up resistor
are in the range of 100 kΩ. This is the value of
the internal pull up.
While the impedance of DSH/DSL pins is very
low when the transistor is on (low impedance
path through the external diode down to the power
transistor), the impedance is only controlled by
the pull up resistor when the transistor is off. In
that case relevant dV/dt applied by the power
transistor during the commutation at the output
results in a considerable current injected through
the stray capacitance of the diode into the
desaturation detection pin (DSH/L). This coupled
noise may be easily reduced using an active bias
for the sensing diode.
An Active Bias structure is available only for
IR22141 version for DSH/L pin. The DSH/L pins
present an active pull-up respectively to VB/VCC,
and a pull-down respectively to VS/COM.
The dedicated biasing circuit reduces the
impedance on the DSH/L pin when the voltage
exceeds the VDESAT threshold (see figure 16). This
low impedance helps in rejecting the noise
providing the current inject by the parasitic
capacitance. When the power transistor is fully
on, the sensing diode gets forward biased and
the voltage at the DSH/L pin decreases. At this
point the biasing circuit deactivates, in order to
reduce the bias current of the diode as shown in
figure 16.
Figure 16: RDSH/L Active Biasing
6. Output stage
The structure is shown in figure 13 and consists
of two turns on stages and one turn off stage.
When the driver turns on the IGBT (see figure 8),
a first stage is constantly activated while an
additional stage is maintained active only for a
limited time (ton1). This feature boost the total
driving capability in order to accommodate both
fast gate charge to the plateau voltage and dV/dt
control in switching.
VDSH/L
VDESAT-
VDESAT+
100 ohm
100K ohm
RDSH/L
19
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At turn off, a single n-channel sinks up to 3A (IO-
) and offers a low impedance path to prevent the
self-turn on due to the parasitic Miller capacitance
in the power switch.
HIN
LIN
FAULT/SD
LO(LOP/LON)
DSH
FLT_CLR
SY_FLT
HO(HOP/HON)
DSL
A B C D E F G
Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output
7. Timing and logic state diagrams
description
The following figures show the input/output logic
diagram.
Figure 17 shows the SY_FLT and FAULT/SD
signals as output, whereas figure 18 shows them
as input.
20
IR2214/IR22141(SS)
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AB C D E F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input
Referred to timing diagram of figure 17:
A. When the input signals are on together the
outputs go off (anti-shoot through).
B. The HO signal is on and the high side IGBT
desaturates, the HO turn off softly while the
SY_FLT stays low. When SY_FLT goes high
the FAULT/SD goes low. While in SSD, if
LIN goes up, LO does not change (freeze).
C. When FAULT/SD is latched low (see FAULT/
SD section) FLT_CLR can disable it and the
outputs go back to follow the inputs.
D. The DSH goes high but this is not read
because HO is off.
E. The LO signal is on and the low side IGBT
desaturates, the low side behaviour is the
same as described in point B.
F. The DSL goes high but this is not read
because LO is off.
G. As point A (anti-shoot through).
Referred to logic diagram figure 18:
A. The device is in hold state, regardless of input
variations. Hold state is forced by SY_FLT
forced low externally
B. The device outputs goes off by hard
shutdown, externally commanded. A through
B is the same sequence adopted by another
IR2214 device in SSD procedure.
C. Externally driven low FAULT/SD (shutdown
state) cannot be disabled by forcing FLT_CLR
(see FAULT/SD section).
D. The FAULT/SD is released and the outputs
go back to follow the inputs.
E. Externally driven low FAULT/SD: outputs go
off by hard shutdown (like point B).
F. As point A and B but for the low side output.
21
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Sizing tips
Bootstrap supply
The VBS voltage provides the supply to the high
side driver circuitry of the IR2214. This supply
sits on top of the VS voltage and so it must be
floating.
The bootstrap method to generate VBS supply
can be used with IR2214. The bootstrap supply
is formed by a diode and a capacitor connected
as in figure 19.
Figure 19: bootstrap supply schematic
This method has the advantage of being simple
and low cost but may force some limitations on
duty-cycle and on-time since they are limited by
the requirement to refresh the charge in the boot-
strap capacitor.
Proper capacitor choice can reduce drastically
these limitations.
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is
to establish the minimum voltage drop (
∆
VBS)
that we have to guarantee when the high side
IGBT is on.
bootstrap
diode
IR2214
bootstrap
capacitor
VB
VS
VCC
HOP
HON
SSDH
DC+
bootstrap
resistor
COM
VCC
VBS
VF
VGE
VCEon
VFP
ILOAD
motor
Rboot
If VGEmin is the minimum gate emitter voltage we
want to maintain, the voltage drop must be:
under the condition:
where VCC is the IC voltage supply, VF is boot-
strap diode forward voltage, VCEon is emitter-col-
lector voltage of low side IGBT and VBSUV- is the
high-side supply undervoltage negative going
threshold.
Now we must consider the influencing factors
contributing VBS to decrease:
- IGBT turn on required Gate charge (QG);
- IGBT gate-source leakage current (ILK_GE);
- Floating section quiescent current (IQBS);
- Floating section leakage current (ILK)
- Bootstrap diode leakage current (ILK_DIODE);
- Desat diode bias when on (IDS- )
- Charge required by the internal level shifters
(QLS); typical 20nC
- Bootstrap capacitor leakage current (ILK_CAP);
- High side on time (THON).
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend
using at least one low ESR ceramic capacitor
(paralleling electrolytic and low ESR ceramic
may result in an efficient solution).
Then we have:
CEonGEFCCBS VVVVV −−−≤∆ min
−
>BSUVGE VV min
++++= QBSGELKLSGTOT IIQQQ _
(
HONDSCAPLKDIODELKLK TIIII ⋅++++ −)
__
22
IR2214/IR22141(SS)
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ADVANCE DATA
The minimum size of bootstrap capacitor is:
An example follows:
a) using a 25A @ 125C IGBT (IRGP30B120KD):
• IQBS = 800 µA (See Static Electrical Charact.);
• ILK = 50 µA (See Static Electrical Charact.);
• QLS = 20 nC;
• QG = 160 nC (Datasheet IRGP30B120KD);
• ILK_GE = 100 nA (Datasheet IRGP30B120KD);
• ILK_DIODE = 100 µA (with reverse recovery
time <100 ns);
• ILK_CAP = 0 (neglected for ceramic capacitor);
• IDS- = 150 µA (see Static Electrical Charact.);
• THON = 100 µs.
And:
•VCC = 15 V
•VF = 1 V
•VCEonmax = 3.1 V
•VGEmin = 10.5 V
the maximum voltage drop ∆VBS becomes
and the boodstrap capacitor is:
BS
TOT
BOOT V
Q
C∆
=
min
=−−−≤∆ CEonGEFCCBS VVVVV min
VVVVV 4.01.35.10115 =−−−=
nF
V
nC
CBOOT 725
4.0
290 =≥
NOTICE: Here above VCC has been cho-
sen to be 15V. Some IGBTs may require
higher supply to work correctly with the boot-
strap technique. Also Vcc variations must be
accounted in the above formulas.
Some important considerations
a. Voltage ripple
There are three different cases making the boot-
strap circuit gets conductive (see figure 19):
• I
LOAD < 0; the load current flows in the low
side IGBT displaying relevant VCEon
In this case we have the lowest value for VBS.
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off
the Vs node is pushed up by the load current
until the high side freewheeling diode get for-
warded biased
•ILOAD = 0; the IGBT is not loaded while be-
ing on and VCE can be neglected
•ILOAD > 0; the load current flows through the
freewheeling diode
In this case we have the highest value for VBS.
Turning on the high side IGBT, ILOAD flows into
it and VS is pulled up.
To minimize the risk of undervoltage, bootstrap
capacitor should be sized according to the
ILOAD<0 case.
CEonFCCBS VVVV −−=
FCCBS VVV −=
FPFCCBS VVVV +−=
23
IR2214/IR22141(SS)
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ADVANCE DATA
b. Bootstrap Resistor
A resistor (Rboot) is placed in series with boot-
strap diode (see figure 19) so to limit the current
when the bootstrap capacitor is initially charged.
We suggest not exceeding some Ohms (typi-
cally 5, maximum 10 Ohm) to avoid increasing
the VBS time-constant. The minimum on time for
charging the bootstrap capacitor or for refresh-
ing its charge must be verified against this time-
constant.
c. Bootstrap Capacitor
For high THON designs where is used an electro-
lytic tank capacitor, its ESR must be consid-
ered. This parasitic resistance forms a voltage
divider with Rboot generating a voltage step on VBS
at the first charge of bootstrap capacitor. The
voltage step and the related speed (dVBS/dt)
should be limited. As a general rule, ESR should
meet the following constraint:
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best com-
promise, the first acting as fast charge thank for
the gate charge only and limiting the dVBS/dt by
reducing the equivalent resistance while the sec-
ond keeps the VBS voltage drop inside the de-
sired ∆VBS.
d. Bootstrap Diode
The diode must have a BV> 1200V and a fast
recovery time (trr < 100 ns) to minimize the
amount of charge fed back from the bootstrap
capacitor to VCC supply
VV
RESRESR CC
BOOT
3≤⋅
+
Gate resistances
The switching speed of the output transistor can
be controlled by properly size the resistors con-
trolling the turn-on and turn-off gate current. The
following section provides some basic rules for
sizing the resistors to obtain the desired switch-
ing time and speed by introducing the equivalent
output resistance of the gate driver (RDRp and
RDRn).
The examples always use IGBT power transis-
tor. Figure 20 shows the nomenclature used in
the following paragraphs. In addition, Vge
* indi-
cates the plateau voltage, Qgc and Qge indicate
the gate to collector and gate to emitter charge
respectively.
Figure 20: Nomenclature
Vge*
10%
t1,QGE
CRESoff
CRESon
VCE
IC
VGE
CRES
10%
90% CRES
tDon
VGE
dV/dt
IC
t2,QGC
t,Q
tR
tSW
24
IR2214/IR22141(SS)
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ADVANCE DATA
≤
>
−+⋅
=
+
++
1
1
1
121
11
onSW
o
onSW
on
SW
ooSW
on
DRp ttwhen
I
Vcc
ttwhen
t
t
I
Vcc
I
Vcc
t
t
R
When RGon > 7 Ohm, RDRp is defined by
(IO1+ ,IO2+ and ton1 from the IR2214 datasheet).
RESoff
avg
out C
I
dt
dV =
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using
typical datasheet values and assuming
Vcc=15V).
• Output voltage slope
Turn-on gate resistor RGon can be sized to con-
trol output slope (dVOUT/dt).
While the output voltage has a non-linear
behaviour, the maximum output slope can be ap-
proximated by:
inserting the expression yielding Iavg and
rearranging:
As an example, table 2 shows the sizing of gate
resistance to get dVout/dt=5V/ns when using two
popular IGBTs, typical datasheet values and
assuming Vcc=15V.
NOTICE: Turn on time must be lower than TBL to
avoid improper desaturation detection and SSD
triggering.
dt
dV
C
VVcc
Rout
RESoff
ge
TOT ⋅
−
=*
Sizing the turn-on gate resistor
• Switching-time
For the matters of the calculation included here-
after, the switching time tsw is defined as the time
spent to reach the end of the plateau voltage (a
total Qgc+Qge has been provided to the IGBT gate).
To obtain the desired switching time the gate
resistance can be sized starting from Qge and
Qgc, Vcc, Vge* (see figure 21):
and
Figure 21: RGon sizing
sw
gegc
avg t
QQ
I+
=
Vcc/Vb
RDRp
RGon
CRES
COM/Vs
Iavg
where GonDRpTOT RRR +=
RGon = gate on-resistor
RDR
p
= driver equivalent on-resistance
avg
ge
TOT I
VVcc
R*
−
=
25
IR2214/IR22141(SS)
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ADVANCE DATA
OFF
HS Turning ON
ON
dV/dt
RGoff
CRESoff
RDRn
Translated into equations::
Rearranging the equation yields:
When RGoff > 4 Ohm, RDRn is well defined by
Vcc/IO- (IO- from IR2214 datasheet).
As an example, table 3 reports RGoff for two popu-
lar IGBT to withstand dVout/dt = 5V/ns.
NOTICE: the above-described equations are in-
tended being an approximated way for the gate
resistances sizing. More accurate sizing may
account more precise device modelling and para-
sitic component dependent on the PCB and
power section layout and related connections.
()()
RRIRRV DRnGoffDRnGoffth +=⋅+≥
dt
dV
Cout
RESoff
⋅
DRn
RESoff
th
Goff R
dt
dV
C
V
R−
⋅
≤
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor RGoff
is when the collector of the IGBT in off state is
forced to commutate by external events (i.e. the
turn-on of the companion IGBT).
In this case the dV/dt of the output node induces
a parasitic current through CRESoff flowing in RGoff
and RDRn (see figure 22).
If the voltage drop at the gate exceeds the thresh-
old voltage of the IGBT, the device may self turn
on causing large oscillation and relevant cross
conduction.
Figure 22: RGoff sizing: current path when Low
Side is off and High Side turns on
IGBT Qge Qgc Vge* tsw Iavg Rtot
RGon → std commercial value Tsw
IRGP30B120K(D) 19nC 82nC 9V 400ns 0.25A 24Ω RTOT - RDRp = 12.7 Ω → 10 Ω →420ns
IRG4PH30K(D) 10nC 20nC 9V 200ns 0.15A
40Ω RTOT - RDRp = 32.5 Ω → 33 Ω →202ns
IGBT Qge Qgc Vge* CRESoff Rtot
RGon → std commercial value dVout/dt
IRGP30B120K(D) 19nC 82nC 9V 85pF 14Ω RTOT - RDRp = 6.5 Ω → 8.2 Ω →4.5V/ns
IRG4PH30K(D) 10nc 20nC 9V 14pF
85Ω RTOT - RDRp = 78 Ω → 82 Ω →5V/ns
IGBT Vth(min) CRESoff RGoff
IRGP30B120K(D) 4 85pF RGoff ? 4 Ω
IRG4PH30K(D) 3 14pF RGoff ? 35 Ω
Table 1: tsw driven RGon sizing
Table 2: dVOUT/dt driven RGon sizing
Table 3: RGoff sizing
≥
≥
26
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ADVANCE DATA
PCB LA YOUT TIPS
Distance from H to L voltage:
The IR2214 pin out maximizes the distance be-
tween floating (from DC- to DC+) and low voltage
pins. It’s strongly recommended to place com-
ponents tied to floating voltage in the high volt-
age side of device (VB, VS side) while the other
components in the opposite side.
Ground plane:
Ground plane must not be placed under or
nearby the high voltage floating side to minimize
noise coupling.
Gate drive loops:
Current loops behave like an antenna able to re-
ceive and transmit EM noise. In order to reduce
EM coupling and improve the power switch turn
on/off performances, gate drive loops must be
reduced as much as possible. Figure 23 shows
the high and low side gate loops.
Moreover, current can be injected inside the gate
drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the
gate loop contributes to develop a voltage across
the gate-emitter increasing the possibility of self
turn-on effect. For this reason is strongly recom-
mended to place the three gate resistances close
together and to minimize the loop
area (see figure 23).
gate
resistance
VS/COM
VB/ VCC
H/LOP
H/LON
SSDH/L
VGE
Gate Drive
Loop
CGC
IGC
Figure 23: gate drive loop
Supply capacitors:
IR2214 output stages are able to quickly turn on
IGBT with up to 2 A of output current. The sup-
ply capacitors must be placed as close as pos-
sible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating
supply) in order to minimize parasitic inductance/
resistance.
Routing and placement example:
Figure 24 shows one of the possible layout solu-
tions using a 3 layer PCB. This example takes
into account all the previous considerations.
Placement and routing for supply capacitors and
gate resistances in the high and low voltage side
minimize respectively supply path and gate drive
loop. The bootstrap diode is placed under the
device to have the cathode as close as possible
to bootstrap capacitor and the anode far from
high voltage and close to VCC.
27
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ADVANCE DATA
Referred to figure 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
R2
R3
R4
R5
R6
R7
C2
D3
D2
IR2214
VGH
VGL
DC+
Phase
a) b)
D1
R1
C1
VEH
VEL
VCC
c)
Figure 24: layout example: top (a), bottom (b)
and ground plane (c) layer
28
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ADVANCE DATA
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/17/2003
Case outline
01 6076 01
01 5537 01 MO-150AH
24-Lead SSOP
